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radv: add missing return values check for some winsys calls
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
48 #include "radv_cs.h"
49 #include "util/disk_cache.h"
50 #include "vk_util.h"
51 #include <xf86drm.h>
52 #include <amdgpu.h>
53 #include "drm-uapi/amdgpu_drm.h"
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/driconf.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static void
133 radv_physical_device_init_mem_types(struct radv_physical_device *device)
134 {
135 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
136 uint64_t vram_size = radv_get_vram_size(device);
137 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
138 device->memory_properties.memoryHeapCount = 0;
139 if (vram_size > 0) {
140 vram_index = device->memory_properties.memoryHeapCount++;
141 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
142 .size = vram_size,
143 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
144 };
145 }
146
147 if (device->rad_info.gart_size > 0) {
148 gart_index = device->memory_properties.memoryHeapCount++;
149 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
150 .size = device->rad_info.gart_size,
151 .flags = 0,
152 };
153 }
154
155 if (visible_vram_size) {
156 visible_vram_index = device->memory_properties.memoryHeapCount++;
157 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
158 .size = visible_vram_size,
159 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
160 };
161 }
162
163 unsigned type_count = 0;
164
165 if (vram_index >= 0 || visible_vram_index >= 0) {
166 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
167 device->memory_flags[type_count] = RADEON_FLAG_NO_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index >= 0 ? vram_index : visible_vram_index,
171 };
172 }
173
174 if (gart_index >= 0) {
175 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
176 device->memory_flags[type_count] = RADEON_FLAG_GTT_WC | RADEON_FLAG_CPU_ACCESS;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->memory_domains[type_count] = RADEON_DOMAIN_VRAM;
185 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193
194 if (gart_index >= 0) {
195 device->memory_domains[type_count] = RADEON_DOMAIN_GTT;
196 device->memory_flags[type_count] = RADEON_FLAG_CPU_ACCESS;
197 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
198 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
200 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205
206 if (device->rad_info.has_l2_uncached) {
207 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
208 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
209
210 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
212 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
213
214 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
215 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
216 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
217
218 device->memory_domains[type_count] = device->memory_domains[i];
219 device->memory_flags[type_count] = device->memory_flags[i] | RADEON_FLAG_VA_UNCACHED;
220 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
221 .propertyFlags = property_flags,
222 .heapIndex = mem_type.heapIndex,
223 };
224 }
225 }
226 device->memory_properties.memoryTypeCount = type_count;
227 }
228 }
229
230 static const char *
231 radv_get_compiler_string(struct radv_physical_device *pdevice)
232 {
233 if (!pdevice->use_llvm) {
234 /* Some games like SotTR apply shader workarounds if the LLVM
235 * version is too old or if the LLVM version string is
236 * missing. This gives 2-5% performance with SotTR and ACO.
237 */
238 if (driQueryOptionb(&pdevice->instance->dri_options,
239 "radv_report_llvm9_version_string")) {
240 return "ACO/LLVM 9.0.1";
241 }
242
243 return "ACO";
244 }
245
246 return "LLVM " MESA_LLVM_VERSION_STRING;
247 }
248
249 static VkResult
250 radv_physical_device_try_create(struct radv_instance *instance,
251 drmDevicePtr drm_device,
252 struct radv_physical_device **device_out)
253 {
254 VkResult result;
255 int fd = -1;
256 int master_fd = -1;
257
258 if (drm_device) {
259 const char *path = drm_device->nodes[DRM_NODE_RENDER];
260 drmVersionPtr version;
261
262 fd = open(path, O_RDWR | O_CLOEXEC);
263 if (fd < 0) {
264 if (instance->debug_flags & RADV_DEBUG_STARTUP)
265 radv_logi("Could not open device '%s'", path);
266
267 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
268 }
269
270 version = drmGetVersion(fd);
271 if (!version) {
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Could not get the kernel driver version for device '%s'", path);
276
277 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
278 "failed to get version %s: %m", path);
279 }
280
281 if (strcmp(version->name, "amdgpu")) {
282 drmFreeVersion(version);
283 close(fd);
284
285 if (instance->debug_flags & RADV_DEBUG_STARTUP)
286 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
287
288 return VK_ERROR_INCOMPATIBLE_DRIVER;
289 }
290 drmFreeVersion(version);
291
292 if (instance->debug_flags & RADV_DEBUG_STARTUP)
293 radv_logi("Found compatible device '%s'.", path);
294 }
295
296 struct radv_physical_device *device =
297 vk_zalloc2(&instance->alloc, NULL, sizeof(*device), 8,
298 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
299 if (!device) {
300 result = vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
301 goto fail_fd;
302 }
303
304 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
305 device->instance = instance;
306
307 if (drm_device) {
308 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
309 instance->perftest_flags);
310 } else {
311 device->ws = radv_null_winsys_create();
312 }
313
314 if (!device->ws) {
315 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
316 "failed to initialize winsys");
317 goto fail_alloc;
318 }
319
320 if (drm_device && instance->enabled_extensions.KHR_display) {
321 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
322 if (master_fd >= 0) {
323 uint32_t accel_working = 0;
324 struct drm_amdgpu_info request = {
325 .return_pointer = (uintptr_t)&accel_working,
326 .return_size = sizeof(accel_working),
327 .query = AMDGPU_INFO_ACCEL_WORKING
328 };
329
330 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
331 close(master_fd);
332 master_fd = -1;
333 }
334 }
335 }
336
337 device->master_fd = master_fd;
338 device->local_fd = fd;
339 device->ws->query_info(device->ws, &device->rad_info);
340
341 device->use_llvm = instance->debug_flags & RADV_DEBUG_LLVM;
342
343 snprintf(device->name, sizeof(device->name),
344 "AMD RADV %s (%s)",
345 device->rad_info.name, radv_get_compiler_string(device));
346
347 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
348 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
349 "cannot generate UUID");
350 goto fail_wsi;
351 }
352
353 /* These flags affect shader compilation. */
354 uint64_t shader_env_flags = (device->use_llvm ? 0 : 0x2);
355
356 /* The gpu id is already embedded in the uuid so we just pass "radv"
357 * when creating the cache.
358 */
359 char buf[VK_UUID_SIZE * 2 + 1];
360 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
361 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
362
363 if (device->rad_info.chip_class < GFX8 || !device->use_llvm)
364 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
365
366 radv_get_driver_uuid(&device->driver_uuid);
367 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
368
369 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
370 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
371
372 device->dcc_msaa_allowed =
373 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
374
375 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
376 device->rad_info.family != CHIP_NAVI14 &&
377 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
378
379 /* TODO: Implement NGG GS with ACO. */
380 device->use_ngg_gs = device->use_ngg && device->use_llvm;
381 device->use_ngg_streamout = false;
382
383 /* Determine the number of threads per wave for all stages. */
384 device->cs_wave_size = 64;
385 device->ps_wave_size = 64;
386 device->ge_wave_size = 64;
387
388 if (device->rad_info.chip_class >= GFX10) {
389 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
390 device->cs_wave_size = 32;
391
392 /* For pixel shaders, wave64 is recommanded. */
393 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
394 device->ps_wave_size = 32;
395
396 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
397 device->ge_wave_size = 32;
398 }
399
400 radv_physical_device_init_mem_types(device);
401
402 radv_physical_device_get_supported_extensions(device,
403 &device->supported_extensions);
404
405 if (drm_device)
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 vk_error(instance, result);
418 goto fail_disk_cache;
419 }
420
421 *device_out = device;
422
423 return VK_SUCCESS;
424
425 fail_disk_cache:
426 disk_cache_destroy(device->disk_cache);
427 fail_wsi:
428 device->ws->destroy(device->ws);
429 fail_alloc:
430 vk_free(&instance->alloc, device);
431 fail_fd:
432 if (fd != -1)
433 close(fd);
434 if (master_fd != -1)
435 close(master_fd);
436 return result;
437 }
438
439 static void
440 radv_physical_device_destroy(struct radv_physical_device *device)
441 {
442 radv_finish_wsi(device);
443 device->ws->destroy(device->ws);
444 disk_cache_destroy(device->disk_cache);
445 close(device->local_fd);
446 if (device->master_fd != -1)
447 close(device->master_fd);
448 vk_free(&device->instance->alloc, device);
449 }
450
451 static void *
452 default_alloc_func(void *pUserData, size_t size, size_t align,
453 VkSystemAllocationScope allocationScope)
454 {
455 return malloc(size);
456 }
457
458 static void *
459 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
460 size_t align, VkSystemAllocationScope allocationScope)
461 {
462 return realloc(pOriginal, size);
463 }
464
465 static void
466 default_free_func(void *pUserData, void *pMemory)
467 {
468 free(pMemory);
469 }
470
471 static const VkAllocationCallbacks default_alloc = {
472 .pUserData = NULL,
473 .pfnAllocation = default_alloc_func,
474 .pfnReallocation = default_realloc_func,
475 .pfnFree = default_free_func,
476 };
477
478 static const struct debug_control radv_debug_options[] = {
479 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
480 {"nodcc", RADV_DEBUG_NO_DCC},
481 {"shaders", RADV_DEBUG_DUMP_SHADERS},
482 {"nocache", RADV_DEBUG_NO_CACHE},
483 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
484 {"nohiz", RADV_DEBUG_NO_HIZ},
485 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
486 {"allbos", RADV_DEBUG_ALL_BOS},
487 {"noibs", RADV_DEBUG_NO_IBS},
488 {"spirv", RADV_DEBUG_DUMP_SPIRV},
489 {"vmfaults", RADV_DEBUG_VM_FAULTS},
490 {"zerovram", RADV_DEBUG_ZERO_VRAM},
491 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
492 {"preoptir", RADV_DEBUG_PREOPTIR},
493 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
494 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
495 {"info", RADV_DEBUG_INFO},
496 {"errors", RADV_DEBUG_ERRORS},
497 {"startup", RADV_DEBUG_STARTUP},
498 {"checkir", RADV_DEBUG_CHECKIR},
499 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
500 {"nobinning", RADV_DEBUG_NOBINNING},
501 {"nongg", RADV_DEBUG_NO_NGG},
502 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
503 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
504 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
505 {"llvm", RADV_DEBUG_LLVM},
506 {NULL, 0}
507 };
508
509 const char *
510 radv_get_debug_option_name(int id)
511 {
512 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
513 return radv_debug_options[id].string;
514 }
515
516 static const struct debug_control radv_perftest_options[] = {
517 {"localbos", RADV_PERFTEST_LOCAL_BOS},
518 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
519 {"bolist", RADV_PERFTEST_BO_LIST},
520 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
521 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
522 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
523 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
524 {"dfsm", RADV_PERFTEST_DFSM},
525 {NULL, 0}
526 };
527
528 const char *
529 radv_get_perftest_option_name(int id)
530 {
531 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
532 return radv_perftest_options[id].string;
533 }
534
535 static void
536 radv_handle_per_app_options(struct radv_instance *instance,
537 const VkApplicationInfo *info)
538 {
539 const char *name = info ? info->pApplicationName : NULL;
540 const char *engine_name = info ? info->pEngineName : NULL;
541
542 if (name) {
543 if (!strcmp(name, "DOOM_VFR")) {
544 /* Work around a Doom VFR game bug */
545 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
546 } else if (!strcmp(name, "Fledge")) {
547 /*
548 * Zero VRAM for "The Surge 2"
549 *
550 * This avoid a hang when when rendering any level. Likely
551 * uninitialized data in an indirect draw.
552 */
553 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
554 } else if (!strcmp(name, "No Man's Sky")) {
555 /* Work around a NMS game bug */
556 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
557 } else if (!strcmp(name, "DOOMEternal")) {
558 /* Zero VRAM for Doom Eternal to fix rendering issues. */
559 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
560 } else if (!strcmp(name, "Red Dead Redemption 2")) {
561 /* Work around a RDR2 game bug */
562 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
563 }
564 }
565
566 if (engine_name) {
567 if (!strcmp(engine_name, "vkd3d")) {
568 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
569 * rendering issues.
570 */
571 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
572 } else if (!strcmp(engine_name, "Quantic Dream Engine")) {
573 /* Fix various artifacts in Detroit: Become Human */
574 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM |
575 RADV_DEBUG_DISCARD_TO_DEMOTE;
576 }
577 }
578
579 instance->enable_mrt_output_nan_fixup =
580 driQueryOptionb(&instance->dri_options,
581 "radv_enable_mrt_output_nan_fixup");
582
583 if (driQueryOptionb(&instance->dri_options, "radv_no_dynamic_bounds"))
584 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
585 }
586
587 static const char radv_dri_options_xml[] =
588 DRI_CONF_BEGIN
589 DRI_CONF_SECTION_PERFORMANCE
590 DRI_CONF_ADAPTIVE_SYNC("true")
591 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
592 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
593 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
594 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
595 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
596 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
597 DRI_CONF_SECTION_END
598
599 DRI_CONF_SECTION_DEBUG
600 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
601 DRI_CONF_SECTION_END
602 DRI_CONF_END;
603
604 static void radv_init_dri_options(struct radv_instance *instance)
605 {
606 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
607 driParseConfigFiles(&instance->dri_options,
608 &instance->available_dri_options,
609 0, "radv", NULL,
610 instance->engineName,
611 instance->engineVersion);
612 }
613
614 VkResult radv_CreateInstance(
615 const VkInstanceCreateInfo* pCreateInfo,
616 const VkAllocationCallbacks* pAllocator,
617 VkInstance* pInstance)
618 {
619 struct radv_instance *instance;
620 VkResult result;
621
622 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
623 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
624 if (!instance)
625 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
626
627 vk_object_base_init(NULL, &instance->base, VK_OBJECT_TYPE_INSTANCE);
628
629 if (pAllocator)
630 instance->alloc = *pAllocator;
631 else
632 instance->alloc = default_alloc;
633
634 if (pCreateInfo->pApplicationInfo) {
635 const VkApplicationInfo *app = pCreateInfo->pApplicationInfo;
636
637 instance->engineName =
638 vk_strdup(&instance->alloc, app->pEngineName,
639 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
640 instance->engineVersion = app->engineVersion;
641 instance->apiVersion = app->apiVersion;
642 }
643
644 if (instance->apiVersion == 0)
645 instance->apiVersion = VK_API_VERSION_1_0;
646
647 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
648 radv_debug_options);
649
650 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
651 radv_perftest_options);
652
653 if (instance->debug_flags & RADV_DEBUG_STARTUP)
654 radv_logi("Created an instance");
655
656 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
657 int idx;
658 for (idx = 0; idx < RADV_INSTANCE_EXTENSION_COUNT; idx++) {
659 if (!strcmp(pCreateInfo->ppEnabledExtensionNames[i],
660 radv_instance_extensions[idx].extensionName))
661 break;
662 }
663
664 if (idx >= RADV_INSTANCE_EXTENSION_COUNT ||
665 !radv_instance_extensions_supported.extensions[idx]) {
666 vk_object_base_finish(&instance->base);
667 vk_free2(&default_alloc, pAllocator, instance);
668 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
669 }
670
671 instance->enabled_extensions.extensions[idx] = true;
672 }
673
674 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
675
676 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
677 /* Vulkan requires that entrypoints for extensions which have
678 * not been enabled must not be advertised.
679 */
680 if (!unchecked &&
681 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
682 &instance->enabled_extensions)) {
683 instance->dispatch.entrypoints[i] = NULL;
684 } else {
685 instance->dispatch.entrypoints[i] =
686 radv_instance_dispatch_table.entrypoints[i];
687 }
688 }
689
690 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
691 /* Vulkan requires that entrypoints for extensions which have
692 * not been enabled must not be advertised.
693 */
694 if (!unchecked &&
695 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
696 &instance->enabled_extensions)) {
697 instance->physical_device_dispatch.entrypoints[i] = NULL;
698 } else {
699 instance->physical_device_dispatch.entrypoints[i] =
700 radv_physical_device_dispatch_table.entrypoints[i];
701 }
702 }
703
704 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
705 /* Vulkan requires that entrypoints for extensions which have
706 * not been enabled must not be advertised.
707 */
708 if (!unchecked &&
709 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
710 &instance->enabled_extensions, NULL)) {
711 instance->device_dispatch.entrypoints[i] = NULL;
712 } else {
713 instance->device_dispatch.entrypoints[i] =
714 radv_device_dispatch_table.entrypoints[i];
715 }
716 }
717
718 instance->physical_devices_enumerated = false;
719 list_inithead(&instance->physical_devices);
720
721 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
722 if (result != VK_SUCCESS) {
723 vk_object_base_finish(&instance->base);
724 vk_free2(&default_alloc, pAllocator, instance);
725 return vk_error(instance, result);
726 }
727
728 glsl_type_singleton_init_or_ref();
729
730 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
731
732 radv_init_dri_options(instance);
733 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
734
735 *pInstance = radv_instance_to_handle(instance);
736
737 return VK_SUCCESS;
738 }
739
740 void radv_DestroyInstance(
741 VkInstance _instance,
742 const VkAllocationCallbacks* pAllocator)
743 {
744 RADV_FROM_HANDLE(radv_instance, instance, _instance);
745
746 if (!instance)
747 return;
748
749 list_for_each_entry_safe(struct radv_physical_device, pdevice,
750 &instance->physical_devices, link) {
751 radv_physical_device_destroy(pdevice);
752 }
753
754 vk_free(&instance->alloc, instance->engineName);
755
756 VG(VALGRIND_DESTROY_MEMPOOL(instance));
757
758 glsl_type_singleton_decref();
759
760 driDestroyOptionCache(&instance->dri_options);
761 driDestroyOptionInfo(&instance->available_dri_options);
762
763 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
764
765 vk_object_base_finish(&instance->base);
766 vk_free(&instance->alloc, instance);
767 }
768
769 static VkResult
770 radv_enumerate_physical_devices(struct radv_instance *instance)
771 {
772 if (instance->physical_devices_enumerated)
773 return VK_SUCCESS;
774
775 instance->physical_devices_enumerated = true;
776
777 /* TODO: Check for more devices ? */
778 drmDevicePtr devices[8];
779 VkResult result = VK_SUCCESS;
780 int max_devices;
781
782 if (getenv("RADV_FORCE_FAMILY")) {
783 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
784 * device that allows to test the compiler without having an
785 * AMDGPU instance.
786 */
787 struct radv_physical_device *pdevice;
788
789 result = radv_physical_device_try_create(instance, NULL, &pdevice);
790 if (result != VK_SUCCESS)
791 return result;
792
793 list_addtail(&pdevice->link, &instance->physical_devices);
794 return VK_SUCCESS;
795 }
796
797 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
798
799 if (instance->debug_flags & RADV_DEBUG_STARTUP)
800 radv_logi("Found %d drm nodes", max_devices);
801
802 if (max_devices < 1)
803 return vk_error(instance, VK_SUCCESS);
804
805 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
806 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
807 devices[i]->bustype == DRM_BUS_PCI &&
808 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
809
810 struct radv_physical_device *pdevice;
811 result = radv_physical_device_try_create(instance, devices[i],
812 &pdevice);
813 /* Incompatible DRM device, skip. */
814 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
815 result = VK_SUCCESS;
816 continue;
817 }
818
819 /* Error creating the physical device, report the error. */
820 if (result != VK_SUCCESS)
821 break;
822
823 list_addtail(&pdevice->link, &instance->physical_devices);
824 }
825 }
826 drmFreeDevices(devices, max_devices);
827
828 /* If we successfully enumerated any devices, call it success */
829 return result;
830 }
831
832 VkResult radv_EnumeratePhysicalDevices(
833 VkInstance _instance,
834 uint32_t* pPhysicalDeviceCount,
835 VkPhysicalDevice* pPhysicalDevices)
836 {
837 RADV_FROM_HANDLE(radv_instance, instance, _instance);
838 VK_OUTARRAY_MAKE(out, pPhysicalDevices, pPhysicalDeviceCount);
839
840 VkResult result = radv_enumerate_physical_devices(instance);
841 if (result != VK_SUCCESS)
842 return result;
843
844 list_for_each_entry(struct radv_physical_device, pdevice,
845 &instance->physical_devices, link) {
846 vk_outarray_append(&out, i) {
847 *i = radv_physical_device_to_handle(pdevice);
848 }
849 }
850
851 return vk_outarray_status(&out);
852 }
853
854 VkResult radv_EnumeratePhysicalDeviceGroups(
855 VkInstance _instance,
856 uint32_t* pPhysicalDeviceGroupCount,
857 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
858 {
859 RADV_FROM_HANDLE(radv_instance, instance, _instance);
860 VK_OUTARRAY_MAKE(out, pPhysicalDeviceGroupProperties,
861 pPhysicalDeviceGroupCount);
862
863 VkResult result = radv_enumerate_physical_devices(instance);
864 if (result != VK_SUCCESS)
865 return result;
866
867 list_for_each_entry(struct radv_physical_device, pdevice,
868 &instance->physical_devices, link) {
869 vk_outarray_append(&out, p) {
870 p->physicalDeviceCount = 1;
871 memset(p->physicalDevices, 0, sizeof(p->physicalDevices));
872 p->physicalDevices[0] = radv_physical_device_to_handle(pdevice);
873 p->subsetAllocation = false;
874 }
875 }
876
877 return vk_outarray_status(&out);
878 }
879
880 void radv_GetPhysicalDeviceFeatures(
881 VkPhysicalDevice physicalDevice,
882 VkPhysicalDeviceFeatures* pFeatures)
883 {
884 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
885 memset(pFeatures, 0, sizeof(*pFeatures));
886
887 *pFeatures = (VkPhysicalDeviceFeatures) {
888 .robustBufferAccess = true,
889 .fullDrawIndexUint32 = true,
890 .imageCubeArray = true,
891 .independentBlend = true,
892 .geometryShader = true,
893 .tessellationShader = true,
894 .sampleRateShading = true,
895 .dualSrcBlend = true,
896 .logicOp = true,
897 .multiDrawIndirect = true,
898 .drawIndirectFirstInstance = true,
899 .depthClamp = true,
900 .depthBiasClamp = true,
901 .fillModeNonSolid = true,
902 .depthBounds = true,
903 .wideLines = true,
904 .largePoints = true,
905 .alphaToOne = true,
906 .multiViewport = true,
907 .samplerAnisotropy = true,
908 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
909 .textureCompressionASTC_LDR = false,
910 .textureCompressionBC = true,
911 .occlusionQueryPrecise = true,
912 .pipelineStatisticsQuery = true,
913 .vertexPipelineStoresAndAtomics = true,
914 .fragmentStoresAndAtomics = true,
915 .shaderTessellationAndGeometryPointSize = true,
916 .shaderImageGatherExtended = true,
917 .shaderStorageImageExtendedFormats = true,
918 .shaderStorageImageMultisample = true,
919 .shaderUniformBufferArrayDynamicIndexing = true,
920 .shaderSampledImageArrayDynamicIndexing = true,
921 .shaderStorageBufferArrayDynamicIndexing = true,
922 .shaderStorageImageArrayDynamicIndexing = true,
923 .shaderStorageImageReadWithoutFormat = true,
924 .shaderStorageImageWriteWithoutFormat = true,
925 .shaderClipDistance = true,
926 .shaderCullDistance = true,
927 .shaderFloat64 = true,
928 .shaderInt64 = true,
929 .shaderInt16 = true,
930 .sparseBinding = true,
931 .variableMultisampleRate = true,
932 .shaderResourceMinLod = true,
933 .inheritedQueries = true,
934 };
935 }
936
937 static void
938 radv_get_physical_device_features_1_1(struct radv_physical_device *pdevice,
939 VkPhysicalDeviceVulkan11Features *f)
940 {
941 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES);
942
943 f->storageBuffer16BitAccess = true;
944 f->uniformAndStorageBuffer16BitAccess = true;
945 f->storagePushConstant16 = true;
946 f->storageInputOutput16 = pdevice->rad_info.has_packed_math_16bit && (LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm);
947 f->multiview = true;
948 f->multiviewGeometryShader = true;
949 f->multiviewTessellationShader = true;
950 f->variablePointersStorageBuffer = true;
951 f->variablePointers = true;
952 f->protectedMemory = false;
953 f->samplerYcbcrConversion = true;
954 f->shaderDrawParameters = true;
955 }
956
957 static void
958 radv_get_physical_device_features_1_2(struct radv_physical_device *pdevice,
959 VkPhysicalDeviceVulkan12Features *f)
960 {
961 assert(f->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES);
962
963 f->samplerMirrorClampToEdge = true;
964 f->drawIndirectCount = true;
965 f->storageBuffer8BitAccess = true;
966 f->uniformAndStorageBuffer8BitAccess = true;
967 f->storagePushConstant8 = true;
968 f->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
969 f->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
970 f->shaderFloat16 = pdevice->rad_info.has_packed_math_16bit;
971 f->shaderInt8 = true;
972
973 f->descriptorIndexing = true;
974 f->shaderInputAttachmentArrayDynamicIndexing = true;
975 f->shaderUniformTexelBufferArrayDynamicIndexing = true;
976 f->shaderStorageTexelBufferArrayDynamicIndexing = true;
977 f->shaderUniformBufferArrayNonUniformIndexing = true;
978 f->shaderSampledImageArrayNonUniformIndexing = true;
979 f->shaderStorageBufferArrayNonUniformIndexing = true;
980 f->shaderStorageImageArrayNonUniformIndexing = true;
981 f->shaderInputAttachmentArrayNonUniformIndexing = true;
982 f->shaderUniformTexelBufferArrayNonUniformIndexing = true;
983 f->shaderStorageTexelBufferArrayNonUniformIndexing = true;
984 f->descriptorBindingUniformBufferUpdateAfterBind = true;
985 f->descriptorBindingSampledImageUpdateAfterBind = true;
986 f->descriptorBindingStorageImageUpdateAfterBind = true;
987 f->descriptorBindingStorageBufferUpdateAfterBind = true;
988 f->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
989 f->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
990 f->descriptorBindingUpdateUnusedWhilePending = true;
991 f->descriptorBindingPartiallyBound = true;
992 f->descriptorBindingVariableDescriptorCount = true;
993 f->runtimeDescriptorArray = true;
994
995 f->samplerFilterMinmax = true;
996 f->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
997 f->imagelessFramebuffer = true;
998 f->uniformBufferStandardLayout = true;
999 f->shaderSubgroupExtendedTypes = true;
1000 f->separateDepthStencilLayouts = true;
1001 f->hostQueryReset = true;
1002 f->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1003 f->bufferDeviceAddress = true;
1004 f->bufferDeviceAddressCaptureReplay = false;
1005 f->bufferDeviceAddressMultiDevice = false;
1006 f->vulkanMemoryModel = false;
1007 f->vulkanMemoryModelDeviceScope = false;
1008 f->vulkanMemoryModelAvailabilityVisibilityChains = false;
1009 f->shaderOutputViewportIndex = true;
1010 f->shaderOutputLayer = true;
1011 f->subgroupBroadcastDynamicId = true;
1012 }
1013
1014 void radv_GetPhysicalDeviceFeatures2(
1015 VkPhysicalDevice physicalDevice,
1016 VkPhysicalDeviceFeatures2 *pFeatures)
1017 {
1018 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1019 radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1020
1021 VkPhysicalDeviceVulkan11Features core_1_1 = {
1022 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES,
1023 };
1024 radv_get_physical_device_features_1_1(pdevice, &core_1_1);
1025
1026 VkPhysicalDeviceVulkan12Features core_1_2 = {
1027 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES,
1028 };
1029 radv_get_physical_device_features_1_2(pdevice, &core_1_2);
1030
1031 #define CORE_FEATURE(major, minor, feature) \
1032 features->feature = core_##major##_##minor.feature
1033
1034 vk_foreach_struct(ext, pFeatures->pNext) {
1035 switch (ext->sType) {
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
1037 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
1038 CORE_FEATURE(1, 1, variablePointersStorageBuffer);
1039 CORE_FEATURE(1, 1, variablePointers);
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
1043 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
1044 CORE_FEATURE(1, 1, multiview);
1045 CORE_FEATURE(1, 1, multiviewGeometryShader);
1046 CORE_FEATURE(1, 1, multiviewTessellationShader);
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
1050 VkPhysicalDeviceShaderDrawParametersFeatures *features =
1051 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
1052 CORE_FEATURE(1, 1, shaderDrawParameters);
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
1056 VkPhysicalDeviceProtectedMemoryFeatures *features =
1057 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
1058 CORE_FEATURE(1, 1, protectedMemory);
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1062 VkPhysicalDevice16BitStorageFeatures *features =
1063 (VkPhysicalDevice16BitStorageFeatures*)ext;
1064 CORE_FEATURE(1, 1, storageBuffer16BitAccess);
1065 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess);
1066 CORE_FEATURE(1, 1, storagePushConstant16);
1067 CORE_FEATURE(1, 1, storageInputOutput16);
1068 break;
1069 }
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1071 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1072 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1073 CORE_FEATURE(1, 1, samplerYcbcrConversion);
1074 break;
1075 }
1076 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1077 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1078 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1079 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing);
1080 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing);
1081 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing);
1082 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing);
1083 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing);
1084 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing);
1085 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing);
1086 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing);
1087 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing);
1088 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing);
1089 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind);
1090 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind);
1091 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind);
1092 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind);
1093 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind);
1094 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind);
1095 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending);
1096 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound);
1097 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount);
1098 CORE_FEATURE(1, 2, runtimeDescriptorArray);
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1102 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1103 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1104 features->conditionalRendering = true;
1105 features->inheritedConditionalRendering = false;
1106 break;
1107 }
1108 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1109 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1110 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1111 features->vertexAttributeInstanceRateDivisor = true;
1112 features->vertexAttributeInstanceRateZeroDivisor = true;
1113 break;
1114 }
1115 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1116 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1117 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1118 features->transformFeedback = true;
1119 features->geometryStreams = !pdevice->use_ngg_streamout;
1120 break;
1121 }
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1123 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1124 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1125 CORE_FEATURE(1, 2, scalarBlockLayout);
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1129 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1130 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1131 features->memoryPriority = true;
1132 break;
1133 }
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1135 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1136 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1137 features->bufferDeviceAddress = true;
1138 features->bufferDeviceAddressCaptureReplay = false;
1139 features->bufferDeviceAddressMultiDevice = false;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1143 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1144 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1145 CORE_FEATURE(1, 2, bufferDeviceAddress);
1146 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay);
1147 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice);
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1151 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1152 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1153 features->depthClipEnable = true;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1157 VkPhysicalDeviceHostQueryResetFeatures *features =
1158 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1159 CORE_FEATURE(1, 2, hostQueryReset);
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1163 VkPhysicalDevice8BitStorageFeatures *features =
1164 (VkPhysicalDevice8BitStorageFeatures *)ext;
1165 CORE_FEATURE(1, 2, storageBuffer8BitAccess);
1166 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess);
1167 CORE_FEATURE(1, 2, storagePushConstant8);
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1171 VkPhysicalDeviceShaderFloat16Int8Features *features =
1172 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1173 CORE_FEATURE(1, 2, shaderFloat16);
1174 CORE_FEATURE(1, 2, shaderInt8);
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1178 VkPhysicalDeviceShaderAtomicInt64Features *features =
1179 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1180 CORE_FEATURE(1, 2, shaderBufferInt64Atomics);
1181 CORE_FEATURE(1, 2, shaderSharedInt64Atomics);
1182 break;
1183 }
1184 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1185 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1186 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1187 features->shaderDemoteToHelperInvocation = LLVM_VERSION_MAJOR >= 9 || !pdevice->use_llvm;
1188 break;
1189 }
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1191 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1192 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1193
1194 features->inlineUniformBlock = true;
1195 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1199 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1200 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1201 features->computeDerivativeGroupQuads = false;
1202 features->computeDerivativeGroupLinear = true;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1206 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1207 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1208 features->ycbcrImageArrays = true;
1209 break;
1210 }
1211 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1212 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1213 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1214 CORE_FEATURE(1, 2, uniformBufferStandardLayout);
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1218 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1219 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1220 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1221 break;
1222 }
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1224 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1225 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1226 CORE_FEATURE(1, 2, imagelessFramebuffer);
1227 break;
1228 }
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1230 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1231 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1232 features->pipelineExecutableInfo = true;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1236 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1237 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1238 features->shaderSubgroupClock = true;
1239 features->shaderDeviceClock = pdevice->rad_info.chip_class >= GFX8;
1240 break;
1241 }
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1243 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1244 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1245 features->texelBufferAlignment = true;
1246 break;
1247 }
1248 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1249 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1250 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1251 CORE_FEATURE(1, 2, timelineSemaphore);
1252 break;
1253 }
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1255 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1256 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1257 features->subgroupSizeControl = true;
1258 features->computeFullSubgroups = true;
1259 break;
1260 }
1261 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1262 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1263 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1264 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1265 break;
1266 }
1267 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1268 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1269 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1270 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes);
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1274 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1275 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1276 CORE_FEATURE(1, 2, separateDepthStencilLayouts);
1277 break;
1278 }
1279 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1280 radv_get_physical_device_features_1_1(pdevice, (void *)ext);
1281 break;
1282 }
1283 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1284 radv_get_physical_device_features_1_2(pdevice, (void *)ext);
1285 break;
1286 }
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1288 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1289 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1290 features->rectangularLines = false;
1291 features->bresenhamLines = true;
1292 features->smoothLines = false;
1293 features->stippledRectangularLines = false;
1294 features->stippledBresenhamLines = true;
1295 features->stippledSmoothLines = false;
1296 break;
1297 }
1298 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
1299 VkDeviceMemoryOverallocationCreateInfoAMD *features =
1300 (VkDeviceMemoryOverallocationCreateInfoAMD *)ext;
1301 features->overallocationBehavior = true;
1302 break;
1303 }
1304 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT: {
1305 VkPhysicalDeviceRobustness2FeaturesEXT *features =
1306 (VkPhysicalDeviceRobustness2FeaturesEXT *)ext;
1307 features->robustBufferAccess2 = true;
1308 features->robustImageAccess2 = true;
1309 features->nullDescriptor = true;
1310 break;
1311 }
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
1313 VkPhysicalDeviceCustomBorderColorFeaturesEXT *features =
1314 (VkPhysicalDeviceCustomBorderColorFeaturesEXT *)ext;
1315 features->customBorderColors = true;
1316 features->customBorderColorWithoutFormat = true;
1317 break;
1318 }
1319 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT: {
1320 VkPhysicalDevicePrivateDataFeaturesEXT *features =
1321 (VkPhysicalDevicePrivateDataFeaturesEXT *)ext;
1322 features->privateData = true;
1323 break;
1324 }
1325 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT: {
1326 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *features =
1327 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT *)ext;
1328 features-> pipelineCreationCacheControl = true;
1329 break;
1330 }
1331 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT: {
1332 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *features =
1333 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT *) ext;
1334 features->extendedDynamicState = true;
1335 break;
1336 }
1337 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT: {
1338 VkPhysicalDeviceImageRobustnessFeaturesEXT *features =
1339 (VkPhysicalDeviceImageRobustnessFeaturesEXT *)ext;
1340 features->robustImageAccess = true;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT: {
1344 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *features =
1345 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT *)ext;
1346 features->shaderBufferFloat32Atomics = true;
1347 features->shaderBufferFloat32AtomicAdd = false;
1348 features->shaderBufferFloat64Atomics = true;
1349 features->shaderBufferFloat64AtomicAdd = false;
1350 features->shaderSharedFloat32Atomics = true;
1351 features->shaderSharedFloat32AtomicAdd = pdevice->rad_info.chip_class >= GFX8 &&
1352 (!pdevice->use_llvm || LLVM_VERSION_MAJOR >= 10);
1353 features->shaderSharedFloat64Atomics = true;
1354 features->shaderSharedFloat64AtomicAdd = false;
1355 features->shaderImageFloat32Atomics = true;
1356 features->shaderImageFloat32AtomicAdd = false;
1357 features->sparseImageFloat32Atomics = false;
1358 features->sparseImageFloat32AtomicAdd = false;
1359 break;
1360 }
1361 default:
1362 break;
1363 }
1364 }
1365 #undef CORE_FEATURE
1366 }
1367
1368 static size_t
1369 radv_max_descriptor_set_size()
1370 {
1371 /* make sure that the entire descriptor set is addressable with a signed
1372 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1373 * be at most 2 GiB. the combined image & samples object count as one of
1374 * both. This limit is for the pipeline layout, not for the set layout, but
1375 * there is no set limit, so we just set a pipeline limit. I don't think
1376 * any app is going to hit this soon. */
1377 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1378 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1379 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1380 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1381 32 /* sampler, largest when combined with image */ +
1382 64 /* sampled image */ +
1383 64 /* storage image */);
1384 }
1385
1386 void radv_GetPhysicalDeviceProperties(
1387 VkPhysicalDevice physicalDevice,
1388 VkPhysicalDeviceProperties* pProperties)
1389 {
1390 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1391 VkSampleCountFlags sample_counts = 0xf;
1392
1393 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1394
1395 VkPhysicalDeviceLimits limits = {
1396 .maxImageDimension1D = (1 << 14),
1397 .maxImageDimension2D = (1 << 14),
1398 .maxImageDimension3D = (1 << 11),
1399 .maxImageDimensionCube = (1 << 14),
1400 .maxImageArrayLayers = (1 << 11),
1401 .maxTexelBufferElements = UINT32_MAX,
1402 .maxUniformBufferRange = UINT32_MAX,
1403 .maxStorageBufferRange = UINT32_MAX,
1404 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1405 .maxMemoryAllocationCount = UINT32_MAX,
1406 .maxSamplerAllocationCount = 64 * 1024,
1407 .bufferImageGranularity = 64, /* A cache line */
1408 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1409 .maxBoundDescriptorSets = MAX_SETS,
1410 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1411 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1412 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1413 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1414 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1415 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1416 .maxPerStageResources = max_descriptor_set_size,
1417 .maxDescriptorSetSamplers = max_descriptor_set_size,
1418 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1419 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1420 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1421 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1422 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1423 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1424 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1425 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1426 .maxVertexInputBindings = MAX_VBS,
1427 .maxVertexInputAttributeOffset = 2047,
1428 .maxVertexInputBindingStride = 2048,
1429 .maxVertexOutputComponents = 128,
1430 .maxTessellationGenerationLevel = 64,
1431 .maxTessellationPatchSize = 32,
1432 .maxTessellationControlPerVertexInputComponents = 128,
1433 .maxTessellationControlPerVertexOutputComponents = 128,
1434 .maxTessellationControlPerPatchOutputComponents = 120,
1435 .maxTessellationControlTotalOutputComponents = 4096,
1436 .maxTessellationEvaluationInputComponents = 128,
1437 .maxTessellationEvaluationOutputComponents = 128,
1438 .maxGeometryShaderInvocations = 127,
1439 .maxGeometryInputComponents = 64,
1440 .maxGeometryOutputComponents = 128,
1441 .maxGeometryOutputVertices = 256,
1442 .maxGeometryTotalOutputComponents = 1024,
1443 .maxFragmentInputComponents = 128,
1444 .maxFragmentOutputAttachments = 8,
1445 .maxFragmentDualSrcAttachments = 1,
1446 .maxFragmentCombinedOutputResources = 8,
1447 .maxComputeSharedMemorySize = 32768,
1448 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1449 .maxComputeWorkGroupInvocations = 1024,
1450 .maxComputeWorkGroupSize = {
1451 1024,
1452 1024,
1453 1024
1454 },
1455 .subPixelPrecisionBits = 8,
1456 .subTexelPrecisionBits = 8,
1457 .mipmapPrecisionBits = 8,
1458 .maxDrawIndexedIndexValue = UINT32_MAX,
1459 .maxDrawIndirectCount = UINT32_MAX,
1460 .maxSamplerLodBias = 16,
1461 .maxSamplerAnisotropy = 16,
1462 .maxViewports = MAX_VIEWPORTS,
1463 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1464 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1465 .viewportSubPixelBits = 8,
1466 .minMemoryMapAlignment = 4096, /* A page */
1467 .minTexelBufferOffsetAlignment = 4,
1468 .minUniformBufferOffsetAlignment = 4,
1469 .minStorageBufferOffsetAlignment = 4,
1470 .minTexelOffset = -32,
1471 .maxTexelOffset = 31,
1472 .minTexelGatherOffset = -32,
1473 .maxTexelGatherOffset = 31,
1474 .minInterpolationOffset = -2,
1475 .maxInterpolationOffset = 2,
1476 .subPixelInterpolationOffsetBits = 8,
1477 .maxFramebufferWidth = (1 << 14),
1478 .maxFramebufferHeight = (1 << 14),
1479 .maxFramebufferLayers = (1 << 10),
1480 .framebufferColorSampleCounts = sample_counts,
1481 .framebufferDepthSampleCounts = sample_counts,
1482 .framebufferStencilSampleCounts = sample_counts,
1483 .framebufferNoAttachmentsSampleCounts = sample_counts,
1484 .maxColorAttachments = MAX_RTS,
1485 .sampledImageColorSampleCounts = sample_counts,
1486 .sampledImageIntegerSampleCounts = sample_counts,
1487 .sampledImageDepthSampleCounts = sample_counts,
1488 .sampledImageStencilSampleCounts = sample_counts,
1489 .storageImageSampleCounts = sample_counts,
1490 .maxSampleMaskWords = 1,
1491 .timestampComputeAndGraphics = true,
1492 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1493 .maxClipDistances = 8,
1494 .maxCullDistances = 8,
1495 .maxCombinedClipAndCullDistances = 8,
1496 .discreteQueuePriorities = 2,
1497 .pointSizeRange = { 0.0, 8191.875 },
1498 .lineWidthRange = { 0.0, 8191.875 },
1499 .pointSizeGranularity = (1.0 / 8.0),
1500 .lineWidthGranularity = (1.0 / 8.0),
1501 .strictLines = false, /* FINISHME */
1502 .standardSampleLocations = true,
1503 .optimalBufferCopyOffsetAlignment = 128,
1504 .optimalBufferCopyRowPitchAlignment = 128,
1505 .nonCoherentAtomSize = 64,
1506 };
1507
1508 *pProperties = (VkPhysicalDeviceProperties) {
1509 .apiVersion = radv_physical_device_api_version(pdevice),
1510 .driverVersion = vk_get_driver_version(),
1511 .vendorID = ATI_VENDOR_ID,
1512 .deviceID = pdevice->rad_info.pci_id,
1513 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1514 .limits = limits,
1515 .sparseProperties = {0},
1516 };
1517
1518 strcpy(pProperties->deviceName, pdevice->name);
1519 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1520 }
1521
1522 static void
1523 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1524 VkPhysicalDeviceVulkan11Properties *p)
1525 {
1526 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1527
1528 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1529 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1530 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1531 /* The LUID is for Windows. */
1532 p->deviceLUIDValid = false;
1533 p->deviceNodeMask = 0;
1534
1535 p->subgroupSize = RADV_SUBGROUP_SIZE;
1536 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1537 VK_SHADER_STAGE_COMPUTE_BIT;
1538 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1539 VK_SUBGROUP_FEATURE_VOTE_BIT |
1540 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1541 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1542 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1543 VK_SUBGROUP_FEATURE_QUAD_BIT |
1544 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1545 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1546 p->subgroupQuadOperationsInAllStages = true;
1547
1548 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1549 p->maxMultiviewViewCount = MAX_VIEWS;
1550 p->maxMultiviewInstanceIndex = INT_MAX;
1551 p->protectedNoFault = false;
1552 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1553 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1554 }
1555
1556 static void
1557 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1558 VkPhysicalDeviceVulkan12Properties *p)
1559 {
1560 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1561
1562 p->driverID = VK_DRIVER_ID_MESA_RADV;
1563 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1564 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1565 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1 " (%s)",
1566 radv_get_compiler_string(pdevice));
1567 p->conformanceVersion = (VkConformanceVersion) {
1568 .major = 1,
1569 .minor = 2,
1570 .subminor = 0,
1571 .patch = 0,
1572 };
1573
1574 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1575 * controlled by the same config register.
1576 */
1577 if (pdevice->rad_info.has_packed_math_16bit) {
1578 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1579 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1580 } else {
1581 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1582 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1583 }
1584
1585 /* With LLVM, do not allow both preserving and flushing denorms because
1586 * different shaders in the same pipeline can have different settings and
1587 * this won't work for merged shaders. To make it work, this requires LLVM
1588 * support for changing the register. The same logic applies for the
1589 * rounding modes because they are configured with the same config
1590 * register.
1591 */
1592 p->shaderDenormFlushToZeroFloat32 = true;
1593 p->shaderDenormPreserveFloat32 = !pdevice->use_llvm;
1594 p->shaderRoundingModeRTEFloat32 = true;
1595 p->shaderRoundingModeRTZFloat32 = !pdevice->use_llvm;
1596 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1597
1598 p->shaderDenormFlushToZeroFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1599 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1600 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_packed_math_16bit;
1601 p->shaderRoundingModeRTZFloat16 = pdevice->rad_info.has_packed_math_16bit && !pdevice->use_llvm;
1602 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_packed_math_16bit;
1603
1604 p->shaderDenormFlushToZeroFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1605 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1606 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1607 p->shaderRoundingModeRTZFloat64 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_llvm;
1608 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1609
1610 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1611 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1612 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1613 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1614 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1615 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1616 p->robustBufferAccessUpdateAfterBind = false;
1617 p->quadDivergentImplicitLod = false;
1618
1619 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1620 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1621 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1622 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1623 32 /* sampler, largest when combined with image */ +
1624 64 /* sampled image */ +
1625 64 /* storage image */);
1626 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1627 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1628 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1629 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1630 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1631 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1632 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1633 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1634 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1635 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1636 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1637 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1638 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1639 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1640 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1641
1642 /* We support all of the depth resolve modes */
1643 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1644 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1645 VK_RESOLVE_MODE_MIN_BIT_KHR |
1646 VK_RESOLVE_MODE_MAX_BIT_KHR;
1647
1648 /* Average doesn't make sense for stencil so we don't support that */
1649 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1650 VK_RESOLVE_MODE_MIN_BIT_KHR |
1651 VK_RESOLVE_MODE_MAX_BIT_KHR;
1652
1653 p->independentResolveNone = true;
1654 p->independentResolve = true;
1655
1656 /* GFX6-8 only support single channel min/max filter. */
1657 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1658 p->filterMinmaxSingleComponentFormats = true;
1659
1660 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1661
1662 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1663 }
1664
1665 void radv_GetPhysicalDeviceProperties2(
1666 VkPhysicalDevice physicalDevice,
1667 VkPhysicalDeviceProperties2 *pProperties)
1668 {
1669 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1670 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1671
1672 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1673 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1674 };
1675 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1676
1677 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1678 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1679 };
1680 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1681
1682 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1683 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1684 sizeof(core_##major##_##minor.core_property))
1685
1686 #define CORE_PROPERTY(major, minor, property) \
1687 CORE_RENAMED_PROPERTY(major, minor, property, property)
1688
1689 vk_foreach_struct(ext, pProperties->pNext) {
1690 switch (ext->sType) {
1691 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1692 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1693 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1694 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1695 break;
1696 }
1697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1698 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1699 CORE_PROPERTY(1, 1, deviceUUID);
1700 CORE_PROPERTY(1, 1, driverUUID);
1701 CORE_PROPERTY(1, 1, deviceLUID);
1702 CORE_PROPERTY(1, 1, deviceLUIDValid);
1703 break;
1704 }
1705 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1706 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1707 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1708 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1709 break;
1710 }
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1712 VkPhysicalDevicePointClippingProperties *properties =
1713 (VkPhysicalDevicePointClippingProperties*)ext;
1714 CORE_PROPERTY(1, 1, pointClippingBehavior);
1715 break;
1716 }
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1718 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1719 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1720 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1721 break;
1722 }
1723 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1724 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1725 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1726 properties->minImportedHostPointerAlignment = 4096;
1727 break;
1728 }
1729 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1730 VkPhysicalDeviceSubgroupProperties *properties =
1731 (VkPhysicalDeviceSubgroupProperties*)ext;
1732 CORE_PROPERTY(1, 1, subgroupSize);
1733 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1734 subgroupSupportedStages);
1735 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1736 subgroupSupportedOperations);
1737 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1738 subgroupQuadOperationsInAllStages);
1739 break;
1740 }
1741 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1742 VkPhysicalDeviceMaintenance3Properties *properties =
1743 (VkPhysicalDeviceMaintenance3Properties*)ext;
1744 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1745 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1746 break;
1747 }
1748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1749 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1750 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1751 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1752 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1753 break;
1754 }
1755 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1756 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1757 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1758
1759 /* Shader engines. */
1760 properties->shaderEngineCount =
1761 pdevice->rad_info.max_se;
1762 properties->shaderArraysPerEngineCount =
1763 pdevice->rad_info.max_sh_per_se;
1764 properties->computeUnitsPerShaderArray =
1765 pdevice->rad_info.min_good_cu_per_sa;
1766 properties->simdPerComputeUnit =
1767 pdevice->rad_info.num_simd_per_compute_unit;
1768 properties->wavefrontsPerSimd =
1769 pdevice->rad_info.max_wave64_per_simd;
1770 properties->wavefrontSize = 64;
1771
1772 /* SGPR. */
1773 properties->sgprsPerSimd =
1774 pdevice->rad_info.num_physical_sgprs_per_simd;
1775 properties->minSgprAllocation =
1776 pdevice->rad_info.min_sgpr_alloc;
1777 properties->maxSgprAllocation =
1778 pdevice->rad_info.max_sgpr_alloc;
1779 properties->sgprAllocationGranularity =
1780 pdevice->rad_info.sgpr_alloc_granularity;
1781
1782 /* VGPR. */
1783 properties->vgprsPerSimd =
1784 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1785 properties->minVgprAllocation =
1786 pdevice->rad_info.min_wave64_vgpr_alloc;
1787 properties->maxVgprAllocation =
1788 pdevice->rad_info.max_vgpr_alloc;
1789 properties->vgprAllocationGranularity =
1790 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1791 break;
1792 }
1793 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1794 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1795 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1796
1797 properties->shaderCoreFeatures = 0;
1798 properties->activeComputeUnitCount =
1799 pdevice->rad_info.num_good_compute_units;
1800 break;
1801 }
1802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1803 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1804 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1805 properties->maxVertexAttribDivisor = UINT32_MAX;
1806 break;
1807 }
1808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1809 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1810 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1811 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1812 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1813 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1814 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1815 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1816 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1817 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1818 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1819 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1820 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1821 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1822 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1823 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1824 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1825 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1826 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1827 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1828 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1829 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1830 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1831 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1832 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1833 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1834 break;
1835 }
1836 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1837 VkPhysicalDeviceProtectedMemoryProperties *properties =
1838 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1839 CORE_PROPERTY(1, 1, protectedNoFault);
1840 break;
1841 }
1842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1843 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1844 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1845 properties->primitiveOverestimationSize = 0;
1846 properties->maxExtraPrimitiveOverestimationSize = 0;
1847 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1848 properties->primitiveUnderestimation = false;
1849 properties->conservativePointAndLineRasterization = false;
1850 properties->degenerateTrianglesRasterized = false;
1851 properties->degenerateLinesRasterized = false;
1852 properties->fullyCoveredFragmentShaderInputVariable = false;
1853 properties->conservativeRasterizationPostDepthCoverage = false;
1854 break;
1855 }
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1857 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1858 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1859 properties->pciDomain = pdevice->bus_info.domain;
1860 properties->pciBus = pdevice->bus_info.bus;
1861 properties->pciDevice = pdevice->bus_info.dev;
1862 properties->pciFunction = pdevice->bus_info.func;
1863 break;
1864 }
1865 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1866 VkPhysicalDeviceDriverProperties *properties =
1867 (VkPhysicalDeviceDriverProperties *) ext;
1868 CORE_PROPERTY(1, 2, driverID);
1869 CORE_PROPERTY(1, 2, driverName);
1870 CORE_PROPERTY(1, 2, driverInfo);
1871 CORE_PROPERTY(1, 2, conformanceVersion);
1872 break;
1873 }
1874 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1875 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1876 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1877 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1878 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1879 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1880 properties->maxTransformFeedbackStreamDataSize = 512;
1881 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1882 properties->maxTransformFeedbackBufferDataStride = 512;
1883 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1884 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1885 properties->transformFeedbackRasterizationStreamSelect = false;
1886 properties->transformFeedbackDraw = true;
1887 break;
1888 }
1889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1890 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1891 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1892
1893 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1894 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1895 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1896 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1897 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1898 break;
1899 }
1900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1901 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1902 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1903 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1904 VK_SAMPLE_COUNT_4_BIT |
1905 VK_SAMPLE_COUNT_8_BIT;
1906 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1907 properties->sampleLocationCoordinateRange[0] = 0.0f;
1908 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1909 properties->sampleLocationSubPixelBits = 4;
1910 properties->variableSampleLocations = false;
1911 break;
1912 }
1913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1914 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1915 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1916 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1917 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1918 CORE_PROPERTY(1, 2, independentResolveNone);
1919 CORE_PROPERTY(1, 2, independentResolve);
1920 break;
1921 }
1922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1923 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1924 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1925 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1926 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1927 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1928 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1929 break;
1930 }
1931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1932 VkPhysicalDeviceFloatControlsProperties *properties =
1933 (VkPhysicalDeviceFloatControlsProperties *)ext;
1934 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1935 CORE_PROPERTY(1, 2, roundingModeIndependence);
1936 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1937 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1938 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1939 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1940 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1941 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1942 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1943 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1944 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1945 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1946 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1947 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1948 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1949 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1950 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1951 break;
1952 }
1953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1954 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1955 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1956 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1957 break;
1958 }
1959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1960 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1961 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1962 props->minSubgroupSize = 64;
1963 props->maxSubgroupSize = 64;
1964 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1965 props->requiredSubgroupSizeStages = 0;
1966
1967 if (pdevice->rad_info.chip_class >= GFX10) {
1968 /* Only GFX10+ supports wave32. */
1969 props->minSubgroupSize = 32;
1970 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1971 }
1972 break;
1973 }
1974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1975 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1976 break;
1977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1978 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1979 break;
1980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1981 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1982 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1983 props->lineSubPixelPrecisionBits = 4;
1984 break;
1985 }
1986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT: {
1987 VkPhysicalDeviceRobustness2PropertiesEXT *properties =
1988 (VkPhysicalDeviceRobustness2PropertiesEXT *)ext;
1989 properties->robustStorageBufferAccessSizeAlignment = 4;
1990 properties->robustUniformBufferAccessSizeAlignment = 4;
1991 break;
1992 }
1993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT: {
1994 VkPhysicalDeviceCustomBorderColorPropertiesEXT *props =
1995 (VkPhysicalDeviceCustomBorderColorPropertiesEXT *)ext;
1996 props->maxCustomBorderColorSamplers = RADV_BORDER_COLOR_COUNT;
1997 break;
1998 }
1999 default:
2000 break;
2001 }
2002 }
2003 }
2004
2005 static void radv_get_physical_device_queue_family_properties(
2006 struct radv_physical_device* pdevice,
2007 uint32_t* pCount,
2008 VkQueueFamilyProperties** pQueueFamilyProperties)
2009 {
2010 int num_queue_families = 1;
2011 int idx;
2012 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2013 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
2014 num_queue_families++;
2015
2016 if (pQueueFamilyProperties == NULL) {
2017 *pCount = num_queue_families;
2018 return;
2019 }
2020
2021 if (!*pCount)
2022 return;
2023
2024 idx = 0;
2025 if (*pCount >= 1) {
2026 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2027 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
2028 VK_QUEUE_COMPUTE_BIT |
2029 VK_QUEUE_TRANSFER_BIT |
2030 VK_QUEUE_SPARSE_BINDING_BIT,
2031 .queueCount = 1,
2032 .timestampValidBits = 64,
2033 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2034 };
2035 idx++;
2036 }
2037
2038 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
2039 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
2040 if (*pCount > idx) {
2041 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
2042 .queueFlags = VK_QUEUE_COMPUTE_BIT |
2043 VK_QUEUE_TRANSFER_BIT |
2044 VK_QUEUE_SPARSE_BINDING_BIT,
2045 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
2046 .timestampValidBits = 64,
2047 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
2048 };
2049 idx++;
2050 }
2051 }
2052 *pCount = idx;
2053 }
2054
2055 void radv_GetPhysicalDeviceQueueFamilyProperties(
2056 VkPhysicalDevice physicalDevice,
2057 uint32_t* pCount,
2058 VkQueueFamilyProperties* pQueueFamilyProperties)
2059 {
2060 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2061 if (!pQueueFamilyProperties) {
2062 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2063 return;
2064 }
2065 VkQueueFamilyProperties *properties[] = {
2066 pQueueFamilyProperties + 0,
2067 pQueueFamilyProperties + 1,
2068 pQueueFamilyProperties + 2,
2069 };
2070 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2071 assert(*pCount <= 3);
2072 }
2073
2074 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2075 VkPhysicalDevice physicalDevice,
2076 uint32_t* pCount,
2077 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2078 {
2079 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2080 if (!pQueueFamilyProperties) {
2081 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2082 return;
2083 }
2084 VkQueueFamilyProperties *properties[] = {
2085 &pQueueFamilyProperties[0].queueFamilyProperties,
2086 &pQueueFamilyProperties[1].queueFamilyProperties,
2087 &pQueueFamilyProperties[2].queueFamilyProperties,
2088 };
2089 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2090 assert(*pCount <= 3);
2091 }
2092
2093 void radv_GetPhysicalDeviceMemoryProperties(
2094 VkPhysicalDevice physicalDevice,
2095 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2096 {
2097 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2098
2099 *pMemoryProperties = physical_device->memory_properties;
2100 }
2101
2102 static void
2103 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2104 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2105 {
2106 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2107 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2108 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2109 uint64_t vram_size = radv_get_vram_size(device);
2110 uint64_t gtt_size = device->rad_info.gart_size;
2111 uint64_t heap_budget, heap_usage;
2112
2113 /* For all memory heaps, the computation of budget is as follow:
2114 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2115 *
2116 * The Vulkan spec 1.1.97 says that the budget should include any
2117 * currently allocated device memory.
2118 *
2119 * Note that the application heap usages are not really accurate (eg.
2120 * in presence of shared buffers).
2121 */
2122 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2123 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2124
2125 if ((device->memory_domains[i] & RADEON_DOMAIN_VRAM) && (device->memory_flags[i] & RADEON_FLAG_NO_CPU_ACCESS)) {
2126 heap_usage = device->ws->query_value(device->ws,
2127 RADEON_ALLOCATED_VRAM);
2128
2129 heap_budget = vram_size -
2130 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2131 heap_usage;
2132
2133 memoryBudget->heapBudget[heap_index] = heap_budget;
2134 memoryBudget->heapUsage[heap_index] = heap_usage;
2135 } else if (device->memory_domains[i] & RADEON_DOMAIN_VRAM) {
2136 heap_usage = device->ws->query_value(device->ws,
2137 RADEON_ALLOCATED_VRAM_VIS);
2138
2139 heap_budget = visible_vram_size -
2140 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2141 heap_usage;
2142
2143 memoryBudget->heapBudget[heap_index] = heap_budget;
2144 memoryBudget->heapUsage[heap_index] = heap_usage;
2145 } else {
2146 assert(device->memory_domains[i] & RADEON_DOMAIN_GTT);
2147
2148 heap_usage = device->ws->query_value(device->ws,
2149 RADEON_ALLOCATED_GTT);
2150
2151 heap_budget = gtt_size -
2152 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2153 heap_usage;
2154
2155 memoryBudget->heapBudget[heap_index] = heap_budget;
2156 memoryBudget->heapUsage[heap_index] = heap_usage;
2157 }
2158 }
2159
2160 /* The heapBudget and heapUsage values must be zero for array elements
2161 * greater than or equal to
2162 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2163 */
2164 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2165 memoryBudget->heapBudget[i] = 0;
2166 memoryBudget->heapUsage[i] = 0;
2167 }
2168 }
2169
2170 void radv_GetPhysicalDeviceMemoryProperties2(
2171 VkPhysicalDevice physicalDevice,
2172 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2173 {
2174 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2175 &pMemoryProperties->memoryProperties);
2176
2177 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2178 vk_find_struct(pMemoryProperties->pNext,
2179 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2180 if (memory_budget)
2181 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2182 }
2183
2184 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2185 VkDevice _device,
2186 VkExternalMemoryHandleTypeFlagBits handleType,
2187 const void *pHostPointer,
2188 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2189 {
2190 RADV_FROM_HANDLE(radv_device, device, _device);
2191
2192 switch (handleType)
2193 {
2194 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2195 const struct radv_physical_device *physical_device = device->physical_device;
2196 uint32_t memoryTypeBits = 0;
2197 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2198 if (physical_device->memory_domains[i] == RADEON_DOMAIN_GTT &&
2199 !(physical_device->memory_flags[i] & RADEON_FLAG_GTT_WC)) {
2200 memoryTypeBits = (1 << i);
2201 break;
2202 }
2203 }
2204 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2205 return VK_SUCCESS;
2206 }
2207 default:
2208 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2209 }
2210 }
2211
2212 static enum radeon_ctx_priority
2213 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2214 {
2215 /* Default to MEDIUM when a specific global priority isn't requested */
2216 if (!pObj)
2217 return RADEON_CTX_PRIORITY_MEDIUM;
2218
2219 switch(pObj->globalPriority) {
2220 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2221 return RADEON_CTX_PRIORITY_REALTIME;
2222 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2223 return RADEON_CTX_PRIORITY_HIGH;
2224 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2225 return RADEON_CTX_PRIORITY_MEDIUM;
2226 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2227 return RADEON_CTX_PRIORITY_LOW;
2228 default:
2229 unreachable("Illegal global priority value");
2230 return RADEON_CTX_PRIORITY_INVALID;
2231 }
2232 }
2233
2234 static int
2235 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2236 uint32_t queue_family_index, int idx,
2237 VkDeviceQueueCreateFlags flags,
2238 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2239 {
2240 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2241 queue->device = device;
2242 queue->queue_family_index = queue_family_index;
2243 queue->queue_idx = idx;
2244 queue->priority = radv_get_queue_global_priority(global_priority);
2245 queue->flags = flags;
2246 queue->hw_ctx = NULL;
2247
2248 VkResult result = device->ws->ctx_create(device->ws, queue->priority, &queue->hw_ctx);
2249 if (result != VK_SUCCESS)
2250 return vk_error(device->instance, result);
2251
2252 list_inithead(&queue->pending_submissions);
2253 pthread_mutex_init(&queue->pending_mutex, NULL);
2254
2255 return VK_SUCCESS;
2256 }
2257
2258 static void
2259 radv_queue_finish(struct radv_queue *queue)
2260 {
2261 pthread_mutex_destroy(&queue->pending_mutex);
2262
2263 if (queue->hw_ctx)
2264 queue->device->ws->ctx_destroy(queue->hw_ctx);
2265
2266 if (queue->initial_full_flush_preamble_cs)
2267 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2268 if (queue->initial_preamble_cs)
2269 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2270 if (queue->continue_preamble_cs)
2271 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2272 if (queue->descriptor_bo)
2273 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2274 if (queue->scratch_bo)
2275 queue->device->ws->buffer_destroy(queue->scratch_bo);
2276 if (queue->esgs_ring_bo)
2277 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2278 if (queue->gsvs_ring_bo)
2279 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2280 if (queue->tess_rings_bo)
2281 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2282 if (queue->gds_bo)
2283 queue->device->ws->buffer_destroy(queue->gds_bo);
2284 if (queue->gds_oa_bo)
2285 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2286 if (queue->compute_scratch_bo)
2287 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2288 }
2289
2290 static void
2291 radv_bo_list_init(struct radv_bo_list *bo_list)
2292 {
2293 pthread_mutex_init(&bo_list->mutex, NULL);
2294 bo_list->list.count = bo_list->capacity = 0;
2295 bo_list->list.bos = NULL;
2296 }
2297
2298 static void
2299 radv_bo_list_finish(struct radv_bo_list *bo_list)
2300 {
2301 free(bo_list->list.bos);
2302 pthread_mutex_destroy(&bo_list->mutex);
2303 }
2304
2305 VkResult radv_bo_list_add(struct radv_device *device,
2306 struct radeon_winsys_bo *bo)
2307 {
2308 struct radv_bo_list *bo_list = &device->bo_list;
2309
2310 if (bo->is_local)
2311 return VK_SUCCESS;
2312
2313 if (unlikely(!device->use_global_bo_list))
2314 return VK_SUCCESS;
2315
2316 pthread_mutex_lock(&bo_list->mutex);
2317 if (bo_list->list.count == bo_list->capacity) {
2318 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2319 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2320
2321 if (!data) {
2322 pthread_mutex_unlock(&bo_list->mutex);
2323 return VK_ERROR_OUT_OF_HOST_MEMORY;
2324 }
2325
2326 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2327 bo_list->capacity = capacity;
2328 }
2329
2330 bo_list->list.bos[bo_list->list.count++] = bo;
2331 pthread_mutex_unlock(&bo_list->mutex);
2332 return VK_SUCCESS;
2333 }
2334
2335 void radv_bo_list_remove(struct radv_device *device,
2336 struct radeon_winsys_bo *bo)
2337 {
2338 struct radv_bo_list *bo_list = &device->bo_list;
2339
2340 if (bo->is_local)
2341 return;
2342
2343 if (unlikely(!device->use_global_bo_list))
2344 return;
2345
2346 pthread_mutex_lock(&bo_list->mutex);
2347 /* Loop the list backwards so we find the most recently added
2348 * memory first. */
2349 for(unsigned i = bo_list->list.count; i-- > 0;) {
2350 if (bo_list->list.bos[i] == bo) {
2351 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2352 --bo_list->list.count;
2353 break;
2354 }
2355 }
2356 pthread_mutex_unlock(&bo_list->mutex);
2357 }
2358
2359 static void
2360 radv_device_init_gs_info(struct radv_device *device)
2361 {
2362 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2363 device->physical_device->rad_info.family);
2364 }
2365
2366 static int radv_get_device_extension_index(const char *name)
2367 {
2368 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2369 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2370 return i;
2371 }
2372 return -1;
2373 }
2374
2375 static int
2376 radv_get_int_debug_option(const char *name, int default_value)
2377 {
2378 const char *str;
2379 int result;
2380
2381 str = getenv(name);
2382 if (!str) {
2383 result = default_value;
2384 } else {
2385 char *endptr;
2386
2387 result = strtol(str, &endptr, 0);
2388 if (str == endptr) {
2389 /* No digits founs. */
2390 result = default_value;
2391 }
2392 }
2393
2394 return result;
2395 }
2396
2397 static void
2398 radv_device_init_dispatch(struct radv_device *device)
2399 {
2400 const struct radv_instance *instance = device->physical_device->instance;
2401 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2402 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2403 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2404
2405 if (radv_thread_trace >= 0) {
2406 /* Use device entrypoints from the SQTT layer if enabled. */
2407 dispatch_table_layer = &sqtt_device_dispatch_table;
2408 }
2409
2410 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2411 /* Vulkan requires that entrypoints for extensions which have not been
2412 * enabled must not be advertised.
2413 */
2414 if (!unchecked &&
2415 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2416 &instance->enabled_extensions,
2417 &device->enabled_extensions)) {
2418 device->dispatch.entrypoints[i] = NULL;
2419 } else if (dispatch_table_layer &&
2420 dispatch_table_layer->entrypoints[i]) {
2421 device->dispatch.entrypoints[i] =
2422 dispatch_table_layer->entrypoints[i];
2423 } else {
2424 device->dispatch.entrypoints[i] =
2425 radv_device_dispatch_table.entrypoints[i];
2426 }
2427 }
2428 }
2429
2430 static VkResult
2431 radv_create_pthread_cond(pthread_cond_t *cond)
2432 {
2433 pthread_condattr_t condattr;
2434 if (pthread_condattr_init(&condattr)) {
2435 return VK_ERROR_INITIALIZATION_FAILED;
2436 }
2437
2438 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2439 pthread_condattr_destroy(&condattr);
2440 return VK_ERROR_INITIALIZATION_FAILED;
2441 }
2442 if (pthread_cond_init(cond, &condattr)) {
2443 pthread_condattr_destroy(&condattr);
2444 return VK_ERROR_INITIALIZATION_FAILED;
2445 }
2446 pthread_condattr_destroy(&condattr);
2447 return VK_SUCCESS;
2448 }
2449
2450 static VkResult
2451 check_physical_device_features(VkPhysicalDevice physicalDevice,
2452 const VkPhysicalDeviceFeatures *features)
2453 {
2454 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2455 VkPhysicalDeviceFeatures supported_features;
2456 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2457 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2458 VkBool32 *enabled_feature = (VkBool32 *)features;
2459 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2460 for (uint32_t i = 0; i < num_features; i++) {
2461 if (enabled_feature[i] && !supported_feature[i])
2462 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2463 }
2464
2465 return VK_SUCCESS;
2466 }
2467
2468 static VkResult radv_device_init_border_color(struct radv_device *device)
2469 {
2470 device->border_color_data.bo =
2471 device->ws->buffer_create(device->ws,
2472 RADV_BORDER_COLOR_BUFFER_SIZE,
2473 4096,
2474 RADEON_DOMAIN_VRAM,
2475 RADEON_FLAG_CPU_ACCESS |
2476 RADEON_FLAG_READ_ONLY |
2477 RADEON_FLAG_NO_INTERPROCESS_SHARING,
2478 RADV_BO_PRIORITY_SHADER);
2479
2480 if (device->border_color_data.bo == NULL)
2481 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2482
2483 device->border_color_data.colors_gpu_ptr =
2484 device->ws->buffer_map(device->border_color_data.bo);
2485 if (!device->border_color_data.colors_gpu_ptr)
2486 return vk_error(device->physical_device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2487 pthread_mutex_init(&device->border_color_data.mutex, NULL);
2488
2489 return VK_SUCCESS;
2490 }
2491
2492 static void radv_device_finish_border_color(struct radv_device *device)
2493 {
2494 if (device->border_color_data.bo) {
2495 device->ws->buffer_destroy(device->border_color_data.bo);
2496
2497 pthread_mutex_destroy(&device->border_color_data.mutex);
2498 }
2499 }
2500
2501 VkResult radv_CreateDevice(
2502 VkPhysicalDevice physicalDevice,
2503 const VkDeviceCreateInfo* pCreateInfo,
2504 const VkAllocationCallbacks* pAllocator,
2505 VkDevice* pDevice)
2506 {
2507 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2508 VkResult result;
2509 struct radv_device *device;
2510
2511 bool keep_shader_info = false;
2512 bool robust_buffer_access = false;
2513 bool overallocation_disallowed = false;
2514 bool custom_border_colors = false;
2515
2516 /* Check enabled features */
2517 if (pCreateInfo->pEnabledFeatures) {
2518 result = check_physical_device_features(physicalDevice,
2519 pCreateInfo->pEnabledFeatures);
2520 if (result != VK_SUCCESS)
2521 return result;
2522
2523 if (pCreateInfo->pEnabledFeatures->robustBufferAccess)
2524 robust_buffer_access = true;
2525 }
2526
2527 vk_foreach_struct_const(ext, pCreateInfo->pNext) {
2528 switch (ext->sType) {
2529 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2: {
2530 const VkPhysicalDeviceFeatures2 *features = (const void *)ext;
2531 result = check_physical_device_features(physicalDevice,
2532 &features->features);
2533 if (result != VK_SUCCESS)
2534 return result;
2535
2536 if (features->features.robustBufferAccess)
2537 robust_buffer_access = true;
2538 break;
2539 }
2540 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD: {
2541 const VkDeviceMemoryOverallocationCreateInfoAMD *overallocation = (const void *)ext;
2542 if (overallocation->overallocationBehavior == VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD)
2543 overallocation_disallowed = true;
2544 break;
2545 }
2546 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT: {
2547 const VkPhysicalDeviceCustomBorderColorFeaturesEXT *border_color_features = (const void *)ext;
2548 custom_border_colors = border_color_features->customBorderColors;
2549 break;
2550 }
2551 default:
2552 break;
2553 }
2554 }
2555
2556 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2557 sizeof(*device), 8,
2558 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2559 if (!device)
2560 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2561
2562 vk_device_init(&device->vk, pCreateInfo,
2563 &physical_device->instance->alloc, pAllocator);
2564
2565 device->instance = physical_device->instance;
2566 device->physical_device = physical_device;
2567
2568 device->ws = physical_device->ws;
2569
2570 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2571 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2572 int index = radv_get_device_extension_index(ext_name);
2573 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2574 vk_free(&device->vk.alloc, device);
2575 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2576 }
2577
2578 device->enabled_extensions.extensions[index] = true;
2579 }
2580
2581 radv_device_init_dispatch(device);
2582
2583 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2584
2585 /* With update after bind we can't attach bo's to the command buffer
2586 * from the descriptor set anymore, so we have to use a global BO list.
2587 */
2588 device->use_global_bo_list =
2589 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2590 device->enabled_extensions.EXT_descriptor_indexing ||
2591 device->enabled_extensions.EXT_buffer_device_address ||
2592 device->enabled_extensions.KHR_buffer_device_address;
2593
2594 device->robust_buffer_access = robust_buffer_access;
2595
2596 mtx_init(&device->shader_slab_mutex, mtx_plain);
2597 list_inithead(&device->shader_slabs);
2598
2599 device->overallocation_disallowed = overallocation_disallowed;
2600 mtx_init(&device->overallocation_mutex, mtx_plain);
2601
2602 radv_bo_list_init(&device->bo_list);
2603
2604 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2605 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2606 uint32_t qfi = queue_create->queueFamilyIndex;
2607 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2608 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2609
2610 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2611
2612 device->queues[qfi] = vk_alloc(&device->vk.alloc,
2613 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2614 if (!device->queues[qfi]) {
2615 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2616 goto fail;
2617 }
2618
2619 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2620
2621 device->queue_count[qfi] = queue_create->queueCount;
2622
2623 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2624 result = radv_queue_init(device, &device->queues[qfi][q],
2625 qfi, q, queue_create->flags,
2626 global_priority);
2627 if (result != VK_SUCCESS)
2628 goto fail;
2629 }
2630 }
2631
2632 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2633 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2634
2635 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2636 device->dfsm_allowed = device->pbb_allowed &&
2637 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2638
2639 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2640
2641 /* The maximum number of scratch waves. Scratch space isn't divided
2642 * evenly between CUs. The number is only a function of the number of CUs.
2643 * We can decrease the constant to decrease the scratch buffer size.
2644 *
2645 * sctx->scratch_waves must be >= the maximum possible size of
2646 * 1 threadgroup, so that the hw doesn't hang from being unable
2647 * to start any.
2648 *
2649 * The recommended value is 4 per CU at most. Higher numbers don't
2650 * bring much benefit, but they still occupy chip resources (think
2651 * async compute). I've seen ~2% performance difference between 4 and 32.
2652 */
2653 uint32_t max_threads_per_block = 2048;
2654 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2655 max_threads_per_block / 64);
2656
2657 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2658
2659 if (device->physical_device->rad_info.chip_class >= GFX7) {
2660 /* If the KMD allows it (there is a KMD hw register for it),
2661 * allow launching waves out-of-order.
2662 */
2663 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2664 }
2665
2666 radv_device_init_gs_info(device);
2667
2668 device->tess_offchip_block_dw_size =
2669 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2670
2671 if (getenv("RADV_TRACE_FILE")) {
2672 const char *filename = getenv("RADV_TRACE_FILE");
2673
2674 keep_shader_info = true;
2675
2676 if (!radv_init_trace(device))
2677 goto fail;
2678
2679 fprintf(stderr, "*****************************************************************************\n");
2680 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2681 fprintf(stderr, "*****************************************************************************\n");
2682
2683 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2684 radv_dump_enabled_options(device, stderr);
2685 }
2686
2687 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2688 if (radv_thread_trace >= 0) {
2689 fprintf(stderr, "*************************************************\n");
2690 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
2691 fprintf(stderr, "*************************************************\n");
2692
2693 if (device->physical_device->rad_info.chip_class < GFX8) {
2694 fprintf(stderr, "GPU hardware not supported: refer to "
2695 "the RGP documentation for the list of "
2696 "supported GPUs!\n");
2697 abort();
2698 }
2699
2700 /* Default buffer size set to 1MB per SE. */
2701 device->thread_trace_buffer_size =
2702 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2703 device->thread_trace_start_frame = radv_thread_trace;
2704
2705 if (!radv_thread_trace_init(device))
2706 goto fail;
2707 }
2708
2709 device->keep_shader_info = keep_shader_info;
2710 result = radv_device_init_meta(device);
2711 if (result != VK_SUCCESS)
2712 goto fail;
2713
2714 radv_device_init_msaa(device);
2715
2716 /* If the border color extension is enabled, let's create the buffer we need. */
2717 if (custom_border_colors) {
2718 result = radv_device_init_border_color(device);
2719 if (result != VK_SUCCESS)
2720 goto fail;
2721 }
2722
2723 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2724 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2725 if (!device->empty_cs[family])
2726 goto fail;
2727
2728 switch (family) {
2729 case RADV_QUEUE_GENERAL:
2730 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2731 radeon_emit(device->empty_cs[family], CC0_UPDATE_LOAD_ENABLES(1));
2732 radeon_emit(device->empty_cs[family], CC1_UPDATE_SHADOW_ENABLES(1));
2733 break;
2734 case RADV_QUEUE_COMPUTE:
2735 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2736 radeon_emit(device->empty_cs[family], 0);
2737 break;
2738 }
2739
2740 result = device->ws->cs_finalize(device->empty_cs[family]);
2741 if (result != VK_SUCCESS)
2742 goto fail;
2743 }
2744
2745 if (device->physical_device->rad_info.chip_class >= GFX7)
2746 cik_create_gfx_config(device);
2747
2748 VkPipelineCacheCreateInfo ci;
2749 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2750 ci.pNext = NULL;
2751 ci.flags = 0;
2752 ci.pInitialData = NULL;
2753 ci.initialDataSize = 0;
2754 VkPipelineCache pc;
2755 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2756 &ci, NULL, &pc);
2757 if (result != VK_SUCCESS)
2758 goto fail_meta;
2759
2760 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2761
2762 result = radv_create_pthread_cond(&device->timeline_cond);
2763 if (result != VK_SUCCESS)
2764 goto fail_mem_cache;
2765
2766 device->force_aniso =
2767 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2768 if (device->force_aniso >= 0) {
2769 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2770 1 << util_logbase2(device->force_aniso));
2771 }
2772
2773 *pDevice = radv_device_to_handle(device);
2774 return VK_SUCCESS;
2775
2776 fail_mem_cache:
2777 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2778 fail_meta:
2779 radv_device_finish_meta(device);
2780 fail:
2781 radv_bo_list_finish(&device->bo_list);
2782
2783 radv_thread_trace_finish(device);
2784
2785 if (device->trace_bo)
2786 device->ws->buffer_destroy(device->trace_bo);
2787
2788 if (device->gfx_init)
2789 device->ws->buffer_destroy(device->gfx_init);
2790
2791 radv_device_finish_border_color(device);
2792
2793 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2794 for (unsigned q = 0; q < device->queue_count[i]; q++)
2795 radv_queue_finish(&device->queues[i][q]);
2796 if (device->queue_count[i])
2797 vk_free(&device->vk.alloc, device->queues[i]);
2798 }
2799
2800 vk_free(&device->vk.alloc, device);
2801 return result;
2802 }
2803
2804 void radv_DestroyDevice(
2805 VkDevice _device,
2806 const VkAllocationCallbacks* pAllocator)
2807 {
2808 RADV_FROM_HANDLE(radv_device, device, _device);
2809
2810 if (!device)
2811 return;
2812
2813 if (device->trace_bo)
2814 device->ws->buffer_destroy(device->trace_bo);
2815
2816 if (device->gfx_init)
2817 device->ws->buffer_destroy(device->gfx_init);
2818
2819 radv_device_finish_border_color(device);
2820
2821 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2822 for (unsigned q = 0; q < device->queue_count[i]; q++)
2823 radv_queue_finish(&device->queues[i][q]);
2824 if (device->queue_count[i])
2825 vk_free(&device->vk.alloc, device->queues[i]);
2826 if (device->empty_cs[i])
2827 device->ws->cs_destroy(device->empty_cs[i]);
2828 }
2829 radv_device_finish_meta(device);
2830
2831 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2832 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2833
2834 radv_destroy_shader_slabs(device);
2835
2836 pthread_cond_destroy(&device->timeline_cond);
2837 radv_bo_list_finish(&device->bo_list);
2838
2839 radv_thread_trace_finish(device);
2840
2841 vk_free(&device->vk.alloc, device);
2842 }
2843
2844 VkResult radv_EnumerateInstanceLayerProperties(
2845 uint32_t* pPropertyCount,
2846 VkLayerProperties* pProperties)
2847 {
2848 if (pProperties == NULL) {
2849 *pPropertyCount = 0;
2850 return VK_SUCCESS;
2851 }
2852
2853 /* None supported at this time */
2854 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2855 }
2856
2857 VkResult radv_EnumerateDeviceLayerProperties(
2858 VkPhysicalDevice physicalDevice,
2859 uint32_t* pPropertyCount,
2860 VkLayerProperties* pProperties)
2861 {
2862 if (pProperties == NULL) {
2863 *pPropertyCount = 0;
2864 return VK_SUCCESS;
2865 }
2866
2867 /* None supported at this time */
2868 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2869 }
2870
2871 void radv_GetDeviceQueue2(
2872 VkDevice _device,
2873 const VkDeviceQueueInfo2* pQueueInfo,
2874 VkQueue* pQueue)
2875 {
2876 RADV_FROM_HANDLE(radv_device, device, _device);
2877 struct radv_queue *queue;
2878
2879 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2880 if (pQueueInfo->flags != queue->flags) {
2881 /* From the Vulkan 1.1.70 spec:
2882 *
2883 * "The queue returned by vkGetDeviceQueue2 must have the same
2884 * flags value from this structure as that used at device
2885 * creation time in a VkDeviceQueueCreateInfo instance. If no
2886 * matching flags were specified at device creation time then
2887 * pQueue will return VK_NULL_HANDLE."
2888 */
2889 *pQueue = VK_NULL_HANDLE;
2890 return;
2891 }
2892
2893 *pQueue = radv_queue_to_handle(queue);
2894 }
2895
2896 void radv_GetDeviceQueue(
2897 VkDevice _device,
2898 uint32_t queueFamilyIndex,
2899 uint32_t queueIndex,
2900 VkQueue* pQueue)
2901 {
2902 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2903 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2904 .queueFamilyIndex = queueFamilyIndex,
2905 .queueIndex = queueIndex
2906 };
2907
2908 radv_GetDeviceQueue2(_device, &info, pQueue);
2909 }
2910
2911 static void
2912 fill_geom_tess_rings(struct radv_queue *queue,
2913 uint32_t *map,
2914 bool add_sample_positions,
2915 uint32_t esgs_ring_size,
2916 struct radeon_winsys_bo *esgs_ring_bo,
2917 uint32_t gsvs_ring_size,
2918 struct radeon_winsys_bo *gsvs_ring_bo,
2919 uint32_t tess_factor_ring_size,
2920 uint32_t tess_offchip_ring_offset,
2921 uint32_t tess_offchip_ring_size,
2922 struct radeon_winsys_bo *tess_rings_bo)
2923 {
2924 uint32_t *desc = &map[4];
2925
2926 if (esgs_ring_bo) {
2927 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2928
2929 /* stride 0, num records - size, add tid, swizzle, elsize4,
2930 index stride 64 */
2931 desc[0] = esgs_va;
2932 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2933 S_008F04_SWIZZLE_ENABLE(true);
2934 desc[2] = esgs_ring_size;
2935 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2936 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2937 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2938 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2939 S_008F0C_INDEX_STRIDE(3) |
2940 S_008F0C_ADD_TID_ENABLE(1);
2941
2942 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2943 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2944 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2945 S_008F0C_RESOURCE_LEVEL(1);
2946 } else {
2947 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2948 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2949 S_008F0C_ELEMENT_SIZE(1);
2950 }
2951
2952 /* GS entry for ES->GS ring */
2953 /* stride 0, num records - size, elsize0,
2954 index stride 0 */
2955 desc[4] = esgs_va;
2956 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2957 desc[6] = esgs_ring_size;
2958 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2959 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2960 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2961 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2962
2963 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2964 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2965 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2966 S_008F0C_RESOURCE_LEVEL(1);
2967 } else {
2968 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2969 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2970 }
2971 }
2972
2973 desc += 8;
2974
2975 if (gsvs_ring_bo) {
2976 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2977
2978 /* VS entry for GS->VS ring */
2979 /* stride 0, num records - size, elsize0,
2980 index stride 0 */
2981 desc[0] = gsvs_va;
2982 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2983 desc[2] = gsvs_ring_size;
2984 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2985 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2986 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2987 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2988
2989 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2990 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2991 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
2992 S_008F0C_RESOURCE_LEVEL(1);
2993 } else {
2994 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2995 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2996 }
2997
2998 /* stride gsvs_itemsize, num records 64
2999 elsize 4, index stride 16 */
3000 /* shader will patch stride and desc[2] */
3001 desc[4] = gsvs_va;
3002 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3003 S_008F04_SWIZZLE_ENABLE(1);
3004 desc[6] = 0;
3005 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3009 S_008F0C_INDEX_STRIDE(1) |
3010 S_008F0C_ADD_TID_ENABLE(true);
3011
3012 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3013 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3014 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3015 S_008F0C_RESOURCE_LEVEL(1);
3016 } else {
3017 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3018 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3019 S_008F0C_ELEMENT_SIZE(1);
3020 }
3021
3022 }
3023
3024 desc += 8;
3025
3026 if (tess_rings_bo) {
3027 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3028 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3029
3030 desc[0] = tess_va;
3031 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3032 desc[2] = tess_factor_ring_size;
3033 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3034 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3035 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3036 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3037
3038 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3039 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3040 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3041 S_008F0C_RESOURCE_LEVEL(1);
3042 } else {
3043 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3044 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3045 }
3046
3047 desc[4] = tess_offchip_va;
3048 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3049 desc[6] = tess_offchip_ring_size;
3050 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3051 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3052 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3053 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3054
3055 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3056 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3057 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3058 S_008F0C_RESOURCE_LEVEL(1);
3059 } else {
3060 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3061 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3062 }
3063 }
3064
3065 desc += 8;
3066
3067 if (add_sample_positions) {
3068 /* add sample positions after all rings */
3069 memcpy(desc, queue->device->sample_locations_1x, 8);
3070 desc += 2;
3071 memcpy(desc, queue->device->sample_locations_2x, 16);
3072 desc += 4;
3073 memcpy(desc, queue->device->sample_locations_4x, 32);
3074 desc += 8;
3075 memcpy(desc, queue->device->sample_locations_8x, 64);
3076 }
3077 }
3078
3079 static unsigned
3080 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3081 {
3082 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3083 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3084 device->physical_device->rad_info.family != CHIP_STONEY;
3085 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3086 unsigned max_offchip_buffers;
3087 unsigned offchip_granularity;
3088 unsigned hs_offchip_param;
3089
3090 /*
3091 * Per RadeonSI:
3092 * This must be one less than the maximum number due to a hw limitation.
3093 * Various hardware bugs need thGFX7
3094 *
3095 * Per AMDVLK:
3096 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3097 * Gfx7 should limit max_offchip_buffers to 508
3098 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3099 *
3100 * Follow AMDVLK here.
3101 */
3102 if (device->physical_device->rad_info.chip_class >= GFX10) {
3103 max_offchip_buffers_per_se = 256;
3104 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3105 device->physical_device->rad_info.chip_class == GFX7 ||
3106 device->physical_device->rad_info.chip_class == GFX6)
3107 --max_offchip_buffers_per_se;
3108
3109 max_offchip_buffers = max_offchip_buffers_per_se *
3110 device->physical_device->rad_info.max_se;
3111
3112 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3113 * around by setting 4K granularity.
3114 */
3115 if (device->tess_offchip_block_dw_size == 4096) {
3116 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3117 offchip_granularity = V_03093C_X_4K_DWORDS;
3118 } else {
3119 assert(device->tess_offchip_block_dw_size == 8192);
3120 offchip_granularity = V_03093C_X_8K_DWORDS;
3121 }
3122
3123 switch (device->physical_device->rad_info.chip_class) {
3124 case GFX6:
3125 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3126 break;
3127 case GFX7:
3128 case GFX8:
3129 case GFX9:
3130 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3131 break;
3132 case GFX10:
3133 break;
3134 default:
3135 break;
3136 }
3137
3138 *max_offchip_buffers_p = max_offchip_buffers;
3139 if (device->physical_device->rad_info.chip_class >= GFX10_3) {
3140 hs_offchip_param = S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers - 1) |
3141 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity);
3142 } else if (device->physical_device->rad_info.chip_class >= GFX7) {
3143 if (device->physical_device->rad_info.chip_class >= GFX8)
3144 --max_offchip_buffers;
3145 hs_offchip_param =
3146 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3147 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3148 } else {
3149 hs_offchip_param =
3150 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3151 }
3152 return hs_offchip_param;
3153 }
3154
3155 static void
3156 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3157 struct radeon_winsys_bo *esgs_ring_bo,
3158 uint32_t esgs_ring_size,
3159 struct radeon_winsys_bo *gsvs_ring_bo,
3160 uint32_t gsvs_ring_size)
3161 {
3162 if (!esgs_ring_bo && !gsvs_ring_bo)
3163 return;
3164
3165 if (esgs_ring_bo)
3166 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3167
3168 if (gsvs_ring_bo)
3169 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3170
3171 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3172 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3173 radeon_emit(cs, esgs_ring_size >> 8);
3174 radeon_emit(cs, gsvs_ring_size >> 8);
3175 } else {
3176 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3177 radeon_emit(cs, esgs_ring_size >> 8);
3178 radeon_emit(cs, gsvs_ring_size >> 8);
3179 }
3180 }
3181
3182 static void
3183 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3184 unsigned hs_offchip_param, unsigned tf_ring_size,
3185 struct radeon_winsys_bo *tess_rings_bo)
3186 {
3187 uint64_t tf_va;
3188
3189 if (!tess_rings_bo)
3190 return;
3191
3192 tf_va = radv_buffer_get_va(tess_rings_bo);
3193
3194 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3195
3196 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3197 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3198 S_030938_SIZE(tf_ring_size / 4));
3199 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3200 tf_va >> 8);
3201
3202 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3203 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3204 S_030984_BASE_HI(tf_va >> 40));
3205 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3206 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3207 S_030944_BASE_HI(tf_va >> 40));
3208 }
3209 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3210 hs_offchip_param);
3211 } else {
3212 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3213 S_008988_SIZE(tf_ring_size / 4));
3214 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3215 tf_va >> 8);
3216 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3217 hs_offchip_param);
3218 }
3219 }
3220
3221 static void
3222 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3223 uint32_t size_per_wave, uint32_t waves,
3224 struct radeon_winsys_bo *scratch_bo)
3225 {
3226 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3227 return;
3228
3229 if (!scratch_bo)
3230 return;
3231
3232 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3233
3234 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3235 S_0286E8_WAVES(waves) |
3236 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3237 }
3238
3239 static void
3240 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3241 uint32_t size_per_wave, uint32_t waves,
3242 struct radeon_winsys_bo *compute_scratch_bo)
3243 {
3244 uint64_t scratch_va;
3245
3246 if (!compute_scratch_bo)
3247 return;
3248
3249 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3250
3251 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3252
3253 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3254 radeon_emit(cs, scratch_va);
3255 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3256 S_008F04_SWIZZLE_ENABLE(1));
3257
3258 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3259 S_00B860_WAVES(waves) |
3260 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3261 }
3262
3263 static void
3264 radv_emit_global_shader_pointers(struct radv_queue *queue,
3265 struct radeon_cmdbuf *cs,
3266 struct radeon_winsys_bo *descriptor_bo)
3267 {
3268 uint64_t va;
3269
3270 if (!descriptor_bo)
3271 return;
3272
3273 va = radv_buffer_get_va(descriptor_bo);
3274
3275 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3276
3277 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3278 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3279 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3280 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3281 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3282
3283 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3284 radv_emit_shader_pointer(queue->device, cs, regs[i],
3285 va, true);
3286 }
3287 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3288 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3289 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3290 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3291 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3292
3293 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3294 radv_emit_shader_pointer(queue->device, cs, regs[i],
3295 va, true);
3296 }
3297 } else {
3298 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3299 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3300 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3301 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3302 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3303 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3304
3305 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3306 radv_emit_shader_pointer(queue->device, cs, regs[i],
3307 va, true);
3308 }
3309 }
3310 }
3311
3312 static void
3313 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3314 {
3315 struct radv_device *device = queue->device;
3316
3317 if (device->gfx_init) {
3318 uint64_t va = radv_buffer_get_va(device->gfx_init);
3319
3320 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3321 radeon_emit(cs, va);
3322 radeon_emit(cs, va >> 32);
3323 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3324
3325 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3326 } else {
3327 si_emit_graphics(device, cs);
3328 }
3329 }
3330
3331 static void
3332 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3333 {
3334 struct radv_physical_device *physical_device = queue->device->physical_device;
3335 si_emit_compute(physical_device, cs);
3336 }
3337
3338 static VkResult
3339 radv_get_preamble_cs(struct radv_queue *queue,
3340 uint32_t scratch_size_per_wave,
3341 uint32_t scratch_waves,
3342 uint32_t compute_scratch_size_per_wave,
3343 uint32_t compute_scratch_waves,
3344 uint32_t esgs_ring_size,
3345 uint32_t gsvs_ring_size,
3346 bool needs_tess_rings,
3347 bool needs_gds,
3348 bool needs_gds_oa,
3349 bool needs_sample_positions,
3350 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3351 struct radeon_cmdbuf **initial_preamble_cs,
3352 struct radeon_cmdbuf **continue_preamble_cs)
3353 {
3354 struct radeon_winsys_bo *scratch_bo = NULL;
3355 struct radeon_winsys_bo *descriptor_bo = NULL;
3356 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3357 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3358 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3359 struct radeon_winsys_bo *tess_rings_bo = NULL;
3360 struct radeon_winsys_bo *gds_bo = NULL;
3361 struct radeon_winsys_bo *gds_oa_bo = NULL;
3362 struct radeon_cmdbuf *dest_cs[3] = {0};
3363 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3364 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3365 unsigned max_offchip_buffers;
3366 unsigned hs_offchip_param = 0;
3367 unsigned tess_offchip_ring_offset;
3368 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3369 if (!queue->has_tess_rings) {
3370 if (needs_tess_rings)
3371 add_tess_rings = true;
3372 }
3373 if (!queue->has_gds) {
3374 if (needs_gds)
3375 add_gds = true;
3376 }
3377 if (!queue->has_gds_oa) {
3378 if (needs_gds_oa)
3379 add_gds_oa = true;
3380 }
3381 if (!queue->has_sample_positions) {
3382 if (needs_sample_positions)
3383 add_sample_positions = true;
3384 }
3385 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3386 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3387 &max_offchip_buffers);
3388 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3389 tess_offchip_ring_size = max_offchip_buffers *
3390 queue->device->tess_offchip_block_dw_size * 4;
3391
3392 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3393 if (scratch_size_per_wave)
3394 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3395 else
3396 scratch_waves = 0;
3397
3398 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3399 if (compute_scratch_size_per_wave)
3400 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3401 else
3402 compute_scratch_waves = 0;
3403
3404 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3405 scratch_waves <= queue->scratch_waves &&
3406 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3407 compute_scratch_waves <= queue->compute_scratch_waves &&
3408 esgs_ring_size <= queue->esgs_ring_size &&
3409 gsvs_ring_size <= queue->gsvs_ring_size &&
3410 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3411 queue->initial_preamble_cs) {
3412 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3413 *initial_preamble_cs = queue->initial_preamble_cs;
3414 *continue_preamble_cs = queue->continue_preamble_cs;
3415 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3416 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3417 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3418 *continue_preamble_cs = NULL;
3419 return VK_SUCCESS;
3420 }
3421
3422 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3423 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3424 if (scratch_size > queue_scratch_size) {
3425 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3426 scratch_size,
3427 4096,
3428 RADEON_DOMAIN_VRAM,
3429 ring_bo_flags,
3430 RADV_BO_PRIORITY_SCRATCH);
3431 if (!scratch_bo)
3432 goto fail;
3433 } else
3434 scratch_bo = queue->scratch_bo;
3435
3436 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3437 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3438 if (compute_scratch_size > compute_queue_scratch_size) {
3439 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3440 compute_scratch_size,
3441 4096,
3442 RADEON_DOMAIN_VRAM,
3443 ring_bo_flags,
3444 RADV_BO_PRIORITY_SCRATCH);
3445 if (!compute_scratch_bo)
3446 goto fail;
3447
3448 } else
3449 compute_scratch_bo = queue->compute_scratch_bo;
3450
3451 if (esgs_ring_size > queue->esgs_ring_size) {
3452 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3453 esgs_ring_size,
3454 4096,
3455 RADEON_DOMAIN_VRAM,
3456 ring_bo_flags,
3457 RADV_BO_PRIORITY_SCRATCH);
3458 if (!esgs_ring_bo)
3459 goto fail;
3460 } else {
3461 esgs_ring_bo = queue->esgs_ring_bo;
3462 esgs_ring_size = queue->esgs_ring_size;
3463 }
3464
3465 if (gsvs_ring_size > queue->gsvs_ring_size) {
3466 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3467 gsvs_ring_size,
3468 4096,
3469 RADEON_DOMAIN_VRAM,
3470 ring_bo_flags,
3471 RADV_BO_PRIORITY_SCRATCH);
3472 if (!gsvs_ring_bo)
3473 goto fail;
3474 } else {
3475 gsvs_ring_bo = queue->gsvs_ring_bo;
3476 gsvs_ring_size = queue->gsvs_ring_size;
3477 }
3478
3479 if (add_tess_rings) {
3480 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3481 tess_offchip_ring_offset + tess_offchip_ring_size,
3482 256,
3483 RADEON_DOMAIN_VRAM,
3484 ring_bo_flags,
3485 RADV_BO_PRIORITY_SCRATCH);
3486 if (!tess_rings_bo)
3487 goto fail;
3488 } else {
3489 tess_rings_bo = queue->tess_rings_bo;
3490 }
3491
3492 if (add_gds) {
3493 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3494
3495 /* 4 streamout GDS counters.
3496 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3497 */
3498 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3499 256, 4,
3500 RADEON_DOMAIN_GDS,
3501 ring_bo_flags,
3502 RADV_BO_PRIORITY_SCRATCH);
3503 if (!gds_bo)
3504 goto fail;
3505 } else {
3506 gds_bo = queue->gds_bo;
3507 }
3508
3509 if (add_gds_oa) {
3510 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3511
3512 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3513 4, 1,
3514 RADEON_DOMAIN_OA,
3515 ring_bo_flags,
3516 RADV_BO_PRIORITY_SCRATCH);
3517 if (!gds_oa_bo)
3518 goto fail;
3519 } else {
3520 gds_oa_bo = queue->gds_oa_bo;
3521 }
3522
3523 if (scratch_bo != queue->scratch_bo ||
3524 esgs_ring_bo != queue->esgs_ring_bo ||
3525 gsvs_ring_bo != queue->gsvs_ring_bo ||
3526 tess_rings_bo != queue->tess_rings_bo ||
3527 add_sample_positions) {
3528 uint32_t size = 0;
3529 if (gsvs_ring_bo || esgs_ring_bo ||
3530 tess_rings_bo || add_sample_positions) {
3531 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3532 if (add_sample_positions)
3533 size += 128; /* 64+32+16+8 = 120 bytes */
3534 }
3535 else if (scratch_bo)
3536 size = 8; /* 2 dword */
3537
3538 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3539 size,
3540 4096,
3541 RADEON_DOMAIN_VRAM,
3542 RADEON_FLAG_CPU_ACCESS |
3543 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3544 RADEON_FLAG_READ_ONLY,
3545 RADV_BO_PRIORITY_DESCRIPTOR);
3546 if (!descriptor_bo)
3547 goto fail;
3548 } else
3549 descriptor_bo = queue->descriptor_bo;
3550
3551 if (descriptor_bo != queue->descriptor_bo) {
3552 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3553 if (!map)
3554 goto fail;
3555
3556 if (scratch_bo) {
3557 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3558 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3559 S_008F04_SWIZZLE_ENABLE(1);
3560 map[0] = scratch_va;
3561 map[1] = rsrc1;
3562 }
3563
3564 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3565 fill_geom_tess_rings(queue, map, add_sample_positions,
3566 esgs_ring_size, esgs_ring_bo,
3567 gsvs_ring_size, gsvs_ring_bo,
3568 tess_factor_ring_size,
3569 tess_offchip_ring_offset,
3570 tess_offchip_ring_size,
3571 tess_rings_bo);
3572
3573 queue->device->ws->buffer_unmap(descriptor_bo);
3574 }
3575
3576 for(int i = 0; i < 3; ++i) {
3577 struct radeon_cmdbuf *cs = NULL;
3578 cs = queue->device->ws->cs_create(queue->device->ws,
3579 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3580 if (!cs)
3581 goto fail;
3582
3583 dest_cs[i] = cs;
3584
3585 if (scratch_bo)
3586 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3587
3588 /* Emit initial configuration. */
3589 switch (queue->queue_family_index) {
3590 case RADV_QUEUE_GENERAL:
3591 radv_init_graphics_state(cs, queue);
3592 break;
3593 case RADV_QUEUE_COMPUTE:
3594 radv_init_compute_state(cs, queue);
3595 break;
3596 case RADV_QUEUE_TRANSFER:
3597 break;
3598 }
3599
3600 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3601 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3602 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3603
3604 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3605 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3606 }
3607
3608 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3609 gsvs_ring_bo, gsvs_ring_size);
3610 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3611 tess_factor_ring_size, tess_rings_bo);
3612 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3613 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3614 compute_scratch_waves, compute_scratch_bo);
3615 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3616 scratch_waves, scratch_bo);
3617
3618 if (gds_bo)
3619 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3620 if (gds_oa_bo)
3621 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3622
3623 if (queue->device->trace_bo)
3624 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
3625
3626 if (queue->device->border_color_data.bo)
3627 radv_cs_add_buffer(queue->device->ws, cs,
3628 queue->device->border_color_data.bo);
3629
3630 if (i == 0) {
3631 si_cs_emit_cache_flush(cs,
3632 queue->device->physical_device->rad_info.chip_class,
3633 NULL, 0,
3634 queue->queue_family_index == RING_COMPUTE &&
3635 queue->device->physical_device->rad_info.chip_class >= GFX7,
3636 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3637 RADV_CMD_FLAG_INV_ICACHE |
3638 RADV_CMD_FLAG_INV_SCACHE |
3639 RADV_CMD_FLAG_INV_VCACHE |
3640 RADV_CMD_FLAG_INV_L2 |
3641 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3642 } else if (i == 1) {
3643 si_cs_emit_cache_flush(cs,
3644 queue->device->physical_device->rad_info.chip_class,
3645 NULL, 0,
3646 queue->queue_family_index == RING_COMPUTE &&
3647 queue->device->physical_device->rad_info.chip_class >= GFX7,
3648 RADV_CMD_FLAG_INV_ICACHE |
3649 RADV_CMD_FLAG_INV_SCACHE |
3650 RADV_CMD_FLAG_INV_VCACHE |
3651 RADV_CMD_FLAG_INV_L2 |
3652 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3653 }
3654
3655 if (queue->device->ws->cs_finalize(cs) != VK_SUCCESS)
3656 goto fail;
3657 }
3658
3659 if (queue->initial_full_flush_preamble_cs)
3660 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3661
3662 if (queue->initial_preamble_cs)
3663 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3664
3665 if (queue->continue_preamble_cs)
3666 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3667
3668 queue->initial_full_flush_preamble_cs = dest_cs[0];
3669 queue->initial_preamble_cs = dest_cs[1];
3670 queue->continue_preamble_cs = dest_cs[2];
3671
3672 if (scratch_bo != queue->scratch_bo) {
3673 if (queue->scratch_bo)
3674 queue->device->ws->buffer_destroy(queue->scratch_bo);
3675 queue->scratch_bo = scratch_bo;
3676 }
3677 queue->scratch_size_per_wave = scratch_size_per_wave;
3678 queue->scratch_waves = scratch_waves;
3679
3680 if (compute_scratch_bo != queue->compute_scratch_bo) {
3681 if (queue->compute_scratch_bo)
3682 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3683 queue->compute_scratch_bo = compute_scratch_bo;
3684 }
3685 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3686 queue->compute_scratch_waves = compute_scratch_waves;
3687
3688 if (esgs_ring_bo != queue->esgs_ring_bo) {
3689 if (queue->esgs_ring_bo)
3690 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3691 queue->esgs_ring_bo = esgs_ring_bo;
3692 queue->esgs_ring_size = esgs_ring_size;
3693 }
3694
3695 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3696 if (queue->gsvs_ring_bo)
3697 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3698 queue->gsvs_ring_bo = gsvs_ring_bo;
3699 queue->gsvs_ring_size = gsvs_ring_size;
3700 }
3701
3702 if (tess_rings_bo != queue->tess_rings_bo) {
3703 queue->tess_rings_bo = tess_rings_bo;
3704 queue->has_tess_rings = true;
3705 }
3706
3707 if (gds_bo != queue->gds_bo) {
3708 queue->gds_bo = gds_bo;
3709 queue->has_gds = true;
3710 }
3711
3712 if (gds_oa_bo != queue->gds_oa_bo) {
3713 queue->gds_oa_bo = gds_oa_bo;
3714 queue->has_gds_oa = true;
3715 }
3716
3717 if (descriptor_bo != queue->descriptor_bo) {
3718 if (queue->descriptor_bo)
3719 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3720
3721 queue->descriptor_bo = descriptor_bo;
3722 }
3723
3724 if (add_sample_positions)
3725 queue->has_sample_positions = true;
3726
3727 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3728 *initial_preamble_cs = queue->initial_preamble_cs;
3729 *continue_preamble_cs = queue->continue_preamble_cs;
3730 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3731 *continue_preamble_cs = NULL;
3732 return VK_SUCCESS;
3733 fail:
3734 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3735 if (dest_cs[i])
3736 queue->device->ws->cs_destroy(dest_cs[i]);
3737 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3738 queue->device->ws->buffer_destroy(descriptor_bo);
3739 if (scratch_bo && scratch_bo != queue->scratch_bo)
3740 queue->device->ws->buffer_destroy(scratch_bo);
3741 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3742 queue->device->ws->buffer_destroy(compute_scratch_bo);
3743 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3744 queue->device->ws->buffer_destroy(esgs_ring_bo);
3745 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3746 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3747 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3748 queue->device->ws->buffer_destroy(tess_rings_bo);
3749 if (gds_bo && gds_bo != queue->gds_bo)
3750 queue->device->ws->buffer_destroy(gds_bo);
3751 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3752 queue->device->ws->buffer_destroy(gds_oa_bo);
3753
3754 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3755 }
3756
3757 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3758 struct radv_winsys_sem_counts *counts,
3759 int num_sems,
3760 struct radv_semaphore_part **sems,
3761 const uint64_t *timeline_values,
3762 VkFence _fence,
3763 bool is_signal)
3764 {
3765 int syncobj_idx = 0, sem_idx = 0;
3766
3767 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3768 return VK_SUCCESS;
3769
3770 for (uint32_t i = 0; i < num_sems; i++) {
3771 switch(sems[i]->kind) {
3772 case RADV_SEMAPHORE_SYNCOBJ:
3773 counts->syncobj_count++;
3774 break;
3775 case RADV_SEMAPHORE_WINSYS:
3776 counts->sem_count++;
3777 break;
3778 case RADV_SEMAPHORE_NONE:
3779 break;
3780 case RADV_SEMAPHORE_TIMELINE:
3781 counts->syncobj_count++;
3782 break;
3783 }
3784 }
3785
3786 if (_fence != VK_NULL_HANDLE) {
3787 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3788
3789 struct radv_fence_part *part =
3790 fence->temporary.kind != RADV_FENCE_NONE ?
3791 &fence->temporary : &fence->permanent;
3792 if (part->kind == RADV_FENCE_SYNCOBJ)
3793 counts->syncobj_count++;
3794 }
3795
3796 if (counts->syncobj_count) {
3797 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3798 if (!counts->syncobj)
3799 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3800 }
3801
3802 if (counts->sem_count) {
3803 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3804 if (!counts->sem) {
3805 free(counts->syncobj);
3806 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3807 }
3808 }
3809
3810 for (uint32_t i = 0; i < num_sems; i++) {
3811 switch(sems[i]->kind) {
3812 case RADV_SEMAPHORE_NONE:
3813 unreachable("Empty semaphore");
3814 break;
3815 case RADV_SEMAPHORE_SYNCOBJ:
3816 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3817 break;
3818 case RADV_SEMAPHORE_WINSYS:
3819 counts->sem[sem_idx++] = sems[i]->ws_sem;
3820 break;
3821 case RADV_SEMAPHORE_TIMELINE: {
3822 pthread_mutex_lock(&sems[i]->timeline.mutex);
3823 struct radv_timeline_point *point = NULL;
3824 if (is_signal) {
3825 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3826 } else {
3827 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3828 }
3829
3830 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3831
3832 if (point) {
3833 counts->syncobj[syncobj_idx++] = point->syncobj;
3834 } else {
3835 /* Explicitly remove the semaphore so we might not find
3836 * a point later post-submit. */
3837 sems[i] = NULL;
3838 }
3839 break;
3840 }
3841 }
3842 }
3843
3844 if (_fence != VK_NULL_HANDLE) {
3845 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3846
3847 struct radv_fence_part *part =
3848 fence->temporary.kind != RADV_FENCE_NONE ?
3849 &fence->temporary : &fence->permanent;
3850 if (part->kind == RADV_FENCE_SYNCOBJ)
3851 counts->syncobj[syncobj_idx++] = part->syncobj;
3852 }
3853
3854 assert(syncobj_idx <= counts->syncobj_count);
3855 counts->syncobj_count = syncobj_idx;
3856
3857 return VK_SUCCESS;
3858 }
3859
3860 static void
3861 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3862 {
3863 free(sem_info->wait.syncobj);
3864 free(sem_info->wait.sem);
3865 free(sem_info->signal.syncobj);
3866 free(sem_info->signal.sem);
3867 }
3868
3869
3870 static void radv_free_temp_syncobjs(struct radv_device *device,
3871 int num_sems,
3872 struct radv_semaphore_part *sems)
3873 {
3874 for (uint32_t i = 0; i < num_sems; i++) {
3875 radv_destroy_semaphore_part(device, sems + i);
3876 }
3877 }
3878
3879 static VkResult
3880 radv_alloc_sem_info(struct radv_device *device,
3881 struct radv_winsys_sem_info *sem_info,
3882 int num_wait_sems,
3883 struct radv_semaphore_part **wait_sems,
3884 const uint64_t *wait_values,
3885 int num_signal_sems,
3886 struct radv_semaphore_part **signal_sems,
3887 const uint64_t *signal_values,
3888 VkFence fence)
3889 {
3890 VkResult ret;
3891 memset(sem_info, 0, sizeof(*sem_info));
3892
3893 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3894 if (ret)
3895 return ret;
3896 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
3897 if (ret)
3898 radv_free_sem_info(sem_info);
3899
3900 /* caller can override these */
3901 sem_info->cs_emit_wait = true;
3902 sem_info->cs_emit_signal = true;
3903 return ret;
3904 }
3905
3906 static void
3907 radv_finalize_timelines(struct radv_device *device,
3908 uint32_t num_wait_sems,
3909 struct radv_semaphore_part **wait_sems,
3910 const uint64_t *wait_values,
3911 uint32_t num_signal_sems,
3912 struct radv_semaphore_part **signal_sems,
3913 const uint64_t *signal_values,
3914 struct list_head *processing_list)
3915 {
3916 for (uint32_t i = 0; i < num_wait_sems; ++i) {
3917 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3918 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
3919 struct radv_timeline_point *point =
3920 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
3921 point->wait_count -= 2;
3922 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
3923 }
3924 }
3925 for (uint32_t i = 0; i < num_signal_sems; ++i) {
3926 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3927 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
3928 struct radv_timeline_point *point =
3929 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
3930 signal_sems[i]->timeline.highest_submitted =
3931 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
3932 point->wait_count -= 2;
3933 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
3934 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
3935 }
3936 }
3937 }
3938
3939 static void
3940 radv_sparse_buffer_bind_memory(struct radv_device *device,
3941 const VkSparseBufferMemoryBindInfo *bind)
3942 {
3943 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3944
3945 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3946 struct radv_device_memory *mem = NULL;
3947
3948 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3949 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3950
3951 device->ws->buffer_virtual_bind(buffer->bo,
3952 bind->pBinds[i].resourceOffset,
3953 bind->pBinds[i].size,
3954 mem ? mem->bo : NULL,
3955 bind->pBinds[i].memoryOffset);
3956 }
3957 }
3958
3959 static void
3960 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3961 const VkSparseImageOpaqueMemoryBindInfo *bind)
3962 {
3963 RADV_FROM_HANDLE(radv_image, image, bind->image);
3964
3965 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3966 struct radv_device_memory *mem = NULL;
3967
3968 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3969 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3970
3971 device->ws->buffer_virtual_bind(image->bo,
3972 bind->pBinds[i].resourceOffset,
3973 bind->pBinds[i].size,
3974 mem ? mem->bo : NULL,
3975 bind->pBinds[i].memoryOffset);
3976 }
3977 }
3978
3979 static VkResult
3980 radv_get_preambles(struct radv_queue *queue,
3981 const VkCommandBuffer *cmd_buffers,
3982 uint32_t cmd_buffer_count,
3983 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3984 struct radeon_cmdbuf **initial_preamble_cs,
3985 struct radeon_cmdbuf **continue_preamble_cs)
3986 {
3987 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
3988 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
3989 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3990 bool tess_rings_needed = false;
3991 bool gds_needed = false;
3992 bool gds_oa_needed = false;
3993 bool sample_positions_needed = false;
3994
3995 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
3996 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3997 cmd_buffers[j]);
3998
3999 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4000 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4001 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4002 cmd_buffer->compute_scratch_size_per_wave_needed);
4003 compute_waves_wanted = MAX2(compute_waves_wanted,
4004 cmd_buffer->compute_scratch_waves_wanted);
4005 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4006 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4007 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4008 gds_needed |= cmd_buffer->gds_needed;
4009 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4010 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4011 }
4012
4013 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4014 compute_scratch_size_per_wave, compute_waves_wanted,
4015 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4016 gds_needed, gds_oa_needed, sample_positions_needed,
4017 initial_full_flush_preamble_cs,
4018 initial_preamble_cs, continue_preamble_cs);
4019 }
4020
4021 struct radv_deferred_queue_submission {
4022 struct radv_queue *queue;
4023 VkCommandBuffer *cmd_buffers;
4024 uint32_t cmd_buffer_count;
4025
4026 /* Sparse bindings that happen on a queue. */
4027 VkSparseBufferMemoryBindInfo *buffer_binds;
4028 uint32_t buffer_bind_count;
4029 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4030 uint32_t image_opaque_bind_count;
4031
4032 bool flush_caches;
4033 VkShaderStageFlags wait_dst_stage_mask;
4034 struct radv_semaphore_part **wait_semaphores;
4035 uint32_t wait_semaphore_count;
4036 struct radv_semaphore_part **signal_semaphores;
4037 uint32_t signal_semaphore_count;
4038 VkFence fence;
4039
4040 uint64_t *wait_values;
4041 uint64_t *signal_values;
4042
4043 struct radv_semaphore_part *temporary_semaphore_parts;
4044 uint32_t temporary_semaphore_part_count;
4045
4046 struct list_head queue_pending_list;
4047 uint32_t submission_wait_count;
4048 struct radv_timeline_waiter *wait_nodes;
4049
4050 struct list_head processing_list;
4051 };
4052
4053 struct radv_queue_submission {
4054 const VkCommandBuffer *cmd_buffers;
4055 uint32_t cmd_buffer_count;
4056
4057 /* Sparse bindings that happen on a queue. */
4058 const VkSparseBufferMemoryBindInfo *buffer_binds;
4059 uint32_t buffer_bind_count;
4060 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4061 uint32_t image_opaque_bind_count;
4062
4063 bool flush_caches;
4064 VkPipelineStageFlags wait_dst_stage_mask;
4065 const VkSemaphore *wait_semaphores;
4066 uint32_t wait_semaphore_count;
4067 const VkSemaphore *signal_semaphores;
4068 uint32_t signal_semaphore_count;
4069 VkFence fence;
4070
4071 const uint64_t *wait_values;
4072 uint32_t wait_value_count;
4073 const uint64_t *signal_values;
4074 uint32_t signal_value_count;
4075 };
4076
4077 static VkResult
4078 radv_create_deferred_submission(struct radv_queue *queue,
4079 const struct radv_queue_submission *submission,
4080 struct radv_deferred_queue_submission **out)
4081 {
4082 struct radv_deferred_queue_submission *deferred = NULL;
4083 size_t size = sizeof(struct radv_deferred_queue_submission);
4084
4085 uint32_t temporary_count = 0;
4086 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4087 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4088 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4089 ++temporary_count;
4090 }
4091
4092 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4093 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4094 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4095 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4096 size += temporary_count * sizeof(struct radv_semaphore_part);
4097 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4098 size += submission->wait_value_count * sizeof(uint64_t);
4099 size += submission->signal_value_count * sizeof(uint64_t);
4100 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4101
4102 deferred = calloc(1, size);
4103 if (!deferred)
4104 return VK_ERROR_OUT_OF_HOST_MEMORY;
4105
4106 deferred->queue = queue;
4107
4108 deferred->cmd_buffers = (void*)(deferred + 1);
4109 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4110 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4111 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4112
4113 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4114 deferred->buffer_bind_count = submission->buffer_bind_count;
4115 memcpy(deferred->buffer_binds, submission->buffer_binds,
4116 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4117
4118 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4119 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4120 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4121 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4122
4123 deferred->flush_caches = submission->flush_caches;
4124 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4125
4126 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4127 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4128
4129 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4130 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4131
4132 deferred->fence = submission->fence;
4133
4134 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4135 deferred->temporary_semaphore_part_count = temporary_count;
4136
4137 uint32_t temporary_idx = 0;
4138 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4139 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4140 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4141 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4142 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4143 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4144 ++temporary_idx;
4145 } else
4146 deferred->wait_semaphores[i] = &semaphore->permanent;
4147 }
4148
4149 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4150 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4151 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4152 deferred->signal_semaphores[i] = &semaphore->temporary;
4153 } else {
4154 deferred->signal_semaphores[i] = &semaphore->permanent;
4155 }
4156 }
4157
4158 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4159 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4160 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4161 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4162
4163 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4164 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4165 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4166 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4167
4168 *out = deferred;
4169 return VK_SUCCESS;
4170 }
4171
4172 static void
4173 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4174 struct list_head *processing_list)
4175 {
4176 uint32_t wait_cnt = 0;
4177 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4178 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4179 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4180 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4181 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4182 ++wait_cnt;
4183 waiter->value = submission->wait_values[i];
4184 waiter->submission = submission;
4185 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4186 ++waiter;
4187 }
4188 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4189 }
4190 }
4191
4192 pthread_mutex_lock(&submission->queue->pending_mutex);
4193
4194 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4195 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4196
4197 pthread_mutex_unlock(&submission->queue->pending_mutex);
4198
4199 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4200 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4201 * submission. */
4202 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4203 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4204 list_addtail(&submission->processing_list, processing_list);
4205 }
4206 }
4207
4208 static void
4209 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4210 struct list_head *processing_list)
4211 {
4212 pthread_mutex_lock(&submission->queue->pending_mutex);
4213 list_del(&submission->queue_pending_list);
4214
4215 /* trigger the next submission in the queue. */
4216 if (!list_is_empty(&submission->queue->pending_submissions)) {
4217 struct radv_deferred_queue_submission *next_submission =
4218 list_first_entry(&submission->queue->pending_submissions,
4219 struct radv_deferred_queue_submission,
4220 queue_pending_list);
4221 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4222 list_addtail(&next_submission->processing_list, processing_list);
4223 }
4224 }
4225 pthread_mutex_unlock(&submission->queue->pending_mutex);
4226
4227 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4228 }
4229
4230 static VkResult
4231 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4232 struct list_head *processing_list)
4233 {
4234 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4235 struct radv_queue *queue = submission->queue;
4236 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4237 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4238 struct radeon_winsys_fence *base_fence = NULL;
4239 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4240 bool can_patch = true;
4241 uint32_t advance;
4242 struct radv_winsys_sem_info sem_info;
4243 VkResult result;
4244 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4245 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4246 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4247
4248 if (fence) {
4249 /* Under most circumstances, out fences won't be temporary.
4250 * However, the spec does allow it for opaque_fd.
4251 *
4252 * From the Vulkan 1.0.53 spec:
4253 *
4254 * "If the import is temporary, the implementation must
4255 * restore the semaphore to its prior permanent state after
4256 * submitting the next semaphore wait operation."
4257 */
4258 struct radv_fence_part *part =
4259 fence->temporary.kind != RADV_FENCE_NONE ?
4260 &fence->temporary : &fence->permanent;
4261 if (part->kind == RADV_FENCE_WINSYS)
4262 base_fence = part->fence;
4263 }
4264
4265 result = radv_get_preambles(queue, submission->cmd_buffers,
4266 submission->cmd_buffer_count,
4267 &initial_preamble_cs,
4268 &initial_flush_preamble_cs,
4269 &continue_preamble_cs);
4270 if (result != VK_SUCCESS)
4271 goto fail;
4272
4273 result = radv_alloc_sem_info(queue->device,
4274 &sem_info,
4275 submission->wait_semaphore_count,
4276 submission->wait_semaphores,
4277 submission->wait_values,
4278 submission->signal_semaphore_count,
4279 submission->signal_semaphores,
4280 submission->signal_values,
4281 submission->fence);
4282 if (result != VK_SUCCESS)
4283 goto fail;
4284
4285 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4286 radv_sparse_buffer_bind_memory(queue->device,
4287 submission->buffer_binds + i);
4288 }
4289
4290 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4291 radv_sparse_image_opaque_bind_memory(queue->device,
4292 submission->image_opaque_binds + i);
4293 }
4294
4295 if (!submission->cmd_buffer_count) {
4296 result = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4297 &queue->device->empty_cs[queue->queue_family_index],
4298 1, NULL, NULL,
4299 &sem_info, NULL,
4300 false, base_fence);
4301 if (result != VK_SUCCESS)
4302 goto fail;
4303 } else {
4304 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4305 (submission->cmd_buffer_count));
4306
4307 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4308 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4309 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4310
4311 cs_array[j] = cmd_buffer->cs;
4312 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4313 can_patch = false;
4314
4315 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4316 }
4317
4318 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4319 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4320 const struct radv_winsys_bo_list *bo_list = NULL;
4321
4322 advance = MIN2(max_cs_submission,
4323 submission->cmd_buffer_count - j);
4324
4325 if (queue->device->trace_bo)
4326 *queue->device->trace_id_ptr = 0;
4327
4328 sem_info.cs_emit_wait = j == 0;
4329 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4330
4331 if (unlikely(queue->device->use_global_bo_list)) {
4332 pthread_mutex_lock(&queue->device->bo_list.mutex);
4333 bo_list = &queue->device->bo_list.list;
4334 }
4335
4336 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4337 advance, initial_preamble, continue_preamble_cs,
4338 &sem_info, bo_list,
4339 can_patch, base_fence);
4340
4341 if (unlikely(queue->device->use_global_bo_list))
4342 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4343
4344 if (result != VK_SUCCESS)
4345 goto fail;
4346
4347 if (queue->device->trace_bo) {
4348 radv_check_gpu_hangs(queue, cs_array[j]);
4349 }
4350 }
4351
4352 free(cs_array);
4353 }
4354
4355 radv_free_temp_syncobjs(queue->device,
4356 submission->temporary_semaphore_part_count,
4357 submission->temporary_semaphore_parts);
4358 radv_finalize_timelines(queue->device,
4359 submission->wait_semaphore_count,
4360 submission->wait_semaphores,
4361 submission->wait_values,
4362 submission->signal_semaphore_count,
4363 submission->signal_semaphores,
4364 submission->signal_values,
4365 processing_list);
4366 /* Has to happen after timeline finalization to make sure the
4367 * condition variable is only triggered when timelines and queue have
4368 * been updated. */
4369 radv_queue_submission_update_queue(submission, processing_list);
4370 radv_free_sem_info(&sem_info);
4371 free(submission);
4372 return VK_SUCCESS;
4373
4374 fail:
4375 if (result != VK_SUCCESS && result != VK_ERROR_DEVICE_LOST) {
4376 /* When something bad happened during the submission, such as
4377 * an out of memory issue, it might be hard to recover from
4378 * this inconsistent state. To avoid this sort of problem, we
4379 * assume that we are in a really bad situation and return
4380 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4381 * to submit the same job again to this device.
4382 */
4383 result = VK_ERROR_DEVICE_LOST;
4384 }
4385
4386 radv_free_temp_syncobjs(queue->device,
4387 submission->temporary_semaphore_part_count,
4388 submission->temporary_semaphore_parts);
4389 free(submission);
4390 return result;
4391 }
4392
4393 static VkResult
4394 radv_process_submissions(struct list_head *processing_list)
4395 {
4396 while(!list_is_empty(processing_list)) {
4397 struct radv_deferred_queue_submission *submission =
4398 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4399 list_del(&submission->processing_list);
4400
4401 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4402 if (result != VK_SUCCESS)
4403 return result;
4404 }
4405 return VK_SUCCESS;
4406 }
4407
4408 static VkResult radv_queue_submit(struct radv_queue *queue,
4409 const struct radv_queue_submission *submission)
4410 {
4411 struct radv_deferred_queue_submission *deferred = NULL;
4412
4413 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4414 if (result != VK_SUCCESS)
4415 return result;
4416
4417 struct list_head processing_list;
4418 list_inithead(&processing_list);
4419
4420 radv_queue_enqueue_submission(deferred, &processing_list);
4421 return radv_process_submissions(&processing_list);
4422 }
4423
4424 bool
4425 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4426 {
4427 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4428 struct radv_winsys_sem_info sem_info;
4429 VkResult result;
4430
4431 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4432 0, NULL, VK_NULL_HANDLE);
4433 if (result != VK_SUCCESS)
4434 return false;
4435
4436 result = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1,
4437 NULL, NULL, &sem_info, NULL,
4438 false, NULL);
4439 radv_free_sem_info(&sem_info);
4440 if (result != VK_SUCCESS)
4441 return false;
4442
4443 return true;
4444
4445 }
4446
4447 /* Signals fence as soon as all the work currently put on queue is done. */
4448 static VkResult radv_signal_fence(struct radv_queue *queue,
4449 VkFence fence)
4450 {
4451 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4452 .fence = fence
4453 });
4454 }
4455
4456 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4457 {
4458 return info->commandBufferCount ||
4459 info->waitSemaphoreCount ||
4460 info->signalSemaphoreCount;
4461 }
4462
4463 VkResult radv_QueueSubmit(
4464 VkQueue _queue,
4465 uint32_t submitCount,
4466 const VkSubmitInfo* pSubmits,
4467 VkFence fence)
4468 {
4469 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4470 VkResult result;
4471 uint32_t fence_idx = 0;
4472 bool flushed_caches = false;
4473
4474 if (fence != VK_NULL_HANDLE) {
4475 for (uint32_t i = 0; i < submitCount; ++i)
4476 if (radv_submit_has_effects(pSubmits + i))
4477 fence_idx = i;
4478 } else
4479 fence_idx = UINT32_MAX;
4480
4481 for (uint32_t i = 0; i < submitCount; i++) {
4482 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4483 continue;
4484
4485 VkPipelineStageFlags wait_dst_stage_mask = 0;
4486 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4487 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4488 }
4489
4490 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4491 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4492
4493 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4494 .cmd_buffers = pSubmits[i].pCommandBuffers,
4495 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4496 .wait_dst_stage_mask = wait_dst_stage_mask,
4497 .flush_caches = !flushed_caches,
4498 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4499 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4500 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4501 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4502 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4503 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4504 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4505 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4506 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4507 });
4508 if (result != VK_SUCCESS)
4509 return result;
4510
4511 flushed_caches = true;
4512 }
4513
4514 if (fence != VK_NULL_HANDLE && !submitCount) {
4515 result = radv_signal_fence(queue, fence);
4516 if (result != VK_SUCCESS)
4517 return result;
4518 }
4519
4520 return VK_SUCCESS;
4521 }
4522
4523 VkResult radv_QueueWaitIdle(
4524 VkQueue _queue)
4525 {
4526 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4527
4528 pthread_mutex_lock(&queue->pending_mutex);
4529 while (!list_is_empty(&queue->pending_submissions)) {
4530 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4531 }
4532 pthread_mutex_unlock(&queue->pending_mutex);
4533
4534 if (!queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4535 radv_queue_family_to_ring(queue->queue_family_index),
4536 queue->queue_idx))
4537 return VK_ERROR_DEVICE_LOST;
4538
4539 return VK_SUCCESS;
4540 }
4541
4542 VkResult radv_DeviceWaitIdle(
4543 VkDevice _device)
4544 {
4545 RADV_FROM_HANDLE(radv_device, device, _device);
4546
4547 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4548 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4549 VkResult result =
4550 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4551
4552 if (result != VK_SUCCESS)
4553 return result;
4554 }
4555 }
4556 return VK_SUCCESS;
4557 }
4558
4559 VkResult radv_EnumerateInstanceExtensionProperties(
4560 const char* pLayerName,
4561 uint32_t* pPropertyCount,
4562 VkExtensionProperties* pProperties)
4563 {
4564 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4565
4566 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4567 if (radv_instance_extensions_supported.extensions[i]) {
4568 vk_outarray_append(&out, prop) {
4569 *prop = radv_instance_extensions[i];
4570 }
4571 }
4572 }
4573
4574 return vk_outarray_status(&out);
4575 }
4576
4577 VkResult radv_EnumerateDeviceExtensionProperties(
4578 VkPhysicalDevice physicalDevice,
4579 const char* pLayerName,
4580 uint32_t* pPropertyCount,
4581 VkExtensionProperties* pProperties)
4582 {
4583 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4584 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4585
4586 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4587 if (device->supported_extensions.extensions[i]) {
4588 vk_outarray_append(&out, prop) {
4589 *prop = radv_device_extensions[i];
4590 }
4591 }
4592 }
4593
4594 return vk_outarray_status(&out);
4595 }
4596
4597 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4598 VkInstance _instance,
4599 const char* pName)
4600 {
4601 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4602
4603 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4604 * when we have to return valid function pointers, NULL, or it's left
4605 * undefined. See the table for exact details.
4606 */
4607 if (pName == NULL)
4608 return NULL;
4609
4610 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4611 if (strcmp(pName, "vk" #entrypoint) == 0) \
4612 return (PFN_vkVoidFunction)radv_##entrypoint
4613
4614 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4615 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4616 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4617 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4618
4619 /* GetInstanceProcAddr() can also be called with a NULL instance.
4620 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4621 */
4622 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4623
4624 #undef LOOKUP_RADV_ENTRYPOINT
4625
4626 if (instance == NULL)
4627 return NULL;
4628
4629 int idx = radv_get_instance_entrypoint_index(pName);
4630 if (idx >= 0)
4631 return instance->dispatch.entrypoints[idx];
4632
4633 idx = radv_get_physical_device_entrypoint_index(pName);
4634 if (idx >= 0)
4635 return instance->physical_device_dispatch.entrypoints[idx];
4636
4637 idx = radv_get_device_entrypoint_index(pName);
4638 if (idx >= 0)
4639 return instance->device_dispatch.entrypoints[idx];
4640
4641 return NULL;
4642 }
4643
4644 /* The loader wants us to expose a second GetInstanceProcAddr function
4645 * to work around certain LD_PRELOAD issues seen in apps.
4646 */
4647 PUBLIC
4648 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4649 VkInstance instance,
4650 const char* pName);
4651
4652 PUBLIC
4653 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4654 VkInstance instance,
4655 const char* pName)
4656 {
4657 return radv_GetInstanceProcAddr(instance, pName);
4658 }
4659
4660 PUBLIC
4661 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4662 VkInstance _instance,
4663 const char* pName);
4664
4665 PUBLIC
4666 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4667 VkInstance _instance,
4668 const char* pName)
4669 {
4670 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4671
4672 if (!pName || !instance)
4673 return NULL;
4674
4675 int idx = radv_get_physical_device_entrypoint_index(pName);
4676 if (idx < 0)
4677 return NULL;
4678
4679 return instance->physical_device_dispatch.entrypoints[idx];
4680 }
4681
4682 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4683 VkDevice _device,
4684 const char* pName)
4685 {
4686 RADV_FROM_HANDLE(radv_device, device, _device);
4687
4688 if (!device || !pName)
4689 return NULL;
4690
4691 int idx = radv_get_device_entrypoint_index(pName);
4692 if (idx < 0)
4693 return NULL;
4694
4695 return device->dispatch.entrypoints[idx];
4696 }
4697
4698 bool radv_get_memory_fd(struct radv_device *device,
4699 struct radv_device_memory *memory,
4700 int *pFD)
4701 {
4702 struct radeon_bo_metadata metadata;
4703
4704 if (memory->image) {
4705 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
4706 radv_init_metadata(device, memory->image, &metadata);
4707 device->ws->buffer_set_metadata(memory->bo, &metadata);
4708 }
4709
4710 return device->ws->buffer_get_fd(device->ws, memory->bo,
4711 pFD);
4712 }
4713
4714
4715 void
4716 radv_free_memory(struct radv_device *device,
4717 const VkAllocationCallbacks* pAllocator,
4718 struct radv_device_memory *mem)
4719 {
4720 if (mem == NULL)
4721 return;
4722
4723 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4724 if (mem->android_hardware_buffer)
4725 AHardwareBuffer_release(mem->android_hardware_buffer);
4726 #endif
4727
4728 if (mem->bo) {
4729 if (device->overallocation_disallowed) {
4730 mtx_lock(&device->overallocation_mutex);
4731 device->allocated_memory_size[mem->heap_index] -= mem->alloc_size;
4732 mtx_unlock(&device->overallocation_mutex);
4733 }
4734
4735 radv_bo_list_remove(device, mem->bo);
4736 device->ws->buffer_destroy(mem->bo);
4737 mem->bo = NULL;
4738 }
4739
4740 vk_object_base_finish(&mem->base);
4741 vk_free2(&device->vk.alloc, pAllocator, mem);
4742 }
4743
4744 static VkResult radv_alloc_memory(struct radv_device *device,
4745 const VkMemoryAllocateInfo* pAllocateInfo,
4746 const VkAllocationCallbacks* pAllocator,
4747 VkDeviceMemory* pMem)
4748 {
4749 struct radv_device_memory *mem;
4750 VkResult result;
4751 enum radeon_bo_domain domain;
4752 uint32_t flags = 0;
4753
4754 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4755
4756 const VkImportMemoryFdInfoKHR *import_info =
4757 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4758 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4759 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4760 const VkExportMemoryAllocateInfo *export_info =
4761 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4762 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4763 vk_find_struct_const(pAllocateInfo->pNext,
4764 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4765 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4766 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4767
4768 const struct wsi_memory_allocate_info *wsi_info =
4769 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4770
4771 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4772 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4773 /* Apparently, this is allowed */
4774 *pMem = VK_NULL_HANDLE;
4775 return VK_SUCCESS;
4776 }
4777
4778 mem = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*mem), 8,
4779 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4780 if (mem == NULL)
4781 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4782
4783 vk_object_base_init(&device->vk, &mem->base,
4784 VK_OBJECT_TYPE_DEVICE_MEMORY);
4785
4786 if (wsi_info && wsi_info->implicit_sync)
4787 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4788
4789 if (dedicate_info) {
4790 mem->image = radv_image_from_handle(dedicate_info->image);
4791 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4792 } else {
4793 mem->image = NULL;
4794 mem->buffer = NULL;
4795 }
4796
4797 float priority_float = 0.5;
4798 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4799 vk_find_struct_const(pAllocateInfo->pNext,
4800 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4801 if (priority_ext)
4802 priority_float = priority_ext->priority;
4803
4804 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4805 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4806
4807 mem->user_ptr = NULL;
4808 mem->bo = NULL;
4809
4810 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4811 mem->android_hardware_buffer = NULL;
4812 #endif
4813
4814 if (ahb_import_info) {
4815 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4816 if (result != VK_SUCCESS)
4817 goto fail;
4818 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4819 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4820 if (result != VK_SUCCESS)
4821 goto fail;
4822 } else if (import_info) {
4823 assert(import_info->handleType ==
4824 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4825 import_info->handleType ==
4826 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4827 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4828 priority, NULL);
4829 if (!mem->bo) {
4830 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4831 goto fail;
4832 } else {
4833 close(import_info->fd);
4834 }
4835 } else if (host_ptr_info) {
4836 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
4837 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
4838 pAllocateInfo->allocationSize,
4839 priority);
4840 if (!mem->bo) {
4841 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4842 goto fail;
4843 } else {
4844 mem->user_ptr = host_ptr_info->pHostPointer;
4845 }
4846 } else {
4847 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
4848 uint32_t heap_index;
4849
4850 heap_index = device->physical_device->memory_properties.memoryTypes[pAllocateInfo->memoryTypeIndex].heapIndex;
4851 domain = device->physical_device->memory_domains[pAllocateInfo->memoryTypeIndex];
4852 flags |= device->physical_device->memory_flags[pAllocateInfo->memoryTypeIndex];
4853
4854 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
4855 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
4856 if (device->use_global_bo_list) {
4857 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
4858 }
4859 }
4860
4861 if (device->overallocation_disallowed) {
4862 uint64_t total_size =
4863 device->physical_device->memory_properties.memoryHeaps[heap_index].size;
4864
4865 mtx_lock(&device->overallocation_mutex);
4866 if (device->allocated_memory_size[heap_index] + alloc_size > total_size) {
4867 mtx_unlock(&device->overallocation_mutex);
4868 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4869 goto fail;
4870 }
4871 device->allocated_memory_size[heap_index] += alloc_size;
4872 mtx_unlock(&device->overallocation_mutex);
4873 }
4874
4875 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
4876 domain, flags, priority);
4877
4878 if (!mem->bo) {
4879 if (device->overallocation_disallowed) {
4880 mtx_lock(&device->overallocation_mutex);
4881 device->allocated_memory_size[heap_index] -= alloc_size;
4882 mtx_unlock(&device->overallocation_mutex);
4883 }
4884 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4885 goto fail;
4886 }
4887
4888 mem->heap_index = heap_index;
4889 mem->alloc_size = alloc_size;
4890 }
4891
4892 if (!wsi_info) {
4893 result = radv_bo_list_add(device, mem->bo);
4894 if (result != VK_SUCCESS)
4895 goto fail;
4896 }
4897
4898 *pMem = radv_device_memory_to_handle(mem);
4899
4900 return VK_SUCCESS;
4901
4902 fail:
4903 radv_free_memory(device, pAllocator,mem);
4904
4905 return result;
4906 }
4907
4908 VkResult radv_AllocateMemory(
4909 VkDevice _device,
4910 const VkMemoryAllocateInfo* pAllocateInfo,
4911 const VkAllocationCallbacks* pAllocator,
4912 VkDeviceMemory* pMem)
4913 {
4914 RADV_FROM_HANDLE(radv_device, device, _device);
4915 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
4916 }
4917
4918 void radv_FreeMemory(
4919 VkDevice _device,
4920 VkDeviceMemory _mem,
4921 const VkAllocationCallbacks* pAllocator)
4922 {
4923 RADV_FROM_HANDLE(radv_device, device, _device);
4924 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
4925
4926 radv_free_memory(device, pAllocator, mem);
4927 }
4928
4929 VkResult radv_MapMemory(
4930 VkDevice _device,
4931 VkDeviceMemory _memory,
4932 VkDeviceSize offset,
4933 VkDeviceSize size,
4934 VkMemoryMapFlags flags,
4935 void** ppData)
4936 {
4937 RADV_FROM_HANDLE(radv_device, device, _device);
4938 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4939
4940 if (mem == NULL) {
4941 *ppData = NULL;
4942 return VK_SUCCESS;
4943 }
4944
4945 if (mem->user_ptr)
4946 *ppData = mem->user_ptr;
4947 else
4948 *ppData = device->ws->buffer_map(mem->bo);
4949
4950 if (*ppData) {
4951 *ppData += offset;
4952 return VK_SUCCESS;
4953 }
4954
4955 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
4956 }
4957
4958 void radv_UnmapMemory(
4959 VkDevice _device,
4960 VkDeviceMemory _memory)
4961 {
4962 RADV_FROM_HANDLE(radv_device, device, _device);
4963 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4964
4965 if (mem == NULL)
4966 return;
4967
4968 if (mem->user_ptr == NULL)
4969 device->ws->buffer_unmap(mem->bo);
4970 }
4971
4972 VkResult radv_FlushMappedMemoryRanges(
4973 VkDevice _device,
4974 uint32_t memoryRangeCount,
4975 const VkMappedMemoryRange* pMemoryRanges)
4976 {
4977 return VK_SUCCESS;
4978 }
4979
4980 VkResult radv_InvalidateMappedMemoryRanges(
4981 VkDevice _device,
4982 uint32_t memoryRangeCount,
4983 const VkMappedMemoryRange* pMemoryRanges)
4984 {
4985 return VK_SUCCESS;
4986 }
4987
4988 void radv_GetBufferMemoryRequirements(
4989 VkDevice _device,
4990 VkBuffer _buffer,
4991 VkMemoryRequirements* pMemoryRequirements)
4992 {
4993 RADV_FROM_HANDLE(radv_device, device, _device);
4994 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4995
4996 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4997
4998 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4999 pMemoryRequirements->alignment = 4096;
5000 else
5001 pMemoryRequirements->alignment = 16;
5002
5003 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5004 }
5005
5006 void radv_GetBufferMemoryRequirements2(
5007 VkDevice device,
5008 const VkBufferMemoryRequirementsInfo2 *pInfo,
5009 VkMemoryRequirements2 *pMemoryRequirements)
5010 {
5011 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5012 &pMemoryRequirements->memoryRequirements);
5013 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5014 switch (ext->sType) {
5015 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5016 VkMemoryDedicatedRequirements *req =
5017 (VkMemoryDedicatedRequirements *) ext;
5018 req->requiresDedicatedAllocation = false;
5019 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5020 break;
5021 }
5022 default:
5023 break;
5024 }
5025 }
5026 }
5027
5028 void radv_GetImageMemoryRequirements(
5029 VkDevice _device,
5030 VkImage _image,
5031 VkMemoryRequirements* pMemoryRequirements)
5032 {
5033 RADV_FROM_HANDLE(radv_device, device, _device);
5034 RADV_FROM_HANDLE(radv_image, image, _image);
5035
5036 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5037
5038 pMemoryRequirements->size = image->size;
5039 pMemoryRequirements->alignment = image->alignment;
5040 }
5041
5042 void radv_GetImageMemoryRequirements2(
5043 VkDevice device,
5044 const VkImageMemoryRequirementsInfo2 *pInfo,
5045 VkMemoryRequirements2 *pMemoryRequirements)
5046 {
5047 radv_GetImageMemoryRequirements(device, pInfo->image,
5048 &pMemoryRequirements->memoryRequirements);
5049
5050 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5051
5052 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5053 switch (ext->sType) {
5054 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5055 VkMemoryDedicatedRequirements *req =
5056 (VkMemoryDedicatedRequirements *) ext;
5057 req->requiresDedicatedAllocation = image->shareable &&
5058 image->tiling != VK_IMAGE_TILING_LINEAR;
5059 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5060 break;
5061 }
5062 default:
5063 break;
5064 }
5065 }
5066 }
5067
5068 void radv_GetImageSparseMemoryRequirements(
5069 VkDevice device,
5070 VkImage image,
5071 uint32_t* pSparseMemoryRequirementCount,
5072 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5073 {
5074 stub();
5075 }
5076
5077 void radv_GetImageSparseMemoryRequirements2(
5078 VkDevice device,
5079 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5080 uint32_t* pSparseMemoryRequirementCount,
5081 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5082 {
5083 stub();
5084 }
5085
5086 void radv_GetDeviceMemoryCommitment(
5087 VkDevice device,
5088 VkDeviceMemory memory,
5089 VkDeviceSize* pCommittedMemoryInBytes)
5090 {
5091 *pCommittedMemoryInBytes = 0;
5092 }
5093
5094 VkResult radv_BindBufferMemory2(VkDevice device,
5095 uint32_t bindInfoCount,
5096 const VkBindBufferMemoryInfo *pBindInfos)
5097 {
5098 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5099 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5100 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5101
5102 if (mem) {
5103 buffer->bo = mem->bo;
5104 buffer->offset = pBindInfos[i].memoryOffset;
5105 } else {
5106 buffer->bo = NULL;
5107 }
5108 }
5109 return VK_SUCCESS;
5110 }
5111
5112 VkResult radv_BindBufferMemory(
5113 VkDevice device,
5114 VkBuffer buffer,
5115 VkDeviceMemory memory,
5116 VkDeviceSize memoryOffset)
5117 {
5118 const VkBindBufferMemoryInfo info = {
5119 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5120 .buffer = buffer,
5121 .memory = memory,
5122 .memoryOffset = memoryOffset
5123 };
5124
5125 return radv_BindBufferMemory2(device, 1, &info);
5126 }
5127
5128 VkResult radv_BindImageMemory2(VkDevice device,
5129 uint32_t bindInfoCount,
5130 const VkBindImageMemoryInfo *pBindInfos)
5131 {
5132 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5133 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5134 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5135
5136 if (mem) {
5137 image->bo = mem->bo;
5138 image->offset = pBindInfos[i].memoryOffset;
5139 } else {
5140 image->bo = NULL;
5141 image->offset = 0;
5142 }
5143 }
5144 return VK_SUCCESS;
5145 }
5146
5147
5148 VkResult radv_BindImageMemory(
5149 VkDevice device,
5150 VkImage image,
5151 VkDeviceMemory memory,
5152 VkDeviceSize memoryOffset)
5153 {
5154 const VkBindImageMemoryInfo info = {
5155 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5156 .image = image,
5157 .memory = memory,
5158 .memoryOffset = memoryOffset
5159 };
5160
5161 return radv_BindImageMemory2(device, 1, &info);
5162 }
5163
5164 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5165 {
5166 return info->bufferBindCount ||
5167 info->imageOpaqueBindCount ||
5168 info->imageBindCount ||
5169 info->waitSemaphoreCount ||
5170 info->signalSemaphoreCount;
5171 }
5172
5173 VkResult radv_QueueBindSparse(
5174 VkQueue _queue,
5175 uint32_t bindInfoCount,
5176 const VkBindSparseInfo* pBindInfo,
5177 VkFence fence)
5178 {
5179 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5180 VkResult result;
5181 uint32_t fence_idx = 0;
5182
5183 if (fence != VK_NULL_HANDLE) {
5184 for (uint32_t i = 0; i < bindInfoCount; ++i)
5185 if (radv_sparse_bind_has_effects(pBindInfo + i))
5186 fence_idx = i;
5187 } else
5188 fence_idx = UINT32_MAX;
5189
5190 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5191 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5192 continue;
5193
5194 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5195 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5196
5197 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5198 .buffer_binds = pBindInfo[i].pBufferBinds,
5199 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5200 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5201 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5202 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5203 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5204 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5205 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5206 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5207 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5208 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5209 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5210 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5211 });
5212
5213 if (result != VK_SUCCESS)
5214 return result;
5215 }
5216
5217 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5218 result = radv_signal_fence(queue, fence);
5219 if (result != VK_SUCCESS)
5220 return result;
5221 }
5222
5223 return VK_SUCCESS;
5224 }
5225
5226 static void
5227 radv_destroy_fence_part(struct radv_device *device,
5228 struct radv_fence_part *part)
5229 {
5230 switch (part->kind) {
5231 case RADV_FENCE_NONE:
5232 break;
5233 case RADV_FENCE_WINSYS:
5234 device->ws->destroy_fence(part->fence);
5235 break;
5236 case RADV_FENCE_SYNCOBJ:
5237 device->ws->destroy_syncobj(device->ws, part->syncobj);
5238 break;
5239 case RADV_FENCE_WSI:
5240 part->fence_wsi->destroy(part->fence_wsi);
5241 break;
5242 default:
5243 unreachable("Invalid fence type");
5244 }
5245
5246 part->kind = RADV_FENCE_NONE;
5247 }
5248
5249 static void
5250 radv_destroy_fence(struct radv_device *device,
5251 const VkAllocationCallbacks *pAllocator,
5252 struct radv_fence *fence)
5253 {
5254 radv_destroy_fence_part(device, &fence->temporary);
5255 radv_destroy_fence_part(device, &fence->permanent);
5256
5257 vk_object_base_finish(&fence->base);
5258 vk_free2(&device->vk.alloc, pAllocator, fence);
5259 }
5260
5261 VkResult radv_CreateFence(
5262 VkDevice _device,
5263 const VkFenceCreateInfo* pCreateInfo,
5264 const VkAllocationCallbacks* pAllocator,
5265 VkFence* pFence)
5266 {
5267 RADV_FROM_HANDLE(radv_device, device, _device);
5268 const VkExportFenceCreateInfo *export =
5269 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5270 VkExternalFenceHandleTypeFlags handleTypes =
5271 export ? export->handleTypes : 0;
5272 struct radv_fence *fence;
5273
5274 fence = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*fence), 8,
5275 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5276 if (!fence)
5277 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5278
5279 vk_object_base_init(&device->vk, &fence->base, VK_OBJECT_TYPE_FENCE);
5280
5281 if (device->always_use_syncobj || handleTypes) {
5282 fence->permanent.kind = RADV_FENCE_SYNCOBJ;
5283
5284 bool create_signaled = false;
5285 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5286 create_signaled = true;
5287
5288 int ret = device->ws->create_syncobj(device->ws, create_signaled,
5289 &fence->permanent.syncobj);
5290 if (ret) {
5291 radv_destroy_fence(device, pAllocator, fence);
5292 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5293 }
5294 } else {
5295 fence->permanent.kind = RADV_FENCE_WINSYS;
5296
5297 fence->permanent.fence = device->ws->create_fence();
5298 if (!fence->permanent.fence) {
5299 vk_free2(&device->vk.alloc, pAllocator, fence);
5300 radv_destroy_fence(device, pAllocator, fence);
5301 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5302 }
5303 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5304 device->ws->signal_fence(fence->permanent.fence);
5305 }
5306
5307 *pFence = radv_fence_to_handle(fence);
5308
5309 return VK_SUCCESS;
5310 }
5311
5312
5313 void radv_DestroyFence(
5314 VkDevice _device,
5315 VkFence _fence,
5316 const VkAllocationCallbacks* pAllocator)
5317 {
5318 RADV_FROM_HANDLE(radv_device, device, _device);
5319 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5320
5321 if (!fence)
5322 return;
5323
5324 radv_destroy_fence(device, pAllocator, fence);
5325 }
5326
5327
5328 uint64_t radv_get_current_time(void)
5329 {
5330 struct timespec tv;
5331 clock_gettime(CLOCK_MONOTONIC, &tv);
5332 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5333 }
5334
5335 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5336 {
5337 uint64_t current_time = radv_get_current_time();
5338
5339 timeout = MIN2(UINT64_MAX - current_time, timeout);
5340
5341 return current_time + timeout;
5342 }
5343
5344
5345 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5346 uint32_t fenceCount, const VkFence *pFences)
5347 {
5348 for (uint32_t i = 0; i < fenceCount; ++i) {
5349 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5350
5351 struct radv_fence_part *part =
5352 fence->temporary.kind != RADV_FENCE_NONE ?
5353 &fence->temporary : &fence->permanent;
5354 if (part->kind != RADV_FENCE_WINSYS ||
5355 !device->ws->is_fence_waitable(part->fence))
5356 return false;
5357 }
5358 return true;
5359 }
5360
5361 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5362 {
5363 for (uint32_t i = 0; i < fenceCount; ++i) {
5364 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5365
5366 struct radv_fence_part *part =
5367 fence->temporary.kind != RADV_FENCE_NONE ?
5368 &fence->temporary : &fence->permanent;
5369 if (part->kind != RADV_FENCE_SYNCOBJ)
5370 return false;
5371 }
5372 return true;
5373 }
5374
5375 VkResult radv_WaitForFences(
5376 VkDevice _device,
5377 uint32_t fenceCount,
5378 const VkFence* pFences,
5379 VkBool32 waitAll,
5380 uint64_t timeout)
5381 {
5382 RADV_FROM_HANDLE(radv_device, device, _device);
5383 timeout = radv_get_absolute_timeout(timeout);
5384
5385 if (device->always_use_syncobj &&
5386 radv_all_fences_syncobj(fenceCount, pFences))
5387 {
5388 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5389 if (!handles)
5390 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5391
5392 for (uint32_t i = 0; i < fenceCount; ++i) {
5393 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5394
5395 struct radv_fence_part *part =
5396 fence->temporary.kind != RADV_FENCE_NONE ?
5397 &fence->temporary : &fence->permanent;
5398
5399 assert(part->kind == RADV_FENCE_SYNCOBJ);
5400 handles[i] = part->syncobj;
5401 }
5402
5403 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5404
5405 free(handles);
5406 return success ? VK_SUCCESS : VK_TIMEOUT;
5407 }
5408
5409 if (!waitAll && fenceCount > 1) {
5410 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5411 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5412 uint32_t wait_count = 0;
5413 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5414 if (!fences)
5415 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5416
5417 for (uint32_t i = 0; i < fenceCount; ++i) {
5418 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5419
5420 struct radv_fence_part *part =
5421 fence->temporary.kind != RADV_FENCE_NONE ?
5422 &fence->temporary : &fence->permanent;
5423 assert(part->kind == RADV_FENCE_WINSYS);
5424
5425 if (device->ws->fence_wait(device->ws, part->fence, false, 0)) {
5426 free(fences);
5427 return VK_SUCCESS;
5428 }
5429
5430 fences[wait_count++] = part->fence;
5431 }
5432
5433 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5434 waitAll, timeout - radv_get_current_time());
5435
5436 free(fences);
5437 return success ? VK_SUCCESS : VK_TIMEOUT;
5438 }
5439
5440 while(radv_get_current_time() <= timeout) {
5441 for (uint32_t i = 0; i < fenceCount; ++i) {
5442 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5443 return VK_SUCCESS;
5444 }
5445 }
5446 return VK_TIMEOUT;
5447 }
5448
5449 for (uint32_t i = 0; i < fenceCount; ++i) {
5450 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5451 bool expired = false;
5452
5453 struct radv_fence_part *part =
5454 fence->temporary.kind != RADV_FENCE_NONE ?
5455 &fence->temporary : &fence->permanent;
5456
5457 switch (part->kind) {
5458 case RADV_FENCE_NONE:
5459 break;
5460 case RADV_FENCE_WINSYS:
5461 if (!device->ws->is_fence_waitable(part->fence)) {
5462 while (!device->ws->is_fence_waitable(part->fence) &&
5463 radv_get_current_time() <= timeout)
5464 /* Do nothing */;
5465 }
5466
5467 expired = device->ws->fence_wait(device->ws,
5468 part->fence,
5469 true, timeout);
5470 if (!expired)
5471 return VK_TIMEOUT;
5472 break;
5473 case RADV_FENCE_SYNCOBJ:
5474 if (!device->ws->wait_syncobj(device->ws,
5475 &part->syncobj, 1, true,
5476 timeout))
5477 return VK_TIMEOUT;
5478 break;
5479 case RADV_FENCE_WSI: {
5480 VkResult result = part->fence_wsi->wait(part->fence_wsi, timeout);
5481 if (result != VK_SUCCESS)
5482 return result;
5483 break;
5484 }
5485 default:
5486 unreachable("Invalid fence type");
5487 }
5488 }
5489
5490 return VK_SUCCESS;
5491 }
5492
5493 VkResult radv_ResetFences(VkDevice _device,
5494 uint32_t fenceCount,
5495 const VkFence *pFences)
5496 {
5497 RADV_FROM_HANDLE(radv_device, device, _device);
5498
5499 for (unsigned i = 0; i < fenceCount; ++i) {
5500 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5501
5502 /* From the Vulkan 1.0.53 spec:
5503 *
5504 * "If any member of pFences currently has its payload
5505 * imported with temporary permanence, that fence’s prior
5506 * permanent payload is irst restored. The remaining
5507 * operations described therefore operate on the restored
5508 * payload."
5509 */
5510 if (fence->temporary.kind != RADV_FENCE_NONE)
5511 radv_destroy_fence_part(device, &fence->temporary);
5512
5513 struct radv_fence_part *part = &fence->permanent;
5514
5515 switch (part->kind) {
5516 case RADV_FENCE_WSI:
5517 device->ws->reset_fence(part->fence);
5518 break;
5519 case RADV_FENCE_SYNCOBJ:
5520 device->ws->reset_syncobj(device->ws, part->syncobj);
5521 break;
5522 default:
5523 unreachable("Invalid fence type");
5524 }
5525 }
5526
5527 return VK_SUCCESS;
5528 }
5529
5530 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5531 {
5532 RADV_FROM_HANDLE(radv_device, device, _device);
5533 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5534
5535 struct radv_fence_part *part =
5536 fence->temporary.kind != RADV_FENCE_NONE ?
5537 &fence->temporary : &fence->permanent;
5538
5539 switch (part->kind) {
5540 case RADV_FENCE_NONE:
5541 break;
5542 case RADV_FENCE_WINSYS:
5543 if (!device->ws->fence_wait(device->ws, part->fence, false, 0))
5544 return VK_NOT_READY;
5545 break;
5546 case RADV_FENCE_SYNCOBJ: {
5547 bool success = device->ws->wait_syncobj(device->ws,
5548 &part->syncobj, 1, true, 0);
5549 if (!success)
5550 return VK_NOT_READY;
5551 break;
5552 }
5553 case RADV_FENCE_WSI: {
5554 VkResult result = part->fence_wsi->wait(part->fence_wsi, 0);
5555 if (result != VK_SUCCESS) {
5556 if (result == VK_TIMEOUT)
5557 return VK_NOT_READY;
5558 return result;
5559 }
5560 break;
5561 }
5562 default:
5563 unreachable("Invalid fence type");
5564 }
5565
5566 return VK_SUCCESS;
5567 }
5568
5569
5570 // Queue semaphore functions
5571
5572 static void
5573 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5574 {
5575 timeline->highest_signaled = value;
5576 timeline->highest_submitted = value;
5577 list_inithead(&timeline->points);
5578 list_inithead(&timeline->free_points);
5579 list_inithead(&timeline->waiters);
5580 pthread_mutex_init(&timeline->mutex, NULL);
5581 }
5582
5583 static void
5584 radv_destroy_timeline(struct radv_device *device,
5585 struct radv_timeline *timeline)
5586 {
5587 list_for_each_entry_safe(struct radv_timeline_point, point,
5588 &timeline->free_points, list) {
5589 list_del(&point->list);
5590 device->ws->destroy_syncobj(device->ws, point->syncobj);
5591 free(point);
5592 }
5593 list_for_each_entry_safe(struct radv_timeline_point, point,
5594 &timeline->points, list) {
5595 list_del(&point->list);
5596 device->ws->destroy_syncobj(device->ws, point->syncobj);
5597 free(point);
5598 }
5599 pthread_mutex_destroy(&timeline->mutex);
5600 }
5601
5602 static void
5603 radv_timeline_gc_locked(struct radv_device *device,
5604 struct radv_timeline *timeline)
5605 {
5606 list_for_each_entry_safe(struct radv_timeline_point, point,
5607 &timeline->points, list) {
5608 if (point->wait_count || point->value > timeline->highest_submitted)
5609 return;
5610
5611 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5612 timeline->highest_signaled = point->value;
5613 list_del(&point->list);
5614 list_add(&point->list, &timeline->free_points);
5615 }
5616 }
5617 }
5618
5619 static struct radv_timeline_point *
5620 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5621 struct radv_timeline *timeline,
5622 uint64_t p)
5623 {
5624 radv_timeline_gc_locked(device, timeline);
5625
5626 if (p <= timeline->highest_signaled)
5627 return NULL;
5628
5629 list_for_each_entry(struct radv_timeline_point, point,
5630 &timeline->points, list) {
5631 if (point->value >= p) {
5632 ++point->wait_count;
5633 return point;
5634 }
5635 }
5636 return NULL;
5637 }
5638
5639 static struct radv_timeline_point *
5640 radv_timeline_add_point_locked(struct radv_device *device,
5641 struct radv_timeline *timeline,
5642 uint64_t p)
5643 {
5644 radv_timeline_gc_locked(device, timeline);
5645
5646 struct radv_timeline_point *ret = NULL;
5647 struct radv_timeline_point *prev = NULL;
5648 int r;
5649
5650 if (p <= timeline->highest_signaled)
5651 return NULL;
5652
5653 list_for_each_entry(struct radv_timeline_point, point,
5654 &timeline->points, list) {
5655 if (point->value == p) {
5656 return NULL;
5657 }
5658
5659 if (point->value < p)
5660 prev = point;
5661 }
5662
5663 if (list_is_empty(&timeline->free_points)) {
5664 ret = malloc(sizeof(struct radv_timeline_point));
5665 r = device->ws->create_syncobj(device->ws, false, &ret->syncobj);
5666 if (r) {
5667 free(ret);
5668 return NULL;
5669 }
5670 } else {
5671 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5672 list_del(&ret->list);
5673
5674 device->ws->reset_syncobj(device->ws, ret->syncobj);
5675 }
5676
5677 ret->value = p;
5678 ret->wait_count = 1;
5679
5680 if (prev) {
5681 list_add(&ret->list, &prev->list);
5682 } else {
5683 list_addtail(&ret->list, &timeline->points);
5684 }
5685 return ret;
5686 }
5687
5688
5689 static VkResult
5690 radv_timeline_wait_locked(struct radv_device *device,
5691 struct radv_timeline *timeline,
5692 uint64_t value,
5693 uint64_t abs_timeout)
5694 {
5695 while(timeline->highest_submitted < value) {
5696 struct timespec abstime;
5697 timespec_from_nsec(&abstime, abs_timeout);
5698
5699 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5700
5701 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5702 return VK_TIMEOUT;
5703 }
5704
5705 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5706 if (!point)
5707 return VK_SUCCESS;
5708
5709 pthread_mutex_unlock(&timeline->mutex);
5710
5711 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5712
5713 pthread_mutex_lock(&timeline->mutex);
5714 point->wait_count--;
5715 return success ? VK_SUCCESS : VK_TIMEOUT;
5716 }
5717
5718 static void
5719 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5720 struct list_head *processing_list)
5721 {
5722 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5723 &timeline->waiters, list) {
5724 if (waiter->value > timeline->highest_submitted)
5725 continue;
5726
5727 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5728 list_addtail(&waiter->submission->processing_list, processing_list);
5729 }
5730 list_del(&waiter->list);
5731 }
5732 }
5733
5734 static
5735 void radv_destroy_semaphore_part(struct radv_device *device,
5736 struct radv_semaphore_part *part)
5737 {
5738 switch(part->kind) {
5739 case RADV_SEMAPHORE_NONE:
5740 break;
5741 case RADV_SEMAPHORE_WINSYS:
5742 device->ws->destroy_sem(part->ws_sem);
5743 break;
5744 case RADV_SEMAPHORE_TIMELINE:
5745 radv_destroy_timeline(device, &part->timeline);
5746 break;
5747 case RADV_SEMAPHORE_SYNCOBJ:
5748 device->ws->destroy_syncobj(device->ws, part->syncobj);
5749 break;
5750 }
5751 part->kind = RADV_SEMAPHORE_NONE;
5752 }
5753
5754 static VkSemaphoreTypeKHR
5755 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5756 {
5757 const VkSemaphoreTypeCreateInfo *type_info =
5758 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
5759
5760 if (!type_info)
5761 return VK_SEMAPHORE_TYPE_BINARY;
5762
5763 if (initial_value)
5764 *initial_value = type_info->initialValue;
5765 return type_info->semaphoreType;
5766 }
5767
5768 static void
5769 radv_destroy_semaphore(struct radv_device *device,
5770 const VkAllocationCallbacks *pAllocator,
5771 struct radv_semaphore *sem)
5772 {
5773 radv_destroy_semaphore_part(device, &sem->temporary);
5774 radv_destroy_semaphore_part(device, &sem->permanent);
5775 vk_object_base_finish(&sem->base);
5776 vk_free2(&device->vk.alloc, pAllocator, sem);
5777 }
5778
5779 VkResult radv_CreateSemaphore(
5780 VkDevice _device,
5781 const VkSemaphoreCreateInfo* pCreateInfo,
5782 const VkAllocationCallbacks* pAllocator,
5783 VkSemaphore* pSemaphore)
5784 {
5785 RADV_FROM_HANDLE(radv_device, device, _device);
5786 const VkExportSemaphoreCreateInfo *export =
5787 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5788 VkExternalSemaphoreHandleTypeFlags handleTypes =
5789 export ? export->handleTypes : 0;
5790 uint64_t initial_value = 0;
5791 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5792
5793 struct radv_semaphore *sem = vk_alloc2(&device->vk.alloc, pAllocator,
5794 sizeof(*sem), 8,
5795 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5796 if (!sem)
5797 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5798
5799 vk_object_base_init(&device->vk, &sem->base,
5800 VK_OBJECT_TYPE_SEMAPHORE);
5801
5802 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5803 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5804
5805 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
5806 radv_create_timeline(&sem->permanent.timeline, initial_value);
5807 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5808 } else if (device->always_use_syncobj || handleTypes) {
5809 assert (device->physical_device->rad_info.has_syncobj);
5810 int ret = device->ws->create_syncobj(device->ws, false,
5811 &sem->permanent.syncobj);
5812 if (ret) {
5813 radv_destroy_semaphore(device, pAllocator, sem);
5814 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5815 }
5816 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5817 } else {
5818 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5819 if (!sem->permanent.ws_sem) {
5820 radv_destroy_semaphore(device, pAllocator, sem);
5821 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5822 }
5823 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5824 }
5825
5826 *pSemaphore = radv_semaphore_to_handle(sem);
5827 return VK_SUCCESS;
5828 }
5829
5830 void radv_DestroySemaphore(
5831 VkDevice _device,
5832 VkSemaphore _semaphore,
5833 const VkAllocationCallbacks* pAllocator)
5834 {
5835 RADV_FROM_HANDLE(radv_device, device, _device);
5836 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5837 if (!_semaphore)
5838 return;
5839
5840 radv_destroy_semaphore(device, pAllocator, sem);
5841 }
5842
5843 VkResult
5844 radv_GetSemaphoreCounterValue(VkDevice _device,
5845 VkSemaphore _semaphore,
5846 uint64_t* pValue)
5847 {
5848 RADV_FROM_HANDLE(radv_device, device, _device);
5849 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5850
5851 struct radv_semaphore_part *part =
5852 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5853
5854 switch (part->kind) {
5855 case RADV_SEMAPHORE_TIMELINE: {
5856 pthread_mutex_lock(&part->timeline.mutex);
5857 radv_timeline_gc_locked(device, &part->timeline);
5858 *pValue = part->timeline.highest_signaled;
5859 pthread_mutex_unlock(&part->timeline.mutex);
5860 return VK_SUCCESS;
5861 }
5862 case RADV_SEMAPHORE_NONE:
5863 case RADV_SEMAPHORE_SYNCOBJ:
5864 case RADV_SEMAPHORE_WINSYS:
5865 unreachable("Invalid semaphore type");
5866 }
5867 unreachable("Unhandled semaphore type");
5868 }
5869
5870
5871 static VkResult
5872 radv_wait_timelines(struct radv_device *device,
5873 const VkSemaphoreWaitInfo* pWaitInfo,
5874 uint64_t abs_timeout)
5875 {
5876 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
5877 for (;;) {
5878 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5879 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5880 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5881 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
5882 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5883
5884 if (result == VK_SUCCESS)
5885 return VK_SUCCESS;
5886 }
5887 if (radv_get_current_time() > abs_timeout)
5888 return VK_TIMEOUT;
5889 }
5890 }
5891
5892 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5893 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5894 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5895 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
5896 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5897
5898 if (result != VK_SUCCESS)
5899 return result;
5900 }
5901 return VK_SUCCESS;
5902 }
5903 VkResult
5904 radv_WaitSemaphores(VkDevice _device,
5905 const VkSemaphoreWaitInfo* pWaitInfo,
5906 uint64_t timeout)
5907 {
5908 RADV_FROM_HANDLE(radv_device, device, _device);
5909 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
5910 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
5911 }
5912
5913 VkResult
5914 radv_SignalSemaphore(VkDevice _device,
5915 const VkSemaphoreSignalInfo* pSignalInfo)
5916 {
5917 RADV_FROM_HANDLE(radv_device, device, _device);
5918 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
5919
5920 struct radv_semaphore_part *part =
5921 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5922
5923 switch(part->kind) {
5924 case RADV_SEMAPHORE_TIMELINE: {
5925 pthread_mutex_lock(&part->timeline.mutex);
5926 radv_timeline_gc_locked(device, &part->timeline);
5927 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
5928 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
5929
5930 struct list_head processing_list;
5931 list_inithead(&processing_list);
5932 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
5933 pthread_mutex_unlock(&part->timeline.mutex);
5934
5935 return radv_process_submissions(&processing_list);
5936 }
5937 case RADV_SEMAPHORE_NONE:
5938 case RADV_SEMAPHORE_SYNCOBJ:
5939 case RADV_SEMAPHORE_WINSYS:
5940 unreachable("Invalid semaphore type");
5941 }
5942 return VK_SUCCESS;
5943 }
5944
5945 static void radv_destroy_event(struct radv_device *device,
5946 const VkAllocationCallbacks* pAllocator,
5947 struct radv_event *event)
5948 {
5949 if (event->bo)
5950 device->ws->buffer_destroy(event->bo);
5951
5952 vk_object_base_finish(&event->base);
5953 vk_free2(&device->vk.alloc, pAllocator, event);
5954 }
5955
5956 VkResult radv_CreateEvent(
5957 VkDevice _device,
5958 const VkEventCreateInfo* pCreateInfo,
5959 const VkAllocationCallbacks* pAllocator,
5960 VkEvent* pEvent)
5961 {
5962 RADV_FROM_HANDLE(radv_device, device, _device);
5963 struct radv_event *event = vk_alloc2(&device->vk.alloc, pAllocator,
5964 sizeof(*event), 8,
5965 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5966
5967 if (!event)
5968 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5969
5970 vk_object_base_init(&device->vk, &event->base, VK_OBJECT_TYPE_EVENT);
5971
5972 event->bo = device->ws->buffer_create(device->ws, 8, 8,
5973 RADEON_DOMAIN_GTT,
5974 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
5975 RADV_BO_PRIORITY_FENCE);
5976 if (!event->bo) {
5977 radv_destroy_event(device, pAllocator, event);
5978 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5979 }
5980
5981 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
5982 if (!event->map) {
5983 radv_destroy_event(device, pAllocator, event);
5984 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5985 }
5986
5987 *pEvent = radv_event_to_handle(event);
5988
5989 return VK_SUCCESS;
5990 }
5991
5992 void radv_DestroyEvent(
5993 VkDevice _device,
5994 VkEvent _event,
5995 const VkAllocationCallbacks* pAllocator)
5996 {
5997 RADV_FROM_HANDLE(radv_device, device, _device);
5998 RADV_FROM_HANDLE(radv_event, event, _event);
5999
6000 if (!event)
6001 return;
6002
6003 radv_destroy_event(device, pAllocator, event);
6004 }
6005
6006 VkResult radv_GetEventStatus(
6007 VkDevice _device,
6008 VkEvent _event)
6009 {
6010 RADV_FROM_HANDLE(radv_event, event, _event);
6011
6012 if (*event->map == 1)
6013 return VK_EVENT_SET;
6014 return VK_EVENT_RESET;
6015 }
6016
6017 VkResult radv_SetEvent(
6018 VkDevice _device,
6019 VkEvent _event)
6020 {
6021 RADV_FROM_HANDLE(radv_event, event, _event);
6022 *event->map = 1;
6023
6024 return VK_SUCCESS;
6025 }
6026
6027 VkResult radv_ResetEvent(
6028 VkDevice _device,
6029 VkEvent _event)
6030 {
6031 RADV_FROM_HANDLE(radv_event, event, _event);
6032 *event->map = 0;
6033
6034 return VK_SUCCESS;
6035 }
6036
6037 static void
6038 radv_destroy_buffer(struct radv_device *device,
6039 const VkAllocationCallbacks *pAllocator,
6040 struct radv_buffer *buffer)
6041 {
6042 if ((buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) && buffer->bo)
6043 device->ws->buffer_destroy(buffer->bo);
6044
6045 vk_object_base_finish(&buffer->base);
6046 vk_free2(&device->vk.alloc, pAllocator, buffer);
6047 }
6048
6049 VkResult radv_CreateBuffer(
6050 VkDevice _device,
6051 const VkBufferCreateInfo* pCreateInfo,
6052 const VkAllocationCallbacks* pAllocator,
6053 VkBuffer* pBuffer)
6054 {
6055 RADV_FROM_HANDLE(radv_device, device, _device);
6056 struct radv_buffer *buffer;
6057
6058 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6059 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6060
6061 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6062
6063 buffer = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*buffer), 8,
6064 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6065 if (buffer == NULL)
6066 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6067
6068 vk_object_base_init(&device->vk, &buffer->base, VK_OBJECT_TYPE_BUFFER);
6069
6070 buffer->size = pCreateInfo->size;
6071 buffer->usage = pCreateInfo->usage;
6072 buffer->bo = NULL;
6073 buffer->offset = 0;
6074 buffer->flags = pCreateInfo->flags;
6075
6076 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6077 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6078
6079 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6080 buffer->bo = device->ws->buffer_create(device->ws,
6081 align64(buffer->size, 4096),
6082 4096, 0, RADEON_FLAG_VIRTUAL,
6083 RADV_BO_PRIORITY_VIRTUAL);
6084 if (!buffer->bo) {
6085 radv_destroy_buffer(device, pAllocator, buffer);
6086 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6087 }
6088 }
6089
6090 *pBuffer = radv_buffer_to_handle(buffer);
6091
6092 return VK_SUCCESS;
6093 }
6094
6095 void radv_DestroyBuffer(
6096 VkDevice _device,
6097 VkBuffer _buffer,
6098 const VkAllocationCallbacks* pAllocator)
6099 {
6100 RADV_FROM_HANDLE(radv_device, device, _device);
6101 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6102
6103 if (!buffer)
6104 return;
6105
6106 radv_destroy_buffer(device, pAllocator, buffer);
6107 }
6108
6109 VkDeviceAddress radv_GetBufferDeviceAddress(
6110 VkDevice device,
6111 const VkBufferDeviceAddressInfo* pInfo)
6112 {
6113 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6114 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6115 }
6116
6117
6118 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6119 const VkBufferDeviceAddressInfo* pInfo)
6120 {
6121 return 0;
6122 }
6123
6124 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6125 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6126 {
6127 return 0;
6128 }
6129
6130 static inline unsigned
6131 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6132 {
6133 if (stencil)
6134 return plane->surface.u.legacy.stencil_tiling_index[level];
6135 else
6136 return plane->surface.u.legacy.tiling_index[level];
6137 }
6138
6139 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6140 {
6141 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6142 }
6143
6144 static uint32_t
6145 radv_init_dcc_control_reg(struct radv_device *device,
6146 struct radv_image_view *iview)
6147 {
6148 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6149 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6150 unsigned max_compressed_block_size;
6151 unsigned independent_128b_blocks;
6152 unsigned independent_64b_blocks;
6153
6154 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6155 return 0;
6156
6157 if (!device->physical_device->rad_info.has_dedicated_vram) {
6158 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6159 * dGPU and 64 for APU because all of our APUs to date use
6160 * DIMMs which have a request granularity size of 64B while all
6161 * other chips have a 32B request size.
6162 */
6163 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6164 }
6165
6166 if (device->physical_device->rad_info.chip_class >= GFX10) {
6167 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6168 independent_64b_blocks = 0;
6169 independent_128b_blocks = 1;
6170 } else {
6171 independent_128b_blocks = 0;
6172
6173 if (iview->image->info.samples > 1) {
6174 if (iview->image->planes[0].surface.bpe == 1)
6175 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6176 else if (iview->image->planes[0].surface.bpe == 2)
6177 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6178 }
6179
6180 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6181 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6182 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6183 /* If this DCC image is potentially going to be used in texture
6184 * fetches, we need some special settings.
6185 */
6186 independent_64b_blocks = 1;
6187 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6188 } else {
6189 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6190 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6191 * big as possible for better compression state.
6192 */
6193 independent_64b_blocks = 0;
6194 max_compressed_block_size = max_uncompressed_block_size;
6195 }
6196 }
6197
6198 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6199 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6200 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6201 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6202 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6203 }
6204
6205 void
6206 radv_initialise_color_surface(struct radv_device *device,
6207 struct radv_color_buffer_info *cb,
6208 struct radv_image_view *iview)
6209 {
6210 const struct vk_format_description *desc;
6211 unsigned ntype, format, swap, endian;
6212 unsigned blend_clamp = 0, blend_bypass = 0;
6213 uint64_t va;
6214 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6215 const struct radeon_surf *surf = &plane->surface;
6216
6217 desc = vk_format_description(iview->vk_format);
6218
6219 memset(cb, 0, sizeof(*cb));
6220
6221 /* Intensity is implemented as Red, so treat it that way. */
6222 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6223
6224 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6225
6226 cb->cb_color_base = va >> 8;
6227
6228 if (device->physical_device->rad_info.chip_class >= GFX9) {
6229 if (device->physical_device->rad_info.chip_class >= GFX10) {
6230 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6231 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6232 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6233 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6234 } else {
6235 struct gfx9_surf_meta_flags meta = {
6236 .rb_aligned = 1,
6237 .pipe_aligned = 1,
6238 };
6239
6240 if (surf->dcc_offset)
6241 meta = surf->u.gfx9.dcc;
6242
6243 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6244 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6245 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6246 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6247 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6248 }
6249
6250 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6251 cb->cb_color_base |= surf->tile_swizzle;
6252 } else {
6253 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6254 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6255
6256 cb->cb_color_base += level_info->offset >> 8;
6257 if (level_info->mode == RADEON_SURF_MODE_2D)
6258 cb->cb_color_base |= surf->tile_swizzle;
6259
6260 pitch_tile_max = level_info->nblk_x / 8 - 1;
6261 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6262 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6263
6264 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6265 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6266 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6267
6268 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6269
6270 if (radv_image_has_fmask(iview->image)) {
6271 if (device->physical_device->rad_info.chip_class >= GFX7)
6272 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6273 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6274 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6275 } else {
6276 /* This must be set for fast clear to work without FMASK. */
6277 if (device->physical_device->rad_info.chip_class >= GFX7)
6278 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6279 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6280 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6281 }
6282 }
6283
6284 /* CMASK variables */
6285 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6286 va += surf->cmask_offset;
6287 cb->cb_color_cmask = va >> 8;
6288
6289 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6290 va += surf->dcc_offset;
6291
6292 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6293 device->physical_device->rad_info.chip_class <= GFX8)
6294 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6295
6296 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6297 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6298
6299 cb->cb_dcc_base = va >> 8;
6300 cb->cb_dcc_base |= dcc_tile_swizzle;
6301
6302 /* GFX10 field has the same base shift as the GFX6 field. */
6303 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6304 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6305 S_028C6C_SLICE_MAX_GFX10(max_slice);
6306
6307 if (iview->image->info.samples > 1) {
6308 unsigned log_samples = util_logbase2(iview->image->info.samples);
6309
6310 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6311 S_028C74_NUM_FRAGMENTS(log_samples);
6312 }
6313
6314 if (radv_image_has_fmask(iview->image)) {
6315 va = radv_buffer_get_va(iview->bo) + iview->image->offset + surf->fmask_offset;
6316 cb->cb_color_fmask = va >> 8;
6317 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6318 } else {
6319 cb->cb_color_fmask = cb->cb_color_base;
6320 }
6321
6322 ntype = radv_translate_color_numformat(iview->vk_format,
6323 desc,
6324 vk_format_get_first_non_void_channel(iview->vk_format));
6325 format = radv_translate_colorformat(iview->vk_format);
6326 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6327 radv_finishme("Illegal color\n");
6328 swap = radv_translate_colorswap(iview->vk_format, false);
6329 endian = radv_colorformat_endian_swap(format);
6330
6331 /* blend clamp should be set for all NORM/SRGB types */
6332 if (ntype == V_028C70_NUMBER_UNORM ||
6333 ntype == V_028C70_NUMBER_SNORM ||
6334 ntype == V_028C70_NUMBER_SRGB)
6335 blend_clamp = 1;
6336
6337 /* set blend bypass according to docs if SINT/UINT or
6338 8/24 COLOR variants */
6339 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6340 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6341 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6342 blend_clamp = 0;
6343 blend_bypass = 1;
6344 }
6345 #if 0
6346 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6347 (format == V_028C70_COLOR_8 ||
6348 format == V_028C70_COLOR_8_8 ||
6349 format == V_028C70_COLOR_8_8_8_8))
6350 ->color_is_int8 = true;
6351 #endif
6352 cb->cb_color_info = S_028C70_FORMAT(format) |
6353 S_028C70_COMP_SWAP(swap) |
6354 S_028C70_BLEND_CLAMP(blend_clamp) |
6355 S_028C70_BLEND_BYPASS(blend_bypass) |
6356 S_028C70_SIMPLE_FLOAT(1) |
6357 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6358 ntype != V_028C70_NUMBER_SNORM &&
6359 ntype != V_028C70_NUMBER_SRGB &&
6360 format != V_028C70_COLOR_8_24 &&
6361 format != V_028C70_COLOR_24_8) |
6362 S_028C70_NUMBER_TYPE(ntype) |
6363 S_028C70_ENDIAN(endian);
6364 if (radv_image_has_fmask(iview->image)) {
6365 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6366 if (device->physical_device->rad_info.chip_class == GFX6) {
6367 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6368 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6369 }
6370
6371 if (radv_image_is_tc_compat_cmask(iview->image)) {
6372 /* Allow the texture block to read FMASK directly
6373 * without decompressing it. This bit must be cleared
6374 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6375 * otherwise the operation doesn't happen.
6376 */
6377 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6378
6379 /* Set CMASK into a tiling format that allows the
6380 * texture block to read it.
6381 */
6382 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6383 }
6384 }
6385
6386 if (radv_image_has_cmask(iview->image) &&
6387 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6388 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6389
6390 if (radv_dcc_enabled(iview->image, iview->base_mip))
6391 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6392
6393 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6394
6395 /* This must be set for fast clear to work without FMASK. */
6396 if (!radv_image_has_fmask(iview->image) &&
6397 device->physical_device->rad_info.chip_class == GFX6) {
6398 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6399 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6400 }
6401
6402 if (device->physical_device->rad_info.chip_class >= GFX9) {
6403 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6404
6405 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6406 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6407 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6408 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6409
6410 if (device->physical_device->rad_info.chip_class >= GFX10) {
6411 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6412
6413 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6414 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6415 S_028EE0_RESOURCE_LEVEL(1);
6416 } else {
6417 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6418 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6419 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6420 }
6421
6422 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6423 S_028C68_MIP0_HEIGHT(height - 1) |
6424 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6425 }
6426 }
6427
6428 static unsigned
6429 radv_calc_decompress_on_z_planes(struct radv_device *device,
6430 struct radv_image_view *iview)
6431 {
6432 unsigned max_zplanes = 0;
6433
6434 assert(radv_image_is_tc_compat_htile(iview->image));
6435
6436 if (device->physical_device->rad_info.chip_class >= GFX9) {
6437 /* Default value for 32-bit depth surfaces. */
6438 max_zplanes = 4;
6439
6440 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6441 iview->image->info.samples > 1)
6442 max_zplanes = 2;
6443
6444 max_zplanes = max_zplanes + 1;
6445 } else {
6446 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6447 /* Do not enable Z plane compression for 16-bit depth
6448 * surfaces because isn't supported on GFX8. Only
6449 * 32-bit depth surfaces are supported by the hardware.
6450 * This allows to maintain shader compatibility and to
6451 * reduce the number of depth decompressions.
6452 */
6453 max_zplanes = 1;
6454 } else {
6455 if (iview->image->info.samples <= 1)
6456 max_zplanes = 5;
6457 else if (iview->image->info.samples <= 4)
6458 max_zplanes = 3;
6459 else
6460 max_zplanes = 2;
6461 }
6462 }
6463
6464 return max_zplanes;
6465 }
6466
6467 void
6468 radv_initialise_ds_surface(struct radv_device *device,
6469 struct radv_ds_buffer_info *ds,
6470 struct radv_image_view *iview)
6471 {
6472 unsigned level = iview->base_mip;
6473 unsigned format, stencil_format;
6474 uint64_t va, s_offs, z_offs;
6475 bool stencil_only = false;
6476 const struct radv_image_plane *plane = &iview->image->planes[0];
6477 const struct radeon_surf *surf = &plane->surface;
6478
6479 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6480
6481 memset(ds, 0, sizeof(*ds));
6482 switch (iview->image->vk_format) {
6483 case VK_FORMAT_D24_UNORM_S8_UINT:
6484 case VK_FORMAT_X8_D24_UNORM_PACK32:
6485 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6486 ds->offset_scale = 2.0f;
6487 break;
6488 case VK_FORMAT_D16_UNORM:
6489 case VK_FORMAT_D16_UNORM_S8_UINT:
6490 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6491 ds->offset_scale = 4.0f;
6492 break;
6493 case VK_FORMAT_D32_SFLOAT:
6494 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6495 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6496 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6497 ds->offset_scale = 1.0f;
6498 break;
6499 case VK_FORMAT_S8_UINT:
6500 stencil_only = true;
6501 break;
6502 default:
6503 break;
6504 }
6505
6506 format = radv_translate_dbformat(iview->image->vk_format);
6507 stencil_format = surf->has_stencil ?
6508 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6509
6510 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6511 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6512 S_028008_SLICE_MAX(max_slice);
6513 if (device->physical_device->rad_info.chip_class >= GFX10) {
6514 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6515 S_028008_SLICE_MAX_HI(max_slice >> 11);
6516 }
6517
6518 ds->db_htile_data_base = 0;
6519 ds->db_htile_surface = 0;
6520
6521 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6522 s_offs = z_offs = va;
6523
6524 if (device->physical_device->rad_info.chip_class >= GFX9) {
6525 assert(surf->u.gfx9.surf_offset == 0);
6526 s_offs += surf->u.gfx9.stencil_offset;
6527
6528 ds->db_z_info = S_028038_FORMAT(format) |
6529 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6530 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6531 S_028038_MAXMIP(iview->image->info.levels - 1) |
6532 S_028038_ZRANGE_PRECISION(1);
6533 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6534 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6535
6536 if (device->physical_device->rad_info.chip_class == GFX9) {
6537 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6538 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6539 }
6540
6541 ds->db_depth_view |= S_028008_MIPID(level);
6542 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6543 S_02801C_Y_MAX(iview->image->info.height - 1);
6544
6545 if (radv_htile_enabled(iview->image, level)) {
6546 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6547
6548 if (radv_image_is_tc_compat_htile(iview->image)) {
6549 unsigned max_zplanes =
6550 radv_calc_decompress_on_z_planes(device, iview);
6551
6552 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6553
6554 if (device->physical_device->rad_info.chip_class >= GFX10) {
6555 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6556 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6557 } else {
6558 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6559 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6560 }
6561 }
6562
6563 if (!surf->has_stencil)
6564 /* Use all of the htile_buffer for depth if there's no stencil. */
6565 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6566 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6567 surf->htile_offset;
6568 ds->db_htile_data_base = va >> 8;
6569 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6570 S_028ABC_PIPE_ALIGNED(1);
6571
6572 if (device->physical_device->rad_info.chip_class == GFX9) {
6573 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(1);
6574 }
6575 }
6576 } else {
6577 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6578
6579 if (stencil_only)
6580 level_info = &surf->u.legacy.stencil_level[level];
6581
6582 z_offs += surf->u.legacy.level[level].offset;
6583 s_offs += surf->u.legacy.stencil_level[level].offset;
6584
6585 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6586 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6587 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6588
6589 if (iview->image->info.samples > 1)
6590 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6591
6592 if (device->physical_device->rad_info.chip_class >= GFX7) {
6593 struct radeon_info *info = &device->physical_device->rad_info;
6594 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6595 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6596 unsigned macro_index = surf->u.legacy.macro_tile_index;
6597 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6598 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6599 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6600
6601 if (stencil_only)
6602 tile_mode = stencil_tile_mode;
6603
6604 ds->db_depth_info |=
6605 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6606 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6607 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6608 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6609 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6610 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6611 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6612 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6613 } else {
6614 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6615 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6616 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6617 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6618 if (stencil_only)
6619 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6620 }
6621
6622 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6623 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6624 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6625
6626 if (radv_htile_enabled(iview->image, level)) {
6627 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6628
6629 if (!surf->has_stencil &&
6630 !radv_image_is_tc_compat_htile(iview->image))
6631 /* Use all of the htile_buffer for depth if there's no stencil. */
6632 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6633
6634 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6635 surf->htile_offset;
6636 ds->db_htile_data_base = va >> 8;
6637 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6638
6639 if (radv_image_is_tc_compat_htile(iview->image)) {
6640 unsigned max_zplanes =
6641 radv_calc_decompress_on_z_planes(device, iview);
6642
6643 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6644 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6645 }
6646 }
6647 }
6648
6649 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6650 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6651 }
6652
6653 VkResult radv_CreateFramebuffer(
6654 VkDevice _device,
6655 const VkFramebufferCreateInfo* pCreateInfo,
6656 const VkAllocationCallbacks* pAllocator,
6657 VkFramebuffer* pFramebuffer)
6658 {
6659 RADV_FROM_HANDLE(radv_device, device, _device);
6660 struct radv_framebuffer *framebuffer;
6661 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6662 vk_find_struct_const(pCreateInfo->pNext,
6663 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6664
6665 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6666
6667 size_t size = sizeof(*framebuffer);
6668 if (!imageless_create_info)
6669 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6670 framebuffer = vk_alloc2(&device->vk.alloc, pAllocator, size, 8,
6671 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6672 if (framebuffer == NULL)
6673 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6674
6675 vk_object_base_init(&device->vk, &framebuffer->base,
6676 VK_OBJECT_TYPE_FRAMEBUFFER);
6677
6678 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6679 framebuffer->width = pCreateInfo->width;
6680 framebuffer->height = pCreateInfo->height;
6681 framebuffer->layers = pCreateInfo->layers;
6682 if (imageless_create_info) {
6683 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6684 const VkFramebufferAttachmentImageInfo *attachment =
6685 imageless_create_info->pAttachmentImageInfos + i;
6686 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6687 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6688 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6689 }
6690 } else {
6691 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6692 VkImageView _iview = pCreateInfo->pAttachments[i];
6693 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6694 framebuffer->attachments[i] = iview;
6695 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6696 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6697 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6698 }
6699 }
6700
6701 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6702 return VK_SUCCESS;
6703 }
6704
6705 void radv_DestroyFramebuffer(
6706 VkDevice _device,
6707 VkFramebuffer _fb,
6708 const VkAllocationCallbacks* pAllocator)
6709 {
6710 RADV_FROM_HANDLE(radv_device, device, _device);
6711 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6712
6713 if (!fb)
6714 return;
6715 vk_object_base_finish(&fb->base);
6716 vk_free2(&device->vk.alloc, pAllocator, fb);
6717 }
6718
6719 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6720 {
6721 switch (address_mode) {
6722 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6723 return V_008F30_SQ_TEX_WRAP;
6724 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6725 return V_008F30_SQ_TEX_MIRROR;
6726 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6727 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6728 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6729 return V_008F30_SQ_TEX_CLAMP_BORDER;
6730 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6731 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6732 default:
6733 unreachable("illegal tex wrap mode");
6734 break;
6735 }
6736 }
6737
6738 static unsigned
6739 radv_tex_compare(VkCompareOp op)
6740 {
6741 switch (op) {
6742 case VK_COMPARE_OP_NEVER:
6743 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6744 case VK_COMPARE_OP_LESS:
6745 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6746 case VK_COMPARE_OP_EQUAL:
6747 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6748 case VK_COMPARE_OP_LESS_OR_EQUAL:
6749 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6750 case VK_COMPARE_OP_GREATER:
6751 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6752 case VK_COMPARE_OP_NOT_EQUAL:
6753 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6754 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6755 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6756 case VK_COMPARE_OP_ALWAYS:
6757 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6758 default:
6759 unreachable("illegal compare mode");
6760 break;
6761 }
6762 }
6763
6764 static unsigned
6765 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6766 {
6767 switch (filter) {
6768 case VK_FILTER_NEAREST:
6769 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6770 V_008F38_SQ_TEX_XY_FILTER_POINT);
6771 case VK_FILTER_LINEAR:
6772 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6773 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6774 case VK_FILTER_CUBIC_IMG:
6775 default:
6776 fprintf(stderr, "illegal texture filter");
6777 return 0;
6778 }
6779 }
6780
6781 static unsigned
6782 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6783 {
6784 switch (mode) {
6785 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6786 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6787 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6788 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6789 default:
6790 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6791 }
6792 }
6793
6794 static unsigned
6795 radv_tex_bordercolor(VkBorderColor bcolor)
6796 {
6797 switch (bcolor) {
6798 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6799 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6800 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6801 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6802 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6803 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6804 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6805 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6806 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6807 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT:
6808 case VK_BORDER_COLOR_INT_CUSTOM_EXT:
6809 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER;
6810 default:
6811 break;
6812 }
6813 return 0;
6814 }
6815
6816 static unsigned
6817 radv_tex_aniso_filter(unsigned filter)
6818 {
6819 if (filter < 2)
6820 return 0;
6821 if (filter < 4)
6822 return 1;
6823 if (filter < 8)
6824 return 2;
6825 if (filter < 16)
6826 return 3;
6827 return 4;
6828 }
6829
6830 static unsigned
6831 radv_tex_filter_mode(VkSamplerReductionMode mode)
6832 {
6833 switch (mode) {
6834 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6835 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6836 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6837 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6838 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6839 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6840 default:
6841 break;
6842 }
6843 return 0;
6844 }
6845
6846 static uint32_t
6847 radv_get_max_anisotropy(struct radv_device *device,
6848 const VkSamplerCreateInfo *pCreateInfo)
6849 {
6850 if (device->force_aniso >= 0)
6851 return device->force_aniso;
6852
6853 if (pCreateInfo->anisotropyEnable &&
6854 pCreateInfo->maxAnisotropy > 1.0f)
6855 return (uint32_t)pCreateInfo->maxAnisotropy;
6856
6857 return 0;
6858 }
6859
6860 static inline int S_FIXED(float value, unsigned frac_bits)
6861 {
6862 return value * (1 << frac_bits);
6863 }
6864
6865 static uint32_t radv_register_border_color(struct radv_device *device,
6866 VkClearColorValue value)
6867 {
6868 uint32_t slot;
6869
6870 pthread_mutex_lock(&device->border_color_data.mutex);
6871
6872 for (slot = 0; slot < RADV_BORDER_COLOR_COUNT; slot++) {
6873 if (!device->border_color_data.used[slot]) {
6874 /* Copy to the GPU wrt endian-ness. */
6875 util_memcpy_cpu_to_le32(&device->border_color_data.colors_gpu_ptr[slot],
6876 &value,
6877 sizeof(VkClearColorValue));
6878
6879 device->border_color_data.used[slot] = true;
6880 break;
6881 }
6882 }
6883
6884 pthread_mutex_unlock(&device->border_color_data.mutex);
6885
6886 return slot;
6887 }
6888
6889 static void radv_unregister_border_color(struct radv_device *device,
6890 uint32_t slot)
6891 {
6892 pthread_mutex_lock(&device->border_color_data.mutex);
6893
6894 device->border_color_data.used[slot] = false;
6895
6896 pthread_mutex_unlock(&device->border_color_data.mutex);
6897 }
6898
6899 static void
6900 radv_init_sampler(struct radv_device *device,
6901 struct radv_sampler *sampler,
6902 const VkSamplerCreateInfo *pCreateInfo)
6903 {
6904 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
6905 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
6906 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
6907 device->physical_device->rad_info.chip_class == GFX9;
6908 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6909 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6910 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
6911 bool uses_border_color = pCreateInfo->addressModeU == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
6912 pCreateInfo->addressModeV == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER ||
6913 pCreateInfo->addressModeW == VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER;
6914 VkBorderColor border_color = uses_border_color ? pCreateInfo->borderColor : VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
6915 uint32_t border_color_ptr;
6916
6917 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
6918 vk_find_struct_const(pCreateInfo->pNext,
6919 SAMPLER_REDUCTION_MODE_CREATE_INFO);
6920 if (sampler_reduction)
6921 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
6922
6923 if (pCreateInfo->compareEnable)
6924 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
6925
6926 sampler->border_color_slot = RADV_BORDER_COLOR_COUNT;
6927
6928 if (border_color == VK_BORDER_COLOR_FLOAT_CUSTOM_EXT || border_color == VK_BORDER_COLOR_INT_CUSTOM_EXT) {
6929 const VkSamplerCustomBorderColorCreateInfoEXT *custom_border_color =
6930 vk_find_struct_const(pCreateInfo->pNext,
6931 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT);
6932
6933 assert(custom_border_color);
6934
6935 sampler->border_color_slot =
6936 radv_register_border_color(device, custom_border_color->customBorderColor);
6937
6938 /* Did we fail to find a slot? */
6939 if (sampler->border_color_slot == RADV_BORDER_COLOR_COUNT) {
6940 fprintf(stderr, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
6941 border_color = VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK;
6942 }
6943 }
6944
6945 /* If we don't have a custom color, set the ptr to 0 */
6946 border_color_ptr = sampler->border_color_slot != RADV_BORDER_COLOR_COUNT
6947 ? sampler->border_color_slot
6948 : 0;
6949
6950 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
6951 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
6952 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
6953 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
6954 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
6955 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
6956 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
6957 S_008F30_ANISO_BIAS(max_aniso_ratio) |
6958 S_008F30_DISABLE_CUBE_WRAP(0) |
6959 S_008F30_COMPAT_MODE(compat_mode) |
6960 S_008F30_FILTER_MODE(filter_mode) |
6961 S_008F30_TRUNC_COORD(trunc_coord));
6962 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
6963 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
6964 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
6965 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
6966 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
6967 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
6968 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
6969 S_008F38_MIP_POINT_PRECLAMP(0));
6970 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr) |
6971 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color)));
6972
6973 if (device->physical_device->rad_info.chip_class >= GFX10) {
6974 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6975 } else {
6976 sampler->state[2] |=
6977 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
6978 S_008F38_FILTER_PREC_FIX(1) |
6979 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
6980 }
6981 }
6982
6983 VkResult radv_CreateSampler(
6984 VkDevice _device,
6985 const VkSamplerCreateInfo* pCreateInfo,
6986 const VkAllocationCallbacks* pAllocator,
6987 VkSampler* pSampler)
6988 {
6989 RADV_FROM_HANDLE(radv_device, device, _device);
6990 struct radv_sampler *sampler;
6991
6992 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
6993 vk_find_struct_const(pCreateInfo->pNext,
6994 SAMPLER_YCBCR_CONVERSION_INFO);
6995
6996 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
6997
6998 sampler = vk_alloc2(&device->vk.alloc, pAllocator, sizeof(*sampler), 8,
6999 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7000 if (!sampler)
7001 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7002
7003 vk_object_base_init(&device->vk, &sampler->base,
7004 VK_OBJECT_TYPE_SAMPLER);
7005
7006 radv_init_sampler(device, sampler, pCreateInfo);
7007
7008 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7009 *pSampler = radv_sampler_to_handle(sampler);
7010
7011 return VK_SUCCESS;
7012 }
7013
7014 void radv_DestroySampler(
7015 VkDevice _device,
7016 VkSampler _sampler,
7017 const VkAllocationCallbacks* pAllocator)
7018 {
7019 RADV_FROM_HANDLE(radv_device, device, _device);
7020 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7021
7022 if (!sampler)
7023 return;
7024
7025 if (sampler->border_color_slot != RADV_BORDER_COLOR_COUNT)
7026 radv_unregister_border_color(device, sampler->border_color_slot);
7027
7028 vk_object_base_finish(&sampler->base);
7029 vk_free2(&device->vk.alloc, pAllocator, sampler);
7030 }
7031
7032 /* vk_icd.h does not declare this function, so we declare it here to
7033 * suppress Wmissing-prototypes.
7034 */
7035 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7036 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7037
7038 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7039 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7040 {
7041 /* For the full details on loader interface versioning, see
7042 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7043 * What follows is a condensed summary, to help you navigate the large and
7044 * confusing official doc.
7045 *
7046 * - Loader interface v0 is incompatible with later versions. We don't
7047 * support it.
7048 *
7049 * - In loader interface v1:
7050 * - The first ICD entrypoint called by the loader is
7051 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7052 * entrypoint.
7053 * - The ICD must statically expose no other Vulkan symbol unless it is
7054 * linked with -Bsymbolic.
7055 * - Each dispatchable Vulkan handle created by the ICD must be
7056 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7057 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7058 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7059 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7060 * such loader-managed surfaces.
7061 *
7062 * - Loader interface v2 differs from v1 in:
7063 * - The first ICD entrypoint called by the loader is
7064 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7065 * statically expose this entrypoint.
7066 *
7067 * - Loader interface v3 differs from v2 in:
7068 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7069 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7070 * because the loader no longer does so.
7071 */
7072 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7073 return VK_SUCCESS;
7074 }
7075
7076 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7077 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7078 int *pFD)
7079 {
7080 RADV_FROM_HANDLE(radv_device, device, _device);
7081 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7082
7083 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7084
7085 /* At the moment, we support only the below handle types. */
7086 assert(pGetFdInfo->handleType ==
7087 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7088 pGetFdInfo->handleType ==
7089 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7090
7091 bool ret = radv_get_memory_fd(device, memory, pFD);
7092 if (ret == false)
7093 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7094 return VK_SUCCESS;
7095 }
7096
7097 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device *dev,
7098 enum radeon_bo_domain domains,
7099 enum radeon_bo_flag flags,
7100 enum radeon_bo_flag ignore_flags)
7101 {
7102 /* Don't count GTT/CPU as relevant:
7103 *
7104 * - We're not fully consistent between the two.
7105 * - Sometimes VRAM gets VRAM|GTT.
7106 */
7107 const enum radeon_bo_domain relevant_domains = RADEON_DOMAIN_VRAM |
7108 RADEON_DOMAIN_GDS |
7109 RADEON_DOMAIN_OA;
7110 uint32_t bits = 0;
7111 for (unsigned i = 0; i < dev->memory_properties.memoryTypeCount; ++i) {
7112 if ((domains & relevant_domains) != (dev->memory_domains[i] & relevant_domains))
7113 continue;
7114
7115 if ((flags & ~ignore_flags) != (dev->memory_flags[i] & ~ignore_flags))
7116 continue;
7117
7118 bits |= 1u << i;
7119 }
7120
7121 return bits;
7122 }
7123
7124 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device *dev,
7125 enum radeon_bo_domain domains,
7126 enum radeon_bo_flag flags)
7127 {
7128 enum radeon_bo_flag ignore_flags = ~(RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_GTT_WC);
7129 uint32_t bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7130
7131 if (!bits) {
7132 ignore_flags |= RADEON_FLAG_NO_CPU_ACCESS;
7133 bits = radv_compute_valid_memory_types_attempt(dev, domains, flags, ignore_flags);
7134 }
7135
7136 return bits;
7137 }
7138 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7139 VkExternalMemoryHandleTypeFlagBits handleType,
7140 int fd,
7141 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7142 {
7143 RADV_FROM_HANDLE(radv_device, device, _device);
7144
7145 switch (handleType) {
7146 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT: {
7147 enum radeon_bo_domain domains;
7148 enum radeon_bo_flag flags;
7149 if (!device->ws->buffer_get_flags_from_fd(device->ws, fd, &domains, &flags))
7150 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7151
7152 pMemoryFdProperties->memoryTypeBits = radv_compute_valid_memory_types(device->physical_device, domains, flags);
7153 return VK_SUCCESS;
7154 }
7155 default:
7156 /* The valid usage section for this function says:
7157 *
7158 * "handleType must not be one of the handle types defined as
7159 * opaque."
7160 *
7161 * So opaque handle types fall into the default "unsupported" case.
7162 */
7163 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7164 }
7165 }
7166
7167 static VkResult radv_import_opaque_fd(struct radv_device *device,
7168 int fd,
7169 uint32_t *syncobj)
7170 {
7171 uint32_t syncobj_handle = 0;
7172 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7173 if (ret != 0)
7174 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7175
7176 if (*syncobj)
7177 device->ws->destroy_syncobj(device->ws, *syncobj);
7178
7179 *syncobj = syncobj_handle;
7180 close(fd);
7181
7182 return VK_SUCCESS;
7183 }
7184
7185 static VkResult radv_import_sync_fd(struct radv_device *device,
7186 int fd,
7187 uint32_t *syncobj)
7188 {
7189 /* If we create a syncobj we do it locally so that if we have an error, we don't
7190 * leave a syncobj in an undetermined state in the fence. */
7191 uint32_t syncobj_handle = *syncobj;
7192 if (!syncobj_handle) {
7193 bool create_signaled = fd == -1 ? true : false;
7194
7195 int ret = device->ws->create_syncobj(device->ws, create_signaled,
7196 &syncobj_handle);
7197 if (ret) {
7198 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7199 }
7200 } else {
7201 if (fd == -1)
7202 device->ws->signal_syncobj(device->ws, syncobj_handle);
7203 }
7204
7205 if (fd != -1) {
7206 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7207 if (ret)
7208 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7209 close(fd);
7210 }
7211
7212 *syncobj = syncobj_handle;
7213
7214 return VK_SUCCESS;
7215 }
7216
7217 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7218 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7219 {
7220 RADV_FROM_HANDLE(radv_device, device, _device);
7221 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7222 VkResult result;
7223 struct radv_semaphore_part *dst = NULL;
7224
7225 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7226 dst = &sem->temporary;
7227 } else {
7228 dst = &sem->permanent;
7229 }
7230
7231 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
7232
7233 switch(pImportSemaphoreFdInfo->handleType) {
7234 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7235 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7236 break;
7237 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7238 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7239 break;
7240 default:
7241 unreachable("Unhandled semaphore handle type");
7242 }
7243
7244 if (result == VK_SUCCESS) {
7245 dst->syncobj = syncobj;
7246 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7247 }
7248
7249 return result;
7250 }
7251
7252 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7253 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7254 int *pFd)
7255 {
7256 RADV_FROM_HANDLE(radv_device, device, _device);
7257 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7258 int ret;
7259 uint32_t syncobj_handle;
7260
7261 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7262 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
7263 syncobj_handle = sem->temporary.syncobj;
7264 } else {
7265 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
7266 syncobj_handle = sem->permanent.syncobj;
7267 }
7268
7269 switch(pGetFdInfo->handleType) {
7270 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7271 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7272 if (ret)
7273 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7274 break;
7275 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7276 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7277 if (ret)
7278 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7279
7280 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7281 radv_destroy_semaphore_part(device, &sem->temporary);
7282 } else {
7283 device->ws->reset_syncobj(device->ws, syncobj_handle);
7284 }
7285 break;
7286 default:
7287 unreachable("Unhandled semaphore handle type");
7288 }
7289
7290 return VK_SUCCESS;
7291 }
7292
7293 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7294 VkPhysicalDevice physicalDevice,
7295 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7296 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7297 {
7298 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7299 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7300
7301 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7302 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7303 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7304 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7305
7306 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7307 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7308 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7309 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7310 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7311 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7312 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7313 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7314 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7315 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7316 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7317 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7318 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7319 } else {
7320 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7321 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7322 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7323 }
7324 }
7325
7326 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7327 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7328 {
7329 RADV_FROM_HANDLE(radv_device, device, _device);
7330 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7331 struct radv_fence_part *dst = NULL;
7332 VkResult result;
7333
7334 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7335 dst = &fence->temporary;
7336 } else {
7337 dst = &fence->permanent;
7338 }
7339
7340 uint32_t syncobj = dst->kind == RADV_FENCE_SYNCOBJ ? dst->syncobj : 0;
7341
7342 switch(pImportFenceFdInfo->handleType) {
7343 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7344 result = radv_import_opaque_fd(device, pImportFenceFdInfo->fd, &syncobj);
7345 break;
7346 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7347 result = radv_import_sync_fd(device, pImportFenceFdInfo->fd, &syncobj);
7348 break;
7349 default:
7350 unreachable("Unhandled fence handle type");
7351 }
7352
7353 if (result == VK_SUCCESS) {
7354 dst->syncobj = syncobj;
7355 dst->kind = RADV_FENCE_SYNCOBJ;
7356 }
7357
7358 return result;
7359 }
7360
7361 VkResult radv_GetFenceFdKHR(VkDevice _device,
7362 const VkFenceGetFdInfoKHR *pGetFdInfo,
7363 int *pFd)
7364 {
7365 RADV_FROM_HANDLE(radv_device, device, _device);
7366 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7367 int ret;
7368
7369 struct radv_fence_part *part =
7370 fence->temporary.kind != RADV_FENCE_NONE ?
7371 &fence->temporary : &fence->permanent;
7372
7373 switch(pGetFdInfo->handleType) {
7374 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7375 ret = device->ws->export_syncobj(device->ws, part->syncobj, pFd);
7376 if (ret)
7377 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7378 break;
7379 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7380 ret = device->ws->export_syncobj_to_sync_file(device->ws,
7381 part->syncobj, pFd);
7382 if (ret)
7383 return vk_error(device->instance, VK_ERROR_TOO_MANY_OBJECTS);
7384
7385 if (part == &fence->temporary) {
7386 radv_destroy_fence_part(device, part);
7387 } else {
7388 device->ws->reset_syncobj(device->ws, part->syncobj);
7389 }
7390 break;
7391 default:
7392 unreachable("Unhandled fence handle type");
7393 }
7394
7395 return VK_SUCCESS;
7396 }
7397
7398 void radv_GetPhysicalDeviceExternalFenceProperties(
7399 VkPhysicalDevice physicalDevice,
7400 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7401 VkExternalFenceProperties *pExternalFenceProperties)
7402 {
7403 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7404
7405 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7406 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7407 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7408 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7409 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7410 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7411 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7412 } else {
7413 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7414 pExternalFenceProperties->compatibleHandleTypes = 0;
7415 pExternalFenceProperties->externalFenceFeatures = 0;
7416 }
7417 }
7418
7419 VkResult
7420 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7421 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7422 const VkAllocationCallbacks* pAllocator,
7423 VkDebugReportCallbackEXT* pCallback)
7424 {
7425 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7426 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7427 pCreateInfo, pAllocator, &instance->alloc,
7428 pCallback);
7429 }
7430
7431 void
7432 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7433 VkDebugReportCallbackEXT _callback,
7434 const VkAllocationCallbacks* pAllocator)
7435 {
7436 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7437 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7438 _callback, pAllocator, &instance->alloc);
7439 }
7440
7441 void
7442 radv_DebugReportMessageEXT(VkInstance _instance,
7443 VkDebugReportFlagsEXT flags,
7444 VkDebugReportObjectTypeEXT objectType,
7445 uint64_t object,
7446 size_t location,
7447 int32_t messageCode,
7448 const char* pLayerPrefix,
7449 const char* pMessage)
7450 {
7451 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7452 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7453 object, location, messageCode, pLayerPrefix, pMessage);
7454 }
7455
7456 void
7457 radv_GetDeviceGroupPeerMemoryFeatures(
7458 VkDevice device,
7459 uint32_t heapIndex,
7460 uint32_t localDeviceIndex,
7461 uint32_t remoteDeviceIndex,
7462 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7463 {
7464 assert(localDeviceIndex == remoteDeviceIndex);
7465
7466 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7467 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7468 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7469 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7470 }
7471
7472 static const VkTimeDomainEXT radv_time_domains[] = {
7473 VK_TIME_DOMAIN_DEVICE_EXT,
7474 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7475 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7476 };
7477
7478 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7479 VkPhysicalDevice physicalDevice,
7480 uint32_t *pTimeDomainCount,
7481 VkTimeDomainEXT *pTimeDomains)
7482 {
7483 int d;
7484 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7485
7486 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7487 vk_outarray_append(&out, i) {
7488 *i = radv_time_domains[d];
7489 }
7490 }
7491
7492 return vk_outarray_status(&out);
7493 }
7494
7495 static uint64_t
7496 radv_clock_gettime(clockid_t clock_id)
7497 {
7498 struct timespec current;
7499 int ret;
7500
7501 ret = clock_gettime(clock_id, &current);
7502 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7503 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7504 if (ret < 0)
7505 return 0;
7506
7507 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7508 }
7509
7510 VkResult radv_GetCalibratedTimestampsEXT(
7511 VkDevice _device,
7512 uint32_t timestampCount,
7513 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7514 uint64_t *pTimestamps,
7515 uint64_t *pMaxDeviation)
7516 {
7517 RADV_FROM_HANDLE(radv_device, device, _device);
7518 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7519 int d;
7520 uint64_t begin, end;
7521 uint64_t max_clock_period = 0;
7522
7523 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7524
7525 for (d = 0; d < timestampCount; d++) {
7526 switch (pTimestampInfos[d].timeDomain) {
7527 case VK_TIME_DOMAIN_DEVICE_EXT:
7528 pTimestamps[d] = device->ws->query_value(device->ws,
7529 RADEON_TIMESTAMP);
7530 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7531 max_clock_period = MAX2(max_clock_period, device_period);
7532 break;
7533 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7534 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7535 max_clock_period = MAX2(max_clock_period, 1);
7536 break;
7537
7538 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7539 pTimestamps[d] = begin;
7540 break;
7541 default:
7542 pTimestamps[d] = 0;
7543 break;
7544 }
7545 }
7546
7547 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7548
7549 /*
7550 * The maximum deviation is the sum of the interval over which we
7551 * perform the sampling and the maximum period of any sampled
7552 * clock. That's because the maximum skew between any two sampled
7553 * clock edges is when the sampled clock with the largest period is
7554 * sampled at the end of that period but right at the beginning of the
7555 * sampling interval and some other clock is sampled right at the
7556 * begining of its sampling period and right at the end of the
7557 * sampling interval. Let's assume the GPU has the longest clock
7558 * period and that the application is sampling GPU and monotonic:
7559 *
7560 * s e
7561 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7562 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7563 *
7564 * g
7565 * 0 1 2 3
7566 * GPU -----_____-----_____-----_____-----_____
7567 *
7568 * m
7569 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7570 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7571 *
7572 * Interval <----------------->
7573 * Deviation <-------------------------->
7574 *
7575 * s = read(raw) 2
7576 * g = read(GPU) 1
7577 * m = read(monotonic) 2
7578 * e = read(raw) b
7579 *
7580 * We round the sample interval up by one tick to cover sampling error
7581 * in the interval clock
7582 */
7583
7584 uint64_t sample_interval = end - begin + 1;
7585
7586 *pMaxDeviation = sample_interval + max_clock_period;
7587
7588 return VK_SUCCESS;
7589 }
7590
7591 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7592 VkPhysicalDevice physicalDevice,
7593 VkSampleCountFlagBits samples,
7594 VkMultisamplePropertiesEXT* pMultisampleProperties)
7595 {
7596 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7597 VK_SAMPLE_COUNT_4_BIT |
7598 VK_SAMPLE_COUNT_8_BIT)) {
7599 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7600 } else {
7601 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7602 }
7603 }
7604
7605 VkResult radv_CreatePrivateDataSlotEXT(
7606 VkDevice _device,
7607 const VkPrivateDataSlotCreateInfoEXT* pCreateInfo,
7608 const VkAllocationCallbacks* pAllocator,
7609 VkPrivateDataSlotEXT* pPrivateDataSlot)
7610 {
7611 RADV_FROM_HANDLE(radv_device, device, _device);
7612 return vk_private_data_slot_create(&device->vk, pCreateInfo, pAllocator,
7613 pPrivateDataSlot);
7614 }
7615
7616 void radv_DestroyPrivateDataSlotEXT(
7617 VkDevice _device,
7618 VkPrivateDataSlotEXT privateDataSlot,
7619 const VkAllocationCallbacks* pAllocator)
7620 {
7621 RADV_FROM_HANDLE(radv_device, device, _device);
7622 vk_private_data_slot_destroy(&device->vk, privateDataSlot, pAllocator);
7623 }
7624
7625 VkResult radv_SetPrivateDataEXT(
7626 VkDevice _device,
7627 VkObjectType objectType,
7628 uint64_t objectHandle,
7629 VkPrivateDataSlotEXT privateDataSlot,
7630 uint64_t data)
7631 {
7632 RADV_FROM_HANDLE(radv_device, device, _device);
7633 return vk_object_base_set_private_data(&device->vk, objectType,
7634 objectHandle, privateDataSlot,
7635 data);
7636 }
7637
7638 void radv_GetPrivateDataEXT(
7639 VkDevice _device,
7640 VkObjectType objectType,
7641 uint64_t objectHandle,
7642 VkPrivateDataSlotEXT privateDataSlot,
7643 uint64_t* pData)
7644 {
7645 RADV_FROM_HANDLE(radv_device, device, _device);
7646 vk_object_base_get_private_data(&device->vk, objectType, objectHandle,
7647 privateDataSlot, pData);
7648 }