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radv: fix using LOAD_CONTEXT_REG with old GFX ME firmwares on GFX8
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
373 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
374 (device->rad_info.chip_class >= VI &&
375 device->rad_info.me_fw_feature >= 41);
376
377 radv_physical_device_init_mem_types(device);
378 radv_fill_device_extension_table(device, &device->supported_extensions);
379
380 device->bus_info = *drm_device->businfo.pci;
381
382 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
383 ac_print_gpu_info(&device->rad_info);
384
385 /* The WSI is structured as a layer on top of the driver, so this has
386 * to be the last part of initialization (at least until we get other
387 * semi-layers).
388 */
389 result = radv_init_wsi(device);
390 if (result != VK_SUCCESS) {
391 device->ws->destroy(device->ws);
392 vk_error(instance, result);
393 goto fail;
394 }
395
396 return VK_SUCCESS;
397
398 fail:
399 close(fd);
400 if (master_fd != -1)
401 close(master_fd);
402 return result;
403 }
404
405 static void
406 radv_physical_device_finish(struct radv_physical_device *device)
407 {
408 radv_finish_wsi(device);
409 device->ws->destroy(device->ws);
410 disk_cache_destroy(device->disk_cache);
411 close(device->local_fd);
412 if (device->master_fd != -1)
413 close(device->master_fd);
414 }
415
416 static void *
417 default_alloc_func(void *pUserData, size_t size, size_t align,
418 VkSystemAllocationScope allocationScope)
419 {
420 return malloc(size);
421 }
422
423 static void *
424 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
425 size_t align, VkSystemAllocationScope allocationScope)
426 {
427 return realloc(pOriginal, size);
428 }
429
430 static void
431 default_free_func(void *pUserData, void *pMemory)
432 {
433 free(pMemory);
434 }
435
436 static const VkAllocationCallbacks default_alloc = {
437 .pUserData = NULL,
438 .pfnAllocation = default_alloc_func,
439 .pfnReallocation = default_realloc_func,
440 .pfnFree = default_free_func,
441 };
442
443 static const struct debug_control radv_debug_options[] = {
444 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
445 {"nodcc", RADV_DEBUG_NO_DCC},
446 {"shaders", RADV_DEBUG_DUMP_SHADERS},
447 {"nocache", RADV_DEBUG_NO_CACHE},
448 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
449 {"nohiz", RADV_DEBUG_NO_HIZ},
450 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
451 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
452 {"allbos", RADV_DEBUG_ALL_BOS},
453 {"noibs", RADV_DEBUG_NO_IBS},
454 {"spirv", RADV_DEBUG_DUMP_SPIRV},
455 {"vmfaults", RADV_DEBUG_VM_FAULTS},
456 {"zerovram", RADV_DEBUG_ZERO_VRAM},
457 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
458 {"nosisched", RADV_DEBUG_NO_SISCHED},
459 {"preoptir", RADV_DEBUG_PREOPTIR},
460 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
461 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
462 {"info", RADV_DEBUG_INFO},
463 {"errors", RADV_DEBUG_ERRORS},
464 {"startup", RADV_DEBUG_STARTUP},
465 {"checkir", RADV_DEBUG_CHECKIR},
466 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
467 {"nobinning", RADV_DEBUG_NOBINNING},
468 {NULL, 0}
469 };
470
471 const char *
472 radv_get_debug_option_name(int id)
473 {
474 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
475 return radv_debug_options[id].string;
476 }
477
478 static const struct debug_control radv_perftest_options[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
480 {"sisched", RADV_PERFTEST_SISCHED},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525
526 VkResult radv_CreateInstance(
527 const VkInstanceCreateInfo* pCreateInfo,
528 const VkAllocationCallbacks* pAllocator,
529 VkInstance* pInstance)
530 {
531 struct radv_instance *instance;
532 VkResult result;
533
534 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
535
536 uint32_t client_version;
537 if (pCreateInfo->pApplicationInfo &&
538 pCreateInfo->pApplicationInfo->apiVersion != 0) {
539 client_version = pCreateInfo->pApplicationInfo->apiVersion;
540 } else {
541 client_version = VK_API_VERSION_1_0;
542 }
543
544 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
545 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
546 if (!instance)
547 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
550
551 if (pAllocator)
552 instance->alloc = *pAllocator;
553 else
554 instance->alloc = default_alloc;
555
556 instance->apiVersion = client_version;
557 instance->physicalDeviceCount = -1;
558
559 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
560 radv_debug_options);
561
562 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
563 radv_perftest_options);
564
565
566 if (instance->debug_flags & RADV_DEBUG_STARTUP)
567 radv_logi("Created an instance");
568
569 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
570 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
571 int index = radv_get_instance_extension_index(ext_name);
572
573 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
574 vk_free2(&default_alloc, pAllocator, instance);
575 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
576 }
577
578 instance->enabled_extensions.extensions[index] = true;
579 }
580
581 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
582 if (result != VK_SUCCESS) {
583 vk_free2(&default_alloc, pAllocator, instance);
584 return vk_error(instance, result);
585 }
586
587 _mesa_locale_init();
588
589 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
590
591 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
592
593 *pInstance = radv_instance_to_handle(instance);
594
595 return VK_SUCCESS;
596 }
597
598 void radv_DestroyInstance(
599 VkInstance _instance,
600 const VkAllocationCallbacks* pAllocator)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603
604 if (!instance)
605 return;
606
607 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
608 radv_physical_device_finish(instance->physicalDevices + i);
609 }
610
611 VG(VALGRIND_DESTROY_MEMPOOL(instance));
612
613 _mesa_locale_fini();
614
615 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
616
617 vk_free(&instance->alloc, instance);
618 }
619
620 static VkResult
621 radv_enumerate_devices(struct radv_instance *instance)
622 {
623 /* TODO: Check for more devices ? */
624 drmDevicePtr devices[8];
625 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
626 int max_devices;
627
628 instance->physicalDeviceCount = 0;
629
630 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
631
632 if (instance->debug_flags & RADV_DEBUG_STARTUP)
633 radv_logi("Found %d drm nodes", max_devices);
634
635 if (max_devices < 1)
636 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
637
638 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
639 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
640 devices[i]->bustype == DRM_BUS_PCI &&
641 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
642
643 result = radv_physical_device_init(instance->physicalDevices +
644 instance->physicalDeviceCount,
645 instance,
646 devices[i]);
647 if (result == VK_SUCCESS)
648 ++instance->physicalDeviceCount;
649 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
650 break;
651 }
652 }
653 drmFreeDevices(devices, max_devices);
654
655 return result;
656 }
657
658 VkResult radv_EnumeratePhysicalDevices(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceCount,
661 VkPhysicalDevice* pPhysicalDevices)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDevices) {
674 *pPhysicalDeviceCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
678 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
679 }
680
681 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
682 : VK_SUCCESS;
683 }
684
685 VkResult radv_EnumeratePhysicalDeviceGroups(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceGroupCount,
688 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDeviceGroupProperties) {
701 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
705 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
706 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
708 }
709 }
710 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
711 : VK_SUCCESS;
712 }
713
714 void radv_GetPhysicalDeviceFeatures(
715 VkPhysicalDevice physicalDevice,
716 VkPhysicalDeviceFeatures* pFeatures)
717 {
718 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
719 memset(pFeatures, 0, sizeof(*pFeatures));
720
721 *pFeatures = (VkPhysicalDeviceFeatures) {
722 .robustBufferAccess = true,
723 .fullDrawIndexUint32 = true,
724 .imageCubeArray = true,
725 .independentBlend = true,
726 .geometryShader = true,
727 .tessellationShader = true,
728 .sampleRateShading = true,
729 .dualSrcBlend = true,
730 .logicOp = true,
731 .multiDrawIndirect = true,
732 .drawIndirectFirstInstance = true,
733 .depthClamp = true,
734 .depthBiasClamp = true,
735 .fillModeNonSolid = true,
736 .depthBounds = true,
737 .wideLines = true,
738 .largePoints = true,
739 .alphaToOne = true,
740 .multiViewport = true,
741 .samplerAnisotropy = true,
742 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
743 pdevice->rad_info.family == CHIP_STONEY,
744 .textureCompressionASTC_LDR = false,
745 .textureCompressionBC = true,
746 .occlusionQueryPrecise = true,
747 .pipelineStatisticsQuery = true,
748 .vertexPipelineStoresAndAtomics = true,
749 .fragmentStoresAndAtomics = true,
750 .shaderTessellationAndGeometryPointSize = true,
751 .shaderImageGatherExtended = true,
752 .shaderStorageImageExtendedFormats = true,
753 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
754 .shaderUniformBufferArrayDynamicIndexing = true,
755 .shaderSampledImageArrayDynamicIndexing = true,
756 .shaderStorageBufferArrayDynamicIndexing = true,
757 .shaderStorageImageArrayDynamicIndexing = true,
758 .shaderStorageImageReadWithoutFormat = true,
759 .shaderStorageImageWriteWithoutFormat = true,
760 .shaderClipDistance = true,
761 .shaderCullDistance = true,
762 .shaderFloat64 = true,
763 .shaderInt64 = true,
764 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
765 .sparseBinding = true,
766 .variableMultisampleRate = true,
767 .inheritedQueries = true,
768 };
769 }
770
771 void radv_GetPhysicalDeviceFeatures2(
772 VkPhysicalDevice physicalDevice,
773 VkPhysicalDeviceFeatures2 *pFeatures)
774 {
775 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
776 vk_foreach_struct(ext, pFeatures->pNext) {
777 switch (ext->sType) {
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
779 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
780 features->variablePointersStorageBuffer = true;
781 features->variablePointers = true;
782 break;
783 }
784 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
785 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
786 features->multiview = true;
787 features->multiviewGeometryShader = true;
788 features->multiviewTessellationShader = true;
789 break;
790 }
791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
792 VkPhysicalDeviceShaderDrawParameterFeatures *features =
793 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
794 features->shaderDrawParameters = true;
795 break;
796 }
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
798 VkPhysicalDeviceProtectedMemoryFeatures *features =
799 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
800 features->protectedMemory = false;
801 break;
802 }
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
804 VkPhysicalDevice16BitStorageFeatures *features =
805 (VkPhysicalDevice16BitStorageFeatures*)ext;
806 bool enabled = pdevice->rad_info.chip_class >= VI;
807 features->storageBuffer16BitAccess = enabled;
808 features->uniformAndStorageBuffer16BitAccess = enabled;
809 features->storagePushConstant16 = enabled;
810 features->storageInputOutput16 = enabled;
811 break;
812 }
813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
814 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
815 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
816 features->samplerYcbcrConversion = false;
817 break;
818 }
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
820 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
821 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
822 features->shaderInputAttachmentArrayDynamicIndexing = true;
823 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
824 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
825 features->shaderUniformBufferArrayNonUniformIndexing = false;
826 features->shaderSampledImageArrayNonUniformIndexing = false;
827 features->shaderStorageBufferArrayNonUniformIndexing = false;
828 features->shaderStorageImageArrayNonUniformIndexing = false;
829 features->shaderInputAttachmentArrayNonUniformIndexing = false;
830 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
831 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
832 features->descriptorBindingUniformBufferUpdateAfterBind = true;
833 features->descriptorBindingSampledImageUpdateAfterBind = true;
834 features->descriptorBindingStorageImageUpdateAfterBind = true;
835 features->descriptorBindingStorageBufferUpdateAfterBind = true;
836 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
837 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
838 features->descriptorBindingUpdateUnusedWhilePending = true;
839 features->descriptorBindingPartiallyBound = true;
840 features->descriptorBindingVariableDescriptorCount = true;
841 features->runtimeDescriptorArray = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
845 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
846 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
847 features->conditionalRendering = true;
848 features->inheritedConditionalRendering = false;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
852 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
853 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
854 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
855 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
856 break;
857 }
858 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
859 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
860 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
861 features->transformFeedback = true;
862 features->geometryStreams = true;
863 break;
864 }
865 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
866 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
867 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
868 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
869 break;
870 }
871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
872 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
873 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
874 features->memoryPriority = VK_TRUE;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
878 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
879 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
880 features->bufferDeviceAddress = true;
881 features->bufferDeviceAddressCaptureReplay = false;
882 features->bufferDeviceAddressMultiDevice = false;
883 break;
884 }
885 default:
886 break;
887 }
888 }
889 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
890 }
891
892 void radv_GetPhysicalDeviceProperties(
893 VkPhysicalDevice physicalDevice,
894 VkPhysicalDeviceProperties* pProperties)
895 {
896 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
897 VkSampleCountFlags sample_counts = 0xf;
898
899 /* make sure that the entire descriptor set is addressable with a signed
900 * 32-bit int. So the sum of all limits scaled by descriptor size has to
901 * be at most 2 GiB. the combined image & samples object count as one of
902 * both. This limit is for the pipeline layout, not for the set layout, but
903 * there is no set limit, so we just set a pipeline limit. I don't think
904 * any app is going to hit this soon. */
905 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
906 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
907 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
908 32 /* sampler, largest when combined with image */ +
909 64 /* sampled image */ +
910 64 /* storage image */);
911
912 VkPhysicalDeviceLimits limits = {
913 .maxImageDimension1D = (1 << 14),
914 .maxImageDimension2D = (1 << 14),
915 .maxImageDimension3D = (1 << 11),
916 .maxImageDimensionCube = (1 << 14),
917 .maxImageArrayLayers = (1 << 11),
918 .maxTexelBufferElements = 128 * 1024 * 1024,
919 .maxUniformBufferRange = UINT32_MAX,
920 .maxStorageBufferRange = UINT32_MAX,
921 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
922 .maxMemoryAllocationCount = UINT32_MAX,
923 .maxSamplerAllocationCount = 64 * 1024,
924 .bufferImageGranularity = 64, /* A cache line */
925 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
926 .maxBoundDescriptorSets = MAX_SETS,
927 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
928 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
929 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
930 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
931 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
932 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
933 .maxPerStageResources = max_descriptor_set_size,
934 .maxDescriptorSetSamplers = max_descriptor_set_size,
935 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
936 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
937 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
938 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
939 .maxDescriptorSetSampledImages = max_descriptor_set_size,
940 .maxDescriptorSetStorageImages = max_descriptor_set_size,
941 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
942 .maxVertexInputAttributes = 32,
943 .maxVertexInputBindings = 32,
944 .maxVertexInputAttributeOffset = 2047,
945 .maxVertexInputBindingStride = 2048,
946 .maxVertexOutputComponents = 128,
947 .maxTessellationGenerationLevel = 64,
948 .maxTessellationPatchSize = 32,
949 .maxTessellationControlPerVertexInputComponents = 128,
950 .maxTessellationControlPerVertexOutputComponents = 128,
951 .maxTessellationControlPerPatchOutputComponents = 120,
952 .maxTessellationControlTotalOutputComponents = 4096,
953 .maxTessellationEvaluationInputComponents = 128,
954 .maxTessellationEvaluationOutputComponents = 128,
955 .maxGeometryShaderInvocations = 127,
956 .maxGeometryInputComponents = 64,
957 .maxGeometryOutputComponents = 128,
958 .maxGeometryOutputVertices = 256,
959 .maxGeometryTotalOutputComponents = 1024,
960 .maxFragmentInputComponents = 128,
961 .maxFragmentOutputAttachments = 8,
962 .maxFragmentDualSrcAttachments = 1,
963 .maxFragmentCombinedOutputResources = 8,
964 .maxComputeSharedMemorySize = 32768,
965 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
966 .maxComputeWorkGroupInvocations = 2048,
967 .maxComputeWorkGroupSize = {
968 2048,
969 2048,
970 2048
971 },
972 .subPixelPrecisionBits = 8,
973 .subTexelPrecisionBits = 8,
974 .mipmapPrecisionBits = 8,
975 .maxDrawIndexedIndexValue = UINT32_MAX,
976 .maxDrawIndirectCount = UINT32_MAX,
977 .maxSamplerLodBias = 16,
978 .maxSamplerAnisotropy = 16,
979 .maxViewports = MAX_VIEWPORTS,
980 .maxViewportDimensions = { (1 << 14), (1 << 14) },
981 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
982 .viewportSubPixelBits = 8,
983 .minMemoryMapAlignment = 4096, /* A page */
984 .minTexelBufferOffsetAlignment = 1,
985 .minUniformBufferOffsetAlignment = 4,
986 .minStorageBufferOffsetAlignment = 4,
987 .minTexelOffset = -32,
988 .maxTexelOffset = 31,
989 .minTexelGatherOffset = -32,
990 .maxTexelGatherOffset = 31,
991 .minInterpolationOffset = -2,
992 .maxInterpolationOffset = 2,
993 .subPixelInterpolationOffsetBits = 8,
994 .maxFramebufferWidth = (1 << 14),
995 .maxFramebufferHeight = (1 << 14),
996 .maxFramebufferLayers = (1 << 10),
997 .framebufferColorSampleCounts = sample_counts,
998 .framebufferDepthSampleCounts = sample_counts,
999 .framebufferStencilSampleCounts = sample_counts,
1000 .framebufferNoAttachmentsSampleCounts = sample_counts,
1001 .maxColorAttachments = MAX_RTS,
1002 .sampledImageColorSampleCounts = sample_counts,
1003 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1004 .sampledImageDepthSampleCounts = sample_counts,
1005 .sampledImageStencilSampleCounts = sample_counts,
1006 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1007 .maxSampleMaskWords = 1,
1008 .timestampComputeAndGraphics = true,
1009 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1010 .maxClipDistances = 8,
1011 .maxCullDistances = 8,
1012 .maxCombinedClipAndCullDistances = 8,
1013 .discreteQueuePriorities = 2,
1014 .pointSizeRange = { 0.125, 255.875 },
1015 .lineWidthRange = { 0.0, 7.9921875 },
1016 .pointSizeGranularity = (1.0 / 8.0),
1017 .lineWidthGranularity = (1.0 / 128.0),
1018 .strictLines = false, /* FINISHME */
1019 .standardSampleLocations = true,
1020 .optimalBufferCopyOffsetAlignment = 128,
1021 .optimalBufferCopyRowPitchAlignment = 128,
1022 .nonCoherentAtomSize = 64,
1023 };
1024
1025 *pProperties = (VkPhysicalDeviceProperties) {
1026 .apiVersion = radv_physical_device_api_version(pdevice),
1027 .driverVersion = vk_get_driver_version(),
1028 .vendorID = ATI_VENDOR_ID,
1029 .deviceID = pdevice->rad_info.pci_id,
1030 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1031 .limits = limits,
1032 .sparseProperties = {0},
1033 };
1034
1035 strcpy(pProperties->deviceName, pdevice->name);
1036 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1037 }
1038
1039 void radv_GetPhysicalDeviceProperties2(
1040 VkPhysicalDevice physicalDevice,
1041 VkPhysicalDeviceProperties2 *pProperties)
1042 {
1043 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1044 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1045
1046 vk_foreach_struct(ext, pProperties->pNext) {
1047 switch (ext->sType) {
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1049 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1050 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1051 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1052 break;
1053 }
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1055 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1056 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1057 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1058 properties->deviceLUIDValid = false;
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1062 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1063 properties->maxMultiviewViewCount = MAX_VIEWS;
1064 properties->maxMultiviewInstanceIndex = INT_MAX;
1065 break;
1066 }
1067 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1068 VkPhysicalDevicePointClippingProperties *properties =
1069 (VkPhysicalDevicePointClippingProperties*)ext;
1070 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1071 break;
1072 }
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1074 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1075 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1076 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1077 break;
1078 }
1079 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1080 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1081 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1082 properties->minImportedHostPointerAlignment = 4096;
1083 break;
1084 }
1085 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1086 VkPhysicalDeviceSubgroupProperties *properties =
1087 (VkPhysicalDeviceSubgroupProperties*)ext;
1088 properties->subgroupSize = 64;
1089 properties->supportedStages = VK_SHADER_STAGE_ALL;
1090 properties->supportedOperations =
1091 VK_SUBGROUP_FEATURE_BASIC_BIT |
1092 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1093 VK_SUBGROUP_FEATURE_QUAD_BIT |
1094 VK_SUBGROUP_FEATURE_VOTE_BIT;
1095 if (pdevice->rad_info.chip_class >= VI) {
1096 properties->supportedOperations |=
1097 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1098 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1099 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1100 }
1101 properties->quadOperationsInAllStages = true;
1102 break;
1103 }
1104 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1105 VkPhysicalDeviceMaintenance3Properties *properties =
1106 (VkPhysicalDeviceMaintenance3Properties*)ext;
1107 /* Make sure everything is addressable by a signed 32-bit int, and
1108 * our largest descriptors are 96 bytes. */
1109 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1110 /* Our buffer size fields allow only this much */
1111 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1112 break;
1113 }
1114 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1115 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1116 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1117 /* GFX6-8 only support single channel min/max filter. */
1118 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1119 properties->filterMinmaxSingleComponentFormats = true;
1120 break;
1121 }
1122 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1123 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1124 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1125
1126 /* Shader engines. */
1127 properties->shaderEngineCount =
1128 pdevice->rad_info.max_se;
1129 properties->shaderArraysPerEngineCount =
1130 pdevice->rad_info.max_sh_per_se;
1131 properties->computeUnitsPerShaderArray =
1132 pdevice->rad_info.num_good_cu_per_sh;
1133 properties->simdPerComputeUnit = 4;
1134 properties->wavefrontsPerSimd =
1135 pdevice->rad_info.family == CHIP_TONGA ||
1136 pdevice->rad_info.family == CHIP_ICELAND ||
1137 pdevice->rad_info.family == CHIP_POLARIS10 ||
1138 pdevice->rad_info.family == CHIP_POLARIS11 ||
1139 pdevice->rad_info.family == CHIP_POLARIS12 ||
1140 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1141 properties->wavefrontSize = 64;
1142
1143 /* SGPR. */
1144 properties->sgprsPerSimd =
1145 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1146 properties->minSgprAllocation =
1147 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1148 properties->maxSgprAllocation =
1149 pdevice->rad_info.family == CHIP_TONGA ||
1150 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1151 properties->sgprAllocationGranularity =
1152 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1153
1154 /* VGPR. */
1155 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1156 properties->minVgprAllocation = 4;
1157 properties->maxVgprAllocation = 256;
1158 properties->vgprAllocationGranularity = 4;
1159 break;
1160 }
1161 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1162 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1163 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1164 properties->maxVertexAttribDivisor = UINT32_MAX;
1165 break;
1166 }
1167 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1168 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1169 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1170 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1171 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1172 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1173 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1174 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1175 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1176 properties->robustBufferAccessUpdateAfterBind = false;
1177 properties->quadDivergentImplicitLod = false;
1178
1179 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1180 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1181 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1182 32 /* sampler, largest when combined with image */ +
1183 64 /* sampled image */ +
1184 64 /* storage image */);
1185 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1186 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1187 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1188 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1189 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1190 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1191 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1192 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1193 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1194 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1195 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1196 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1197 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1198 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1199 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1200 break;
1201 }
1202 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1203 VkPhysicalDeviceProtectedMemoryProperties *properties =
1204 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1205 properties->protectedNoFault = false;
1206 break;
1207 }
1208 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1209 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1210 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1211 properties->primitiveOverestimationSize = 0;
1212 properties->maxExtraPrimitiveOverestimationSize = 0;
1213 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1214 properties->primitiveUnderestimation = VK_FALSE;
1215 properties->conservativePointAndLineRasterization = VK_FALSE;
1216 properties->degenerateTrianglesRasterized = VK_FALSE;
1217 properties->degenerateLinesRasterized = VK_FALSE;
1218 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1219 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1220 break;
1221 }
1222 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1223 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1224 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1225 properties->pciDomain = pdevice->bus_info.domain;
1226 properties->pciBus = pdevice->bus_info.bus;
1227 properties->pciDevice = pdevice->bus_info.dev;
1228 properties->pciFunction = pdevice->bus_info.func;
1229 break;
1230 }
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1232 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1233 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1234
1235 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1236 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1237 strcpy(driver_props->driverName, "radv");
1238
1239 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1240 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1241 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1242 " (LLVM %d.%d.%d)",
1243 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1244 MESA_LLVM_VERSION_PATCH);
1245
1246 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1247 .major = 1,
1248 .minor = 1,
1249 .subminor = 2,
1250 .patch = 0,
1251 };
1252 break;
1253 }
1254 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1255 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1256 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1257 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1258 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1259 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1260 properties->maxTransformFeedbackStreamDataSize = 512;
1261 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1262 properties->maxTransformFeedbackBufferDataStride = 512;
1263 properties->transformFeedbackQueries = true;
1264 properties->transformFeedbackStreamsLinesTriangles = false;
1265 properties->transformFeedbackRasterizationStreamSelect = false;
1266 properties->transformFeedbackDraw = true;
1267 break;
1268 }
1269 default:
1270 break;
1271 }
1272 }
1273 }
1274
1275 static void radv_get_physical_device_queue_family_properties(
1276 struct radv_physical_device* pdevice,
1277 uint32_t* pCount,
1278 VkQueueFamilyProperties** pQueueFamilyProperties)
1279 {
1280 int num_queue_families = 1;
1281 int idx;
1282 if (pdevice->rad_info.num_compute_rings > 0 &&
1283 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1284 num_queue_families++;
1285
1286 if (pQueueFamilyProperties == NULL) {
1287 *pCount = num_queue_families;
1288 return;
1289 }
1290
1291 if (!*pCount)
1292 return;
1293
1294 idx = 0;
1295 if (*pCount >= 1) {
1296 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1297 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1298 VK_QUEUE_COMPUTE_BIT |
1299 VK_QUEUE_TRANSFER_BIT |
1300 VK_QUEUE_SPARSE_BINDING_BIT,
1301 .queueCount = 1,
1302 .timestampValidBits = 64,
1303 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1304 };
1305 idx++;
1306 }
1307
1308 if (pdevice->rad_info.num_compute_rings > 0 &&
1309 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1310 if (*pCount > idx) {
1311 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1312 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1313 VK_QUEUE_TRANSFER_BIT |
1314 VK_QUEUE_SPARSE_BINDING_BIT,
1315 .queueCount = pdevice->rad_info.num_compute_rings,
1316 .timestampValidBits = 64,
1317 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1318 };
1319 idx++;
1320 }
1321 }
1322 *pCount = idx;
1323 }
1324
1325 void radv_GetPhysicalDeviceQueueFamilyProperties(
1326 VkPhysicalDevice physicalDevice,
1327 uint32_t* pCount,
1328 VkQueueFamilyProperties* pQueueFamilyProperties)
1329 {
1330 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1331 if (!pQueueFamilyProperties) {
1332 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1333 return;
1334 }
1335 VkQueueFamilyProperties *properties[] = {
1336 pQueueFamilyProperties + 0,
1337 pQueueFamilyProperties + 1,
1338 pQueueFamilyProperties + 2,
1339 };
1340 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1341 assert(*pCount <= 3);
1342 }
1343
1344 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1345 VkPhysicalDevice physicalDevice,
1346 uint32_t* pCount,
1347 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1348 {
1349 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1350 if (!pQueueFamilyProperties) {
1351 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1352 return;
1353 }
1354 VkQueueFamilyProperties *properties[] = {
1355 &pQueueFamilyProperties[0].queueFamilyProperties,
1356 &pQueueFamilyProperties[1].queueFamilyProperties,
1357 &pQueueFamilyProperties[2].queueFamilyProperties,
1358 };
1359 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1360 assert(*pCount <= 3);
1361 }
1362
1363 void radv_GetPhysicalDeviceMemoryProperties(
1364 VkPhysicalDevice physicalDevice,
1365 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1366 {
1367 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1368
1369 *pMemoryProperties = physical_device->memory_properties;
1370 }
1371
1372 static void
1373 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1374 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1375 {
1376 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1377 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1378 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1379 uint64_t vram_size = radv_get_vram_size(device);
1380 uint64_t gtt_size = device->rad_info.gart_size;
1381 uint64_t heap_budget, heap_usage;
1382
1383 /* For all memory heaps, the computation of budget is as follow:
1384 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1385 *
1386 * The Vulkan spec 1.1.97 says that the budget should include any
1387 * currently allocated device memory.
1388 *
1389 * Note that the application heap usages are not really accurate (eg.
1390 * in presence of shared buffers).
1391 */
1392 if (vram_size) {
1393 heap_usage = device->ws->query_value(device->ws,
1394 RADEON_ALLOCATED_VRAM);
1395
1396 heap_budget = vram_size -
1397 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1398 heap_usage;
1399
1400 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1401 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1402 }
1403
1404 if (visible_vram_size) {
1405 heap_usage = device->ws->query_value(device->ws,
1406 RADEON_ALLOCATED_VRAM_VIS);
1407
1408 heap_budget = visible_vram_size -
1409 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1410 heap_usage;
1411
1412 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1413 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1414 }
1415
1416 if (gtt_size) {
1417 heap_usage = device->ws->query_value(device->ws,
1418 RADEON_ALLOCATED_GTT);
1419
1420 heap_budget = gtt_size -
1421 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1422 heap_usage;
1423
1424 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1425 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1426 }
1427
1428 /* The heapBudget and heapUsage values must be zero for array elements
1429 * greater than or equal to
1430 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1431 */
1432 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1433 memoryBudget->heapBudget[i] = 0;
1434 memoryBudget->heapUsage[i] = 0;
1435 }
1436 }
1437
1438 void radv_GetPhysicalDeviceMemoryProperties2(
1439 VkPhysicalDevice physicalDevice,
1440 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1441 {
1442 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1443 &pMemoryProperties->memoryProperties);
1444
1445 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1446 vk_find_struct(pMemoryProperties->pNext,
1447 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1448 if (memory_budget)
1449 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1450 }
1451
1452 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1453 VkDevice _device,
1454 VkExternalMemoryHandleTypeFlagBits handleType,
1455 const void *pHostPointer,
1456 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1457 {
1458 RADV_FROM_HANDLE(radv_device, device, _device);
1459
1460 switch (handleType)
1461 {
1462 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1463 const struct radv_physical_device *physical_device = device->physical_device;
1464 uint32_t memoryTypeBits = 0;
1465 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1466 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1467 memoryTypeBits = (1 << i);
1468 break;
1469 }
1470 }
1471 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1472 return VK_SUCCESS;
1473 }
1474 default:
1475 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1476 }
1477 }
1478
1479 static enum radeon_ctx_priority
1480 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1481 {
1482 /* Default to MEDIUM when a specific global priority isn't requested */
1483 if (!pObj)
1484 return RADEON_CTX_PRIORITY_MEDIUM;
1485
1486 switch(pObj->globalPriority) {
1487 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1488 return RADEON_CTX_PRIORITY_REALTIME;
1489 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1490 return RADEON_CTX_PRIORITY_HIGH;
1491 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1492 return RADEON_CTX_PRIORITY_MEDIUM;
1493 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1494 return RADEON_CTX_PRIORITY_LOW;
1495 default:
1496 unreachable("Illegal global priority value");
1497 return RADEON_CTX_PRIORITY_INVALID;
1498 }
1499 }
1500
1501 static int
1502 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1503 uint32_t queue_family_index, int idx,
1504 VkDeviceQueueCreateFlags flags,
1505 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1506 {
1507 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1508 queue->device = device;
1509 queue->queue_family_index = queue_family_index;
1510 queue->queue_idx = idx;
1511 queue->priority = radv_get_queue_global_priority(global_priority);
1512 queue->flags = flags;
1513
1514 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1515 if (!queue->hw_ctx)
1516 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1517
1518 return VK_SUCCESS;
1519 }
1520
1521 static void
1522 radv_queue_finish(struct radv_queue *queue)
1523 {
1524 if (queue->hw_ctx)
1525 queue->device->ws->ctx_destroy(queue->hw_ctx);
1526
1527 if (queue->initial_full_flush_preamble_cs)
1528 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1529 if (queue->initial_preamble_cs)
1530 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1531 if (queue->continue_preamble_cs)
1532 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1533 if (queue->descriptor_bo)
1534 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1535 if (queue->scratch_bo)
1536 queue->device->ws->buffer_destroy(queue->scratch_bo);
1537 if (queue->esgs_ring_bo)
1538 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1539 if (queue->gsvs_ring_bo)
1540 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1541 if (queue->tess_rings_bo)
1542 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1543 if (queue->compute_scratch_bo)
1544 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1545 }
1546
1547 static void
1548 radv_bo_list_init(struct radv_bo_list *bo_list)
1549 {
1550 pthread_mutex_init(&bo_list->mutex, NULL);
1551 bo_list->list.count = bo_list->capacity = 0;
1552 bo_list->list.bos = NULL;
1553 }
1554
1555 static void
1556 radv_bo_list_finish(struct radv_bo_list *bo_list)
1557 {
1558 free(bo_list->list.bos);
1559 pthread_mutex_destroy(&bo_list->mutex);
1560 }
1561
1562 static VkResult radv_bo_list_add(struct radv_device *device,
1563 struct radeon_winsys_bo *bo)
1564 {
1565 struct radv_bo_list *bo_list = &device->bo_list;
1566
1567 if (bo->is_local)
1568 return VK_SUCCESS;
1569
1570 if (unlikely(!device->use_global_bo_list))
1571 return VK_SUCCESS;
1572
1573 pthread_mutex_lock(&bo_list->mutex);
1574 if (bo_list->list.count == bo_list->capacity) {
1575 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1576 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1577
1578 if (!data) {
1579 pthread_mutex_unlock(&bo_list->mutex);
1580 return VK_ERROR_OUT_OF_HOST_MEMORY;
1581 }
1582
1583 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1584 bo_list->capacity = capacity;
1585 }
1586
1587 bo_list->list.bos[bo_list->list.count++] = bo;
1588 pthread_mutex_unlock(&bo_list->mutex);
1589 return VK_SUCCESS;
1590 }
1591
1592 static void radv_bo_list_remove(struct radv_device *device,
1593 struct radeon_winsys_bo *bo)
1594 {
1595 struct radv_bo_list *bo_list = &device->bo_list;
1596
1597 if (bo->is_local)
1598 return;
1599
1600 if (unlikely(!device->use_global_bo_list))
1601 return;
1602
1603 pthread_mutex_lock(&bo_list->mutex);
1604 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1605 if (bo_list->list.bos[i] == bo) {
1606 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1607 --bo_list->list.count;
1608 break;
1609 }
1610 }
1611 pthread_mutex_unlock(&bo_list->mutex);
1612 }
1613
1614 static void
1615 radv_device_init_gs_info(struct radv_device *device)
1616 {
1617 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1618 device->physical_device->rad_info.family);
1619 }
1620
1621 static int radv_get_device_extension_index(const char *name)
1622 {
1623 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1624 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1625 return i;
1626 }
1627 return -1;
1628 }
1629
1630 static int
1631 radv_get_int_debug_option(const char *name, int default_value)
1632 {
1633 const char *str;
1634 int result;
1635
1636 str = getenv(name);
1637 if (!str) {
1638 result = default_value;
1639 } else {
1640 char *endptr;
1641
1642 result = strtol(str, &endptr, 0);
1643 if (str == endptr) {
1644 /* No digits founs. */
1645 result = default_value;
1646 }
1647 }
1648
1649 return result;
1650 }
1651
1652 VkResult radv_CreateDevice(
1653 VkPhysicalDevice physicalDevice,
1654 const VkDeviceCreateInfo* pCreateInfo,
1655 const VkAllocationCallbacks* pAllocator,
1656 VkDevice* pDevice)
1657 {
1658 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1659 VkResult result;
1660 struct radv_device *device;
1661
1662 bool keep_shader_info = false;
1663
1664 /* Check enabled features */
1665 if (pCreateInfo->pEnabledFeatures) {
1666 VkPhysicalDeviceFeatures supported_features;
1667 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1668 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1669 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1670 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1671 for (uint32_t i = 0; i < num_features; i++) {
1672 if (enabled_feature[i] && !supported_feature[i])
1673 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1674 }
1675 }
1676
1677 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1678 sizeof(*device), 8,
1679 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1680 if (!device)
1681 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1682
1683 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1684 device->instance = physical_device->instance;
1685 device->physical_device = physical_device;
1686
1687 device->ws = physical_device->ws;
1688 if (pAllocator)
1689 device->alloc = *pAllocator;
1690 else
1691 device->alloc = physical_device->instance->alloc;
1692
1693 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1694 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1695 int index = radv_get_device_extension_index(ext_name);
1696 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1697 vk_free(&device->alloc, device);
1698 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1699 }
1700
1701 device->enabled_extensions.extensions[index] = true;
1702 }
1703
1704 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1705
1706 /* With update after bind we can't attach bo's to the command buffer
1707 * from the descriptor set anymore, so we have to use a global BO list.
1708 */
1709 device->use_global_bo_list =
1710 device->enabled_extensions.EXT_descriptor_indexing ||
1711 device->enabled_extensions.EXT_buffer_device_address;
1712
1713 mtx_init(&device->shader_slab_mutex, mtx_plain);
1714 list_inithead(&device->shader_slabs);
1715
1716 radv_bo_list_init(&device->bo_list);
1717
1718 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1719 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1720 uint32_t qfi = queue_create->queueFamilyIndex;
1721 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1722 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1723
1724 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1725
1726 device->queues[qfi] = vk_alloc(&device->alloc,
1727 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1728 if (!device->queues[qfi]) {
1729 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1730 goto fail;
1731 }
1732
1733 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1734
1735 device->queue_count[qfi] = queue_create->queueCount;
1736
1737 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1738 result = radv_queue_init(device, &device->queues[qfi][q],
1739 qfi, q, queue_create->flags,
1740 global_priority);
1741 if (result != VK_SUCCESS)
1742 goto fail;
1743 }
1744 }
1745
1746 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1747 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1748
1749 /* Disabled and not implemented for now. */
1750 device->dfsm_allowed = device->pbb_allowed &&
1751 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1752 device->physical_device->rad_info.family == CHIP_RAVEN2);
1753
1754 #ifdef ANDROID
1755 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1756 #endif
1757
1758 /* The maximum number of scratch waves. Scratch space isn't divided
1759 * evenly between CUs. The number is only a function of the number of CUs.
1760 * We can decrease the constant to decrease the scratch buffer size.
1761 *
1762 * sctx->scratch_waves must be >= the maximum possible size of
1763 * 1 threadgroup, so that the hw doesn't hang from being unable
1764 * to start any.
1765 *
1766 * The recommended value is 4 per CU at most. Higher numbers don't
1767 * bring much benefit, but they still occupy chip resources (think
1768 * async compute). I've seen ~2% performance difference between 4 and 32.
1769 */
1770 uint32_t max_threads_per_block = 2048;
1771 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1772 max_threads_per_block / 64);
1773
1774 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1775
1776 if (device->physical_device->rad_info.chip_class >= CIK) {
1777 /* If the KMD allows it (there is a KMD hw register for it),
1778 * allow launching waves out-of-order.
1779 */
1780 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1781 }
1782
1783 radv_device_init_gs_info(device);
1784
1785 device->tess_offchip_block_dw_size =
1786 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1787 device->has_distributed_tess =
1788 device->physical_device->rad_info.chip_class >= VI &&
1789 device->physical_device->rad_info.max_se >= 2;
1790
1791 if (getenv("RADV_TRACE_FILE")) {
1792 const char *filename = getenv("RADV_TRACE_FILE");
1793
1794 keep_shader_info = true;
1795
1796 if (!radv_init_trace(device))
1797 goto fail;
1798
1799 fprintf(stderr, "*****************************************************************************\n");
1800 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1801 fprintf(stderr, "*****************************************************************************\n");
1802
1803 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1804 radv_dump_enabled_options(device, stderr);
1805 }
1806
1807 device->keep_shader_info = keep_shader_info;
1808
1809 result = radv_device_init_meta(device);
1810 if (result != VK_SUCCESS)
1811 goto fail;
1812
1813 radv_device_init_msaa(device);
1814
1815 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1816 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1817 switch (family) {
1818 case RADV_QUEUE_GENERAL:
1819 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1820 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1821 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1822 break;
1823 case RADV_QUEUE_COMPUTE:
1824 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1825 radeon_emit(device->empty_cs[family], 0);
1826 break;
1827 }
1828 device->ws->cs_finalize(device->empty_cs[family]);
1829 }
1830
1831 if (device->physical_device->rad_info.chip_class >= CIK)
1832 cik_create_gfx_config(device);
1833
1834 VkPipelineCacheCreateInfo ci;
1835 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1836 ci.pNext = NULL;
1837 ci.flags = 0;
1838 ci.pInitialData = NULL;
1839 ci.initialDataSize = 0;
1840 VkPipelineCache pc;
1841 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1842 &ci, NULL, &pc);
1843 if (result != VK_SUCCESS)
1844 goto fail_meta;
1845
1846 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1847
1848 device->force_aniso =
1849 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1850 if (device->force_aniso >= 0) {
1851 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1852 1 << util_logbase2(device->force_aniso));
1853 }
1854
1855 *pDevice = radv_device_to_handle(device);
1856 return VK_SUCCESS;
1857
1858 fail_meta:
1859 radv_device_finish_meta(device);
1860 fail:
1861 radv_bo_list_finish(&device->bo_list);
1862
1863 if (device->trace_bo)
1864 device->ws->buffer_destroy(device->trace_bo);
1865
1866 if (device->gfx_init)
1867 device->ws->buffer_destroy(device->gfx_init);
1868
1869 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1870 for (unsigned q = 0; q < device->queue_count[i]; q++)
1871 radv_queue_finish(&device->queues[i][q]);
1872 if (device->queue_count[i])
1873 vk_free(&device->alloc, device->queues[i]);
1874 }
1875
1876 vk_free(&device->alloc, device);
1877 return result;
1878 }
1879
1880 void radv_DestroyDevice(
1881 VkDevice _device,
1882 const VkAllocationCallbacks* pAllocator)
1883 {
1884 RADV_FROM_HANDLE(radv_device, device, _device);
1885
1886 if (!device)
1887 return;
1888
1889 if (device->trace_bo)
1890 device->ws->buffer_destroy(device->trace_bo);
1891
1892 if (device->gfx_init)
1893 device->ws->buffer_destroy(device->gfx_init);
1894
1895 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1896 for (unsigned q = 0; q < device->queue_count[i]; q++)
1897 radv_queue_finish(&device->queues[i][q]);
1898 if (device->queue_count[i])
1899 vk_free(&device->alloc, device->queues[i]);
1900 if (device->empty_cs[i])
1901 device->ws->cs_destroy(device->empty_cs[i]);
1902 }
1903 radv_device_finish_meta(device);
1904
1905 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1906 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1907
1908 radv_destroy_shader_slabs(device);
1909
1910 radv_bo_list_finish(&device->bo_list);
1911 vk_free(&device->alloc, device);
1912 }
1913
1914 VkResult radv_EnumerateInstanceLayerProperties(
1915 uint32_t* pPropertyCount,
1916 VkLayerProperties* pProperties)
1917 {
1918 if (pProperties == NULL) {
1919 *pPropertyCount = 0;
1920 return VK_SUCCESS;
1921 }
1922
1923 /* None supported at this time */
1924 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1925 }
1926
1927 VkResult radv_EnumerateDeviceLayerProperties(
1928 VkPhysicalDevice physicalDevice,
1929 uint32_t* pPropertyCount,
1930 VkLayerProperties* pProperties)
1931 {
1932 if (pProperties == NULL) {
1933 *pPropertyCount = 0;
1934 return VK_SUCCESS;
1935 }
1936
1937 /* None supported at this time */
1938 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1939 }
1940
1941 void radv_GetDeviceQueue2(
1942 VkDevice _device,
1943 const VkDeviceQueueInfo2* pQueueInfo,
1944 VkQueue* pQueue)
1945 {
1946 RADV_FROM_HANDLE(radv_device, device, _device);
1947 struct radv_queue *queue;
1948
1949 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1950 if (pQueueInfo->flags != queue->flags) {
1951 /* From the Vulkan 1.1.70 spec:
1952 *
1953 * "The queue returned by vkGetDeviceQueue2 must have the same
1954 * flags value from this structure as that used at device
1955 * creation time in a VkDeviceQueueCreateInfo instance. If no
1956 * matching flags were specified at device creation time then
1957 * pQueue will return VK_NULL_HANDLE."
1958 */
1959 *pQueue = VK_NULL_HANDLE;
1960 return;
1961 }
1962
1963 *pQueue = radv_queue_to_handle(queue);
1964 }
1965
1966 void radv_GetDeviceQueue(
1967 VkDevice _device,
1968 uint32_t queueFamilyIndex,
1969 uint32_t queueIndex,
1970 VkQueue* pQueue)
1971 {
1972 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1973 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1974 .queueFamilyIndex = queueFamilyIndex,
1975 .queueIndex = queueIndex
1976 };
1977
1978 radv_GetDeviceQueue2(_device, &info, pQueue);
1979 }
1980
1981 static void
1982 fill_geom_tess_rings(struct radv_queue *queue,
1983 uint32_t *map,
1984 bool add_sample_positions,
1985 uint32_t esgs_ring_size,
1986 struct radeon_winsys_bo *esgs_ring_bo,
1987 uint32_t gsvs_ring_size,
1988 struct radeon_winsys_bo *gsvs_ring_bo,
1989 uint32_t tess_factor_ring_size,
1990 uint32_t tess_offchip_ring_offset,
1991 uint32_t tess_offchip_ring_size,
1992 struct radeon_winsys_bo *tess_rings_bo)
1993 {
1994 uint32_t *desc = &map[4];
1995
1996 if (esgs_ring_bo) {
1997 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
1998
1999 /* stride 0, num records - size, add tid, swizzle, elsize4,
2000 index stride 64 */
2001 desc[0] = esgs_va;
2002 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2003 S_008F04_STRIDE(0) |
2004 S_008F04_SWIZZLE_ENABLE(true);
2005 desc[2] = esgs_ring_size;
2006 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2007 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2008 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2009 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2010 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2011 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2012 S_008F0C_ELEMENT_SIZE(1) |
2013 S_008F0C_INDEX_STRIDE(3) |
2014 S_008F0C_ADD_TID_ENABLE(true);
2015
2016 /* GS entry for ES->GS ring */
2017 /* stride 0, num records - size, elsize0,
2018 index stride 0 */
2019 desc[4] = esgs_va;
2020 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2021 S_008F04_STRIDE(0) |
2022 S_008F04_SWIZZLE_ENABLE(false);
2023 desc[6] = esgs_ring_size;
2024 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2025 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2026 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2027 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2028 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2029 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2030 S_008F0C_ELEMENT_SIZE(0) |
2031 S_008F0C_INDEX_STRIDE(0) |
2032 S_008F0C_ADD_TID_ENABLE(false);
2033 }
2034
2035 desc += 8;
2036
2037 if (gsvs_ring_bo) {
2038 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2039
2040 /* VS entry for GS->VS ring */
2041 /* stride 0, num records - size, elsize0,
2042 index stride 0 */
2043 desc[0] = gsvs_va;
2044 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2045 S_008F04_STRIDE(0) |
2046 S_008F04_SWIZZLE_ENABLE(false);
2047 desc[2] = gsvs_ring_size;
2048 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2049 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2050 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2051 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2052 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2053 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2054 S_008F0C_ELEMENT_SIZE(0) |
2055 S_008F0C_INDEX_STRIDE(0) |
2056 S_008F0C_ADD_TID_ENABLE(false);
2057
2058 /* stride gsvs_itemsize, num records 64
2059 elsize 4, index stride 16 */
2060 /* shader will patch stride and desc[2] */
2061 desc[4] = gsvs_va;
2062 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2063 S_008F04_STRIDE(0) |
2064 S_008F04_SWIZZLE_ENABLE(true);
2065 desc[6] = 0;
2066 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2067 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2068 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2069 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2070 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2071 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2072 S_008F0C_ELEMENT_SIZE(1) |
2073 S_008F0C_INDEX_STRIDE(1) |
2074 S_008F0C_ADD_TID_ENABLE(true);
2075 }
2076
2077 desc += 8;
2078
2079 if (tess_rings_bo) {
2080 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2081 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2082
2083 desc[0] = tess_va;
2084 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2085 S_008F04_STRIDE(0) |
2086 S_008F04_SWIZZLE_ENABLE(false);
2087 desc[2] = tess_factor_ring_size;
2088 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2089 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2090 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2091 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2092 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2093 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2094 S_008F0C_ELEMENT_SIZE(0) |
2095 S_008F0C_INDEX_STRIDE(0) |
2096 S_008F0C_ADD_TID_ENABLE(false);
2097
2098 desc[4] = tess_offchip_va;
2099 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2100 S_008F04_STRIDE(0) |
2101 S_008F04_SWIZZLE_ENABLE(false);
2102 desc[6] = tess_offchip_ring_size;
2103 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2104 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2105 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2106 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2107 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2108 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2109 S_008F0C_ELEMENT_SIZE(0) |
2110 S_008F0C_INDEX_STRIDE(0) |
2111 S_008F0C_ADD_TID_ENABLE(false);
2112 }
2113
2114 desc += 8;
2115
2116 if (add_sample_positions) {
2117 /* add sample positions after all rings */
2118 memcpy(desc, queue->device->sample_locations_1x, 8);
2119 desc += 2;
2120 memcpy(desc, queue->device->sample_locations_2x, 16);
2121 desc += 4;
2122 memcpy(desc, queue->device->sample_locations_4x, 32);
2123 desc += 8;
2124 memcpy(desc, queue->device->sample_locations_8x, 64);
2125 }
2126 }
2127
2128 static unsigned
2129 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2130 {
2131 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2132 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2133 device->physical_device->rad_info.family != CHIP_STONEY;
2134 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2135 unsigned max_offchip_buffers;
2136 unsigned offchip_granularity;
2137 unsigned hs_offchip_param;
2138
2139 /*
2140 * Per RadeonSI:
2141 * This must be one less than the maximum number due to a hw limitation.
2142 * Various hardware bugs in SI, CIK, and GFX9 need this.
2143 *
2144 * Per AMDVLK:
2145 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2146 * Gfx7 should limit max_offchip_buffers to 508
2147 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2148 *
2149 * Follow AMDVLK here.
2150 */
2151 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2152 device->physical_device->rad_info.chip_class == CIK ||
2153 device->physical_device->rad_info.chip_class == SI)
2154 --max_offchip_buffers_per_se;
2155
2156 max_offchip_buffers = max_offchip_buffers_per_se *
2157 device->physical_device->rad_info.max_se;
2158
2159 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2160 * around by setting 4K granularity.
2161 */
2162 if (device->tess_offchip_block_dw_size == 4096) {
2163 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2164 offchip_granularity = V_03093C_X_4K_DWORDS;
2165 } else {
2166 assert(device->tess_offchip_block_dw_size == 8192);
2167 offchip_granularity = V_03093C_X_8K_DWORDS;
2168 }
2169
2170 switch (device->physical_device->rad_info.chip_class) {
2171 case SI:
2172 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2173 break;
2174 case CIK:
2175 case VI:
2176 case GFX9:
2177 default:
2178 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2179 break;
2180 }
2181
2182 *max_offchip_buffers_p = max_offchip_buffers;
2183 if (device->physical_device->rad_info.chip_class >= CIK) {
2184 if (device->physical_device->rad_info.chip_class >= VI)
2185 --max_offchip_buffers;
2186 hs_offchip_param =
2187 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2188 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2189 } else {
2190 hs_offchip_param =
2191 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2192 }
2193 return hs_offchip_param;
2194 }
2195
2196 static void
2197 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2198 struct radeon_winsys_bo *esgs_ring_bo,
2199 uint32_t esgs_ring_size,
2200 struct radeon_winsys_bo *gsvs_ring_bo,
2201 uint32_t gsvs_ring_size)
2202 {
2203 if (!esgs_ring_bo && !gsvs_ring_bo)
2204 return;
2205
2206 if (esgs_ring_bo)
2207 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2208
2209 if (gsvs_ring_bo)
2210 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2211
2212 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2213 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2214 radeon_emit(cs, esgs_ring_size >> 8);
2215 radeon_emit(cs, gsvs_ring_size >> 8);
2216 } else {
2217 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2218 radeon_emit(cs, esgs_ring_size >> 8);
2219 radeon_emit(cs, gsvs_ring_size >> 8);
2220 }
2221 }
2222
2223 static void
2224 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2225 unsigned hs_offchip_param, unsigned tf_ring_size,
2226 struct radeon_winsys_bo *tess_rings_bo)
2227 {
2228 uint64_t tf_va;
2229
2230 if (!tess_rings_bo)
2231 return;
2232
2233 tf_va = radv_buffer_get_va(tess_rings_bo);
2234
2235 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2236
2237 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2238 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2239 S_030938_SIZE(tf_ring_size / 4));
2240 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2241 tf_va >> 8);
2242 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2243 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2244 S_030944_BASE_HI(tf_va >> 40));
2245 }
2246 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2247 hs_offchip_param);
2248 } else {
2249 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2250 S_008988_SIZE(tf_ring_size / 4));
2251 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2252 tf_va >> 8);
2253 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2254 hs_offchip_param);
2255 }
2256 }
2257
2258 static void
2259 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2260 struct radeon_winsys_bo *compute_scratch_bo)
2261 {
2262 uint64_t scratch_va;
2263
2264 if (!compute_scratch_bo)
2265 return;
2266
2267 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2268
2269 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2270
2271 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2272 radeon_emit(cs, scratch_va);
2273 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2274 S_008F04_SWIZZLE_ENABLE(1));
2275 }
2276
2277 static void
2278 radv_emit_global_shader_pointers(struct radv_queue *queue,
2279 struct radeon_cmdbuf *cs,
2280 struct radeon_winsys_bo *descriptor_bo)
2281 {
2282 uint64_t va;
2283
2284 if (!descriptor_bo)
2285 return;
2286
2287 va = radv_buffer_get_va(descriptor_bo);
2288
2289 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2290
2291 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2292 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2293 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2294 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2295 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2296
2297 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2298 radv_emit_shader_pointer(queue->device, cs, regs[i],
2299 va, true);
2300 }
2301 } else {
2302 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2303 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2304 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2305 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2306 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2307 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2308
2309 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2310 radv_emit_shader_pointer(queue->device, cs, regs[i],
2311 va, true);
2312 }
2313 }
2314 }
2315
2316 static void
2317 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2318 {
2319 struct radv_device *device = queue->device;
2320
2321 if (device->gfx_init) {
2322 uint64_t va = radv_buffer_get_va(device->gfx_init);
2323
2324 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2325 radeon_emit(cs, va);
2326 radeon_emit(cs, va >> 32);
2327 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2328
2329 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2330 } else {
2331 struct radv_physical_device *physical_device = device->physical_device;
2332 si_emit_graphics(physical_device, cs);
2333 }
2334 }
2335
2336 static void
2337 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2338 {
2339 struct radv_physical_device *physical_device = queue->device->physical_device;
2340 si_emit_compute(physical_device, cs);
2341 }
2342
2343 static VkResult
2344 radv_get_preamble_cs(struct radv_queue *queue,
2345 uint32_t scratch_size,
2346 uint32_t compute_scratch_size,
2347 uint32_t esgs_ring_size,
2348 uint32_t gsvs_ring_size,
2349 bool needs_tess_rings,
2350 bool needs_sample_positions,
2351 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2352 struct radeon_cmdbuf **initial_preamble_cs,
2353 struct radeon_cmdbuf **continue_preamble_cs)
2354 {
2355 struct radeon_winsys_bo *scratch_bo = NULL;
2356 struct radeon_winsys_bo *descriptor_bo = NULL;
2357 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2358 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2359 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2360 struct radeon_winsys_bo *tess_rings_bo = NULL;
2361 struct radeon_cmdbuf *dest_cs[3] = {0};
2362 bool add_tess_rings = false, add_sample_positions = false;
2363 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2364 unsigned max_offchip_buffers;
2365 unsigned hs_offchip_param = 0;
2366 unsigned tess_offchip_ring_offset;
2367 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2368 if (!queue->has_tess_rings) {
2369 if (needs_tess_rings)
2370 add_tess_rings = true;
2371 }
2372 if (!queue->has_sample_positions) {
2373 if (needs_sample_positions)
2374 add_sample_positions = true;
2375 }
2376 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2377 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2378 &max_offchip_buffers);
2379 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2380 tess_offchip_ring_size = max_offchip_buffers *
2381 queue->device->tess_offchip_block_dw_size * 4;
2382
2383 if (scratch_size <= queue->scratch_size &&
2384 compute_scratch_size <= queue->compute_scratch_size &&
2385 esgs_ring_size <= queue->esgs_ring_size &&
2386 gsvs_ring_size <= queue->gsvs_ring_size &&
2387 !add_tess_rings && !add_sample_positions &&
2388 queue->initial_preamble_cs) {
2389 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2390 *initial_preamble_cs = queue->initial_preamble_cs;
2391 *continue_preamble_cs = queue->continue_preamble_cs;
2392 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2393 *continue_preamble_cs = NULL;
2394 return VK_SUCCESS;
2395 }
2396
2397 if (scratch_size > queue->scratch_size) {
2398 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2399 scratch_size,
2400 4096,
2401 RADEON_DOMAIN_VRAM,
2402 ring_bo_flags,
2403 RADV_BO_PRIORITY_SCRATCH);
2404 if (!scratch_bo)
2405 goto fail;
2406 } else
2407 scratch_bo = queue->scratch_bo;
2408
2409 if (compute_scratch_size > queue->compute_scratch_size) {
2410 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2411 compute_scratch_size,
2412 4096,
2413 RADEON_DOMAIN_VRAM,
2414 ring_bo_flags,
2415 RADV_BO_PRIORITY_SCRATCH);
2416 if (!compute_scratch_bo)
2417 goto fail;
2418
2419 } else
2420 compute_scratch_bo = queue->compute_scratch_bo;
2421
2422 if (esgs_ring_size > queue->esgs_ring_size) {
2423 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2424 esgs_ring_size,
2425 4096,
2426 RADEON_DOMAIN_VRAM,
2427 ring_bo_flags,
2428 RADV_BO_PRIORITY_SCRATCH);
2429 if (!esgs_ring_bo)
2430 goto fail;
2431 } else {
2432 esgs_ring_bo = queue->esgs_ring_bo;
2433 esgs_ring_size = queue->esgs_ring_size;
2434 }
2435
2436 if (gsvs_ring_size > queue->gsvs_ring_size) {
2437 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2438 gsvs_ring_size,
2439 4096,
2440 RADEON_DOMAIN_VRAM,
2441 ring_bo_flags,
2442 RADV_BO_PRIORITY_SCRATCH);
2443 if (!gsvs_ring_bo)
2444 goto fail;
2445 } else {
2446 gsvs_ring_bo = queue->gsvs_ring_bo;
2447 gsvs_ring_size = queue->gsvs_ring_size;
2448 }
2449
2450 if (add_tess_rings) {
2451 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2452 tess_offchip_ring_offset + tess_offchip_ring_size,
2453 256,
2454 RADEON_DOMAIN_VRAM,
2455 ring_bo_flags,
2456 RADV_BO_PRIORITY_SCRATCH);
2457 if (!tess_rings_bo)
2458 goto fail;
2459 } else {
2460 tess_rings_bo = queue->tess_rings_bo;
2461 }
2462
2463 if (scratch_bo != queue->scratch_bo ||
2464 esgs_ring_bo != queue->esgs_ring_bo ||
2465 gsvs_ring_bo != queue->gsvs_ring_bo ||
2466 tess_rings_bo != queue->tess_rings_bo ||
2467 add_sample_positions) {
2468 uint32_t size = 0;
2469 if (gsvs_ring_bo || esgs_ring_bo ||
2470 tess_rings_bo || add_sample_positions) {
2471 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2472 if (add_sample_positions)
2473 size += 128; /* 64+32+16+8 = 120 bytes */
2474 }
2475 else if (scratch_bo)
2476 size = 8; /* 2 dword */
2477
2478 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2479 size,
2480 4096,
2481 RADEON_DOMAIN_VRAM,
2482 RADEON_FLAG_CPU_ACCESS |
2483 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2484 RADEON_FLAG_READ_ONLY,
2485 RADV_BO_PRIORITY_DESCRIPTOR);
2486 if (!descriptor_bo)
2487 goto fail;
2488 } else
2489 descriptor_bo = queue->descriptor_bo;
2490
2491 if (descriptor_bo != queue->descriptor_bo) {
2492 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2493
2494 if (scratch_bo) {
2495 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2496 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2497 S_008F04_SWIZZLE_ENABLE(1);
2498 map[0] = scratch_va;
2499 map[1] = rsrc1;
2500 }
2501
2502 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2503 fill_geom_tess_rings(queue, map, add_sample_positions,
2504 esgs_ring_size, esgs_ring_bo,
2505 gsvs_ring_size, gsvs_ring_bo,
2506 tess_factor_ring_size,
2507 tess_offchip_ring_offset,
2508 tess_offchip_ring_size,
2509 tess_rings_bo);
2510
2511 queue->device->ws->buffer_unmap(descriptor_bo);
2512 }
2513
2514 for(int i = 0; i < 3; ++i) {
2515 struct radeon_cmdbuf *cs = NULL;
2516 cs = queue->device->ws->cs_create(queue->device->ws,
2517 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2518 if (!cs)
2519 goto fail;
2520
2521 dest_cs[i] = cs;
2522
2523 if (scratch_bo)
2524 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2525
2526 /* Emit initial configuration. */
2527 switch (queue->queue_family_index) {
2528 case RADV_QUEUE_GENERAL:
2529 radv_init_graphics_state(cs, queue);
2530 break;
2531 case RADV_QUEUE_COMPUTE:
2532 radv_init_compute_state(cs, queue);
2533 break;
2534 case RADV_QUEUE_TRANSFER:
2535 break;
2536 }
2537
2538 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2539 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2540 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2541 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2542 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2543 }
2544
2545 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2546 gsvs_ring_bo, gsvs_ring_size);
2547 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2548 tess_factor_ring_size, tess_rings_bo);
2549 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2550 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2551
2552 if (i == 0) {
2553 si_cs_emit_cache_flush(cs,
2554 queue->device->physical_device->rad_info.chip_class,
2555 NULL, 0,
2556 queue->queue_family_index == RING_COMPUTE &&
2557 queue->device->physical_device->rad_info.chip_class >= CIK,
2558 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2559 RADV_CMD_FLAG_INV_ICACHE |
2560 RADV_CMD_FLAG_INV_SMEM_L1 |
2561 RADV_CMD_FLAG_INV_VMEM_L1 |
2562 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2563 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2564 } else if (i == 1) {
2565 si_cs_emit_cache_flush(cs,
2566 queue->device->physical_device->rad_info.chip_class,
2567 NULL, 0,
2568 queue->queue_family_index == RING_COMPUTE &&
2569 queue->device->physical_device->rad_info.chip_class >= CIK,
2570 RADV_CMD_FLAG_INV_ICACHE |
2571 RADV_CMD_FLAG_INV_SMEM_L1 |
2572 RADV_CMD_FLAG_INV_VMEM_L1 |
2573 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2574 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2575 }
2576
2577 if (!queue->device->ws->cs_finalize(cs))
2578 goto fail;
2579 }
2580
2581 if (queue->initial_full_flush_preamble_cs)
2582 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2583
2584 if (queue->initial_preamble_cs)
2585 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2586
2587 if (queue->continue_preamble_cs)
2588 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2589
2590 queue->initial_full_flush_preamble_cs = dest_cs[0];
2591 queue->initial_preamble_cs = dest_cs[1];
2592 queue->continue_preamble_cs = dest_cs[2];
2593
2594 if (scratch_bo != queue->scratch_bo) {
2595 if (queue->scratch_bo)
2596 queue->device->ws->buffer_destroy(queue->scratch_bo);
2597 queue->scratch_bo = scratch_bo;
2598 queue->scratch_size = scratch_size;
2599 }
2600
2601 if (compute_scratch_bo != queue->compute_scratch_bo) {
2602 if (queue->compute_scratch_bo)
2603 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2604 queue->compute_scratch_bo = compute_scratch_bo;
2605 queue->compute_scratch_size = compute_scratch_size;
2606 }
2607
2608 if (esgs_ring_bo != queue->esgs_ring_bo) {
2609 if (queue->esgs_ring_bo)
2610 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2611 queue->esgs_ring_bo = esgs_ring_bo;
2612 queue->esgs_ring_size = esgs_ring_size;
2613 }
2614
2615 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2616 if (queue->gsvs_ring_bo)
2617 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2618 queue->gsvs_ring_bo = gsvs_ring_bo;
2619 queue->gsvs_ring_size = gsvs_ring_size;
2620 }
2621
2622 if (tess_rings_bo != queue->tess_rings_bo) {
2623 queue->tess_rings_bo = tess_rings_bo;
2624 queue->has_tess_rings = true;
2625 }
2626
2627 if (descriptor_bo != queue->descriptor_bo) {
2628 if (queue->descriptor_bo)
2629 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2630
2631 queue->descriptor_bo = descriptor_bo;
2632 }
2633
2634 if (add_sample_positions)
2635 queue->has_sample_positions = true;
2636
2637 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2638 *initial_preamble_cs = queue->initial_preamble_cs;
2639 *continue_preamble_cs = queue->continue_preamble_cs;
2640 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2641 *continue_preamble_cs = NULL;
2642 return VK_SUCCESS;
2643 fail:
2644 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2645 if (dest_cs[i])
2646 queue->device->ws->cs_destroy(dest_cs[i]);
2647 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2648 queue->device->ws->buffer_destroy(descriptor_bo);
2649 if (scratch_bo && scratch_bo != queue->scratch_bo)
2650 queue->device->ws->buffer_destroy(scratch_bo);
2651 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2652 queue->device->ws->buffer_destroy(compute_scratch_bo);
2653 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2654 queue->device->ws->buffer_destroy(esgs_ring_bo);
2655 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2656 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2657 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2658 queue->device->ws->buffer_destroy(tess_rings_bo);
2659 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2660 }
2661
2662 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2663 struct radv_winsys_sem_counts *counts,
2664 int num_sems,
2665 const VkSemaphore *sems,
2666 VkFence _fence,
2667 bool reset_temp)
2668 {
2669 int syncobj_idx = 0, sem_idx = 0;
2670
2671 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2672 return VK_SUCCESS;
2673
2674 for (uint32_t i = 0; i < num_sems; i++) {
2675 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2676
2677 if (sem->temp_syncobj || sem->syncobj)
2678 counts->syncobj_count++;
2679 else
2680 counts->sem_count++;
2681 }
2682
2683 if (_fence != VK_NULL_HANDLE) {
2684 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2685 if (fence->temp_syncobj || fence->syncobj)
2686 counts->syncobj_count++;
2687 }
2688
2689 if (counts->syncobj_count) {
2690 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2691 if (!counts->syncobj)
2692 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2693 }
2694
2695 if (counts->sem_count) {
2696 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2697 if (!counts->sem) {
2698 free(counts->syncobj);
2699 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2700 }
2701 }
2702
2703 for (uint32_t i = 0; i < num_sems; i++) {
2704 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2705
2706 if (sem->temp_syncobj) {
2707 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2708 }
2709 else if (sem->syncobj)
2710 counts->syncobj[syncobj_idx++] = sem->syncobj;
2711 else {
2712 assert(sem->sem);
2713 counts->sem[sem_idx++] = sem->sem;
2714 }
2715 }
2716
2717 if (_fence != VK_NULL_HANDLE) {
2718 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2719 if (fence->temp_syncobj)
2720 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2721 else if (fence->syncobj)
2722 counts->syncobj[syncobj_idx++] = fence->syncobj;
2723 }
2724
2725 return VK_SUCCESS;
2726 }
2727
2728 static void
2729 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2730 {
2731 free(sem_info->wait.syncobj);
2732 free(sem_info->wait.sem);
2733 free(sem_info->signal.syncobj);
2734 free(sem_info->signal.sem);
2735 }
2736
2737
2738 static void radv_free_temp_syncobjs(struct radv_device *device,
2739 int num_sems,
2740 const VkSemaphore *sems)
2741 {
2742 for (uint32_t i = 0; i < num_sems; i++) {
2743 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2744
2745 if (sem->temp_syncobj) {
2746 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2747 sem->temp_syncobj = 0;
2748 }
2749 }
2750 }
2751
2752 static VkResult
2753 radv_alloc_sem_info(struct radv_instance *instance,
2754 struct radv_winsys_sem_info *sem_info,
2755 int num_wait_sems,
2756 const VkSemaphore *wait_sems,
2757 int num_signal_sems,
2758 const VkSemaphore *signal_sems,
2759 VkFence fence)
2760 {
2761 VkResult ret;
2762 memset(sem_info, 0, sizeof(*sem_info));
2763
2764 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2765 if (ret)
2766 return ret;
2767 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2768 if (ret)
2769 radv_free_sem_info(sem_info);
2770
2771 /* caller can override these */
2772 sem_info->cs_emit_wait = true;
2773 sem_info->cs_emit_signal = true;
2774 return ret;
2775 }
2776
2777 /* Signals fence as soon as all the work currently put on queue is done. */
2778 static VkResult radv_signal_fence(struct radv_queue *queue,
2779 struct radv_fence *fence)
2780 {
2781 int ret;
2782 VkResult result;
2783 struct radv_winsys_sem_info sem_info;
2784
2785 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2786 radv_fence_to_handle(fence));
2787 if (result != VK_SUCCESS)
2788 return result;
2789
2790 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2791 &queue->device->empty_cs[queue->queue_family_index],
2792 1, NULL, NULL, &sem_info, NULL,
2793 false, fence->fence);
2794 radv_free_sem_info(&sem_info);
2795
2796 if (ret)
2797 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2798
2799 return VK_SUCCESS;
2800 }
2801
2802 VkResult radv_QueueSubmit(
2803 VkQueue _queue,
2804 uint32_t submitCount,
2805 const VkSubmitInfo* pSubmits,
2806 VkFence _fence)
2807 {
2808 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2809 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2810 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2811 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2812 int ret;
2813 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2814 uint32_t scratch_size = 0;
2815 uint32_t compute_scratch_size = 0;
2816 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2817 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2818 VkResult result;
2819 bool fence_emitted = false;
2820 bool tess_rings_needed = false;
2821 bool sample_positions_needed = false;
2822
2823 /* Do this first so failing to allocate scratch buffers can't result in
2824 * partially executed submissions. */
2825 for (uint32_t i = 0; i < submitCount; i++) {
2826 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2827 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2828 pSubmits[i].pCommandBuffers[j]);
2829
2830 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2831 compute_scratch_size = MAX2(compute_scratch_size,
2832 cmd_buffer->compute_scratch_size_needed);
2833 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2834 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2835 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2836 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2837 }
2838 }
2839
2840 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2841 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2842 sample_positions_needed, &initial_flush_preamble_cs,
2843 &initial_preamble_cs, &continue_preamble_cs);
2844 if (result != VK_SUCCESS)
2845 return result;
2846
2847 for (uint32_t i = 0; i < submitCount; i++) {
2848 struct radeon_cmdbuf **cs_array;
2849 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2850 bool can_patch = true;
2851 uint32_t advance;
2852 struct radv_winsys_sem_info sem_info;
2853
2854 result = radv_alloc_sem_info(queue->device->instance,
2855 &sem_info,
2856 pSubmits[i].waitSemaphoreCount,
2857 pSubmits[i].pWaitSemaphores,
2858 pSubmits[i].signalSemaphoreCount,
2859 pSubmits[i].pSignalSemaphores,
2860 _fence);
2861 if (result != VK_SUCCESS)
2862 return result;
2863
2864 if (!pSubmits[i].commandBufferCount) {
2865 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2866 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2867 &queue->device->empty_cs[queue->queue_family_index],
2868 1, NULL, NULL,
2869 &sem_info, NULL,
2870 false, base_fence);
2871 if (ret) {
2872 radv_loge("failed to submit CS %d\n", i);
2873 abort();
2874 }
2875 fence_emitted = true;
2876 }
2877 radv_free_sem_info(&sem_info);
2878 continue;
2879 }
2880
2881 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2882 (pSubmits[i].commandBufferCount));
2883
2884 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2885 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2886 pSubmits[i].pCommandBuffers[j]);
2887 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2888
2889 cs_array[j] = cmd_buffer->cs;
2890 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2891 can_patch = false;
2892
2893 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2894 }
2895
2896 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2897 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2898 const struct radv_winsys_bo_list *bo_list = NULL;
2899
2900 advance = MIN2(max_cs_submission,
2901 pSubmits[i].commandBufferCount - j);
2902
2903 if (queue->device->trace_bo)
2904 *queue->device->trace_id_ptr = 0;
2905
2906 sem_info.cs_emit_wait = j == 0;
2907 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2908
2909 if (unlikely(queue->device->use_global_bo_list)) {
2910 pthread_mutex_lock(&queue->device->bo_list.mutex);
2911 bo_list = &queue->device->bo_list.list;
2912 }
2913
2914 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2915 advance, initial_preamble, continue_preamble_cs,
2916 &sem_info, bo_list,
2917 can_patch, base_fence);
2918
2919 if (unlikely(queue->device->use_global_bo_list))
2920 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2921
2922 if (ret) {
2923 radv_loge("failed to submit CS %d\n", i);
2924 abort();
2925 }
2926 fence_emitted = true;
2927 if (queue->device->trace_bo) {
2928 radv_check_gpu_hangs(queue, cs_array[j]);
2929 }
2930 }
2931
2932 radv_free_temp_syncobjs(queue->device,
2933 pSubmits[i].waitSemaphoreCount,
2934 pSubmits[i].pWaitSemaphores);
2935 radv_free_sem_info(&sem_info);
2936 free(cs_array);
2937 }
2938
2939 if (fence) {
2940 if (!fence_emitted) {
2941 result = radv_signal_fence(queue, fence);
2942 if (result != VK_SUCCESS)
2943 return result;
2944 }
2945 fence->submitted = true;
2946 }
2947
2948 return VK_SUCCESS;
2949 }
2950
2951 VkResult radv_QueueWaitIdle(
2952 VkQueue _queue)
2953 {
2954 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2955
2956 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2957 radv_queue_family_to_ring(queue->queue_family_index),
2958 queue->queue_idx);
2959 return VK_SUCCESS;
2960 }
2961
2962 VkResult radv_DeviceWaitIdle(
2963 VkDevice _device)
2964 {
2965 RADV_FROM_HANDLE(radv_device, device, _device);
2966
2967 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2968 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2969 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2970 }
2971 }
2972 return VK_SUCCESS;
2973 }
2974
2975 VkResult radv_EnumerateInstanceExtensionProperties(
2976 const char* pLayerName,
2977 uint32_t* pPropertyCount,
2978 VkExtensionProperties* pProperties)
2979 {
2980 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2981
2982 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2983 if (radv_supported_instance_extensions.extensions[i]) {
2984 vk_outarray_append(&out, prop) {
2985 *prop = radv_instance_extensions[i];
2986 }
2987 }
2988 }
2989
2990 return vk_outarray_status(&out);
2991 }
2992
2993 VkResult radv_EnumerateDeviceExtensionProperties(
2994 VkPhysicalDevice physicalDevice,
2995 const char* pLayerName,
2996 uint32_t* pPropertyCount,
2997 VkExtensionProperties* pProperties)
2998 {
2999 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3000 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3001
3002 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3003 if (device->supported_extensions.extensions[i]) {
3004 vk_outarray_append(&out, prop) {
3005 *prop = radv_device_extensions[i];
3006 }
3007 }
3008 }
3009
3010 return vk_outarray_status(&out);
3011 }
3012
3013 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3014 VkInstance _instance,
3015 const char* pName)
3016 {
3017 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3018
3019 return radv_lookup_entrypoint_checked(pName,
3020 instance ? instance->apiVersion : 0,
3021 instance ? &instance->enabled_extensions : NULL,
3022 NULL);
3023 }
3024
3025 /* The loader wants us to expose a second GetInstanceProcAddr function
3026 * to work around certain LD_PRELOAD issues seen in apps.
3027 */
3028 PUBLIC
3029 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3030 VkInstance instance,
3031 const char* pName);
3032
3033 PUBLIC
3034 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3035 VkInstance instance,
3036 const char* pName)
3037 {
3038 return radv_GetInstanceProcAddr(instance, pName);
3039 }
3040
3041 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3042 VkDevice _device,
3043 const char* pName)
3044 {
3045 RADV_FROM_HANDLE(radv_device, device, _device);
3046
3047 return radv_lookup_entrypoint_checked(pName,
3048 device->instance->apiVersion,
3049 &device->instance->enabled_extensions,
3050 &device->enabled_extensions);
3051 }
3052
3053 bool radv_get_memory_fd(struct radv_device *device,
3054 struct radv_device_memory *memory,
3055 int *pFD)
3056 {
3057 struct radeon_bo_metadata metadata;
3058
3059 if (memory->image) {
3060 radv_init_metadata(device, memory->image, &metadata);
3061 device->ws->buffer_set_metadata(memory->bo, &metadata);
3062 }
3063
3064 return device->ws->buffer_get_fd(device->ws, memory->bo,
3065 pFD);
3066 }
3067
3068 static VkResult radv_alloc_memory(struct radv_device *device,
3069 const VkMemoryAllocateInfo* pAllocateInfo,
3070 const VkAllocationCallbacks* pAllocator,
3071 VkDeviceMemory* pMem)
3072 {
3073 struct radv_device_memory *mem;
3074 VkResult result;
3075 enum radeon_bo_domain domain;
3076 uint32_t flags = 0;
3077 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3078
3079 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3080
3081 if (pAllocateInfo->allocationSize == 0) {
3082 /* Apparently, this is allowed */
3083 *pMem = VK_NULL_HANDLE;
3084 return VK_SUCCESS;
3085 }
3086
3087 const VkImportMemoryFdInfoKHR *import_info =
3088 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3089 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3090 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3091 const VkExportMemoryAllocateInfo *export_info =
3092 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3093 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3094 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3095
3096 const struct wsi_memory_allocate_info *wsi_info =
3097 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3098
3099 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3100 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3101 if (mem == NULL)
3102 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3103
3104 if (wsi_info && wsi_info->implicit_sync)
3105 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3106
3107 if (dedicate_info) {
3108 mem->image = radv_image_from_handle(dedicate_info->image);
3109 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3110 } else {
3111 mem->image = NULL;
3112 mem->buffer = NULL;
3113 }
3114
3115 float priority_float = 0.5;
3116 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3117 vk_find_struct_const(pAllocateInfo->pNext,
3118 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3119 if (priority_ext)
3120 priority_float = priority_ext->priority;
3121
3122 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3123 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3124
3125 mem->user_ptr = NULL;
3126
3127 if (import_info) {
3128 assert(import_info->handleType ==
3129 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3130 import_info->handleType ==
3131 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3132 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3133 priority, NULL, NULL);
3134 if (!mem->bo) {
3135 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3136 goto fail;
3137 } else {
3138 close(import_info->fd);
3139 }
3140 } else if (host_ptr_info) {
3141 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3142 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3143 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3144 pAllocateInfo->allocationSize,
3145 priority);
3146 if (!mem->bo) {
3147 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3148 goto fail;
3149 } else {
3150 mem->user_ptr = host_ptr_info->pHostPointer;
3151 }
3152 } else {
3153 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3154 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3155 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3156 domain = RADEON_DOMAIN_GTT;
3157 else
3158 domain = RADEON_DOMAIN_VRAM;
3159
3160 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3161 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3162 else
3163 flags |= RADEON_FLAG_CPU_ACCESS;
3164
3165 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3166 flags |= RADEON_FLAG_GTT_WC;
3167
3168 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3169 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3170
3171 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3172 domain, flags, priority);
3173
3174 if (!mem->bo) {
3175 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3176 goto fail;
3177 }
3178 mem->type_index = mem_type_index;
3179 }
3180
3181 result = radv_bo_list_add(device, mem->bo);
3182 if (result != VK_SUCCESS)
3183 goto fail_bo;
3184
3185 *pMem = radv_device_memory_to_handle(mem);
3186
3187 return VK_SUCCESS;
3188
3189 fail_bo:
3190 device->ws->buffer_destroy(mem->bo);
3191 fail:
3192 vk_free2(&device->alloc, pAllocator, mem);
3193
3194 return result;
3195 }
3196
3197 VkResult radv_AllocateMemory(
3198 VkDevice _device,
3199 const VkMemoryAllocateInfo* pAllocateInfo,
3200 const VkAllocationCallbacks* pAllocator,
3201 VkDeviceMemory* pMem)
3202 {
3203 RADV_FROM_HANDLE(radv_device, device, _device);
3204 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3205 }
3206
3207 void radv_FreeMemory(
3208 VkDevice _device,
3209 VkDeviceMemory _mem,
3210 const VkAllocationCallbacks* pAllocator)
3211 {
3212 RADV_FROM_HANDLE(radv_device, device, _device);
3213 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3214
3215 if (mem == NULL)
3216 return;
3217
3218 radv_bo_list_remove(device, mem->bo);
3219 device->ws->buffer_destroy(mem->bo);
3220 mem->bo = NULL;
3221
3222 vk_free2(&device->alloc, pAllocator, mem);
3223 }
3224
3225 VkResult radv_MapMemory(
3226 VkDevice _device,
3227 VkDeviceMemory _memory,
3228 VkDeviceSize offset,
3229 VkDeviceSize size,
3230 VkMemoryMapFlags flags,
3231 void** ppData)
3232 {
3233 RADV_FROM_HANDLE(radv_device, device, _device);
3234 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3235
3236 if (mem == NULL) {
3237 *ppData = NULL;
3238 return VK_SUCCESS;
3239 }
3240
3241 if (mem->user_ptr)
3242 *ppData = mem->user_ptr;
3243 else
3244 *ppData = device->ws->buffer_map(mem->bo);
3245
3246 if (*ppData) {
3247 *ppData += offset;
3248 return VK_SUCCESS;
3249 }
3250
3251 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3252 }
3253
3254 void radv_UnmapMemory(
3255 VkDevice _device,
3256 VkDeviceMemory _memory)
3257 {
3258 RADV_FROM_HANDLE(radv_device, device, _device);
3259 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3260
3261 if (mem == NULL)
3262 return;
3263
3264 if (mem->user_ptr == NULL)
3265 device->ws->buffer_unmap(mem->bo);
3266 }
3267
3268 VkResult radv_FlushMappedMemoryRanges(
3269 VkDevice _device,
3270 uint32_t memoryRangeCount,
3271 const VkMappedMemoryRange* pMemoryRanges)
3272 {
3273 return VK_SUCCESS;
3274 }
3275
3276 VkResult radv_InvalidateMappedMemoryRanges(
3277 VkDevice _device,
3278 uint32_t memoryRangeCount,
3279 const VkMappedMemoryRange* pMemoryRanges)
3280 {
3281 return VK_SUCCESS;
3282 }
3283
3284 void radv_GetBufferMemoryRequirements(
3285 VkDevice _device,
3286 VkBuffer _buffer,
3287 VkMemoryRequirements* pMemoryRequirements)
3288 {
3289 RADV_FROM_HANDLE(radv_device, device, _device);
3290 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3291
3292 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3293
3294 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3295 pMemoryRequirements->alignment = 4096;
3296 else
3297 pMemoryRequirements->alignment = 16;
3298
3299 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3300 }
3301
3302 void radv_GetBufferMemoryRequirements2(
3303 VkDevice device,
3304 const VkBufferMemoryRequirementsInfo2 *pInfo,
3305 VkMemoryRequirements2 *pMemoryRequirements)
3306 {
3307 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3308 &pMemoryRequirements->memoryRequirements);
3309 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3310 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3311 switch (ext->sType) {
3312 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3313 VkMemoryDedicatedRequirements *req =
3314 (VkMemoryDedicatedRequirements *) ext;
3315 req->requiresDedicatedAllocation = buffer->shareable;
3316 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3317 break;
3318 }
3319 default:
3320 break;
3321 }
3322 }
3323 }
3324
3325 void radv_GetImageMemoryRequirements(
3326 VkDevice _device,
3327 VkImage _image,
3328 VkMemoryRequirements* pMemoryRequirements)
3329 {
3330 RADV_FROM_HANDLE(radv_device, device, _device);
3331 RADV_FROM_HANDLE(radv_image, image, _image);
3332
3333 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3334
3335 pMemoryRequirements->size = image->size;
3336 pMemoryRequirements->alignment = image->alignment;
3337 }
3338
3339 void radv_GetImageMemoryRequirements2(
3340 VkDevice device,
3341 const VkImageMemoryRequirementsInfo2 *pInfo,
3342 VkMemoryRequirements2 *pMemoryRequirements)
3343 {
3344 radv_GetImageMemoryRequirements(device, pInfo->image,
3345 &pMemoryRequirements->memoryRequirements);
3346
3347 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3348
3349 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3350 switch (ext->sType) {
3351 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3352 VkMemoryDedicatedRequirements *req =
3353 (VkMemoryDedicatedRequirements *) ext;
3354 req->requiresDedicatedAllocation = image->shareable;
3355 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3356 break;
3357 }
3358 default:
3359 break;
3360 }
3361 }
3362 }
3363
3364 void radv_GetImageSparseMemoryRequirements(
3365 VkDevice device,
3366 VkImage image,
3367 uint32_t* pSparseMemoryRequirementCount,
3368 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3369 {
3370 stub();
3371 }
3372
3373 void radv_GetImageSparseMemoryRequirements2(
3374 VkDevice device,
3375 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3376 uint32_t* pSparseMemoryRequirementCount,
3377 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3378 {
3379 stub();
3380 }
3381
3382 void radv_GetDeviceMemoryCommitment(
3383 VkDevice device,
3384 VkDeviceMemory memory,
3385 VkDeviceSize* pCommittedMemoryInBytes)
3386 {
3387 *pCommittedMemoryInBytes = 0;
3388 }
3389
3390 VkResult radv_BindBufferMemory2(VkDevice device,
3391 uint32_t bindInfoCount,
3392 const VkBindBufferMemoryInfo *pBindInfos)
3393 {
3394 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3395 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3396 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3397
3398 if (mem) {
3399 buffer->bo = mem->bo;
3400 buffer->offset = pBindInfos[i].memoryOffset;
3401 } else {
3402 buffer->bo = NULL;
3403 }
3404 }
3405 return VK_SUCCESS;
3406 }
3407
3408 VkResult radv_BindBufferMemory(
3409 VkDevice device,
3410 VkBuffer buffer,
3411 VkDeviceMemory memory,
3412 VkDeviceSize memoryOffset)
3413 {
3414 const VkBindBufferMemoryInfo info = {
3415 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3416 .buffer = buffer,
3417 .memory = memory,
3418 .memoryOffset = memoryOffset
3419 };
3420
3421 return radv_BindBufferMemory2(device, 1, &info);
3422 }
3423
3424 VkResult radv_BindImageMemory2(VkDevice device,
3425 uint32_t bindInfoCount,
3426 const VkBindImageMemoryInfo *pBindInfos)
3427 {
3428 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3429 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3430 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3431
3432 if (mem) {
3433 image->bo = mem->bo;
3434 image->offset = pBindInfos[i].memoryOffset;
3435 } else {
3436 image->bo = NULL;
3437 image->offset = 0;
3438 }
3439 }
3440 return VK_SUCCESS;
3441 }
3442
3443
3444 VkResult radv_BindImageMemory(
3445 VkDevice device,
3446 VkImage image,
3447 VkDeviceMemory memory,
3448 VkDeviceSize memoryOffset)
3449 {
3450 const VkBindImageMemoryInfo info = {
3451 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3452 .image = image,
3453 .memory = memory,
3454 .memoryOffset = memoryOffset
3455 };
3456
3457 return radv_BindImageMemory2(device, 1, &info);
3458 }
3459
3460
3461 static void
3462 radv_sparse_buffer_bind_memory(struct radv_device *device,
3463 const VkSparseBufferMemoryBindInfo *bind)
3464 {
3465 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3466
3467 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3468 struct radv_device_memory *mem = NULL;
3469
3470 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3471 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3472
3473 device->ws->buffer_virtual_bind(buffer->bo,
3474 bind->pBinds[i].resourceOffset,
3475 bind->pBinds[i].size,
3476 mem ? mem->bo : NULL,
3477 bind->pBinds[i].memoryOffset);
3478 }
3479 }
3480
3481 static void
3482 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3483 const VkSparseImageOpaqueMemoryBindInfo *bind)
3484 {
3485 RADV_FROM_HANDLE(radv_image, image, bind->image);
3486
3487 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3488 struct radv_device_memory *mem = NULL;
3489
3490 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3491 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3492
3493 device->ws->buffer_virtual_bind(image->bo,
3494 bind->pBinds[i].resourceOffset,
3495 bind->pBinds[i].size,
3496 mem ? mem->bo : NULL,
3497 bind->pBinds[i].memoryOffset);
3498 }
3499 }
3500
3501 VkResult radv_QueueBindSparse(
3502 VkQueue _queue,
3503 uint32_t bindInfoCount,
3504 const VkBindSparseInfo* pBindInfo,
3505 VkFence _fence)
3506 {
3507 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3508 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3509 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3510 bool fence_emitted = false;
3511 VkResult result;
3512 int ret;
3513
3514 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3515 struct radv_winsys_sem_info sem_info;
3516 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3517 radv_sparse_buffer_bind_memory(queue->device,
3518 pBindInfo[i].pBufferBinds + j);
3519 }
3520
3521 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3522 radv_sparse_image_opaque_bind_memory(queue->device,
3523 pBindInfo[i].pImageOpaqueBinds + j);
3524 }
3525
3526 VkResult result;
3527 result = radv_alloc_sem_info(queue->device->instance,
3528 &sem_info,
3529 pBindInfo[i].waitSemaphoreCount,
3530 pBindInfo[i].pWaitSemaphores,
3531 pBindInfo[i].signalSemaphoreCount,
3532 pBindInfo[i].pSignalSemaphores,
3533 _fence);
3534 if (result != VK_SUCCESS)
3535 return result;
3536
3537 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3538 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3539 &queue->device->empty_cs[queue->queue_family_index],
3540 1, NULL, NULL,
3541 &sem_info, NULL,
3542 false, base_fence);
3543 if (ret) {
3544 radv_loge("failed to submit CS %d\n", i);
3545 abort();
3546 }
3547
3548 fence_emitted = true;
3549 if (fence)
3550 fence->submitted = true;
3551 }
3552
3553 radv_free_sem_info(&sem_info);
3554
3555 }
3556
3557 if (fence) {
3558 if (!fence_emitted) {
3559 result = radv_signal_fence(queue, fence);
3560 if (result != VK_SUCCESS)
3561 return result;
3562 }
3563 fence->submitted = true;
3564 }
3565
3566 return VK_SUCCESS;
3567 }
3568
3569 VkResult radv_CreateFence(
3570 VkDevice _device,
3571 const VkFenceCreateInfo* pCreateInfo,
3572 const VkAllocationCallbacks* pAllocator,
3573 VkFence* pFence)
3574 {
3575 RADV_FROM_HANDLE(radv_device, device, _device);
3576 const VkExportFenceCreateInfo *export =
3577 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3578 VkExternalFenceHandleTypeFlags handleTypes =
3579 export ? export->handleTypes : 0;
3580
3581 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3582 sizeof(*fence), 8,
3583 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3584
3585 if (!fence)
3586 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3587
3588 fence->fence_wsi = NULL;
3589 fence->submitted = false;
3590 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3591 fence->temp_syncobj = 0;
3592 if (device->always_use_syncobj || handleTypes) {
3593 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3594 if (ret) {
3595 vk_free2(&device->alloc, pAllocator, fence);
3596 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3597 }
3598 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3599 device->ws->signal_syncobj(device->ws, fence->syncobj);
3600 }
3601 fence->fence = NULL;
3602 } else {
3603 fence->fence = device->ws->create_fence();
3604 if (!fence->fence) {
3605 vk_free2(&device->alloc, pAllocator, fence);
3606 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3607 }
3608 fence->syncobj = 0;
3609 }
3610
3611 *pFence = radv_fence_to_handle(fence);
3612
3613 return VK_SUCCESS;
3614 }
3615
3616 void radv_DestroyFence(
3617 VkDevice _device,
3618 VkFence _fence,
3619 const VkAllocationCallbacks* pAllocator)
3620 {
3621 RADV_FROM_HANDLE(radv_device, device, _device);
3622 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3623
3624 if (!fence)
3625 return;
3626
3627 if (fence->temp_syncobj)
3628 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3629 if (fence->syncobj)
3630 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3631 if (fence->fence)
3632 device->ws->destroy_fence(fence->fence);
3633 if (fence->fence_wsi)
3634 fence->fence_wsi->destroy(fence->fence_wsi);
3635 vk_free2(&device->alloc, pAllocator, fence);
3636 }
3637
3638
3639 static uint64_t radv_get_current_time()
3640 {
3641 struct timespec tv;
3642 clock_gettime(CLOCK_MONOTONIC, &tv);
3643 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3644 }
3645
3646 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3647 {
3648 uint64_t current_time = radv_get_current_time();
3649
3650 timeout = MIN2(UINT64_MAX - current_time, timeout);
3651
3652 return current_time + timeout;
3653 }
3654
3655
3656 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3657 {
3658 for (uint32_t i = 0; i < fenceCount; ++i) {
3659 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3660 if (fence->fence == NULL || fence->syncobj ||
3661 fence->temp_syncobj ||
3662 (!fence->signalled && !fence->submitted))
3663 return false;
3664 }
3665 return true;
3666 }
3667
3668 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3669 {
3670 for (uint32_t i = 0; i < fenceCount; ++i) {
3671 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3672 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3673 return false;
3674 }
3675 return true;
3676 }
3677
3678 VkResult radv_WaitForFences(
3679 VkDevice _device,
3680 uint32_t fenceCount,
3681 const VkFence* pFences,
3682 VkBool32 waitAll,
3683 uint64_t timeout)
3684 {
3685 RADV_FROM_HANDLE(radv_device, device, _device);
3686 timeout = radv_get_absolute_timeout(timeout);
3687
3688 if (device->always_use_syncobj &&
3689 radv_all_fences_syncobj(fenceCount, pFences))
3690 {
3691 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3692 if (!handles)
3693 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3694
3695 for (uint32_t i = 0; i < fenceCount; ++i) {
3696 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3697 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3698 }
3699
3700 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3701
3702 free(handles);
3703 return success ? VK_SUCCESS : VK_TIMEOUT;
3704 }
3705
3706 if (!waitAll && fenceCount > 1) {
3707 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3708 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3709 uint32_t wait_count = 0;
3710 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3711 if (!fences)
3712 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3713
3714 for (uint32_t i = 0; i < fenceCount; ++i) {
3715 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3716
3717 if (fence->signalled) {
3718 free(fences);
3719 return VK_SUCCESS;
3720 }
3721
3722 fences[wait_count++] = fence->fence;
3723 }
3724
3725 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3726 waitAll, timeout - radv_get_current_time());
3727
3728 free(fences);
3729 return success ? VK_SUCCESS : VK_TIMEOUT;
3730 }
3731
3732 while(radv_get_current_time() <= timeout) {
3733 for (uint32_t i = 0; i < fenceCount; ++i) {
3734 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3735 return VK_SUCCESS;
3736 }
3737 }
3738 return VK_TIMEOUT;
3739 }
3740
3741 for (uint32_t i = 0; i < fenceCount; ++i) {
3742 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3743 bool expired = false;
3744
3745 if (fence->temp_syncobj) {
3746 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3747 return VK_TIMEOUT;
3748 continue;
3749 }
3750
3751 if (fence->syncobj) {
3752 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3753 return VK_TIMEOUT;
3754 continue;
3755 }
3756
3757 if (fence->signalled)
3758 continue;
3759
3760 if (fence->fence) {
3761 if (!fence->submitted) {
3762 while(radv_get_current_time() <= timeout &&
3763 !fence->submitted)
3764 /* Do nothing */;
3765
3766 if (!fence->submitted)
3767 return VK_TIMEOUT;
3768
3769 /* Recheck as it may have been set by
3770 * submitting operations. */
3771
3772 if (fence->signalled)
3773 continue;
3774 }
3775
3776 expired = device->ws->fence_wait(device->ws,
3777 fence->fence,
3778 true, timeout);
3779 if (!expired)
3780 return VK_TIMEOUT;
3781 }
3782
3783 if (fence->fence_wsi) {
3784 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3785 if (result != VK_SUCCESS)
3786 return result;
3787 }
3788
3789 fence->signalled = true;
3790 }
3791
3792 return VK_SUCCESS;
3793 }
3794
3795 VkResult radv_ResetFences(VkDevice _device,
3796 uint32_t fenceCount,
3797 const VkFence *pFences)
3798 {
3799 RADV_FROM_HANDLE(radv_device, device, _device);
3800
3801 for (unsigned i = 0; i < fenceCount; ++i) {
3802 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3803 fence->submitted = fence->signalled = false;
3804
3805 /* Per spec, we first restore the permanent payload, and then reset, so
3806 * having a temp syncobj should not skip resetting the permanent syncobj. */
3807 if (fence->temp_syncobj) {
3808 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3809 fence->temp_syncobj = 0;
3810 }
3811
3812 if (fence->syncobj) {
3813 device->ws->reset_syncobj(device->ws, fence->syncobj);
3814 }
3815 }
3816
3817 return VK_SUCCESS;
3818 }
3819
3820 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3821 {
3822 RADV_FROM_HANDLE(radv_device, device, _device);
3823 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3824
3825 if (fence->temp_syncobj) {
3826 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3827 return success ? VK_SUCCESS : VK_NOT_READY;
3828 }
3829
3830 if (fence->syncobj) {
3831 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3832 return success ? VK_SUCCESS : VK_NOT_READY;
3833 }
3834
3835 if (fence->signalled)
3836 return VK_SUCCESS;
3837 if (!fence->submitted)
3838 return VK_NOT_READY;
3839 if (fence->fence) {
3840 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3841 return VK_NOT_READY;
3842 }
3843 if (fence->fence_wsi) {
3844 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3845
3846 if (result != VK_SUCCESS) {
3847 if (result == VK_TIMEOUT)
3848 return VK_NOT_READY;
3849 return result;
3850 }
3851 }
3852 return VK_SUCCESS;
3853 }
3854
3855
3856 // Queue semaphore functions
3857
3858 VkResult radv_CreateSemaphore(
3859 VkDevice _device,
3860 const VkSemaphoreCreateInfo* pCreateInfo,
3861 const VkAllocationCallbacks* pAllocator,
3862 VkSemaphore* pSemaphore)
3863 {
3864 RADV_FROM_HANDLE(radv_device, device, _device);
3865 const VkExportSemaphoreCreateInfo *export =
3866 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3867 VkExternalSemaphoreHandleTypeFlags handleTypes =
3868 export ? export->handleTypes : 0;
3869
3870 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3871 sizeof(*sem), 8,
3872 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3873 if (!sem)
3874 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3875
3876 sem->temp_syncobj = 0;
3877 /* create a syncobject if we are going to export this semaphore */
3878 if (device->always_use_syncobj || handleTypes) {
3879 assert (device->physical_device->rad_info.has_syncobj);
3880 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3881 if (ret) {
3882 vk_free2(&device->alloc, pAllocator, sem);
3883 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3884 }
3885 sem->sem = NULL;
3886 } else {
3887 sem->sem = device->ws->create_sem(device->ws);
3888 if (!sem->sem) {
3889 vk_free2(&device->alloc, pAllocator, sem);
3890 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3891 }
3892 sem->syncobj = 0;
3893 }
3894
3895 *pSemaphore = radv_semaphore_to_handle(sem);
3896 return VK_SUCCESS;
3897 }
3898
3899 void radv_DestroySemaphore(
3900 VkDevice _device,
3901 VkSemaphore _semaphore,
3902 const VkAllocationCallbacks* pAllocator)
3903 {
3904 RADV_FROM_HANDLE(radv_device, device, _device);
3905 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3906 if (!_semaphore)
3907 return;
3908
3909 if (sem->syncobj)
3910 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3911 else
3912 device->ws->destroy_sem(sem->sem);
3913 vk_free2(&device->alloc, pAllocator, sem);
3914 }
3915
3916 VkResult radv_CreateEvent(
3917 VkDevice _device,
3918 const VkEventCreateInfo* pCreateInfo,
3919 const VkAllocationCallbacks* pAllocator,
3920 VkEvent* pEvent)
3921 {
3922 RADV_FROM_HANDLE(radv_device, device, _device);
3923 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3924 sizeof(*event), 8,
3925 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3926
3927 if (!event)
3928 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3929
3930 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3931 RADEON_DOMAIN_GTT,
3932 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3933 RADV_BO_PRIORITY_FENCE);
3934 if (!event->bo) {
3935 vk_free2(&device->alloc, pAllocator, event);
3936 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3937 }
3938
3939 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3940
3941 *pEvent = radv_event_to_handle(event);
3942
3943 return VK_SUCCESS;
3944 }
3945
3946 void radv_DestroyEvent(
3947 VkDevice _device,
3948 VkEvent _event,
3949 const VkAllocationCallbacks* pAllocator)
3950 {
3951 RADV_FROM_HANDLE(radv_device, device, _device);
3952 RADV_FROM_HANDLE(radv_event, event, _event);
3953
3954 if (!event)
3955 return;
3956 device->ws->buffer_destroy(event->bo);
3957 vk_free2(&device->alloc, pAllocator, event);
3958 }
3959
3960 VkResult radv_GetEventStatus(
3961 VkDevice _device,
3962 VkEvent _event)
3963 {
3964 RADV_FROM_HANDLE(radv_event, event, _event);
3965
3966 if (*event->map == 1)
3967 return VK_EVENT_SET;
3968 return VK_EVENT_RESET;
3969 }
3970
3971 VkResult radv_SetEvent(
3972 VkDevice _device,
3973 VkEvent _event)
3974 {
3975 RADV_FROM_HANDLE(radv_event, event, _event);
3976 *event->map = 1;
3977
3978 return VK_SUCCESS;
3979 }
3980
3981 VkResult radv_ResetEvent(
3982 VkDevice _device,
3983 VkEvent _event)
3984 {
3985 RADV_FROM_HANDLE(radv_event, event, _event);
3986 *event->map = 0;
3987
3988 return VK_SUCCESS;
3989 }
3990
3991 VkResult radv_CreateBuffer(
3992 VkDevice _device,
3993 const VkBufferCreateInfo* pCreateInfo,
3994 const VkAllocationCallbacks* pAllocator,
3995 VkBuffer* pBuffer)
3996 {
3997 RADV_FROM_HANDLE(radv_device, device, _device);
3998 struct radv_buffer *buffer;
3999
4000 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4001
4002 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4003 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4004 if (buffer == NULL)
4005 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4006
4007 buffer->size = pCreateInfo->size;
4008 buffer->usage = pCreateInfo->usage;
4009 buffer->bo = NULL;
4010 buffer->offset = 0;
4011 buffer->flags = pCreateInfo->flags;
4012
4013 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4014 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4015
4016 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4017 buffer->bo = device->ws->buffer_create(device->ws,
4018 align64(buffer->size, 4096),
4019 4096, 0, RADEON_FLAG_VIRTUAL,
4020 RADV_BO_PRIORITY_VIRTUAL);
4021 if (!buffer->bo) {
4022 vk_free2(&device->alloc, pAllocator, buffer);
4023 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4024 }
4025 }
4026
4027 *pBuffer = radv_buffer_to_handle(buffer);
4028
4029 return VK_SUCCESS;
4030 }
4031
4032 void radv_DestroyBuffer(
4033 VkDevice _device,
4034 VkBuffer _buffer,
4035 const VkAllocationCallbacks* pAllocator)
4036 {
4037 RADV_FROM_HANDLE(radv_device, device, _device);
4038 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4039
4040 if (!buffer)
4041 return;
4042
4043 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4044 device->ws->buffer_destroy(buffer->bo);
4045
4046 vk_free2(&device->alloc, pAllocator, buffer);
4047 }
4048
4049 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4050 VkDevice device,
4051 const VkBufferDeviceAddressInfoEXT* pInfo)
4052 {
4053 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4054 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4055 }
4056
4057
4058 static inline unsigned
4059 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4060 {
4061 if (stencil)
4062 return image->surface.u.legacy.stencil_tiling_index[level];
4063 else
4064 return image->surface.u.legacy.tiling_index[level];
4065 }
4066
4067 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4068 {
4069 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4070 }
4071
4072 static uint32_t
4073 radv_init_dcc_control_reg(struct radv_device *device,
4074 struct radv_image_view *iview)
4075 {
4076 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4077 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4078 unsigned max_compressed_block_size;
4079 unsigned independent_64b_blocks;
4080
4081 if (!radv_image_has_dcc(iview->image))
4082 return 0;
4083
4084 if (iview->image->info.samples > 1) {
4085 if (iview->image->surface.bpe == 1)
4086 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4087 else if (iview->image->surface.bpe == 2)
4088 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4089 }
4090
4091 if (!device->physical_device->rad_info.has_dedicated_vram) {
4092 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4093 * dGPU and 64 for APU because all of our APUs to date use
4094 * DIMMs which have a request granularity size of 64B while all
4095 * other chips have a 32B request size.
4096 */
4097 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4098 }
4099
4100 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4101 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4102 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4103 /* If this DCC image is potentially going to be used in texture
4104 * fetches, we need some special settings.
4105 */
4106 independent_64b_blocks = 1;
4107 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4108 } else {
4109 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4110 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4111 * big as possible for better compression state.
4112 */
4113 independent_64b_blocks = 0;
4114 max_compressed_block_size = max_uncompressed_block_size;
4115 }
4116
4117 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4118 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4119 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4120 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4121 }
4122
4123 static void
4124 radv_initialise_color_surface(struct radv_device *device,
4125 struct radv_color_buffer_info *cb,
4126 struct radv_image_view *iview)
4127 {
4128 const struct vk_format_description *desc;
4129 unsigned ntype, format, swap, endian;
4130 unsigned blend_clamp = 0, blend_bypass = 0;
4131 uint64_t va;
4132 const struct radeon_surf *surf = &iview->image->surface;
4133
4134 desc = vk_format_description(iview->vk_format);
4135
4136 memset(cb, 0, sizeof(*cb));
4137
4138 /* Intensity is implemented as Red, so treat it that way. */
4139 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4140
4141 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4142
4143 cb->cb_color_base = va >> 8;
4144
4145 if (device->physical_device->rad_info.chip_class >= GFX9) {
4146 struct gfx9_surf_meta_flags meta;
4147 if (iview->image->dcc_offset)
4148 meta = iview->image->surface.u.gfx9.dcc;
4149 else
4150 meta = iview->image->surface.u.gfx9.cmask;
4151
4152 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4153 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4154 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4155 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4156
4157 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4158 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4159 } else {
4160 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4161 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4162
4163 cb->cb_color_base += level_info->offset >> 8;
4164 if (level_info->mode == RADEON_SURF_MODE_2D)
4165 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4166
4167 pitch_tile_max = level_info->nblk_x / 8 - 1;
4168 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4169 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4170
4171 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4172 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4173 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4174
4175 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4176
4177 if (radv_image_has_fmask(iview->image)) {
4178 if (device->physical_device->rad_info.chip_class >= CIK)
4179 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4180 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4181 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4182 } else {
4183 /* This must be set for fast clear to work without FMASK. */
4184 if (device->physical_device->rad_info.chip_class >= CIK)
4185 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4186 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4187 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4188 }
4189 }
4190
4191 /* CMASK variables */
4192 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4193 va += iview->image->cmask.offset;
4194 cb->cb_color_cmask = va >> 8;
4195
4196 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4197 va += iview->image->dcc_offset;
4198 cb->cb_dcc_base = va >> 8;
4199 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4200
4201 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4202 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4203 S_028C6C_SLICE_MAX(max_slice);
4204
4205 if (iview->image->info.samples > 1) {
4206 unsigned log_samples = util_logbase2(iview->image->info.samples);
4207
4208 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4209 S_028C74_NUM_FRAGMENTS(log_samples);
4210 }
4211
4212 if (radv_image_has_fmask(iview->image)) {
4213 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4214 cb->cb_color_fmask = va >> 8;
4215 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4216 } else {
4217 cb->cb_color_fmask = cb->cb_color_base;
4218 }
4219
4220 ntype = radv_translate_color_numformat(iview->vk_format,
4221 desc,
4222 vk_format_get_first_non_void_channel(iview->vk_format));
4223 format = radv_translate_colorformat(iview->vk_format);
4224 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4225 radv_finishme("Illegal color\n");
4226 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4227 endian = radv_colorformat_endian_swap(format);
4228
4229 /* blend clamp should be set for all NORM/SRGB types */
4230 if (ntype == V_028C70_NUMBER_UNORM ||
4231 ntype == V_028C70_NUMBER_SNORM ||
4232 ntype == V_028C70_NUMBER_SRGB)
4233 blend_clamp = 1;
4234
4235 /* set blend bypass according to docs if SINT/UINT or
4236 8/24 COLOR variants */
4237 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4238 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4239 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4240 blend_clamp = 0;
4241 blend_bypass = 1;
4242 }
4243 #if 0
4244 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4245 (format == V_028C70_COLOR_8 ||
4246 format == V_028C70_COLOR_8_8 ||
4247 format == V_028C70_COLOR_8_8_8_8))
4248 ->color_is_int8 = true;
4249 #endif
4250 cb->cb_color_info = S_028C70_FORMAT(format) |
4251 S_028C70_COMP_SWAP(swap) |
4252 S_028C70_BLEND_CLAMP(blend_clamp) |
4253 S_028C70_BLEND_BYPASS(blend_bypass) |
4254 S_028C70_SIMPLE_FLOAT(1) |
4255 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4256 ntype != V_028C70_NUMBER_SNORM &&
4257 ntype != V_028C70_NUMBER_SRGB &&
4258 format != V_028C70_COLOR_8_24 &&
4259 format != V_028C70_COLOR_24_8) |
4260 S_028C70_NUMBER_TYPE(ntype) |
4261 S_028C70_ENDIAN(endian);
4262 if (radv_image_has_fmask(iview->image)) {
4263 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4264 if (device->physical_device->rad_info.chip_class == SI) {
4265 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4266 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4267 }
4268 }
4269
4270 if (radv_image_has_cmask(iview->image) &&
4271 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4272 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4273
4274 if (radv_dcc_enabled(iview->image, iview->base_mip))
4275 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4276
4277 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4278
4279 /* This must be set for fast clear to work without FMASK. */
4280 if (!radv_image_has_fmask(iview->image) &&
4281 device->physical_device->rad_info.chip_class == SI) {
4282 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4283 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4284 }
4285
4286 if (device->physical_device->rad_info.chip_class >= GFX9) {
4287 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4288 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4289
4290 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4291 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4292 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4293 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4294 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4295 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4296 }
4297 }
4298
4299 static unsigned
4300 radv_calc_decompress_on_z_planes(struct radv_device *device,
4301 struct radv_image_view *iview)
4302 {
4303 unsigned max_zplanes = 0;
4304
4305 assert(radv_image_is_tc_compat_htile(iview->image));
4306
4307 if (device->physical_device->rad_info.chip_class >= GFX9) {
4308 /* Default value for 32-bit depth surfaces. */
4309 max_zplanes = 4;
4310
4311 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4312 iview->image->info.samples > 1)
4313 max_zplanes = 2;
4314
4315 max_zplanes = max_zplanes + 1;
4316 } else {
4317 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4318 /* Do not enable Z plane compression for 16-bit depth
4319 * surfaces because isn't supported on GFX8. Only
4320 * 32-bit depth surfaces are supported by the hardware.
4321 * This allows to maintain shader compatibility and to
4322 * reduce the number of depth decompressions.
4323 */
4324 max_zplanes = 1;
4325 } else {
4326 if (iview->image->info.samples <= 1)
4327 max_zplanes = 5;
4328 else if (iview->image->info.samples <= 4)
4329 max_zplanes = 3;
4330 else
4331 max_zplanes = 2;
4332 }
4333 }
4334
4335 return max_zplanes;
4336 }
4337
4338 static void
4339 radv_initialise_ds_surface(struct radv_device *device,
4340 struct radv_ds_buffer_info *ds,
4341 struct radv_image_view *iview)
4342 {
4343 unsigned level = iview->base_mip;
4344 unsigned format, stencil_format;
4345 uint64_t va, s_offs, z_offs;
4346 bool stencil_only = false;
4347 memset(ds, 0, sizeof(*ds));
4348 switch (iview->image->vk_format) {
4349 case VK_FORMAT_D24_UNORM_S8_UINT:
4350 case VK_FORMAT_X8_D24_UNORM_PACK32:
4351 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4352 ds->offset_scale = 2.0f;
4353 break;
4354 case VK_FORMAT_D16_UNORM:
4355 case VK_FORMAT_D16_UNORM_S8_UINT:
4356 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4357 ds->offset_scale = 4.0f;
4358 break;
4359 case VK_FORMAT_D32_SFLOAT:
4360 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4361 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4362 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4363 ds->offset_scale = 1.0f;
4364 break;
4365 case VK_FORMAT_S8_UINT:
4366 stencil_only = true;
4367 break;
4368 default:
4369 break;
4370 }
4371
4372 format = radv_translate_dbformat(iview->image->vk_format);
4373 stencil_format = iview->image->surface.has_stencil ?
4374 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4375
4376 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4377 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4378 S_028008_SLICE_MAX(max_slice);
4379
4380 ds->db_htile_data_base = 0;
4381 ds->db_htile_surface = 0;
4382
4383 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4384 s_offs = z_offs = va;
4385
4386 if (device->physical_device->rad_info.chip_class >= GFX9) {
4387 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4388 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4389
4390 ds->db_z_info = S_028038_FORMAT(format) |
4391 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4392 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4393 S_028038_MAXMIP(iview->image->info.levels - 1) |
4394 S_028038_ZRANGE_PRECISION(1);
4395 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4396 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4397
4398 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4399 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4400 ds->db_depth_view |= S_028008_MIPID(level);
4401
4402 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4403 S_02801C_Y_MAX(iview->image->info.height - 1);
4404
4405 if (radv_htile_enabled(iview->image, level)) {
4406 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4407
4408 if (radv_image_is_tc_compat_htile(iview->image)) {
4409 unsigned max_zplanes =
4410 radv_calc_decompress_on_z_planes(device, iview);
4411
4412 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4413 S_028038_ITERATE_FLUSH(1);
4414 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4415 }
4416
4417 if (!iview->image->surface.has_stencil)
4418 /* Use all of the htile_buffer for depth if there's no stencil. */
4419 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4420 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4421 iview->image->htile_offset;
4422 ds->db_htile_data_base = va >> 8;
4423 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4424 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4425 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4426 }
4427 } else {
4428 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4429
4430 if (stencil_only)
4431 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4432
4433 z_offs += iview->image->surface.u.legacy.level[level].offset;
4434 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4435
4436 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4437 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4438 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4439
4440 if (iview->image->info.samples > 1)
4441 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4442
4443 if (device->physical_device->rad_info.chip_class >= CIK) {
4444 struct radeon_info *info = &device->physical_device->rad_info;
4445 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4446 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4447 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4448 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4449 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4450 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4451
4452 if (stencil_only)
4453 tile_mode = stencil_tile_mode;
4454
4455 ds->db_depth_info |=
4456 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4457 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4458 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4459 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4460 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4461 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4462 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4463 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4464 } else {
4465 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4466 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4467 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4468 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4469 if (stencil_only)
4470 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4471 }
4472
4473 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4474 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4475 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4476
4477 if (radv_htile_enabled(iview->image, level)) {
4478 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4479
4480 if (!iview->image->surface.has_stencil &&
4481 !radv_image_is_tc_compat_htile(iview->image))
4482 /* Use all of the htile_buffer for depth if there's no stencil. */
4483 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4484
4485 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4486 iview->image->htile_offset;
4487 ds->db_htile_data_base = va >> 8;
4488 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4489
4490 if (radv_image_is_tc_compat_htile(iview->image)) {
4491 unsigned max_zplanes =
4492 radv_calc_decompress_on_z_planes(device, iview);
4493
4494 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4495 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4496 }
4497 }
4498 }
4499
4500 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4501 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4502 }
4503
4504 VkResult radv_CreateFramebuffer(
4505 VkDevice _device,
4506 const VkFramebufferCreateInfo* pCreateInfo,
4507 const VkAllocationCallbacks* pAllocator,
4508 VkFramebuffer* pFramebuffer)
4509 {
4510 RADV_FROM_HANDLE(radv_device, device, _device);
4511 struct radv_framebuffer *framebuffer;
4512
4513 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4514
4515 size_t size = sizeof(*framebuffer) +
4516 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4517 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4518 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4519 if (framebuffer == NULL)
4520 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4521
4522 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4523 framebuffer->width = pCreateInfo->width;
4524 framebuffer->height = pCreateInfo->height;
4525 framebuffer->layers = pCreateInfo->layers;
4526 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4527 VkImageView _iview = pCreateInfo->pAttachments[i];
4528 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4529 framebuffer->attachments[i].attachment = iview;
4530 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4531 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4532 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4533 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4534 }
4535 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4536 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4537 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4538 }
4539
4540 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4541 return VK_SUCCESS;
4542 }
4543
4544 void radv_DestroyFramebuffer(
4545 VkDevice _device,
4546 VkFramebuffer _fb,
4547 const VkAllocationCallbacks* pAllocator)
4548 {
4549 RADV_FROM_HANDLE(radv_device, device, _device);
4550 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4551
4552 if (!fb)
4553 return;
4554 vk_free2(&device->alloc, pAllocator, fb);
4555 }
4556
4557 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4558 {
4559 switch (address_mode) {
4560 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4561 return V_008F30_SQ_TEX_WRAP;
4562 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4563 return V_008F30_SQ_TEX_MIRROR;
4564 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4565 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4566 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4567 return V_008F30_SQ_TEX_CLAMP_BORDER;
4568 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4569 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4570 default:
4571 unreachable("illegal tex wrap mode");
4572 break;
4573 }
4574 }
4575
4576 static unsigned
4577 radv_tex_compare(VkCompareOp op)
4578 {
4579 switch (op) {
4580 case VK_COMPARE_OP_NEVER:
4581 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4582 case VK_COMPARE_OP_LESS:
4583 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4584 case VK_COMPARE_OP_EQUAL:
4585 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4586 case VK_COMPARE_OP_LESS_OR_EQUAL:
4587 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4588 case VK_COMPARE_OP_GREATER:
4589 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4590 case VK_COMPARE_OP_NOT_EQUAL:
4591 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4592 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4593 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4594 case VK_COMPARE_OP_ALWAYS:
4595 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4596 default:
4597 unreachable("illegal compare mode");
4598 break;
4599 }
4600 }
4601
4602 static unsigned
4603 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4604 {
4605 switch (filter) {
4606 case VK_FILTER_NEAREST:
4607 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4608 V_008F38_SQ_TEX_XY_FILTER_POINT);
4609 case VK_FILTER_LINEAR:
4610 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4611 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4612 case VK_FILTER_CUBIC_IMG:
4613 default:
4614 fprintf(stderr, "illegal texture filter");
4615 return 0;
4616 }
4617 }
4618
4619 static unsigned
4620 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4621 {
4622 switch (mode) {
4623 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4624 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4625 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4626 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4627 default:
4628 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4629 }
4630 }
4631
4632 static unsigned
4633 radv_tex_bordercolor(VkBorderColor bcolor)
4634 {
4635 switch (bcolor) {
4636 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4637 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4638 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4639 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4640 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4641 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4642 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4643 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4644 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4645 default:
4646 break;
4647 }
4648 return 0;
4649 }
4650
4651 static unsigned
4652 radv_tex_aniso_filter(unsigned filter)
4653 {
4654 if (filter < 2)
4655 return 0;
4656 if (filter < 4)
4657 return 1;
4658 if (filter < 8)
4659 return 2;
4660 if (filter < 16)
4661 return 3;
4662 return 4;
4663 }
4664
4665 static unsigned
4666 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4667 {
4668 switch (mode) {
4669 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4670 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4671 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4672 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4673 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4674 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4675 default:
4676 break;
4677 }
4678 return 0;
4679 }
4680
4681 static uint32_t
4682 radv_get_max_anisotropy(struct radv_device *device,
4683 const VkSamplerCreateInfo *pCreateInfo)
4684 {
4685 if (device->force_aniso >= 0)
4686 return device->force_aniso;
4687
4688 if (pCreateInfo->anisotropyEnable &&
4689 pCreateInfo->maxAnisotropy > 1.0f)
4690 return (uint32_t)pCreateInfo->maxAnisotropy;
4691
4692 return 0;
4693 }
4694
4695 static void
4696 radv_init_sampler(struct radv_device *device,
4697 struct radv_sampler *sampler,
4698 const VkSamplerCreateInfo *pCreateInfo)
4699 {
4700 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4701 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4702 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4703 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4704
4705 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4706 vk_find_struct_const(pCreateInfo->pNext,
4707 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4708 if (sampler_reduction)
4709 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4710
4711 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4712 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4713 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4714 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4715 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4716 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4717 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4718 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4719 S_008F30_DISABLE_CUBE_WRAP(0) |
4720 S_008F30_COMPAT_MODE(is_vi) |
4721 S_008F30_FILTER_MODE(filter_mode));
4722 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4723 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4724 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4725 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4726 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4727 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4728 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4729 S_008F38_MIP_POINT_PRECLAMP(0) |
4730 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4731 S_008F38_FILTER_PREC_FIX(1) |
4732 S_008F38_ANISO_OVERRIDE(is_vi));
4733 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4734 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4735 }
4736
4737 VkResult radv_CreateSampler(
4738 VkDevice _device,
4739 const VkSamplerCreateInfo* pCreateInfo,
4740 const VkAllocationCallbacks* pAllocator,
4741 VkSampler* pSampler)
4742 {
4743 RADV_FROM_HANDLE(radv_device, device, _device);
4744 struct radv_sampler *sampler;
4745
4746 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4747
4748 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4749 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4750 if (!sampler)
4751 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4752
4753 radv_init_sampler(device, sampler, pCreateInfo);
4754 *pSampler = radv_sampler_to_handle(sampler);
4755
4756 return VK_SUCCESS;
4757 }
4758
4759 void radv_DestroySampler(
4760 VkDevice _device,
4761 VkSampler _sampler,
4762 const VkAllocationCallbacks* pAllocator)
4763 {
4764 RADV_FROM_HANDLE(radv_device, device, _device);
4765 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4766
4767 if (!sampler)
4768 return;
4769 vk_free2(&device->alloc, pAllocator, sampler);
4770 }
4771
4772 /* vk_icd.h does not declare this function, so we declare it here to
4773 * suppress Wmissing-prototypes.
4774 */
4775 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4776 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4777
4778 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4779 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4780 {
4781 /* For the full details on loader interface versioning, see
4782 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4783 * What follows is a condensed summary, to help you navigate the large and
4784 * confusing official doc.
4785 *
4786 * - Loader interface v0 is incompatible with later versions. We don't
4787 * support it.
4788 *
4789 * - In loader interface v1:
4790 * - The first ICD entrypoint called by the loader is
4791 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4792 * entrypoint.
4793 * - The ICD must statically expose no other Vulkan symbol unless it is
4794 * linked with -Bsymbolic.
4795 * - Each dispatchable Vulkan handle created by the ICD must be
4796 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4797 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4798 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4799 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4800 * such loader-managed surfaces.
4801 *
4802 * - Loader interface v2 differs from v1 in:
4803 * - The first ICD entrypoint called by the loader is
4804 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4805 * statically expose this entrypoint.
4806 *
4807 * - Loader interface v3 differs from v2 in:
4808 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4809 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4810 * because the loader no longer does so.
4811 */
4812 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4813 return VK_SUCCESS;
4814 }
4815
4816 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4817 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4818 int *pFD)
4819 {
4820 RADV_FROM_HANDLE(radv_device, device, _device);
4821 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4822
4823 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4824
4825 /* At the moment, we support only the below handle types. */
4826 assert(pGetFdInfo->handleType ==
4827 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4828 pGetFdInfo->handleType ==
4829 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4830
4831 bool ret = radv_get_memory_fd(device, memory, pFD);
4832 if (ret == false)
4833 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4834 return VK_SUCCESS;
4835 }
4836
4837 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4838 VkExternalMemoryHandleTypeFlagBits handleType,
4839 int fd,
4840 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4841 {
4842 RADV_FROM_HANDLE(radv_device, device, _device);
4843
4844 switch (handleType) {
4845 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4846 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4847 return VK_SUCCESS;
4848
4849 default:
4850 /* The valid usage section for this function says:
4851 *
4852 * "handleType must not be one of the handle types defined as
4853 * opaque."
4854 *
4855 * So opaque handle types fall into the default "unsupported" case.
4856 */
4857 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4858 }
4859 }
4860
4861 static VkResult radv_import_opaque_fd(struct radv_device *device,
4862 int fd,
4863 uint32_t *syncobj)
4864 {
4865 uint32_t syncobj_handle = 0;
4866 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4867 if (ret != 0)
4868 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4869
4870 if (*syncobj)
4871 device->ws->destroy_syncobj(device->ws, *syncobj);
4872
4873 *syncobj = syncobj_handle;
4874 close(fd);
4875
4876 return VK_SUCCESS;
4877 }
4878
4879 static VkResult radv_import_sync_fd(struct radv_device *device,
4880 int fd,
4881 uint32_t *syncobj)
4882 {
4883 /* If we create a syncobj we do it locally so that if we have an error, we don't
4884 * leave a syncobj in an undetermined state in the fence. */
4885 uint32_t syncobj_handle = *syncobj;
4886 if (!syncobj_handle) {
4887 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4888 if (ret) {
4889 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4890 }
4891 }
4892
4893 if (fd == -1) {
4894 device->ws->signal_syncobj(device->ws, syncobj_handle);
4895 } else {
4896 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4897 if (ret != 0)
4898 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4899 }
4900
4901 *syncobj = syncobj_handle;
4902 if (fd != -1)
4903 close(fd);
4904
4905 return VK_SUCCESS;
4906 }
4907
4908 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4909 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4910 {
4911 RADV_FROM_HANDLE(radv_device, device, _device);
4912 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4913 uint32_t *syncobj_dst = NULL;
4914
4915 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4916 syncobj_dst = &sem->temp_syncobj;
4917 } else {
4918 syncobj_dst = &sem->syncobj;
4919 }
4920
4921 switch(pImportSemaphoreFdInfo->handleType) {
4922 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4923 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4924 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4925 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4926 default:
4927 unreachable("Unhandled semaphore handle type");
4928 }
4929 }
4930
4931 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4932 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4933 int *pFd)
4934 {
4935 RADV_FROM_HANDLE(radv_device, device, _device);
4936 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4937 int ret;
4938 uint32_t syncobj_handle;
4939
4940 if (sem->temp_syncobj)
4941 syncobj_handle = sem->temp_syncobj;
4942 else
4943 syncobj_handle = sem->syncobj;
4944
4945 switch(pGetFdInfo->handleType) {
4946 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4947 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4948 break;
4949 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4950 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4951 if (!ret) {
4952 if (sem->temp_syncobj) {
4953 close (sem->temp_syncobj);
4954 sem->temp_syncobj = 0;
4955 } else {
4956 device->ws->reset_syncobj(device->ws, syncobj_handle);
4957 }
4958 }
4959 break;
4960 default:
4961 unreachable("Unhandled semaphore handle type");
4962 }
4963
4964 if (ret)
4965 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4966 return VK_SUCCESS;
4967 }
4968
4969 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4970 VkPhysicalDevice physicalDevice,
4971 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4972 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4973 {
4974 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4975
4976 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4977 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4978 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4979 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4980 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4981 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4982 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4983 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4984 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4985 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4986 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4987 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4988 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4989 } else {
4990 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4991 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4992 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4993 }
4994 }
4995
4996 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4997 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4998 {
4999 RADV_FROM_HANDLE(radv_device, device, _device);
5000 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5001 uint32_t *syncobj_dst = NULL;
5002
5003
5004 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5005 syncobj_dst = &fence->temp_syncobj;
5006 } else {
5007 syncobj_dst = &fence->syncobj;
5008 }
5009
5010 switch(pImportFenceFdInfo->handleType) {
5011 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5012 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5013 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5014 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5015 default:
5016 unreachable("Unhandled fence handle type");
5017 }
5018 }
5019
5020 VkResult radv_GetFenceFdKHR(VkDevice _device,
5021 const VkFenceGetFdInfoKHR *pGetFdInfo,
5022 int *pFd)
5023 {
5024 RADV_FROM_HANDLE(radv_device, device, _device);
5025 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5026 int ret;
5027 uint32_t syncobj_handle;
5028
5029 if (fence->temp_syncobj)
5030 syncobj_handle = fence->temp_syncobj;
5031 else
5032 syncobj_handle = fence->syncobj;
5033
5034 switch(pGetFdInfo->handleType) {
5035 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5036 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5037 break;
5038 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5039 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5040 if (!ret) {
5041 if (fence->temp_syncobj) {
5042 close (fence->temp_syncobj);
5043 fence->temp_syncobj = 0;
5044 } else {
5045 device->ws->reset_syncobj(device->ws, syncobj_handle);
5046 }
5047 }
5048 break;
5049 default:
5050 unreachable("Unhandled fence handle type");
5051 }
5052
5053 if (ret)
5054 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5055 return VK_SUCCESS;
5056 }
5057
5058 void radv_GetPhysicalDeviceExternalFenceProperties(
5059 VkPhysicalDevice physicalDevice,
5060 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5061 VkExternalFenceProperties *pExternalFenceProperties)
5062 {
5063 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5064
5065 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5066 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5067 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5068 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5069 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5070 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5071 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5072 } else {
5073 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5074 pExternalFenceProperties->compatibleHandleTypes = 0;
5075 pExternalFenceProperties->externalFenceFeatures = 0;
5076 }
5077 }
5078
5079 VkResult
5080 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5081 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5082 const VkAllocationCallbacks* pAllocator,
5083 VkDebugReportCallbackEXT* pCallback)
5084 {
5085 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5086 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5087 pCreateInfo, pAllocator, &instance->alloc,
5088 pCallback);
5089 }
5090
5091 void
5092 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5093 VkDebugReportCallbackEXT _callback,
5094 const VkAllocationCallbacks* pAllocator)
5095 {
5096 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5097 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5098 _callback, pAllocator, &instance->alloc);
5099 }
5100
5101 void
5102 radv_DebugReportMessageEXT(VkInstance _instance,
5103 VkDebugReportFlagsEXT flags,
5104 VkDebugReportObjectTypeEXT objectType,
5105 uint64_t object,
5106 size_t location,
5107 int32_t messageCode,
5108 const char* pLayerPrefix,
5109 const char* pMessage)
5110 {
5111 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5112 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5113 object, location, messageCode, pLayerPrefix, pMessage);
5114 }
5115
5116 void
5117 radv_GetDeviceGroupPeerMemoryFeatures(
5118 VkDevice device,
5119 uint32_t heapIndex,
5120 uint32_t localDeviceIndex,
5121 uint32_t remoteDeviceIndex,
5122 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5123 {
5124 assert(localDeviceIndex == remoteDeviceIndex);
5125
5126 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5127 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5128 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5129 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5130 }
5131
5132 static const VkTimeDomainEXT radv_time_domains[] = {
5133 VK_TIME_DOMAIN_DEVICE_EXT,
5134 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5135 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5136 };
5137
5138 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5139 VkPhysicalDevice physicalDevice,
5140 uint32_t *pTimeDomainCount,
5141 VkTimeDomainEXT *pTimeDomains)
5142 {
5143 int d;
5144 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5145
5146 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5147 vk_outarray_append(&out, i) {
5148 *i = radv_time_domains[d];
5149 }
5150 }
5151
5152 return vk_outarray_status(&out);
5153 }
5154
5155 static uint64_t
5156 radv_clock_gettime(clockid_t clock_id)
5157 {
5158 struct timespec current;
5159 int ret;
5160
5161 ret = clock_gettime(clock_id, &current);
5162 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5163 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5164 if (ret < 0)
5165 return 0;
5166
5167 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5168 }
5169
5170 VkResult radv_GetCalibratedTimestampsEXT(
5171 VkDevice _device,
5172 uint32_t timestampCount,
5173 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5174 uint64_t *pTimestamps,
5175 uint64_t *pMaxDeviation)
5176 {
5177 RADV_FROM_HANDLE(radv_device, device, _device);
5178 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5179 int d;
5180 uint64_t begin, end;
5181 uint64_t max_clock_period = 0;
5182
5183 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5184
5185 for (d = 0; d < timestampCount; d++) {
5186 switch (pTimestampInfos[d].timeDomain) {
5187 case VK_TIME_DOMAIN_DEVICE_EXT:
5188 pTimestamps[d] = device->ws->query_value(device->ws,
5189 RADEON_TIMESTAMP);
5190 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5191 max_clock_period = MAX2(max_clock_period, device_period);
5192 break;
5193 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5194 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5195 max_clock_period = MAX2(max_clock_period, 1);
5196 break;
5197
5198 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5199 pTimestamps[d] = begin;
5200 break;
5201 default:
5202 pTimestamps[d] = 0;
5203 break;
5204 }
5205 }
5206
5207 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5208
5209 /*
5210 * The maximum deviation is the sum of the interval over which we
5211 * perform the sampling and the maximum period of any sampled
5212 * clock. That's because the maximum skew between any two sampled
5213 * clock edges is when the sampled clock with the largest period is
5214 * sampled at the end of that period but right at the beginning of the
5215 * sampling interval and some other clock is sampled right at the
5216 * begining of its sampling period and right at the end of the
5217 * sampling interval. Let's assume the GPU has the longest clock
5218 * period and that the application is sampling GPU and monotonic:
5219 *
5220 * s e
5221 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5222 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5223 *
5224 * g
5225 * 0 1 2 3
5226 * GPU -----_____-----_____-----_____-----_____
5227 *
5228 * m
5229 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5230 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5231 *
5232 * Interval <----------------->
5233 * Deviation <-------------------------->
5234 *
5235 * s = read(raw) 2
5236 * g = read(GPU) 1
5237 * m = read(monotonic) 2
5238 * e = read(raw) b
5239 *
5240 * We round the sample interval up by one tick to cover sampling error
5241 * in the interval clock
5242 */
5243
5244 uint64_t sample_interval = end - begin + 1;
5245
5246 *pMaxDeviation = sample_interval + max_clock_period;
5247
5248 return VK_SUCCESS;
5249 }