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98cfd9b58a91237dcf374c10a32ed2f317e33538
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static void
187 radv_handle_env_var_force_family(struct radv_physical_device *device)
188 {
189 const char *family = getenv("RADV_FORCE_FAMILY");
190 unsigned i;
191
192 if (!family)
193 return;
194
195 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
196 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
197 /* Override family and chip_class. */
198 device->rad_info.family = i;
199
200 if (i >= CHIP_VEGA10)
201 device->rad_info.chip_class = GFX9;
202 else if (i >= CHIP_TONGA)
203 device->rad_info.chip_class = VI;
204 else if (i >= CHIP_BONAIRE)
205 device->rad_info.chip_class = CIK;
206 else
207 device->rad_info.chip_class = SI;
208
209 return;
210 }
211 }
212
213 fprintf(stderr, "radv: Unknown family: %s\n", family);
214 exit(1);
215 }
216
217 static VkResult
218 radv_physical_device_init(struct radv_physical_device *device,
219 struct radv_instance *instance,
220 drmDevicePtr drm_device)
221 {
222 const char *path = drm_device->nodes[DRM_NODE_RENDER];
223 VkResult result;
224 drmVersionPtr version;
225 int fd;
226
227 fd = open(path, O_RDWR | O_CLOEXEC);
228 if (fd < 0)
229 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
230
231 version = drmGetVersion(fd);
232 if (!version) {
233 close(fd);
234 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
235 "failed to get version %s: %m", path);
236 }
237
238 if (strcmp(version->name, "amdgpu")) {
239 drmFreeVersion(version);
240 close(fd);
241 return VK_ERROR_INCOMPATIBLE_DRIVER;
242 }
243 drmFreeVersion(version);
244
245 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
246 device->instance = instance;
247 assert(strlen(path) < ARRAY_SIZE(device->path));
248 strncpy(device->path, path, ARRAY_SIZE(device->path));
249
250 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
251 instance->perftest_flags);
252 if (!device->ws) {
253 result = VK_ERROR_INCOMPATIBLE_DRIVER;
254 goto fail;
255 }
256
257 device->local_fd = fd;
258 device->ws->query_info(device->ws, &device->rad_info);
259
260 radv_handle_env_var_force_family(device);
261
262 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
263
264 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
265 device->ws->destroy(device->ws);
266 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
267 "cannot generate UUID");
268 goto fail;
269 }
270
271 /* These flags affect shader compilation. */
272 uint64_t shader_env_flags =
273 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
274 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
275
276 /* The gpu id is already embeded in the uuid so we just pass "radv"
277 * when creating the cache.
278 */
279 char buf[VK_UUID_SIZE * 2 + 1];
280 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
281 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
282
283 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
284
285 radv_get_driver_uuid(&device->device_uuid);
286 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
287
288 if (device->rad_info.family == CHIP_STONEY ||
289 device->rad_info.chip_class >= GFX9) {
290 device->has_rbplus = true;
291 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
292 }
293
294 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
295 * on SI.
296 */
297 device->has_clear_state = device->rad_info.chip_class >= CIK;
298
299 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
300
301 /* Vega10/Raven need a special workaround for a hardware bug. */
302 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
303 device->rad_info.family == CHIP_RAVEN;
304
305 radv_physical_device_init_mem_types(device);
306
307 result = radv_init_wsi(device);
308 if (result != VK_SUCCESS) {
309 device->ws->destroy(device->ws);
310 goto fail;
311 }
312
313 return VK_SUCCESS;
314
315 fail:
316 close(fd);
317 return result;
318 }
319
320 static void
321 radv_physical_device_finish(struct radv_physical_device *device)
322 {
323 radv_finish_wsi(device);
324 device->ws->destroy(device->ws);
325 disk_cache_destroy(device->disk_cache);
326 close(device->local_fd);
327 }
328
329 static void *
330 default_alloc_func(void *pUserData, size_t size, size_t align,
331 VkSystemAllocationScope allocationScope)
332 {
333 return malloc(size);
334 }
335
336 static void *
337 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
338 size_t align, VkSystemAllocationScope allocationScope)
339 {
340 return realloc(pOriginal, size);
341 }
342
343 static void
344 default_free_func(void *pUserData, void *pMemory)
345 {
346 free(pMemory);
347 }
348
349 static const VkAllocationCallbacks default_alloc = {
350 .pUserData = NULL,
351 .pfnAllocation = default_alloc_func,
352 .pfnReallocation = default_realloc_func,
353 .pfnFree = default_free_func,
354 };
355
356 static const struct debug_control radv_debug_options[] = {
357 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
358 {"nodcc", RADV_DEBUG_NO_DCC},
359 {"shaders", RADV_DEBUG_DUMP_SHADERS},
360 {"nocache", RADV_DEBUG_NO_CACHE},
361 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
362 {"nohiz", RADV_DEBUG_NO_HIZ},
363 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
364 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
365 {"allbos", RADV_DEBUG_ALL_BOS},
366 {"noibs", RADV_DEBUG_NO_IBS},
367 {"spirv", RADV_DEBUG_DUMP_SPIRV},
368 {"vmfaults", RADV_DEBUG_VM_FAULTS},
369 {"zerovram", RADV_DEBUG_ZERO_VRAM},
370 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
371 {"nosisched", RADV_DEBUG_NO_SISCHED},
372 {"preoptir", RADV_DEBUG_PREOPTIR},
373 {NULL, 0}
374 };
375
376 const char *
377 radv_get_debug_option_name(int id)
378 {
379 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
380 return radv_debug_options[id].string;
381 }
382
383 static const struct debug_control radv_perftest_options[] = {
384 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
385 {"sisched", RADV_PERFTEST_SISCHED},
386 {"localbos", RADV_PERFTEST_LOCAL_BOS},
387 {"binning", RADV_PERFTEST_BINNING},
388 {NULL, 0}
389 };
390
391 const char *
392 radv_get_perftest_option_name(int id)
393 {
394 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
395 return radv_perftest_options[id].string;
396 }
397
398 static void
399 radv_handle_per_app_options(struct radv_instance *instance,
400 const VkApplicationInfo *info)
401 {
402 const char *name = info ? info->pApplicationName : NULL;
403
404 if (!name)
405 return;
406
407 if (!strcmp(name, "Talos - Linux - 32bit") ||
408 !strcmp(name, "Talos - Linux - 64bit")) {
409 /* Force enable LLVM sisched for Talos because it looks safe
410 * and it gives few more FPS.
411 */
412 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
413 }
414 }
415
416 VkResult radv_CreateInstance(
417 const VkInstanceCreateInfo* pCreateInfo,
418 const VkAllocationCallbacks* pAllocator,
419 VkInstance* pInstance)
420 {
421 struct radv_instance *instance;
422 VkResult result;
423
424 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
425
426 uint32_t client_version;
427 if (pCreateInfo->pApplicationInfo &&
428 pCreateInfo->pApplicationInfo->apiVersion != 0) {
429 client_version = pCreateInfo->pApplicationInfo->apiVersion;
430 } else {
431 client_version = VK_MAKE_VERSION(1, 0, 0);
432 }
433
434 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
435 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
436 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
437 "Client requested version %d.%d.%d",
438 VK_VERSION_MAJOR(client_version),
439 VK_VERSION_MINOR(client_version),
440 VK_VERSION_PATCH(client_version));
441 }
442
443 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
444 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
445 if (!radv_instance_extension_supported(ext_name))
446 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
447 }
448
449 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
450 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
451 if (!instance)
452 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
453
454 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
455
456 if (pAllocator)
457 instance->alloc = *pAllocator;
458 else
459 instance->alloc = default_alloc;
460
461 instance->apiVersion = client_version;
462 instance->physicalDeviceCount = -1;
463
464 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
465 if (result != VK_SUCCESS) {
466 vk_free2(&default_alloc, pAllocator, instance);
467 return vk_error(result);
468 }
469
470 _mesa_locale_init();
471
472 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
473
474 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
475 radv_debug_options);
476
477 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
478 radv_perftest_options);
479
480 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
481
482 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
483 /* Disable sisched when the user requests it, this is mostly
484 * useful when the driver force-enable sisched for the given
485 * application.
486 */
487 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
488 }
489
490 *pInstance = radv_instance_to_handle(instance);
491
492 return VK_SUCCESS;
493 }
494
495 void radv_DestroyInstance(
496 VkInstance _instance,
497 const VkAllocationCallbacks* pAllocator)
498 {
499 RADV_FROM_HANDLE(radv_instance, instance, _instance);
500
501 if (!instance)
502 return;
503
504 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
505 radv_physical_device_finish(instance->physicalDevices + i);
506 }
507
508 VG(VALGRIND_DESTROY_MEMPOOL(instance));
509
510 _mesa_locale_fini();
511
512 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
513
514 vk_free(&instance->alloc, instance);
515 }
516
517 static VkResult
518 radv_enumerate_devices(struct radv_instance *instance)
519 {
520 /* TODO: Check for more devices ? */
521 drmDevicePtr devices[8];
522 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
523 int max_devices;
524
525 instance->physicalDeviceCount = 0;
526
527 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
528 if (max_devices < 1)
529 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
530
531 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
532 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
533 devices[i]->bustype == DRM_BUS_PCI &&
534 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
535
536 result = radv_physical_device_init(instance->physicalDevices +
537 instance->physicalDeviceCount,
538 instance,
539 devices[i]);
540 if (result == VK_SUCCESS)
541 ++instance->physicalDeviceCount;
542 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
543 break;
544 }
545 }
546 drmFreeDevices(devices, max_devices);
547
548 return result;
549 }
550
551 VkResult radv_EnumeratePhysicalDevices(
552 VkInstance _instance,
553 uint32_t* pPhysicalDeviceCount,
554 VkPhysicalDevice* pPhysicalDevices)
555 {
556 RADV_FROM_HANDLE(radv_instance, instance, _instance);
557 VkResult result;
558
559 if (instance->physicalDeviceCount < 0) {
560 result = radv_enumerate_devices(instance);
561 if (result != VK_SUCCESS &&
562 result != VK_ERROR_INCOMPATIBLE_DRIVER)
563 return result;
564 }
565
566 if (!pPhysicalDevices) {
567 *pPhysicalDeviceCount = instance->physicalDeviceCount;
568 } else {
569 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
570 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
571 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
572 }
573
574 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
575 : VK_SUCCESS;
576 }
577
578 void radv_GetPhysicalDeviceFeatures(
579 VkPhysicalDevice physicalDevice,
580 VkPhysicalDeviceFeatures* pFeatures)
581 {
582 memset(pFeatures, 0, sizeof(*pFeatures));
583
584 *pFeatures = (VkPhysicalDeviceFeatures) {
585 .robustBufferAccess = true,
586 .fullDrawIndexUint32 = true,
587 .imageCubeArray = true,
588 .independentBlend = true,
589 .geometryShader = true,
590 .tessellationShader = true,
591 .sampleRateShading = true,
592 .dualSrcBlend = true,
593 .logicOp = true,
594 .multiDrawIndirect = true,
595 .drawIndirectFirstInstance = true,
596 .depthClamp = true,
597 .depthBiasClamp = true,
598 .fillModeNonSolid = true,
599 .depthBounds = true,
600 .wideLines = true,
601 .largePoints = true,
602 .alphaToOne = true,
603 .multiViewport = true,
604 .samplerAnisotropy = true,
605 .textureCompressionETC2 = false,
606 .textureCompressionASTC_LDR = false,
607 .textureCompressionBC = true,
608 .occlusionQueryPrecise = true,
609 .pipelineStatisticsQuery = true,
610 .vertexPipelineStoresAndAtomics = true,
611 .fragmentStoresAndAtomics = true,
612 .shaderTessellationAndGeometryPointSize = true,
613 .shaderImageGatherExtended = true,
614 .shaderStorageImageExtendedFormats = true,
615 .shaderStorageImageMultisample = false,
616 .shaderUniformBufferArrayDynamicIndexing = true,
617 .shaderSampledImageArrayDynamicIndexing = true,
618 .shaderStorageBufferArrayDynamicIndexing = true,
619 .shaderStorageImageArrayDynamicIndexing = true,
620 .shaderStorageImageReadWithoutFormat = true,
621 .shaderStorageImageWriteWithoutFormat = true,
622 .shaderClipDistance = true,
623 .shaderCullDistance = true,
624 .shaderFloat64 = true,
625 .shaderInt64 = true,
626 .shaderInt16 = false,
627 .sparseBinding = true,
628 .variableMultisampleRate = true,
629 .inheritedQueries = true,
630 };
631 }
632
633 void radv_GetPhysicalDeviceFeatures2KHR(
634 VkPhysicalDevice physicalDevice,
635 VkPhysicalDeviceFeatures2KHR *pFeatures)
636 {
637 vk_foreach_struct(ext, pFeatures->pNext) {
638 switch (ext->sType) {
639 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
640 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
641 features->variablePointersStorageBuffer = true;
642 features->variablePointers = false;
643 break;
644 }
645 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
646 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
647 features->multiview = true;
648 features->multiviewGeometryShader = true;
649 features->multiviewTessellationShader = true;
650 break;
651 }
652 default:
653 break;
654 }
655 }
656 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
657 }
658
659 void radv_GetPhysicalDeviceProperties(
660 VkPhysicalDevice physicalDevice,
661 VkPhysicalDeviceProperties* pProperties)
662 {
663 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
664 VkSampleCountFlags sample_counts = 0xf;
665
666 /* make sure that the entire descriptor set is addressable with a signed
667 * 32-bit int. So the sum of all limits scaled by descriptor size has to
668 * be at most 2 GiB. the combined image & samples object count as one of
669 * both. This limit is for the pipeline layout, not for the set layout, but
670 * there is no set limit, so we just set a pipeline limit. I don't think
671 * any app is going to hit this soon. */
672 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
673 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
674 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
675 32 /* sampler, largest when combined with image */ +
676 64 /* sampled image */ +
677 64 /* storage image */);
678
679 VkPhysicalDeviceLimits limits = {
680 .maxImageDimension1D = (1 << 14),
681 .maxImageDimension2D = (1 << 14),
682 .maxImageDimension3D = (1 << 11),
683 .maxImageDimensionCube = (1 << 14),
684 .maxImageArrayLayers = (1 << 11),
685 .maxTexelBufferElements = 128 * 1024 * 1024,
686 .maxUniformBufferRange = UINT32_MAX,
687 .maxStorageBufferRange = UINT32_MAX,
688 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
689 .maxMemoryAllocationCount = UINT32_MAX,
690 .maxSamplerAllocationCount = 64 * 1024,
691 .bufferImageGranularity = 64, /* A cache line */
692 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
693 .maxBoundDescriptorSets = MAX_SETS,
694 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
695 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
696 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
697 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
698 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
699 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
700 .maxPerStageResources = max_descriptor_set_size,
701 .maxDescriptorSetSamplers = max_descriptor_set_size,
702 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
703 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
704 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
705 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
706 .maxDescriptorSetSampledImages = max_descriptor_set_size,
707 .maxDescriptorSetStorageImages = max_descriptor_set_size,
708 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
709 .maxVertexInputAttributes = 32,
710 .maxVertexInputBindings = 32,
711 .maxVertexInputAttributeOffset = 2047,
712 .maxVertexInputBindingStride = 2048,
713 .maxVertexOutputComponents = 128,
714 .maxTessellationGenerationLevel = 64,
715 .maxTessellationPatchSize = 32,
716 .maxTessellationControlPerVertexInputComponents = 128,
717 .maxTessellationControlPerVertexOutputComponents = 128,
718 .maxTessellationControlPerPatchOutputComponents = 120,
719 .maxTessellationControlTotalOutputComponents = 4096,
720 .maxTessellationEvaluationInputComponents = 128,
721 .maxTessellationEvaluationOutputComponents = 128,
722 .maxGeometryShaderInvocations = 127,
723 .maxGeometryInputComponents = 64,
724 .maxGeometryOutputComponents = 128,
725 .maxGeometryOutputVertices = 256,
726 .maxGeometryTotalOutputComponents = 1024,
727 .maxFragmentInputComponents = 128,
728 .maxFragmentOutputAttachments = 8,
729 .maxFragmentDualSrcAttachments = 1,
730 .maxFragmentCombinedOutputResources = 8,
731 .maxComputeSharedMemorySize = 32768,
732 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
733 .maxComputeWorkGroupInvocations = 2048,
734 .maxComputeWorkGroupSize = {
735 2048,
736 2048,
737 2048
738 },
739 .subPixelPrecisionBits = 4 /* FIXME */,
740 .subTexelPrecisionBits = 4 /* FIXME */,
741 .mipmapPrecisionBits = 4 /* FIXME */,
742 .maxDrawIndexedIndexValue = UINT32_MAX,
743 .maxDrawIndirectCount = UINT32_MAX,
744 .maxSamplerLodBias = 16,
745 .maxSamplerAnisotropy = 16,
746 .maxViewports = MAX_VIEWPORTS,
747 .maxViewportDimensions = { (1 << 14), (1 << 14) },
748 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
749 .viewportSubPixelBits = 13, /* We take a float? */
750 .minMemoryMapAlignment = 4096, /* A page */
751 .minTexelBufferOffsetAlignment = 1,
752 .minUniformBufferOffsetAlignment = 4,
753 .minStorageBufferOffsetAlignment = 4,
754 .minTexelOffset = -32,
755 .maxTexelOffset = 31,
756 .minTexelGatherOffset = -32,
757 .maxTexelGatherOffset = 31,
758 .minInterpolationOffset = -2,
759 .maxInterpolationOffset = 2,
760 .subPixelInterpolationOffsetBits = 8,
761 .maxFramebufferWidth = (1 << 14),
762 .maxFramebufferHeight = (1 << 14),
763 .maxFramebufferLayers = (1 << 10),
764 .framebufferColorSampleCounts = sample_counts,
765 .framebufferDepthSampleCounts = sample_counts,
766 .framebufferStencilSampleCounts = sample_counts,
767 .framebufferNoAttachmentsSampleCounts = sample_counts,
768 .maxColorAttachments = MAX_RTS,
769 .sampledImageColorSampleCounts = sample_counts,
770 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
771 .sampledImageDepthSampleCounts = sample_counts,
772 .sampledImageStencilSampleCounts = sample_counts,
773 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
774 .maxSampleMaskWords = 1,
775 .timestampComputeAndGraphics = true,
776 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
777 .maxClipDistances = 8,
778 .maxCullDistances = 8,
779 .maxCombinedClipAndCullDistances = 8,
780 .discreteQueuePriorities = 1,
781 .pointSizeRange = { 0.125, 255.875 },
782 .lineWidthRange = { 0.0, 7.9921875 },
783 .pointSizeGranularity = (1.0 / 8.0),
784 .lineWidthGranularity = (1.0 / 128.0),
785 .strictLines = false, /* FINISHME */
786 .standardSampleLocations = true,
787 .optimalBufferCopyOffsetAlignment = 128,
788 .optimalBufferCopyRowPitchAlignment = 128,
789 .nonCoherentAtomSize = 64,
790 };
791
792 *pProperties = (VkPhysicalDeviceProperties) {
793 .apiVersion = radv_physical_device_api_version(pdevice),
794 .driverVersion = vk_get_driver_version(),
795 .vendorID = ATI_VENDOR_ID,
796 .deviceID = pdevice->rad_info.pci_id,
797 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
798 .limits = limits,
799 .sparseProperties = {0},
800 };
801
802 strcpy(pProperties->deviceName, pdevice->name);
803 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
804 }
805
806 void radv_GetPhysicalDeviceProperties2KHR(
807 VkPhysicalDevice physicalDevice,
808 VkPhysicalDeviceProperties2KHR *pProperties)
809 {
810 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
811 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
812
813 vk_foreach_struct(ext, pProperties->pNext) {
814 switch (ext->sType) {
815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
816 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
817 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
818 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
819 break;
820 }
821 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
822 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
823 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
824 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
825 properties->deviceLUIDValid = false;
826 break;
827 }
828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
829 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
830 properties->maxMultiviewViewCount = MAX_VIEWS;
831 properties->maxMultiviewInstanceIndex = INT_MAX;
832 break;
833 }
834 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
835 VkPhysicalDevicePointClippingPropertiesKHR *properties =
836 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
837 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
838 break;
839 }
840 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
841 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
842 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
843 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
847 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
848 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
849 properties->minImportedHostPointerAlignment = 4096;
850 break;
851 }
852 default:
853 break;
854 }
855 }
856 }
857
858 static void radv_get_physical_device_queue_family_properties(
859 struct radv_physical_device* pdevice,
860 uint32_t* pCount,
861 VkQueueFamilyProperties** pQueueFamilyProperties)
862 {
863 int num_queue_families = 1;
864 int idx;
865 if (pdevice->rad_info.num_compute_rings > 0 &&
866 pdevice->rad_info.chip_class >= CIK &&
867 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
868 num_queue_families++;
869
870 if (pQueueFamilyProperties == NULL) {
871 *pCount = num_queue_families;
872 return;
873 }
874
875 if (!*pCount)
876 return;
877
878 idx = 0;
879 if (*pCount >= 1) {
880 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
881 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
882 VK_QUEUE_COMPUTE_BIT |
883 VK_QUEUE_TRANSFER_BIT |
884 VK_QUEUE_SPARSE_BINDING_BIT,
885 .queueCount = 1,
886 .timestampValidBits = 64,
887 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
888 };
889 idx++;
890 }
891
892 if (pdevice->rad_info.num_compute_rings > 0 &&
893 pdevice->rad_info.chip_class >= CIK &&
894 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
895 if (*pCount > idx) {
896 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
897 .queueFlags = VK_QUEUE_COMPUTE_BIT |
898 VK_QUEUE_TRANSFER_BIT |
899 VK_QUEUE_SPARSE_BINDING_BIT,
900 .queueCount = pdevice->rad_info.num_compute_rings,
901 .timestampValidBits = 64,
902 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
903 };
904 idx++;
905 }
906 }
907 *pCount = idx;
908 }
909
910 void radv_GetPhysicalDeviceQueueFamilyProperties(
911 VkPhysicalDevice physicalDevice,
912 uint32_t* pCount,
913 VkQueueFamilyProperties* pQueueFamilyProperties)
914 {
915 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
916 if (!pQueueFamilyProperties) {
917 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
918 return;
919 }
920 VkQueueFamilyProperties *properties[] = {
921 pQueueFamilyProperties + 0,
922 pQueueFamilyProperties + 1,
923 pQueueFamilyProperties + 2,
924 };
925 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
926 assert(*pCount <= 3);
927 }
928
929 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
930 VkPhysicalDevice physicalDevice,
931 uint32_t* pCount,
932 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
933 {
934 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
935 if (!pQueueFamilyProperties) {
936 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
937 return;
938 }
939 VkQueueFamilyProperties *properties[] = {
940 &pQueueFamilyProperties[0].queueFamilyProperties,
941 &pQueueFamilyProperties[1].queueFamilyProperties,
942 &pQueueFamilyProperties[2].queueFamilyProperties,
943 };
944 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
945 assert(*pCount <= 3);
946 }
947
948 void radv_GetPhysicalDeviceMemoryProperties(
949 VkPhysicalDevice physicalDevice,
950 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
951 {
952 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
953
954 *pMemoryProperties = physical_device->memory_properties;
955 }
956
957 void radv_GetPhysicalDeviceMemoryProperties2KHR(
958 VkPhysicalDevice physicalDevice,
959 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
960 {
961 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
962 &pMemoryProperties->memoryProperties);
963 }
964
965 VkResult radv_GetMemoryHostPointerPropertiesEXT(
966 VkDevice _device,
967 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
968 const void *pHostPointer,
969 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
970 {
971 RADV_FROM_HANDLE(radv_device, device, _device);
972
973 switch (handleType)
974 {
975 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
976 const struct radv_physical_device *physical_device = device->physical_device;
977 uint32_t memoryTypeBits = 0;
978 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
979 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
980 memoryTypeBits = (1 << i);
981 break;
982 }
983 }
984 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
985 return VK_SUCCESS;
986 }
987 default:
988 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
989 }
990 }
991
992 static enum radeon_ctx_priority
993 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
994 {
995 /* Default to MEDIUM when a specific global priority isn't requested */
996 if (!pObj)
997 return RADEON_CTX_PRIORITY_MEDIUM;
998
999 switch(pObj->globalPriority) {
1000 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1001 return RADEON_CTX_PRIORITY_REALTIME;
1002 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1003 return RADEON_CTX_PRIORITY_HIGH;
1004 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1005 return RADEON_CTX_PRIORITY_MEDIUM;
1006 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1007 return RADEON_CTX_PRIORITY_LOW;
1008 default:
1009 unreachable("Illegal global priority value");
1010 return RADEON_CTX_PRIORITY_INVALID;
1011 }
1012 }
1013
1014 static int
1015 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1016 uint32_t queue_family_index, int idx,
1017 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1018 {
1019 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1020 queue->device = device;
1021 queue->queue_family_index = queue_family_index;
1022 queue->queue_idx = idx;
1023 queue->priority = radv_get_queue_global_priority(global_priority);
1024
1025 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1026 if (!queue->hw_ctx)
1027 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1028
1029 return VK_SUCCESS;
1030 }
1031
1032 static void
1033 radv_queue_finish(struct radv_queue *queue)
1034 {
1035 if (queue->hw_ctx)
1036 queue->device->ws->ctx_destroy(queue->hw_ctx);
1037
1038 if (queue->initial_full_flush_preamble_cs)
1039 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1040 if (queue->initial_preamble_cs)
1041 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1042 if (queue->continue_preamble_cs)
1043 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1044 if (queue->descriptor_bo)
1045 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1046 if (queue->scratch_bo)
1047 queue->device->ws->buffer_destroy(queue->scratch_bo);
1048 if (queue->esgs_ring_bo)
1049 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1050 if (queue->gsvs_ring_bo)
1051 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1052 if (queue->tess_factor_ring_bo)
1053 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1054 if (queue->tess_offchip_ring_bo)
1055 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1056 if (queue->compute_scratch_bo)
1057 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1058 }
1059
1060 static void
1061 radv_device_init_gs_info(struct radv_device *device)
1062 {
1063 switch (device->physical_device->rad_info.family) {
1064 case CHIP_OLAND:
1065 case CHIP_HAINAN:
1066 case CHIP_KAVERI:
1067 case CHIP_KABINI:
1068 case CHIP_MULLINS:
1069 case CHIP_ICELAND:
1070 case CHIP_CARRIZO:
1071 case CHIP_STONEY:
1072 device->gs_table_depth = 16;
1073 return;
1074 case CHIP_TAHITI:
1075 case CHIP_PITCAIRN:
1076 case CHIP_VERDE:
1077 case CHIP_BONAIRE:
1078 case CHIP_HAWAII:
1079 case CHIP_TONGA:
1080 case CHIP_FIJI:
1081 case CHIP_POLARIS10:
1082 case CHIP_POLARIS11:
1083 case CHIP_POLARIS12:
1084 case CHIP_VEGA10:
1085 case CHIP_RAVEN:
1086 device->gs_table_depth = 32;
1087 return;
1088 default:
1089 unreachable("unknown GPU");
1090 }
1091 }
1092
1093 VkResult radv_CreateDevice(
1094 VkPhysicalDevice physicalDevice,
1095 const VkDeviceCreateInfo* pCreateInfo,
1096 const VkAllocationCallbacks* pAllocator,
1097 VkDevice* pDevice)
1098 {
1099 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1100 VkResult result;
1101 struct radv_device *device;
1102
1103 bool keep_shader_info = false;
1104
1105 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1106 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1107 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1108 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1109
1110 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1111 keep_shader_info = true;
1112 }
1113
1114 /* Check enabled features */
1115 if (pCreateInfo->pEnabledFeatures) {
1116 VkPhysicalDeviceFeatures supported_features;
1117 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1118 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1119 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1120 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1121 for (uint32_t i = 0; i < num_features; i++) {
1122 if (enabled_feature[i] && !supported_feature[i])
1123 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1124 }
1125 }
1126
1127 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1128 sizeof(*device), 8,
1129 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1130 if (!device)
1131 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1132
1133 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1134 device->instance = physical_device->instance;
1135 device->physical_device = physical_device;
1136
1137 device->ws = physical_device->ws;
1138 if (pAllocator)
1139 device->alloc = *pAllocator;
1140 else
1141 device->alloc = physical_device->instance->alloc;
1142
1143 mtx_init(&device->shader_slab_mutex, mtx_plain);
1144 list_inithead(&device->shader_slabs);
1145
1146 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1147 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1148 uint32_t qfi = queue_create->queueFamilyIndex;
1149 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1150 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1151
1152 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1153
1154 device->queues[qfi] = vk_alloc(&device->alloc,
1155 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1156 if (!device->queues[qfi]) {
1157 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1158 goto fail;
1159 }
1160
1161 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1162
1163 device->queue_count[qfi] = queue_create->queueCount;
1164
1165 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1166 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1167 if (result != VK_SUCCESS)
1168 goto fail;
1169 }
1170 }
1171
1172 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1173 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1174
1175 /* Disabled and not implemented for now. */
1176 device->dfsm_allowed = device->pbb_allowed && false;
1177
1178 #ifdef ANDROID
1179 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1180 #endif
1181
1182 device->llvm_supports_spill = true;
1183
1184 /* The maximum number of scratch waves. Scratch space isn't divided
1185 * evenly between CUs. The number is only a function of the number of CUs.
1186 * We can decrease the constant to decrease the scratch buffer size.
1187 *
1188 * sctx->scratch_waves must be >= the maximum posible size of
1189 * 1 threadgroup, so that the hw doesn't hang from being unable
1190 * to start any.
1191 *
1192 * The recommended value is 4 per CU at most. Higher numbers don't
1193 * bring much benefit, but they still occupy chip resources (think
1194 * async compute). I've seen ~2% performance difference between 4 and 32.
1195 */
1196 uint32_t max_threads_per_block = 2048;
1197 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1198 max_threads_per_block / 64);
1199
1200 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1201 S_00B800_FORCE_START_AT_000(1);
1202
1203 if (device->physical_device->rad_info.chip_class >= CIK) {
1204 /* If the KMD allows it (there is a KMD hw register for it),
1205 * allow launching waves out-of-order.
1206 */
1207 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1208 }
1209
1210 radv_device_init_gs_info(device);
1211
1212 device->tess_offchip_block_dw_size =
1213 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1214 device->has_distributed_tess =
1215 device->physical_device->rad_info.chip_class >= VI &&
1216 device->physical_device->rad_info.max_se >= 2;
1217
1218 if (getenv("RADV_TRACE_FILE")) {
1219 keep_shader_info = true;
1220
1221 if (!radv_init_trace(device))
1222 goto fail;
1223 }
1224
1225 device->keep_shader_info = keep_shader_info;
1226
1227 result = radv_device_init_meta(device);
1228 if (result != VK_SUCCESS)
1229 goto fail;
1230
1231 radv_device_init_msaa(device);
1232
1233 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1234 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1235 switch (family) {
1236 case RADV_QUEUE_GENERAL:
1237 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1238 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1239 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1240 break;
1241 case RADV_QUEUE_COMPUTE:
1242 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1243 radeon_emit(device->empty_cs[family], 0);
1244 break;
1245 }
1246 device->ws->cs_finalize(device->empty_cs[family]);
1247 }
1248
1249 if (device->physical_device->rad_info.chip_class >= CIK)
1250 cik_create_gfx_config(device);
1251
1252 VkPipelineCacheCreateInfo ci;
1253 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1254 ci.pNext = NULL;
1255 ci.flags = 0;
1256 ci.pInitialData = NULL;
1257 ci.initialDataSize = 0;
1258 VkPipelineCache pc;
1259 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1260 &ci, NULL, &pc);
1261 if (result != VK_SUCCESS)
1262 goto fail_meta;
1263
1264 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1265
1266 *pDevice = radv_device_to_handle(device);
1267 return VK_SUCCESS;
1268
1269 fail_meta:
1270 radv_device_finish_meta(device);
1271 fail:
1272 if (device->trace_bo)
1273 device->ws->buffer_destroy(device->trace_bo);
1274
1275 if (device->gfx_init)
1276 device->ws->buffer_destroy(device->gfx_init);
1277
1278 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1279 for (unsigned q = 0; q < device->queue_count[i]; q++)
1280 radv_queue_finish(&device->queues[i][q]);
1281 if (device->queue_count[i])
1282 vk_free(&device->alloc, device->queues[i]);
1283 }
1284
1285 vk_free(&device->alloc, device);
1286 return result;
1287 }
1288
1289 void radv_DestroyDevice(
1290 VkDevice _device,
1291 const VkAllocationCallbacks* pAllocator)
1292 {
1293 RADV_FROM_HANDLE(radv_device, device, _device);
1294
1295 if (!device)
1296 return;
1297
1298 if (device->trace_bo)
1299 device->ws->buffer_destroy(device->trace_bo);
1300
1301 if (device->gfx_init)
1302 device->ws->buffer_destroy(device->gfx_init);
1303
1304 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1305 for (unsigned q = 0; q < device->queue_count[i]; q++)
1306 radv_queue_finish(&device->queues[i][q]);
1307 if (device->queue_count[i])
1308 vk_free(&device->alloc, device->queues[i]);
1309 if (device->empty_cs[i])
1310 device->ws->cs_destroy(device->empty_cs[i]);
1311 }
1312 radv_device_finish_meta(device);
1313
1314 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1315 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1316
1317 radv_destroy_shader_slabs(device);
1318
1319 vk_free(&device->alloc, device);
1320 }
1321
1322 VkResult radv_EnumerateInstanceLayerProperties(
1323 uint32_t* pPropertyCount,
1324 VkLayerProperties* pProperties)
1325 {
1326 if (pProperties == NULL) {
1327 *pPropertyCount = 0;
1328 return VK_SUCCESS;
1329 }
1330
1331 /* None supported at this time */
1332 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1333 }
1334
1335 VkResult radv_EnumerateDeviceLayerProperties(
1336 VkPhysicalDevice physicalDevice,
1337 uint32_t* pPropertyCount,
1338 VkLayerProperties* pProperties)
1339 {
1340 if (pProperties == NULL) {
1341 *pPropertyCount = 0;
1342 return VK_SUCCESS;
1343 }
1344
1345 /* None supported at this time */
1346 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1347 }
1348
1349 void radv_GetDeviceQueue(
1350 VkDevice _device,
1351 uint32_t queueFamilyIndex,
1352 uint32_t queueIndex,
1353 VkQueue* pQueue)
1354 {
1355 RADV_FROM_HANDLE(radv_device, device, _device);
1356
1357 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1358 }
1359
1360 static void
1361 fill_geom_tess_rings(struct radv_queue *queue,
1362 uint32_t *map,
1363 bool add_sample_positions,
1364 uint32_t esgs_ring_size,
1365 struct radeon_winsys_bo *esgs_ring_bo,
1366 uint32_t gsvs_ring_size,
1367 struct radeon_winsys_bo *gsvs_ring_bo,
1368 uint32_t tess_factor_ring_size,
1369 struct radeon_winsys_bo *tess_factor_ring_bo,
1370 uint32_t tess_offchip_ring_size,
1371 struct radeon_winsys_bo *tess_offchip_ring_bo)
1372 {
1373 uint64_t esgs_va = 0, gsvs_va = 0;
1374 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1375 uint32_t *desc = &map[4];
1376
1377 if (esgs_ring_bo)
1378 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1379 if (gsvs_ring_bo)
1380 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1381 if (tess_factor_ring_bo)
1382 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1383 if (tess_offchip_ring_bo)
1384 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1385
1386 /* stride 0, num records - size, add tid, swizzle, elsize4,
1387 index stride 64 */
1388 desc[0] = esgs_va;
1389 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1390 S_008F04_STRIDE(0) |
1391 S_008F04_SWIZZLE_ENABLE(true);
1392 desc[2] = esgs_ring_size;
1393 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1394 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1395 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1396 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1397 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1398 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1399 S_008F0C_ELEMENT_SIZE(1) |
1400 S_008F0C_INDEX_STRIDE(3) |
1401 S_008F0C_ADD_TID_ENABLE(true);
1402
1403 desc += 4;
1404 /* GS entry for ES->GS ring */
1405 /* stride 0, num records - size, elsize0,
1406 index stride 0 */
1407 desc[0] = esgs_va;
1408 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1409 S_008F04_STRIDE(0) |
1410 S_008F04_SWIZZLE_ENABLE(false);
1411 desc[2] = esgs_ring_size;
1412 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1413 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1414 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1415 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1416 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1417 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1418 S_008F0C_ELEMENT_SIZE(0) |
1419 S_008F0C_INDEX_STRIDE(0) |
1420 S_008F0C_ADD_TID_ENABLE(false);
1421
1422 desc += 4;
1423 /* VS entry for GS->VS ring */
1424 /* stride 0, num records - size, elsize0,
1425 index stride 0 */
1426 desc[0] = gsvs_va;
1427 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1428 S_008F04_STRIDE(0) |
1429 S_008F04_SWIZZLE_ENABLE(false);
1430 desc[2] = gsvs_ring_size;
1431 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1432 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1433 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1434 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1435 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1436 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1437 S_008F0C_ELEMENT_SIZE(0) |
1438 S_008F0C_INDEX_STRIDE(0) |
1439 S_008F0C_ADD_TID_ENABLE(false);
1440 desc += 4;
1441
1442 /* stride gsvs_itemsize, num records 64
1443 elsize 4, index stride 16 */
1444 /* shader will patch stride and desc[2] */
1445 desc[0] = gsvs_va;
1446 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1447 S_008F04_STRIDE(0) |
1448 S_008F04_SWIZZLE_ENABLE(true);
1449 desc[2] = 0;
1450 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1451 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1452 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1453 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1454 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1455 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1456 S_008F0C_ELEMENT_SIZE(1) |
1457 S_008F0C_INDEX_STRIDE(1) |
1458 S_008F0C_ADD_TID_ENABLE(true);
1459 desc += 4;
1460
1461 desc[0] = tess_factor_va;
1462 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1463 S_008F04_STRIDE(0) |
1464 S_008F04_SWIZZLE_ENABLE(false);
1465 desc[2] = tess_factor_ring_size;
1466 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1467 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1468 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1469 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1470 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1471 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1472 S_008F0C_ELEMENT_SIZE(0) |
1473 S_008F0C_INDEX_STRIDE(0) |
1474 S_008F0C_ADD_TID_ENABLE(false);
1475 desc += 4;
1476
1477 desc[0] = tess_offchip_va;
1478 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1479 S_008F04_STRIDE(0) |
1480 S_008F04_SWIZZLE_ENABLE(false);
1481 desc[2] = tess_offchip_ring_size;
1482 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1483 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1484 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1485 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1486 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1487 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1488 S_008F0C_ELEMENT_SIZE(0) |
1489 S_008F0C_INDEX_STRIDE(0) |
1490 S_008F0C_ADD_TID_ENABLE(false);
1491 desc += 4;
1492
1493 /* add sample positions after all rings */
1494 memcpy(desc, queue->device->sample_locations_1x, 8);
1495 desc += 2;
1496 memcpy(desc, queue->device->sample_locations_2x, 16);
1497 desc += 4;
1498 memcpy(desc, queue->device->sample_locations_4x, 32);
1499 desc += 8;
1500 memcpy(desc, queue->device->sample_locations_8x, 64);
1501 desc += 16;
1502 memcpy(desc, queue->device->sample_locations_16x, 128);
1503 }
1504
1505 static unsigned
1506 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1507 {
1508 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1509 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1510 device->physical_device->rad_info.family != CHIP_STONEY;
1511 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1512 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1513 device->physical_device->rad_info.max_se;
1514 unsigned offchip_granularity;
1515 unsigned hs_offchip_param;
1516 switch (device->tess_offchip_block_dw_size) {
1517 default:
1518 assert(0);
1519 /* fall through */
1520 case 8192:
1521 offchip_granularity = V_03093C_X_8K_DWORDS;
1522 break;
1523 case 4096:
1524 offchip_granularity = V_03093C_X_4K_DWORDS;
1525 break;
1526 }
1527
1528 switch (device->physical_device->rad_info.chip_class) {
1529 case SI:
1530 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1531 break;
1532 case CIK:
1533 case VI:
1534 case GFX9:
1535 default:
1536 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1537 break;
1538 }
1539
1540 *max_offchip_buffers_p = max_offchip_buffers;
1541 if (device->physical_device->rad_info.chip_class >= CIK) {
1542 if (device->physical_device->rad_info.chip_class >= VI)
1543 --max_offchip_buffers;
1544 hs_offchip_param =
1545 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1546 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1547 } else {
1548 hs_offchip_param =
1549 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1550 }
1551 return hs_offchip_param;
1552 }
1553
1554 static VkResult
1555 radv_get_preamble_cs(struct radv_queue *queue,
1556 uint32_t scratch_size,
1557 uint32_t compute_scratch_size,
1558 uint32_t esgs_ring_size,
1559 uint32_t gsvs_ring_size,
1560 bool needs_tess_rings,
1561 bool needs_sample_positions,
1562 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1563 struct radeon_winsys_cs **initial_preamble_cs,
1564 struct radeon_winsys_cs **continue_preamble_cs)
1565 {
1566 struct radeon_winsys_bo *scratch_bo = NULL;
1567 struct radeon_winsys_bo *descriptor_bo = NULL;
1568 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1569 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1570 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1571 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1572 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1573 struct radeon_winsys_cs *dest_cs[3] = {0};
1574 bool add_tess_rings = false, add_sample_positions = false;
1575 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1576 unsigned max_offchip_buffers;
1577 unsigned hs_offchip_param = 0;
1578 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1579 if (!queue->has_tess_rings) {
1580 if (needs_tess_rings)
1581 add_tess_rings = true;
1582 }
1583 if (!queue->has_sample_positions) {
1584 if (needs_sample_positions)
1585 add_sample_positions = true;
1586 }
1587 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1588 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1589 &max_offchip_buffers);
1590 tess_offchip_ring_size = max_offchip_buffers *
1591 queue->device->tess_offchip_block_dw_size * 4;
1592
1593 if (scratch_size <= queue->scratch_size &&
1594 compute_scratch_size <= queue->compute_scratch_size &&
1595 esgs_ring_size <= queue->esgs_ring_size &&
1596 gsvs_ring_size <= queue->gsvs_ring_size &&
1597 !add_tess_rings && !add_sample_positions &&
1598 queue->initial_preamble_cs) {
1599 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1600 *initial_preamble_cs = queue->initial_preamble_cs;
1601 *continue_preamble_cs = queue->continue_preamble_cs;
1602 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1603 *continue_preamble_cs = NULL;
1604 return VK_SUCCESS;
1605 }
1606
1607 if (scratch_size > queue->scratch_size) {
1608 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1609 scratch_size,
1610 4096,
1611 RADEON_DOMAIN_VRAM,
1612 ring_bo_flags);
1613 if (!scratch_bo)
1614 goto fail;
1615 } else
1616 scratch_bo = queue->scratch_bo;
1617
1618 if (compute_scratch_size > queue->compute_scratch_size) {
1619 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1620 compute_scratch_size,
1621 4096,
1622 RADEON_DOMAIN_VRAM,
1623 ring_bo_flags);
1624 if (!compute_scratch_bo)
1625 goto fail;
1626
1627 } else
1628 compute_scratch_bo = queue->compute_scratch_bo;
1629
1630 if (esgs_ring_size > queue->esgs_ring_size) {
1631 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1632 esgs_ring_size,
1633 4096,
1634 RADEON_DOMAIN_VRAM,
1635 ring_bo_flags);
1636 if (!esgs_ring_bo)
1637 goto fail;
1638 } else {
1639 esgs_ring_bo = queue->esgs_ring_bo;
1640 esgs_ring_size = queue->esgs_ring_size;
1641 }
1642
1643 if (gsvs_ring_size > queue->gsvs_ring_size) {
1644 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1645 gsvs_ring_size,
1646 4096,
1647 RADEON_DOMAIN_VRAM,
1648 ring_bo_flags);
1649 if (!gsvs_ring_bo)
1650 goto fail;
1651 } else {
1652 gsvs_ring_bo = queue->gsvs_ring_bo;
1653 gsvs_ring_size = queue->gsvs_ring_size;
1654 }
1655
1656 if (add_tess_rings) {
1657 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1658 tess_factor_ring_size,
1659 256,
1660 RADEON_DOMAIN_VRAM,
1661 ring_bo_flags);
1662 if (!tess_factor_ring_bo)
1663 goto fail;
1664 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1665 tess_offchip_ring_size,
1666 256,
1667 RADEON_DOMAIN_VRAM,
1668 ring_bo_flags);
1669 if (!tess_offchip_ring_bo)
1670 goto fail;
1671 } else {
1672 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1673 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1674 }
1675
1676 if (scratch_bo != queue->scratch_bo ||
1677 esgs_ring_bo != queue->esgs_ring_bo ||
1678 gsvs_ring_bo != queue->gsvs_ring_bo ||
1679 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1680 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1681 uint32_t size = 0;
1682 if (gsvs_ring_bo || esgs_ring_bo ||
1683 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1684 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1685 if (add_sample_positions)
1686 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1687 }
1688 else if (scratch_bo)
1689 size = 8; /* 2 dword */
1690
1691 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1692 size,
1693 4096,
1694 RADEON_DOMAIN_VRAM,
1695 RADEON_FLAG_CPU_ACCESS |
1696 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1697 RADEON_FLAG_READ_ONLY);
1698 if (!descriptor_bo)
1699 goto fail;
1700 } else
1701 descriptor_bo = queue->descriptor_bo;
1702
1703 for(int i = 0; i < 3; ++i) {
1704 struct radeon_winsys_cs *cs = NULL;
1705 cs = queue->device->ws->cs_create(queue->device->ws,
1706 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1707 if (!cs)
1708 goto fail;
1709
1710 dest_cs[i] = cs;
1711
1712 if (scratch_bo)
1713 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1714
1715 if (esgs_ring_bo)
1716 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1717
1718 if (gsvs_ring_bo)
1719 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1720
1721 if (tess_factor_ring_bo)
1722 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1723
1724 if (tess_offchip_ring_bo)
1725 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1726
1727 if (descriptor_bo)
1728 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1729
1730 if (descriptor_bo != queue->descriptor_bo) {
1731 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1732
1733 if (scratch_bo) {
1734 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1735 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1736 S_008F04_SWIZZLE_ENABLE(1);
1737 map[0] = scratch_va;
1738 map[1] = rsrc1;
1739 }
1740
1741 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1742 add_sample_positions)
1743 fill_geom_tess_rings(queue, map, add_sample_positions,
1744 esgs_ring_size, esgs_ring_bo,
1745 gsvs_ring_size, gsvs_ring_bo,
1746 tess_factor_ring_size, tess_factor_ring_bo,
1747 tess_offchip_ring_size, tess_offchip_ring_bo);
1748
1749 queue->device->ws->buffer_unmap(descriptor_bo);
1750 }
1751
1752 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1753 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1754 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1755 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1756 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1757 }
1758
1759 if (esgs_ring_bo || gsvs_ring_bo) {
1760 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1761 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1762 radeon_emit(cs, esgs_ring_size >> 8);
1763 radeon_emit(cs, gsvs_ring_size >> 8);
1764 } else {
1765 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1766 radeon_emit(cs, esgs_ring_size >> 8);
1767 radeon_emit(cs, gsvs_ring_size >> 8);
1768 }
1769 }
1770
1771 if (tess_factor_ring_bo) {
1772 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1773 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1774 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1775 S_030938_SIZE(tess_factor_ring_size / 4));
1776 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1777 tf_va >> 8);
1778 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1779 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1780 tf_va >> 40);
1781 }
1782 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1783 } else {
1784 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1785 S_008988_SIZE(tess_factor_ring_size / 4));
1786 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1787 tf_va >> 8);
1788 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1789 hs_offchip_param);
1790 }
1791 }
1792
1793 if (descriptor_bo) {
1794 uint64_t va = radv_buffer_get_va(descriptor_bo);
1795 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1796 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1797 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1798 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1799 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1800
1801 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1802 radeon_set_sh_reg_seq(cs, regs[i], 2);
1803 radeon_emit(cs, va);
1804 radeon_emit(cs, va >> 32);
1805 }
1806 } else {
1807 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1808 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1809 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1810 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1811 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1812 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1813
1814 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1815 radeon_set_sh_reg_seq(cs, regs[i], 2);
1816 radeon_emit(cs, va);
1817 radeon_emit(cs, va >> 32);
1818 }
1819 }
1820 }
1821
1822 if (compute_scratch_bo) {
1823 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1824 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1825 S_008F04_SWIZZLE_ENABLE(1);
1826
1827 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1828
1829 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1830 radeon_emit(cs, scratch_va);
1831 radeon_emit(cs, rsrc1);
1832 }
1833
1834 if (i == 0) {
1835 si_cs_emit_cache_flush(cs,
1836 queue->device->physical_device->rad_info.chip_class,
1837 NULL, 0,
1838 queue->queue_family_index == RING_COMPUTE &&
1839 queue->device->physical_device->rad_info.chip_class >= CIK,
1840 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1841 RADV_CMD_FLAG_INV_ICACHE |
1842 RADV_CMD_FLAG_INV_SMEM_L1 |
1843 RADV_CMD_FLAG_INV_VMEM_L1 |
1844 RADV_CMD_FLAG_INV_GLOBAL_L2);
1845 } else if (i == 1) {
1846 si_cs_emit_cache_flush(cs,
1847 queue->device->physical_device->rad_info.chip_class,
1848 NULL, 0,
1849 queue->queue_family_index == RING_COMPUTE &&
1850 queue->device->physical_device->rad_info.chip_class >= CIK,
1851 RADV_CMD_FLAG_INV_ICACHE |
1852 RADV_CMD_FLAG_INV_SMEM_L1 |
1853 RADV_CMD_FLAG_INV_VMEM_L1 |
1854 RADV_CMD_FLAG_INV_GLOBAL_L2);
1855 }
1856
1857 if (!queue->device->ws->cs_finalize(cs))
1858 goto fail;
1859 }
1860
1861 if (queue->initial_full_flush_preamble_cs)
1862 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1863
1864 if (queue->initial_preamble_cs)
1865 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1866
1867 if (queue->continue_preamble_cs)
1868 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1869
1870 queue->initial_full_flush_preamble_cs = dest_cs[0];
1871 queue->initial_preamble_cs = dest_cs[1];
1872 queue->continue_preamble_cs = dest_cs[2];
1873
1874 if (scratch_bo != queue->scratch_bo) {
1875 if (queue->scratch_bo)
1876 queue->device->ws->buffer_destroy(queue->scratch_bo);
1877 queue->scratch_bo = scratch_bo;
1878 queue->scratch_size = scratch_size;
1879 }
1880
1881 if (compute_scratch_bo != queue->compute_scratch_bo) {
1882 if (queue->compute_scratch_bo)
1883 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1884 queue->compute_scratch_bo = compute_scratch_bo;
1885 queue->compute_scratch_size = compute_scratch_size;
1886 }
1887
1888 if (esgs_ring_bo != queue->esgs_ring_bo) {
1889 if (queue->esgs_ring_bo)
1890 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1891 queue->esgs_ring_bo = esgs_ring_bo;
1892 queue->esgs_ring_size = esgs_ring_size;
1893 }
1894
1895 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1896 if (queue->gsvs_ring_bo)
1897 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1898 queue->gsvs_ring_bo = gsvs_ring_bo;
1899 queue->gsvs_ring_size = gsvs_ring_size;
1900 }
1901
1902 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1903 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1904 }
1905
1906 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1907 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1908 queue->has_tess_rings = true;
1909 }
1910
1911 if (descriptor_bo != queue->descriptor_bo) {
1912 if (queue->descriptor_bo)
1913 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1914
1915 queue->descriptor_bo = descriptor_bo;
1916 }
1917
1918 if (add_sample_positions)
1919 queue->has_sample_positions = true;
1920
1921 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1922 *initial_preamble_cs = queue->initial_preamble_cs;
1923 *continue_preamble_cs = queue->continue_preamble_cs;
1924 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1925 *continue_preamble_cs = NULL;
1926 return VK_SUCCESS;
1927 fail:
1928 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1929 if (dest_cs[i])
1930 queue->device->ws->cs_destroy(dest_cs[i]);
1931 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1932 queue->device->ws->buffer_destroy(descriptor_bo);
1933 if (scratch_bo && scratch_bo != queue->scratch_bo)
1934 queue->device->ws->buffer_destroy(scratch_bo);
1935 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1936 queue->device->ws->buffer_destroy(compute_scratch_bo);
1937 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1938 queue->device->ws->buffer_destroy(esgs_ring_bo);
1939 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1940 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1941 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1942 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1943 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1944 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1945 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1946 }
1947
1948 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1949 int num_sems,
1950 const VkSemaphore *sems,
1951 VkFence _fence,
1952 bool reset_temp)
1953 {
1954 int syncobj_idx = 0, sem_idx = 0;
1955
1956 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1957 return VK_SUCCESS;
1958
1959 for (uint32_t i = 0; i < num_sems; i++) {
1960 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1961
1962 if (sem->temp_syncobj || sem->syncobj)
1963 counts->syncobj_count++;
1964 else
1965 counts->sem_count++;
1966 }
1967
1968 if (_fence != VK_NULL_HANDLE) {
1969 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1970 if (fence->temp_syncobj || fence->syncobj)
1971 counts->syncobj_count++;
1972 }
1973
1974 if (counts->syncobj_count) {
1975 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1976 if (!counts->syncobj)
1977 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1978 }
1979
1980 if (counts->sem_count) {
1981 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1982 if (!counts->sem) {
1983 free(counts->syncobj);
1984 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1985 }
1986 }
1987
1988 for (uint32_t i = 0; i < num_sems; i++) {
1989 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1990
1991 if (sem->temp_syncobj) {
1992 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1993 }
1994 else if (sem->syncobj)
1995 counts->syncobj[syncobj_idx++] = sem->syncobj;
1996 else {
1997 assert(sem->sem);
1998 counts->sem[sem_idx++] = sem->sem;
1999 }
2000 }
2001
2002 if (_fence != VK_NULL_HANDLE) {
2003 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2004 if (fence->temp_syncobj)
2005 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2006 else if (fence->syncobj)
2007 counts->syncobj[syncobj_idx++] = fence->syncobj;
2008 }
2009
2010 return VK_SUCCESS;
2011 }
2012
2013 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2014 {
2015 free(sem_info->wait.syncobj);
2016 free(sem_info->wait.sem);
2017 free(sem_info->signal.syncobj);
2018 free(sem_info->signal.sem);
2019 }
2020
2021
2022 static void radv_free_temp_syncobjs(struct radv_device *device,
2023 int num_sems,
2024 const VkSemaphore *sems)
2025 {
2026 for (uint32_t i = 0; i < num_sems; i++) {
2027 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2028
2029 if (sem->temp_syncobj) {
2030 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2031 sem->temp_syncobj = 0;
2032 }
2033 }
2034 }
2035
2036 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2037 int num_wait_sems,
2038 const VkSemaphore *wait_sems,
2039 int num_signal_sems,
2040 const VkSemaphore *signal_sems,
2041 VkFence fence)
2042 {
2043 VkResult ret;
2044 memset(sem_info, 0, sizeof(*sem_info));
2045
2046 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2047 if (ret)
2048 return ret;
2049 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2050 if (ret)
2051 radv_free_sem_info(sem_info);
2052
2053 /* caller can override these */
2054 sem_info->cs_emit_wait = true;
2055 sem_info->cs_emit_signal = true;
2056 return ret;
2057 }
2058
2059 /* Signals fence as soon as all the work currently put on queue is done. */
2060 static VkResult radv_signal_fence(struct radv_queue *queue,
2061 struct radv_fence *fence)
2062 {
2063 int ret;
2064 VkResult result;
2065 struct radv_winsys_sem_info sem_info;
2066
2067 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2068 radv_fence_to_handle(fence));
2069 if (result != VK_SUCCESS)
2070 return result;
2071
2072 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2073 &queue->device->empty_cs[queue->queue_family_index],
2074 1, NULL, NULL, &sem_info,
2075 false, fence->fence);
2076 radv_free_sem_info(&sem_info);
2077
2078 /* TODO: find a better error */
2079 if (ret)
2080 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2081
2082 return VK_SUCCESS;
2083 }
2084
2085 VkResult radv_QueueSubmit(
2086 VkQueue _queue,
2087 uint32_t submitCount,
2088 const VkSubmitInfo* pSubmits,
2089 VkFence _fence)
2090 {
2091 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2092 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2093 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2094 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2095 int ret;
2096 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2097 uint32_t scratch_size = 0;
2098 uint32_t compute_scratch_size = 0;
2099 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2100 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2101 VkResult result;
2102 bool fence_emitted = false;
2103 bool tess_rings_needed = false;
2104 bool sample_positions_needed = false;
2105
2106 /* Do this first so failing to allocate scratch buffers can't result in
2107 * partially executed submissions. */
2108 for (uint32_t i = 0; i < submitCount; i++) {
2109 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2110 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2111 pSubmits[i].pCommandBuffers[j]);
2112
2113 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2114 compute_scratch_size = MAX2(compute_scratch_size,
2115 cmd_buffer->compute_scratch_size_needed);
2116 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2117 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2118 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2119 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2120 }
2121 }
2122
2123 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2124 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2125 sample_positions_needed, &initial_flush_preamble_cs,
2126 &initial_preamble_cs, &continue_preamble_cs);
2127 if (result != VK_SUCCESS)
2128 return result;
2129
2130 for (uint32_t i = 0; i < submitCount; i++) {
2131 struct radeon_winsys_cs **cs_array;
2132 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2133 bool can_patch = true;
2134 uint32_t advance;
2135 struct radv_winsys_sem_info sem_info;
2136
2137 result = radv_alloc_sem_info(&sem_info,
2138 pSubmits[i].waitSemaphoreCount,
2139 pSubmits[i].pWaitSemaphores,
2140 pSubmits[i].signalSemaphoreCount,
2141 pSubmits[i].pSignalSemaphores,
2142 _fence);
2143 if (result != VK_SUCCESS)
2144 return result;
2145
2146 if (!pSubmits[i].commandBufferCount) {
2147 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2148 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2149 &queue->device->empty_cs[queue->queue_family_index],
2150 1, NULL, NULL,
2151 &sem_info,
2152 false, base_fence);
2153 if (ret) {
2154 radv_loge("failed to submit CS %d\n", i);
2155 abort();
2156 }
2157 fence_emitted = true;
2158 }
2159 radv_free_sem_info(&sem_info);
2160 continue;
2161 }
2162
2163 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2164 (pSubmits[i].commandBufferCount));
2165
2166 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2167 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2168 pSubmits[i].pCommandBuffers[j]);
2169 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2170
2171 cs_array[j] = cmd_buffer->cs;
2172 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2173 can_patch = false;
2174
2175 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2176 }
2177
2178 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2179 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2180 advance = MIN2(max_cs_submission,
2181 pSubmits[i].commandBufferCount - j);
2182
2183 if (queue->device->trace_bo)
2184 *queue->device->trace_id_ptr = 0;
2185
2186 sem_info.cs_emit_wait = j == 0;
2187 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2188
2189 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2190 advance, initial_preamble, continue_preamble_cs,
2191 &sem_info,
2192 can_patch, base_fence);
2193
2194 if (ret) {
2195 radv_loge("failed to submit CS %d\n", i);
2196 abort();
2197 }
2198 fence_emitted = true;
2199 if (queue->device->trace_bo) {
2200 radv_check_gpu_hangs(queue, cs_array[j]);
2201 }
2202 }
2203
2204 radv_free_temp_syncobjs(queue->device,
2205 pSubmits[i].waitSemaphoreCount,
2206 pSubmits[i].pWaitSemaphores);
2207 radv_free_sem_info(&sem_info);
2208 free(cs_array);
2209 }
2210
2211 if (fence) {
2212 if (!fence_emitted) {
2213 radv_signal_fence(queue, fence);
2214 }
2215 fence->submitted = true;
2216 }
2217
2218 return VK_SUCCESS;
2219 }
2220
2221 VkResult radv_QueueWaitIdle(
2222 VkQueue _queue)
2223 {
2224 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2225
2226 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2227 radv_queue_family_to_ring(queue->queue_family_index),
2228 queue->queue_idx);
2229 return VK_SUCCESS;
2230 }
2231
2232 VkResult radv_DeviceWaitIdle(
2233 VkDevice _device)
2234 {
2235 RADV_FROM_HANDLE(radv_device, device, _device);
2236
2237 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2238 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2239 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2240 }
2241 }
2242 return VK_SUCCESS;
2243 }
2244
2245 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2246 VkInstance instance,
2247 const char* pName)
2248 {
2249 return radv_lookup_entrypoint(pName);
2250 }
2251
2252 /* The loader wants us to expose a second GetInstanceProcAddr function
2253 * to work around certain LD_PRELOAD issues seen in apps.
2254 */
2255 PUBLIC
2256 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2257 VkInstance instance,
2258 const char* pName);
2259
2260 PUBLIC
2261 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2262 VkInstance instance,
2263 const char* pName)
2264 {
2265 return radv_GetInstanceProcAddr(instance, pName);
2266 }
2267
2268 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2269 VkDevice device,
2270 const char* pName)
2271 {
2272 return radv_lookup_entrypoint(pName);
2273 }
2274
2275 bool radv_get_memory_fd(struct radv_device *device,
2276 struct radv_device_memory *memory,
2277 int *pFD)
2278 {
2279 struct radeon_bo_metadata metadata;
2280
2281 if (memory->image) {
2282 radv_init_metadata(device, memory->image, &metadata);
2283 device->ws->buffer_set_metadata(memory->bo, &metadata);
2284 }
2285
2286 return device->ws->buffer_get_fd(device->ws, memory->bo,
2287 pFD);
2288 }
2289
2290 static VkResult radv_alloc_memory(struct radv_device *device,
2291 const VkMemoryAllocateInfo* pAllocateInfo,
2292 const VkAllocationCallbacks* pAllocator,
2293 VkDeviceMemory* pMem)
2294 {
2295 struct radv_device_memory *mem;
2296 VkResult result;
2297 enum radeon_bo_domain domain;
2298 uint32_t flags = 0;
2299 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2300
2301 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2302
2303 if (pAllocateInfo->allocationSize == 0) {
2304 /* Apparently, this is allowed */
2305 *pMem = VK_NULL_HANDLE;
2306 return VK_SUCCESS;
2307 }
2308
2309 const VkImportMemoryFdInfoKHR *import_info =
2310 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2311 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2312 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2313 const VkExportMemoryAllocateInfoKHR *export_info =
2314 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2315 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2316 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2317
2318 const struct wsi_memory_allocate_info *wsi_info =
2319 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2320
2321 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2322 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2323 if (mem == NULL)
2324 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2325
2326 if (wsi_info && wsi_info->implicit_sync)
2327 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2328
2329 if (dedicate_info) {
2330 mem->image = radv_image_from_handle(dedicate_info->image);
2331 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2332 } else {
2333 mem->image = NULL;
2334 mem->buffer = NULL;
2335 }
2336
2337 mem->user_ptr = NULL;
2338
2339 if (import_info) {
2340 assert(import_info->handleType ==
2341 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2342 import_info->handleType ==
2343 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2344 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2345 NULL, NULL);
2346 if (!mem->bo) {
2347 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2348 goto fail;
2349 } else {
2350 close(import_info->fd);
2351 goto out_success;
2352 }
2353 }
2354
2355 if (host_ptr_info) {
2356 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2357 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2358 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2359 pAllocateInfo->allocationSize);
2360 if (!mem->bo) {
2361 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2362 goto fail;
2363 } else {
2364 mem->user_ptr = host_ptr_info->pHostPointer;
2365 goto out_success;
2366 }
2367 }
2368
2369 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2370 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2371 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2372 domain = RADEON_DOMAIN_GTT;
2373 else
2374 domain = RADEON_DOMAIN_VRAM;
2375
2376 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2377 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2378 else
2379 flags |= RADEON_FLAG_CPU_ACCESS;
2380
2381 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2382 flags |= RADEON_FLAG_GTT_WC;
2383
2384 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2385 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2386
2387 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2388 domain, flags);
2389
2390 if (!mem->bo) {
2391 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2392 goto fail;
2393 }
2394 mem->type_index = mem_type_index;
2395 out_success:
2396 *pMem = radv_device_memory_to_handle(mem);
2397
2398 return VK_SUCCESS;
2399
2400 fail:
2401 vk_free2(&device->alloc, pAllocator, mem);
2402
2403 return result;
2404 }
2405
2406 VkResult radv_AllocateMemory(
2407 VkDevice _device,
2408 const VkMemoryAllocateInfo* pAllocateInfo,
2409 const VkAllocationCallbacks* pAllocator,
2410 VkDeviceMemory* pMem)
2411 {
2412 RADV_FROM_HANDLE(radv_device, device, _device);
2413 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2414 }
2415
2416 void radv_FreeMemory(
2417 VkDevice _device,
2418 VkDeviceMemory _mem,
2419 const VkAllocationCallbacks* pAllocator)
2420 {
2421 RADV_FROM_HANDLE(radv_device, device, _device);
2422 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2423
2424 if (mem == NULL)
2425 return;
2426
2427 device->ws->buffer_destroy(mem->bo);
2428 mem->bo = NULL;
2429
2430 vk_free2(&device->alloc, pAllocator, mem);
2431 }
2432
2433 VkResult radv_MapMemory(
2434 VkDevice _device,
2435 VkDeviceMemory _memory,
2436 VkDeviceSize offset,
2437 VkDeviceSize size,
2438 VkMemoryMapFlags flags,
2439 void** ppData)
2440 {
2441 RADV_FROM_HANDLE(radv_device, device, _device);
2442 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2443
2444 if (mem == NULL) {
2445 *ppData = NULL;
2446 return VK_SUCCESS;
2447 }
2448
2449 if (mem->user_ptr)
2450 *ppData = mem->user_ptr;
2451 else
2452 *ppData = device->ws->buffer_map(mem->bo);
2453
2454 if (*ppData) {
2455 *ppData += offset;
2456 return VK_SUCCESS;
2457 }
2458
2459 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2460 }
2461
2462 void radv_UnmapMemory(
2463 VkDevice _device,
2464 VkDeviceMemory _memory)
2465 {
2466 RADV_FROM_HANDLE(radv_device, device, _device);
2467 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2468
2469 if (mem == NULL)
2470 return;
2471
2472 if (mem->user_ptr == NULL)
2473 device->ws->buffer_unmap(mem->bo);
2474 }
2475
2476 VkResult radv_FlushMappedMemoryRanges(
2477 VkDevice _device,
2478 uint32_t memoryRangeCount,
2479 const VkMappedMemoryRange* pMemoryRanges)
2480 {
2481 return VK_SUCCESS;
2482 }
2483
2484 VkResult radv_InvalidateMappedMemoryRanges(
2485 VkDevice _device,
2486 uint32_t memoryRangeCount,
2487 const VkMappedMemoryRange* pMemoryRanges)
2488 {
2489 return VK_SUCCESS;
2490 }
2491
2492 void radv_GetBufferMemoryRequirements(
2493 VkDevice _device,
2494 VkBuffer _buffer,
2495 VkMemoryRequirements* pMemoryRequirements)
2496 {
2497 RADV_FROM_HANDLE(radv_device, device, _device);
2498 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2499
2500 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2501
2502 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2503 pMemoryRequirements->alignment = 4096;
2504 else
2505 pMemoryRequirements->alignment = 16;
2506
2507 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2508 }
2509
2510 void radv_GetBufferMemoryRequirements2KHR(
2511 VkDevice device,
2512 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2513 VkMemoryRequirements2KHR* pMemoryRequirements)
2514 {
2515 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2516 &pMemoryRequirements->memoryRequirements);
2517 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2518 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2519 switch (ext->sType) {
2520 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2521 VkMemoryDedicatedRequirementsKHR *req =
2522 (VkMemoryDedicatedRequirementsKHR *) ext;
2523 req->requiresDedicatedAllocation = buffer->shareable;
2524 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2525 break;
2526 }
2527 default:
2528 break;
2529 }
2530 }
2531 }
2532
2533 void radv_GetImageMemoryRequirements(
2534 VkDevice _device,
2535 VkImage _image,
2536 VkMemoryRequirements* pMemoryRequirements)
2537 {
2538 RADV_FROM_HANDLE(radv_device, device, _device);
2539 RADV_FROM_HANDLE(radv_image, image, _image);
2540
2541 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2542
2543 pMemoryRequirements->size = image->size;
2544 pMemoryRequirements->alignment = image->alignment;
2545 }
2546
2547 void radv_GetImageMemoryRequirements2KHR(
2548 VkDevice device,
2549 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2550 VkMemoryRequirements2KHR* pMemoryRequirements)
2551 {
2552 radv_GetImageMemoryRequirements(device, pInfo->image,
2553 &pMemoryRequirements->memoryRequirements);
2554
2555 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2556
2557 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2558 switch (ext->sType) {
2559 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2560 VkMemoryDedicatedRequirementsKHR *req =
2561 (VkMemoryDedicatedRequirementsKHR *) ext;
2562 req->requiresDedicatedAllocation = image->shareable;
2563 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2564 break;
2565 }
2566 default:
2567 break;
2568 }
2569 }
2570 }
2571
2572 void radv_GetImageSparseMemoryRequirements(
2573 VkDevice device,
2574 VkImage image,
2575 uint32_t* pSparseMemoryRequirementCount,
2576 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2577 {
2578 stub();
2579 }
2580
2581 void radv_GetImageSparseMemoryRequirements2KHR(
2582 VkDevice device,
2583 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2584 uint32_t* pSparseMemoryRequirementCount,
2585 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2586 {
2587 stub();
2588 }
2589
2590 void radv_GetDeviceMemoryCommitment(
2591 VkDevice device,
2592 VkDeviceMemory memory,
2593 VkDeviceSize* pCommittedMemoryInBytes)
2594 {
2595 *pCommittedMemoryInBytes = 0;
2596 }
2597
2598 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2599 uint32_t bindInfoCount,
2600 const VkBindBufferMemoryInfoKHR *pBindInfos)
2601 {
2602 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2603 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2604 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2605
2606 if (mem) {
2607 buffer->bo = mem->bo;
2608 buffer->offset = pBindInfos[i].memoryOffset;
2609 } else {
2610 buffer->bo = NULL;
2611 }
2612 }
2613 return VK_SUCCESS;
2614 }
2615
2616 VkResult radv_BindBufferMemory(
2617 VkDevice device,
2618 VkBuffer buffer,
2619 VkDeviceMemory memory,
2620 VkDeviceSize memoryOffset)
2621 {
2622 const VkBindBufferMemoryInfoKHR info = {
2623 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2624 .buffer = buffer,
2625 .memory = memory,
2626 .memoryOffset = memoryOffset
2627 };
2628
2629 return radv_BindBufferMemory2KHR(device, 1, &info);
2630 }
2631
2632 VkResult radv_BindImageMemory2KHR(VkDevice device,
2633 uint32_t bindInfoCount,
2634 const VkBindImageMemoryInfoKHR *pBindInfos)
2635 {
2636 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2637 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2638 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2639
2640 if (mem) {
2641 image->bo = mem->bo;
2642 image->offset = pBindInfos[i].memoryOffset;
2643 } else {
2644 image->bo = NULL;
2645 image->offset = 0;
2646 }
2647 }
2648 return VK_SUCCESS;
2649 }
2650
2651
2652 VkResult radv_BindImageMemory(
2653 VkDevice device,
2654 VkImage image,
2655 VkDeviceMemory memory,
2656 VkDeviceSize memoryOffset)
2657 {
2658 const VkBindImageMemoryInfoKHR info = {
2659 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2660 .image = image,
2661 .memory = memory,
2662 .memoryOffset = memoryOffset
2663 };
2664
2665 return radv_BindImageMemory2KHR(device, 1, &info);
2666 }
2667
2668
2669 static void
2670 radv_sparse_buffer_bind_memory(struct radv_device *device,
2671 const VkSparseBufferMemoryBindInfo *bind)
2672 {
2673 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2674
2675 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2676 struct radv_device_memory *mem = NULL;
2677
2678 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2679 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2680
2681 device->ws->buffer_virtual_bind(buffer->bo,
2682 bind->pBinds[i].resourceOffset,
2683 bind->pBinds[i].size,
2684 mem ? mem->bo : NULL,
2685 bind->pBinds[i].memoryOffset);
2686 }
2687 }
2688
2689 static void
2690 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2691 const VkSparseImageOpaqueMemoryBindInfo *bind)
2692 {
2693 RADV_FROM_HANDLE(radv_image, image, bind->image);
2694
2695 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2696 struct radv_device_memory *mem = NULL;
2697
2698 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2699 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2700
2701 device->ws->buffer_virtual_bind(image->bo,
2702 bind->pBinds[i].resourceOffset,
2703 bind->pBinds[i].size,
2704 mem ? mem->bo : NULL,
2705 bind->pBinds[i].memoryOffset);
2706 }
2707 }
2708
2709 VkResult radv_QueueBindSparse(
2710 VkQueue _queue,
2711 uint32_t bindInfoCount,
2712 const VkBindSparseInfo* pBindInfo,
2713 VkFence _fence)
2714 {
2715 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2716 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2717 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2718 bool fence_emitted = false;
2719
2720 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2721 struct radv_winsys_sem_info sem_info;
2722 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2723 radv_sparse_buffer_bind_memory(queue->device,
2724 pBindInfo[i].pBufferBinds + j);
2725 }
2726
2727 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2728 radv_sparse_image_opaque_bind_memory(queue->device,
2729 pBindInfo[i].pImageOpaqueBinds + j);
2730 }
2731
2732 VkResult result;
2733 result = radv_alloc_sem_info(&sem_info,
2734 pBindInfo[i].waitSemaphoreCount,
2735 pBindInfo[i].pWaitSemaphores,
2736 pBindInfo[i].signalSemaphoreCount,
2737 pBindInfo[i].pSignalSemaphores,
2738 _fence);
2739 if (result != VK_SUCCESS)
2740 return result;
2741
2742 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2743 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2744 &queue->device->empty_cs[queue->queue_family_index],
2745 1, NULL, NULL,
2746 &sem_info,
2747 false, base_fence);
2748 fence_emitted = true;
2749 if (fence)
2750 fence->submitted = true;
2751 }
2752
2753 radv_free_sem_info(&sem_info);
2754
2755 }
2756
2757 if (fence) {
2758 if (!fence_emitted) {
2759 radv_signal_fence(queue, fence);
2760 }
2761 fence->submitted = true;
2762 }
2763
2764 return VK_SUCCESS;
2765 }
2766
2767 VkResult radv_CreateFence(
2768 VkDevice _device,
2769 const VkFenceCreateInfo* pCreateInfo,
2770 const VkAllocationCallbacks* pAllocator,
2771 VkFence* pFence)
2772 {
2773 RADV_FROM_HANDLE(radv_device, device, _device);
2774 const VkExportFenceCreateInfoKHR *export =
2775 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2776 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2777 export ? export->handleTypes : 0;
2778
2779 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2780 sizeof(*fence), 8,
2781 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2782
2783 if (!fence)
2784 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2785
2786 fence->submitted = false;
2787 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2788 fence->temp_syncobj = 0;
2789 if (device->always_use_syncobj || handleTypes) {
2790 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2791 if (ret) {
2792 vk_free2(&device->alloc, pAllocator, fence);
2793 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2794 }
2795 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2796 device->ws->signal_syncobj(device->ws, fence->syncobj);
2797 }
2798 fence->fence = NULL;
2799 } else {
2800 fence->fence = device->ws->create_fence();
2801 if (!fence->fence) {
2802 vk_free2(&device->alloc, pAllocator, fence);
2803 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2804 }
2805 fence->syncobj = 0;
2806 }
2807
2808 *pFence = radv_fence_to_handle(fence);
2809
2810 return VK_SUCCESS;
2811 }
2812
2813 void radv_DestroyFence(
2814 VkDevice _device,
2815 VkFence _fence,
2816 const VkAllocationCallbacks* pAllocator)
2817 {
2818 RADV_FROM_HANDLE(radv_device, device, _device);
2819 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2820
2821 if (!fence)
2822 return;
2823
2824 if (fence->temp_syncobj)
2825 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2826 if (fence->syncobj)
2827 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2828 if (fence->fence)
2829 device->ws->destroy_fence(fence->fence);
2830 vk_free2(&device->alloc, pAllocator, fence);
2831 }
2832
2833 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2834 {
2835 uint64_t current_time;
2836 struct timespec tv;
2837
2838 clock_gettime(CLOCK_MONOTONIC, &tv);
2839 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2840
2841 timeout = MIN2(UINT64_MAX - current_time, timeout);
2842
2843 return current_time + timeout;
2844 }
2845
2846 VkResult radv_WaitForFences(
2847 VkDevice _device,
2848 uint32_t fenceCount,
2849 const VkFence* pFences,
2850 VkBool32 waitAll,
2851 uint64_t timeout)
2852 {
2853 RADV_FROM_HANDLE(radv_device, device, _device);
2854 timeout = radv_get_absolute_timeout(timeout);
2855
2856 if (!waitAll && fenceCount > 1) {
2857 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2858 }
2859
2860 for (uint32_t i = 0; i < fenceCount; ++i) {
2861 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2862 bool expired = false;
2863
2864 if (fence->temp_syncobj) {
2865 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2866 return VK_TIMEOUT;
2867 continue;
2868 }
2869
2870 if (fence->syncobj) {
2871 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2872 return VK_TIMEOUT;
2873 continue;
2874 }
2875
2876 if (fence->signalled)
2877 continue;
2878
2879 if (!fence->submitted)
2880 return VK_TIMEOUT;
2881
2882 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2883 if (!expired)
2884 return VK_TIMEOUT;
2885
2886 fence->signalled = true;
2887 }
2888
2889 return VK_SUCCESS;
2890 }
2891
2892 VkResult radv_ResetFences(VkDevice _device,
2893 uint32_t fenceCount,
2894 const VkFence *pFences)
2895 {
2896 RADV_FROM_HANDLE(radv_device, device, _device);
2897
2898 for (unsigned i = 0; i < fenceCount; ++i) {
2899 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2900 fence->submitted = fence->signalled = false;
2901
2902 /* Per spec, we first restore the permanent payload, and then reset, so
2903 * having a temp syncobj should not skip resetting the permanent syncobj. */
2904 if (fence->temp_syncobj) {
2905 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2906 fence->temp_syncobj = 0;
2907 }
2908
2909 if (fence->syncobj) {
2910 device->ws->reset_syncobj(device->ws, fence->syncobj);
2911 }
2912 }
2913
2914 return VK_SUCCESS;
2915 }
2916
2917 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2918 {
2919 RADV_FROM_HANDLE(radv_device, device, _device);
2920 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2921
2922 if (fence->temp_syncobj) {
2923 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2924 return success ? VK_SUCCESS : VK_NOT_READY;
2925 }
2926
2927 if (fence->syncobj) {
2928 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2929 return success ? VK_SUCCESS : VK_NOT_READY;
2930 }
2931
2932 if (fence->signalled)
2933 return VK_SUCCESS;
2934 if (!fence->submitted)
2935 return VK_NOT_READY;
2936 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2937 return VK_NOT_READY;
2938
2939 return VK_SUCCESS;
2940 }
2941
2942
2943 // Queue semaphore functions
2944
2945 VkResult radv_CreateSemaphore(
2946 VkDevice _device,
2947 const VkSemaphoreCreateInfo* pCreateInfo,
2948 const VkAllocationCallbacks* pAllocator,
2949 VkSemaphore* pSemaphore)
2950 {
2951 RADV_FROM_HANDLE(radv_device, device, _device);
2952 const VkExportSemaphoreCreateInfoKHR *export =
2953 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2954 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2955 export ? export->handleTypes : 0;
2956
2957 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2958 sizeof(*sem), 8,
2959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2960 if (!sem)
2961 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2962
2963 sem->temp_syncobj = 0;
2964 /* create a syncobject if we are going to export this semaphore */
2965 if (device->always_use_syncobj || handleTypes) {
2966 assert (device->physical_device->rad_info.has_syncobj);
2967 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2968 if (ret) {
2969 vk_free2(&device->alloc, pAllocator, sem);
2970 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2971 }
2972 sem->sem = NULL;
2973 } else {
2974 sem->sem = device->ws->create_sem(device->ws);
2975 if (!sem->sem) {
2976 vk_free2(&device->alloc, pAllocator, sem);
2977 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2978 }
2979 sem->syncobj = 0;
2980 }
2981
2982 *pSemaphore = radv_semaphore_to_handle(sem);
2983 return VK_SUCCESS;
2984 }
2985
2986 void radv_DestroySemaphore(
2987 VkDevice _device,
2988 VkSemaphore _semaphore,
2989 const VkAllocationCallbacks* pAllocator)
2990 {
2991 RADV_FROM_HANDLE(radv_device, device, _device);
2992 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2993 if (!_semaphore)
2994 return;
2995
2996 if (sem->syncobj)
2997 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2998 else
2999 device->ws->destroy_sem(sem->sem);
3000 vk_free2(&device->alloc, pAllocator, sem);
3001 }
3002
3003 VkResult radv_CreateEvent(
3004 VkDevice _device,
3005 const VkEventCreateInfo* pCreateInfo,
3006 const VkAllocationCallbacks* pAllocator,
3007 VkEvent* pEvent)
3008 {
3009 RADV_FROM_HANDLE(radv_device, device, _device);
3010 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3011 sizeof(*event), 8,
3012 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3013
3014 if (!event)
3015 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3016
3017 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3018 RADEON_DOMAIN_GTT,
3019 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3020 if (!event->bo) {
3021 vk_free2(&device->alloc, pAllocator, event);
3022 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3023 }
3024
3025 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3026
3027 *pEvent = radv_event_to_handle(event);
3028
3029 return VK_SUCCESS;
3030 }
3031
3032 void radv_DestroyEvent(
3033 VkDevice _device,
3034 VkEvent _event,
3035 const VkAllocationCallbacks* pAllocator)
3036 {
3037 RADV_FROM_HANDLE(radv_device, device, _device);
3038 RADV_FROM_HANDLE(radv_event, event, _event);
3039
3040 if (!event)
3041 return;
3042 device->ws->buffer_destroy(event->bo);
3043 vk_free2(&device->alloc, pAllocator, event);
3044 }
3045
3046 VkResult radv_GetEventStatus(
3047 VkDevice _device,
3048 VkEvent _event)
3049 {
3050 RADV_FROM_HANDLE(radv_event, event, _event);
3051
3052 if (*event->map == 1)
3053 return VK_EVENT_SET;
3054 return VK_EVENT_RESET;
3055 }
3056
3057 VkResult radv_SetEvent(
3058 VkDevice _device,
3059 VkEvent _event)
3060 {
3061 RADV_FROM_HANDLE(radv_event, event, _event);
3062 *event->map = 1;
3063
3064 return VK_SUCCESS;
3065 }
3066
3067 VkResult radv_ResetEvent(
3068 VkDevice _device,
3069 VkEvent _event)
3070 {
3071 RADV_FROM_HANDLE(radv_event, event, _event);
3072 *event->map = 0;
3073
3074 return VK_SUCCESS;
3075 }
3076
3077 VkResult radv_CreateBuffer(
3078 VkDevice _device,
3079 const VkBufferCreateInfo* pCreateInfo,
3080 const VkAllocationCallbacks* pAllocator,
3081 VkBuffer* pBuffer)
3082 {
3083 RADV_FROM_HANDLE(radv_device, device, _device);
3084 struct radv_buffer *buffer;
3085
3086 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3087
3088 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3089 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3090 if (buffer == NULL)
3091 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3092
3093 buffer->size = pCreateInfo->size;
3094 buffer->usage = pCreateInfo->usage;
3095 buffer->bo = NULL;
3096 buffer->offset = 0;
3097 buffer->flags = pCreateInfo->flags;
3098
3099 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3100 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3101
3102 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3103 buffer->bo = device->ws->buffer_create(device->ws,
3104 align64(buffer->size, 4096),
3105 4096, 0, RADEON_FLAG_VIRTUAL);
3106 if (!buffer->bo) {
3107 vk_free2(&device->alloc, pAllocator, buffer);
3108 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3109 }
3110 }
3111
3112 *pBuffer = radv_buffer_to_handle(buffer);
3113
3114 return VK_SUCCESS;
3115 }
3116
3117 void radv_DestroyBuffer(
3118 VkDevice _device,
3119 VkBuffer _buffer,
3120 const VkAllocationCallbacks* pAllocator)
3121 {
3122 RADV_FROM_HANDLE(radv_device, device, _device);
3123 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3124
3125 if (!buffer)
3126 return;
3127
3128 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3129 device->ws->buffer_destroy(buffer->bo);
3130
3131 vk_free2(&device->alloc, pAllocator, buffer);
3132 }
3133
3134 static inline unsigned
3135 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3136 {
3137 if (stencil)
3138 return image->surface.u.legacy.stencil_tiling_index[level];
3139 else
3140 return image->surface.u.legacy.tiling_index[level];
3141 }
3142
3143 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3144 {
3145 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3146 }
3147
3148 static void
3149 radv_initialise_color_surface(struct radv_device *device,
3150 struct radv_color_buffer_info *cb,
3151 struct radv_image_view *iview)
3152 {
3153 const struct vk_format_description *desc;
3154 unsigned ntype, format, swap, endian;
3155 unsigned blend_clamp = 0, blend_bypass = 0;
3156 uint64_t va;
3157 const struct radeon_surf *surf = &iview->image->surface;
3158
3159 desc = vk_format_description(iview->vk_format);
3160
3161 memset(cb, 0, sizeof(*cb));
3162
3163 /* Intensity is implemented as Red, so treat it that way. */
3164 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3165
3166 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3167
3168 cb->cb_color_base = va >> 8;
3169
3170 if (device->physical_device->rad_info.chip_class >= GFX9) {
3171 struct gfx9_surf_meta_flags meta;
3172 if (iview->image->dcc_offset)
3173 meta = iview->image->surface.u.gfx9.dcc;
3174 else
3175 meta = iview->image->surface.u.gfx9.cmask;
3176
3177 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3178 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3179 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3180 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3181
3182 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3183 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3184 } else {
3185 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3186 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3187
3188 cb->cb_color_base += level_info->offset >> 8;
3189 if (level_info->mode == RADEON_SURF_MODE_2D)
3190 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3191
3192 pitch_tile_max = level_info->nblk_x / 8 - 1;
3193 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3194 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3195
3196 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3197 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3198 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3199
3200 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3201
3202 if (iview->image->fmask.size) {
3203 if (device->physical_device->rad_info.chip_class >= CIK)
3204 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3205 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3206 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3207 } else {
3208 /* This must be set for fast clear to work without FMASK. */
3209 if (device->physical_device->rad_info.chip_class >= CIK)
3210 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3211 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3212 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3213 }
3214 }
3215
3216 /* CMASK variables */
3217 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3218 va += iview->image->cmask.offset;
3219 cb->cb_color_cmask = va >> 8;
3220
3221 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3222 va += iview->image->dcc_offset;
3223 cb->cb_dcc_base = va >> 8;
3224 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3225
3226 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3227 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3228 S_028C6C_SLICE_MAX(max_slice);
3229
3230 if (iview->image->info.samples > 1) {
3231 unsigned log_samples = util_logbase2(iview->image->info.samples);
3232
3233 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3234 S_028C74_NUM_FRAGMENTS(log_samples);
3235 }
3236
3237 if (iview->image->fmask.size) {
3238 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3239 cb->cb_color_fmask = va >> 8;
3240 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3241 } else {
3242 cb->cb_color_fmask = cb->cb_color_base;
3243 }
3244
3245 ntype = radv_translate_color_numformat(iview->vk_format,
3246 desc,
3247 vk_format_get_first_non_void_channel(iview->vk_format));
3248 format = radv_translate_colorformat(iview->vk_format);
3249 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3250 radv_finishme("Illegal color\n");
3251 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3252 endian = radv_colorformat_endian_swap(format);
3253
3254 /* blend clamp should be set for all NORM/SRGB types */
3255 if (ntype == V_028C70_NUMBER_UNORM ||
3256 ntype == V_028C70_NUMBER_SNORM ||
3257 ntype == V_028C70_NUMBER_SRGB)
3258 blend_clamp = 1;
3259
3260 /* set blend bypass according to docs if SINT/UINT or
3261 8/24 COLOR variants */
3262 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3263 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3264 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3265 blend_clamp = 0;
3266 blend_bypass = 1;
3267 }
3268 #if 0
3269 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3270 (format == V_028C70_COLOR_8 ||
3271 format == V_028C70_COLOR_8_8 ||
3272 format == V_028C70_COLOR_8_8_8_8))
3273 ->color_is_int8 = true;
3274 #endif
3275 cb->cb_color_info = S_028C70_FORMAT(format) |
3276 S_028C70_COMP_SWAP(swap) |
3277 S_028C70_BLEND_CLAMP(blend_clamp) |
3278 S_028C70_BLEND_BYPASS(blend_bypass) |
3279 S_028C70_SIMPLE_FLOAT(1) |
3280 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3281 ntype != V_028C70_NUMBER_SNORM &&
3282 ntype != V_028C70_NUMBER_SRGB &&
3283 format != V_028C70_COLOR_8_24 &&
3284 format != V_028C70_COLOR_24_8) |
3285 S_028C70_NUMBER_TYPE(ntype) |
3286 S_028C70_ENDIAN(endian);
3287 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3288 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3289 if (device->physical_device->rad_info.chip_class == SI) {
3290 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3291 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3292 }
3293 }
3294
3295 if (iview->image->cmask.size &&
3296 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3297 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3298
3299 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3300 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3301
3302 if (device->physical_device->rad_info.chip_class >= VI) {
3303 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3304 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3305 unsigned independent_64b_blocks = 0;
3306 unsigned max_compressed_block_size;
3307
3308 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3309 64 for APU because all of our APUs to date use DIMMs which have
3310 a request granularity size of 64B while all other chips have a
3311 32B request size */
3312 if (!device->physical_device->rad_info.has_dedicated_vram)
3313 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3314
3315 if (iview->image->info.samples > 1) {
3316 if (iview->image->surface.bpe == 1)
3317 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3318 else if (iview->image->surface.bpe == 2)
3319 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3320 }
3321
3322 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3323 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3324 independent_64b_blocks = 1;
3325 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3326 } else
3327 max_compressed_block_size = max_uncompressed_block_size;
3328
3329 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3330 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3331 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3332 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3333 }
3334
3335 /* This must be set for fast clear to work without FMASK. */
3336 if (!iview->image->fmask.size &&
3337 device->physical_device->rad_info.chip_class == SI) {
3338 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3339 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3340 }
3341
3342 if (device->physical_device->rad_info.chip_class >= GFX9) {
3343 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3344 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3345
3346 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3347 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3348 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3349 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3350 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3351 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3352 }
3353 }
3354
3355 static void
3356 radv_initialise_ds_surface(struct radv_device *device,
3357 struct radv_ds_buffer_info *ds,
3358 struct radv_image_view *iview)
3359 {
3360 unsigned level = iview->base_mip;
3361 unsigned format, stencil_format;
3362 uint64_t va, s_offs, z_offs;
3363 bool stencil_only = false;
3364 memset(ds, 0, sizeof(*ds));
3365 switch (iview->image->vk_format) {
3366 case VK_FORMAT_D24_UNORM_S8_UINT:
3367 case VK_FORMAT_X8_D24_UNORM_PACK32:
3368 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3369 ds->offset_scale = 2.0f;
3370 break;
3371 case VK_FORMAT_D16_UNORM:
3372 case VK_FORMAT_D16_UNORM_S8_UINT:
3373 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3374 ds->offset_scale = 4.0f;
3375 break;
3376 case VK_FORMAT_D32_SFLOAT:
3377 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3378 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3379 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3380 ds->offset_scale = 1.0f;
3381 break;
3382 case VK_FORMAT_S8_UINT:
3383 stencil_only = true;
3384 break;
3385 default:
3386 break;
3387 }
3388
3389 format = radv_translate_dbformat(iview->image->vk_format);
3390 stencil_format = iview->image->surface.has_stencil ?
3391 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3392
3393 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3394 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3395 S_028008_SLICE_MAX(max_slice);
3396
3397 ds->db_htile_data_base = 0;
3398 ds->db_htile_surface = 0;
3399
3400 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3401 s_offs = z_offs = va;
3402
3403 if (device->physical_device->rad_info.chip_class >= GFX9) {
3404 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3405 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3406
3407 ds->db_z_info = S_028038_FORMAT(format) |
3408 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3409 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3410 S_028038_MAXMIP(iview->image->info.levels - 1);
3411 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3412 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3413
3414 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3415 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3416 ds->db_depth_view |= S_028008_MIPID(level);
3417
3418 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3419 S_02801C_Y_MAX(iview->image->info.height - 1);
3420
3421 if (radv_htile_enabled(iview->image, level)) {
3422 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3423
3424 if (iview->image->tc_compatible_htile) {
3425 unsigned max_zplanes = 4;
3426
3427 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3428 iview->image->info.samples > 1)
3429 max_zplanes = 2;
3430
3431 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3432 S_028038_ITERATE_FLUSH(1);
3433 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3434 }
3435
3436 if (!iview->image->surface.has_stencil)
3437 /* Use all of the htile_buffer for depth if there's no stencil. */
3438 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3439 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3440 iview->image->htile_offset;
3441 ds->db_htile_data_base = va >> 8;
3442 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3443 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3444 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3445 }
3446 } else {
3447 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3448
3449 if (stencil_only)
3450 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3451
3452 z_offs += iview->image->surface.u.legacy.level[level].offset;
3453 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3454
3455 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3456 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3457 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3458
3459 if (iview->image->info.samples > 1)
3460 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3461
3462 if (device->physical_device->rad_info.chip_class >= CIK) {
3463 struct radeon_info *info = &device->physical_device->rad_info;
3464 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3465 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3466 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3467 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3468 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3469 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3470
3471 if (stencil_only)
3472 tile_mode = stencil_tile_mode;
3473
3474 ds->db_depth_info |=
3475 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3476 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3477 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3478 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3479 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3480 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3481 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3482 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3483 } else {
3484 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3485 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3486 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3487 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3488 if (stencil_only)
3489 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3490 }
3491
3492 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3493 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3494 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3495
3496 if (radv_htile_enabled(iview->image, level)) {
3497 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3498
3499 if (!iview->image->surface.has_stencil &&
3500 !iview->image->tc_compatible_htile)
3501 /* Use all of the htile_buffer for depth if there's no stencil. */
3502 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3503
3504 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3505 iview->image->htile_offset;
3506 ds->db_htile_data_base = va >> 8;
3507 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3508
3509 if (iview->image->tc_compatible_htile) {
3510 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3511
3512 if (iview->image->info.samples <= 1)
3513 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3514 else if (iview->image->info.samples <= 4)
3515 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3516 else
3517 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3518 }
3519 }
3520 }
3521
3522 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3523 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3524 }
3525
3526 VkResult radv_CreateFramebuffer(
3527 VkDevice _device,
3528 const VkFramebufferCreateInfo* pCreateInfo,
3529 const VkAllocationCallbacks* pAllocator,
3530 VkFramebuffer* pFramebuffer)
3531 {
3532 RADV_FROM_HANDLE(radv_device, device, _device);
3533 struct radv_framebuffer *framebuffer;
3534
3535 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3536
3537 size_t size = sizeof(*framebuffer) +
3538 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3539 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3540 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3541 if (framebuffer == NULL)
3542 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3543
3544 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3545 framebuffer->width = pCreateInfo->width;
3546 framebuffer->height = pCreateInfo->height;
3547 framebuffer->layers = pCreateInfo->layers;
3548 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3549 VkImageView _iview = pCreateInfo->pAttachments[i];
3550 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3551 framebuffer->attachments[i].attachment = iview;
3552 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3553 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3554 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3555 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3556 }
3557 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3558 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3559 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3560 }
3561
3562 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3563 return VK_SUCCESS;
3564 }
3565
3566 void radv_DestroyFramebuffer(
3567 VkDevice _device,
3568 VkFramebuffer _fb,
3569 const VkAllocationCallbacks* pAllocator)
3570 {
3571 RADV_FROM_HANDLE(radv_device, device, _device);
3572 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3573
3574 if (!fb)
3575 return;
3576 vk_free2(&device->alloc, pAllocator, fb);
3577 }
3578
3579 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3580 {
3581 switch (address_mode) {
3582 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3583 return V_008F30_SQ_TEX_WRAP;
3584 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3585 return V_008F30_SQ_TEX_MIRROR;
3586 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3587 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3588 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3589 return V_008F30_SQ_TEX_CLAMP_BORDER;
3590 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3591 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3592 default:
3593 unreachable("illegal tex wrap mode");
3594 break;
3595 }
3596 }
3597
3598 static unsigned
3599 radv_tex_compare(VkCompareOp op)
3600 {
3601 switch (op) {
3602 case VK_COMPARE_OP_NEVER:
3603 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3604 case VK_COMPARE_OP_LESS:
3605 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3606 case VK_COMPARE_OP_EQUAL:
3607 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3608 case VK_COMPARE_OP_LESS_OR_EQUAL:
3609 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3610 case VK_COMPARE_OP_GREATER:
3611 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3612 case VK_COMPARE_OP_NOT_EQUAL:
3613 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3614 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3615 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3616 case VK_COMPARE_OP_ALWAYS:
3617 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3618 default:
3619 unreachable("illegal compare mode");
3620 break;
3621 }
3622 }
3623
3624 static unsigned
3625 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3626 {
3627 switch (filter) {
3628 case VK_FILTER_NEAREST:
3629 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3630 V_008F38_SQ_TEX_XY_FILTER_POINT);
3631 case VK_FILTER_LINEAR:
3632 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3633 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3634 case VK_FILTER_CUBIC_IMG:
3635 default:
3636 fprintf(stderr, "illegal texture filter");
3637 return 0;
3638 }
3639 }
3640
3641 static unsigned
3642 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3643 {
3644 switch (mode) {
3645 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3646 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3647 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3648 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3649 default:
3650 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3651 }
3652 }
3653
3654 static unsigned
3655 radv_tex_bordercolor(VkBorderColor bcolor)
3656 {
3657 switch (bcolor) {
3658 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3659 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3660 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3661 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3662 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3663 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3664 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3665 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3666 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3667 default:
3668 break;
3669 }
3670 return 0;
3671 }
3672
3673 static unsigned
3674 radv_tex_aniso_filter(unsigned filter)
3675 {
3676 if (filter < 2)
3677 return 0;
3678 if (filter < 4)
3679 return 1;
3680 if (filter < 8)
3681 return 2;
3682 if (filter < 16)
3683 return 3;
3684 return 4;
3685 }
3686
3687 static void
3688 radv_init_sampler(struct radv_device *device,
3689 struct radv_sampler *sampler,
3690 const VkSamplerCreateInfo *pCreateInfo)
3691 {
3692 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3693 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3694 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3695 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3696
3697 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3698 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3699 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3700 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3701 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3702 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3703 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3704 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3705 S_008F30_DISABLE_CUBE_WRAP(0) |
3706 S_008F30_COMPAT_MODE(is_vi));
3707 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3708 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3709 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3710 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3711 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3712 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3713 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3714 S_008F38_MIP_POINT_PRECLAMP(0) |
3715 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3716 S_008F38_FILTER_PREC_FIX(1) |
3717 S_008F38_ANISO_OVERRIDE(is_vi));
3718 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3719 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3720 }
3721
3722 VkResult radv_CreateSampler(
3723 VkDevice _device,
3724 const VkSamplerCreateInfo* pCreateInfo,
3725 const VkAllocationCallbacks* pAllocator,
3726 VkSampler* pSampler)
3727 {
3728 RADV_FROM_HANDLE(radv_device, device, _device);
3729 struct radv_sampler *sampler;
3730
3731 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3732
3733 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3734 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3735 if (!sampler)
3736 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3737
3738 radv_init_sampler(device, sampler, pCreateInfo);
3739 *pSampler = radv_sampler_to_handle(sampler);
3740
3741 return VK_SUCCESS;
3742 }
3743
3744 void radv_DestroySampler(
3745 VkDevice _device,
3746 VkSampler _sampler,
3747 const VkAllocationCallbacks* pAllocator)
3748 {
3749 RADV_FROM_HANDLE(radv_device, device, _device);
3750 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3751
3752 if (!sampler)
3753 return;
3754 vk_free2(&device->alloc, pAllocator, sampler);
3755 }
3756
3757 /* vk_icd.h does not declare this function, so we declare it here to
3758 * suppress Wmissing-prototypes.
3759 */
3760 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3761 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3762
3763 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3764 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3765 {
3766 /* For the full details on loader interface versioning, see
3767 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3768 * What follows is a condensed summary, to help you navigate the large and
3769 * confusing official doc.
3770 *
3771 * - Loader interface v0 is incompatible with later versions. We don't
3772 * support it.
3773 *
3774 * - In loader interface v1:
3775 * - The first ICD entrypoint called by the loader is
3776 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3777 * entrypoint.
3778 * - The ICD must statically expose no other Vulkan symbol unless it is
3779 * linked with -Bsymbolic.
3780 * - Each dispatchable Vulkan handle created by the ICD must be
3781 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3782 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3783 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3784 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3785 * such loader-managed surfaces.
3786 *
3787 * - Loader interface v2 differs from v1 in:
3788 * - The first ICD entrypoint called by the loader is
3789 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3790 * statically expose this entrypoint.
3791 *
3792 * - Loader interface v3 differs from v2 in:
3793 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3794 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3795 * because the loader no longer does so.
3796 */
3797 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3798 return VK_SUCCESS;
3799 }
3800
3801 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3802 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3803 int *pFD)
3804 {
3805 RADV_FROM_HANDLE(radv_device, device, _device);
3806 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3807
3808 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3809
3810 /* At the moment, we support only the below handle types. */
3811 assert(pGetFdInfo->handleType ==
3812 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3813 pGetFdInfo->handleType ==
3814 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3815
3816 bool ret = radv_get_memory_fd(device, memory, pFD);
3817 if (ret == false)
3818 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3819 return VK_SUCCESS;
3820 }
3821
3822 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3823 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3824 int fd,
3825 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3826 {
3827 switch (handleType) {
3828 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3829 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3830 return VK_SUCCESS;
3831
3832 default:
3833 /* The valid usage section for this function says:
3834 *
3835 * "handleType must not be one of the handle types defined as
3836 * opaque."
3837 *
3838 * So opaque handle types fall into the default "unsupported" case.
3839 */
3840 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3841 }
3842 }
3843
3844 static VkResult radv_import_opaque_fd(struct radv_device *device,
3845 int fd,
3846 uint32_t *syncobj)
3847 {
3848 uint32_t syncobj_handle = 0;
3849 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3850 if (ret != 0)
3851 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3852
3853 if (*syncobj)
3854 device->ws->destroy_syncobj(device->ws, *syncobj);
3855
3856 *syncobj = syncobj_handle;
3857 close(fd);
3858
3859 return VK_SUCCESS;
3860 }
3861
3862 static VkResult radv_import_sync_fd(struct radv_device *device,
3863 int fd,
3864 uint32_t *syncobj)
3865 {
3866 /* If we create a syncobj we do it locally so that if we have an error, we don't
3867 * leave a syncobj in an undetermined state in the fence. */
3868 uint32_t syncobj_handle = *syncobj;
3869 if (!syncobj_handle) {
3870 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3871 if (ret) {
3872 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3873 }
3874 }
3875
3876 if (fd == -1) {
3877 device->ws->signal_syncobj(device->ws, syncobj_handle);
3878 } else {
3879 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3880 if (ret != 0)
3881 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3882 }
3883
3884 *syncobj = syncobj_handle;
3885 if (fd != -1)
3886 close(fd);
3887
3888 return VK_SUCCESS;
3889 }
3890
3891 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3892 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3893 {
3894 RADV_FROM_HANDLE(radv_device, device, _device);
3895 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3896 uint32_t *syncobj_dst = NULL;
3897
3898 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3899 syncobj_dst = &sem->temp_syncobj;
3900 } else {
3901 syncobj_dst = &sem->syncobj;
3902 }
3903
3904 switch(pImportSemaphoreFdInfo->handleType) {
3905 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3906 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3907 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3908 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3909 default:
3910 unreachable("Unhandled semaphore handle type");
3911 }
3912 }
3913
3914 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3915 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3916 int *pFd)
3917 {
3918 RADV_FROM_HANDLE(radv_device, device, _device);
3919 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3920 int ret;
3921 uint32_t syncobj_handle;
3922
3923 if (sem->temp_syncobj)
3924 syncobj_handle = sem->temp_syncobj;
3925 else
3926 syncobj_handle = sem->syncobj;
3927
3928 switch(pGetFdInfo->handleType) {
3929 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3930 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3931 break;
3932 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3933 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3934 if (!ret) {
3935 if (sem->temp_syncobj) {
3936 close (sem->temp_syncobj);
3937 sem->temp_syncobj = 0;
3938 } else {
3939 device->ws->reset_syncobj(device->ws, syncobj_handle);
3940 }
3941 }
3942 break;
3943 default:
3944 unreachable("Unhandled semaphore handle type");
3945 }
3946
3947 if (ret)
3948 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3949 return VK_SUCCESS;
3950 }
3951
3952 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3953 VkPhysicalDevice physicalDevice,
3954 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3955 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3956 {
3957 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3958
3959 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
3960 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3961 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3962 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3963 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3964 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3965 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3966 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3967 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3968 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3969 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3970 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3971 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3972 } else {
3973 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3974 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3975 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3976 }
3977 }
3978
3979 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3980 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3981 {
3982 RADV_FROM_HANDLE(radv_device, device, _device);
3983 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3984 uint32_t *syncobj_dst = NULL;
3985
3986
3987 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3988 syncobj_dst = &fence->temp_syncobj;
3989 } else {
3990 syncobj_dst = &fence->syncobj;
3991 }
3992
3993 switch(pImportFenceFdInfo->handleType) {
3994 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3995 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3996 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3997 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3998 default:
3999 unreachable("Unhandled fence handle type");
4000 }
4001 }
4002
4003 VkResult radv_GetFenceFdKHR(VkDevice _device,
4004 const VkFenceGetFdInfoKHR *pGetFdInfo,
4005 int *pFd)
4006 {
4007 RADV_FROM_HANDLE(radv_device, device, _device);
4008 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4009 int ret;
4010 uint32_t syncobj_handle;
4011
4012 if (fence->temp_syncobj)
4013 syncobj_handle = fence->temp_syncobj;
4014 else
4015 syncobj_handle = fence->syncobj;
4016
4017 switch(pGetFdInfo->handleType) {
4018 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4019 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4020 break;
4021 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4022 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4023 if (!ret) {
4024 if (fence->temp_syncobj) {
4025 close (fence->temp_syncobj);
4026 fence->temp_syncobj = 0;
4027 } else {
4028 device->ws->reset_syncobj(device->ws, syncobj_handle);
4029 }
4030 }
4031 break;
4032 default:
4033 unreachable("Unhandled fence handle type");
4034 }
4035
4036 if (ret)
4037 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4038 return VK_SUCCESS;
4039 }
4040
4041 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
4042 VkPhysicalDevice physicalDevice,
4043 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4044 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4045 {
4046 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4047
4048 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4049 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4050 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4051 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4052 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4053 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4054 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4055 } else {
4056 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4057 pExternalFenceProperties->compatibleHandleTypes = 0;
4058 pExternalFenceProperties->externalFenceFeatures = 0;
4059 }
4060 }
4061
4062 VkResult
4063 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4064 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4065 const VkAllocationCallbacks* pAllocator,
4066 VkDebugReportCallbackEXT* pCallback)
4067 {
4068 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4069 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4070 pCreateInfo, pAllocator, &instance->alloc,
4071 pCallback);
4072 }
4073
4074 void
4075 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4076 VkDebugReportCallbackEXT _callback,
4077 const VkAllocationCallbacks* pAllocator)
4078 {
4079 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4080 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4081 _callback, pAllocator, &instance->alloc);
4082 }
4083
4084 void
4085 radv_DebugReportMessageEXT(VkInstance _instance,
4086 VkDebugReportFlagsEXT flags,
4087 VkDebugReportObjectTypeEXT objectType,
4088 uint64_t object,
4089 size_t location,
4090 int32_t messageCode,
4091 const char* pLayerPrefix,
4092 const char* pMessage)
4093 {
4094 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4095 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4096 object, location, messageCode, pLayerPrefix, pMessage);
4097 }