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[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
48 #include "radv_cs.h"
49 #include "util/disk_cache.h"
50 #include "vk_util.h"
51 #include <xf86drm.h>
52 #include <amdgpu.h>
53 #include <amdgpu_drm.h>
54 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
55 #include "winsys/null/radv_null_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static bool
133 radv_is_mem_type_vram(enum radv_mem_type type)
134 {
135 return type == RADV_MEM_TYPE_VRAM ||
136 type == RADV_MEM_TYPE_VRAM_UNCACHED;
137 }
138
139 static bool
140 radv_is_mem_type_vram_visible(enum radv_mem_type type)
141 {
142 return type == RADV_MEM_TYPE_VRAM_CPU_ACCESS ||
143 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
144 }
145 static bool
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type)
147 {
148 return type == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
149 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
150 }
151
152 static bool
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type)
154 {
155 return type == RADV_MEM_TYPE_GTT_CACHED ||
156 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
157 }
158
159 static bool
160 radv_is_mem_type_uncached(enum radv_mem_type type)
161 {
162 return type == RADV_MEM_TYPE_VRAM_UNCACHED ||
163 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED ||
164 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED ||
165 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
166 }
167
168 static void
169 radv_physical_device_init_mem_types(struct radv_physical_device *device)
170 {
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
172 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
173 uint64_t vram_size = radv_get_vram_size(device);
174 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
175 device->memory_properties.memoryHeapCount = 0;
176 if (vram_size > 0) {
177 vram_index = device->memory_properties.memoryHeapCount++;
178 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
179 .size = vram_size,
180 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
181 };
182 }
183 if (visible_vram_size) {
184 visible_vram_index = device->memory_properties.memoryHeapCount++;
185 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
186 .size = visible_vram_size,
187 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
188 };
189 }
190 if (device->rad_info.gart_size > 0) {
191 gart_index = device->memory_properties.memoryHeapCount++;
192 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
193 .size = device->rad_info.gart_size,
194 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
195 };
196 }
197
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
199 unsigned type_count = 0;
200 if (vram_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
204 .heapIndex = vram_index,
205 };
206 }
207 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
212 .heapIndex = gart_index,
213 };
214 }
215 if (visible_vram_index >= 0) {
216 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
221 .heapIndex = visible_vram_index,
222 };
223 }
224 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
230 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
231 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
234 .heapIndex = gart_index,
235 };
236 }
237 if (gart_index >= 0) {
238 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
239 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
240 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
243 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
244 .heapIndex = gart_index,
245 };
246 }
247 device->memory_properties.memoryTypeCount = type_count;
248
249 if (device->rad_info.has_l2_uncached) {
250 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
251 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
252
253 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
255 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
256 enum radv_mem_type mem_type_id;
257
258 switch (device->mem_type_indices[i]) {
259 case RADV_MEM_TYPE_VRAM:
260 mem_type_id = RADV_MEM_TYPE_VRAM_UNCACHED;
261 break;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
263 mem_type_id = RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
264 break;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
266 mem_type_id = RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
267 break;
268 case RADV_MEM_TYPE_GTT_CACHED:
269 mem_type_id = RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
270 break;
271 default:
272 unreachable("invalid memory type");
273 }
274
275 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
278
279 device->mem_type_indices[type_count] = mem_type_id;
280 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
281 .propertyFlags = property_flags,
282 .heapIndex = mem_type.heapIndex,
283 };
284 }
285 }
286 device->memory_properties.memoryTypeCount = type_count;
287 }
288 }
289
290 static VkResult
291 radv_physical_device_init(struct radv_physical_device *device,
292 struct radv_instance *instance,
293 drmDevicePtr drm_device)
294 {
295 VkResult result;
296 int fd = -1;
297 int master_fd = -1;
298
299 if (drm_device) {
300 const char *path = drm_device->nodes[DRM_NODE_RENDER];
301 drmVersionPtr version;
302
303 fd = open(path, O_RDWR | O_CLOEXEC);
304 if (fd < 0) {
305 if (instance->debug_flags & RADV_DEBUG_STARTUP)
306 radv_logi("Could not open device '%s'", path);
307
308 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
309 }
310
311 version = drmGetVersion(fd);
312 if (!version) {
313 close(fd);
314
315 if (instance->debug_flags & RADV_DEBUG_STARTUP)
316 radv_logi("Could not get the kernel driver version for device '%s'", path);
317
318 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
319 "failed to get version %s: %m", path);
320 }
321
322 if (strcmp(version->name, "amdgpu")) {
323 drmFreeVersion(version);
324 close(fd);
325
326 if (instance->debug_flags & RADV_DEBUG_STARTUP)
327 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
328
329 return VK_ERROR_INCOMPATIBLE_DRIVER;
330 }
331 drmFreeVersion(version);
332
333 if (instance->debug_flags & RADV_DEBUG_STARTUP)
334 radv_logi("Found compatible device '%s'.", path);
335 }
336
337 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
338 device->instance = instance;
339
340 if (drm_device) {
341 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
342 instance->perftest_flags);
343 } else {
344 device->ws = radv_null_winsys_create();
345 }
346
347 if (!device->ws) {
348 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
349 goto fail;
350 }
351
352 if (drm_device && instance->enabled_extensions.KHR_display) {
353 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
354 if (master_fd >= 0) {
355 uint32_t accel_working = 0;
356 struct drm_amdgpu_info request = {
357 .return_pointer = (uintptr_t)&accel_working,
358 .return_size = sizeof(accel_working),
359 .query = AMDGPU_INFO_ACCEL_WORKING
360 };
361
362 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
363 close(master_fd);
364 master_fd = -1;
365 }
366 }
367 }
368
369 device->master_fd = master_fd;
370 device->local_fd = fd;
371 device->ws->query_info(device->ws, &device->rad_info);
372
373 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
374
375 snprintf(device->name, sizeof(device->name),
376 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
377 device->rad_info.name);
378
379 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
380 device->ws->destroy(device->ws);
381 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
382 "cannot generate UUID");
383 goto fail;
384 }
385
386 /* These flags affect shader compilation. */
387 uint64_t shader_env_flags = (device->use_aco ? 0x2 : 0);
388
389 /* The gpu id is already embedded in the uuid so we just pass "radv"
390 * when creating the cache.
391 */
392 char buf[VK_UUID_SIZE * 2 + 1];
393 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
394 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
395
396 if (device->rad_info.chip_class < GFX8)
397 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
398
399 radv_get_driver_uuid(&device->driver_uuid);
400 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
401
402 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
403 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
404
405 device->dcc_msaa_allowed =
406 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
407
408 device->use_shader_ballot = (device->use_aco && device->rad_info.chip_class >= GFX8) ||
409 (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
410
411 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
412 device->rad_info.family != CHIP_NAVI14 &&
413 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
414
415 /* TODO: Implement NGG GS with ACO. */
416 device->use_ngg_gs = device->use_ngg && !device->use_aco;
417 device->use_ngg_streamout = false;
418
419 /* Determine the number of threads per wave for all stages. */
420 device->cs_wave_size = 64;
421 device->ps_wave_size = 64;
422 device->ge_wave_size = 64;
423
424 if (device->rad_info.chip_class >= GFX10) {
425 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
426 device->cs_wave_size = 32;
427
428 /* For pixel shaders, wave64 is recommanded. */
429 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
430 device->ps_wave_size = 32;
431
432 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
433 device->ge_wave_size = 32;
434 }
435
436 radv_physical_device_init_mem_types(device);
437 radv_fill_device_extension_table(device, &device->supported_extensions);
438
439 if (drm_device)
440 device->bus_info = *drm_device->businfo.pci;
441
442 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
443 ac_print_gpu_info(&device->rad_info);
444
445 /* The WSI is structured as a layer on top of the driver, so this has
446 * to be the last part of initialization (at least until we get other
447 * semi-layers).
448 */
449 result = radv_init_wsi(device);
450 if (result != VK_SUCCESS) {
451 device->ws->destroy(device->ws);
452 vk_error(instance, result);
453 goto fail;
454 }
455
456 return VK_SUCCESS;
457
458 fail:
459 close(fd);
460 if (master_fd != -1)
461 close(master_fd);
462 return result;
463 }
464
465 static void
466 radv_physical_device_finish(struct radv_physical_device *device)
467 {
468 radv_finish_wsi(device);
469 device->ws->destroy(device->ws);
470 disk_cache_destroy(device->disk_cache);
471 close(device->local_fd);
472 if (device->master_fd != -1)
473 close(device->master_fd);
474 }
475
476 static void *
477 default_alloc_func(void *pUserData, size_t size, size_t align,
478 VkSystemAllocationScope allocationScope)
479 {
480 return malloc(size);
481 }
482
483 static void *
484 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
485 size_t align, VkSystemAllocationScope allocationScope)
486 {
487 return realloc(pOriginal, size);
488 }
489
490 static void
491 default_free_func(void *pUserData, void *pMemory)
492 {
493 free(pMemory);
494 }
495
496 static const VkAllocationCallbacks default_alloc = {
497 .pUserData = NULL,
498 .pfnAllocation = default_alloc_func,
499 .pfnReallocation = default_realloc_func,
500 .pfnFree = default_free_func,
501 };
502
503 static const struct debug_control radv_debug_options[] = {
504 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
505 {"nodcc", RADV_DEBUG_NO_DCC},
506 {"shaders", RADV_DEBUG_DUMP_SHADERS},
507 {"nocache", RADV_DEBUG_NO_CACHE},
508 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
509 {"nohiz", RADV_DEBUG_NO_HIZ},
510 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
511 {"allbos", RADV_DEBUG_ALL_BOS},
512 {"noibs", RADV_DEBUG_NO_IBS},
513 {"spirv", RADV_DEBUG_DUMP_SPIRV},
514 {"vmfaults", RADV_DEBUG_VM_FAULTS},
515 {"zerovram", RADV_DEBUG_ZERO_VRAM},
516 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
517 {"preoptir", RADV_DEBUG_PREOPTIR},
518 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
519 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
520 {"info", RADV_DEBUG_INFO},
521 {"errors", RADV_DEBUG_ERRORS},
522 {"startup", RADV_DEBUG_STARTUP},
523 {"checkir", RADV_DEBUG_CHECKIR},
524 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
525 {"nobinning", RADV_DEBUG_NOBINNING},
526 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
527 {"nongg", RADV_DEBUG_NO_NGG},
528 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
529 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
530 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
531 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
532 {NULL, 0}
533 };
534
535 const char *
536 radv_get_debug_option_name(int id)
537 {
538 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
539 return radv_debug_options[id].string;
540 }
541
542 static const struct debug_control radv_perftest_options[] = {
543 {"localbos", RADV_PERFTEST_LOCAL_BOS},
544 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
545 {"bolist", RADV_PERFTEST_BO_LIST},
546 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
547 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
548 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
549 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
550 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
551 {"dfsm", RADV_PERFTEST_DFSM},
552 {"aco", RADV_PERFTEST_ACO},
553 {NULL, 0}
554 };
555
556 const char *
557 radv_get_perftest_option_name(int id)
558 {
559 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
560 return radv_perftest_options[id].string;
561 }
562
563 static void
564 radv_handle_per_app_options(struct radv_instance *instance,
565 const VkApplicationInfo *info)
566 {
567 const char *name = info ? info->pApplicationName : NULL;
568
569 if (!name)
570 return;
571
572 if (!strcmp(name, "DOOM_VFR")) {
573 /* Work around a Doom VFR game bug */
574 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
575 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
576 /* Workaround for a WaW hazard when LLVM moves/merges
577 * load/store memory operations.
578 * See https://reviews.llvm.org/D61313
579 */
580 if (LLVM_VERSION_MAJOR < 9)
581 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
582 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
583 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT) &&
584 !(instance->perftest_flags & RADV_PERFTEST_ACO)) {
585 /* Force enable VK_AMD_shader_ballot because it looks
586 * safe and it gives a nice boost (+20% on Vega 56 at
587 * this time). It also prevents corruption on LLVM.
588 */
589 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
590 }
591 } else if (!strcmp(name, "Fledge")) {
592 /*
593 * Zero VRAM for "The Surge 2"
594 *
595 * This avoid a hang when when rendering any level. Likely
596 * uninitialized data in an indirect draw.
597 */
598 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
599 } else if (!strcmp(name, "No Man's Sky")) {
600 /* Work around a NMS game bug */
601 instance->debug_flags |= RADV_DEBUG_DISCARD_TO_DEMOTE;
602 }
603 }
604
605 static int radv_get_instance_extension_index(const char *name)
606 {
607 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
608 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
609 return i;
610 }
611 return -1;
612 }
613
614 static const char radv_dri_options_xml[] =
615 DRI_CONF_BEGIN
616 DRI_CONF_SECTION_PERFORMANCE
617 DRI_CONF_ADAPTIVE_SYNC("true")
618 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
619 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
620 DRI_CONF_SECTION_END
621
622 DRI_CONF_SECTION_DEBUG
623 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
624 DRI_CONF_SECTION_END
625 DRI_CONF_END;
626
627 static void radv_init_dri_options(struct radv_instance *instance)
628 {
629 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
630 driParseConfigFiles(&instance->dri_options,
631 &instance->available_dri_options,
632 0, "radv", NULL,
633 instance->engineName,
634 instance->engineVersion);
635 }
636
637 VkResult radv_CreateInstance(
638 const VkInstanceCreateInfo* pCreateInfo,
639 const VkAllocationCallbacks* pAllocator,
640 VkInstance* pInstance)
641 {
642 struct radv_instance *instance;
643 VkResult result;
644
645 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
646
647 uint32_t client_version;
648 if (pCreateInfo->pApplicationInfo &&
649 pCreateInfo->pApplicationInfo->apiVersion != 0) {
650 client_version = pCreateInfo->pApplicationInfo->apiVersion;
651 } else {
652 client_version = VK_API_VERSION_1_0;
653 }
654
655 const char *engine_name = NULL;
656 uint32_t engine_version = 0;
657 if (pCreateInfo->pApplicationInfo) {
658 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
659 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
660 }
661
662 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
664 if (!instance)
665 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
666
667 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
668
669 if (pAllocator)
670 instance->alloc = *pAllocator;
671 else
672 instance->alloc = default_alloc;
673
674 instance->apiVersion = client_version;
675 instance->physicalDeviceCount = -1;
676
677 /* Get secure compile thread count. NOTE: We cap this at 32 */
678 #define MAX_SC_PROCS 32
679 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
680 if (num_sc_threads)
681 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
682
683 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
684 radv_debug_options);
685
686 /* Disable memory cache when secure compile is set */
687 if (radv_device_use_secure_compile(instance))
688 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
689
690 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
691 radv_perftest_options);
692
693 if (instance->perftest_flags & RADV_PERFTEST_ACO)
694 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
695
696 if (instance->debug_flags & RADV_DEBUG_STARTUP)
697 radv_logi("Created an instance");
698
699 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
700 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
701 int index = radv_get_instance_extension_index(ext_name);
702
703 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
704 vk_free2(&default_alloc, pAllocator, instance);
705 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
706 }
707
708 instance->enabled_extensions.extensions[index] = true;
709 }
710
711 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
712
713 for (unsigned i = 0; i < ARRAY_SIZE(instance->dispatch.entrypoints); i++) {
714 /* Vulkan requires that entrypoints for extensions which have
715 * not been enabled must not be advertised.
716 */
717 if (!unchecked &&
718 !radv_instance_entrypoint_is_enabled(i, instance->apiVersion,
719 &instance->enabled_extensions)) {
720 instance->dispatch.entrypoints[i] = NULL;
721 } else {
722 instance->dispatch.entrypoints[i] =
723 radv_instance_dispatch_table.entrypoints[i];
724 }
725 }
726
727 for (unsigned i = 0; i < ARRAY_SIZE(instance->physical_device_dispatch.entrypoints); i++) {
728 /* Vulkan requires that entrypoints for extensions which have
729 * not been enabled must not be advertised.
730 */
731 if (!unchecked &&
732 !radv_physical_device_entrypoint_is_enabled(i, instance->apiVersion,
733 &instance->enabled_extensions)) {
734 instance->physical_device_dispatch.entrypoints[i] = NULL;
735 } else {
736 instance->physical_device_dispatch.entrypoints[i] =
737 radv_physical_device_dispatch_table.entrypoints[i];
738 }
739 }
740
741 for (unsigned i = 0; i < ARRAY_SIZE(instance->device_dispatch.entrypoints); i++) {
742 /* Vulkan requires that entrypoints for extensions which have
743 * not been enabled must not be advertised.
744 */
745 if (!unchecked &&
746 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
747 &instance->enabled_extensions, NULL)) {
748 instance->device_dispatch.entrypoints[i] = NULL;
749 } else {
750 instance->device_dispatch.entrypoints[i] =
751 radv_device_dispatch_table.entrypoints[i];
752 }
753 }
754
755 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
756 if (result != VK_SUCCESS) {
757 vk_free2(&default_alloc, pAllocator, instance);
758 return vk_error(instance, result);
759 }
760
761 instance->engineName = vk_strdup(&instance->alloc, engine_name,
762 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
763 instance->engineVersion = engine_version;
764
765 glsl_type_singleton_init_or_ref();
766
767 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
768
769 radv_init_dri_options(instance);
770 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
771
772 *pInstance = radv_instance_to_handle(instance);
773
774 return VK_SUCCESS;
775 }
776
777 void radv_DestroyInstance(
778 VkInstance _instance,
779 const VkAllocationCallbacks* pAllocator)
780 {
781 RADV_FROM_HANDLE(radv_instance, instance, _instance);
782
783 if (!instance)
784 return;
785
786 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
787 radv_physical_device_finish(instance->physicalDevices + i);
788 }
789
790 vk_free(&instance->alloc, instance->engineName);
791
792 VG(VALGRIND_DESTROY_MEMPOOL(instance));
793
794 glsl_type_singleton_decref();
795
796 driDestroyOptionCache(&instance->dri_options);
797 driDestroyOptionInfo(&instance->available_dri_options);
798
799 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
800
801 vk_free(&instance->alloc, instance);
802 }
803
804 static VkResult
805 radv_enumerate_devices(struct radv_instance *instance)
806 {
807 /* TODO: Check for more devices ? */
808 drmDevicePtr devices[8];
809 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
810 int max_devices;
811
812 instance->physicalDeviceCount = 0;
813
814 if (getenv("RADV_FORCE_FAMILY")) {
815 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
816 * device that allows to test the compiler without having an
817 * AMDGPU instance.
818 */
819 result = radv_physical_device_init(instance->physicalDevices +
820 instance->physicalDeviceCount,
821 instance, NULL);
822
823 ++instance->physicalDeviceCount;
824 return VK_SUCCESS;
825 }
826
827 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
828
829 if (instance->debug_flags & RADV_DEBUG_STARTUP)
830 radv_logi("Found %d drm nodes", max_devices);
831
832 if (max_devices < 1)
833 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
834
835 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
836 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
837 devices[i]->bustype == DRM_BUS_PCI &&
838 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
839
840 result = radv_physical_device_init(instance->physicalDevices +
841 instance->physicalDeviceCount,
842 instance,
843 devices[i]);
844 if (result == VK_SUCCESS)
845 ++instance->physicalDeviceCount;
846 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
847 break;
848 }
849 }
850 drmFreeDevices(devices, max_devices);
851
852 return result;
853 }
854
855 VkResult radv_EnumeratePhysicalDevices(
856 VkInstance _instance,
857 uint32_t* pPhysicalDeviceCount,
858 VkPhysicalDevice* pPhysicalDevices)
859 {
860 RADV_FROM_HANDLE(radv_instance, instance, _instance);
861 VkResult result;
862
863 if (instance->physicalDeviceCount < 0) {
864 result = radv_enumerate_devices(instance);
865 if (result != VK_SUCCESS &&
866 result != VK_ERROR_INCOMPATIBLE_DRIVER)
867 return result;
868 }
869
870 if (!pPhysicalDevices) {
871 *pPhysicalDeviceCount = instance->physicalDeviceCount;
872 } else {
873 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
874 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
875 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
876 }
877
878 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
879 : VK_SUCCESS;
880 }
881
882 VkResult radv_EnumeratePhysicalDeviceGroups(
883 VkInstance _instance,
884 uint32_t* pPhysicalDeviceGroupCount,
885 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
886 {
887 RADV_FROM_HANDLE(radv_instance, instance, _instance);
888 VkResult result;
889
890 if (instance->physicalDeviceCount < 0) {
891 result = radv_enumerate_devices(instance);
892 if (result != VK_SUCCESS &&
893 result != VK_ERROR_INCOMPATIBLE_DRIVER)
894 return result;
895 }
896
897 if (!pPhysicalDeviceGroupProperties) {
898 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
899 } else {
900 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
901 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
902 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
903 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
904 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
905 }
906 }
907 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
908 : VK_SUCCESS;
909 }
910
911 void radv_GetPhysicalDeviceFeatures(
912 VkPhysicalDevice physicalDevice,
913 VkPhysicalDeviceFeatures* pFeatures)
914 {
915 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
916 memset(pFeatures, 0, sizeof(*pFeatures));
917
918 *pFeatures = (VkPhysicalDeviceFeatures) {
919 .robustBufferAccess = true,
920 .fullDrawIndexUint32 = true,
921 .imageCubeArray = true,
922 .independentBlend = true,
923 .geometryShader = true,
924 .tessellationShader = true,
925 .sampleRateShading = true,
926 .dualSrcBlend = true,
927 .logicOp = true,
928 .multiDrawIndirect = true,
929 .drawIndirectFirstInstance = true,
930 .depthClamp = true,
931 .depthBiasClamp = true,
932 .fillModeNonSolid = true,
933 .depthBounds = true,
934 .wideLines = true,
935 .largePoints = true,
936 .alphaToOne = true,
937 .multiViewport = true,
938 .samplerAnisotropy = true,
939 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
940 .textureCompressionASTC_LDR = false,
941 .textureCompressionBC = true,
942 .occlusionQueryPrecise = true,
943 .pipelineStatisticsQuery = true,
944 .vertexPipelineStoresAndAtomics = true,
945 .fragmentStoresAndAtomics = true,
946 .shaderTessellationAndGeometryPointSize = true,
947 .shaderImageGatherExtended = true,
948 .shaderStorageImageExtendedFormats = true,
949 .shaderStorageImageMultisample = true,
950 .shaderUniformBufferArrayDynamicIndexing = true,
951 .shaderSampledImageArrayDynamicIndexing = true,
952 .shaderStorageBufferArrayDynamicIndexing = true,
953 .shaderStorageImageArrayDynamicIndexing = true,
954 .shaderStorageImageReadWithoutFormat = true,
955 .shaderStorageImageWriteWithoutFormat = true,
956 .shaderClipDistance = true,
957 .shaderCullDistance = true,
958 .shaderFloat64 = true,
959 .shaderInt64 = true,
960 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
961 .sparseBinding = true,
962 .variableMultisampleRate = true,
963 .inheritedQueries = true,
964 };
965 }
966
967 void radv_GetPhysicalDeviceFeatures2(
968 VkPhysicalDevice physicalDevice,
969 VkPhysicalDeviceFeatures2 *pFeatures)
970 {
971 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
972 vk_foreach_struct(ext, pFeatures->pNext) {
973 switch (ext->sType) {
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
975 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
976 features->variablePointersStorageBuffer = true;
977 features->variablePointers = true;
978 break;
979 }
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
981 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
982 features->multiview = true;
983 features->multiviewGeometryShader = true;
984 features->multiviewTessellationShader = true;
985 break;
986 }
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
988 VkPhysicalDeviceShaderDrawParametersFeatures *features =
989 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
990 features->shaderDrawParameters = true;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
994 VkPhysicalDeviceProtectedMemoryFeatures *features =
995 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
996 features->protectedMemory = false;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
1000 VkPhysicalDevice16BitStorageFeatures *features =
1001 (VkPhysicalDevice16BitStorageFeatures*)ext;
1002 bool enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1003 features->storageBuffer16BitAccess = enable;
1004 features->uniformAndStorageBuffer16BitAccess = enable;
1005 features->storagePushConstant16 = enable;
1006 features->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
1007 break;
1008 }
1009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
1010 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
1011 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
1012 features->samplerYcbcrConversion = true;
1013 break;
1014 }
1015 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES: {
1016 VkPhysicalDeviceDescriptorIndexingFeatures *features =
1017 (VkPhysicalDeviceDescriptorIndexingFeatures*)ext;
1018 features->shaderInputAttachmentArrayDynamicIndexing = true;
1019 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1020 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1021 features->shaderUniformBufferArrayNonUniformIndexing = true;
1022 features->shaderSampledImageArrayNonUniformIndexing = true;
1023 features->shaderStorageBufferArrayNonUniformIndexing = true;
1024 features->shaderStorageImageArrayNonUniformIndexing = true;
1025 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1026 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1027 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1028 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1029 features->descriptorBindingSampledImageUpdateAfterBind = true;
1030 features->descriptorBindingStorageImageUpdateAfterBind = true;
1031 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1032 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1033 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1034 features->descriptorBindingUpdateUnusedWhilePending = true;
1035 features->descriptorBindingPartiallyBound = true;
1036 features->descriptorBindingVariableDescriptorCount = true;
1037 features->runtimeDescriptorArray = true;
1038 break;
1039 }
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1041 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1042 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1043 features->conditionalRendering = true;
1044 features->inheritedConditionalRendering = false;
1045 break;
1046 }
1047 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1048 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1049 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1050 features->vertexAttributeInstanceRateDivisor = true;
1051 features->vertexAttributeInstanceRateZeroDivisor = true;
1052 break;
1053 }
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1055 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1056 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1057 features->transformFeedback = true;
1058 features->geometryStreams = !pdevice->use_ngg_streamout;
1059 break;
1060 }
1061 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES: {
1062 VkPhysicalDeviceScalarBlockLayoutFeatures *features =
1063 (VkPhysicalDeviceScalarBlockLayoutFeatures *)ext;
1064 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1065 break;
1066 }
1067 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1068 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1069 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1070 features->memoryPriority = true;
1071 break;
1072 }
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1074 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1075 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1076 features->bufferDeviceAddress = true;
1077 features->bufferDeviceAddressCaptureReplay = false;
1078 features->bufferDeviceAddressMultiDevice = false;
1079 break;
1080 }
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES: {
1082 VkPhysicalDeviceBufferDeviceAddressFeatures *features =
1083 (VkPhysicalDeviceBufferDeviceAddressFeatures *)ext;
1084 features->bufferDeviceAddress = true;
1085 features->bufferDeviceAddressCaptureReplay = false;
1086 features->bufferDeviceAddressMultiDevice = false;
1087 break;
1088 }
1089 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1090 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1091 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1092 features->depthClipEnable = true;
1093 break;
1094 }
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES: {
1096 VkPhysicalDeviceHostQueryResetFeatures *features =
1097 (VkPhysicalDeviceHostQueryResetFeatures *)ext;
1098 features->hostQueryReset = true;
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES: {
1102 VkPhysicalDevice8BitStorageFeatures *features =
1103 (VkPhysicalDevice8BitStorageFeatures *)ext;
1104 bool enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1105 features->storageBuffer8BitAccess = enable;
1106 features->uniformAndStorageBuffer8BitAccess = enable;
1107 features->storagePushConstant8 = enable;
1108 break;
1109 }
1110 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES: {
1111 VkPhysicalDeviceShaderFloat16Int8Features *features =
1112 (VkPhysicalDeviceShaderFloat16Int8Features*)ext;
1113 features->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
1114 features->shaderInt8 = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1115 break;
1116 }
1117 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES: {
1118 VkPhysicalDeviceShaderAtomicInt64Features *features =
1119 (VkPhysicalDeviceShaderAtomicInt64Features *)ext;
1120 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1121 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1125 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1126 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1127 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1128 break;
1129 }
1130 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1131 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1132 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1133
1134 features->inlineUniformBlock = true;
1135 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1139 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1140 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1141 features->computeDerivativeGroupQuads = false;
1142 features->computeDerivativeGroupLinear = true;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1146 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1147 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1148 features->ycbcrImageArrays = true;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES: {
1152 VkPhysicalDeviceUniformBufferStandardLayoutFeatures *features =
1153 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures *)ext;
1154 features->uniformBufferStandardLayout = true;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1158 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1159 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1160 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1161 break;
1162 }
1163 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES: {
1164 VkPhysicalDeviceImagelessFramebufferFeatures *features =
1165 (VkPhysicalDeviceImagelessFramebufferFeatures *)ext;
1166 features->imagelessFramebuffer = true;
1167 break;
1168 }
1169 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1170 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1171 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1172 features->pipelineExecutableInfo = true;
1173 break;
1174 }
1175 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1176 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1177 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1178 features->shaderSubgroupClock = true;
1179 features->shaderDeviceClock = false;
1180 break;
1181 }
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1183 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1184 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1185 features->texelBufferAlignment = true;
1186 break;
1187 }
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES: {
1189 VkPhysicalDeviceTimelineSemaphoreFeatures *features =
1190 (VkPhysicalDeviceTimelineSemaphoreFeatures *) ext;
1191 features->timelineSemaphore = true;
1192 break;
1193 }
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1195 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1196 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1197 features->subgroupSizeControl = true;
1198 features->computeFullSubgroups = true;
1199 break;
1200 }
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1202 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1203 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1204 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES: {
1208 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *features =
1209 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures *)ext;
1210 features->shaderSubgroupExtendedTypes = !pdevice->use_aco;
1211 break;
1212 }
1213 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR: {
1214 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *features =
1215 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR *)ext;
1216 features->separateDepthStencilLayouts = true;
1217 break;
1218 }
1219 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES: {
1220 VkPhysicalDeviceVulkan11Features *features =
1221 (VkPhysicalDeviceVulkan11Features *)ext;
1222 bool storage16_enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1223 features->storageBuffer16BitAccess = storage16_enable;
1224 features->uniformAndStorageBuffer16BitAccess = storage16_enable;
1225 features->storagePushConstant16 = storage16_enable;
1226 features->storageInputOutput16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco && LLVM_VERSION_MAJOR >= 9;
1227 features->multiview = true;
1228 features->multiviewGeometryShader = true;
1229 features->multiviewTessellationShader = true;
1230 features->variablePointersStorageBuffer = true;
1231 features->variablePointers = true;
1232 features->protectedMemory = false;
1233 features->samplerYcbcrConversion = true;
1234 features->shaderDrawParameters = true;
1235 break;
1236 }
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES: {
1238 VkPhysicalDeviceVulkan12Features *features =
1239 (VkPhysicalDeviceVulkan12Features *)ext;
1240 bool int8_enable = !pdevice->use_aco || pdevice->rad_info.chip_class >= GFX8;
1241 features->samplerMirrorClampToEdge = true;
1242 features->drawIndirectCount = true;
1243 features->storageBuffer8BitAccess = int8_enable;
1244 features->uniformAndStorageBuffer8BitAccess = int8_enable;
1245 features->storagePushConstant8 = int8_enable;
1246 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1247 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1248 features->shaderFloat16 = pdevice->rad_info.has_double_rate_fp16 && !pdevice->use_aco;
1249 features->shaderInt8 = int8_enable;
1250 features->descriptorIndexing = true;
1251 features->shaderInputAttachmentArrayDynamicIndexing = true;
1252 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1253 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1254 features->shaderUniformBufferArrayNonUniformIndexing = true;
1255 features->shaderSampledImageArrayNonUniformIndexing = true;
1256 features->shaderStorageBufferArrayNonUniformIndexing = true;
1257 features->shaderStorageImageArrayNonUniformIndexing = true;
1258 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1259 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1260 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1261 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1262 features->descriptorBindingSampledImageUpdateAfterBind = true;
1263 features->descriptorBindingStorageImageUpdateAfterBind = true;
1264 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1265 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1266 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1267 features->descriptorBindingUpdateUnusedWhilePending = true;
1268 features->descriptorBindingPartiallyBound = true;
1269 features->descriptorBindingVariableDescriptorCount = true;
1270 features->runtimeDescriptorArray = true;
1271 features->samplerFilterMinmax = true;
1272 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1273 features->imagelessFramebuffer = true;
1274 features->uniformBufferStandardLayout = true;
1275 features->shaderSubgroupExtendedTypes = !pdevice->use_aco;
1276 features->separateDepthStencilLayouts = true;
1277 features->hostQueryReset = true;
1278 features->timelineSemaphore = pdevice->rad_info.has_syncobj_wait_for_submit;
1279 features->bufferDeviceAddress = true;
1280 features->bufferDeviceAddressCaptureReplay = false;
1281 features->bufferDeviceAddressMultiDevice = false;
1282 features->vulkanMemoryModel = false;
1283 features->vulkanMemoryModelDeviceScope = false;
1284 features->vulkanMemoryModelAvailabilityVisibilityChains = false;
1285 features->shaderOutputViewportIndex = true;
1286 features->shaderOutputLayer = true;
1287 features->subgroupBroadcastDynamicId = true;
1288 break;
1289 }
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT: {
1291 VkPhysicalDeviceLineRasterizationFeaturesEXT *features =
1292 (VkPhysicalDeviceLineRasterizationFeaturesEXT *)ext;
1293 features->rectangularLines = false;
1294 features->bresenhamLines = true;
1295 features->smoothLines = false;
1296 features->stippledRectangularLines = false;
1297 features->stippledBresenhamLines = true;
1298 features->stippledSmoothLines = false;
1299 break;
1300 }
1301 default:
1302 break;
1303 }
1304 }
1305 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1306 }
1307
1308 static size_t
1309 radv_max_descriptor_set_size()
1310 {
1311 /* make sure that the entire descriptor set is addressable with a signed
1312 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1313 * be at most 2 GiB. the combined image & samples object count as one of
1314 * both. This limit is for the pipeline layout, not for the set layout, but
1315 * there is no set limit, so we just set a pipeline limit. I don't think
1316 * any app is going to hit this soon. */
1317 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1318 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1319 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1320 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1321 32 /* sampler, largest when combined with image */ +
1322 64 /* sampled image */ +
1323 64 /* storage image */);
1324 }
1325
1326 void radv_GetPhysicalDeviceProperties(
1327 VkPhysicalDevice physicalDevice,
1328 VkPhysicalDeviceProperties* pProperties)
1329 {
1330 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1331 VkSampleCountFlags sample_counts = 0xf;
1332
1333 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1334
1335 VkPhysicalDeviceLimits limits = {
1336 .maxImageDimension1D = (1 << 14),
1337 .maxImageDimension2D = (1 << 14),
1338 .maxImageDimension3D = (1 << 11),
1339 .maxImageDimensionCube = (1 << 14),
1340 .maxImageArrayLayers = (1 << 11),
1341 .maxTexelBufferElements = 128 * 1024 * 1024,
1342 .maxUniformBufferRange = UINT32_MAX,
1343 .maxStorageBufferRange = UINT32_MAX,
1344 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1345 .maxMemoryAllocationCount = UINT32_MAX,
1346 .maxSamplerAllocationCount = 64 * 1024,
1347 .bufferImageGranularity = 64, /* A cache line */
1348 .sparseAddressSpaceSize = RADV_MAX_MEMORY_ALLOCATION_SIZE, /* buffer max size */
1349 .maxBoundDescriptorSets = MAX_SETS,
1350 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1351 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1352 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1353 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1354 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1355 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1356 .maxPerStageResources = max_descriptor_set_size,
1357 .maxDescriptorSetSamplers = max_descriptor_set_size,
1358 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1359 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1360 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1361 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1362 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1363 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1364 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1365 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1366 .maxVertexInputBindings = MAX_VBS,
1367 .maxVertexInputAttributeOffset = 2047,
1368 .maxVertexInputBindingStride = 2048,
1369 .maxVertexOutputComponents = 128,
1370 .maxTessellationGenerationLevel = 64,
1371 .maxTessellationPatchSize = 32,
1372 .maxTessellationControlPerVertexInputComponents = 128,
1373 .maxTessellationControlPerVertexOutputComponents = 128,
1374 .maxTessellationControlPerPatchOutputComponents = 120,
1375 .maxTessellationControlTotalOutputComponents = 4096,
1376 .maxTessellationEvaluationInputComponents = 128,
1377 .maxTessellationEvaluationOutputComponents = 128,
1378 .maxGeometryShaderInvocations = 127,
1379 .maxGeometryInputComponents = 64,
1380 .maxGeometryOutputComponents = 128,
1381 .maxGeometryOutputVertices = 256,
1382 .maxGeometryTotalOutputComponents = 1024,
1383 .maxFragmentInputComponents = 128,
1384 .maxFragmentOutputAttachments = 8,
1385 .maxFragmentDualSrcAttachments = 1,
1386 .maxFragmentCombinedOutputResources = 8,
1387 .maxComputeSharedMemorySize = 32768,
1388 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1389 .maxComputeWorkGroupInvocations = 1024,
1390 .maxComputeWorkGroupSize = {
1391 1024,
1392 1024,
1393 1024
1394 },
1395 .subPixelPrecisionBits = 8,
1396 .subTexelPrecisionBits = 8,
1397 .mipmapPrecisionBits = 8,
1398 .maxDrawIndexedIndexValue = UINT32_MAX,
1399 .maxDrawIndirectCount = UINT32_MAX,
1400 .maxSamplerLodBias = 16,
1401 .maxSamplerAnisotropy = 16,
1402 .maxViewports = MAX_VIEWPORTS,
1403 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1404 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1405 .viewportSubPixelBits = 8,
1406 .minMemoryMapAlignment = 4096, /* A page */
1407 .minTexelBufferOffsetAlignment = 4,
1408 .minUniformBufferOffsetAlignment = 4,
1409 .minStorageBufferOffsetAlignment = 4,
1410 .minTexelOffset = -32,
1411 .maxTexelOffset = 31,
1412 .minTexelGatherOffset = -32,
1413 .maxTexelGatherOffset = 31,
1414 .minInterpolationOffset = -2,
1415 .maxInterpolationOffset = 2,
1416 .subPixelInterpolationOffsetBits = 8,
1417 .maxFramebufferWidth = (1 << 14),
1418 .maxFramebufferHeight = (1 << 14),
1419 .maxFramebufferLayers = (1 << 10),
1420 .framebufferColorSampleCounts = sample_counts,
1421 .framebufferDepthSampleCounts = sample_counts,
1422 .framebufferStencilSampleCounts = sample_counts,
1423 .framebufferNoAttachmentsSampleCounts = sample_counts,
1424 .maxColorAttachments = MAX_RTS,
1425 .sampledImageColorSampleCounts = sample_counts,
1426 .sampledImageIntegerSampleCounts = sample_counts,
1427 .sampledImageDepthSampleCounts = sample_counts,
1428 .sampledImageStencilSampleCounts = sample_counts,
1429 .storageImageSampleCounts = sample_counts,
1430 .maxSampleMaskWords = 1,
1431 .timestampComputeAndGraphics = true,
1432 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1433 .maxClipDistances = 8,
1434 .maxCullDistances = 8,
1435 .maxCombinedClipAndCullDistances = 8,
1436 .discreteQueuePriorities = 2,
1437 .pointSizeRange = { 0.0, 8192.0 },
1438 .lineWidthRange = { 0.0, 8192.0 },
1439 .pointSizeGranularity = (1.0 / 8.0),
1440 .lineWidthGranularity = (1.0 / 8.0),
1441 .strictLines = false, /* FINISHME */
1442 .standardSampleLocations = true,
1443 .optimalBufferCopyOffsetAlignment = 128,
1444 .optimalBufferCopyRowPitchAlignment = 128,
1445 .nonCoherentAtomSize = 64,
1446 };
1447
1448 *pProperties = (VkPhysicalDeviceProperties) {
1449 .apiVersion = radv_physical_device_api_version(pdevice),
1450 .driverVersion = vk_get_driver_version(),
1451 .vendorID = ATI_VENDOR_ID,
1452 .deviceID = pdevice->rad_info.pci_id,
1453 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1454 .limits = limits,
1455 .sparseProperties = {0},
1456 };
1457
1458 strcpy(pProperties->deviceName, pdevice->name);
1459 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1460 }
1461
1462 static void
1463 radv_get_physical_device_properties_1_1(struct radv_physical_device *pdevice,
1464 VkPhysicalDeviceVulkan11Properties *p)
1465 {
1466 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES);
1467
1468 memcpy(p->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1469 memcpy(p->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1470 memset(p->deviceLUID, 0, VK_LUID_SIZE);
1471 /* The LUID is for Windows. */
1472 p->deviceLUIDValid = false;
1473 p->deviceNodeMask = 0;
1474
1475 p->subgroupSize = RADV_SUBGROUP_SIZE;
1476 p->subgroupSupportedStages = VK_SHADER_STAGE_ALL_GRAPHICS |
1477 VK_SHADER_STAGE_COMPUTE_BIT;
1478 p->subgroupSupportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT |
1479 VK_SUBGROUP_FEATURE_VOTE_BIT |
1480 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1481 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1482 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1483 VK_SUBGROUP_FEATURE_QUAD_BIT;
1484
1485 if (((pdevice->rad_info.chip_class == GFX6 ||
1486 pdevice->rad_info.chip_class == GFX7) && !pdevice->use_aco) ||
1487 pdevice->rad_info.chip_class >= GFX8) {
1488 p->subgroupSupportedOperations |= VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1489 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1490 }
1491 p->subgroupQuadOperationsInAllStages = true;
1492
1493 p->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1494 p->maxMultiviewViewCount = MAX_VIEWS;
1495 p->maxMultiviewInstanceIndex = INT_MAX;
1496 p->protectedNoFault = false;
1497 p->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1498 p->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1499 }
1500
1501 static void
1502 radv_get_physical_device_properties_1_2(struct radv_physical_device *pdevice,
1503 VkPhysicalDeviceVulkan12Properties *p)
1504 {
1505 assert(p->sType == VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES);
1506
1507 p->driverID = VK_DRIVER_ID_MESA_RADV;
1508 snprintf(p->driverName, VK_MAX_DRIVER_NAME_SIZE, "radv");
1509 snprintf(p->driverInfo, VK_MAX_DRIVER_INFO_SIZE,
1510 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1511 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1512 p->conformanceVersion = (VkConformanceVersion) {
1513 .major = 1,
1514 .minor = 2,
1515 .subminor = 0,
1516 .patch = 0,
1517 };
1518
1519 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1520 * controlled by the same config register.
1521 */
1522 if (pdevice->rad_info.has_double_rate_fp16) {
1523 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1524 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1525 } else {
1526 p->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1527 p->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR;
1528 }
1529
1530 /* Do not allow both preserving and flushing denorms because different
1531 * shaders in the same pipeline can have different settings and this
1532 * won't work for merged shaders. To make it work, this requires LLVM
1533 * support for changing the register. The same logic applies for the
1534 * rounding modes because they are configured with the same config
1535 * register. TODO: we can enable a lot of these for ACO when it
1536 * supports all stages.
1537 */
1538 p->shaderDenormFlushToZeroFloat32 = true;
1539 p->shaderDenormPreserveFloat32 = false;
1540 p->shaderRoundingModeRTEFloat32 = true;
1541 p->shaderRoundingModeRTZFloat32 = false;
1542 p->shaderSignedZeroInfNanPreserveFloat32 = true;
1543
1544 p->shaderDenormFlushToZeroFloat16 = false;
1545 p->shaderDenormPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
1546 p->shaderRoundingModeRTEFloat16 = pdevice->rad_info.has_double_rate_fp16;
1547 p->shaderRoundingModeRTZFloat16 = false;
1548 p->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.has_double_rate_fp16;
1549
1550 p->shaderDenormFlushToZeroFloat64 = false;
1551 p->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1552 p->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1553 p->shaderRoundingModeRTZFloat64 = false;
1554 p->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1555
1556 p->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1557 p->shaderUniformBufferArrayNonUniformIndexingNative = false;
1558 p->shaderSampledImageArrayNonUniformIndexingNative = false;
1559 p->shaderStorageBufferArrayNonUniformIndexingNative = false;
1560 p->shaderStorageImageArrayNonUniformIndexingNative = false;
1561 p->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1562 p->robustBufferAccessUpdateAfterBind = false;
1563 p->quadDivergentImplicitLod = false;
1564
1565 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1566 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1567 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1568 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1569 32 /* sampler, largest when combined with image */ +
1570 64 /* sampled image */ +
1571 64 /* storage image */);
1572 p->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1573 p->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1574 p->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1575 p->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1576 p->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1577 p->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1578 p->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1579 p->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1580 p->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1581 p->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1582 p->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1583 p->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1584 p->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1585 p->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1586 p->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1587
1588 /* We support all of the depth resolve modes */
1589 p->supportedDepthResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1590 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1591 VK_RESOLVE_MODE_MIN_BIT_KHR |
1592 VK_RESOLVE_MODE_MAX_BIT_KHR;
1593
1594 /* Average doesn't make sense for stencil so we don't support that */
1595 p->supportedStencilResolveModes = VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1596 VK_RESOLVE_MODE_MIN_BIT_KHR |
1597 VK_RESOLVE_MODE_MAX_BIT_KHR;
1598
1599 p->independentResolveNone = true;
1600 p->independentResolve = true;
1601
1602 /* GFX6-8 only support single channel min/max filter. */
1603 p->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1604 p->filterMinmaxSingleComponentFormats = true;
1605
1606 p->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1607
1608 p->framebufferIntegerColorSampleCounts = VK_SAMPLE_COUNT_1_BIT;
1609 }
1610
1611 void radv_GetPhysicalDeviceProperties2(
1612 VkPhysicalDevice physicalDevice,
1613 VkPhysicalDeviceProperties2 *pProperties)
1614 {
1615 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1616 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1617
1618 VkPhysicalDeviceVulkan11Properties core_1_1 = {
1619 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES,
1620 };
1621 radv_get_physical_device_properties_1_1(pdevice, &core_1_1);
1622
1623 VkPhysicalDeviceVulkan12Properties core_1_2 = {
1624 .sType = VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES,
1625 };
1626 radv_get_physical_device_properties_1_2(pdevice, &core_1_2);
1627
1628 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1629 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1630 sizeof(core_##major##_##minor.core_property))
1631
1632 #define CORE_PROPERTY(major, minor, property) \
1633 CORE_RENAMED_PROPERTY(major, minor, property, property)
1634
1635 vk_foreach_struct(ext, pProperties->pNext) {
1636 switch (ext->sType) {
1637 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1638 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1639 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1640 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1641 break;
1642 }
1643 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1644 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1645 CORE_PROPERTY(1, 1, deviceUUID);
1646 CORE_PROPERTY(1, 1, driverUUID);
1647 CORE_PROPERTY(1, 1, deviceLUID);
1648 CORE_PROPERTY(1, 1, deviceLUIDValid);
1649 break;
1650 }
1651 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1652 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1653 CORE_PROPERTY(1, 1, maxMultiviewViewCount);
1654 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex);
1655 break;
1656 }
1657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1658 VkPhysicalDevicePointClippingProperties *properties =
1659 (VkPhysicalDevicePointClippingProperties*)ext;
1660 CORE_PROPERTY(1, 1, pointClippingBehavior);
1661 break;
1662 }
1663 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1664 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1665 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1666 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1667 break;
1668 }
1669 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1670 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1671 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1672 properties->minImportedHostPointerAlignment = 4096;
1673 break;
1674 }
1675 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1676 VkPhysicalDeviceSubgroupProperties *properties =
1677 (VkPhysicalDeviceSubgroupProperties*)ext;
1678 CORE_PROPERTY(1, 1, subgroupSize);
1679 CORE_RENAMED_PROPERTY(1, 1, supportedStages,
1680 subgroupSupportedStages);
1681 CORE_RENAMED_PROPERTY(1, 1, supportedOperations,
1682 subgroupSupportedOperations);
1683 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages,
1684 subgroupQuadOperationsInAllStages);
1685 break;
1686 }
1687 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1688 VkPhysicalDeviceMaintenance3Properties *properties =
1689 (VkPhysicalDeviceMaintenance3Properties*)ext;
1690 CORE_PROPERTY(1, 1, maxPerSetDescriptors);
1691 CORE_PROPERTY(1, 1, maxMemoryAllocationSize);
1692 break;
1693 }
1694 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES: {
1695 VkPhysicalDeviceSamplerFilterMinmaxProperties *properties =
1696 (VkPhysicalDeviceSamplerFilterMinmaxProperties *)ext;
1697 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping);
1698 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats);
1699 break;
1700 }
1701 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1702 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1703 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1704
1705 /* Shader engines. */
1706 properties->shaderEngineCount =
1707 pdevice->rad_info.max_se;
1708 properties->shaderArraysPerEngineCount =
1709 pdevice->rad_info.max_sh_per_se;
1710 properties->computeUnitsPerShaderArray =
1711 pdevice->rad_info.num_good_cu_per_sh;
1712 properties->simdPerComputeUnit =
1713 pdevice->rad_info.num_simd_per_compute_unit;
1714 properties->wavefrontsPerSimd =
1715 pdevice->rad_info.max_wave64_per_simd;
1716 properties->wavefrontSize = 64;
1717
1718 /* SGPR. */
1719 properties->sgprsPerSimd =
1720 pdevice->rad_info.num_physical_sgprs_per_simd;
1721 properties->minSgprAllocation =
1722 pdevice->rad_info.min_sgpr_alloc;
1723 properties->maxSgprAllocation =
1724 pdevice->rad_info.max_sgpr_alloc;
1725 properties->sgprAllocationGranularity =
1726 pdevice->rad_info.sgpr_alloc_granularity;
1727
1728 /* VGPR. */
1729 properties->vgprsPerSimd =
1730 pdevice->rad_info.num_physical_wave64_vgprs_per_simd;
1731 properties->minVgprAllocation =
1732 pdevice->rad_info.min_wave64_vgpr_alloc;
1733 properties->maxVgprAllocation =
1734 pdevice->rad_info.max_vgpr_alloc;
1735 properties->vgprAllocationGranularity =
1736 pdevice->rad_info.wave64_vgpr_alloc_granularity;
1737 break;
1738 }
1739 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1740 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1741 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1742
1743 properties->shaderCoreFeatures = 0;
1744 properties->activeComputeUnitCount =
1745 pdevice->rad_info.num_good_compute_units;
1746 break;
1747 }
1748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1749 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1750 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1751 properties->maxVertexAttribDivisor = UINT32_MAX;
1752 break;
1753 }
1754 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES: {
1755 VkPhysicalDeviceDescriptorIndexingProperties *properties =
1756 (VkPhysicalDeviceDescriptorIndexingProperties*)ext;
1757 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools);
1758 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative);
1759 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative);
1760 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative);
1761 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative);
1762 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative);
1763 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind);
1764 CORE_PROPERTY(1, 2, quadDivergentImplicitLod);
1765 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers);
1766 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers);
1767 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers);
1768 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages);
1769 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages);
1770 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments);
1771 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources);
1772 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers);
1773 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers);
1774 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic);
1775 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers);
1776 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic);
1777 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages);
1778 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages);
1779 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments);
1780 break;
1781 }
1782 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1783 VkPhysicalDeviceProtectedMemoryProperties *properties =
1784 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1785 CORE_PROPERTY(1, 1, protectedNoFault);
1786 break;
1787 }
1788 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1789 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1790 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1791 properties->primitiveOverestimationSize = 0;
1792 properties->maxExtraPrimitiveOverestimationSize = 0;
1793 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1794 properties->primitiveUnderestimation = false;
1795 properties->conservativePointAndLineRasterization = false;
1796 properties->degenerateTrianglesRasterized = false;
1797 properties->degenerateLinesRasterized = false;
1798 properties->fullyCoveredFragmentShaderInputVariable = false;
1799 properties->conservativeRasterizationPostDepthCoverage = false;
1800 break;
1801 }
1802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1803 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1804 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1805 properties->pciDomain = pdevice->bus_info.domain;
1806 properties->pciBus = pdevice->bus_info.bus;
1807 properties->pciDevice = pdevice->bus_info.dev;
1808 properties->pciFunction = pdevice->bus_info.func;
1809 break;
1810 }
1811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES: {
1812 VkPhysicalDeviceDriverProperties *properties =
1813 (VkPhysicalDeviceDriverProperties *) ext;
1814 CORE_PROPERTY(1, 2, driverID);
1815 CORE_PROPERTY(1, 2, driverName);
1816 CORE_PROPERTY(1, 2, driverInfo);
1817 CORE_PROPERTY(1, 2, conformanceVersion);
1818 break;
1819 }
1820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1821 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1822 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1823 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1824 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1825 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1826 properties->maxTransformFeedbackStreamDataSize = 512;
1827 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1828 properties->maxTransformFeedbackBufferDataStride = 512;
1829 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1830 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1831 properties->transformFeedbackRasterizationStreamSelect = false;
1832 properties->transformFeedbackDraw = true;
1833 break;
1834 }
1835 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1836 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1837 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1838
1839 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1840 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1841 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1842 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1843 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1844 break;
1845 }
1846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1847 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1848 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1849 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1850 VK_SAMPLE_COUNT_4_BIT |
1851 VK_SAMPLE_COUNT_8_BIT;
1852 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1853 properties->sampleLocationCoordinateRange[0] = 0.0f;
1854 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1855 properties->sampleLocationSubPixelBits = 4;
1856 properties->variableSampleLocations = false;
1857 break;
1858 }
1859 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES: {
1860 VkPhysicalDeviceDepthStencilResolveProperties *properties =
1861 (VkPhysicalDeviceDepthStencilResolveProperties *)ext;
1862 CORE_PROPERTY(1, 2, supportedDepthResolveModes);
1863 CORE_PROPERTY(1, 2, supportedStencilResolveModes);
1864 CORE_PROPERTY(1, 2, independentResolveNone);
1865 CORE_PROPERTY(1, 2, independentResolve);
1866 break;
1867 }
1868 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1869 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1870 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1871 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1872 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1873 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1874 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1875 break;
1876 }
1877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES : {
1878 VkPhysicalDeviceFloatControlsProperties *properties =
1879 (VkPhysicalDeviceFloatControlsProperties *)ext;
1880 CORE_PROPERTY(1, 2, denormBehaviorIndependence);
1881 CORE_PROPERTY(1, 2, roundingModeIndependence);
1882 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16);
1883 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16);
1884 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16);
1885 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16);
1886 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16);
1887 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32);
1888 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32);
1889 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32);
1890 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32);
1891 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32);
1892 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64);
1893 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64);
1894 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64);
1895 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64);
1896 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64);
1897 break;
1898 }
1899 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES: {
1900 VkPhysicalDeviceTimelineSemaphoreProperties *properties =
1901 (VkPhysicalDeviceTimelineSemaphoreProperties *) ext;
1902 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference);
1903 break;
1904 }
1905 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1906 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1907 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1908 props->minSubgroupSize = 64;
1909 props->maxSubgroupSize = 64;
1910 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1911 props->requiredSubgroupSizeStages = 0;
1912
1913 if (pdevice->rad_info.chip_class >= GFX10) {
1914 /* Only GFX10+ supports wave32. */
1915 props->minSubgroupSize = 32;
1916 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1917 }
1918 break;
1919 }
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES:
1921 radv_get_physical_device_properties_1_1(pdevice, (void *)ext);
1922 break;
1923 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES:
1924 radv_get_physical_device_properties_1_2(pdevice, (void *)ext);
1925 break;
1926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT: {
1927 VkPhysicalDeviceLineRasterizationPropertiesEXT *props =
1928 (VkPhysicalDeviceLineRasterizationPropertiesEXT *)ext;
1929 props->lineSubPixelPrecisionBits = 4;
1930 break;
1931 }
1932 default:
1933 break;
1934 }
1935 }
1936 }
1937
1938 static void radv_get_physical_device_queue_family_properties(
1939 struct radv_physical_device* pdevice,
1940 uint32_t* pCount,
1941 VkQueueFamilyProperties** pQueueFamilyProperties)
1942 {
1943 int num_queue_families = 1;
1944 int idx;
1945 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1946 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1947 num_queue_families++;
1948
1949 if (pQueueFamilyProperties == NULL) {
1950 *pCount = num_queue_families;
1951 return;
1952 }
1953
1954 if (!*pCount)
1955 return;
1956
1957 idx = 0;
1958 if (*pCount >= 1) {
1959 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1960 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1961 VK_QUEUE_COMPUTE_BIT |
1962 VK_QUEUE_TRANSFER_BIT |
1963 VK_QUEUE_SPARSE_BINDING_BIT,
1964 .queueCount = 1,
1965 .timestampValidBits = 64,
1966 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1967 };
1968 idx++;
1969 }
1970
1971 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1972 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1973 if (*pCount > idx) {
1974 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1975 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1976 VK_QUEUE_TRANSFER_BIT |
1977 VK_QUEUE_SPARSE_BINDING_BIT,
1978 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1979 .timestampValidBits = 64,
1980 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1981 };
1982 idx++;
1983 }
1984 }
1985 *pCount = idx;
1986 }
1987
1988 void radv_GetPhysicalDeviceQueueFamilyProperties(
1989 VkPhysicalDevice physicalDevice,
1990 uint32_t* pCount,
1991 VkQueueFamilyProperties* pQueueFamilyProperties)
1992 {
1993 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1994 if (!pQueueFamilyProperties) {
1995 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1996 return;
1997 }
1998 VkQueueFamilyProperties *properties[] = {
1999 pQueueFamilyProperties + 0,
2000 pQueueFamilyProperties + 1,
2001 pQueueFamilyProperties + 2,
2002 };
2003 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2004 assert(*pCount <= 3);
2005 }
2006
2007 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2008 VkPhysicalDevice physicalDevice,
2009 uint32_t* pCount,
2010 VkQueueFamilyProperties2 *pQueueFamilyProperties)
2011 {
2012 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
2013 if (!pQueueFamilyProperties) {
2014 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
2015 return;
2016 }
2017 VkQueueFamilyProperties *properties[] = {
2018 &pQueueFamilyProperties[0].queueFamilyProperties,
2019 &pQueueFamilyProperties[1].queueFamilyProperties,
2020 &pQueueFamilyProperties[2].queueFamilyProperties,
2021 };
2022 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
2023 assert(*pCount <= 3);
2024 }
2025
2026 void radv_GetPhysicalDeviceMemoryProperties(
2027 VkPhysicalDevice physicalDevice,
2028 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
2029 {
2030 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2031
2032 *pMemoryProperties = physical_device->memory_properties;
2033 }
2034
2035 static void
2036 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
2037 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
2038 {
2039 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2040 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
2041 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
2042 uint64_t vram_size = radv_get_vram_size(device);
2043 uint64_t gtt_size = device->rad_info.gart_size;
2044 uint64_t heap_budget, heap_usage;
2045
2046 /* For all memory heaps, the computation of budget is as follow:
2047 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2048 *
2049 * The Vulkan spec 1.1.97 says that the budget should include any
2050 * currently allocated device memory.
2051 *
2052 * Note that the application heap usages are not really accurate (eg.
2053 * in presence of shared buffers).
2054 */
2055 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
2056 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
2057
2058 if (radv_is_mem_type_vram(device->mem_type_indices[i])) {
2059 heap_usage = device->ws->query_value(device->ws,
2060 RADEON_ALLOCATED_VRAM);
2061
2062 heap_budget = vram_size -
2063 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
2064 heap_usage;
2065
2066 memoryBudget->heapBudget[heap_index] = heap_budget;
2067 memoryBudget->heapUsage[heap_index] = heap_usage;
2068 } else if (radv_is_mem_type_vram_visible(device->mem_type_indices[i])) {
2069 heap_usage = device->ws->query_value(device->ws,
2070 RADEON_ALLOCATED_VRAM_VIS);
2071
2072 heap_budget = visible_vram_size -
2073 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
2074 heap_usage;
2075
2076 memoryBudget->heapBudget[heap_index] = heap_budget;
2077 memoryBudget->heapUsage[heap_index] = heap_usage;
2078 } else if (radv_is_mem_type_gtt_wc(device->mem_type_indices[i])) {
2079 heap_usage = device->ws->query_value(device->ws,
2080 RADEON_ALLOCATED_GTT);
2081
2082 heap_budget = gtt_size -
2083 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
2084 heap_usage;
2085
2086 memoryBudget->heapBudget[heap_index] = heap_budget;
2087 memoryBudget->heapUsage[heap_index] = heap_usage;
2088 }
2089 }
2090
2091 /* The heapBudget and heapUsage values must be zero for array elements
2092 * greater than or equal to
2093 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2094 */
2095 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
2096 memoryBudget->heapBudget[i] = 0;
2097 memoryBudget->heapUsage[i] = 0;
2098 }
2099 }
2100
2101 void radv_GetPhysicalDeviceMemoryProperties2(
2102 VkPhysicalDevice physicalDevice,
2103 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
2104 {
2105 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
2106 &pMemoryProperties->memoryProperties);
2107
2108 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
2109 vk_find_struct(pMemoryProperties->pNext,
2110 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
2111 if (memory_budget)
2112 radv_get_memory_budget_properties(physicalDevice, memory_budget);
2113 }
2114
2115 VkResult radv_GetMemoryHostPointerPropertiesEXT(
2116 VkDevice _device,
2117 VkExternalMemoryHandleTypeFlagBits handleType,
2118 const void *pHostPointer,
2119 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
2120 {
2121 RADV_FROM_HANDLE(radv_device, device, _device);
2122
2123 switch (handleType)
2124 {
2125 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
2126 const struct radv_physical_device *physical_device = device->physical_device;
2127 uint32_t memoryTypeBits = 0;
2128 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
2129 if (radv_is_mem_type_gtt_cached(physical_device->mem_type_indices[i])) {
2130 memoryTypeBits = (1 << i);
2131 break;
2132 }
2133 }
2134 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
2135 return VK_SUCCESS;
2136 }
2137 default:
2138 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
2139 }
2140 }
2141
2142 static enum radeon_ctx_priority
2143 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
2144 {
2145 /* Default to MEDIUM when a specific global priority isn't requested */
2146 if (!pObj)
2147 return RADEON_CTX_PRIORITY_MEDIUM;
2148
2149 switch(pObj->globalPriority) {
2150 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
2151 return RADEON_CTX_PRIORITY_REALTIME;
2152 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
2153 return RADEON_CTX_PRIORITY_HIGH;
2154 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
2155 return RADEON_CTX_PRIORITY_MEDIUM;
2156 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
2157 return RADEON_CTX_PRIORITY_LOW;
2158 default:
2159 unreachable("Illegal global priority value");
2160 return RADEON_CTX_PRIORITY_INVALID;
2161 }
2162 }
2163
2164 static int
2165 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
2166 uint32_t queue_family_index, int idx,
2167 VkDeviceQueueCreateFlags flags,
2168 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
2169 {
2170 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2171 queue->device = device;
2172 queue->queue_family_index = queue_family_index;
2173 queue->queue_idx = idx;
2174 queue->priority = radv_get_queue_global_priority(global_priority);
2175 queue->flags = flags;
2176
2177 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
2178 if (!queue->hw_ctx)
2179 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2180
2181 list_inithead(&queue->pending_submissions);
2182 pthread_mutex_init(&queue->pending_mutex, NULL);
2183
2184 return VK_SUCCESS;
2185 }
2186
2187 static void
2188 radv_queue_finish(struct radv_queue *queue)
2189 {
2190 pthread_mutex_destroy(&queue->pending_mutex);
2191
2192 if (queue->hw_ctx)
2193 queue->device->ws->ctx_destroy(queue->hw_ctx);
2194
2195 if (queue->initial_full_flush_preamble_cs)
2196 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2197 if (queue->initial_preamble_cs)
2198 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2199 if (queue->continue_preamble_cs)
2200 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2201 if (queue->descriptor_bo)
2202 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2203 if (queue->scratch_bo)
2204 queue->device->ws->buffer_destroy(queue->scratch_bo);
2205 if (queue->esgs_ring_bo)
2206 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2207 if (queue->gsvs_ring_bo)
2208 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2209 if (queue->tess_rings_bo)
2210 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
2211 if (queue->gds_bo)
2212 queue->device->ws->buffer_destroy(queue->gds_bo);
2213 if (queue->gds_oa_bo)
2214 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
2215 if (queue->compute_scratch_bo)
2216 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2217 }
2218
2219 static void
2220 radv_bo_list_init(struct radv_bo_list *bo_list)
2221 {
2222 pthread_mutex_init(&bo_list->mutex, NULL);
2223 bo_list->list.count = bo_list->capacity = 0;
2224 bo_list->list.bos = NULL;
2225 }
2226
2227 static void
2228 radv_bo_list_finish(struct radv_bo_list *bo_list)
2229 {
2230 free(bo_list->list.bos);
2231 pthread_mutex_destroy(&bo_list->mutex);
2232 }
2233
2234 static VkResult radv_bo_list_add(struct radv_device *device,
2235 struct radeon_winsys_bo *bo)
2236 {
2237 struct radv_bo_list *bo_list = &device->bo_list;
2238
2239 if (bo->is_local)
2240 return VK_SUCCESS;
2241
2242 if (unlikely(!device->use_global_bo_list))
2243 return VK_SUCCESS;
2244
2245 pthread_mutex_lock(&bo_list->mutex);
2246 if (bo_list->list.count == bo_list->capacity) {
2247 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2248 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2249
2250 if (!data) {
2251 pthread_mutex_unlock(&bo_list->mutex);
2252 return VK_ERROR_OUT_OF_HOST_MEMORY;
2253 }
2254
2255 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2256 bo_list->capacity = capacity;
2257 }
2258
2259 bo_list->list.bos[bo_list->list.count++] = bo;
2260 pthread_mutex_unlock(&bo_list->mutex);
2261 return VK_SUCCESS;
2262 }
2263
2264 static void radv_bo_list_remove(struct radv_device *device,
2265 struct radeon_winsys_bo *bo)
2266 {
2267 struct radv_bo_list *bo_list = &device->bo_list;
2268
2269 if (bo->is_local)
2270 return;
2271
2272 if (unlikely(!device->use_global_bo_list))
2273 return;
2274
2275 pthread_mutex_lock(&bo_list->mutex);
2276 for(unsigned i = 0; i < bo_list->list.count; ++i) {
2277 if (bo_list->list.bos[i] == bo) {
2278 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2279 --bo_list->list.count;
2280 break;
2281 }
2282 }
2283 pthread_mutex_unlock(&bo_list->mutex);
2284 }
2285
2286 static void
2287 radv_device_init_gs_info(struct radv_device *device)
2288 {
2289 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2290 device->physical_device->rad_info.family);
2291 }
2292
2293 static int radv_get_device_extension_index(const char *name)
2294 {
2295 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2296 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2297 return i;
2298 }
2299 return -1;
2300 }
2301
2302 static int
2303 radv_get_int_debug_option(const char *name, int default_value)
2304 {
2305 const char *str;
2306 int result;
2307
2308 str = getenv(name);
2309 if (!str) {
2310 result = default_value;
2311 } else {
2312 char *endptr;
2313
2314 result = strtol(str, &endptr, 0);
2315 if (str == endptr) {
2316 /* No digits founs. */
2317 result = default_value;
2318 }
2319 }
2320
2321 return result;
2322 }
2323
2324 static int install_seccomp_filter() {
2325
2326 struct sock_filter filter[] = {
2327 /* Check arch is 64bit x86 */
2328 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2329 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2330
2331 /* Futex is required for mutex locks */
2332 #if defined __NR__newselect
2333 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2334 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2335 #elif defined __NR_select
2336 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2337 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2338 #else
2339 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2340 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2341 #endif
2342
2343 /* Allow system exit calls for the forked process */
2344 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2345 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2346
2347 /* Allow system read calls */
2348 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2349 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2350
2351 /* Allow system write calls */
2352 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2353 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2354
2355 /* Allow system brk calls (we need this for malloc) */
2356 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2357 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2358
2359 /* Futex is required for mutex locks */
2360 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2361 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2362
2363 /* Return error if we hit a system call not on the whitelist */
2364 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2365
2366 /* Allow whitelisted system calls */
2367 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2368 };
2369
2370 struct sock_fprog prog = {
2371 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2372 .filter = filter,
2373 };
2374
2375 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2376 return -1;
2377
2378 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2379 return -1;
2380
2381 return 0;
2382 }
2383
2384 /* Helper function with timeout support for reading from the pipe between
2385 * processes used for secure compile.
2386 */
2387 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2388 {
2389 fd_set fds;
2390 struct timeval tv;
2391
2392 FD_ZERO(&fds);
2393 FD_SET(fd, &fds);
2394
2395 while (true) {
2396 /* We can't rely on the value of tv after calling select() so
2397 * we must reset it on each iteration of the loop.
2398 */
2399 tv.tv_sec = 5;
2400 tv.tv_usec = 0;
2401
2402 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2403
2404 if (rval == -1) {
2405 /* select error */
2406 return false;
2407 } else if (rval) {
2408 ssize_t bytes_read = read(fd, buf, size);
2409 if (bytes_read < 0)
2410 return false;
2411
2412 buf += bytes_read;
2413 size -= bytes_read;
2414 if (size == 0)
2415 return true;
2416 } else {
2417 /* select timeout */
2418 return false;
2419 }
2420 }
2421 }
2422
2423 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2424 {
2425 DIR *d;
2426 struct dirent *dir;
2427 d = opendir("/proc/self/fd");
2428 if (!d)
2429 return false;
2430 int dir_fd = dirfd(d);
2431
2432 while ((dir = readdir(d)) != NULL) {
2433 if (dir->d_name[0] == '.')
2434 continue;
2435
2436 int fd = atoi(dir->d_name);
2437 if (fd == dir_fd)
2438 continue;
2439
2440 bool keep = false;
2441 for (int i = 0; !keep && i < keep_fd_count; ++i)
2442 if (keep_fds[i] == fd)
2443 keep = true;
2444
2445 if (keep)
2446 continue;
2447
2448 close(fd);
2449 }
2450 closedir(d);
2451 return true;
2452 }
2453
2454 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2455 int *fd_server, int *fd_client,
2456 unsigned process, bool make_fifo)
2457 {
2458 bool result = false;
2459 char *fifo_server_path = NULL;
2460 char *fifo_client_path = NULL;
2461
2462 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2463 goto open_fifo_exit;
2464
2465 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2466 goto open_fifo_exit;
2467
2468 if (make_fifo) {
2469 int file1 = mkfifo(fifo_server_path, 0666);
2470 if(file1 < 0)
2471 goto open_fifo_exit;
2472
2473 int file2 = mkfifo(fifo_client_path, 0666);
2474 if(file2 < 0)
2475 goto open_fifo_exit;
2476 }
2477
2478 *fd_server = open(fifo_server_path, O_RDWR);
2479 if(*fd_server < 1)
2480 goto open_fifo_exit;
2481
2482 *fd_client = open(fifo_client_path, O_RDWR);
2483 if(*fd_client < 1) {
2484 close(*fd_server);
2485 goto open_fifo_exit;
2486 }
2487
2488 result = true;
2489
2490 open_fifo_exit:
2491 free(fifo_server_path);
2492 free(fifo_client_path);
2493
2494 return result;
2495 }
2496
2497 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2498 int fd_idle_device_output)
2499 {
2500 int fd_secure_input;
2501 int fd_secure_output;
2502 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2503 &fd_secure_input,
2504 &fd_secure_output,
2505 process, false);
2506
2507 enum radv_secure_compile_type sc_type;
2508
2509 const int needed_fds[] = {
2510 fd_secure_input,
2511 fd_secure_output,
2512 fd_idle_device_output,
2513 };
2514
2515 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2516 install_seccomp_filter() == -1) {
2517 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2518 } else {
2519 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2520 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2521 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2522 }
2523
2524 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2525
2526 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2527 goto secure_compile_exit;
2528
2529 while (true) {
2530 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2531
2532 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2533 struct radv_pipeline *pipeline;
2534 bool sc_read = true;
2535
2536 pipeline = vk_zalloc2(&device->alloc, NULL, sizeof(*pipeline), 8,
2537 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2538
2539 pipeline->device = device;
2540
2541 /* Read pipeline layout */
2542 struct radv_pipeline_layout layout;
2543 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2544 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2545 if (!sc_read)
2546 goto secure_compile_exit;
2547
2548 for (uint32_t set = 0; set < layout.num_sets; set++) {
2549 uint32_t layout_size;
2550 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2551 if (!sc_read)
2552 goto secure_compile_exit;
2553
2554 layout.set[set].layout = malloc(layout_size);
2555 layout.set[set].layout->layout_size = layout_size;
2556 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2557 layout.set[set].layout->layout_size, true);
2558 }
2559
2560 pipeline->layout = &layout;
2561
2562 /* Read pipeline key */
2563 struct radv_pipeline_key key;
2564 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2565
2566 /* Read pipeline create flags */
2567 VkPipelineCreateFlags flags;
2568 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2569
2570 /* Read stage and shader information */
2571 uint32_t num_stages;
2572 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2573 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2574 if (!sc_read)
2575 goto secure_compile_exit;
2576
2577 for (uint32_t i = 0; i < num_stages; i++) {
2578
2579 /* Read stage */
2580 gl_shader_stage stage;
2581 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2582
2583 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2584
2585 /* Read entry point name */
2586 size_t name_size;
2587 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2588 if (!sc_read)
2589 goto secure_compile_exit;
2590
2591 char *ep_name = malloc(name_size);
2592 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2593 pStage->pName = ep_name;
2594
2595 /* Read shader module */
2596 size_t module_size;
2597 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2598 if (!sc_read)
2599 goto secure_compile_exit;
2600
2601 struct radv_shader_module *module = malloc(module_size);
2602 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2603 pStage->module = radv_shader_module_to_handle(module);
2604
2605 /* Read specialization info */
2606 bool has_spec_info;
2607 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2608 if (!sc_read)
2609 goto secure_compile_exit;
2610
2611 if (has_spec_info) {
2612 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2613 pStage->pSpecializationInfo = specInfo;
2614
2615 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2616 if (!sc_read)
2617 goto secure_compile_exit;
2618
2619 void *si_data = malloc(specInfo->dataSize);
2620 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2621 specInfo->pData = si_data;
2622
2623 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2624 if (!sc_read)
2625 goto secure_compile_exit;
2626
2627 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2628 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2629 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2630 if (!sc_read)
2631 goto secure_compile_exit;
2632 }
2633
2634 specInfo->pMapEntries = mapEntries;
2635 }
2636
2637 pStages[stage] = pStage;
2638 }
2639
2640 /* Compile the shaders */
2641 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2642 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2643
2644 /* free memory allocated above */
2645 for (uint32_t set = 0; set < layout.num_sets; set++)
2646 free(layout.set[set].layout);
2647
2648 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2649 if (!pStages[i])
2650 continue;
2651
2652 free((void *) pStages[i]->pName);
2653 free(radv_shader_module_from_handle(pStages[i]->module));
2654 if (pStages[i]->pSpecializationInfo) {
2655 free((void *) pStages[i]->pSpecializationInfo->pData);
2656 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2657 free((void *) pStages[i]->pSpecializationInfo);
2658 }
2659 free((void *) pStages[i]);
2660 }
2661
2662 vk_free(&device->alloc, pipeline);
2663
2664 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2665 write(fd_secure_output, &sc_type, sizeof(sc_type));
2666
2667 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2668 goto secure_compile_exit;
2669 }
2670 }
2671
2672 secure_compile_exit:
2673 close(fd_secure_input);
2674 close(fd_secure_output);
2675 close(fd_idle_device_output);
2676 _exit(0);
2677 }
2678
2679 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2680 {
2681 int fd_secure_input[2];
2682 int fd_secure_output[2];
2683
2684 /* create pipe descriptors (used to communicate between processes) */
2685 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2686 return RADV_SC_TYPE_INIT_FAILURE;
2687
2688
2689 int sc_pid;
2690 if ((sc_pid = fork()) == 0) {
2691 device->sc_state->secure_compile_thread_counter = process;
2692 run_secure_compile_device(device, process, fd_secure_output[1]);
2693 } else {
2694 if (sc_pid == -1)
2695 return RADV_SC_TYPE_INIT_FAILURE;
2696
2697 /* Read the init result returned from the secure process */
2698 enum radv_secure_compile_type sc_type;
2699 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2700
2701 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2702 close(fd_secure_input[0]);
2703 close(fd_secure_input[1]);
2704 close(fd_secure_output[1]);
2705 close(fd_secure_output[0]);
2706 int status;
2707 waitpid(sc_pid, &status, 0);
2708
2709 return RADV_SC_TYPE_INIT_FAILURE;
2710 } else {
2711 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2712 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2713
2714 close(fd_secure_input[0]);
2715 close(fd_secure_input[1]);
2716 close(fd_secure_output[1]);
2717 close(fd_secure_output[0]);
2718
2719 int status;
2720 waitpid(sc_pid, &status, 0);
2721 }
2722 }
2723
2724 return RADV_SC_TYPE_INIT_SUCCESS;
2725 }
2726
2727 /* Run a bare bones fork of a device that was forked right after its creation.
2728 * This device will have low overhead when it is forked again before each
2729 * pipeline compilation. This device sits idle and its only job is to fork
2730 * itself.
2731 */
2732 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2733 int fd_secure_input, int fd_secure_output)
2734 {
2735 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2736 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2737 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2738
2739 write(fd_secure_output, &sc_type, sizeof(sc_type));
2740
2741 while (true) {
2742 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2743
2744 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2745 sc_type = fork_secure_compile_device(device, process);
2746
2747 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2748 goto secure_compile_exit;
2749
2750 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2751 goto secure_compile_exit;
2752 }
2753 }
2754
2755 secure_compile_exit:
2756 close(fd_secure_input);
2757 close(fd_secure_output);
2758 _exit(0);
2759 }
2760
2761 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2762 {
2763 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2764
2765 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2766 write(fd_secure_input, &sc_type, sizeof(sc_type));
2767
2768 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2769 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2770
2771 int status;
2772 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2773 }
2774
2775 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2776 {
2777 device->sc_state = vk_zalloc(&device->alloc,
2778 sizeof(struct radv_secure_compile_state),
2779 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2780
2781 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2782
2783 pid_t upid = getpid();
2784 time_t seconds = time(NULL);
2785
2786 char *uid;
2787 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2788 return VK_ERROR_INITIALIZATION_FAILED;
2789
2790 device->sc_state->uid = uid;
2791
2792 uint8_t sc_threads = device->instance->num_sc_threads;
2793 int fd_secure_input[MAX_SC_PROCS][2];
2794 int fd_secure_output[MAX_SC_PROCS][2];
2795
2796 /* create pipe descriptors (used to communicate between processes) */
2797 for (unsigned i = 0; i < sc_threads; i++) {
2798 if (pipe(fd_secure_input[i]) == -1 ||
2799 pipe(fd_secure_output[i]) == -1) {
2800 return VK_ERROR_INITIALIZATION_FAILED;
2801 }
2802 }
2803
2804 device->sc_state->secure_compile_processes = vk_zalloc(&device->alloc,
2805 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2806 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2807
2808 for (unsigned process = 0; process < sc_threads; process++) {
2809 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2810 device->sc_state->secure_compile_thread_counter = process;
2811 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2812 } else {
2813 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2814 return VK_ERROR_INITIALIZATION_FAILED;
2815
2816 /* Read the init result returned from the secure process */
2817 enum radv_secure_compile_type sc_type;
2818 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2819
2820 bool fifo_result;
2821 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2822 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2823 &device->sc_state->secure_compile_processes[process].fd_server,
2824 &device->sc_state->secure_compile_processes[process].fd_client,
2825 process, true);
2826
2827 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2828 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2829 }
2830
2831 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2832 close(fd_secure_input[process][0]);
2833 close(fd_secure_input[process][1]);
2834 close(fd_secure_output[process][1]);
2835 close(fd_secure_output[process][0]);
2836 int status;
2837 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2838
2839 /* Destroy any forks that were created sucessfully */
2840 for (unsigned i = 0; i < process; i++) {
2841 destroy_secure_compile_device(device, i);
2842 }
2843
2844 return VK_ERROR_INITIALIZATION_FAILED;
2845 }
2846 }
2847 }
2848 return VK_SUCCESS;
2849 }
2850
2851 static void
2852 radv_device_init_dispatch(struct radv_device *device)
2853 {
2854 const struct radv_instance *instance = device->physical_device->instance;
2855 const struct radv_device_dispatch_table *dispatch_table_layer = NULL;
2856 bool unchecked = instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS;
2857 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2858
2859 if (radv_thread_trace >= 0) {
2860 /* Use device entrypoints from the SQTT layer if enabled. */
2861 dispatch_table_layer = &sqtt_device_dispatch_table;
2862 }
2863
2864 for (unsigned i = 0; i < ARRAY_SIZE(device->dispatch.entrypoints); i++) {
2865 /* Vulkan requires that entrypoints for extensions which have not been
2866 * enabled must not be advertised.
2867 */
2868 if (!unchecked &&
2869 !radv_device_entrypoint_is_enabled(i, instance->apiVersion,
2870 &instance->enabled_extensions,
2871 &device->enabled_extensions)) {
2872 device->dispatch.entrypoints[i] = NULL;
2873 } else if (dispatch_table_layer &&
2874 dispatch_table_layer->entrypoints[i]) {
2875 device->dispatch.entrypoints[i] =
2876 dispatch_table_layer->entrypoints[i];
2877 } else {
2878 device->dispatch.entrypoints[i] =
2879 radv_device_dispatch_table.entrypoints[i];
2880 }
2881 }
2882 }
2883
2884 static VkResult
2885 radv_create_pthread_cond(pthread_cond_t *cond)
2886 {
2887 pthread_condattr_t condattr;
2888 if (pthread_condattr_init(&condattr)) {
2889 return VK_ERROR_INITIALIZATION_FAILED;
2890 }
2891
2892 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2893 pthread_condattr_destroy(&condattr);
2894 return VK_ERROR_INITIALIZATION_FAILED;
2895 }
2896 if (pthread_cond_init(cond, &condattr)) {
2897 pthread_condattr_destroy(&condattr);
2898 return VK_ERROR_INITIALIZATION_FAILED;
2899 }
2900 pthread_condattr_destroy(&condattr);
2901 return VK_SUCCESS;
2902 }
2903
2904 VkResult radv_CreateDevice(
2905 VkPhysicalDevice physicalDevice,
2906 const VkDeviceCreateInfo* pCreateInfo,
2907 const VkAllocationCallbacks* pAllocator,
2908 VkDevice* pDevice)
2909 {
2910 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2911 VkResult result;
2912 struct radv_device *device;
2913
2914 bool keep_shader_info = false;
2915
2916 /* Check enabled features */
2917 if (pCreateInfo->pEnabledFeatures) {
2918 VkPhysicalDeviceFeatures supported_features;
2919 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2920 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2921 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
2922 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2923 for (uint32_t i = 0; i < num_features; i++) {
2924 if (enabled_feature[i] && !supported_feature[i])
2925 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2926 }
2927 }
2928
2929 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2930 sizeof(*device), 8,
2931 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2932 if (!device)
2933 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2934
2935 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2936 device->instance = physical_device->instance;
2937 device->physical_device = physical_device;
2938
2939 device->ws = physical_device->ws;
2940 if (pAllocator)
2941 device->alloc = *pAllocator;
2942 else
2943 device->alloc = physical_device->instance->alloc;
2944
2945 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2946 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2947 int index = radv_get_device_extension_index(ext_name);
2948 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2949 vk_free(&device->alloc, device);
2950 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2951 }
2952
2953 device->enabled_extensions.extensions[index] = true;
2954 }
2955
2956 radv_device_init_dispatch(device);
2957
2958 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2959
2960 /* With update after bind we can't attach bo's to the command buffer
2961 * from the descriptor set anymore, so we have to use a global BO list.
2962 */
2963 device->use_global_bo_list =
2964 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2965 device->enabled_extensions.EXT_descriptor_indexing ||
2966 device->enabled_extensions.EXT_buffer_device_address ||
2967 device->enabled_extensions.KHR_buffer_device_address;
2968
2969 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
2970 pCreateInfo->pEnabledFeatures->robustBufferAccess;
2971
2972 mtx_init(&device->shader_slab_mutex, mtx_plain);
2973 list_inithead(&device->shader_slabs);
2974
2975 radv_bo_list_init(&device->bo_list);
2976
2977 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2978 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2979 uint32_t qfi = queue_create->queueFamilyIndex;
2980 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2981 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2982
2983 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2984
2985 device->queues[qfi] = vk_alloc(&device->alloc,
2986 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2987 if (!device->queues[qfi]) {
2988 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2989 goto fail;
2990 }
2991
2992 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2993
2994 device->queue_count[qfi] = queue_create->queueCount;
2995
2996 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2997 result = radv_queue_init(device, &device->queues[qfi][q],
2998 qfi, q, queue_create->flags,
2999 global_priority);
3000 if (result != VK_SUCCESS)
3001 goto fail;
3002 }
3003 }
3004
3005 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
3006 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
3007
3008 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
3009 device->dfsm_allowed = device->pbb_allowed &&
3010 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
3011
3012 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
3013
3014 /* The maximum number of scratch waves. Scratch space isn't divided
3015 * evenly between CUs. The number is only a function of the number of CUs.
3016 * We can decrease the constant to decrease the scratch buffer size.
3017 *
3018 * sctx->scratch_waves must be >= the maximum possible size of
3019 * 1 threadgroup, so that the hw doesn't hang from being unable
3020 * to start any.
3021 *
3022 * The recommended value is 4 per CU at most. Higher numbers don't
3023 * bring much benefit, but they still occupy chip resources (think
3024 * async compute). I've seen ~2% performance difference between 4 and 32.
3025 */
3026 uint32_t max_threads_per_block = 2048;
3027 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
3028 max_threads_per_block / 64);
3029
3030 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
3031
3032 if (device->physical_device->rad_info.chip_class >= GFX7) {
3033 /* If the KMD allows it (there is a KMD hw register for it),
3034 * allow launching waves out-of-order.
3035 */
3036 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
3037 }
3038
3039 radv_device_init_gs_info(device);
3040
3041 device->tess_offchip_block_dw_size =
3042 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
3043
3044 if (getenv("RADV_TRACE_FILE")) {
3045 const char *filename = getenv("RADV_TRACE_FILE");
3046
3047 keep_shader_info = true;
3048
3049 if (!radv_init_trace(device))
3050 goto fail;
3051
3052 fprintf(stderr, "*****************************************************************************\n");
3053 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
3054 fprintf(stderr, "*****************************************************************************\n");
3055
3056 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
3057 radv_dump_enabled_options(device, stderr);
3058 }
3059
3060 int radv_thread_trace = radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
3061 if (radv_thread_trace >= 0) {
3062 fprintf(stderr, "*************************************************\n");
3063 fprintf(stderr, "* WARNING: Thread trace support is experimental *\n");
3064 fprintf(stderr, "*************************************************\n");
3065
3066 if (device->physical_device->rad_info.chip_class < GFX8) {
3067 fprintf(stderr, "GPU hardware not supported: refer to "
3068 "the RGP documentation for the list of "
3069 "supported GPUs!\n");
3070 abort();
3071 }
3072
3073 /* Default buffer size set to 1MB per SE. */
3074 device->thread_trace_buffer_size =
3075 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
3076 device->thread_trace_start_frame = radv_thread_trace;
3077
3078 if (!radv_thread_trace_init(device))
3079 goto fail;
3080 }
3081
3082 /* Temporarily disable secure compile while we create meta shaders, etc */
3083 uint8_t sc_threads = device->instance->num_sc_threads;
3084 if (sc_threads)
3085 device->instance->num_sc_threads = 0;
3086
3087 device->keep_shader_info = keep_shader_info;
3088 result = radv_device_init_meta(device);
3089 if (result != VK_SUCCESS)
3090 goto fail;
3091
3092 radv_device_init_msaa(device);
3093
3094 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
3095 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
3096 switch (family) {
3097 case RADV_QUEUE_GENERAL:
3098 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
3099 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
3100 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
3101 break;
3102 case RADV_QUEUE_COMPUTE:
3103 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
3104 radeon_emit(device->empty_cs[family], 0);
3105 break;
3106 }
3107 device->ws->cs_finalize(device->empty_cs[family]);
3108 }
3109
3110 if (device->physical_device->rad_info.chip_class >= GFX7)
3111 cik_create_gfx_config(device);
3112
3113 VkPipelineCacheCreateInfo ci;
3114 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
3115 ci.pNext = NULL;
3116 ci.flags = 0;
3117 ci.pInitialData = NULL;
3118 ci.initialDataSize = 0;
3119 VkPipelineCache pc;
3120 result = radv_CreatePipelineCache(radv_device_to_handle(device),
3121 &ci, NULL, &pc);
3122 if (result != VK_SUCCESS)
3123 goto fail_meta;
3124
3125 device->mem_cache = radv_pipeline_cache_from_handle(pc);
3126
3127 result = radv_create_pthread_cond(&device->timeline_cond);
3128 if (result != VK_SUCCESS)
3129 goto fail_mem_cache;
3130
3131 device->force_aniso =
3132 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
3133 if (device->force_aniso >= 0) {
3134 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
3135 1 << util_logbase2(device->force_aniso));
3136 }
3137
3138 /* Fork device for secure compile as required */
3139 device->instance->num_sc_threads = sc_threads;
3140 if (radv_device_use_secure_compile(device->instance)) {
3141
3142 result = fork_secure_compile_idle_device(device);
3143 if (result != VK_SUCCESS)
3144 goto fail_meta;
3145 }
3146
3147 *pDevice = radv_device_to_handle(device);
3148 return VK_SUCCESS;
3149
3150 fail_mem_cache:
3151 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
3152 fail_meta:
3153 radv_device_finish_meta(device);
3154 fail:
3155 radv_bo_list_finish(&device->bo_list);
3156
3157 radv_thread_trace_finish(device);
3158
3159 if (device->trace_bo)
3160 device->ws->buffer_destroy(device->trace_bo);
3161
3162 if (device->gfx_init)
3163 device->ws->buffer_destroy(device->gfx_init);
3164
3165 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3166 for (unsigned q = 0; q < device->queue_count[i]; q++)
3167 radv_queue_finish(&device->queues[i][q]);
3168 if (device->queue_count[i])
3169 vk_free(&device->alloc, device->queues[i]);
3170 }
3171
3172 vk_free(&device->alloc, device);
3173 return result;
3174 }
3175
3176 void radv_DestroyDevice(
3177 VkDevice _device,
3178 const VkAllocationCallbacks* pAllocator)
3179 {
3180 RADV_FROM_HANDLE(radv_device, device, _device);
3181
3182 if (!device)
3183 return;
3184
3185 if (device->trace_bo)
3186 device->ws->buffer_destroy(device->trace_bo);
3187
3188 if (device->gfx_init)
3189 device->ws->buffer_destroy(device->gfx_init);
3190
3191 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3192 for (unsigned q = 0; q < device->queue_count[i]; q++)
3193 radv_queue_finish(&device->queues[i][q]);
3194 if (device->queue_count[i])
3195 vk_free(&device->alloc, device->queues[i]);
3196 if (device->empty_cs[i])
3197 device->ws->cs_destroy(device->empty_cs[i]);
3198 }
3199 radv_device_finish_meta(device);
3200
3201 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
3202 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
3203
3204 radv_destroy_shader_slabs(device);
3205
3206 pthread_cond_destroy(&device->timeline_cond);
3207 radv_bo_list_finish(&device->bo_list);
3208
3209 radv_thread_trace_finish(device);
3210
3211 if (radv_device_use_secure_compile(device->instance)) {
3212 for (unsigned i = 0; i < device->instance->num_sc_threads; i++ ) {
3213 destroy_secure_compile_device(device, i);
3214 }
3215 }
3216
3217 if (device->sc_state) {
3218 free(device->sc_state->uid);
3219 vk_free(&device->alloc, device->sc_state->secure_compile_processes);
3220 }
3221 vk_free(&device->alloc, device->sc_state);
3222 vk_free(&device->alloc, device);
3223 }
3224
3225 VkResult radv_EnumerateInstanceLayerProperties(
3226 uint32_t* pPropertyCount,
3227 VkLayerProperties* pProperties)
3228 {
3229 if (pProperties == NULL) {
3230 *pPropertyCount = 0;
3231 return VK_SUCCESS;
3232 }
3233
3234 /* None supported at this time */
3235 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3236 }
3237
3238 VkResult radv_EnumerateDeviceLayerProperties(
3239 VkPhysicalDevice physicalDevice,
3240 uint32_t* pPropertyCount,
3241 VkLayerProperties* pProperties)
3242 {
3243 if (pProperties == NULL) {
3244 *pPropertyCount = 0;
3245 return VK_SUCCESS;
3246 }
3247
3248 /* None supported at this time */
3249 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
3250 }
3251
3252 void radv_GetDeviceQueue2(
3253 VkDevice _device,
3254 const VkDeviceQueueInfo2* pQueueInfo,
3255 VkQueue* pQueue)
3256 {
3257 RADV_FROM_HANDLE(radv_device, device, _device);
3258 struct radv_queue *queue;
3259
3260 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
3261 if (pQueueInfo->flags != queue->flags) {
3262 /* From the Vulkan 1.1.70 spec:
3263 *
3264 * "The queue returned by vkGetDeviceQueue2 must have the same
3265 * flags value from this structure as that used at device
3266 * creation time in a VkDeviceQueueCreateInfo instance. If no
3267 * matching flags were specified at device creation time then
3268 * pQueue will return VK_NULL_HANDLE."
3269 */
3270 *pQueue = VK_NULL_HANDLE;
3271 return;
3272 }
3273
3274 *pQueue = radv_queue_to_handle(queue);
3275 }
3276
3277 void radv_GetDeviceQueue(
3278 VkDevice _device,
3279 uint32_t queueFamilyIndex,
3280 uint32_t queueIndex,
3281 VkQueue* pQueue)
3282 {
3283 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
3284 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
3285 .queueFamilyIndex = queueFamilyIndex,
3286 .queueIndex = queueIndex
3287 };
3288
3289 radv_GetDeviceQueue2(_device, &info, pQueue);
3290 }
3291
3292 static void
3293 fill_geom_tess_rings(struct radv_queue *queue,
3294 uint32_t *map,
3295 bool add_sample_positions,
3296 uint32_t esgs_ring_size,
3297 struct radeon_winsys_bo *esgs_ring_bo,
3298 uint32_t gsvs_ring_size,
3299 struct radeon_winsys_bo *gsvs_ring_bo,
3300 uint32_t tess_factor_ring_size,
3301 uint32_t tess_offchip_ring_offset,
3302 uint32_t tess_offchip_ring_size,
3303 struct radeon_winsys_bo *tess_rings_bo)
3304 {
3305 uint32_t *desc = &map[4];
3306
3307 if (esgs_ring_bo) {
3308 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3309
3310 /* stride 0, num records - size, add tid, swizzle, elsize4,
3311 index stride 64 */
3312 desc[0] = esgs_va;
3313 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3314 S_008F04_SWIZZLE_ENABLE(true);
3315 desc[2] = esgs_ring_size;
3316 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3317 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3318 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3319 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3320 S_008F0C_INDEX_STRIDE(3) |
3321 S_008F0C_ADD_TID_ENABLE(1);
3322
3323 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3324 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3325 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3326 S_008F0C_RESOURCE_LEVEL(1);
3327 } else {
3328 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3329 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3330 S_008F0C_ELEMENT_SIZE(1);
3331 }
3332
3333 /* GS entry for ES->GS ring */
3334 /* stride 0, num records - size, elsize0,
3335 index stride 0 */
3336 desc[4] = esgs_va;
3337 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3338 desc[6] = esgs_ring_size;
3339 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3340 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3341 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3342 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3343
3344 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3345 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3346 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3347 S_008F0C_RESOURCE_LEVEL(1);
3348 } else {
3349 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3350 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3351 }
3352 }
3353
3354 desc += 8;
3355
3356 if (gsvs_ring_bo) {
3357 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3358
3359 /* VS entry for GS->VS ring */
3360 /* stride 0, num records - size, elsize0,
3361 index stride 0 */
3362 desc[0] = gsvs_va;
3363 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3364 desc[2] = gsvs_ring_size;
3365 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3366 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3367 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3368 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3369
3370 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3371 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3372 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3373 S_008F0C_RESOURCE_LEVEL(1);
3374 } else {
3375 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3376 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3377 }
3378
3379 /* stride gsvs_itemsize, num records 64
3380 elsize 4, index stride 16 */
3381 /* shader will patch stride and desc[2] */
3382 desc[4] = gsvs_va;
3383 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3384 S_008F04_SWIZZLE_ENABLE(1);
3385 desc[6] = 0;
3386 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3387 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3388 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3389 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3390 S_008F0C_INDEX_STRIDE(1) |
3391 S_008F0C_ADD_TID_ENABLE(true);
3392
3393 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3394 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3395 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED) |
3396 S_008F0C_RESOURCE_LEVEL(1);
3397 } else {
3398 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3399 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3400 S_008F0C_ELEMENT_SIZE(1);
3401 }
3402
3403 }
3404
3405 desc += 8;
3406
3407 if (tess_rings_bo) {
3408 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3409 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3410
3411 desc[0] = tess_va;
3412 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3413 desc[2] = tess_factor_ring_size;
3414 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3415 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3416 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3417 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3418
3419 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3420 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3421 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3422 S_008F0C_RESOURCE_LEVEL(1);
3423 } else {
3424 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3425 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3426 }
3427
3428 desc[4] = tess_offchip_va;
3429 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3430 desc[6] = tess_offchip_ring_size;
3431 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3432 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3433 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3434 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3435
3436 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3437 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3438 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
3439 S_008F0C_RESOURCE_LEVEL(1);
3440 } else {
3441 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3442 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3443 }
3444 }
3445
3446 desc += 8;
3447
3448 if (add_sample_positions) {
3449 /* add sample positions after all rings */
3450 memcpy(desc, queue->device->sample_locations_1x, 8);
3451 desc += 2;
3452 memcpy(desc, queue->device->sample_locations_2x, 16);
3453 desc += 4;
3454 memcpy(desc, queue->device->sample_locations_4x, 32);
3455 desc += 8;
3456 memcpy(desc, queue->device->sample_locations_8x, 64);
3457 }
3458 }
3459
3460 static unsigned
3461 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3462 {
3463 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3464 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3465 device->physical_device->rad_info.family != CHIP_STONEY;
3466 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3467 unsigned max_offchip_buffers;
3468 unsigned offchip_granularity;
3469 unsigned hs_offchip_param;
3470
3471 /*
3472 * Per RadeonSI:
3473 * This must be one less than the maximum number due to a hw limitation.
3474 * Various hardware bugs need thGFX7
3475 *
3476 * Per AMDVLK:
3477 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3478 * Gfx7 should limit max_offchip_buffers to 508
3479 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3480 *
3481 * Follow AMDVLK here.
3482 */
3483 if (device->physical_device->rad_info.chip_class >= GFX10) {
3484 max_offchip_buffers_per_se = 256;
3485 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3486 device->physical_device->rad_info.chip_class == GFX7 ||
3487 device->physical_device->rad_info.chip_class == GFX6)
3488 --max_offchip_buffers_per_se;
3489
3490 max_offchip_buffers = max_offchip_buffers_per_se *
3491 device->physical_device->rad_info.max_se;
3492
3493 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3494 * around by setting 4K granularity.
3495 */
3496 if (device->tess_offchip_block_dw_size == 4096) {
3497 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3498 offchip_granularity = V_03093C_X_4K_DWORDS;
3499 } else {
3500 assert(device->tess_offchip_block_dw_size == 8192);
3501 offchip_granularity = V_03093C_X_8K_DWORDS;
3502 }
3503
3504 switch (device->physical_device->rad_info.chip_class) {
3505 case GFX6:
3506 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3507 break;
3508 case GFX7:
3509 case GFX8:
3510 case GFX9:
3511 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3512 break;
3513 case GFX10:
3514 break;
3515 default:
3516 break;
3517 }
3518
3519 *max_offchip_buffers_p = max_offchip_buffers;
3520 if (device->physical_device->rad_info.chip_class >= GFX7) {
3521 if (device->physical_device->rad_info.chip_class >= GFX8)
3522 --max_offchip_buffers;
3523 hs_offchip_param =
3524 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3525 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3526 } else {
3527 hs_offchip_param =
3528 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3529 }
3530 return hs_offchip_param;
3531 }
3532
3533 static void
3534 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3535 struct radeon_winsys_bo *esgs_ring_bo,
3536 uint32_t esgs_ring_size,
3537 struct radeon_winsys_bo *gsvs_ring_bo,
3538 uint32_t gsvs_ring_size)
3539 {
3540 if (!esgs_ring_bo && !gsvs_ring_bo)
3541 return;
3542
3543 if (esgs_ring_bo)
3544 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3545
3546 if (gsvs_ring_bo)
3547 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3548
3549 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3550 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3551 radeon_emit(cs, esgs_ring_size >> 8);
3552 radeon_emit(cs, gsvs_ring_size >> 8);
3553 } else {
3554 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3555 radeon_emit(cs, esgs_ring_size >> 8);
3556 radeon_emit(cs, gsvs_ring_size >> 8);
3557 }
3558 }
3559
3560 static void
3561 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3562 unsigned hs_offchip_param, unsigned tf_ring_size,
3563 struct radeon_winsys_bo *tess_rings_bo)
3564 {
3565 uint64_t tf_va;
3566
3567 if (!tess_rings_bo)
3568 return;
3569
3570 tf_va = radv_buffer_get_va(tess_rings_bo);
3571
3572 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3573
3574 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3575 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3576 S_030938_SIZE(tf_ring_size / 4));
3577 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3578 tf_va >> 8);
3579
3580 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3581 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3582 S_030984_BASE_HI(tf_va >> 40));
3583 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3584 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3585 S_030944_BASE_HI(tf_va >> 40));
3586 }
3587 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3588 hs_offchip_param);
3589 } else {
3590 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3591 S_008988_SIZE(tf_ring_size / 4));
3592 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3593 tf_va >> 8);
3594 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3595 hs_offchip_param);
3596 }
3597 }
3598
3599 static void
3600 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3601 uint32_t size_per_wave, uint32_t waves,
3602 struct radeon_winsys_bo *scratch_bo)
3603 {
3604 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3605 return;
3606
3607 if (!scratch_bo)
3608 return;
3609
3610 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3611
3612 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3613 S_0286E8_WAVES(waves) |
3614 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3615 }
3616
3617 static void
3618 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3619 uint32_t size_per_wave, uint32_t waves,
3620 struct radeon_winsys_bo *compute_scratch_bo)
3621 {
3622 uint64_t scratch_va;
3623
3624 if (!compute_scratch_bo)
3625 return;
3626
3627 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3628
3629 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3630
3631 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3632 radeon_emit(cs, scratch_va);
3633 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3634 S_008F04_SWIZZLE_ENABLE(1));
3635
3636 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3637 S_00B860_WAVES(waves) |
3638 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3639 }
3640
3641 static void
3642 radv_emit_global_shader_pointers(struct radv_queue *queue,
3643 struct radeon_cmdbuf *cs,
3644 struct radeon_winsys_bo *descriptor_bo)
3645 {
3646 uint64_t va;
3647
3648 if (!descriptor_bo)
3649 return;
3650
3651 va = radv_buffer_get_va(descriptor_bo);
3652
3653 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3654
3655 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3656 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3657 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3658 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3659 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3660
3661 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3662 radv_emit_shader_pointer(queue->device, cs, regs[i],
3663 va, true);
3664 }
3665 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3666 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3667 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3668 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3669 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3670
3671 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3672 radv_emit_shader_pointer(queue->device, cs, regs[i],
3673 va, true);
3674 }
3675 } else {
3676 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3677 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3678 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3679 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3680 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3681 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3682
3683 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3684 radv_emit_shader_pointer(queue->device, cs, regs[i],
3685 va, true);
3686 }
3687 }
3688 }
3689
3690 static void
3691 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3692 {
3693 struct radv_device *device = queue->device;
3694
3695 if (device->gfx_init) {
3696 uint64_t va = radv_buffer_get_va(device->gfx_init);
3697
3698 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3699 radeon_emit(cs, va);
3700 radeon_emit(cs, va >> 32);
3701 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3702
3703 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3704 } else {
3705 si_emit_graphics(device, cs);
3706 }
3707 }
3708
3709 static void
3710 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3711 {
3712 struct radv_physical_device *physical_device = queue->device->physical_device;
3713 si_emit_compute(physical_device, cs);
3714 }
3715
3716 static VkResult
3717 radv_get_preamble_cs(struct radv_queue *queue,
3718 uint32_t scratch_size_per_wave,
3719 uint32_t scratch_waves,
3720 uint32_t compute_scratch_size_per_wave,
3721 uint32_t compute_scratch_waves,
3722 uint32_t esgs_ring_size,
3723 uint32_t gsvs_ring_size,
3724 bool needs_tess_rings,
3725 bool needs_gds,
3726 bool needs_gds_oa,
3727 bool needs_sample_positions,
3728 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3729 struct radeon_cmdbuf **initial_preamble_cs,
3730 struct radeon_cmdbuf **continue_preamble_cs)
3731 {
3732 struct radeon_winsys_bo *scratch_bo = NULL;
3733 struct radeon_winsys_bo *descriptor_bo = NULL;
3734 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3735 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3736 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3737 struct radeon_winsys_bo *tess_rings_bo = NULL;
3738 struct radeon_winsys_bo *gds_bo = NULL;
3739 struct radeon_winsys_bo *gds_oa_bo = NULL;
3740 struct radeon_cmdbuf *dest_cs[3] = {0};
3741 bool add_tess_rings = false, add_gds = false, add_gds_oa = false, add_sample_positions = false;
3742 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3743 unsigned max_offchip_buffers;
3744 unsigned hs_offchip_param = 0;
3745 unsigned tess_offchip_ring_offset;
3746 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3747 if (!queue->has_tess_rings) {
3748 if (needs_tess_rings)
3749 add_tess_rings = true;
3750 }
3751 if (!queue->has_gds) {
3752 if (needs_gds)
3753 add_gds = true;
3754 }
3755 if (!queue->has_gds_oa) {
3756 if (needs_gds_oa)
3757 add_gds_oa = true;
3758 }
3759 if (!queue->has_sample_positions) {
3760 if (needs_sample_positions)
3761 add_sample_positions = true;
3762 }
3763 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3764 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3765 &max_offchip_buffers);
3766 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3767 tess_offchip_ring_size = max_offchip_buffers *
3768 queue->device->tess_offchip_block_dw_size * 4;
3769
3770 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3771 if (scratch_size_per_wave)
3772 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3773 else
3774 scratch_waves = 0;
3775
3776 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3777 if (compute_scratch_size_per_wave)
3778 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3779 else
3780 compute_scratch_waves = 0;
3781
3782 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3783 scratch_waves <= queue->scratch_waves &&
3784 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3785 compute_scratch_waves <= queue->compute_scratch_waves &&
3786 esgs_ring_size <= queue->esgs_ring_size &&
3787 gsvs_ring_size <= queue->gsvs_ring_size &&
3788 !add_tess_rings && !add_gds && !add_gds_oa && !add_sample_positions &&
3789 queue->initial_preamble_cs) {
3790 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3791 *initial_preamble_cs = queue->initial_preamble_cs;
3792 *continue_preamble_cs = queue->continue_preamble_cs;
3793 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3794 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3795 !needs_gds && !needs_gds_oa && !needs_sample_positions)
3796 *continue_preamble_cs = NULL;
3797 return VK_SUCCESS;
3798 }
3799
3800 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3801 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3802 if (scratch_size > queue_scratch_size) {
3803 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3804 scratch_size,
3805 4096,
3806 RADEON_DOMAIN_VRAM,
3807 ring_bo_flags,
3808 RADV_BO_PRIORITY_SCRATCH);
3809 if (!scratch_bo)
3810 goto fail;
3811 } else
3812 scratch_bo = queue->scratch_bo;
3813
3814 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3815 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3816 if (compute_scratch_size > compute_queue_scratch_size) {
3817 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3818 compute_scratch_size,
3819 4096,
3820 RADEON_DOMAIN_VRAM,
3821 ring_bo_flags,
3822 RADV_BO_PRIORITY_SCRATCH);
3823 if (!compute_scratch_bo)
3824 goto fail;
3825
3826 } else
3827 compute_scratch_bo = queue->compute_scratch_bo;
3828
3829 if (esgs_ring_size > queue->esgs_ring_size) {
3830 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3831 esgs_ring_size,
3832 4096,
3833 RADEON_DOMAIN_VRAM,
3834 ring_bo_flags,
3835 RADV_BO_PRIORITY_SCRATCH);
3836 if (!esgs_ring_bo)
3837 goto fail;
3838 } else {
3839 esgs_ring_bo = queue->esgs_ring_bo;
3840 esgs_ring_size = queue->esgs_ring_size;
3841 }
3842
3843 if (gsvs_ring_size > queue->gsvs_ring_size) {
3844 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3845 gsvs_ring_size,
3846 4096,
3847 RADEON_DOMAIN_VRAM,
3848 ring_bo_flags,
3849 RADV_BO_PRIORITY_SCRATCH);
3850 if (!gsvs_ring_bo)
3851 goto fail;
3852 } else {
3853 gsvs_ring_bo = queue->gsvs_ring_bo;
3854 gsvs_ring_size = queue->gsvs_ring_size;
3855 }
3856
3857 if (add_tess_rings) {
3858 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3859 tess_offchip_ring_offset + tess_offchip_ring_size,
3860 256,
3861 RADEON_DOMAIN_VRAM,
3862 ring_bo_flags,
3863 RADV_BO_PRIORITY_SCRATCH);
3864 if (!tess_rings_bo)
3865 goto fail;
3866 } else {
3867 tess_rings_bo = queue->tess_rings_bo;
3868 }
3869
3870 if (add_gds) {
3871 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3872
3873 /* 4 streamout GDS counters.
3874 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3875 */
3876 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3877 256, 4,
3878 RADEON_DOMAIN_GDS,
3879 ring_bo_flags,
3880 RADV_BO_PRIORITY_SCRATCH);
3881 if (!gds_bo)
3882 goto fail;
3883 } else {
3884 gds_bo = queue->gds_bo;
3885 }
3886
3887 if (add_gds_oa) {
3888 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3889
3890 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3891 4, 1,
3892 RADEON_DOMAIN_OA,
3893 ring_bo_flags,
3894 RADV_BO_PRIORITY_SCRATCH);
3895 if (!gds_oa_bo)
3896 goto fail;
3897 } else {
3898 gds_oa_bo = queue->gds_oa_bo;
3899 }
3900
3901 if (scratch_bo != queue->scratch_bo ||
3902 esgs_ring_bo != queue->esgs_ring_bo ||
3903 gsvs_ring_bo != queue->gsvs_ring_bo ||
3904 tess_rings_bo != queue->tess_rings_bo ||
3905 add_sample_positions) {
3906 uint32_t size = 0;
3907 if (gsvs_ring_bo || esgs_ring_bo ||
3908 tess_rings_bo || add_sample_positions) {
3909 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3910 if (add_sample_positions)
3911 size += 128; /* 64+32+16+8 = 120 bytes */
3912 }
3913 else if (scratch_bo)
3914 size = 8; /* 2 dword */
3915
3916 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3917 size,
3918 4096,
3919 RADEON_DOMAIN_VRAM,
3920 RADEON_FLAG_CPU_ACCESS |
3921 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3922 RADEON_FLAG_READ_ONLY,
3923 RADV_BO_PRIORITY_DESCRIPTOR);
3924 if (!descriptor_bo)
3925 goto fail;
3926 } else
3927 descriptor_bo = queue->descriptor_bo;
3928
3929 if (descriptor_bo != queue->descriptor_bo) {
3930 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3931
3932 if (scratch_bo) {
3933 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3934 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3935 S_008F04_SWIZZLE_ENABLE(1);
3936 map[0] = scratch_va;
3937 map[1] = rsrc1;
3938 }
3939
3940 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3941 fill_geom_tess_rings(queue, map, add_sample_positions,
3942 esgs_ring_size, esgs_ring_bo,
3943 gsvs_ring_size, gsvs_ring_bo,
3944 tess_factor_ring_size,
3945 tess_offchip_ring_offset,
3946 tess_offchip_ring_size,
3947 tess_rings_bo);
3948
3949 queue->device->ws->buffer_unmap(descriptor_bo);
3950 }
3951
3952 for(int i = 0; i < 3; ++i) {
3953 struct radeon_cmdbuf *cs = NULL;
3954 cs = queue->device->ws->cs_create(queue->device->ws,
3955 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3956 if (!cs)
3957 goto fail;
3958
3959 dest_cs[i] = cs;
3960
3961 if (scratch_bo)
3962 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3963
3964 /* Emit initial configuration. */
3965 switch (queue->queue_family_index) {
3966 case RADV_QUEUE_GENERAL:
3967 radv_init_graphics_state(cs, queue);
3968 break;
3969 case RADV_QUEUE_COMPUTE:
3970 radv_init_compute_state(cs, queue);
3971 break;
3972 case RADV_QUEUE_TRANSFER:
3973 break;
3974 }
3975
3976 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3977 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3978 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3979
3980 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3981 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3982 }
3983
3984 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3985 gsvs_ring_bo, gsvs_ring_size);
3986 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3987 tess_factor_ring_size, tess_rings_bo);
3988 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3989 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3990 compute_scratch_waves, compute_scratch_bo);
3991 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3992 scratch_waves, scratch_bo);
3993
3994 if (gds_bo)
3995 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3996 if (gds_oa_bo)
3997 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3998
3999 if (queue->device->trace_bo)
4000 radv_cs_add_buffer(queue->device->ws, cs, queue->device->trace_bo);
4001
4002 if (i == 0) {
4003 si_cs_emit_cache_flush(cs,
4004 queue->device->physical_device->rad_info.chip_class,
4005 NULL, 0,
4006 queue->queue_family_index == RING_COMPUTE &&
4007 queue->device->physical_device->rad_info.chip_class >= GFX7,
4008 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
4009 RADV_CMD_FLAG_INV_ICACHE |
4010 RADV_CMD_FLAG_INV_SCACHE |
4011 RADV_CMD_FLAG_INV_VCACHE |
4012 RADV_CMD_FLAG_INV_L2 |
4013 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
4014 } else if (i == 1) {
4015 si_cs_emit_cache_flush(cs,
4016 queue->device->physical_device->rad_info.chip_class,
4017 NULL, 0,
4018 queue->queue_family_index == RING_COMPUTE &&
4019 queue->device->physical_device->rad_info.chip_class >= GFX7,
4020 RADV_CMD_FLAG_INV_ICACHE |
4021 RADV_CMD_FLAG_INV_SCACHE |
4022 RADV_CMD_FLAG_INV_VCACHE |
4023 RADV_CMD_FLAG_INV_L2 |
4024 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
4025 }
4026
4027 if (!queue->device->ws->cs_finalize(cs))
4028 goto fail;
4029 }
4030
4031 if (queue->initial_full_flush_preamble_cs)
4032 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
4033
4034 if (queue->initial_preamble_cs)
4035 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
4036
4037 if (queue->continue_preamble_cs)
4038 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
4039
4040 queue->initial_full_flush_preamble_cs = dest_cs[0];
4041 queue->initial_preamble_cs = dest_cs[1];
4042 queue->continue_preamble_cs = dest_cs[2];
4043
4044 if (scratch_bo != queue->scratch_bo) {
4045 if (queue->scratch_bo)
4046 queue->device->ws->buffer_destroy(queue->scratch_bo);
4047 queue->scratch_bo = scratch_bo;
4048 }
4049 queue->scratch_size_per_wave = scratch_size_per_wave;
4050 queue->scratch_waves = scratch_waves;
4051
4052 if (compute_scratch_bo != queue->compute_scratch_bo) {
4053 if (queue->compute_scratch_bo)
4054 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
4055 queue->compute_scratch_bo = compute_scratch_bo;
4056 }
4057 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
4058 queue->compute_scratch_waves = compute_scratch_waves;
4059
4060 if (esgs_ring_bo != queue->esgs_ring_bo) {
4061 if (queue->esgs_ring_bo)
4062 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
4063 queue->esgs_ring_bo = esgs_ring_bo;
4064 queue->esgs_ring_size = esgs_ring_size;
4065 }
4066
4067 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
4068 if (queue->gsvs_ring_bo)
4069 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
4070 queue->gsvs_ring_bo = gsvs_ring_bo;
4071 queue->gsvs_ring_size = gsvs_ring_size;
4072 }
4073
4074 if (tess_rings_bo != queue->tess_rings_bo) {
4075 queue->tess_rings_bo = tess_rings_bo;
4076 queue->has_tess_rings = true;
4077 }
4078
4079 if (gds_bo != queue->gds_bo) {
4080 queue->gds_bo = gds_bo;
4081 queue->has_gds = true;
4082 }
4083
4084 if (gds_oa_bo != queue->gds_oa_bo) {
4085 queue->gds_oa_bo = gds_oa_bo;
4086 queue->has_gds_oa = true;
4087 }
4088
4089 if (descriptor_bo != queue->descriptor_bo) {
4090 if (queue->descriptor_bo)
4091 queue->device->ws->buffer_destroy(queue->descriptor_bo);
4092
4093 queue->descriptor_bo = descriptor_bo;
4094 }
4095
4096 if (add_sample_positions)
4097 queue->has_sample_positions = true;
4098
4099 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
4100 *initial_preamble_cs = queue->initial_preamble_cs;
4101 *continue_preamble_cs = queue->continue_preamble_cs;
4102 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
4103 *continue_preamble_cs = NULL;
4104 return VK_SUCCESS;
4105 fail:
4106 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
4107 if (dest_cs[i])
4108 queue->device->ws->cs_destroy(dest_cs[i]);
4109 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
4110 queue->device->ws->buffer_destroy(descriptor_bo);
4111 if (scratch_bo && scratch_bo != queue->scratch_bo)
4112 queue->device->ws->buffer_destroy(scratch_bo);
4113 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
4114 queue->device->ws->buffer_destroy(compute_scratch_bo);
4115 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
4116 queue->device->ws->buffer_destroy(esgs_ring_bo);
4117 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
4118 queue->device->ws->buffer_destroy(gsvs_ring_bo);
4119 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
4120 queue->device->ws->buffer_destroy(tess_rings_bo);
4121 if (gds_bo && gds_bo != queue->gds_bo)
4122 queue->device->ws->buffer_destroy(gds_bo);
4123 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
4124 queue->device->ws->buffer_destroy(gds_oa_bo);
4125
4126 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4127 }
4128
4129 static VkResult radv_alloc_sem_counts(struct radv_device *device,
4130 struct radv_winsys_sem_counts *counts,
4131 int num_sems,
4132 struct radv_semaphore_part **sems,
4133 const uint64_t *timeline_values,
4134 VkFence _fence,
4135 bool is_signal)
4136 {
4137 int syncobj_idx = 0, sem_idx = 0;
4138
4139 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
4140 return VK_SUCCESS;
4141
4142 for (uint32_t i = 0; i < num_sems; i++) {
4143 switch(sems[i]->kind) {
4144 case RADV_SEMAPHORE_SYNCOBJ:
4145 counts->syncobj_count++;
4146 break;
4147 case RADV_SEMAPHORE_WINSYS:
4148 counts->sem_count++;
4149 break;
4150 case RADV_SEMAPHORE_NONE:
4151 break;
4152 case RADV_SEMAPHORE_TIMELINE:
4153 counts->syncobj_count++;
4154 break;
4155 }
4156 }
4157
4158 if (_fence != VK_NULL_HANDLE) {
4159 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4160 if (fence->temp_syncobj || fence->syncobj)
4161 counts->syncobj_count++;
4162 }
4163
4164 if (counts->syncobj_count) {
4165 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
4166 if (!counts->syncobj)
4167 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4168 }
4169
4170 if (counts->sem_count) {
4171 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
4172 if (!counts->sem) {
4173 free(counts->syncobj);
4174 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4175 }
4176 }
4177
4178 for (uint32_t i = 0; i < num_sems; i++) {
4179 switch(sems[i]->kind) {
4180 case RADV_SEMAPHORE_NONE:
4181 unreachable("Empty semaphore");
4182 break;
4183 case RADV_SEMAPHORE_SYNCOBJ:
4184 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
4185 break;
4186 case RADV_SEMAPHORE_WINSYS:
4187 counts->sem[sem_idx++] = sems[i]->ws_sem;
4188 break;
4189 case RADV_SEMAPHORE_TIMELINE: {
4190 pthread_mutex_lock(&sems[i]->timeline.mutex);
4191 struct radv_timeline_point *point = NULL;
4192 if (is_signal) {
4193 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
4194 } else {
4195 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
4196 }
4197
4198 pthread_mutex_unlock(&sems[i]->timeline.mutex);
4199
4200 if (point) {
4201 counts->syncobj[syncobj_idx++] = point->syncobj;
4202 } else {
4203 /* Explicitly remove the semaphore so we might not find
4204 * a point later post-submit. */
4205 sems[i] = NULL;
4206 }
4207 break;
4208 }
4209 }
4210 }
4211
4212 if (_fence != VK_NULL_HANDLE) {
4213 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4214 if (fence->temp_syncobj)
4215 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
4216 else if (fence->syncobj)
4217 counts->syncobj[syncobj_idx++] = fence->syncobj;
4218 }
4219
4220 assert(syncobj_idx <= counts->syncobj_count);
4221 counts->syncobj_count = syncobj_idx;
4222
4223 return VK_SUCCESS;
4224 }
4225
4226 static void
4227 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
4228 {
4229 free(sem_info->wait.syncobj);
4230 free(sem_info->wait.sem);
4231 free(sem_info->signal.syncobj);
4232 free(sem_info->signal.sem);
4233 }
4234
4235
4236 static void radv_free_temp_syncobjs(struct radv_device *device,
4237 int num_sems,
4238 struct radv_semaphore_part *sems)
4239 {
4240 for (uint32_t i = 0; i < num_sems; i++) {
4241 radv_destroy_semaphore_part(device, sems + i);
4242 }
4243 }
4244
4245 static VkResult
4246 radv_alloc_sem_info(struct radv_device *device,
4247 struct radv_winsys_sem_info *sem_info,
4248 int num_wait_sems,
4249 struct radv_semaphore_part **wait_sems,
4250 const uint64_t *wait_values,
4251 int num_signal_sems,
4252 struct radv_semaphore_part **signal_sems,
4253 const uint64_t *signal_values,
4254 VkFence fence)
4255 {
4256 VkResult ret;
4257 memset(sem_info, 0, sizeof(*sem_info));
4258
4259 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
4260 if (ret)
4261 return ret;
4262 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
4263 if (ret)
4264 radv_free_sem_info(sem_info);
4265
4266 /* caller can override these */
4267 sem_info->cs_emit_wait = true;
4268 sem_info->cs_emit_signal = true;
4269 return ret;
4270 }
4271
4272 static void
4273 radv_finalize_timelines(struct radv_device *device,
4274 uint32_t num_wait_sems,
4275 struct radv_semaphore_part **wait_sems,
4276 const uint64_t *wait_values,
4277 uint32_t num_signal_sems,
4278 struct radv_semaphore_part **signal_sems,
4279 const uint64_t *signal_values,
4280 struct list_head *processing_list)
4281 {
4282 for (uint32_t i = 0; i < num_wait_sems; ++i) {
4283 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4284 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
4285 struct radv_timeline_point *point =
4286 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
4287 point->wait_count -= 2;
4288 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
4289 }
4290 }
4291 for (uint32_t i = 0; i < num_signal_sems; ++i) {
4292 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4293 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
4294 struct radv_timeline_point *point =
4295 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
4296 signal_sems[i]->timeline.highest_submitted =
4297 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
4298 point->wait_count -= 2;
4299 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
4300 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
4301 }
4302 }
4303 }
4304
4305 static void
4306 radv_sparse_buffer_bind_memory(struct radv_device *device,
4307 const VkSparseBufferMemoryBindInfo *bind)
4308 {
4309 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4310
4311 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4312 struct radv_device_memory *mem = NULL;
4313
4314 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4315 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4316
4317 device->ws->buffer_virtual_bind(buffer->bo,
4318 bind->pBinds[i].resourceOffset,
4319 bind->pBinds[i].size,
4320 mem ? mem->bo : NULL,
4321 bind->pBinds[i].memoryOffset);
4322 }
4323 }
4324
4325 static void
4326 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4327 const VkSparseImageOpaqueMemoryBindInfo *bind)
4328 {
4329 RADV_FROM_HANDLE(radv_image, image, bind->image);
4330
4331 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4332 struct radv_device_memory *mem = NULL;
4333
4334 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4335 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4336
4337 device->ws->buffer_virtual_bind(image->bo,
4338 bind->pBinds[i].resourceOffset,
4339 bind->pBinds[i].size,
4340 mem ? mem->bo : NULL,
4341 bind->pBinds[i].memoryOffset);
4342 }
4343 }
4344
4345 static VkResult
4346 radv_get_preambles(struct radv_queue *queue,
4347 const VkCommandBuffer *cmd_buffers,
4348 uint32_t cmd_buffer_count,
4349 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4350 struct radeon_cmdbuf **initial_preamble_cs,
4351 struct radeon_cmdbuf **continue_preamble_cs)
4352 {
4353 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4354 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4355 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4356 bool tess_rings_needed = false;
4357 bool gds_needed = false;
4358 bool gds_oa_needed = false;
4359 bool sample_positions_needed = false;
4360
4361 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4363 cmd_buffers[j]);
4364
4365 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4366 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4367 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4368 cmd_buffer->compute_scratch_size_per_wave_needed);
4369 compute_waves_wanted = MAX2(compute_waves_wanted,
4370 cmd_buffer->compute_scratch_waves_wanted);
4371 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4372 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4373 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4374 gds_needed |= cmd_buffer->gds_needed;
4375 gds_oa_needed |= cmd_buffer->gds_oa_needed;
4376 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4377 }
4378
4379 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4380 compute_scratch_size_per_wave, compute_waves_wanted,
4381 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4382 gds_needed, gds_oa_needed, sample_positions_needed,
4383 initial_full_flush_preamble_cs,
4384 initial_preamble_cs, continue_preamble_cs);
4385 }
4386
4387 struct radv_deferred_queue_submission {
4388 struct radv_queue *queue;
4389 VkCommandBuffer *cmd_buffers;
4390 uint32_t cmd_buffer_count;
4391
4392 /* Sparse bindings that happen on a queue. */
4393 VkSparseBufferMemoryBindInfo *buffer_binds;
4394 uint32_t buffer_bind_count;
4395 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4396 uint32_t image_opaque_bind_count;
4397
4398 bool flush_caches;
4399 VkShaderStageFlags wait_dst_stage_mask;
4400 struct radv_semaphore_part **wait_semaphores;
4401 uint32_t wait_semaphore_count;
4402 struct radv_semaphore_part **signal_semaphores;
4403 uint32_t signal_semaphore_count;
4404 VkFence fence;
4405
4406 uint64_t *wait_values;
4407 uint64_t *signal_values;
4408
4409 struct radv_semaphore_part *temporary_semaphore_parts;
4410 uint32_t temporary_semaphore_part_count;
4411
4412 struct list_head queue_pending_list;
4413 uint32_t submission_wait_count;
4414 struct radv_timeline_waiter *wait_nodes;
4415
4416 struct list_head processing_list;
4417 };
4418
4419 struct radv_queue_submission {
4420 const VkCommandBuffer *cmd_buffers;
4421 uint32_t cmd_buffer_count;
4422
4423 /* Sparse bindings that happen on a queue. */
4424 const VkSparseBufferMemoryBindInfo *buffer_binds;
4425 uint32_t buffer_bind_count;
4426 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4427 uint32_t image_opaque_bind_count;
4428
4429 bool flush_caches;
4430 VkPipelineStageFlags wait_dst_stage_mask;
4431 const VkSemaphore *wait_semaphores;
4432 uint32_t wait_semaphore_count;
4433 const VkSemaphore *signal_semaphores;
4434 uint32_t signal_semaphore_count;
4435 VkFence fence;
4436
4437 const uint64_t *wait_values;
4438 uint32_t wait_value_count;
4439 const uint64_t *signal_values;
4440 uint32_t signal_value_count;
4441 };
4442
4443 static VkResult
4444 radv_create_deferred_submission(struct radv_queue *queue,
4445 const struct radv_queue_submission *submission,
4446 struct radv_deferred_queue_submission **out)
4447 {
4448 struct radv_deferred_queue_submission *deferred = NULL;
4449 size_t size = sizeof(struct radv_deferred_queue_submission);
4450
4451 uint32_t temporary_count = 0;
4452 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4453 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4454 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4455 ++temporary_count;
4456 }
4457
4458 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4459 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4460 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4461 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4462 size += temporary_count * sizeof(struct radv_semaphore_part);
4463 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4464 size += submission->wait_value_count * sizeof(uint64_t);
4465 size += submission->signal_value_count * sizeof(uint64_t);
4466 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4467
4468 deferred = calloc(1, size);
4469 if (!deferred)
4470 return VK_ERROR_OUT_OF_HOST_MEMORY;
4471
4472 deferred->queue = queue;
4473
4474 deferred->cmd_buffers = (void*)(deferred + 1);
4475 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4476 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4477 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4478
4479 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4480 deferred->buffer_bind_count = submission->buffer_bind_count;
4481 memcpy(deferred->buffer_binds, submission->buffer_binds,
4482 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4483
4484 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4485 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4486 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4487 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4488
4489 deferred->flush_caches = submission->flush_caches;
4490 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4491
4492 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4493 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4494
4495 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4496 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4497
4498 deferred->fence = submission->fence;
4499
4500 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4501 deferred->temporary_semaphore_part_count = temporary_count;
4502
4503 uint32_t temporary_idx = 0;
4504 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4505 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4506 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4507 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4508 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4509 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4510 ++temporary_idx;
4511 } else
4512 deferred->wait_semaphores[i] = &semaphore->permanent;
4513 }
4514
4515 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4516 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4517 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4518 deferred->signal_semaphores[i] = &semaphore->temporary;
4519 } else {
4520 deferred->signal_semaphores[i] = &semaphore->permanent;
4521 }
4522 }
4523
4524 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4525 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4526 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4527 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4528
4529 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4530 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4531 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4532 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4533
4534 *out = deferred;
4535 return VK_SUCCESS;
4536 }
4537
4538 static void
4539 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4540 struct list_head *processing_list)
4541 {
4542 uint32_t wait_cnt = 0;
4543 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4544 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4545 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4546 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4547 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4548 ++wait_cnt;
4549 waiter->value = submission->wait_values[i];
4550 waiter->submission = submission;
4551 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4552 ++waiter;
4553 }
4554 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4555 }
4556 }
4557
4558 pthread_mutex_lock(&submission->queue->pending_mutex);
4559
4560 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4561 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4562
4563 pthread_mutex_unlock(&submission->queue->pending_mutex);
4564
4565 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4566 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4567 * submission. */
4568 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4569 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4570 list_addtail(&submission->processing_list, processing_list);
4571 }
4572 }
4573
4574 static void
4575 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4576 struct list_head *processing_list)
4577 {
4578 pthread_mutex_lock(&submission->queue->pending_mutex);
4579 list_del(&submission->queue_pending_list);
4580
4581 /* trigger the next submission in the queue. */
4582 if (!list_is_empty(&submission->queue->pending_submissions)) {
4583 struct radv_deferred_queue_submission *next_submission =
4584 list_first_entry(&submission->queue->pending_submissions,
4585 struct radv_deferred_queue_submission,
4586 queue_pending_list);
4587 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4588 list_addtail(&next_submission->processing_list, processing_list);
4589 }
4590 }
4591 pthread_mutex_unlock(&submission->queue->pending_mutex);
4592
4593 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4594 }
4595
4596 static VkResult
4597 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4598 struct list_head *processing_list)
4599 {
4600 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4601 struct radv_queue *queue = submission->queue;
4602 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4603 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4604 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
4605 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4606 bool can_patch = true;
4607 uint32_t advance;
4608 struct radv_winsys_sem_info sem_info;
4609 VkResult result;
4610 int ret;
4611 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4612 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4613 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4614
4615 result = radv_get_preambles(queue, submission->cmd_buffers,
4616 submission->cmd_buffer_count,
4617 &initial_preamble_cs,
4618 &initial_flush_preamble_cs,
4619 &continue_preamble_cs);
4620 if (result != VK_SUCCESS)
4621 goto fail;
4622
4623 result = radv_alloc_sem_info(queue->device,
4624 &sem_info,
4625 submission->wait_semaphore_count,
4626 submission->wait_semaphores,
4627 submission->wait_values,
4628 submission->signal_semaphore_count,
4629 submission->signal_semaphores,
4630 submission->signal_values,
4631 submission->fence);
4632 if (result != VK_SUCCESS)
4633 goto fail;
4634
4635 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4636 radv_sparse_buffer_bind_memory(queue->device,
4637 submission->buffer_binds + i);
4638 }
4639
4640 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4641 radv_sparse_image_opaque_bind_memory(queue->device,
4642 submission->image_opaque_binds + i);
4643 }
4644
4645 if (!submission->cmd_buffer_count) {
4646 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4647 &queue->device->empty_cs[queue->queue_family_index],
4648 1, NULL, NULL,
4649 &sem_info, NULL,
4650 false, base_fence);
4651 if (ret) {
4652 radv_loge("failed to submit CS\n");
4653 abort();
4654 }
4655
4656 goto success;
4657 } else {
4658 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4659 (submission->cmd_buffer_count));
4660
4661 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4662 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4663 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4664
4665 cs_array[j] = cmd_buffer->cs;
4666 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4667 can_patch = false;
4668
4669 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4670 }
4671
4672 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4673 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4674 const struct radv_winsys_bo_list *bo_list = NULL;
4675
4676 advance = MIN2(max_cs_submission,
4677 submission->cmd_buffer_count - j);
4678
4679 if (queue->device->trace_bo)
4680 *queue->device->trace_id_ptr = 0;
4681
4682 sem_info.cs_emit_wait = j == 0;
4683 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4684
4685 if (unlikely(queue->device->use_global_bo_list)) {
4686 pthread_mutex_lock(&queue->device->bo_list.mutex);
4687 bo_list = &queue->device->bo_list.list;
4688 }
4689
4690 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4691 advance, initial_preamble, continue_preamble_cs,
4692 &sem_info, bo_list,
4693 can_patch, base_fence);
4694
4695 if (unlikely(queue->device->use_global_bo_list))
4696 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4697
4698 if (ret) {
4699 radv_loge("failed to submit CS\n");
4700 abort();
4701 }
4702 if (queue->device->trace_bo) {
4703 radv_check_gpu_hangs(queue, cs_array[j]);
4704 }
4705 }
4706
4707 free(cs_array);
4708 }
4709
4710 success:
4711 radv_free_temp_syncobjs(queue->device,
4712 submission->temporary_semaphore_part_count,
4713 submission->temporary_semaphore_parts);
4714 radv_finalize_timelines(queue->device,
4715 submission->wait_semaphore_count,
4716 submission->wait_semaphores,
4717 submission->wait_values,
4718 submission->signal_semaphore_count,
4719 submission->signal_semaphores,
4720 submission->signal_values,
4721 processing_list);
4722 /* Has to happen after timeline finalization to make sure the
4723 * condition variable is only triggered when timelines and queue have
4724 * been updated. */
4725 radv_queue_submission_update_queue(submission, processing_list);
4726 radv_free_sem_info(&sem_info);
4727 free(submission);
4728 return VK_SUCCESS;
4729
4730 fail:
4731 radv_free_temp_syncobjs(queue->device,
4732 submission->temporary_semaphore_part_count,
4733 submission->temporary_semaphore_parts);
4734 free(submission);
4735 return VK_ERROR_DEVICE_LOST;
4736 }
4737
4738 static VkResult
4739 radv_process_submissions(struct list_head *processing_list)
4740 {
4741 while(!list_is_empty(processing_list)) {
4742 struct radv_deferred_queue_submission *submission =
4743 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4744 list_del(&submission->processing_list);
4745
4746 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4747 if (result != VK_SUCCESS)
4748 return result;
4749 }
4750 return VK_SUCCESS;
4751 }
4752
4753 static VkResult radv_queue_submit(struct radv_queue *queue,
4754 const struct radv_queue_submission *submission)
4755 {
4756 struct radv_deferred_queue_submission *deferred = NULL;
4757
4758 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4759 if (result != VK_SUCCESS)
4760 return result;
4761
4762 struct list_head processing_list;
4763 list_inithead(&processing_list);
4764
4765 radv_queue_enqueue_submission(deferred, &processing_list);
4766 return radv_process_submissions(&processing_list);
4767 }
4768
4769 bool
4770 radv_queue_internal_submit(struct radv_queue *queue, struct radeon_cmdbuf *cs)
4771 {
4772 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4773 struct radv_winsys_sem_info sem_info;
4774 VkResult result;
4775 int ret;
4776
4777 result = radv_alloc_sem_info(queue->device, &sem_info, 0, NULL, 0, 0,
4778 0, NULL, VK_NULL_HANDLE);
4779 if (result != VK_SUCCESS)
4780 return false;
4781
4782 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, &cs, 1, NULL,
4783 NULL, &sem_info, NULL, false, NULL);
4784 radv_free_sem_info(&sem_info);
4785 return !ret;
4786 }
4787
4788 /* Signals fence as soon as all the work currently put on queue is done. */
4789 static VkResult radv_signal_fence(struct radv_queue *queue,
4790 VkFence fence)
4791 {
4792 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4793 .fence = fence
4794 });
4795 }
4796
4797 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4798 {
4799 return info->commandBufferCount ||
4800 info->waitSemaphoreCount ||
4801 info->signalSemaphoreCount;
4802 }
4803
4804 VkResult radv_QueueSubmit(
4805 VkQueue _queue,
4806 uint32_t submitCount,
4807 const VkSubmitInfo* pSubmits,
4808 VkFence fence)
4809 {
4810 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4811 VkResult result;
4812 uint32_t fence_idx = 0;
4813 bool flushed_caches = false;
4814
4815 if (fence != VK_NULL_HANDLE) {
4816 for (uint32_t i = 0; i < submitCount; ++i)
4817 if (radv_submit_has_effects(pSubmits + i))
4818 fence_idx = i;
4819 } else
4820 fence_idx = UINT32_MAX;
4821
4822 for (uint32_t i = 0; i < submitCount; i++) {
4823 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4824 continue;
4825
4826 VkPipelineStageFlags wait_dst_stage_mask = 0;
4827 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4828 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4829 }
4830
4831 const VkTimelineSemaphoreSubmitInfo *timeline_info =
4832 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
4833
4834 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4835 .cmd_buffers = pSubmits[i].pCommandBuffers,
4836 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4837 .wait_dst_stage_mask = wait_dst_stage_mask,
4838 .flush_caches = !flushed_caches,
4839 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4840 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4841 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4842 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4843 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4844 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4845 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4846 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4847 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4848 });
4849 if (result != VK_SUCCESS)
4850 return result;
4851
4852 flushed_caches = true;
4853 }
4854
4855 if (fence != VK_NULL_HANDLE && !submitCount) {
4856 result = radv_signal_fence(queue, fence);
4857 if (result != VK_SUCCESS)
4858 return result;
4859 }
4860
4861 return VK_SUCCESS;
4862 }
4863
4864 VkResult radv_QueueWaitIdle(
4865 VkQueue _queue)
4866 {
4867 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4868
4869 pthread_mutex_lock(&queue->pending_mutex);
4870 while (!list_is_empty(&queue->pending_submissions)) {
4871 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4872 }
4873 pthread_mutex_unlock(&queue->pending_mutex);
4874
4875 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4876 radv_queue_family_to_ring(queue->queue_family_index),
4877 queue->queue_idx);
4878 return VK_SUCCESS;
4879 }
4880
4881 VkResult radv_DeviceWaitIdle(
4882 VkDevice _device)
4883 {
4884 RADV_FROM_HANDLE(radv_device, device, _device);
4885
4886 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4887 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4888 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4889 }
4890 }
4891 return VK_SUCCESS;
4892 }
4893
4894 VkResult radv_EnumerateInstanceExtensionProperties(
4895 const char* pLayerName,
4896 uint32_t* pPropertyCount,
4897 VkExtensionProperties* pProperties)
4898 {
4899 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4900
4901 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4902 if (radv_supported_instance_extensions.extensions[i]) {
4903 vk_outarray_append(&out, prop) {
4904 *prop = radv_instance_extensions[i];
4905 }
4906 }
4907 }
4908
4909 return vk_outarray_status(&out);
4910 }
4911
4912 VkResult radv_EnumerateDeviceExtensionProperties(
4913 VkPhysicalDevice physicalDevice,
4914 const char* pLayerName,
4915 uint32_t* pPropertyCount,
4916 VkExtensionProperties* pProperties)
4917 {
4918 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4919 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4920
4921 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4922 if (device->supported_extensions.extensions[i]) {
4923 vk_outarray_append(&out, prop) {
4924 *prop = radv_device_extensions[i];
4925 }
4926 }
4927 }
4928
4929 return vk_outarray_status(&out);
4930 }
4931
4932 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4933 VkInstance _instance,
4934 const char* pName)
4935 {
4936 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4937
4938 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4939 * when we have to return valid function pointers, NULL, or it's left
4940 * undefined. See the table for exact details.
4941 */
4942 if (pName == NULL)
4943 return NULL;
4944
4945 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4946 if (strcmp(pName, "vk" #entrypoint) == 0) \
4947 return (PFN_vkVoidFunction)radv_##entrypoint
4948
4949 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties);
4950 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties);
4951 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion);
4952 LOOKUP_RADV_ENTRYPOINT(CreateInstance);
4953
4954 /* GetInstanceProcAddr() can also be called with a NULL instance.
4955 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4956 */
4957 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr);
4958
4959 #undef LOOKUP_RADV_ENTRYPOINT
4960
4961 if (instance == NULL)
4962 return NULL;
4963
4964 int idx = radv_get_instance_entrypoint_index(pName);
4965 if (idx >= 0)
4966 return instance->dispatch.entrypoints[idx];
4967
4968 idx = radv_get_physical_device_entrypoint_index(pName);
4969 if (idx >= 0)
4970 return instance->physical_device_dispatch.entrypoints[idx];
4971
4972 idx = radv_get_device_entrypoint_index(pName);
4973 if (idx >= 0)
4974 return instance->device_dispatch.entrypoints[idx];
4975
4976 return NULL;
4977 }
4978
4979 /* The loader wants us to expose a second GetInstanceProcAddr function
4980 * to work around certain LD_PRELOAD issues seen in apps.
4981 */
4982 PUBLIC
4983 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4984 VkInstance instance,
4985 const char* pName);
4986
4987 PUBLIC
4988 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4989 VkInstance instance,
4990 const char* pName)
4991 {
4992 return radv_GetInstanceProcAddr(instance, pName);
4993 }
4994
4995 PUBLIC
4996 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4997 VkInstance _instance,
4998 const char* pName);
4999
5000 PUBLIC
5001 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
5002 VkInstance _instance,
5003 const char* pName)
5004 {
5005 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5006
5007 if (!pName || !instance)
5008 return NULL;
5009
5010 int idx = radv_get_physical_device_entrypoint_index(pName);
5011 if (idx < 0)
5012 return NULL;
5013
5014 return instance->physical_device_dispatch.entrypoints[idx];
5015 }
5016
5017 PFN_vkVoidFunction radv_GetDeviceProcAddr(
5018 VkDevice _device,
5019 const char* pName)
5020 {
5021 RADV_FROM_HANDLE(radv_device, device, _device);
5022
5023 if (!device || !pName)
5024 return NULL;
5025
5026 int idx = radv_get_device_entrypoint_index(pName);
5027 if (idx < 0)
5028 return NULL;
5029
5030 return device->dispatch.entrypoints[idx];
5031 }
5032
5033 bool radv_get_memory_fd(struct radv_device *device,
5034 struct radv_device_memory *memory,
5035 int *pFD)
5036 {
5037 struct radeon_bo_metadata metadata;
5038
5039 if (memory->image) {
5040 if (memory->image->tiling != VK_IMAGE_TILING_LINEAR)
5041 radv_init_metadata(device, memory->image, &metadata);
5042 device->ws->buffer_set_metadata(memory->bo, &metadata);
5043 }
5044
5045 return device->ws->buffer_get_fd(device->ws, memory->bo,
5046 pFD);
5047 }
5048
5049
5050 static void radv_free_memory(struct radv_device *device,
5051 const VkAllocationCallbacks* pAllocator,
5052 struct radv_device_memory *mem)
5053 {
5054 if (mem == NULL)
5055 return;
5056
5057 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5058 if (mem->android_hardware_buffer)
5059 AHardwareBuffer_release(mem->android_hardware_buffer);
5060 #endif
5061
5062 if (mem->bo) {
5063 radv_bo_list_remove(device, mem->bo);
5064 device->ws->buffer_destroy(mem->bo);
5065 mem->bo = NULL;
5066 }
5067
5068 vk_free2(&device->alloc, pAllocator, mem);
5069 }
5070
5071 static VkResult radv_alloc_memory(struct radv_device *device,
5072 const VkMemoryAllocateInfo* pAllocateInfo,
5073 const VkAllocationCallbacks* pAllocator,
5074 VkDeviceMemory* pMem)
5075 {
5076 struct radv_device_memory *mem;
5077 VkResult result;
5078 enum radeon_bo_domain domain;
5079 uint32_t flags = 0;
5080 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
5081
5082 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
5083
5084 const VkImportMemoryFdInfoKHR *import_info =
5085 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
5086 const VkMemoryDedicatedAllocateInfo *dedicate_info =
5087 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
5088 const VkExportMemoryAllocateInfo *export_info =
5089 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
5090 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
5091 vk_find_struct_const(pAllocateInfo->pNext,
5092 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
5093 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
5094 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
5095
5096 const struct wsi_memory_allocate_info *wsi_info =
5097 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
5098
5099 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
5100 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
5101 /* Apparently, this is allowed */
5102 *pMem = VK_NULL_HANDLE;
5103 return VK_SUCCESS;
5104 }
5105
5106 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
5107 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5108 if (mem == NULL)
5109 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5110
5111 if (wsi_info && wsi_info->implicit_sync)
5112 flags |= RADEON_FLAG_IMPLICIT_SYNC;
5113
5114 if (dedicate_info) {
5115 mem->image = radv_image_from_handle(dedicate_info->image);
5116 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
5117 } else {
5118 mem->image = NULL;
5119 mem->buffer = NULL;
5120 }
5121
5122 float priority_float = 0.5;
5123 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
5124 vk_find_struct_const(pAllocateInfo->pNext,
5125 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
5126 if (priority_ext)
5127 priority_float = priority_ext->priority;
5128
5129 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
5130 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
5131
5132 mem->user_ptr = NULL;
5133 mem->bo = NULL;
5134
5135 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
5136 mem->android_hardware_buffer = NULL;
5137 #endif
5138
5139 if (ahb_import_info) {
5140 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
5141 if (result != VK_SUCCESS)
5142 goto fail;
5143 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
5144 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
5145 if (result != VK_SUCCESS)
5146 goto fail;
5147 } else if (import_info) {
5148 assert(import_info->handleType ==
5149 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5150 import_info->handleType ==
5151 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5152 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
5153 priority, NULL);
5154 if (!mem->bo) {
5155 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5156 goto fail;
5157 } else {
5158 close(import_info->fd);
5159 }
5160 } else if (host_ptr_info) {
5161 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
5162 assert(radv_is_mem_type_gtt_cached(mem_type_index));
5163 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
5164 pAllocateInfo->allocationSize,
5165 priority);
5166 if (!mem->bo) {
5167 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
5168 goto fail;
5169 } else {
5170 mem->user_ptr = host_ptr_info->pHostPointer;
5171 }
5172 } else {
5173 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
5174 if (radv_is_mem_type_gtt_wc(mem_type_index) ||
5175 radv_is_mem_type_gtt_cached(mem_type_index))
5176 domain = RADEON_DOMAIN_GTT;
5177 else
5178 domain = RADEON_DOMAIN_VRAM;
5179
5180 if (radv_is_mem_type_vram(mem_type_index))
5181 flags |= RADEON_FLAG_NO_CPU_ACCESS;
5182 else
5183 flags |= RADEON_FLAG_CPU_ACCESS;
5184
5185 if (radv_is_mem_type_gtt_wc(mem_type_index))
5186 flags |= RADEON_FLAG_GTT_WC;
5187
5188 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
5189 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
5190 if (device->use_global_bo_list) {
5191 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
5192 }
5193 }
5194
5195 if (radv_is_mem_type_uncached(mem_type_index)) {
5196 assert(device->physical_device->rad_info.has_l2_uncached);
5197 flags |= RADEON_FLAG_VA_UNCACHED;
5198 }
5199
5200 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
5201 domain, flags, priority);
5202
5203 if (!mem->bo) {
5204 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
5205 goto fail;
5206 }
5207 mem->type_index = mem_type_index;
5208 }
5209
5210 result = radv_bo_list_add(device, mem->bo);
5211 if (result != VK_SUCCESS)
5212 goto fail;
5213
5214 *pMem = radv_device_memory_to_handle(mem);
5215
5216 return VK_SUCCESS;
5217
5218 fail:
5219 radv_free_memory(device, pAllocator,mem);
5220
5221 return result;
5222 }
5223
5224 VkResult radv_AllocateMemory(
5225 VkDevice _device,
5226 const VkMemoryAllocateInfo* pAllocateInfo,
5227 const VkAllocationCallbacks* pAllocator,
5228 VkDeviceMemory* pMem)
5229 {
5230 RADV_FROM_HANDLE(radv_device, device, _device);
5231 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
5232 }
5233
5234 void radv_FreeMemory(
5235 VkDevice _device,
5236 VkDeviceMemory _mem,
5237 const VkAllocationCallbacks* pAllocator)
5238 {
5239 RADV_FROM_HANDLE(radv_device, device, _device);
5240 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
5241
5242 radv_free_memory(device, pAllocator, mem);
5243 }
5244
5245 VkResult radv_MapMemory(
5246 VkDevice _device,
5247 VkDeviceMemory _memory,
5248 VkDeviceSize offset,
5249 VkDeviceSize size,
5250 VkMemoryMapFlags flags,
5251 void** ppData)
5252 {
5253 RADV_FROM_HANDLE(radv_device, device, _device);
5254 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5255
5256 if (mem == NULL) {
5257 *ppData = NULL;
5258 return VK_SUCCESS;
5259 }
5260
5261 if (mem->user_ptr)
5262 *ppData = mem->user_ptr;
5263 else
5264 *ppData = device->ws->buffer_map(mem->bo);
5265
5266 if (*ppData) {
5267 *ppData += offset;
5268 return VK_SUCCESS;
5269 }
5270
5271 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
5272 }
5273
5274 void radv_UnmapMemory(
5275 VkDevice _device,
5276 VkDeviceMemory _memory)
5277 {
5278 RADV_FROM_HANDLE(radv_device, device, _device);
5279 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
5280
5281 if (mem == NULL)
5282 return;
5283
5284 if (mem->user_ptr == NULL)
5285 device->ws->buffer_unmap(mem->bo);
5286 }
5287
5288 VkResult radv_FlushMappedMemoryRanges(
5289 VkDevice _device,
5290 uint32_t memoryRangeCount,
5291 const VkMappedMemoryRange* pMemoryRanges)
5292 {
5293 return VK_SUCCESS;
5294 }
5295
5296 VkResult radv_InvalidateMappedMemoryRanges(
5297 VkDevice _device,
5298 uint32_t memoryRangeCount,
5299 const VkMappedMemoryRange* pMemoryRanges)
5300 {
5301 return VK_SUCCESS;
5302 }
5303
5304 void radv_GetBufferMemoryRequirements(
5305 VkDevice _device,
5306 VkBuffer _buffer,
5307 VkMemoryRequirements* pMemoryRequirements)
5308 {
5309 RADV_FROM_HANDLE(radv_device, device, _device);
5310 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5311
5312 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5313
5314 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5315 pMemoryRequirements->alignment = 4096;
5316 else
5317 pMemoryRequirements->alignment = 16;
5318
5319 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
5320 }
5321
5322 void radv_GetBufferMemoryRequirements2(
5323 VkDevice device,
5324 const VkBufferMemoryRequirementsInfo2 *pInfo,
5325 VkMemoryRequirements2 *pMemoryRequirements)
5326 {
5327 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
5328 &pMemoryRequirements->memoryRequirements);
5329 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5330 switch (ext->sType) {
5331 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5332 VkMemoryDedicatedRequirements *req =
5333 (VkMemoryDedicatedRequirements *) ext;
5334 req->requiresDedicatedAllocation = false;
5335 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5336 break;
5337 }
5338 default:
5339 break;
5340 }
5341 }
5342 }
5343
5344 void radv_GetImageMemoryRequirements(
5345 VkDevice _device,
5346 VkImage _image,
5347 VkMemoryRequirements* pMemoryRequirements)
5348 {
5349 RADV_FROM_HANDLE(radv_device, device, _device);
5350 RADV_FROM_HANDLE(radv_image, image, _image);
5351
5352 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
5353
5354 pMemoryRequirements->size = image->size;
5355 pMemoryRequirements->alignment = image->alignment;
5356 }
5357
5358 void radv_GetImageMemoryRequirements2(
5359 VkDevice device,
5360 const VkImageMemoryRequirementsInfo2 *pInfo,
5361 VkMemoryRequirements2 *pMemoryRequirements)
5362 {
5363 radv_GetImageMemoryRequirements(device, pInfo->image,
5364 &pMemoryRequirements->memoryRequirements);
5365
5366 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5367
5368 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5369 switch (ext->sType) {
5370 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5371 VkMemoryDedicatedRequirements *req =
5372 (VkMemoryDedicatedRequirements *) ext;
5373 req->requiresDedicatedAllocation = image->shareable &&
5374 image->tiling != VK_IMAGE_TILING_LINEAR;
5375 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5376 break;
5377 }
5378 default:
5379 break;
5380 }
5381 }
5382 }
5383
5384 void radv_GetImageSparseMemoryRequirements(
5385 VkDevice device,
5386 VkImage image,
5387 uint32_t* pSparseMemoryRequirementCount,
5388 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5389 {
5390 stub();
5391 }
5392
5393 void radv_GetImageSparseMemoryRequirements2(
5394 VkDevice device,
5395 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5396 uint32_t* pSparseMemoryRequirementCount,
5397 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5398 {
5399 stub();
5400 }
5401
5402 void radv_GetDeviceMemoryCommitment(
5403 VkDevice device,
5404 VkDeviceMemory memory,
5405 VkDeviceSize* pCommittedMemoryInBytes)
5406 {
5407 *pCommittedMemoryInBytes = 0;
5408 }
5409
5410 VkResult radv_BindBufferMemory2(VkDevice device,
5411 uint32_t bindInfoCount,
5412 const VkBindBufferMemoryInfo *pBindInfos)
5413 {
5414 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5415 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5416 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5417
5418 if (mem) {
5419 buffer->bo = mem->bo;
5420 buffer->offset = pBindInfos[i].memoryOffset;
5421 } else {
5422 buffer->bo = NULL;
5423 }
5424 }
5425 return VK_SUCCESS;
5426 }
5427
5428 VkResult radv_BindBufferMemory(
5429 VkDevice device,
5430 VkBuffer buffer,
5431 VkDeviceMemory memory,
5432 VkDeviceSize memoryOffset)
5433 {
5434 const VkBindBufferMemoryInfo info = {
5435 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5436 .buffer = buffer,
5437 .memory = memory,
5438 .memoryOffset = memoryOffset
5439 };
5440
5441 return radv_BindBufferMemory2(device, 1, &info);
5442 }
5443
5444 VkResult radv_BindImageMemory2(VkDevice device,
5445 uint32_t bindInfoCount,
5446 const VkBindImageMemoryInfo *pBindInfos)
5447 {
5448 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5449 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5450 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5451
5452 if (mem) {
5453 image->bo = mem->bo;
5454 image->offset = pBindInfos[i].memoryOffset;
5455 } else {
5456 image->bo = NULL;
5457 image->offset = 0;
5458 }
5459 }
5460 return VK_SUCCESS;
5461 }
5462
5463
5464 VkResult radv_BindImageMemory(
5465 VkDevice device,
5466 VkImage image,
5467 VkDeviceMemory memory,
5468 VkDeviceSize memoryOffset)
5469 {
5470 const VkBindImageMemoryInfo info = {
5471 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5472 .image = image,
5473 .memory = memory,
5474 .memoryOffset = memoryOffset
5475 };
5476
5477 return radv_BindImageMemory2(device, 1, &info);
5478 }
5479
5480 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5481 {
5482 return info->bufferBindCount ||
5483 info->imageOpaqueBindCount ||
5484 info->imageBindCount ||
5485 info->waitSemaphoreCount ||
5486 info->signalSemaphoreCount;
5487 }
5488
5489 VkResult radv_QueueBindSparse(
5490 VkQueue _queue,
5491 uint32_t bindInfoCount,
5492 const VkBindSparseInfo* pBindInfo,
5493 VkFence fence)
5494 {
5495 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5496 VkResult result;
5497 uint32_t fence_idx = 0;
5498
5499 if (fence != VK_NULL_HANDLE) {
5500 for (uint32_t i = 0; i < bindInfoCount; ++i)
5501 if (radv_sparse_bind_has_effects(pBindInfo + i))
5502 fence_idx = i;
5503 } else
5504 fence_idx = UINT32_MAX;
5505
5506 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5507 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5508 continue;
5509
5510 const VkTimelineSemaphoreSubmitInfo *timeline_info =
5511 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO);
5512
5513 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5514 .buffer_binds = pBindInfo[i].pBufferBinds,
5515 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5516 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5517 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5518 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5519 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5520 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5521 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5522 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5523 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5524 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5525 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5526 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5527 });
5528
5529 if (result != VK_SUCCESS)
5530 return result;
5531 }
5532
5533 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5534 result = radv_signal_fence(queue, fence);
5535 if (result != VK_SUCCESS)
5536 return result;
5537 }
5538
5539 return VK_SUCCESS;
5540 }
5541
5542 VkResult radv_CreateFence(
5543 VkDevice _device,
5544 const VkFenceCreateInfo* pCreateInfo,
5545 const VkAllocationCallbacks* pAllocator,
5546 VkFence* pFence)
5547 {
5548 RADV_FROM_HANDLE(radv_device, device, _device);
5549 const VkExportFenceCreateInfo *export =
5550 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5551 VkExternalFenceHandleTypeFlags handleTypes =
5552 export ? export->handleTypes : 0;
5553
5554 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
5555 sizeof(*fence), 8,
5556 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5557
5558 if (!fence)
5559 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5560
5561 fence->fence_wsi = NULL;
5562 fence->temp_syncobj = 0;
5563 if (device->always_use_syncobj || handleTypes) {
5564 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
5565 if (ret) {
5566 vk_free2(&device->alloc, pAllocator, fence);
5567 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5568 }
5569 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
5570 device->ws->signal_syncobj(device->ws, fence->syncobj);
5571 }
5572 fence->fence = NULL;
5573 } else {
5574 fence->fence = device->ws->create_fence();
5575 if (!fence->fence) {
5576 vk_free2(&device->alloc, pAllocator, fence);
5577 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5578 }
5579 fence->syncobj = 0;
5580 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5581 device->ws->signal_fence(fence->fence);
5582 }
5583
5584 *pFence = radv_fence_to_handle(fence);
5585
5586 return VK_SUCCESS;
5587 }
5588
5589 void radv_DestroyFence(
5590 VkDevice _device,
5591 VkFence _fence,
5592 const VkAllocationCallbacks* pAllocator)
5593 {
5594 RADV_FROM_HANDLE(radv_device, device, _device);
5595 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5596
5597 if (!fence)
5598 return;
5599
5600 if (fence->temp_syncobj)
5601 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5602 if (fence->syncobj)
5603 device->ws->destroy_syncobj(device->ws, fence->syncobj);
5604 if (fence->fence)
5605 device->ws->destroy_fence(fence->fence);
5606 if (fence->fence_wsi)
5607 fence->fence_wsi->destroy(fence->fence_wsi);
5608 vk_free2(&device->alloc, pAllocator, fence);
5609 }
5610
5611
5612 uint64_t radv_get_current_time(void)
5613 {
5614 struct timespec tv;
5615 clock_gettime(CLOCK_MONOTONIC, &tv);
5616 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5617 }
5618
5619 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5620 {
5621 uint64_t current_time = radv_get_current_time();
5622
5623 timeout = MIN2(UINT64_MAX - current_time, timeout);
5624
5625 return current_time + timeout;
5626 }
5627
5628
5629 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5630 uint32_t fenceCount, const VkFence *pFences)
5631 {
5632 for (uint32_t i = 0; i < fenceCount; ++i) {
5633 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5634 if (fence->fence == NULL || fence->syncobj ||
5635 fence->temp_syncobj || fence->fence_wsi ||
5636 (!device->ws->is_fence_waitable(fence->fence)))
5637 return false;
5638 }
5639 return true;
5640 }
5641
5642 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5643 {
5644 for (uint32_t i = 0; i < fenceCount; ++i) {
5645 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5646 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
5647 return false;
5648 }
5649 return true;
5650 }
5651
5652 VkResult radv_WaitForFences(
5653 VkDevice _device,
5654 uint32_t fenceCount,
5655 const VkFence* pFences,
5656 VkBool32 waitAll,
5657 uint64_t timeout)
5658 {
5659 RADV_FROM_HANDLE(radv_device, device, _device);
5660 timeout = radv_get_absolute_timeout(timeout);
5661
5662 if (device->always_use_syncobj &&
5663 radv_all_fences_syncobj(fenceCount, pFences))
5664 {
5665 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5666 if (!handles)
5667 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5668
5669 for (uint32_t i = 0; i < fenceCount; ++i) {
5670 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5671 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
5672 }
5673
5674 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5675
5676 free(handles);
5677 return success ? VK_SUCCESS : VK_TIMEOUT;
5678 }
5679
5680 if (!waitAll && fenceCount > 1) {
5681 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5682 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5683 uint32_t wait_count = 0;
5684 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5685 if (!fences)
5686 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5687
5688 for (uint32_t i = 0; i < fenceCount; ++i) {
5689 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5690
5691 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
5692 free(fences);
5693 return VK_SUCCESS;
5694 }
5695
5696 fences[wait_count++] = fence->fence;
5697 }
5698
5699 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5700 waitAll, timeout - radv_get_current_time());
5701
5702 free(fences);
5703 return success ? VK_SUCCESS : VK_TIMEOUT;
5704 }
5705
5706 while(radv_get_current_time() <= timeout) {
5707 for (uint32_t i = 0; i < fenceCount; ++i) {
5708 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5709 return VK_SUCCESS;
5710 }
5711 }
5712 return VK_TIMEOUT;
5713 }
5714
5715 for (uint32_t i = 0; i < fenceCount; ++i) {
5716 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5717 bool expired = false;
5718
5719 if (fence->temp_syncobj) {
5720 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
5721 return VK_TIMEOUT;
5722 continue;
5723 }
5724
5725 if (fence->syncobj) {
5726 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
5727 return VK_TIMEOUT;
5728 continue;
5729 }
5730
5731 if (fence->fence) {
5732 if (!device->ws->is_fence_waitable(fence->fence)) {
5733 while(!device->ws->is_fence_waitable(fence->fence) &&
5734 radv_get_current_time() <= timeout)
5735 /* Do nothing */;
5736 }
5737
5738 expired = device->ws->fence_wait(device->ws,
5739 fence->fence,
5740 true, timeout);
5741 if (!expired)
5742 return VK_TIMEOUT;
5743 }
5744
5745 if (fence->fence_wsi) {
5746 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
5747 if (result != VK_SUCCESS)
5748 return result;
5749 }
5750 }
5751
5752 return VK_SUCCESS;
5753 }
5754
5755 VkResult radv_ResetFences(VkDevice _device,
5756 uint32_t fenceCount,
5757 const VkFence *pFences)
5758 {
5759 RADV_FROM_HANDLE(radv_device, device, _device);
5760
5761 for (unsigned i = 0; i < fenceCount; ++i) {
5762 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5763 if (fence->fence)
5764 device->ws->reset_fence(fence->fence);
5765
5766 /* Per spec, we first restore the permanent payload, and then reset, so
5767 * having a temp syncobj should not skip resetting the permanent syncobj. */
5768 if (fence->temp_syncobj) {
5769 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5770 fence->temp_syncobj = 0;
5771 }
5772
5773 if (fence->syncobj) {
5774 device->ws->reset_syncobj(device->ws, fence->syncobj);
5775 }
5776 }
5777
5778 return VK_SUCCESS;
5779 }
5780
5781 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5782 {
5783 RADV_FROM_HANDLE(radv_device, device, _device);
5784 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5785
5786 if (fence->temp_syncobj) {
5787 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
5788 return success ? VK_SUCCESS : VK_NOT_READY;
5789 }
5790
5791 if (fence->syncobj) {
5792 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
5793 return success ? VK_SUCCESS : VK_NOT_READY;
5794 }
5795
5796 if (fence->fence) {
5797 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
5798 return VK_NOT_READY;
5799 }
5800 if (fence->fence_wsi) {
5801 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
5802
5803 if (result != VK_SUCCESS) {
5804 if (result == VK_TIMEOUT)
5805 return VK_NOT_READY;
5806 return result;
5807 }
5808 }
5809 return VK_SUCCESS;
5810 }
5811
5812
5813 // Queue semaphore functions
5814
5815 static void
5816 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5817 {
5818 timeline->highest_signaled = value;
5819 timeline->highest_submitted = value;
5820 list_inithead(&timeline->points);
5821 list_inithead(&timeline->free_points);
5822 list_inithead(&timeline->waiters);
5823 pthread_mutex_init(&timeline->mutex, NULL);
5824 }
5825
5826 static void
5827 radv_destroy_timeline(struct radv_device *device,
5828 struct radv_timeline *timeline)
5829 {
5830 list_for_each_entry_safe(struct radv_timeline_point, point,
5831 &timeline->free_points, list) {
5832 list_del(&point->list);
5833 device->ws->destroy_syncobj(device->ws, point->syncobj);
5834 free(point);
5835 }
5836 list_for_each_entry_safe(struct radv_timeline_point, point,
5837 &timeline->points, list) {
5838 list_del(&point->list);
5839 device->ws->destroy_syncobj(device->ws, point->syncobj);
5840 free(point);
5841 }
5842 pthread_mutex_destroy(&timeline->mutex);
5843 }
5844
5845 static void
5846 radv_timeline_gc_locked(struct radv_device *device,
5847 struct radv_timeline *timeline)
5848 {
5849 list_for_each_entry_safe(struct radv_timeline_point, point,
5850 &timeline->points, list) {
5851 if (point->wait_count || point->value > timeline->highest_submitted)
5852 return;
5853
5854 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5855 timeline->highest_signaled = point->value;
5856 list_del(&point->list);
5857 list_add(&point->list, &timeline->free_points);
5858 }
5859 }
5860 }
5861
5862 static struct radv_timeline_point *
5863 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5864 struct radv_timeline *timeline,
5865 uint64_t p)
5866 {
5867 radv_timeline_gc_locked(device, timeline);
5868
5869 if (p <= timeline->highest_signaled)
5870 return NULL;
5871
5872 list_for_each_entry(struct radv_timeline_point, point,
5873 &timeline->points, list) {
5874 if (point->value >= p) {
5875 ++point->wait_count;
5876 return point;
5877 }
5878 }
5879 return NULL;
5880 }
5881
5882 static struct radv_timeline_point *
5883 radv_timeline_add_point_locked(struct radv_device *device,
5884 struct radv_timeline *timeline,
5885 uint64_t p)
5886 {
5887 radv_timeline_gc_locked(device, timeline);
5888
5889 struct radv_timeline_point *ret = NULL;
5890 struct radv_timeline_point *prev = NULL;
5891
5892 if (p <= timeline->highest_signaled)
5893 return NULL;
5894
5895 list_for_each_entry(struct radv_timeline_point, point,
5896 &timeline->points, list) {
5897 if (point->value == p) {
5898 return NULL;
5899 }
5900
5901 if (point->value < p)
5902 prev = point;
5903 }
5904
5905 if (list_is_empty(&timeline->free_points)) {
5906 ret = malloc(sizeof(struct radv_timeline_point));
5907 device->ws->create_syncobj(device->ws, &ret->syncobj);
5908 } else {
5909 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5910 list_del(&ret->list);
5911
5912 device->ws->reset_syncobj(device->ws, ret->syncobj);
5913 }
5914
5915 ret->value = p;
5916 ret->wait_count = 1;
5917
5918 if (prev) {
5919 list_add(&ret->list, &prev->list);
5920 } else {
5921 list_addtail(&ret->list, &timeline->points);
5922 }
5923 return ret;
5924 }
5925
5926
5927 static VkResult
5928 radv_timeline_wait_locked(struct radv_device *device,
5929 struct radv_timeline *timeline,
5930 uint64_t value,
5931 uint64_t abs_timeout)
5932 {
5933 while(timeline->highest_submitted < value) {
5934 struct timespec abstime;
5935 timespec_from_nsec(&abstime, abs_timeout);
5936
5937 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5938
5939 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5940 return VK_TIMEOUT;
5941 }
5942
5943 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5944 if (!point)
5945 return VK_SUCCESS;
5946
5947 pthread_mutex_unlock(&timeline->mutex);
5948
5949 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5950
5951 pthread_mutex_lock(&timeline->mutex);
5952 point->wait_count--;
5953 return success ? VK_SUCCESS : VK_TIMEOUT;
5954 }
5955
5956 static void
5957 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5958 struct list_head *processing_list)
5959 {
5960 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5961 &timeline->waiters, list) {
5962 if (waiter->value > timeline->highest_submitted)
5963 continue;
5964
5965 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5966 list_addtail(&waiter->submission->processing_list, processing_list);
5967 }
5968 list_del(&waiter->list);
5969 }
5970 }
5971
5972 static
5973 void radv_destroy_semaphore_part(struct radv_device *device,
5974 struct radv_semaphore_part *part)
5975 {
5976 switch(part->kind) {
5977 case RADV_SEMAPHORE_NONE:
5978 break;
5979 case RADV_SEMAPHORE_WINSYS:
5980 device->ws->destroy_sem(part->ws_sem);
5981 break;
5982 case RADV_SEMAPHORE_TIMELINE:
5983 radv_destroy_timeline(device, &part->timeline);
5984 break;
5985 case RADV_SEMAPHORE_SYNCOBJ:
5986 device->ws->destroy_syncobj(device->ws, part->syncobj);
5987 break;
5988 }
5989 part->kind = RADV_SEMAPHORE_NONE;
5990 }
5991
5992 static VkSemaphoreTypeKHR
5993 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5994 {
5995 const VkSemaphoreTypeCreateInfo *type_info =
5996 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO);
5997
5998 if (!type_info)
5999 return VK_SEMAPHORE_TYPE_BINARY;
6000
6001 if (initial_value)
6002 *initial_value = type_info->initialValue;
6003 return type_info->semaphoreType;
6004 }
6005
6006 VkResult radv_CreateSemaphore(
6007 VkDevice _device,
6008 const VkSemaphoreCreateInfo* pCreateInfo,
6009 const VkAllocationCallbacks* pAllocator,
6010 VkSemaphore* pSemaphore)
6011 {
6012 RADV_FROM_HANDLE(radv_device, device, _device);
6013 const VkExportSemaphoreCreateInfo *export =
6014 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
6015 VkExternalSemaphoreHandleTypeFlags handleTypes =
6016 export ? export->handleTypes : 0;
6017 uint64_t initial_value = 0;
6018 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
6019
6020 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
6021 sizeof(*sem), 8,
6022 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6023 if (!sem)
6024 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6025
6026 sem->temporary.kind = RADV_SEMAPHORE_NONE;
6027 sem->permanent.kind = RADV_SEMAPHORE_NONE;
6028
6029 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
6030 radv_create_timeline(&sem->permanent.timeline, initial_value);
6031 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
6032 } else if (device->always_use_syncobj || handleTypes) {
6033 assert (device->physical_device->rad_info.has_syncobj);
6034 int ret = device->ws->create_syncobj(device->ws, &sem->permanent.syncobj);
6035 if (ret) {
6036 vk_free2(&device->alloc, pAllocator, sem);
6037 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6038 }
6039 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
6040 } else {
6041 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
6042 if (!sem->permanent.ws_sem) {
6043 vk_free2(&device->alloc, pAllocator, sem);
6044 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6045 }
6046 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
6047 }
6048
6049 *pSemaphore = radv_semaphore_to_handle(sem);
6050 return VK_SUCCESS;
6051 }
6052
6053 void radv_DestroySemaphore(
6054 VkDevice _device,
6055 VkSemaphore _semaphore,
6056 const VkAllocationCallbacks* pAllocator)
6057 {
6058 RADV_FROM_HANDLE(radv_device, device, _device);
6059 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
6060 if (!_semaphore)
6061 return;
6062
6063 radv_destroy_semaphore_part(device, &sem->temporary);
6064 radv_destroy_semaphore_part(device, &sem->permanent);
6065 vk_free2(&device->alloc, pAllocator, sem);
6066 }
6067
6068 VkResult
6069 radv_GetSemaphoreCounterValue(VkDevice _device,
6070 VkSemaphore _semaphore,
6071 uint64_t* pValue)
6072 {
6073 RADV_FROM_HANDLE(radv_device, device, _device);
6074 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
6075
6076 struct radv_semaphore_part *part =
6077 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6078
6079 switch (part->kind) {
6080 case RADV_SEMAPHORE_TIMELINE: {
6081 pthread_mutex_lock(&part->timeline.mutex);
6082 radv_timeline_gc_locked(device, &part->timeline);
6083 *pValue = part->timeline.highest_signaled;
6084 pthread_mutex_unlock(&part->timeline.mutex);
6085 return VK_SUCCESS;
6086 }
6087 case RADV_SEMAPHORE_NONE:
6088 case RADV_SEMAPHORE_SYNCOBJ:
6089 case RADV_SEMAPHORE_WINSYS:
6090 unreachable("Invalid semaphore type");
6091 }
6092 unreachable("Unhandled semaphore type");
6093 }
6094
6095
6096 static VkResult
6097 radv_wait_timelines(struct radv_device *device,
6098 const VkSemaphoreWaitInfo* pWaitInfo,
6099 uint64_t abs_timeout)
6100 {
6101 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
6102 for (;;) {
6103 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6104 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6105 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
6106 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
6107 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
6108
6109 if (result == VK_SUCCESS)
6110 return VK_SUCCESS;
6111 }
6112 if (radv_get_current_time() > abs_timeout)
6113 return VK_TIMEOUT;
6114 }
6115 }
6116
6117 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
6118 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
6119 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
6120 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
6121 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
6122
6123 if (result != VK_SUCCESS)
6124 return result;
6125 }
6126 return VK_SUCCESS;
6127 }
6128 VkResult
6129 radv_WaitSemaphores(VkDevice _device,
6130 const VkSemaphoreWaitInfo* pWaitInfo,
6131 uint64_t timeout)
6132 {
6133 RADV_FROM_HANDLE(radv_device, device, _device);
6134 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
6135 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
6136 }
6137
6138 VkResult
6139 radv_SignalSemaphore(VkDevice _device,
6140 const VkSemaphoreSignalInfo* pSignalInfo)
6141 {
6142 RADV_FROM_HANDLE(radv_device, device, _device);
6143 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
6144
6145 struct radv_semaphore_part *part =
6146 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
6147
6148 switch(part->kind) {
6149 case RADV_SEMAPHORE_TIMELINE: {
6150 pthread_mutex_lock(&part->timeline.mutex);
6151 radv_timeline_gc_locked(device, &part->timeline);
6152 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
6153 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
6154
6155 struct list_head processing_list;
6156 list_inithead(&processing_list);
6157 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
6158 pthread_mutex_unlock(&part->timeline.mutex);
6159
6160 return radv_process_submissions(&processing_list);
6161 }
6162 case RADV_SEMAPHORE_NONE:
6163 case RADV_SEMAPHORE_SYNCOBJ:
6164 case RADV_SEMAPHORE_WINSYS:
6165 unreachable("Invalid semaphore type");
6166 }
6167 return VK_SUCCESS;
6168 }
6169
6170
6171
6172 VkResult radv_CreateEvent(
6173 VkDevice _device,
6174 const VkEventCreateInfo* pCreateInfo,
6175 const VkAllocationCallbacks* pAllocator,
6176 VkEvent* pEvent)
6177 {
6178 RADV_FROM_HANDLE(radv_device, device, _device);
6179 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
6180 sizeof(*event), 8,
6181 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6182
6183 if (!event)
6184 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6185
6186 event->bo = device->ws->buffer_create(device->ws, 8, 8,
6187 RADEON_DOMAIN_GTT,
6188 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
6189 RADV_BO_PRIORITY_FENCE);
6190 if (!event->bo) {
6191 vk_free2(&device->alloc, pAllocator, event);
6192 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6193 }
6194
6195 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
6196
6197 *pEvent = radv_event_to_handle(event);
6198
6199 return VK_SUCCESS;
6200 }
6201
6202 void radv_DestroyEvent(
6203 VkDevice _device,
6204 VkEvent _event,
6205 const VkAllocationCallbacks* pAllocator)
6206 {
6207 RADV_FROM_HANDLE(radv_device, device, _device);
6208 RADV_FROM_HANDLE(radv_event, event, _event);
6209
6210 if (!event)
6211 return;
6212 device->ws->buffer_destroy(event->bo);
6213 vk_free2(&device->alloc, pAllocator, event);
6214 }
6215
6216 VkResult radv_GetEventStatus(
6217 VkDevice _device,
6218 VkEvent _event)
6219 {
6220 RADV_FROM_HANDLE(radv_event, event, _event);
6221
6222 if (*event->map == 1)
6223 return VK_EVENT_SET;
6224 return VK_EVENT_RESET;
6225 }
6226
6227 VkResult radv_SetEvent(
6228 VkDevice _device,
6229 VkEvent _event)
6230 {
6231 RADV_FROM_HANDLE(radv_event, event, _event);
6232 *event->map = 1;
6233
6234 return VK_SUCCESS;
6235 }
6236
6237 VkResult radv_ResetEvent(
6238 VkDevice _device,
6239 VkEvent _event)
6240 {
6241 RADV_FROM_HANDLE(radv_event, event, _event);
6242 *event->map = 0;
6243
6244 return VK_SUCCESS;
6245 }
6246
6247 VkResult radv_CreateBuffer(
6248 VkDevice _device,
6249 const VkBufferCreateInfo* pCreateInfo,
6250 const VkAllocationCallbacks* pAllocator,
6251 VkBuffer* pBuffer)
6252 {
6253 RADV_FROM_HANDLE(radv_device, device, _device);
6254 struct radv_buffer *buffer;
6255
6256 if (pCreateInfo->size > RADV_MAX_MEMORY_ALLOCATION_SIZE)
6257 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
6258
6259 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
6260
6261 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
6262 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6263 if (buffer == NULL)
6264 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6265
6266 buffer->size = pCreateInfo->size;
6267 buffer->usage = pCreateInfo->usage;
6268 buffer->bo = NULL;
6269 buffer->offset = 0;
6270 buffer->flags = pCreateInfo->flags;
6271
6272 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
6273 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
6274
6275 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
6276 buffer->bo = device->ws->buffer_create(device->ws,
6277 align64(buffer->size, 4096),
6278 4096, 0, RADEON_FLAG_VIRTUAL,
6279 RADV_BO_PRIORITY_VIRTUAL);
6280 if (!buffer->bo) {
6281 vk_free2(&device->alloc, pAllocator, buffer);
6282 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6283 }
6284 }
6285
6286 *pBuffer = radv_buffer_to_handle(buffer);
6287
6288 return VK_SUCCESS;
6289 }
6290
6291 void radv_DestroyBuffer(
6292 VkDevice _device,
6293 VkBuffer _buffer,
6294 const VkAllocationCallbacks* pAllocator)
6295 {
6296 RADV_FROM_HANDLE(radv_device, device, _device);
6297 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
6298
6299 if (!buffer)
6300 return;
6301
6302 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
6303 device->ws->buffer_destroy(buffer->bo);
6304
6305 vk_free2(&device->alloc, pAllocator, buffer);
6306 }
6307
6308 VkDeviceAddress radv_GetBufferDeviceAddress(
6309 VkDevice device,
6310 const VkBufferDeviceAddressInfo* pInfo)
6311 {
6312 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
6313 return radv_buffer_get_va(buffer->bo) + buffer->offset;
6314 }
6315
6316
6317 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device,
6318 const VkBufferDeviceAddressInfo* pInfo)
6319 {
6320 return 0;
6321 }
6322
6323 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device,
6324 const VkDeviceMemoryOpaqueCaptureAddressInfo* pInfo)
6325 {
6326 return 0;
6327 }
6328
6329 static inline unsigned
6330 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
6331 {
6332 if (stencil)
6333 return plane->surface.u.legacy.stencil_tiling_index[level];
6334 else
6335 return plane->surface.u.legacy.tiling_index[level];
6336 }
6337
6338 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
6339 {
6340 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
6341 }
6342
6343 static uint32_t
6344 radv_init_dcc_control_reg(struct radv_device *device,
6345 struct radv_image_view *iview)
6346 {
6347 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
6348 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
6349 unsigned max_compressed_block_size;
6350 unsigned independent_128b_blocks;
6351 unsigned independent_64b_blocks;
6352
6353 if (!radv_dcc_enabled(iview->image, iview->base_mip))
6354 return 0;
6355
6356 if (!device->physical_device->rad_info.has_dedicated_vram) {
6357 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6358 * dGPU and 64 for APU because all of our APUs to date use
6359 * DIMMs which have a request granularity size of 64B while all
6360 * other chips have a 32B request size.
6361 */
6362 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
6363 }
6364
6365 if (device->physical_device->rad_info.chip_class >= GFX10) {
6366 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6367 independent_64b_blocks = 0;
6368 independent_128b_blocks = 1;
6369 } else {
6370 independent_128b_blocks = 0;
6371
6372 if (iview->image->info.samples > 1) {
6373 if (iview->image->planes[0].surface.bpe == 1)
6374 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6375 else if (iview->image->planes[0].surface.bpe == 2)
6376 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6377 }
6378
6379 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6380 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6381 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6382 /* If this DCC image is potentially going to be used in texture
6383 * fetches, we need some special settings.
6384 */
6385 independent_64b_blocks = 1;
6386 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6387 } else {
6388 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6389 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6390 * big as possible for better compression state.
6391 */
6392 independent_64b_blocks = 0;
6393 max_compressed_block_size = max_uncompressed_block_size;
6394 }
6395 }
6396
6397 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6398 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6399 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6400 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6401 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6402 }
6403
6404 void
6405 radv_initialise_color_surface(struct radv_device *device,
6406 struct radv_color_buffer_info *cb,
6407 struct radv_image_view *iview)
6408 {
6409 const struct vk_format_description *desc;
6410 unsigned ntype, format, swap, endian;
6411 unsigned blend_clamp = 0, blend_bypass = 0;
6412 uint64_t va;
6413 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6414 const struct radeon_surf *surf = &plane->surface;
6415
6416 desc = vk_format_description(iview->vk_format);
6417
6418 memset(cb, 0, sizeof(*cb));
6419
6420 /* Intensity is implemented as Red, so treat it that way. */
6421 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6422
6423 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6424
6425 cb->cb_color_base = va >> 8;
6426
6427 if (device->physical_device->rad_info.chip_class >= GFX9) {
6428 struct gfx9_surf_meta_flags meta;
6429 if (iview->image->dcc_offset)
6430 meta = surf->u.gfx9.dcc;
6431 else
6432 meta = surf->u.gfx9.cmask;
6433
6434 if (device->physical_device->rad_info.chip_class >= GFX10) {
6435 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6436 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6437 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
6438 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6439 } else {
6440 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6441 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6442 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6443 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6444 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6445 }
6446
6447 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6448 cb->cb_color_base |= surf->tile_swizzle;
6449 } else {
6450 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6451 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6452
6453 cb->cb_color_base += level_info->offset >> 8;
6454 if (level_info->mode == RADEON_SURF_MODE_2D)
6455 cb->cb_color_base |= surf->tile_swizzle;
6456
6457 pitch_tile_max = level_info->nblk_x / 8 - 1;
6458 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6459 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6460
6461 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6462 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6463 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6464
6465 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6466
6467 if (radv_image_has_fmask(iview->image)) {
6468 if (device->physical_device->rad_info.chip_class >= GFX7)
6469 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6470 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6471 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6472 } else {
6473 /* This must be set for fast clear to work without FMASK. */
6474 if (device->physical_device->rad_info.chip_class >= GFX7)
6475 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6476 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6477 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6478 }
6479 }
6480
6481 /* CMASK variables */
6482 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6483 va += iview->image->cmask_offset;
6484 cb->cb_color_cmask = va >> 8;
6485
6486 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6487 va += iview->image->dcc_offset;
6488
6489 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6490 device->physical_device->rad_info.chip_class <= GFX8)
6491 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6492
6493 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6494 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6495
6496 cb->cb_dcc_base = va >> 8;
6497 cb->cb_dcc_base |= dcc_tile_swizzle;
6498
6499 /* GFX10 field has the same base shift as the GFX6 field. */
6500 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6501 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6502 S_028C6C_SLICE_MAX_GFX10(max_slice);
6503
6504 if (iview->image->info.samples > 1) {
6505 unsigned log_samples = util_logbase2(iview->image->info.samples);
6506
6507 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6508 S_028C74_NUM_FRAGMENTS(log_samples);
6509 }
6510
6511 if (radv_image_has_fmask(iview->image)) {
6512 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
6513 cb->cb_color_fmask = va >> 8;
6514 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6515 } else {
6516 cb->cb_color_fmask = cb->cb_color_base;
6517 }
6518
6519 ntype = radv_translate_color_numformat(iview->vk_format,
6520 desc,
6521 vk_format_get_first_non_void_channel(iview->vk_format));
6522 format = radv_translate_colorformat(iview->vk_format);
6523 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6524 radv_finishme("Illegal color\n");
6525 swap = radv_translate_colorswap(iview->vk_format, false);
6526 endian = radv_colorformat_endian_swap(format);
6527
6528 /* blend clamp should be set for all NORM/SRGB types */
6529 if (ntype == V_028C70_NUMBER_UNORM ||
6530 ntype == V_028C70_NUMBER_SNORM ||
6531 ntype == V_028C70_NUMBER_SRGB)
6532 blend_clamp = 1;
6533
6534 /* set blend bypass according to docs if SINT/UINT or
6535 8/24 COLOR variants */
6536 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6537 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6538 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6539 blend_clamp = 0;
6540 blend_bypass = 1;
6541 }
6542 #if 0
6543 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6544 (format == V_028C70_COLOR_8 ||
6545 format == V_028C70_COLOR_8_8 ||
6546 format == V_028C70_COLOR_8_8_8_8))
6547 ->color_is_int8 = true;
6548 #endif
6549 cb->cb_color_info = S_028C70_FORMAT(format) |
6550 S_028C70_COMP_SWAP(swap) |
6551 S_028C70_BLEND_CLAMP(blend_clamp) |
6552 S_028C70_BLEND_BYPASS(blend_bypass) |
6553 S_028C70_SIMPLE_FLOAT(1) |
6554 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6555 ntype != V_028C70_NUMBER_SNORM &&
6556 ntype != V_028C70_NUMBER_SRGB &&
6557 format != V_028C70_COLOR_8_24 &&
6558 format != V_028C70_COLOR_24_8) |
6559 S_028C70_NUMBER_TYPE(ntype) |
6560 S_028C70_ENDIAN(endian);
6561 if (radv_image_has_fmask(iview->image)) {
6562 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6563 if (device->physical_device->rad_info.chip_class == GFX6) {
6564 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6565 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6566 }
6567
6568 if (radv_image_is_tc_compat_cmask(iview->image)) {
6569 /* Allow the texture block to read FMASK directly
6570 * without decompressing it. This bit must be cleared
6571 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6572 * otherwise the operation doesn't happen.
6573 */
6574 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6575
6576 /* Set CMASK into a tiling format that allows the
6577 * texture block to read it.
6578 */
6579 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6580 }
6581 }
6582
6583 if (radv_image_has_cmask(iview->image) &&
6584 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6585 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6586
6587 if (radv_dcc_enabled(iview->image, iview->base_mip))
6588 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6589
6590 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6591
6592 /* This must be set for fast clear to work without FMASK. */
6593 if (!radv_image_has_fmask(iview->image) &&
6594 device->physical_device->rad_info.chip_class == GFX6) {
6595 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6596 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6597 }
6598
6599 if (device->physical_device->rad_info.chip_class >= GFX9) {
6600 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6601
6602 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6603 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6604 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6605 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6606
6607 if (device->physical_device->rad_info.chip_class >= GFX10) {
6608 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6609
6610 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6611 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6612 S_028EE0_RESOURCE_LEVEL(1);
6613 } else {
6614 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6615 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6616 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6617 }
6618
6619 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6620 S_028C68_MIP0_HEIGHT(height - 1) |
6621 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6622 }
6623 }
6624
6625 static unsigned
6626 radv_calc_decompress_on_z_planes(struct radv_device *device,
6627 struct radv_image_view *iview)
6628 {
6629 unsigned max_zplanes = 0;
6630
6631 assert(radv_image_is_tc_compat_htile(iview->image));
6632
6633 if (device->physical_device->rad_info.chip_class >= GFX9) {
6634 /* Default value for 32-bit depth surfaces. */
6635 max_zplanes = 4;
6636
6637 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6638 iview->image->info.samples > 1)
6639 max_zplanes = 2;
6640
6641 max_zplanes = max_zplanes + 1;
6642 } else {
6643 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6644 /* Do not enable Z plane compression for 16-bit depth
6645 * surfaces because isn't supported on GFX8. Only
6646 * 32-bit depth surfaces are supported by the hardware.
6647 * This allows to maintain shader compatibility and to
6648 * reduce the number of depth decompressions.
6649 */
6650 max_zplanes = 1;
6651 } else {
6652 if (iview->image->info.samples <= 1)
6653 max_zplanes = 5;
6654 else if (iview->image->info.samples <= 4)
6655 max_zplanes = 3;
6656 else
6657 max_zplanes = 2;
6658 }
6659 }
6660
6661 return max_zplanes;
6662 }
6663
6664 void
6665 radv_initialise_ds_surface(struct radv_device *device,
6666 struct radv_ds_buffer_info *ds,
6667 struct radv_image_view *iview)
6668 {
6669 unsigned level = iview->base_mip;
6670 unsigned format, stencil_format;
6671 uint64_t va, s_offs, z_offs;
6672 bool stencil_only = false;
6673 const struct radv_image_plane *plane = &iview->image->planes[0];
6674 const struct radeon_surf *surf = &plane->surface;
6675
6676 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6677
6678 memset(ds, 0, sizeof(*ds));
6679 switch (iview->image->vk_format) {
6680 case VK_FORMAT_D24_UNORM_S8_UINT:
6681 case VK_FORMAT_X8_D24_UNORM_PACK32:
6682 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6683 ds->offset_scale = 2.0f;
6684 break;
6685 case VK_FORMAT_D16_UNORM:
6686 case VK_FORMAT_D16_UNORM_S8_UINT:
6687 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6688 ds->offset_scale = 4.0f;
6689 break;
6690 case VK_FORMAT_D32_SFLOAT:
6691 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6692 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6693 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6694 ds->offset_scale = 1.0f;
6695 break;
6696 case VK_FORMAT_S8_UINT:
6697 stencil_only = true;
6698 break;
6699 default:
6700 break;
6701 }
6702
6703 format = radv_translate_dbformat(iview->image->vk_format);
6704 stencil_format = surf->has_stencil ?
6705 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6706
6707 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6708 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6709 S_028008_SLICE_MAX(max_slice);
6710 if (device->physical_device->rad_info.chip_class >= GFX10) {
6711 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6712 S_028008_SLICE_MAX_HI(max_slice >> 11);
6713 }
6714
6715 ds->db_htile_data_base = 0;
6716 ds->db_htile_surface = 0;
6717
6718 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6719 s_offs = z_offs = va;
6720
6721 if (device->physical_device->rad_info.chip_class >= GFX9) {
6722 assert(surf->u.gfx9.surf_offset == 0);
6723 s_offs += surf->u.gfx9.stencil_offset;
6724
6725 ds->db_z_info = S_028038_FORMAT(format) |
6726 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6727 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6728 S_028038_MAXMIP(iview->image->info.levels - 1) |
6729 S_028038_ZRANGE_PRECISION(1);
6730 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6731 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6732
6733 if (device->physical_device->rad_info.chip_class == GFX9) {
6734 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6735 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6736 }
6737
6738 ds->db_depth_view |= S_028008_MIPID(level);
6739 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6740 S_02801C_Y_MAX(iview->image->info.height - 1);
6741
6742 if (radv_htile_enabled(iview->image, level)) {
6743 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6744
6745 if (radv_image_is_tc_compat_htile(iview->image)) {
6746 unsigned max_zplanes =
6747 radv_calc_decompress_on_z_planes(device, iview);
6748
6749 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6750
6751 if (device->physical_device->rad_info.chip_class >= GFX10) {
6752 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6753 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6754 } else {
6755 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6756 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6757 }
6758 }
6759
6760 if (!surf->has_stencil)
6761 /* Use all of the htile_buffer for depth if there's no stencil. */
6762 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6763 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6764 iview->image->htile_offset;
6765 ds->db_htile_data_base = va >> 8;
6766 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6767 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
6768
6769 if (device->physical_device->rad_info.chip_class == GFX9) {
6770 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
6771 }
6772 }
6773 } else {
6774 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6775
6776 if (stencil_only)
6777 level_info = &surf->u.legacy.stencil_level[level];
6778
6779 z_offs += surf->u.legacy.level[level].offset;
6780 s_offs += surf->u.legacy.stencil_level[level].offset;
6781
6782 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6783 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6784 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6785
6786 if (iview->image->info.samples > 1)
6787 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6788
6789 if (device->physical_device->rad_info.chip_class >= GFX7) {
6790 struct radeon_info *info = &device->physical_device->rad_info;
6791 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6792 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6793 unsigned macro_index = surf->u.legacy.macro_tile_index;
6794 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6795 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6796 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6797
6798 if (stencil_only)
6799 tile_mode = stencil_tile_mode;
6800
6801 ds->db_depth_info |=
6802 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6803 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6804 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6805 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6806 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6807 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6808 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6809 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6810 } else {
6811 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6812 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6813 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6814 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6815 if (stencil_only)
6816 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6817 }
6818
6819 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6820 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6821 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6822
6823 if (radv_htile_enabled(iview->image, level)) {
6824 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6825
6826 if (!surf->has_stencil &&
6827 !radv_image_is_tc_compat_htile(iview->image))
6828 /* Use all of the htile_buffer for depth if there's no stencil. */
6829 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6830
6831 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6832 iview->image->htile_offset;
6833 ds->db_htile_data_base = va >> 8;
6834 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6835
6836 if (radv_image_is_tc_compat_htile(iview->image)) {
6837 unsigned max_zplanes =
6838 radv_calc_decompress_on_z_planes(device, iview);
6839
6840 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6841 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6842 }
6843 }
6844 }
6845
6846 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6847 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6848 }
6849
6850 VkResult radv_CreateFramebuffer(
6851 VkDevice _device,
6852 const VkFramebufferCreateInfo* pCreateInfo,
6853 const VkAllocationCallbacks* pAllocator,
6854 VkFramebuffer* pFramebuffer)
6855 {
6856 RADV_FROM_HANDLE(radv_device, device, _device);
6857 struct radv_framebuffer *framebuffer;
6858 const VkFramebufferAttachmentsCreateInfo *imageless_create_info =
6859 vk_find_struct_const(pCreateInfo->pNext,
6860 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO);
6861
6862 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6863
6864 size_t size = sizeof(*framebuffer);
6865 if (!imageless_create_info)
6866 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6867 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
6868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6869 if (framebuffer == NULL)
6870 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6871
6872 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6873 framebuffer->width = pCreateInfo->width;
6874 framebuffer->height = pCreateInfo->height;
6875 framebuffer->layers = pCreateInfo->layers;
6876 if (imageless_create_info) {
6877 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6878 const VkFramebufferAttachmentImageInfo *attachment =
6879 imageless_create_info->pAttachmentImageInfos + i;
6880 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6881 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6882 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6883 }
6884 } else {
6885 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6886 VkImageView _iview = pCreateInfo->pAttachments[i];
6887 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6888 framebuffer->attachments[i] = iview;
6889 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6890 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6891 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6892 }
6893 }
6894
6895 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6896 return VK_SUCCESS;
6897 }
6898
6899 void radv_DestroyFramebuffer(
6900 VkDevice _device,
6901 VkFramebuffer _fb,
6902 const VkAllocationCallbacks* pAllocator)
6903 {
6904 RADV_FROM_HANDLE(radv_device, device, _device);
6905 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6906
6907 if (!fb)
6908 return;
6909 vk_free2(&device->alloc, pAllocator, fb);
6910 }
6911
6912 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6913 {
6914 switch (address_mode) {
6915 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6916 return V_008F30_SQ_TEX_WRAP;
6917 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6918 return V_008F30_SQ_TEX_MIRROR;
6919 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6920 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6921 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6922 return V_008F30_SQ_TEX_CLAMP_BORDER;
6923 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6924 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6925 default:
6926 unreachable("illegal tex wrap mode");
6927 break;
6928 }
6929 }
6930
6931 static unsigned
6932 radv_tex_compare(VkCompareOp op)
6933 {
6934 switch (op) {
6935 case VK_COMPARE_OP_NEVER:
6936 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6937 case VK_COMPARE_OP_LESS:
6938 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6939 case VK_COMPARE_OP_EQUAL:
6940 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6941 case VK_COMPARE_OP_LESS_OR_EQUAL:
6942 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6943 case VK_COMPARE_OP_GREATER:
6944 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6945 case VK_COMPARE_OP_NOT_EQUAL:
6946 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6947 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6948 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6949 case VK_COMPARE_OP_ALWAYS:
6950 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6951 default:
6952 unreachable("illegal compare mode");
6953 break;
6954 }
6955 }
6956
6957 static unsigned
6958 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6959 {
6960 switch (filter) {
6961 case VK_FILTER_NEAREST:
6962 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6963 V_008F38_SQ_TEX_XY_FILTER_POINT);
6964 case VK_FILTER_LINEAR:
6965 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6966 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6967 case VK_FILTER_CUBIC_IMG:
6968 default:
6969 fprintf(stderr, "illegal texture filter");
6970 return 0;
6971 }
6972 }
6973
6974 static unsigned
6975 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6976 {
6977 switch (mode) {
6978 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6979 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6980 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6981 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6982 default:
6983 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6984 }
6985 }
6986
6987 static unsigned
6988 radv_tex_bordercolor(VkBorderColor bcolor)
6989 {
6990 switch (bcolor) {
6991 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6992 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6993 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6994 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6995 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6996 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6997 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6998 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6999 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
7000 default:
7001 break;
7002 }
7003 return 0;
7004 }
7005
7006 static unsigned
7007 radv_tex_aniso_filter(unsigned filter)
7008 {
7009 if (filter < 2)
7010 return 0;
7011 if (filter < 4)
7012 return 1;
7013 if (filter < 8)
7014 return 2;
7015 if (filter < 16)
7016 return 3;
7017 return 4;
7018 }
7019
7020 static unsigned
7021 radv_tex_filter_mode(VkSamplerReductionMode mode)
7022 {
7023 switch (mode) {
7024 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
7025 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7026 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
7027 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
7028 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
7029 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
7030 default:
7031 break;
7032 }
7033 return 0;
7034 }
7035
7036 static uint32_t
7037 radv_get_max_anisotropy(struct radv_device *device,
7038 const VkSamplerCreateInfo *pCreateInfo)
7039 {
7040 if (device->force_aniso >= 0)
7041 return device->force_aniso;
7042
7043 if (pCreateInfo->anisotropyEnable &&
7044 pCreateInfo->maxAnisotropy > 1.0f)
7045 return (uint32_t)pCreateInfo->maxAnisotropy;
7046
7047 return 0;
7048 }
7049
7050 static inline int S_FIXED(float value, unsigned frac_bits)
7051 {
7052 return value * (1 << frac_bits);
7053 }
7054
7055 static void
7056 radv_init_sampler(struct radv_device *device,
7057 struct radv_sampler *sampler,
7058 const VkSamplerCreateInfo *pCreateInfo)
7059 {
7060 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
7061 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
7062 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
7063 device->physical_device->rad_info.chip_class == GFX9;
7064 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
7065 unsigned depth_compare_func = V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
7066 bool trunc_coord = pCreateInfo->minFilter == VK_FILTER_NEAREST && pCreateInfo->magFilter == VK_FILTER_NEAREST;
7067
7068 const struct VkSamplerReductionModeCreateInfo *sampler_reduction =
7069 vk_find_struct_const(pCreateInfo->pNext,
7070 SAMPLER_REDUCTION_MODE_CREATE_INFO);
7071 if (sampler_reduction)
7072 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
7073
7074 if (pCreateInfo->compareEnable)
7075 depth_compare_func = radv_tex_compare(pCreateInfo->compareOp);
7076
7077 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
7078 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
7079 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
7080 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
7081 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func) |
7082 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
7083 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
7084 S_008F30_ANISO_BIAS(max_aniso_ratio) |
7085 S_008F30_DISABLE_CUBE_WRAP(0) |
7086 S_008F30_COMPAT_MODE(compat_mode) |
7087 S_008F30_FILTER_MODE(filter_mode) |
7088 S_008F30_TRUNC_COORD(trunc_coord));
7089 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
7090 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
7091 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
7092 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
7093 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
7094 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
7095 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
7096 S_008F38_MIP_POINT_PRECLAMP(0));
7097 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
7098 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
7099
7100 if (device->physical_device->rad_info.chip_class >= GFX10) {
7101 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7102 } else {
7103 sampler->state[2] |=
7104 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
7105 S_008F38_FILTER_PREC_FIX(1) |
7106 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
7107 }
7108 }
7109
7110 VkResult radv_CreateSampler(
7111 VkDevice _device,
7112 const VkSamplerCreateInfo* pCreateInfo,
7113 const VkAllocationCallbacks* pAllocator,
7114 VkSampler* pSampler)
7115 {
7116 RADV_FROM_HANDLE(radv_device, device, _device);
7117 struct radv_sampler *sampler;
7118
7119 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
7120 vk_find_struct_const(pCreateInfo->pNext,
7121 SAMPLER_YCBCR_CONVERSION_INFO);
7122
7123 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
7124
7125 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
7126 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
7127 if (!sampler)
7128 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
7129
7130 radv_init_sampler(device, sampler, pCreateInfo);
7131
7132 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
7133 *pSampler = radv_sampler_to_handle(sampler);
7134
7135 return VK_SUCCESS;
7136 }
7137
7138 void radv_DestroySampler(
7139 VkDevice _device,
7140 VkSampler _sampler,
7141 const VkAllocationCallbacks* pAllocator)
7142 {
7143 RADV_FROM_HANDLE(radv_device, device, _device);
7144 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
7145
7146 if (!sampler)
7147 return;
7148 vk_free2(&device->alloc, pAllocator, sampler);
7149 }
7150
7151 /* vk_icd.h does not declare this function, so we declare it here to
7152 * suppress Wmissing-prototypes.
7153 */
7154 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7155 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
7156
7157 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7158 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
7159 {
7160 /* For the full details on loader interface versioning, see
7161 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7162 * What follows is a condensed summary, to help you navigate the large and
7163 * confusing official doc.
7164 *
7165 * - Loader interface v0 is incompatible with later versions. We don't
7166 * support it.
7167 *
7168 * - In loader interface v1:
7169 * - The first ICD entrypoint called by the loader is
7170 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7171 * entrypoint.
7172 * - The ICD must statically expose no other Vulkan symbol unless it is
7173 * linked with -Bsymbolic.
7174 * - Each dispatchable Vulkan handle created by the ICD must be
7175 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7176 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7177 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7178 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7179 * such loader-managed surfaces.
7180 *
7181 * - Loader interface v2 differs from v1 in:
7182 * - The first ICD entrypoint called by the loader is
7183 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7184 * statically expose this entrypoint.
7185 *
7186 * - Loader interface v3 differs from v2 in:
7187 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7188 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7189 * because the loader no longer does so.
7190 */
7191 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
7192 return VK_SUCCESS;
7193 }
7194
7195 VkResult radv_GetMemoryFdKHR(VkDevice _device,
7196 const VkMemoryGetFdInfoKHR *pGetFdInfo,
7197 int *pFD)
7198 {
7199 RADV_FROM_HANDLE(radv_device, device, _device);
7200 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
7201
7202 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
7203
7204 /* At the moment, we support only the below handle types. */
7205 assert(pGetFdInfo->handleType ==
7206 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
7207 pGetFdInfo->handleType ==
7208 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
7209
7210 bool ret = radv_get_memory_fd(device, memory, pFD);
7211 if (ret == false)
7212 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
7213 return VK_SUCCESS;
7214 }
7215
7216 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
7217 VkExternalMemoryHandleTypeFlagBits handleType,
7218 int fd,
7219 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
7220 {
7221 RADV_FROM_HANDLE(radv_device, device, _device);
7222
7223 switch (handleType) {
7224 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
7225 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
7226 return VK_SUCCESS;
7227
7228 default:
7229 /* The valid usage section for this function says:
7230 *
7231 * "handleType must not be one of the handle types defined as
7232 * opaque."
7233 *
7234 * So opaque handle types fall into the default "unsupported" case.
7235 */
7236 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7237 }
7238 }
7239
7240 static VkResult radv_import_opaque_fd(struct radv_device *device,
7241 int fd,
7242 uint32_t *syncobj)
7243 {
7244 uint32_t syncobj_handle = 0;
7245 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
7246 if (ret != 0)
7247 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7248
7249 if (*syncobj)
7250 device->ws->destroy_syncobj(device->ws, *syncobj);
7251
7252 *syncobj = syncobj_handle;
7253 close(fd);
7254
7255 return VK_SUCCESS;
7256 }
7257
7258 static VkResult radv_import_sync_fd(struct radv_device *device,
7259 int fd,
7260 uint32_t *syncobj)
7261 {
7262 /* If we create a syncobj we do it locally so that if we have an error, we don't
7263 * leave a syncobj in an undetermined state in the fence. */
7264 uint32_t syncobj_handle = *syncobj;
7265 if (!syncobj_handle) {
7266 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
7267 if (ret) {
7268 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7269 }
7270 }
7271
7272 if (fd == -1) {
7273 device->ws->signal_syncobj(device->ws, syncobj_handle);
7274 } else {
7275 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
7276 if (ret != 0)
7277 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7278 }
7279
7280 *syncobj = syncobj_handle;
7281 if (fd != -1)
7282 close(fd);
7283
7284 return VK_SUCCESS;
7285 }
7286
7287 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
7288 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
7289 {
7290 RADV_FROM_HANDLE(radv_device, device, _device);
7291 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
7292 VkResult result;
7293 struct radv_semaphore_part *dst = NULL;
7294
7295 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
7296 dst = &sem->temporary;
7297 } else {
7298 dst = &sem->permanent;
7299 }
7300
7301 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
7302
7303 switch(pImportSemaphoreFdInfo->handleType) {
7304 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7305 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7306 break;
7307 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7308 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
7309 break;
7310 default:
7311 unreachable("Unhandled semaphore handle type");
7312 }
7313
7314 if (result == VK_SUCCESS) {
7315 dst->syncobj = syncobj;
7316 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
7317 }
7318
7319 return result;
7320 }
7321
7322 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
7323 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
7324 int *pFd)
7325 {
7326 RADV_FROM_HANDLE(radv_device, device, _device);
7327 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
7328 int ret;
7329 uint32_t syncobj_handle;
7330
7331 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7332 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
7333 syncobj_handle = sem->temporary.syncobj;
7334 } else {
7335 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
7336 syncobj_handle = sem->permanent.syncobj;
7337 }
7338
7339 switch(pGetFdInfo->handleType) {
7340 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
7341 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7342 break;
7343 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
7344 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7345 if (!ret) {
7346 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
7347 radv_destroy_semaphore_part(device, &sem->temporary);
7348 } else {
7349 device->ws->reset_syncobj(device->ws, syncobj_handle);
7350 }
7351 }
7352 break;
7353 default:
7354 unreachable("Unhandled semaphore handle type");
7355 }
7356
7357 if (ret)
7358 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7359 return VK_SUCCESS;
7360 }
7361
7362 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7363 VkPhysicalDevice physicalDevice,
7364 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
7365 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
7366 {
7367 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7368 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
7369
7370 if (type == VK_SEMAPHORE_TYPE_TIMELINE) {
7371 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7372 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7373 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7374
7375 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7376 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7377 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7378 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7379 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7380 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7381 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7382 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7383 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7384 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7385 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7386 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7387 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7388 } else {
7389 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7390 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7391 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7392 }
7393 }
7394
7395 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7396 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7397 {
7398 RADV_FROM_HANDLE(radv_device, device, _device);
7399 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7400 uint32_t *syncobj_dst = NULL;
7401
7402
7403 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7404 syncobj_dst = &fence->temp_syncobj;
7405 } else {
7406 syncobj_dst = &fence->syncobj;
7407 }
7408
7409 switch(pImportFenceFdInfo->handleType) {
7410 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7411 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7412 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7413 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7414 default:
7415 unreachable("Unhandled fence handle type");
7416 }
7417 }
7418
7419 VkResult radv_GetFenceFdKHR(VkDevice _device,
7420 const VkFenceGetFdInfoKHR *pGetFdInfo,
7421 int *pFd)
7422 {
7423 RADV_FROM_HANDLE(radv_device, device, _device);
7424 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7425 int ret;
7426 uint32_t syncobj_handle;
7427
7428 if (fence->temp_syncobj)
7429 syncobj_handle = fence->temp_syncobj;
7430 else
7431 syncobj_handle = fence->syncobj;
7432
7433 switch(pGetFdInfo->handleType) {
7434 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7435 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7436 break;
7437 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7438 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7439 if (!ret) {
7440 if (fence->temp_syncobj) {
7441 close (fence->temp_syncobj);
7442 fence->temp_syncobj = 0;
7443 } else {
7444 device->ws->reset_syncobj(device->ws, syncobj_handle);
7445 }
7446 }
7447 break;
7448 default:
7449 unreachable("Unhandled fence handle type");
7450 }
7451
7452 if (ret)
7453 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7454 return VK_SUCCESS;
7455 }
7456
7457 void radv_GetPhysicalDeviceExternalFenceProperties(
7458 VkPhysicalDevice physicalDevice,
7459 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7460 VkExternalFenceProperties *pExternalFenceProperties)
7461 {
7462 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7463
7464 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7465 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7466 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7467 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7468 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7469 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7470 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7471 } else {
7472 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7473 pExternalFenceProperties->compatibleHandleTypes = 0;
7474 pExternalFenceProperties->externalFenceFeatures = 0;
7475 }
7476 }
7477
7478 VkResult
7479 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7480 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7481 const VkAllocationCallbacks* pAllocator,
7482 VkDebugReportCallbackEXT* pCallback)
7483 {
7484 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7485 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7486 pCreateInfo, pAllocator, &instance->alloc,
7487 pCallback);
7488 }
7489
7490 void
7491 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7492 VkDebugReportCallbackEXT _callback,
7493 const VkAllocationCallbacks* pAllocator)
7494 {
7495 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7496 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7497 _callback, pAllocator, &instance->alloc);
7498 }
7499
7500 void
7501 radv_DebugReportMessageEXT(VkInstance _instance,
7502 VkDebugReportFlagsEXT flags,
7503 VkDebugReportObjectTypeEXT objectType,
7504 uint64_t object,
7505 size_t location,
7506 int32_t messageCode,
7507 const char* pLayerPrefix,
7508 const char* pMessage)
7509 {
7510 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7511 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7512 object, location, messageCode, pLayerPrefix, pMessage);
7513 }
7514
7515 void
7516 radv_GetDeviceGroupPeerMemoryFeatures(
7517 VkDevice device,
7518 uint32_t heapIndex,
7519 uint32_t localDeviceIndex,
7520 uint32_t remoteDeviceIndex,
7521 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7522 {
7523 assert(localDeviceIndex == remoteDeviceIndex);
7524
7525 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7526 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7527 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7528 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7529 }
7530
7531 static const VkTimeDomainEXT radv_time_domains[] = {
7532 VK_TIME_DOMAIN_DEVICE_EXT,
7533 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7534 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7535 };
7536
7537 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7538 VkPhysicalDevice physicalDevice,
7539 uint32_t *pTimeDomainCount,
7540 VkTimeDomainEXT *pTimeDomains)
7541 {
7542 int d;
7543 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7544
7545 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7546 vk_outarray_append(&out, i) {
7547 *i = radv_time_domains[d];
7548 }
7549 }
7550
7551 return vk_outarray_status(&out);
7552 }
7553
7554 static uint64_t
7555 radv_clock_gettime(clockid_t clock_id)
7556 {
7557 struct timespec current;
7558 int ret;
7559
7560 ret = clock_gettime(clock_id, &current);
7561 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7562 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7563 if (ret < 0)
7564 return 0;
7565
7566 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7567 }
7568
7569 VkResult radv_GetCalibratedTimestampsEXT(
7570 VkDevice _device,
7571 uint32_t timestampCount,
7572 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7573 uint64_t *pTimestamps,
7574 uint64_t *pMaxDeviation)
7575 {
7576 RADV_FROM_HANDLE(radv_device, device, _device);
7577 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7578 int d;
7579 uint64_t begin, end;
7580 uint64_t max_clock_period = 0;
7581
7582 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7583
7584 for (d = 0; d < timestampCount; d++) {
7585 switch (pTimestampInfos[d].timeDomain) {
7586 case VK_TIME_DOMAIN_DEVICE_EXT:
7587 pTimestamps[d] = device->ws->query_value(device->ws,
7588 RADEON_TIMESTAMP);
7589 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7590 max_clock_period = MAX2(max_clock_period, device_period);
7591 break;
7592 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7593 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7594 max_clock_period = MAX2(max_clock_period, 1);
7595 break;
7596
7597 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7598 pTimestamps[d] = begin;
7599 break;
7600 default:
7601 pTimestamps[d] = 0;
7602 break;
7603 }
7604 }
7605
7606 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7607
7608 /*
7609 * The maximum deviation is the sum of the interval over which we
7610 * perform the sampling and the maximum period of any sampled
7611 * clock. That's because the maximum skew between any two sampled
7612 * clock edges is when the sampled clock with the largest period is
7613 * sampled at the end of that period but right at the beginning of the
7614 * sampling interval and some other clock is sampled right at the
7615 * begining of its sampling period and right at the end of the
7616 * sampling interval. Let's assume the GPU has the longest clock
7617 * period and that the application is sampling GPU and monotonic:
7618 *
7619 * s e
7620 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7621 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7622 *
7623 * g
7624 * 0 1 2 3
7625 * GPU -----_____-----_____-----_____-----_____
7626 *
7627 * m
7628 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7629 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7630 *
7631 * Interval <----------------->
7632 * Deviation <-------------------------->
7633 *
7634 * s = read(raw) 2
7635 * g = read(GPU) 1
7636 * m = read(monotonic) 2
7637 * e = read(raw) b
7638 *
7639 * We round the sample interval up by one tick to cover sampling error
7640 * in the interval clock
7641 */
7642
7643 uint64_t sample_interval = end - begin + 1;
7644
7645 *pMaxDeviation = sample_interval + max_clock_period;
7646
7647 return VK_SUCCESS;
7648 }
7649
7650 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7651 VkPhysicalDevice physicalDevice,
7652 VkSampleCountFlagBits samples,
7653 VkMultisamplePropertiesEXT* pMultisampleProperties)
7654 {
7655 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7656 VK_SAMPLE_COUNT_4_BIT |
7657 VK_SAMPLE_COUNT_8_BIT)) {
7658 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7659 } else {
7660 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7661 }
7662 }