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9c82fd059f8c20808a70cc818d63f0030782e032
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static void
187 radv_handle_env_var_force_family(struct radv_physical_device *device)
188 {
189 const char *family = getenv("RADV_FORCE_FAMILY");
190 unsigned i;
191
192 if (!family)
193 return;
194
195 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
196 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
197 /* Override family and chip_class. */
198 device->rad_info.family = i;
199
200 if (i >= CHIP_VEGA10)
201 device->rad_info.chip_class = GFX9;
202 else if (i >= CHIP_TONGA)
203 device->rad_info.chip_class = VI;
204 else if (i >= CHIP_BONAIRE)
205 device->rad_info.chip_class = CIK;
206 else
207 device->rad_info.chip_class = SI;
208
209 return;
210 }
211 }
212
213 fprintf(stderr, "radv: Unknown family: %s\n", family);
214 exit(1);
215 }
216
217 static VkResult
218 radv_physical_device_init(struct radv_physical_device *device,
219 struct radv_instance *instance,
220 drmDevicePtr drm_device)
221 {
222 const char *path = drm_device->nodes[DRM_NODE_RENDER];
223 VkResult result;
224 drmVersionPtr version;
225 int fd;
226
227 fd = open(path, O_RDWR | O_CLOEXEC);
228 if (fd < 0)
229 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
230
231 version = drmGetVersion(fd);
232 if (!version) {
233 close(fd);
234 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
235 "failed to get version %s: %m", path);
236 }
237
238 if (strcmp(version->name, "amdgpu")) {
239 drmFreeVersion(version);
240 close(fd);
241 return VK_ERROR_INCOMPATIBLE_DRIVER;
242 }
243 drmFreeVersion(version);
244
245 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
246 device->instance = instance;
247 assert(strlen(path) < ARRAY_SIZE(device->path));
248 strncpy(device->path, path, ARRAY_SIZE(device->path));
249
250 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
251 instance->perftest_flags);
252 if (!device->ws) {
253 result = VK_ERROR_INCOMPATIBLE_DRIVER;
254 goto fail;
255 }
256
257 device->local_fd = fd;
258 device->ws->query_info(device->ws, &device->rad_info);
259
260 radv_handle_env_var_force_family(device);
261
262 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
263
264 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
265 device->ws->destroy(device->ws);
266 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
267 "cannot generate UUID");
268 goto fail;
269 }
270
271 /* These flags affect shader compilation. */
272 uint64_t shader_env_flags =
273 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
274 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
275
276 /* The gpu id is already embeded in the uuid so we just pass "radv"
277 * when creating the cache.
278 */
279 char buf[VK_UUID_SIZE * 2 + 1];
280 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
281 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
282
283 if (device->rad_info.chip_class < VI ||
284 device->rad_info.chip_class > GFX9)
285 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
286
287 radv_get_driver_uuid(&device->device_uuid);
288 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
289
290 if (device->rad_info.family == CHIP_STONEY ||
291 device->rad_info.chip_class >= GFX9) {
292 device->has_rbplus = true;
293 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
294 }
295
296 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
297 * on SI.
298 */
299 device->has_clear_state = device->rad_info.chip_class >= CIK;
300
301 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
302
303 /* Vega10/Raven need a special workaround for a hardware bug. */
304 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
305 device->rad_info.family == CHIP_RAVEN;
306
307 radv_physical_device_init_mem_types(device);
308 radv_fill_device_extension_table(device, &device->supported_extensions);
309
310 result = radv_init_wsi(device);
311 if (result != VK_SUCCESS) {
312 device->ws->destroy(device->ws);
313 goto fail;
314 }
315
316 return VK_SUCCESS;
317
318 fail:
319 close(fd);
320 return result;
321 }
322
323 static void
324 radv_physical_device_finish(struct radv_physical_device *device)
325 {
326 radv_finish_wsi(device);
327 device->ws->destroy(device->ws);
328 disk_cache_destroy(device->disk_cache);
329 close(device->local_fd);
330 }
331
332 static void *
333 default_alloc_func(void *pUserData, size_t size, size_t align,
334 VkSystemAllocationScope allocationScope)
335 {
336 return malloc(size);
337 }
338
339 static void *
340 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
341 size_t align, VkSystemAllocationScope allocationScope)
342 {
343 return realloc(pOriginal, size);
344 }
345
346 static void
347 default_free_func(void *pUserData, void *pMemory)
348 {
349 free(pMemory);
350 }
351
352 static const VkAllocationCallbacks default_alloc = {
353 .pUserData = NULL,
354 .pfnAllocation = default_alloc_func,
355 .pfnReallocation = default_realloc_func,
356 .pfnFree = default_free_func,
357 };
358
359 static const struct debug_control radv_debug_options[] = {
360 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
361 {"nodcc", RADV_DEBUG_NO_DCC},
362 {"shaders", RADV_DEBUG_DUMP_SHADERS},
363 {"nocache", RADV_DEBUG_NO_CACHE},
364 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
365 {"nohiz", RADV_DEBUG_NO_HIZ},
366 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
367 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
368 {"allbos", RADV_DEBUG_ALL_BOS},
369 {"noibs", RADV_DEBUG_NO_IBS},
370 {"spirv", RADV_DEBUG_DUMP_SPIRV},
371 {"vmfaults", RADV_DEBUG_VM_FAULTS},
372 {"zerovram", RADV_DEBUG_ZERO_VRAM},
373 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
374 {"nosisched", RADV_DEBUG_NO_SISCHED},
375 {"preoptir", RADV_DEBUG_PREOPTIR},
376 {NULL, 0}
377 };
378
379 const char *
380 radv_get_debug_option_name(int id)
381 {
382 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
383 return radv_debug_options[id].string;
384 }
385
386 static const struct debug_control radv_perftest_options[] = {
387 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
388 {"sisched", RADV_PERFTEST_SISCHED},
389 {"localbos", RADV_PERFTEST_LOCAL_BOS},
390 {"binning", RADV_PERFTEST_BINNING},
391 {NULL, 0}
392 };
393
394 const char *
395 radv_get_perftest_option_name(int id)
396 {
397 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
398 return radv_perftest_options[id].string;
399 }
400
401 static void
402 radv_handle_per_app_options(struct radv_instance *instance,
403 const VkApplicationInfo *info)
404 {
405 const char *name = info ? info->pApplicationName : NULL;
406
407 if (!name)
408 return;
409
410 if (!strcmp(name, "Talos - Linux - 32bit") ||
411 !strcmp(name, "Talos - Linux - 64bit")) {
412 /* Force enable LLVM sisched for Talos because it looks safe
413 * and it gives few more FPS.
414 */
415 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
416 }
417 }
418
419 static int radv_get_instance_extension_index(const char *name)
420 {
421 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
422 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
423 return i;
424 }
425 return -1;
426 }
427
428
429 VkResult radv_CreateInstance(
430 const VkInstanceCreateInfo* pCreateInfo,
431 const VkAllocationCallbacks* pAllocator,
432 VkInstance* pInstance)
433 {
434 struct radv_instance *instance;
435 VkResult result;
436
437 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
438
439 uint32_t client_version;
440 if (pCreateInfo->pApplicationInfo &&
441 pCreateInfo->pApplicationInfo->apiVersion != 0) {
442 client_version = pCreateInfo->pApplicationInfo->apiVersion;
443 } else {
444 client_version = VK_MAKE_VERSION(1, 0, 0);
445 }
446
447 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
448 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
449 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
450 "Client requested version %d.%d.%d",
451 VK_VERSION_MAJOR(client_version),
452 VK_VERSION_MINOR(client_version),
453 VK_VERSION_PATCH(client_version));
454 }
455
456 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
457 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
458 if (!instance)
459 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
460
461 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
462
463 if (pAllocator)
464 instance->alloc = *pAllocator;
465 else
466 instance->alloc = default_alloc;
467
468 instance->apiVersion = client_version;
469 instance->physicalDeviceCount = -1;
470
471 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
472 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
473 int index = radv_get_instance_extension_index(ext_name);
474
475 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
476 vk_free2(&default_alloc, pAllocator, instance);
477 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
478 }
479
480 instance->enabled_extensions.extensions[index] = true;
481 }
482
483 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
484 if (result != VK_SUCCESS) {
485 vk_free2(&default_alloc, pAllocator, instance);
486 return vk_error(result);
487 }
488
489 _mesa_locale_init();
490
491 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
492
493 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
494 radv_debug_options);
495
496 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
497 radv_perftest_options);
498
499 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
500
501 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
502 /* Disable sisched when the user requests it, this is mostly
503 * useful when the driver force-enable sisched for the given
504 * application.
505 */
506 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
507 }
508
509 *pInstance = radv_instance_to_handle(instance);
510
511 return VK_SUCCESS;
512 }
513
514 void radv_DestroyInstance(
515 VkInstance _instance,
516 const VkAllocationCallbacks* pAllocator)
517 {
518 RADV_FROM_HANDLE(radv_instance, instance, _instance);
519
520 if (!instance)
521 return;
522
523 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
524 radv_physical_device_finish(instance->physicalDevices + i);
525 }
526
527 VG(VALGRIND_DESTROY_MEMPOOL(instance));
528
529 _mesa_locale_fini();
530
531 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
532
533 vk_free(&instance->alloc, instance);
534 }
535
536 static VkResult
537 radv_enumerate_devices(struct radv_instance *instance)
538 {
539 /* TODO: Check for more devices ? */
540 drmDevicePtr devices[8];
541 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
542 int max_devices;
543
544 instance->physicalDeviceCount = 0;
545
546 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
547 if (max_devices < 1)
548 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
549
550 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
551 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
552 devices[i]->bustype == DRM_BUS_PCI &&
553 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
554
555 result = radv_physical_device_init(instance->physicalDevices +
556 instance->physicalDeviceCount,
557 instance,
558 devices[i]);
559 if (result == VK_SUCCESS)
560 ++instance->physicalDeviceCount;
561 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
562 break;
563 }
564 }
565 drmFreeDevices(devices, max_devices);
566
567 return result;
568 }
569
570 VkResult radv_EnumeratePhysicalDevices(
571 VkInstance _instance,
572 uint32_t* pPhysicalDeviceCount,
573 VkPhysicalDevice* pPhysicalDevices)
574 {
575 RADV_FROM_HANDLE(radv_instance, instance, _instance);
576 VkResult result;
577
578 if (instance->physicalDeviceCount < 0) {
579 result = radv_enumerate_devices(instance);
580 if (result != VK_SUCCESS &&
581 result != VK_ERROR_INCOMPATIBLE_DRIVER)
582 return result;
583 }
584
585 if (!pPhysicalDevices) {
586 *pPhysicalDeviceCount = instance->physicalDeviceCount;
587 } else {
588 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
589 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
590 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
591 }
592
593 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
594 : VK_SUCCESS;
595 }
596
597 VkResult radv_EnumeratePhysicalDeviceGroups(
598 VkInstance _instance,
599 uint32_t* pPhysicalDeviceGroupCount,
600 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603 VkResult result;
604
605 if (instance->physicalDeviceCount < 0) {
606 result = radv_enumerate_devices(instance);
607 if (result != VK_SUCCESS &&
608 result != VK_ERROR_INCOMPATIBLE_DRIVER)
609 return result;
610 }
611
612 if (!pPhysicalDeviceGroupProperties) {
613 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
614 } else {
615 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
616 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
617 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
618 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
619 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
620 }
621 }
622 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
623 : VK_SUCCESS;
624 }
625
626 void radv_GetPhysicalDeviceFeatures(
627 VkPhysicalDevice physicalDevice,
628 VkPhysicalDeviceFeatures* pFeatures)
629 {
630 memset(pFeatures, 0, sizeof(*pFeatures));
631
632 *pFeatures = (VkPhysicalDeviceFeatures) {
633 .robustBufferAccess = true,
634 .fullDrawIndexUint32 = true,
635 .imageCubeArray = true,
636 .independentBlend = true,
637 .geometryShader = true,
638 .tessellationShader = true,
639 .sampleRateShading = true,
640 .dualSrcBlend = true,
641 .logicOp = true,
642 .multiDrawIndirect = true,
643 .drawIndirectFirstInstance = true,
644 .depthClamp = true,
645 .depthBiasClamp = true,
646 .fillModeNonSolid = true,
647 .depthBounds = true,
648 .wideLines = true,
649 .largePoints = true,
650 .alphaToOne = true,
651 .multiViewport = true,
652 .samplerAnisotropy = true,
653 .textureCompressionETC2 = false,
654 .textureCompressionASTC_LDR = false,
655 .textureCompressionBC = true,
656 .occlusionQueryPrecise = true,
657 .pipelineStatisticsQuery = true,
658 .vertexPipelineStoresAndAtomics = true,
659 .fragmentStoresAndAtomics = true,
660 .shaderTessellationAndGeometryPointSize = true,
661 .shaderImageGatherExtended = true,
662 .shaderStorageImageExtendedFormats = true,
663 .shaderStorageImageMultisample = false,
664 .shaderUniformBufferArrayDynamicIndexing = true,
665 .shaderSampledImageArrayDynamicIndexing = true,
666 .shaderStorageBufferArrayDynamicIndexing = true,
667 .shaderStorageImageArrayDynamicIndexing = true,
668 .shaderStorageImageReadWithoutFormat = true,
669 .shaderStorageImageWriteWithoutFormat = true,
670 .shaderClipDistance = true,
671 .shaderCullDistance = true,
672 .shaderFloat64 = true,
673 .shaderInt64 = true,
674 .shaderInt16 = false,
675 .sparseBinding = true,
676 .variableMultisampleRate = true,
677 .inheritedQueries = true,
678 };
679 }
680
681 void radv_GetPhysicalDeviceFeatures2(
682 VkPhysicalDevice physicalDevice,
683 VkPhysicalDeviceFeatures2KHR *pFeatures)
684 {
685 vk_foreach_struct(ext, pFeatures->pNext) {
686 switch (ext->sType) {
687 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
688 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
689 features->variablePointersStorageBuffer = true;
690 features->variablePointers = false;
691 break;
692 }
693 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
694 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
695 features->multiview = true;
696 features->multiviewGeometryShader = true;
697 features->multiviewTessellationShader = true;
698 break;
699 }
700 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
701 VkPhysicalDeviceShaderDrawParameterFeatures *features =
702 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
703 features->shaderDrawParameters = true;
704 break;
705 }
706 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
707 VkPhysicalDeviceProtectedMemoryFeatures *features =
708 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
709 features->protectedMemory = false;
710 break;
711 }
712 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
713 VkPhysicalDevice16BitStorageFeatures *features =
714 (VkPhysicalDevice16BitStorageFeatures*)ext;
715 features->storageBuffer16BitAccess = false;
716 features->uniformAndStorageBuffer16BitAccess = false;
717 features->storagePushConstant16 = false;
718 features->storageInputOutput16 = false;
719 break;
720 }
721 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
722 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
723 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
724 features->samplerYcbcrConversion = false;
725 break;
726 }
727 default:
728 break;
729 }
730 }
731 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
732 }
733
734 void radv_GetPhysicalDeviceProperties(
735 VkPhysicalDevice physicalDevice,
736 VkPhysicalDeviceProperties* pProperties)
737 {
738 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
739 VkSampleCountFlags sample_counts = 0xf;
740
741 /* make sure that the entire descriptor set is addressable with a signed
742 * 32-bit int. So the sum of all limits scaled by descriptor size has to
743 * be at most 2 GiB. the combined image & samples object count as one of
744 * both. This limit is for the pipeline layout, not for the set layout, but
745 * there is no set limit, so we just set a pipeline limit. I don't think
746 * any app is going to hit this soon. */
747 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
748 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
749 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
750 32 /* sampler, largest when combined with image */ +
751 64 /* sampled image */ +
752 64 /* storage image */);
753
754 VkPhysicalDeviceLimits limits = {
755 .maxImageDimension1D = (1 << 14),
756 .maxImageDimension2D = (1 << 14),
757 .maxImageDimension3D = (1 << 11),
758 .maxImageDimensionCube = (1 << 14),
759 .maxImageArrayLayers = (1 << 11),
760 .maxTexelBufferElements = 128 * 1024 * 1024,
761 .maxUniformBufferRange = UINT32_MAX,
762 .maxStorageBufferRange = UINT32_MAX,
763 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
764 .maxMemoryAllocationCount = UINT32_MAX,
765 .maxSamplerAllocationCount = 64 * 1024,
766 .bufferImageGranularity = 64, /* A cache line */
767 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
768 .maxBoundDescriptorSets = MAX_SETS,
769 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
770 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
771 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
772 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
773 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
774 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
775 .maxPerStageResources = max_descriptor_set_size,
776 .maxDescriptorSetSamplers = max_descriptor_set_size,
777 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
778 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
779 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
780 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
781 .maxDescriptorSetSampledImages = max_descriptor_set_size,
782 .maxDescriptorSetStorageImages = max_descriptor_set_size,
783 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
784 .maxVertexInputAttributes = 32,
785 .maxVertexInputBindings = 32,
786 .maxVertexInputAttributeOffset = 2047,
787 .maxVertexInputBindingStride = 2048,
788 .maxVertexOutputComponents = 128,
789 .maxTessellationGenerationLevel = 64,
790 .maxTessellationPatchSize = 32,
791 .maxTessellationControlPerVertexInputComponents = 128,
792 .maxTessellationControlPerVertexOutputComponents = 128,
793 .maxTessellationControlPerPatchOutputComponents = 120,
794 .maxTessellationControlTotalOutputComponents = 4096,
795 .maxTessellationEvaluationInputComponents = 128,
796 .maxTessellationEvaluationOutputComponents = 128,
797 .maxGeometryShaderInvocations = 127,
798 .maxGeometryInputComponents = 64,
799 .maxGeometryOutputComponents = 128,
800 .maxGeometryOutputVertices = 256,
801 .maxGeometryTotalOutputComponents = 1024,
802 .maxFragmentInputComponents = 128,
803 .maxFragmentOutputAttachments = 8,
804 .maxFragmentDualSrcAttachments = 1,
805 .maxFragmentCombinedOutputResources = 8,
806 .maxComputeSharedMemorySize = 32768,
807 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
808 .maxComputeWorkGroupInvocations = 2048,
809 .maxComputeWorkGroupSize = {
810 2048,
811 2048,
812 2048
813 },
814 .subPixelPrecisionBits = 4 /* FIXME */,
815 .subTexelPrecisionBits = 4 /* FIXME */,
816 .mipmapPrecisionBits = 4 /* FIXME */,
817 .maxDrawIndexedIndexValue = UINT32_MAX,
818 .maxDrawIndirectCount = UINT32_MAX,
819 .maxSamplerLodBias = 16,
820 .maxSamplerAnisotropy = 16,
821 .maxViewports = MAX_VIEWPORTS,
822 .maxViewportDimensions = { (1 << 14), (1 << 14) },
823 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
824 .viewportSubPixelBits = 13, /* We take a float? */
825 .minMemoryMapAlignment = 4096, /* A page */
826 .minTexelBufferOffsetAlignment = 1,
827 .minUniformBufferOffsetAlignment = 4,
828 .minStorageBufferOffsetAlignment = 4,
829 .minTexelOffset = -32,
830 .maxTexelOffset = 31,
831 .minTexelGatherOffset = -32,
832 .maxTexelGatherOffset = 31,
833 .minInterpolationOffset = -2,
834 .maxInterpolationOffset = 2,
835 .subPixelInterpolationOffsetBits = 8,
836 .maxFramebufferWidth = (1 << 14),
837 .maxFramebufferHeight = (1 << 14),
838 .maxFramebufferLayers = (1 << 10),
839 .framebufferColorSampleCounts = sample_counts,
840 .framebufferDepthSampleCounts = sample_counts,
841 .framebufferStencilSampleCounts = sample_counts,
842 .framebufferNoAttachmentsSampleCounts = sample_counts,
843 .maxColorAttachments = MAX_RTS,
844 .sampledImageColorSampleCounts = sample_counts,
845 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
846 .sampledImageDepthSampleCounts = sample_counts,
847 .sampledImageStencilSampleCounts = sample_counts,
848 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
849 .maxSampleMaskWords = 1,
850 .timestampComputeAndGraphics = true,
851 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
852 .maxClipDistances = 8,
853 .maxCullDistances = 8,
854 .maxCombinedClipAndCullDistances = 8,
855 .discreteQueuePriorities = 1,
856 .pointSizeRange = { 0.125, 255.875 },
857 .lineWidthRange = { 0.0, 7.9921875 },
858 .pointSizeGranularity = (1.0 / 8.0),
859 .lineWidthGranularity = (1.0 / 128.0),
860 .strictLines = false, /* FINISHME */
861 .standardSampleLocations = true,
862 .optimalBufferCopyOffsetAlignment = 128,
863 .optimalBufferCopyRowPitchAlignment = 128,
864 .nonCoherentAtomSize = 64,
865 };
866
867 *pProperties = (VkPhysicalDeviceProperties) {
868 .apiVersion = radv_physical_device_api_version(pdevice),
869 .driverVersion = vk_get_driver_version(),
870 .vendorID = ATI_VENDOR_ID,
871 .deviceID = pdevice->rad_info.pci_id,
872 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
873 .limits = limits,
874 .sparseProperties = {0},
875 };
876
877 strcpy(pProperties->deviceName, pdevice->name);
878 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
879 }
880
881 void radv_GetPhysicalDeviceProperties2(
882 VkPhysicalDevice physicalDevice,
883 VkPhysicalDeviceProperties2KHR *pProperties)
884 {
885 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
886 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
887
888 vk_foreach_struct(ext, pProperties->pNext) {
889 switch (ext->sType) {
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
891 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
892 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
893 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
897 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
898 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
899 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
900 properties->deviceLUIDValid = false;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
904 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
905 properties->maxMultiviewViewCount = MAX_VIEWS;
906 properties->maxMultiviewInstanceIndex = INT_MAX;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
910 VkPhysicalDevicePointClippingPropertiesKHR *properties =
911 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
912 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
916 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
917 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
918 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
919 break;
920 }
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
922 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
923 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
924 properties->minImportedHostPointerAlignment = 4096;
925 break;
926 }
927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
928 VkPhysicalDeviceSubgroupProperties *properties =
929 (VkPhysicalDeviceSubgroupProperties*)ext;
930 properties->subgroupSize = 64;
931 properties->supportedStages = VK_SHADER_STAGE_ALL;
932 properties->supportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT;
933 properties->quadOperationsInAllStages = false;
934 break;
935 }
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
937 VkPhysicalDeviceMaintenance3Properties *properties =
938 (VkPhysicalDeviceMaintenance3Properties*)ext;
939 /* Make sure everything is addressable by a signed 32-bit int, and
940 * our largest descriptors are 96 bytes. */
941 properties->maxPerSetDescriptors = (1ull << 31) / 96;
942 /* Our buffer size fields allow only this much */
943 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
944 break;
945 }
946 default:
947 break;
948 }
949 }
950 }
951
952 static void radv_get_physical_device_queue_family_properties(
953 struct radv_physical_device* pdevice,
954 uint32_t* pCount,
955 VkQueueFamilyProperties** pQueueFamilyProperties)
956 {
957 int num_queue_families = 1;
958 int idx;
959 if (pdevice->rad_info.num_compute_rings > 0 &&
960 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
961 num_queue_families++;
962
963 if (pQueueFamilyProperties == NULL) {
964 *pCount = num_queue_families;
965 return;
966 }
967
968 if (!*pCount)
969 return;
970
971 idx = 0;
972 if (*pCount >= 1) {
973 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
974 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
975 VK_QUEUE_COMPUTE_BIT |
976 VK_QUEUE_TRANSFER_BIT |
977 VK_QUEUE_SPARSE_BINDING_BIT,
978 .queueCount = 1,
979 .timestampValidBits = 64,
980 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
981 };
982 idx++;
983 }
984
985 if (pdevice->rad_info.num_compute_rings > 0 &&
986 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
987 if (*pCount > idx) {
988 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
989 .queueFlags = VK_QUEUE_COMPUTE_BIT |
990 VK_QUEUE_TRANSFER_BIT |
991 VK_QUEUE_SPARSE_BINDING_BIT,
992 .queueCount = pdevice->rad_info.num_compute_rings,
993 .timestampValidBits = 64,
994 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
995 };
996 idx++;
997 }
998 }
999 *pCount = idx;
1000 }
1001
1002 void radv_GetPhysicalDeviceQueueFamilyProperties(
1003 VkPhysicalDevice physicalDevice,
1004 uint32_t* pCount,
1005 VkQueueFamilyProperties* pQueueFamilyProperties)
1006 {
1007 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1008 if (!pQueueFamilyProperties) {
1009 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1010 return;
1011 }
1012 VkQueueFamilyProperties *properties[] = {
1013 pQueueFamilyProperties + 0,
1014 pQueueFamilyProperties + 1,
1015 pQueueFamilyProperties + 2,
1016 };
1017 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1018 assert(*pCount <= 3);
1019 }
1020
1021 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1022 VkPhysicalDevice physicalDevice,
1023 uint32_t* pCount,
1024 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1025 {
1026 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1027 if (!pQueueFamilyProperties) {
1028 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1029 return;
1030 }
1031 VkQueueFamilyProperties *properties[] = {
1032 &pQueueFamilyProperties[0].queueFamilyProperties,
1033 &pQueueFamilyProperties[1].queueFamilyProperties,
1034 &pQueueFamilyProperties[2].queueFamilyProperties,
1035 };
1036 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1037 assert(*pCount <= 3);
1038 }
1039
1040 void radv_GetPhysicalDeviceMemoryProperties(
1041 VkPhysicalDevice physicalDevice,
1042 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1043 {
1044 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1045
1046 *pMemoryProperties = physical_device->memory_properties;
1047 }
1048
1049 void radv_GetPhysicalDeviceMemoryProperties2(
1050 VkPhysicalDevice physicalDevice,
1051 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1052 {
1053 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1054 &pMemoryProperties->memoryProperties);
1055 }
1056
1057 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1058 VkDevice _device,
1059 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1060 const void *pHostPointer,
1061 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1062 {
1063 RADV_FROM_HANDLE(radv_device, device, _device);
1064
1065 switch (handleType)
1066 {
1067 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1068 const struct radv_physical_device *physical_device = device->physical_device;
1069 uint32_t memoryTypeBits = 0;
1070 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1071 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1072 memoryTypeBits = (1 << i);
1073 break;
1074 }
1075 }
1076 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1077 return VK_SUCCESS;
1078 }
1079 default:
1080 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1081 }
1082 }
1083
1084 static enum radeon_ctx_priority
1085 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1086 {
1087 /* Default to MEDIUM when a specific global priority isn't requested */
1088 if (!pObj)
1089 return RADEON_CTX_PRIORITY_MEDIUM;
1090
1091 switch(pObj->globalPriority) {
1092 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1093 return RADEON_CTX_PRIORITY_REALTIME;
1094 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1095 return RADEON_CTX_PRIORITY_HIGH;
1096 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1097 return RADEON_CTX_PRIORITY_MEDIUM;
1098 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1099 return RADEON_CTX_PRIORITY_LOW;
1100 default:
1101 unreachable("Illegal global priority value");
1102 return RADEON_CTX_PRIORITY_INVALID;
1103 }
1104 }
1105
1106 static int
1107 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1108 uint32_t queue_family_index, int idx,
1109 VkDeviceQueueCreateFlags flags,
1110 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1111 {
1112 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1113 queue->device = device;
1114 queue->queue_family_index = queue_family_index;
1115 queue->queue_idx = idx;
1116 queue->priority = radv_get_queue_global_priority(global_priority);
1117 queue->flags = flags;
1118
1119 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1120 if (!queue->hw_ctx)
1121 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1122
1123 return VK_SUCCESS;
1124 }
1125
1126 static void
1127 radv_queue_finish(struct radv_queue *queue)
1128 {
1129 if (queue->hw_ctx)
1130 queue->device->ws->ctx_destroy(queue->hw_ctx);
1131
1132 if (queue->initial_full_flush_preamble_cs)
1133 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1134 if (queue->initial_preamble_cs)
1135 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1136 if (queue->continue_preamble_cs)
1137 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1138 if (queue->descriptor_bo)
1139 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1140 if (queue->scratch_bo)
1141 queue->device->ws->buffer_destroy(queue->scratch_bo);
1142 if (queue->esgs_ring_bo)
1143 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1144 if (queue->gsvs_ring_bo)
1145 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1146 if (queue->tess_rings_bo)
1147 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1148 if (queue->compute_scratch_bo)
1149 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1150 }
1151
1152 static void
1153 radv_device_init_gs_info(struct radv_device *device)
1154 {
1155 switch (device->physical_device->rad_info.family) {
1156 case CHIP_OLAND:
1157 case CHIP_HAINAN:
1158 case CHIP_KAVERI:
1159 case CHIP_KABINI:
1160 case CHIP_MULLINS:
1161 case CHIP_ICELAND:
1162 case CHIP_CARRIZO:
1163 case CHIP_STONEY:
1164 device->gs_table_depth = 16;
1165 return;
1166 case CHIP_TAHITI:
1167 case CHIP_PITCAIRN:
1168 case CHIP_VERDE:
1169 case CHIP_BONAIRE:
1170 case CHIP_HAWAII:
1171 case CHIP_TONGA:
1172 case CHIP_FIJI:
1173 case CHIP_POLARIS10:
1174 case CHIP_POLARIS11:
1175 case CHIP_POLARIS12:
1176 case CHIP_VEGA10:
1177 case CHIP_RAVEN:
1178 device->gs_table_depth = 32;
1179 return;
1180 default:
1181 unreachable("unknown GPU");
1182 }
1183 }
1184
1185 static int radv_get_device_extension_index(const char *name)
1186 {
1187 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1188 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1189 return i;
1190 }
1191 return -1;
1192 }
1193
1194 VkResult radv_CreateDevice(
1195 VkPhysicalDevice physicalDevice,
1196 const VkDeviceCreateInfo* pCreateInfo,
1197 const VkAllocationCallbacks* pAllocator,
1198 VkDevice* pDevice)
1199 {
1200 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1201 VkResult result;
1202 struct radv_device *device;
1203
1204 bool keep_shader_info = false;
1205
1206 /* Check enabled features */
1207 if (pCreateInfo->pEnabledFeatures) {
1208 VkPhysicalDeviceFeatures supported_features;
1209 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1210 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1211 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1212 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1213 for (uint32_t i = 0; i < num_features; i++) {
1214 if (enabled_feature[i] && !supported_feature[i])
1215 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1216 }
1217 }
1218
1219 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1220 sizeof(*device), 8,
1221 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1222 if (!device)
1223 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1224
1225 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1226 device->instance = physical_device->instance;
1227 device->physical_device = physical_device;
1228
1229 device->ws = physical_device->ws;
1230 if (pAllocator)
1231 device->alloc = *pAllocator;
1232 else
1233 device->alloc = physical_device->instance->alloc;
1234
1235 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1236 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1237 int index = radv_get_device_extension_index(ext_name);
1238 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1239 vk_free(&device->alloc, device);
1240 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1241 }
1242
1243 device->enabled_extensions.extensions[index] = true;
1244 }
1245
1246 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1247
1248 mtx_init(&device->shader_slab_mutex, mtx_plain);
1249 list_inithead(&device->shader_slabs);
1250
1251 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1252 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1253 uint32_t qfi = queue_create->queueFamilyIndex;
1254 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1255 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1256
1257 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1258
1259 device->queues[qfi] = vk_alloc(&device->alloc,
1260 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1261 if (!device->queues[qfi]) {
1262 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1263 goto fail;
1264 }
1265
1266 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1267
1268 device->queue_count[qfi] = queue_create->queueCount;
1269
1270 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1271 result = radv_queue_init(device, &device->queues[qfi][q],
1272 qfi, q, queue_create->flags,
1273 global_priority);
1274 if (result != VK_SUCCESS)
1275 goto fail;
1276 }
1277 }
1278
1279 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1280 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1281
1282 /* Disabled and not implemented for now. */
1283 device->dfsm_allowed = device->pbb_allowed && false;
1284
1285 #ifdef ANDROID
1286 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1287 #endif
1288
1289 device->llvm_supports_spill = true;
1290
1291 /* The maximum number of scratch waves. Scratch space isn't divided
1292 * evenly between CUs. The number is only a function of the number of CUs.
1293 * We can decrease the constant to decrease the scratch buffer size.
1294 *
1295 * sctx->scratch_waves must be >= the maximum posible size of
1296 * 1 threadgroup, so that the hw doesn't hang from being unable
1297 * to start any.
1298 *
1299 * The recommended value is 4 per CU at most. Higher numbers don't
1300 * bring much benefit, but they still occupy chip resources (think
1301 * async compute). I've seen ~2% performance difference between 4 and 32.
1302 */
1303 uint32_t max_threads_per_block = 2048;
1304 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1305 max_threads_per_block / 64);
1306
1307 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1308
1309 if (device->physical_device->rad_info.chip_class >= CIK) {
1310 /* If the KMD allows it (there is a KMD hw register for it),
1311 * allow launching waves out-of-order.
1312 */
1313 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1314 }
1315
1316 radv_device_init_gs_info(device);
1317
1318 device->tess_offchip_block_dw_size =
1319 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1320 device->has_distributed_tess =
1321 device->physical_device->rad_info.chip_class >= VI &&
1322 device->physical_device->rad_info.max_se >= 2;
1323
1324 if (getenv("RADV_TRACE_FILE")) {
1325 const char *filename = getenv("RADV_TRACE_FILE");
1326
1327 keep_shader_info = true;
1328
1329 if (!radv_init_trace(device))
1330 goto fail;
1331
1332 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1333 radv_dump_enabled_options(device, stderr);
1334 }
1335
1336 device->keep_shader_info = keep_shader_info;
1337
1338 result = radv_device_init_meta(device);
1339 if (result != VK_SUCCESS)
1340 goto fail;
1341
1342 radv_device_init_msaa(device);
1343
1344 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1345 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1346 switch (family) {
1347 case RADV_QUEUE_GENERAL:
1348 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1349 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1350 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1351 break;
1352 case RADV_QUEUE_COMPUTE:
1353 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1354 radeon_emit(device->empty_cs[family], 0);
1355 break;
1356 }
1357 device->ws->cs_finalize(device->empty_cs[family]);
1358 }
1359
1360 if (device->physical_device->rad_info.chip_class >= CIK)
1361 cik_create_gfx_config(device);
1362
1363 VkPipelineCacheCreateInfo ci;
1364 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1365 ci.pNext = NULL;
1366 ci.flags = 0;
1367 ci.pInitialData = NULL;
1368 ci.initialDataSize = 0;
1369 VkPipelineCache pc;
1370 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1371 &ci, NULL, &pc);
1372 if (result != VK_SUCCESS)
1373 goto fail_meta;
1374
1375 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1376
1377 *pDevice = radv_device_to_handle(device);
1378 return VK_SUCCESS;
1379
1380 fail_meta:
1381 radv_device_finish_meta(device);
1382 fail:
1383 if (device->trace_bo)
1384 device->ws->buffer_destroy(device->trace_bo);
1385
1386 if (device->gfx_init)
1387 device->ws->buffer_destroy(device->gfx_init);
1388
1389 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1390 for (unsigned q = 0; q < device->queue_count[i]; q++)
1391 radv_queue_finish(&device->queues[i][q]);
1392 if (device->queue_count[i])
1393 vk_free(&device->alloc, device->queues[i]);
1394 }
1395
1396 vk_free(&device->alloc, device);
1397 return result;
1398 }
1399
1400 void radv_DestroyDevice(
1401 VkDevice _device,
1402 const VkAllocationCallbacks* pAllocator)
1403 {
1404 RADV_FROM_HANDLE(radv_device, device, _device);
1405
1406 if (!device)
1407 return;
1408
1409 if (device->trace_bo)
1410 device->ws->buffer_destroy(device->trace_bo);
1411
1412 if (device->gfx_init)
1413 device->ws->buffer_destroy(device->gfx_init);
1414
1415 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1416 for (unsigned q = 0; q < device->queue_count[i]; q++)
1417 radv_queue_finish(&device->queues[i][q]);
1418 if (device->queue_count[i])
1419 vk_free(&device->alloc, device->queues[i]);
1420 if (device->empty_cs[i])
1421 device->ws->cs_destroy(device->empty_cs[i]);
1422 }
1423 radv_device_finish_meta(device);
1424
1425 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1426 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1427
1428 radv_destroy_shader_slabs(device);
1429
1430 vk_free(&device->alloc, device);
1431 }
1432
1433 VkResult radv_EnumerateInstanceLayerProperties(
1434 uint32_t* pPropertyCount,
1435 VkLayerProperties* pProperties)
1436 {
1437 if (pProperties == NULL) {
1438 *pPropertyCount = 0;
1439 return VK_SUCCESS;
1440 }
1441
1442 /* None supported at this time */
1443 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1444 }
1445
1446 VkResult radv_EnumerateDeviceLayerProperties(
1447 VkPhysicalDevice physicalDevice,
1448 uint32_t* pPropertyCount,
1449 VkLayerProperties* pProperties)
1450 {
1451 if (pProperties == NULL) {
1452 *pPropertyCount = 0;
1453 return VK_SUCCESS;
1454 }
1455
1456 /* None supported at this time */
1457 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1458 }
1459
1460 void radv_GetDeviceQueue2(
1461 VkDevice _device,
1462 const VkDeviceQueueInfo2* pQueueInfo,
1463 VkQueue* pQueue)
1464 {
1465 RADV_FROM_HANDLE(radv_device, device, _device);
1466 struct radv_queue *queue;
1467
1468 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1469 if (pQueueInfo->flags != queue->flags) {
1470 /* From the Vulkan 1.1.70 spec:
1471 *
1472 * "The queue returned by vkGetDeviceQueue2 must have the same
1473 * flags value from this structure as that used at device
1474 * creation time in a VkDeviceQueueCreateInfo instance. If no
1475 * matching flags were specified at device creation time then
1476 * pQueue will return VK_NULL_HANDLE."
1477 */
1478 *pQueue = VK_NULL_HANDLE;
1479 return;
1480 }
1481
1482 *pQueue = radv_queue_to_handle(queue);
1483 }
1484
1485 void radv_GetDeviceQueue(
1486 VkDevice _device,
1487 uint32_t queueFamilyIndex,
1488 uint32_t queueIndex,
1489 VkQueue* pQueue)
1490 {
1491 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1492 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1493 .queueFamilyIndex = queueFamilyIndex,
1494 .queueIndex = queueIndex
1495 };
1496
1497 radv_GetDeviceQueue2(_device, &info, pQueue);
1498 }
1499
1500 static void
1501 fill_geom_tess_rings(struct radv_queue *queue,
1502 uint32_t *map,
1503 bool add_sample_positions,
1504 uint32_t esgs_ring_size,
1505 struct radeon_winsys_bo *esgs_ring_bo,
1506 uint32_t gsvs_ring_size,
1507 struct radeon_winsys_bo *gsvs_ring_bo,
1508 uint32_t tess_factor_ring_size,
1509 uint32_t tess_offchip_ring_offset,
1510 uint32_t tess_offchip_ring_size,
1511 struct radeon_winsys_bo *tess_rings_bo)
1512 {
1513 uint64_t esgs_va = 0, gsvs_va = 0;
1514 uint64_t tess_va = 0, tess_offchip_va = 0;
1515 uint32_t *desc = &map[4];
1516
1517 if (esgs_ring_bo)
1518 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1519 if (gsvs_ring_bo)
1520 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1521 if (tess_rings_bo) {
1522 tess_va = radv_buffer_get_va(tess_rings_bo);
1523 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1524 }
1525
1526 /* stride 0, num records - size, add tid, swizzle, elsize4,
1527 index stride 64 */
1528 desc[0] = esgs_va;
1529 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1530 S_008F04_STRIDE(0) |
1531 S_008F04_SWIZZLE_ENABLE(true);
1532 desc[2] = esgs_ring_size;
1533 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1534 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1535 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1536 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1537 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1538 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1539 S_008F0C_ELEMENT_SIZE(1) |
1540 S_008F0C_INDEX_STRIDE(3) |
1541 S_008F0C_ADD_TID_ENABLE(true);
1542
1543 desc += 4;
1544 /* GS entry for ES->GS ring */
1545 /* stride 0, num records - size, elsize0,
1546 index stride 0 */
1547 desc[0] = esgs_va;
1548 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1549 S_008F04_STRIDE(0) |
1550 S_008F04_SWIZZLE_ENABLE(false);
1551 desc[2] = esgs_ring_size;
1552 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1553 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1554 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1555 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1556 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1557 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1558 S_008F0C_ELEMENT_SIZE(0) |
1559 S_008F0C_INDEX_STRIDE(0) |
1560 S_008F0C_ADD_TID_ENABLE(false);
1561
1562 desc += 4;
1563 /* VS entry for GS->VS ring */
1564 /* stride 0, num records - size, elsize0,
1565 index stride 0 */
1566 desc[0] = gsvs_va;
1567 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1568 S_008F04_STRIDE(0) |
1569 S_008F04_SWIZZLE_ENABLE(false);
1570 desc[2] = gsvs_ring_size;
1571 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1572 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1573 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1574 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1575 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1576 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1577 S_008F0C_ELEMENT_SIZE(0) |
1578 S_008F0C_INDEX_STRIDE(0) |
1579 S_008F0C_ADD_TID_ENABLE(false);
1580 desc += 4;
1581
1582 /* stride gsvs_itemsize, num records 64
1583 elsize 4, index stride 16 */
1584 /* shader will patch stride and desc[2] */
1585 desc[0] = gsvs_va;
1586 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1587 S_008F04_STRIDE(0) |
1588 S_008F04_SWIZZLE_ENABLE(true);
1589 desc[2] = 0;
1590 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1591 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1592 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1593 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1594 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1595 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1596 S_008F0C_ELEMENT_SIZE(1) |
1597 S_008F0C_INDEX_STRIDE(1) |
1598 S_008F0C_ADD_TID_ENABLE(true);
1599 desc += 4;
1600
1601 desc[0] = tess_va;
1602 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1603 S_008F04_STRIDE(0) |
1604 S_008F04_SWIZZLE_ENABLE(false);
1605 desc[2] = tess_factor_ring_size;
1606 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1607 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1608 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1609 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1610 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1611 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1612 S_008F0C_ELEMENT_SIZE(0) |
1613 S_008F0C_INDEX_STRIDE(0) |
1614 S_008F0C_ADD_TID_ENABLE(false);
1615 desc += 4;
1616
1617 desc[0] = tess_offchip_va;
1618 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1619 S_008F04_STRIDE(0) |
1620 S_008F04_SWIZZLE_ENABLE(false);
1621 desc[2] = tess_offchip_ring_size;
1622 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1623 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1624 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1625 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1626 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1627 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1628 S_008F0C_ELEMENT_SIZE(0) |
1629 S_008F0C_INDEX_STRIDE(0) |
1630 S_008F0C_ADD_TID_ENABLE(false);
1631 desc += 4;
1632
1633 /* add sample positions after all rings */
1634 memcpy(desc, queue->device->sample_locations_1x, 8);
1635 desc += 2;
1636 memcpy(desc, queue->device->sample_locations_2x, 16);
1637 desc += 4;
1638 memcpy(desc, queue->device->sample_locations_4x, 32);
1639 desc += 8;
1640 memcpy(desc, queue->device->sample_locations_8x, 64);
1641 desc += 16;
1642 memcpy(desc, queue->device->sample_locations_16x, 128);
1643 }
1644
1645 static unsigned
1646 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1647 {
1648 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1649 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1650 device->physical_device->rad_info.family != CHIP_STONEY;
1651 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1652 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1653 device->physical_device->rad_info.max_se;
1654 unsigned offchip_granularity;
1655 unsigned hs_offchip_param;
1656 switch (device->tess_offchip_block_dw_size) {
1657 default:
1658 assert(0);
1659 /* fall through */
1660 case 8192:
1661 offchip_granularity = V_03093C_X_8K_DWORDS;
1662 break;
1663 case 4096:
1664 offchip_granularity = V_03093C_X_4K_DWORDS;
1665 break;
1666 }
1667
1668 switch (device->physical_device->rad_info.chip_class) {
1669 case SI:
1670 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1671 break;
1672 case CIK:
1673 case VI:
1674 case GFX9:
1675 default:
1676 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1677 break;
1678 }
1679
1680 *max_offchip_buffers_p = max_offchip_buffers;
1681 if (device->physical_device->rad_info.chip_class >= CIK) {
1682 if (device->physical_device->rad_info.chip_class >= VI)
1683 --max_offchip_buffers;
1684 hs_offchip_param =
1685 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1686 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1687 } else {
1688 hs_offchip_param =
1689 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1690 }
1691 return hs_offchip_param;
1692 }
1693
1694 static VkResult
1695 radv_get_preamble_cs(struct radv_queue *queue,
1696 uint32_t scratch_size,
1697 uint32_t compute_scratch_size,
1698 uint32_t esgs_ring_size,
1699 uint32_t gsvs_ring_size,
1700 bool needs_tess_rings,
1701 bool needs_sample_positions,
1702 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1703 struct radeon_winsys_cs **initial_preamble_cs,
1704 struct radeon_winsys_cs **continue_preamble_cs)
1705 {
1706 struct radeon_winsys_bo *scratch_bo = NULL;
1707 struct radeon_winsys_bo *descriptor_bo = NULL;
1708 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1709 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1710 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1711 struct radeon_winsys_bo *tess_rings_bo = NULL;
1712 struct radeon_winsys_cs *dest_cs[3] = {0};
1713 bool add_tess_rings = false, add_sample_positions = false;
1714 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1715 unsigned max_offchip_buffers;
1716 unsigned hs_offchip_param = 0;
1717 unsigned tess_offchip_ring_offset;
1718 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1719 if (!queue->has_tess_rings) {
1720 if (needs_tess_rings)
1721 add_tess_rings = true;
1722 }
1723 if (!queue->has_sample_positions) {
1724 if (needs_sample_positions)
1725 add_sample_positions = true;
1726 }
1727 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1728 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1729 &max_offchip_buffers);
1730 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1731 tess_offchip_ring_size = max_offchip_buffers *
1732 queue->device->tess_offchip_block_dw_size * 4;
1733
1734 if (scratch_size <= queue->scratch_size &&
1735 compute_scratch_size <= queue->compute_scratch_size &&
1736 esgs_ring_size <= queue->esgs_ring_size &&
1737 gsvs_ring_size <= queue->gsvs_ring_size &&
1738 !add_tess_rings && !add_sample_positions &&
1739 queue->initial_preamble_cs) {
1740 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1741 *initial_preamble_cs = queue->initial_preamble_cs;
1742 *continue_preamble_cs = queue->continue_preamble_cs;
1743 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1744 *continue_preamble_cs = NULL;
1745 return VK_SUCCESS;
1746 }
1747
1748 if (scratch_size > queue->scratch_size) {
1749 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1750 scratch_size,
1751 4096,
1752 RADEON_DOMAIN_VRAM,
1753 ring_bo_flags);
1754 if (!scratch_bo)
1755 goto fail;
1756 } else
1757 scratch_bo = queue->scratch_bo;
1758
1759 if (compute_scratch_size > queue->compute_scratch_size) {
1760 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1761 compute_scratch_size,
1762 4096,
1763 RADEON_DOMAIN_VRAM,
1764 ring_bo_flags);
1765 if (!compute_scratch_bo)
1766 goto fail;
1767
1768 } else
1769 compute_scratch_bo = queue->compute_scratch_bo;
1770
1771 if (esgs_ring_size > queue->esgs_ring_size) {
1772 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1773 esgs_ring_size,
1774 4096,
1775 RADEON_DOMAIN_VRAM,
1776 ring_bo_flags);
1777 if (!esgs_ring_bo)
1778 goto fail;
1779 } else {
1780 esgs_ring_bo = queue->esgs_ring_bo;
1781 esgs_ring_size = queue->esgs_ring_size;
1782 }
1783
1784 if (gsvs_ring_size > queue->gsvs_ring_size) {
1785 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1786 gsvs_ring_size,
1787 4096,
1788 RADEON_DOMAIN_VRAM,
1789 ring_bo_flags);
1790 if (!gsvs_ring_bo)
1791 goto fail;
1792 } else {
1793 gsvs_ring_bo = queue->gsvs_ring_bo;
1794 gsvs_ring_size = queue->gsvs_ring_size;
1795 }
1796
1797 if (add_tess_rings) {
1798 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1799 tess_offchip_ring_offset + tess_offchip_ring_size,
1800 256,
1801 RADEON_DOMAIN_VRAM,
1802 ring_bo_flags);
1803 if (!tess_rings_bo)
1804 goto fail;
1805 } else {
1806 tess_rings_bo = queue->tess_rings_bo;
1807 }
1808
1809 if (scratch_bo != queue->scratch_bo ||
1810 esgs_ring_bo != queue->esgs_ring_bo ||
1811 gsvs_ring_bo != queue->gsvs_ring_bo ||
1812 tess_rings_bo != queue->tess_rings_bo ||
1813 add_sample_positions) {
1814 uint32_t size = 0;
1815 if (gsvs_ring_bo || esgs_ring_bo ||
1816 tess_rings_bo || add_sample_positions) {
1817 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1818 if (add_sample_positions)
1819 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1820 }
1821 else if (scratch_bo)
1822 size = 8; /* 2 dword */
1823
1824 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1825 size,
1826 4096,
1827 RADEON_DOMAIN_VRAM,
1828 RADEON_FLAG_CPU_ACCESS |
1829 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1830 RADEON_FLAG_READ_ONLY);
1831 if (!descriptor_bo)
1832 goto fail;
1833 } else
1834 descriptor_bo = queue->descriptor_bo;
1835
1836 for(int i = 0; i < 3; ++i) {
1837 struct radeon_winsys_cs *cs = NULL;
1838 cs = queue->device->ws->cs_create(queue->device->ws,
1839 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1840 if (!cs)
1841 goto fail;
1842
1843 dest_cs[i] = cs;
1844
1845 if (scratch_bo)
1846 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1847
1848 if (esgs_ring_bo)
1849 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1850
1851 if (gsvs_ring_bo)
1852 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1853
1854 if (tess_rings_bo)
1855 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1856
1857 if (descriptor_bo)
1858 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1859
1860 if (descriptor_bo != queue->descriptor_bo) {
1861 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1862
1863 if (scratch_bo) {
1864 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1865 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1866 S_008F04_SWIZZLE_ENABLE(1);
1867 map[0] = scratch_va;
1868 map[1] = rsrc1;
1869 }
1870
1871 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
1872 add_sample_positions)
1873 fill_geom_tess_rings(queue, map, add_sample_positions,
1874 esgs_ring_size, esgs_ring_bo,
1875 gsvs_ring_size, gsvs_ring_bo,
1876 tess_factor_ring_size,
1877 tess_offchip_ring_offset,
1878 tess_offchip_ring_size,
1879 tess_rings_bo);
1880
1881 queue->device->ws->buffer_unmap(descriptor_bo);
1882 }
1883
1884 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
1885 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1886 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1887 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1888 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1889 }
1890
1891 if (esgs_ring_bo || gsvs_ring_bo) {
1892 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1893 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1894 radeon_emit(cs, esgs_ring_size >> 8);
1895 radeon_emit(cs, gsvs_ring_size >> 8);
1896 } else {
1897 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1898 radeon_emit(cs, esgs_ring_size >> 8);
1899 radeon_emit(cs, gsvs_ring_size >> 8);
1900 }
1901 }
1902
1903 if (tess_rings_bo) {
1904 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
1905 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1906 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1907 S_030938_SIZE(tess_factor_ring_size / 4));
1908 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1909 tf_va >> 8);
1910 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1911 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1912 tf_va >> 40);
1913 }
1914 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1915 } else {
1916 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1917 S_008988_SIZE(tess_factor_ring_size / 4));
1918 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1919 tf_va >> 8);
1920 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1921 hs_offchip_param);
1922 }
1923 }
1924
1925 if (descriptor_bo) {
1926 uint64_t va = radv_buffer_get_va(descriptor_bo);
1927 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1928 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1929 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1930 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1931 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1932
1933 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1934 radeon_set_sh_reg_seq(cs, regs[i], 2);
1935 radeon_emit(cs, va);
1936 radeon_emit(cs, va >> 32);
1937 }
1938 } else {
1939 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1940 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1941 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1942 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1943 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1944 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1945
1946 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1947 radeon_set_sh_reg_seq(cs, regs[i], 2);
1948 radeon_emit(cs, va);
1949 radeon_emit(cs, va >> 32);
1950 }
1951 }
1952 }
1953
1954 if (compute_scratch_bo) {
1955 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1956 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1957 S_008F04_SWIZZLE_ENABLE(1);
1958
1959 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1960
1961 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1962 radeon_emit(cs, scratch_va);
1963 radeon_emit(cs, rsrc1);
1964 }
1965
1966 if (i == 0) {
1967 si_cs_emit_cache_flush(cs,
1968 queue->device->physical_device->rad_info.chip_class,
1969 NULL, 0,
1970 queue->queue_family_index == RING_COMPUTE &&
1971 queue->device->physical_device->rad_info.chip_class >= CIK,
1972 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1973 RADV_CMD_FLAG_INV_ICACHE |
1974 RADV_CMD_FLAG_INV_SMEM_L1 |
1975 RADV_CMD_FLAG_INV_VMEM_L1 |
1976 RADV_CMD_FLAG_INV_GLOBAL_L2);
1977 } else if (i == 1) {
1978 si_cs_emit_cache_flush(cs,
1979 queue->device->physical_device->rad_info.chip_class,
1980 NULL, 0,
1981 queue->queue_family_index == RING_COMPUTE &&
1982 queue->device->physical_device->rad_info.chip_class >= CIK,
1983 RADV_CMD_FLAG_INV_ICACHE |
1984 RADV_CMD_FLAG_INV_SMEM_L1 |
1985 RADV_CMD_FLAG_INV_VMEM_L1 |
1986 RADV_CMD_FLAG_INV_GLOBAL_L2);
1987 }
1988
1989 if (!queue->device->ws->cs_finalize(cs))
1990 goto fail;
1991 }
1992
1993 if (queue->initial_full_flush_preamble_cs)
1994 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1995
1996 if (queue->initial_preamble_cs)
1997 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1998
1999 if (queue->continue_preamble_cs)
2000 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2001
2002 queue->initial_full_flush_preamble_cs = dest_cs[0];
2003 queue->initial_preamble_cs = dest_cs[1];
2004 queue->continue_preamble_cs = dest_cs[2];
2005
2006 if (scratch_bo != queue->scratch_bo) {
2007 if (queue->scratch_bo)
2008 queue->device->ws->buffer_destroy(queue->scratch_bo);
2009 queue->scratch_bo = scratch_bo;
2010 queue->scratch_size = scratch_size;
2011 }
2012
2013 if (compute_scratch_bo != queue->compute_scratch_bo) {
2014 if (queue->compute_scratch_bo)
2015 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2016 queue->compute_scratch_bo = compute_scratch_bo;
2017 queue->compute_scratch_size = compute_scratch_size;
2018 }
2019
2020 if (esgs_ring_bo != queue->esgs_ring_bo) {
2021 if (queue->esgs_ring_bo)
2022 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2023 queue->esgs_ring_bo = esgs_ring_bo;
2024 queue->esgs_ring_size = esgs_ring_size;
2025 }
2026
2027 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2028 if (queue->gsvs_ring_bo)
2029 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2030 queue->gsvs_ring_bo = gsvs_ring_bo;
2031 queue->gsvs_ring_size = gsvs_ring_size;
2032 }
2033
2034 if (tess_rings_bo != queue->tess_rings_bo) {
2035 queue->tess_rings_bo = tess_rings_bo;
2036 queue->has_tess_rings = true;
2037 }
2038
2039 if (descriptor_bo != queue->descriptor_bo) {
2040 if (queue->descriptor_bo)
2041 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2042
2043 queue->descriptor_bo = descriptor_bo;
2044 }
2045
2046 if (add_sample_positions)
2047 queue->has_sample_positions = true;
2048
2049 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2050 *initial_preamble_cs = queue->initial_preamble_cs;
2051 *continue_preamble_cs = queue->continue_preamble_cs;
2052 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2053 *continue_preamble_cs = NULL;
2054 return VK_SUCCESS;
2055 fail:
2056 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2057 if (dest_cs[i])
2058 queue->device->ws->cs_destroy(dest_cs[i]);
2059 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2060 queue->device->ws->buffer_destroy(descriptor_bo);
2061 if (scratch_bo && scratch_bo != queue->scratch_bo)
2062 queue->device->ws->buffer_destroy(scratch_bo);
2063 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2064 queue->device->ws->buffer_destroy(compute_scratch_bo);
2065 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2066 queue->device->ws->buffer_destroy(esgs_ring_bo);
2067 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2068 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2069 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2070 queue->device->ws->buffer_destroy(tess_rings_bo);
2071 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2072 }
2073
2074 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2075 int num_sems,
2076 const VkSemaphore *sems,
2077 VkFence _fence,
2078 bool reset_temp)
2079 {
2080 int syncobj_idx = 0, sem_idx = 0;
2081
2082 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2083 return VK_SUCCESS;
2084
2085 for (uint32_t i = 0; i < num_sems; i++) {
2086 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2087
2088 if (sem->temp_syncobj || sem->syncobj)
2089 counts->syncobj_count++;
2090 else
2091 counts->sem_count++;
2092 }
2093
2094 if (_fence != VK_NULL_HANDLE) {
2095 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2096 if (fence->temp_syncobj || fence->syncobj)
2097 counts->syncobj_count++;
2098 }
2099
2100 if (counts->syncobj_count) {
2101 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2102 if (!counts->syncobj)
2103 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2104 }
2105
2106 if (counts->sem_count) {
2107 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2108 if (!counts->sem) {
2109 free(counts->syncobj);
2110 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2111 }
2112 }
2113
2114 for (uint32_t i = 0; i < num_sems; i++) {
2115 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2116
2117 if (sem->temp_syncobj) {
2118 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2119 }
2120 else if (sem->syncobj)
2121 counts->syncobj[syncobj_idx++] = sem->syncobj;
2122 else {
2123 assert(sem->sem);
2124 counts->sem[sem_idx++] = sem->sem;
2125 }
2126 }
2127
2128 if (_fence != VK_NULL_HANDLE) {
2129 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2130 if (fence->temp_syncobj)
2131 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2132 else if (fence->syncobj)
2133 counts->syncobj[syncobj_idx++] = fence->syncobj;
2134 }
2135
2136 return VK_SUCCESS;
2137 }
2138
2139 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2140 {
2141 free(sem_info->wait.syncobj);
2142 free(sem_info->wait.sem);
2143 free(sem_info->signal.syncobj);
2144 free(sem_info->signal.sem);
2145 }
2146
2147
2148 static void radv_free_temp_syncobjs(struct radv_device *device,
2149 int num_sems,
2150 const VkSemaphore *sems)
2151 {
2152 for (uint32_t i = 0; i < num_sems; i++) {
2153 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2154
2155 if (sem->temp_syncobj) {
2156 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2157 sem->temp_syncobj = 0;
2158 }
2159 }
2160 }
2161
2162 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2163 int num_wait_sems,
2164 const VkSemaphore *wait_sems,
2165 int num_signal_sems,
2166 const VkSemaphore *signal_sems,
2167 VkFence fence)
2168 {
2169 VkResult ret;
2170 memset(sem_info, 0, sizeof(*sem_info));
2171
2172 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2173 if (ret)
2174 return ret;
2175 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2176 if (ret)
2177 radv_free_sem_info(sem_info);
2178
2179 /* caller can override these */
2180 sem_info->cs_emit_wait = true;
2181 sem_info->cs_emit_signal = true;
2182 return ret;
2183 }
2184
2185 /* Signals fence as soon as all the work currently put on queue is done. */
2186 static VkResult radv_signal_fence(struct radv_queue *queue,
2187 struct radv_fence *fence)
2188 {
2189 int ret;
2190 VkResult result;
2191 struct radv_winsys_sem_info sem_info;
2192
2193 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2194 radv_fence_to_handle(fence));
2195 if (result != VK_SUCCESS)
2196 return result;
2197
2198 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2199 &queue->device->empty_cs[queue->queue_family_index],
2200 1, NULL, NULL, &sem_info,
2201 false, fence->fence);
2202 radv_free_sem_info(&sem_info);
2203
2204 /* TODO: find a better error */
2205 if (ret)
2206 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2207
2208 return VK_SUCCESS;
2209 }
2210
2211 VkResult radv_QueueSubmit(
2212 VkQueue _queue,
2213 uint32_t submitCount,
2214 const VkSubmitInfo* pSubmits,
2215 VkFence _fence)
2216 {
2217 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2218 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2219 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2220 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2221 int ret;
2222 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2223 uint32_t scratch_size = 0;
2224 uint32_t compute_scratch_size = 0;
2225 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2226 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2227 VkResult result;
2228 bool fence_emitted = false;
2229 bool tess_rings_needed = false;
2230 bool sample_positions_needed = false;
2231
2232 /* Do this first so failing to allocate scratch buffers can't result in
2233 * partially executed submissions. */
2234 for (uint32_t i = 0; i < submitCount; i++) {
2235 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2236 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2237 pSubmits[i].pCommandBuffers[j]);
2238
2239 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2240 compute_scratch_size = MAX2(compute_scratch_size,
2241 cmd_buffer->compute_scratch_size_needed);
2242 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2243 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2244 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2245 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2246 }
2247 }
2248
2249 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2250 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2251 sample_positions_needed, &initial_flush_preamble_cs,
2252 &initial_preamble_cs, &continue_preamble_cs);
2253 if (result != VK_SUCCESS)
2254 return result;
2255
2256 for (uint32_t i = 0; i < submitCount; i++) {
2257 struct radeon_winsys_cs **cs_array;
2258 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2259 bool can_patch = true;
2260 uint32_t advance;
2261 struct radv_winsys_sem_info sem_info;
2262
2263 result = radv_alloc_sem_info(&sem_info,
2264 pSubmits[i].waitSemaphoreCount,
2265 pSubmits[i].pWaitSemaphores,
2266 pSubmits[i].signalSemaphoreCount,
2267 pSubmits[i].pSignalSemaphores,
2268 _fence);
2269 if (result != VK_SUCCESS)
2270 return result;
2271
2272 if (!pSubmits[i].commandBufferCount) {
2273 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2274 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2275 &queue->device->empty_cs[queue->queue_family_index],
2276 1, NULL, NULL,
2277 &sem_info,
2278 false, base_fence);
2279 if (ret) {
2280 radv_loge("failed to submit CS %d\n", i);
2281 abort();
2282 }
2283 fence_emitted = true;
2284 }
2285 radv_free_sem_info(&sem_info);
2286 continue;
2287 }
2288
2289 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2290 (pSubmits[i].commandBufferCount));
2291
2292 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2293 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2294 pSubmits[i].pCommandBuffers[j]);
2295 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2296
2297 cs_array[j] = cmd_buffer->cs;
2298 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2299 can_patch = false;
2300
2301 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2302 }
2303
2304 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2305 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2306 advance = MIN2(max_cs_submission,
2307 pSubmits[i].commandBufferCount - j);
2308
2309 if (queue->device->trace_bo)
2310 *queue->device->trace_id_ptr = 0;
2311
2312 sem_info.cs_emit_wait = j == 0;
2313 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2314
2315 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2316 advance, initial_preamble, continue_preamble_cs,
2317 &sem_info,
2318 can_patch, base_fence);
2319
2320 if (ret) {
2321 radv_loge("failed to submit CS %d\n", i);
2322 abort();
2323 }
2324 fence_emitted = true;
2325 if (queue->device->trace_bo) {
2326 radv_check_gpu_hangs(queue, cs_array[j]);
2327 }
2328 }
2329
2330 radv_free_temp_syncobjs(queue->device,
2331 pSubmits[i].waitSemaphoreCount,
2332 pSubmits[i].pWaitSemaphores);
2333 radv_free_sem_info(&sem_info);
2334 free(cs_array);
2335 }
2336
2337 if (fence) {
2338 if (!fence_emitted) {
2339 radv_signal_fence(queue, fence);
2340 }
2341 fence->submitted = true;
2342 }
2343
2344 return VK_SUCCESS;
2345 }
2346
2347 VkResult radv_QueueWaitIdle(
2348 VkQueue _queue)
2349 {
2350 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2351
2352 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2353 radv_queue_family_to_ring(queue->queue_family_index),
2354 queue->queue_idx);
2355 return VK_SUCCESS;
2356 }
2357
2358 VkResult radv_DeviceWaitIdle(
2359 VkDevice _device)
2360 {
2361 RADV_FROM_HANDLE(radv_device, device, _device);
2362
2363 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2364 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2365 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2366 }
2367 }
2368 return VK_SUCCESS;
2369 }
2370
2371 VkResult radv_EnumerateInstanceExtensionProperties(
2372 const char* pLayerName,
2373 uint32_t* pPropertyCount,
2374 VkExtensionProperties* pProperties)
2375 {
2376 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2377
2378 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2379 if (radv_supported_instance_extensions.extensions[i]) {
2380 vk_outarray_append(&out, prop) {
2381 *prop = radv_instance_extensions[i];
2382 }
2383 }
2384 }
2385
2386 return vk_outarray_status(&out);
2387 }
2388
2389 VkResult radv_EnumerateDeviceExtensionProperties(
2390 VkPhysicalDevice physicalDevice,
2391 const char* pLayerName,
2392 uint32_t* pPropertyCount,
2393 VkExtensionProperties* pProperties)
2394 {
2395 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2396 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2397
2398 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2399 if (device->supported_extensions.extensions[i]) {
2400 vk_outarray_append(&out, prop) {
2401 *prop = radv_device_extensions[i];
2402 }
2403 }
2404 }
2405
2406 return vk_outarray_status(&out);
2407 }
2408
2409 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2410 VkInstance _instance,
2411 const char* pName)
2412 {
2413 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2414
2415 return radv_lookup_entrypoint_checked(pName,
2416 instance ? instance->apiVersion : 0,
2417 instance ? &instance->enabled_extensions : NULL,
2418 NULL);
2419 }
2420
2421 /* The loader wants us to expose a second GetInstanceProcAddr function
2422 * to work around certain LD_PRELOAD issues seen in apps.
2423 */
2424 PUBLIC
2425 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2426 VkInstance instance,
2427 const char* pName);
2428
2429 PUBLIC
2430 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2431 VkInstance instance,
2432 const char* pName)
2433 {
2434 return radv_GetInstanceProcAddr(instance, pName);
2435 }
2436
2437 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2438 VkDevice _device,
2439 const char* pName)
2440 {
2441 RADV_FROM_HANDLE(radv_device, device, _device);
2442
2443 return radv_lookup_entrypoint_checked(pName,
2444 device->instance->apiVersion,
2445 &device->instance->enabled_extensions,
2446 &device->enabled_extensions);
2447 }
2448
2449 bool radv_get_memory_fd(struct radv_device *device,
2450 struct radv_device_memory *memory,
2451 int *pFD)
2452 {
2453 struct radeon_bo_metadata metadata;
2454
2455 if (memory->image) {
2456 radv_init_metadata(device, memory->image, &metadata);
2457 device->ws->buffer_set_metadata(memory->bo, &metadata);
2458 }
2459
2460 return device->ws->buffer_get_fd(device->ws, memory->bo,
2461 pFD);
2462 }
2463
2464 static VkResult radv_alloc_memory(struct radv_device *device,
2465 const VkMemoryAllocateInfo* pAllocateInfo,
2466 const VkAllocationCallbacks* pAllocator,
2467 VkDeviceMemory* pMem)
2468 {
2469 struct radv_device_memory *mem;
2470 VkResult result;
2471 enum radeon_bo_domain domain;
2472 uint32_t flags = 0;
2473 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2474
2475 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2476
2477 if (pAllocateInfo->allocationSize == 0) {
2478 /* Apparently, this is allowed */
2479 *pMem = VK_NULL_HANDLE;
2480 return VK_SUCCESS;
2481 }
2482
2483 const VkImportMemoryFdInfoKHR *import_info =
2484 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2485 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2486 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2487 const VkExportMemoryAllocateInfoKHR *export_info =
2488 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2489 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2490 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2491
2492 const struct wsi_memory_allocate_info *wsi_info =
2493 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2494
2495 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2496 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2497 if (mem == NULL)
2498 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2499
2500 if (wsi_info && wsi_info->implicit_sync)
2501 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2502
2503 if (dedicate_info) {
2504 mem->image = radv_image_from_handle(dedicate_info->image);
2505 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2506 } else {
2507 mem->image = NULL;
2508 mem->buffer = NULL;
2509 }
2510
2511 mem->user_ptr = NULL;
2512
2513 if (import_info) {
2514 assert(import_info->handleType ==
2515 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2516 import_info->handleType ==
2517 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2518 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2519 NULL, NULL);
2520 if (!mem->bo) {
2521 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2522 goto fail;
2523 } else {
2524 close(import_info->fd);
2525 goto out_success;
2526 }
2527 }
2528
2529 if (host_ptr_info) {
2530 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2531 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2532 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2533 pAllocateInfo->allocationSize);
2534 if (!mem->bo) {
2535 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2536 goto fail;
2537 } else {
2538 mem->user_ptr = host_ptr_info->pHostPointer;
2539 goto out_success;
2540 }
2541 }
2542
2543 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2544 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2545 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2546 domain = RADEON_DOMAIN_GTT;
2547 else
2548 domain = RADEON_DOMAIN_VRAM;
2549
2550 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2551 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2552 else
2553 flags |= RADEON_FLAG_CPU_ACCESS;
2554
2555 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2556 flags |= RADEON_FLAG_GTT_WC;
2557
2558 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2559 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2560
2561 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2562 domain, flags);
2563
2564 if (!mem->bo) {
2565 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2566 goto fail;
2567 }
2568 mem->type_index = mem_type_index;
2569 out_success:
2570 *pMem = radv_device_memory_to_handle(mem);
2571
2572 return VK_SUCCESS;
2573
2574 fail:
2575 vk_free2(&device->alloc, pAllocator, mem);
2576
2577 return result;
2578 }
2579
2580 VkResult radv_AllocateMemory(
2581 VkDevice _device,
2582 const VkMemoryAllocateInfo* pAllocateInfo,
2583 const VkAllocationCallbacks* pAllocator,
2584 VkDeviceMemory* pMem)
2585 {
2586 RADV_FROM_HANDLE(radv_device, device, _device);
2587 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2588 }
2589
2590 void radv_FreeMemory(
2591 VkDevice _device,
2592 VkDeviceMemory _mem,
2593 const VkAllocationCallbacks* pAllocator)
2594 {
2595 RADV_FROM_HANDLE(radv_device, device, _device);
2596 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2597
2598 if (mem == NULL)
2599 return;
2600
2601 device->ws->buffer_destroy(mem->bo);
2602 mem->bo = NULL;
2603
2604 vk_free2(&device->alloc, pAllocator, mem);
2605 }
2606
2607 VkResult radv_MapMemory(
2608 VkDevice _device,
2609 VkDeviceMemory _memory,
2610 VkDeviceSize offset,
2611 VkDeviceSize size,
2612 VkMemoryMapFlags flags,
2613 void** ppData)
2614 {
2615 RADV_FROM_HANDLE(radv_device, device, _device);
2616 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2617
2618 if (mem == NULL) {
2619 *ppData = NULL;
2620 return VK_SUCCESS;
2621 }
2622
2623 if (mem->user_ptr)
2624 *ppData = mem->user_ptr;
2625 else
2626 *ppData = device->ws->buffer_map(mem->bo);
2627
2628 if (*ppData) {
2629 *ppData += offset;
2630 return VK_SUCCESS;
2631 }
2632
2633 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2634 }
2635
2636 void radv_UnmapMemory(
2637 VkDevice _device,
2638 VkDeviceMemory _memory)
2639 {
2640 RADV_FROM_HANDLE(radv_device, device, _device);
2641 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2642
2643 if (mem == NULL)
2644 return;
2645
2646 if (mem->user_ptr == NULL)
2647 device->ws->buffer_unmap(mem->bo);
2648 }
2649
2650 VkResult radv_FlushMappedMemoryRanges(
2651 VkDevice _device,
2652 uint32_t memoryRangeCount,
2653 const VkMappedMemoryRange* pMemoryRanges)
2654 {
2655 return VK_SUCCESS;
2656 }
2657
2658 VkResult radv_InvalidateMappedMemoryRanges(
2659 VkDevice _device,
2660 uint32_t memoryRangeCount,
2661 const VkMappedMemoryRange* pMemoryRanges)
2662 {
2663 return VK_SUCCESS;
2664 }
2665
2666 void radv_GetBufferMemoryRequirements(
2667 VkDevice _device,
2668 VkBuffer _buffer,
2669 VkMemoryRequirements* pMemoryRequirements)
2670 {
2671 RADV_FROM_HANDLE(radv_device, device, _device);
2672 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2673
2674 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2675
2676 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2677 pMemoryRequirements->alignment = 4096;
2678 else
2679 pMemoryRequirements->alignment = 16;
2680
2681 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2682 }
2683
2684 void radv_GetBufferMemoryRequirements2(
2685 VkDevice device,
2686 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2687 VkMemoryRequirements2KHR* pMemoryRequirements)
2688 {
2689 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2690 &pMemoryRequirements->memoryRequirements);
2691 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2692 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2693 switch (ext->sType) {
2694 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2695 VkMemoryDedicatedRequirementsKHR *req =
2696 (VkMemoryDedicatedRequirementsKHR *) ext;
2697 req->requiresDedicatedAllocation = buffer->shareable;
2698 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2699 break;
2700 }
2701 default:
2702 break;
2703 }
2704 }
2705 }
2706
2707 void radv_GetImageMemoryRequirements(
2708 VkDevice _device,
2709 VkImage _image,
2710 VkMemoryRequirements* pMemoryRequirements)
2711 {
2712 RADV_FROM_HANDLE(radv_device, device, _device);
2713 RADV_FROM_HANDLE(radv_image, image, _image);
2714
2715 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2716
2717 pMemoryRequirements->size = image->size;
2718 pMemoryRequirements->alignment = image->alignment;
2719 }
2720
2721 void radv_GetImageMemoryRequirements2(
2722 VkDevice device,
2723 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2724 VkMemoryRequirements2KHR* pMemoryRequirements)
2725 {
2726 radv_GetImageMemoryRequirements(device, pInfo->image,
2727 &pMemoryRequirements->memoryRequirements);
2728
2729 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2730
2731 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2732 switch (ext->sType) {
2733 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2734 VkMemoryDedicatedRequirementsKHR *req =
2735 (VkMemoryDedicatedRequirementsKHR *) ext;
2736 req->requiresDedicatedAllocation = image->shareable;
2737 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2738 break;
2739 }
2740 default:
2741 break;
2742 }
2743 }
2744 }
2745
2746 void radv_GetImageSparseMemoryRequirements(
2747 VkDevice device,
2748 VkImage image,
2749 uint32_t* pSparseMemoryRequirementCount,
2750 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2751 {
2752 stub();
2753 }
2754
2755 void radv_GetImageSparseMemoryRequirements2(
2756 VkDevice device,
2757 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2758 uint32_t* pSparseMemoryRequirementCount,
2759 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2760 {
2761 stub();
2762 }
2763
2764 void radv_GetDeviceMemoryCommitment(
2765 VkDevice device,
2766 VkDeviceMemory memory,
2767 VkDeviceSize* pCommittedMemoryInBytes)
2768 {
2769 *pCommittedMemoryInBytes = 0;
2770 }
2771
2772 VkResult radv_BindBufferMemory2(VkDevice device,
2773 uint32_t bindInfoCount,
2774 const VkBindBufferMemoryInfoKHR *pBindInfos)
2775 {
2776 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2777 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2778 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2779
2780 if (mem) {
2781 buffer->bo = mem->bo;
2782 buffer->offset = pBindInfos[i].memoryOffset;
2783 } else {
2784 buffer->bo = NULL;
2785 }
2786 }
2787 return VK_SUCCESS;
2788 }
2789
2790 VkResult radv_BindBufferMemory(
2791 VkDevice device,
2792 VkBuffer buffer,
2793 VkDeviceMemory memory,
2794 VkDeviceSize memoryOffset)
2795 {
2796 const VkBindBufferMemoryInfoKHR info = {
2797 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2798 .buffer = buffer,
2799 .memory = memory,
2800 .memoryOffset = memoryOffset
2801 };
2802
2803 return radv_BindBufferMemory2(device, 1, &info);
2804 }
2805
2806 VkResult radv_BindImageMemory2(VkDevice device,
2807 uint32_t bindInfoCount,
2808 const VkBindImageMemoryInfoKHR *pBindInfos)
2809 {
2810 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2811 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2812 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2813
2814 if (mem) {
2815 image->bo = mem->bo;
2816 image->offset = pBindInfos[i].memoryOffset;
2817 } else {
2818 image->bo = NULL;
2819 image->offset = 0;
2820 }
2821 }
2822 return VK_SUCCESS;
2823 }
2824
2825
2826 VkResult radv_BindImageMemory(
2827 VkDevice device,
2828 VkImage image,
2829 VkDeviceMemory memory,
2830 VkDeviceSize memoryOffset)
2831 {
2832 const VkBindImageMemoryInfoKHR info = {
2833 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2834 .image = image,
2835 .memory = memory,
2836 .memoryOffset = memoryOffset
2837 };
2838
2839 return radv_BindImageMemory2(device, 1, &info);
2840 }
2841
2842
2843 static void
2844 radv_sparse_buffer_bind_memory(struct radv_device *device,
2845 const VkSparseBufferMemoryBindInfo *bind)
2846 {
2847 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2848
2849 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2850 struct radv_device_memory *mem = NULL;
2851
2852 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2853 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2854
2855 device->ws->buffer_virtual_bind(buffer->bo,
2856 bind->pBinds[i].resourceOffset,
2857 bind->pBinds[i].size,
2858 mem ? mem->bo : NULL,
2859 bind->pBinds[i].memoryOffset);
2860 }
2861 }
2862
2863 static void
2864 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2865 const VkSparseImageOpaqueMemoryBindInfo *bind)
2866 {
2867 RADV_FROM_HANDLE(radv_image, image, bind->image);
2868
2869 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2870 struct radv_device_memory *mem = NULL;
2871
2872 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2873 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2874
2875 device->ws->buffer_virtual_bind(image->bo,
2876 bind->pBinds[i].resourceOffset,
2877 bind->pBinds[i].size,
2878 mem ? mem->bo : NULL,
2879 bind->pBinds[i].memoryOffset);
2880 }
2881 }
2882
2883 VkResult radv_QueueBindSparse(
2884 VkQueue _queue,
2885 uint32_t bindInfoCount,
2886 const VkBindSparseInfo* pBindInfo,
2887 VkFence _fence)
2888 {
2889 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2890 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2891 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2892 bool fence_emitted = false;
2893
2894 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2895 struct radv_winsys_sem_info sem_info;
2896 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2897 radv_sparse_buffer_bind_memory(queue->device,
2898 pBindInfo[i].pBufferBinds + j);
2899 }
2900
2901 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2902 radv_sparse_image_opaque_bind_memory(queue->device,
2903 pBindInfo[i].pImageOpaqueBinds + j);
2904 }
2905
2906 VkResult result;
2907 result = radv_alloc_sem_info(&sem_info,
2908 pBindInfo[i].waitSemaphoreCount,
2909 pBindInfo[i].pWaitSemaphores,
2910 pBindInfo[i].signalSemaphoreCount,
2911 pBindInfo[i].pSignalSemaphores,
2912 _fence);
2913 if (result != VK_SUCCESS)
2914 return result;
2915
2916 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2917 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2918 &queue->device->empty_cs[queue->queue_family_index],
2919 1, NULL, NULL,
2920 &sem_info,
2921 false, base_fence);
2922 fence_emitted = true;
2923 if (fence)
2924 fence->submitted = true;
2925 }
2926
2927 radv_free_sem_info(&sem_info);
2928
2929 }
2930
2931 if (fence) {
2932 if (!fence_emitted) {
2933 radv_signal_fence(queue, fence);
2934 }
2935 fence->submitted = true;
2936 }
2937
2938 return VK_SUCCESS;
2939 }
2940
2941 VkResult radv_CreateFence(
2942 VkDevice _device,
2943 const VkFenceCreateInfo* pCreateInfo,
2944 const VkAllocationCallbacks* pAllocator,
2945 VkFence* pFence)
2946 {
2947 RADV_FROM_HANDLE(radv_device, device, _device);
2948 const VkExportFenceCreateInfoKHR *export =
2949 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2950 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2951 export ? export->handleTypes : 0;
2952
2953 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2954 sizeof(*fence), 8,
2955 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2956
2957 if (!fence)
2958 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2959
2960 fence->submitted = false;
2961 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2962 fence->temp_syncobj = 0;
2963 if (device->always_use_syncobj || handleTypes) {
2964 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2965 if (ret) {
2966 vk_free2(&device->alloc, pAllocator, fence);
2967 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2968 }
2969 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2970 device->ws->signal_syncobj(device->ws, fence->syncobj);
2971 }
2972 fence->fence = NULL;
2973 } else {
2974 fence->fence = device->ws->create_fence();
2975 if (!fence->fence) {
2976 vk_free2(&device->alloc, pAllocator, fence);
2977 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2978 }
2979 fence->syncobj = 0;
2980 }
2981
2982 *pFence = radv_fence_to_handle(fence);
2983
2984 return VK_SUCCESS;
2985 }
2986
2987 void radv_DestroyFence(
2988 VkDevice _device,
2989 VkFence _fence,
2990 const VkAllocationCallbacks* pAllocator)
2991 {
2992 RADV_FROM_HANDLE(radv_device, device, _device);
2993 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2994
2995 if (!fence)
2996 return;
2997
2998 if (fence->temp_syncobj)
2999 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3000 if (fence->syncobj)
3001 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3002 if (fence->fence)
3003 device->ws->destroy_fence(fence->fence);
3004 vk_free2(&device->alloc, pAllocator, fence);
3005 }
3006
3007
3008 static uint64_t radv_get_current_time()
3009 {
3010 struct timespec tv;
3011 clock_gettime(CLOCK_MONOTONIC, &tv);
3012 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3013 }
3014
3015 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3016 {
3017 uint64_t current_time = radv_get_current_time();
3018
3019 timeout = MIN2(UINT64_MAX - current_time, timeout);
3020
3021 return current_time + timeout;
3022 }
3023
3024
3025 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3026 {
3027 for (uint32_t i = 0; i < fenceCount; ++i) {
3028 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3029 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3030 return false;
3031 }
3032 return true;
3033 }
3034
3035 VkResult radv_WaitForFences(
3036 VkDevice _device,
3037 uint32_t fenceCount,
3038 const VkFence* pFences,
3039 VkBool32 waitAll,
3040 uint64_t timeout)
3041 {
3042 RADV_FROM_HANDLE(radv_device, device, _device);
3043 timeout = radv_get_absolute_timeout(timeout);
3044
3045 if (device->always_use_syncobj) {
3046 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3047 if (!handles)
3048 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3049
3050 for (uint32_t i = 0; i < fenceCount; ++i) {
3051 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3052 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3053 }
3054
3055 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3056
3057 free(handles);
3058 return success ? VK_SUCCESS : VK_TIMEOUT;
3059 }
3060
3061 if (!waitAll && fenceCount > 1) {
3062 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3063 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3064 uint32_t wait_count = 0;
3065 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3066 if (!fences)
3067 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3068
3069 for (uint32_t i = 0; i < fenceCount; ++i) {
3070 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3071
3072 if (fence->signalled) {
3073 free(fences);
3074 return VK_SUCCESS;
3075 }
3076
3077 fences[wait_count++] = fence->fence;
3078 }
3079
3080 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3081 waitAll, timeout - radv_get_current_time());
3082
3083 free(fences);
3084 return success ? VK_SUCCESS : VK_TIMEOUT;
3085 }
3086
3087 while(radv_get_current_time() <= timeout) {
3088 for (uint32_t i = 0; i < fenceCount; ++i) {
3089 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3090 return VK_SUCCESS;
3091 }
3092 }
3093 return VK_TIMEOUT;
3094 }
3095
3096 for (uint32_t i = 0; i < fenceCount; ++i) {
3097 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3098 bool expired = false;
3099
3100 if (fence->temp_syncobj) {
3101 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3102 return VK_TIMEOUT;
3103 continue;
3104 }
3105
3106 if (fence->syncobj) {
3107 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3108 return VK_TIMEOUT;
3109 continue;
3110 }
3111
3112 if (fence->signalled)
3113 continue;
3114
3115 if (!fence->submitted) {
3116 while(radv_get_current_time() <= timeout && !fence->submitted)
3117 /* Do nothing */;
3118
3119 if (!fence->submitted)
3120 return VK_TIMEOUT;
3121
3122 /* Recheck as it may have been set by submitting operations. */
3123 if (fence->signalled)
3124 continue;
3125 }
3126
3127 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3128 if (!expired)
3129 return VK_TIMEOUT;
3130
3131 fence->signalled = true;
3132 }
3133
3134 return VK_SUCCESS;
3135 }
3136
3137 VkResult radv_ResetFences(VkDevice _device,
3138 uint32_t fenceCount,
3139 const VkFence *pFences)
3140 {
3141 RADV_FROM_HANDLE(radv_device, device, _device);
3142
3143 for (unsigned i = 0; i < fenceCount; ++i) {
3144 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3145 fence->submitted = fence->signalled = false;
3146
3147 /* Per spec, we first restore the permanent payload, and then reset, so
3148 * having a temp syncobj should not skip resetting the permanent syncobj. */
3149 if (fence->temp_syncobj) {
3150 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3151 fence->temp_syncobj = 0;
3152 }
3153
3154 if (fence->syncobj) {
3155 device->ws->reset_syncobj(device->ws, fence->syncobj);
3156 }
3157 }
3158
3159 return VK_SUCCESS;
3160 }
3161
3162 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3163 {
3164 RADV_FROM_HANDLE(radv_device, device, _device);
3165 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3166
3167 if (fence->temp_syncobj) {
3168 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3169 return success ? VK_SUCCESS : VK_NOT_READY;
3170 }
3171
3172 if (fence->syncobj) {
3173 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3174 return success ? VK_SUCCESS : VK_NOT_READY;
3175 }
3176
3177 if (fence->signalled)
3178 return VK_SUCCESS;
3179 if (!fence->submitted)
3180 return VK_NOT_READY;
3181 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3182 return VK_NOT_READY;
3183
3184 return VK_SUCCESS;
3185 }
3186
3187
3188 // Queue semaphore functions
3189
3190 VkResult radv_CreateSemaphore(
3191 VkDevice _device,
3192 const VkSemaphoreCreateInfo* pCreateInfo,
3193 const VkAllocationCallbacks* pAllocator,
3194 VkSemaphore* pSemaphore)
3195 {
3196 RADV_FROM_HANDLE(radv_device, device, _device);
3197 const VkExportSemaphoreCreateInfoKHR *export =
3198 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3199 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3200 export ? export->handleTypes : 0;
3201
3202 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3203 sizeof(*sem), 8,
3204 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3205 if (!sem)
3206 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3207
3208 sem->temp_syncobj = 0;
3209 /* create a syncobject if we are going to export this semaphore */
3210 if (device->always_use_syncobj || handleTypes) {
3211 assert (device->physical_device->rad_info.has_syncobj);
3212 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3213 if (ret) {
3214 vk_free2(&device->alloc, pAllocator, sem);
3215 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3216 }
3217 sem->sem = NULL;
3218 } else {
3219 sem->sem = device->ws->create_sem(device->ws);
3220 if (!sem->sem) {
3221 vk_free2(&device->alloc, pAllocator, sem);
3222 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3223 }
3224 sem->syncobj = 0;
3225 }
3226
3227 *pSemaphore = radv_semaphore_to_handle(sem);
3228 return VK_SUCCESS;
3229 }
3230
3231 void radv_DestroySemaphore(
3232 VkDevice _device,
3233 VkSemaphore _semaphore,
3234 const VkAllocationCallbacks* pAllocator)
3235 {
3236 RADV_FROM_HANDLE(radv_device, device, _device);
3237 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3238 if (!_semaphore)
3239 return;
3240
3241 if (sem->syncobj)
3242 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3243 else
3244 device->ws->destroy_sem(sem->sem);
3245 vk_free2(&device->alloc, pAllocator, sem);
3246 }
3247
3248 VkResult radv_CreateEvent(
3249 VkDevice _device,
3250 const VkEventCreateInfo* pCreateInfo,
3251 const VkAllocationCallbacks* pAllocator,
3252 VkEvent* pEvent)
3253 {
3254 RADV_FROM_HANDLE(radv_device, device, _device);
3255 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3256 sizeof(*event), 8,
3257 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3258
3259 if (!event)
3260 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3261
3262 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3263 RADEON_DOMAIN_GTT,
3264 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3265 if (!event->bo) {
3266 vk_free2(&device->alloc, pAllocator, event);
3267 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3268 }
3269
3270 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3271
3272 *pEvent = radv_event_to_handle(event);
3273
3274 return VK_SUCCESS;
3275 }
3276
3277 void radv_DestroyEvent(
3278 VkDevice _device,
3279 VkEvent _event,
3280 const VkAllocationCallbacks* pAllocator)
3281 {
3282 RADV_FROM_HANDLE(radv_device, device, _device);
3283 RADV_FROM_HANDLE(radv_event, event, _event);
3284
3285 if (!event)
3286 return;
3287 device->ws->buffer_destroy(event->bo);
3288 vk_free2(&device->alloc, pAllocator, event);
3289 }
3290
3291 VkResult radv_GetEventStatus(
3292 VkDevice _device,
3293 VkEvent _event)
3294 {
3295 RADV_FROM_HANDLE(radv_event, event, _event);
3296
3297 if (*event->map == 1)
3298 return VK_EVENT_SET;
3299 return VK_EVENT_RESET;
3300 }
3301
3302 VkResult radv_SetEvent(
3303 VkDevice _device,
3304 VkEvent _event)
3305 {
3306 RADV_FROM_HANDLE(radv_event, event, _event);
3307 *event->map = 1;
3308
3309 return VK_SUCCESS;
3310 }
3311
3312 VkResult radv_ResetEvent(
3313 VkDevice _device,
3314 VkEvent _event)
3315 {
3316 RADV_FROM_HANDLE(radv_event, event, _event);
3317 *event->map = 0;
3318
3319 return VK_SUCCESS;
3320 }
3321
3322 VkResult radv_CreateBuffer(
3323 VkDevice _device,
3324 const VkBufferCreateInfo* pCreateInfo,
3325 const VkAllocationCallbacks* pAllocator,
3326 VkBuffer* pBuffer)
3327 {
3328 RADV_FROM_HANDLE(radv_device, device, _device);
3329 struct radv_buffer *buffer;
3330
3331 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3332
3333 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3334 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3335 if (buffer == NULL)
3336 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3337
3338 buffer->size = pCreateInfo->size;
3339 buffer->usage = pCreateInfo->usage;
3340 buffer->bo = NULL;
3341 buffer->offset = 0;
3342 buffer->flags = pCreateInfo->flags;
3343
3344 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3345 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3346
3347 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3348 buffer->bo = device->ws->buffer_create(device->ws,
3349 align64(buffer->size, 4096),
3350 4096, 0, RADEON_FLAG_VIRTUAL);
3351 if (!buffer->bo) {
3352 vk_free2(&device->alloc, pAllocator, buffer);
3353 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3354 }
3355 }
3356
3357 *pBuffer = radv_buffer_to_handle(buffer);
3358
3359 return VK_SUCCESS;
3360 }
3361
3362 void radv_DestroyBuffer(
3363 VkDevice _device,
3364 VkBuffer _buffer,
3365 const VkAllocationCallbacks* pAllocator)
3366 {
3367 RADV_FROM_HANDLE(radv_device, device, _device);
3368 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3369
3370 if (!buffer)
3371 return;
3372
3373 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3374 device->ws->buffer_destroy(buffer->bo);
3375
3376 vk_free2(&device->alloc, pAllocator, buffer);
3377 }
3378
3379 static inline unsigned
3380 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3381 {
3382 if (stencil)
3383 return image->surface.u.legacy.stencil_tiling_index[level];
3384 else
3385 return image->surface.u.legacy.tiling_index[level];
3386 }
3387
3388 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3389 {
3390 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3391 }
3392
3393 static void
3394 radv_initialise_color_surface(struct radv_device *device,
3395 struct radv_color_buffer_info *cb,
3396 struct radv_image_view *iview)
3397 {
3398 const struct vk_format_description *desc;
3399 unsigned ntype, format, swap, endian;
3400 unsigned blend_clamp = 0, blend_bypass = 0;
3401 uint64_t va;
3402 const struct radeon_surf *surf = &iview->image->surface;
3403
3404 desc = vk_format_description(iview->vk_format);
3405
3406 memset(cb, 0, sizeof(*cb));
3407
3408 /* Intensity is implemented as Red, so treat it that way. */
3409 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3410
3411 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3412
3413 cb->cb_color_base = va >> 8;
3414
3415 if (device->physical_device->rad_info.chip_class >= GFX9) {
3416 struct gfx9_surf_meta_flags meta;
3417 if (iview->image->dcc_offset)
3418 meta = iview->image->surface.u.gfx9.dcc;
3419 else
3420 meta = iview->image->surface.u.gfx9.cmask;
3421
3422 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3423 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3424 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3425 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3426
3427 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3428 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3429 } else {
3430 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3431 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3432
3433 cb->cb_color_base += level_info->offset >> 8;
3434 if (level_info->mode == RADEON_SURF_MODE_2D)
3435 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3436
3437 pitch_tile_max = level_info->nblk_x / 8 - 1;
3438 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3439 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3440
3441 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3442 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3443 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3444
3445 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3446
3447 if (iview->image->fmask.size) {
3448 if (device->physical_device->rad_info.chip_class >= CIK)
3449 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3450 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3451 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3452 } else {
3453 /* This must be set for fast clear to work without FMASK. */
3454 if (device->physical_device->rad_info.chip_class >= CIK)
3455 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3456 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3457 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3458 }
3459 }
3460
3461 /* CMASK variables */
3462 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3463 va += iview->image->cmask.offset;
3464 cb->cb_color_cmask = va >> 8;
3465
3466 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3467 va += iview->image->dcc_offset;
3468 cb->cb_dcc_base = va >> 8;
3469 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3470
3471 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3472 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3473 S_028C6C_SLICE_MAX(max_slice);
3474
3475 if (iview->image->info.samples > 1) {
3476 unsigned log_samples = util_logbase2(iview->image->info.samples);
3477
3478 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3479 S_028C74_NUM_FRAGMENTS(log_samples);
3480 }
3481
3482 if (iview->image->fmask.size) {
3483 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3484 cb->cb_color_fmask = va >> 8;
3485 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3486 } else {
3487 cb->cb_color_fmask = cb->cb_color_base;
3488 }
3489
3490 ntype = radv_translate_color_numformat(iview->vk_format,
3491 desc,
3492 vk_format_get_first_non_void_channel(iview->vk_format));
3493 format = radv_translate_colorformat(iview->vk_format);
3494 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3495 radv_finishme("Illegal color\n");
3496 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3497 endian = radv_colorformat_endian_swap(format);
3498
3499 /* blend clamp should be set for all NORM/SRGB types */
3500 if (ntype == V_028C70_NUMBER_UNORM ||
3501 ntype == V_028C70_NUMBER_SNORM ||
3502 ntype == V_028C70_NUMBER_SRGB)
3503 blend_clamp = 1;
3504
3505 /* set blend bypass according to docs if SINT/UINT or
3506 8/24 COLOR variants */
3507 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3508 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3509 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3510 blend_clamp = 0;
3511 blend_bypass = 1;
3512 }
3513 #if 0
3514 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3515 (format == V_028C70_COLOR_8 ||
3516 format == V_028C70_COLOR_8_8 ||
3517 format == V_028C70_COLOR_8_8_8_8))
3518 ->color_is_int8 = true;
3519 #endif
3520 cb->cb_color_info = S_028C70_FORMAT(format) |
3521 S_028C70_COMP_SWAP(swap) |
3522 S_028C70_BLEND_CLAMP(blend_clamp) |
3523 S_028C70_BLEND_BYPASS(blend_bypass) |
3524 S_028C70_SIMPLE_FLOAT(1) |
3525 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3526 ntype != V_028C70_NUMBER_SNORM &&
3527 ntype != V_028C70_NUMBER_SRGB &&
3528 format != V_028C70_COLOR_8_24 &&
3529 format != V_028C70_COLOR_24_8) |
3530 S_028C70_NUMBER_TYPE(ntype) |
3531 S_028C70_ENDIAN(endian);
3532 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3533 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3534 if (device->physical_device->rad_info.chip_class == SI) {
3535 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3536 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3537 }
3538 }
3539
3540 if (iview->image->cmask.size &&
3541 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3542 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3543
3544 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3545 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3546
3547 if (device->physical_device->rad_info.chip_class >= VI) {
3548 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3549 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3550 unsigned independent_64b_blocks = 0;
3551 unsigned max_compressed_block_size;
3552
3553 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3554 64 for APU because all of our APUs to date use DIMMs which have
3555 a request granularity size of 64B while all other chips have a
3556 32B request size */
3557 if (!device->physical_device->rad_info.has_dedicated_vram)
3558 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3559
3560 if (iview->image->info.samples > 1) {
3561 if (iview->image->surface.bpe == 1)
3562 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3563 else if (iview->image->surface.bpe == 2)
3564 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3565 }
3566
3567 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3568 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3569 independent_64b_blocks = 1;
3570 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3571 } else
3572 max_compressed_block_size = max_uncompressed_block_size;
3573
3574 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3575 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3576 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3577 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3578 }
3579
3580 /* This must be set for fast clear to work without FMASK. */
3581 if (!iview->image->fmask.size &&
3582 device->physical_device->rad_info.chip_class == SI) {
3583 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3584 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3585 }
3586
3587 if (device->physical_device->rad_info.chip_class >= GFX9) {
3588 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3589 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3590
3591 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3592 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3593 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3594 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3595 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3596 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3597 }
3598 }
3599
3600 static unsigned
3601 radv_calc_decompress_on_z_planes(struct radv_device *device,
3602 struct radv_image_view *iview)
3603 {
3604 unsigned max_zplanes = 0;
3605
3606 assert(iview->image->tc_compatible_htile);
3607
3608 if (device->physical_device->rad_info.chip_class >= GFX9) {
3609 /* Default value for 32-bit depth surfaces. */
3610 max_zplanes = 4;
3611
3612 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3613 iview->image->info.samples > 1)
3614 max_zplanes = 2;
3615
3616 max_zplanes = max_zplanes + 1;
3617 } else {
3618 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3619 /* Do not enable Z plane compression for 16-bit depth
3620 * surfaces because isn't supported on GFX8. Only
3621 * 32-bit depth surfaces are supported by the hardware.
3622 * This allows to maintain shader compatibility and to
3623 * reduce the number of depth decompressions.
3624 */
3625 max_zplanes = 1;
3626 } else {
3627 if (iview->image->info.samples <= 1)
3628 max_zplanes = 5;
3629 else if (iview->image->info.samples <= 4)
3630 max_zplanes = 3;
3631 else
3632 max_zplanes = 2;
3633 }
3634 }
3635
3636 return max_zplanes;
3637 }
3638
3639 static void
3640 radv_initialise_ds_surface(struct radv_device *device,
3641 struct radv_ds_buffer_info *ds,
3642 struct radv_image_view *iview)
3643 {
3644 unsigned level = iview->base_mip;
3645 unsigned format, stencil_format;
3646 uint64_t va, s_offs, z_offs;
3647 bool stencil_only = false;
3648 memset(ds, 0, sizeof(*ds));
3649 switch (iview->image->vk_format) {
3650 case VK_FORMAT_D24_UNORM_S8_UINT:
3651 case VK_FORMAT_X8_D24_UNORM_PACK32:
3652 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3653 ds->offset_scale = 2.0f;
3654 break;
3655 case VK_FORMAT_D16_UNORM:
3656 case VK_FORMAT_D16_UNORM_S8_UINT:
3657 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3658 ds->offset_scale = 4.0f;
3659 break;
3660 case VK_FORMAT_D32_SFLOAT:
3661 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3662 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3663 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3664 ds->offset_scale = 1.0f;
3665 break;
3666 case VK_FORMAT_S8_UINT:
3667 stencil_only = true;
3668 break;
3669 default:
3670 break;
3671 }
3672
3673 format = radv_translate_dbformat(iview->image->vk_format);
3674 stencil_format = iview->image->surface.has_stencil ?
3675 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3676
3677 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3678 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3679 S_028008_SLICE_MAX(max_slice);
3680
3681 ds->db_htile_data_base = 0;
3682 ds->db_htile_surface = 0;
3683
3684 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3685 s_offs = z_offs = va;
3686
3687 if (device->physical_device->rad_info.chip_class >= GFX9) {
3688 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3689 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3690
3691 ds->db_z_info = S_028038_FORMAT(format) |
3692 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3693 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3694 S_028038_MAXMIP(iview->image->info.levels - 1);
3695 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3696 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3697
3698 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3699 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3700 ds->db_depth_view |= S_028008_MIPID(level);
3701
3702 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3703 S_02801C_Y_MAX(iview->image->info.height - 1);
3704
3705 if (radv_htile_enabled(iview->image, level)) {
3706 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3707
3708 if (iview->image->tc_compatible_htile) {
3709 unsigned max_zplanes =
3710 radv_calc_decompress_on_z_planes(device, iview);
3711
3712 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3713 S_028038_ITERATE_FLUSH(1);
3714 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3715 }
3716
3717 if (!iview->image->surface.has_stencil)
3718 /* Use all of the htile_buffer for depth if there's no stencil. */
3719 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3720 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3721 iview->image->htile_offset;
3722 ds->db_htile_data_base = va >> 8;
3723 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3724 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3725 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3726 }
3727 } else {
3728 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3729
3730 if (stencil_only)
3731 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3732
3733 z_offs += iview->image->surface.u.legacy.level[level].offset;
3734 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3735
3736 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3737 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3738 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3739
3740 if (iview->image->info.samples > 1)
3741 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3742
3743 if (device->physical_device->rad_info.chip_class >= CIK) {
3744 struct radeon_info *info = &device->physical_device->rad_info;
3745 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3746 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3747 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3748 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3749 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3750 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3751
3752 if (stencil_only)
3753 tile_mode = stencil_tile_mode;
3754
3755 ds->db_depth_info |=
3756 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3757 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3758 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3759 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3760 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3761 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3762 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3763 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3764 } else {
3765 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3766 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3767 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3768 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3769 if (stencil_only)
3770 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3771 }
3772
3773 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3774 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3775 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3776
3777 if (radv_htile_enabled(iview->image, level)) {
3778 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3779
3780 if (!iview->image->surface.has_stencil &&
3781 !iview->image->tc_compatible_htile)
3782 /* Use all of the htile_buffer for depth if there's no stencil. */
3783 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3784
3785 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3786 iview->image->htile_offset;
3787 ds->db_htile_data_base = va >> 8;
3788 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3789
3790 if (iview->image->tc_compatible_htile) {
3791 unsigned max_zplanes =
3792 radv_calc_decompress_on_z_planes(device, iview);
3793
3794 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3795 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
3796 }
3797 }
3798 }
3799
3800 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3801 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3802 }
3803
3804 VkResult radv_CreateFramebuffer(
3805 VkDevice _device,
3806 const VkFramebufferCreateInfo* pCreateInfo,
3807 const VkAllocationCallbacks* pAllocator,
3808 VkFramebuffer* pFramebuffer)
3809 {
3810 RADV_FROM_HANDLE(radv_device, device, _device);
3811 struct radv_framebuffer *framebuffer;
3812
3813 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3814
3815 size_t size = sizeof(*framebuffer) +
3816 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3817 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3818 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3819 if (framebuffer == NULL)
3820 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3821
3822 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3823 framebuffer->width = pCreateInfo->width;
3824 framebuffer->height = pCreateInfo->height;
3825 framebuffer->layers = pCreateInfo->layers;
3826 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3827 VkImageView _iview = pCreateInfo->pAttachments[i];
3828 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3829 framebuffer->attachments[i].attachment = iview;
3830 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3831 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3832 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3833 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3834 }
3835 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3836 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3837 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3838 }
3839
3840 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3841 return VK_SUCCESS;
3842 }
3843
3844 void radv_DestroyFramebuffer(
3845 VkDevice _device,
3846 VkFramebuffer _fb,
3847 const VkAllocationCallbacks* pAllocator)
3848 {
3849 RADV_FROM_HANDLE(radv_device, device, _device);
3850 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3851
3852 if (!fb)
3853 return;
3854 vk_free2(&device->alloc, pAllocator, fb);
3855 }
3856
3857 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3858 {
3859 switch (address_mode) {
3860 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3861 return V_008F30_SQ_TEX_WRAP;
3862 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3863 return V_008F30_SQ_TEX_MIRROR;
3864 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3865 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3866 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3867 return V_008F30_SQ_TEX_CLAMP_BORDER;
3868 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3869 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3870 default:
3871 unreachable("illegal tex wrap mode");
3872 break;
3873 }
3874 }
3875
3876 static unsigned
3877 radv_tex_compare(VkCompareOp op)
3878 {
3879 switch (op) {
3880 case VK_COMPARE_OP_NEVER:
3881 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3882 case VK_COMPARE_OP_LESS:
3883 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3884 case VK_COMPARE_OP_EQUAL:
3885 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3886 case VK_COMPARE_OP_LESS_OR_EQUAL:
3887 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3888 case VK_COMPARE_OP_GREATER:
3889 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3890 case VK_COMPARE_OP_NOT_EQUAL:
3891 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3892 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3893 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3894 case VK_COMPARE_OP_ALWAYS:
3895 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3896 default:
3897 unreachable("illegal compare mode");
3898 break;
3899 }
3900 }
3901
3902 static unsigned
3903 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3904 {
3905 switch (filter) {
3906 case VK_FILTER_NEAREST:
3907 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3908 V_008F38_SQ_TEX_XY_FILTER_POINT);
3909 case VK_FILTER_LINEAR:
3910 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3911 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3912 case VK_FILTER_CUBIC_IMG:
3913 default:
3914 fprintf(stderr, "illegal texture filter");
3915 return 0;
3916 }
3917 }
3918
3919 static unsigned
3920 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3921 {
3922 switch (mode) {
3923 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3924 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3925 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3926 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3927 default:
3928 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3929 }
3930 }
3931
3932 static unsigned
3933 radv_tex_bordercolor(VkBorderColor bcolor)
3934 {
3935 switch (bcolor) {
3936 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3937 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3938 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3939 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3940 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3941 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3942 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3943 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3944 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3945 default:
3946 break;
3947 }
3948 return 0;
3949 }
3950
3951 static unsigned
3952 radv_tex_aniso_filter(unsigned filter)
3953 {
3954 if (filter < 2)
3955 return 0;
3956 if (filter < 4)
3957 return 1;
3958 if (filter < 8)
3959 return 2;
3960 if (filter < 16)
3961 return 3;
3962 return 4;
3963 }
3964
3965 static void
3966 radv_init_sampler(struct radv_device *device,
3967 struct radv_sampler *sampler,
3968 const VkSamplerCreateInfo *pCreateInfo)
3969 {
3970 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3971 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3972 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3973 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3974
3975 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3976 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3977 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3978 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3979 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3980 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3981 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3982 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3983 S_008F30_DISABLE_CUBE_WRAP(0) |
3984 S_008F30_COMPAT_MODE(is_vi));
3985 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3986 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3987 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3988 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3989 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3990 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3991 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3992 S_008F38_MIP_POINT_PRECLAMP(0) |
3993 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3994 S_008F38_FILTER_PREC_FIX(1) |
3995 S_008F38_ANISO_OVERRIDE(is_vi));
3996 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3997 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3998 }
3999
4000 VkResult radv_CreateSampler(
4001 VkDevice _device,
4002 const VkSamplerCreateInfo* pCreateInfo,
4003 const VkAllocationCallbacks* pAllocator,
4004 VkSampler* pSampler)
4005 {
4006 RADV_FROM_HANDLE(radv_device, device, _device);
4007 struct radv_sampler *sampler;
4008
4009 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4010
4011 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4012 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4013 if (!sampler)
4014 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4015
4016 radv_init_sampler(device, sampler, pCreateInfo);
4017 *pSampler = radv_sampler_to_handle(sampler);
4018
4019 return VK_SUCCESS;
4020 }
4021
4022 void radv_DestroySampler(
4023 VkDevice _device,
4024 VkSampler _sampler,
4025 const VkAllocationCallbacks* pAllocator)
4026 {
4027 RADV_FROM_HANDLE(radv_device, device, _device);
4028 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4029
4030 if (!sampler)
4031 return;
4032 vk_free2(&device->alloc, pAllocator, sampler);
4033 }
4034
4035 /* vk_icd.h does not declare this function, so we declare it here to
4036 * suppress Wmissing-prototypes.
4037 */
4038 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4039 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4040
4041 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4042 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4043 {
4044 /* For the full details on loader interface versioning, see
4045 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4046 * What follows is a condensed summary, to help you navigate the large and
4047 * confusing official doc.
4048 *
4049 * - Loader interface v0 is incompatible with later versions. We don't
4050 * support it.
4051 *
4052 * - In loader interface v1:
4053 * - The first ICD entrypoint called by the loader is
4054 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4055 * entrypoint.
4056 * - The ICD must statically expose no other Vulkan symbol unless it is
4057 * linked with -Bsymbolic.
4058 * - Each dispatchable Vulkan handle created by the ICD must be
4059 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4060 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4061 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4062 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4063 * such loader-managed surfaces.
4064 *
4065 * - Loader interface v2 differs from v1 in:
4066 * - The first ICD entrypoint called by the loader is
4067 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4068 * statically expose this entrypoint.
4069 *
4070 * - Loader interface v3 differs from v2 in:
4071 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4072 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4073 * because the loader no longer does so.
4074 */
4075 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4076 return VK_SUCCESS;
4077 }
4078
4079 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4080 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4081 int *pFD)
4082 {
4083 RADV_FROM_HANDLE(radv_device, device, _device);
4084 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4085
4086 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4087
4088 /* At the moment, we support only the below handle types. */
4089 assert(pGetFdInfo->handleType ==
4090 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4091 pGetFdInfo->handleType ==
4092 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4093
4094 bool ret = radv_get_memory_fd(device, memory, pFD);
4095 if (ret == false)
4096 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4097 return VK_SUCCESS;
4098 }
4099
4100 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4101 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4102 int fd,
4103 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4104 {
4105 switch (handleType) {
4106 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4107 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4108 return VK_SUCCESS;
4109
4110 default:
4111 /* The valid usage section for this function says:
4112 *
4113 * "handleType must not be one of the handle types defined as
4114 * opaque."
4115 *
4116 * So opaque handle types fall into the default "unsupported" case.
4117 */
4118 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4119 }
4120 }
4121
4122 static VkResult radv_import_opaque_fd(struct radv_device *device,
4123 int fd,
4124 uint32_t *syncobj)
4125 {
4126 uint32_t syncobj_handle = 0;
4127 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4128 if (ret != 0)
4129 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4130
4131 if (*syncobj)
4132 device->ws->destroy_syncobj(device->ws, *syncobj);
4133
4134 *syncobj = syncobj_handle;
4135 close(fd);
4136
4137 return VK_SUCCESS;
4138 }
4139
4140 static VkResult radv_import_sync_fd(struct radv_device *device,
4141 int fd,
4142 uint32_t *syncobj)
4143 {
4144 /* If we create a syncobj we do it locally so that if we have an error, we don't
4145 * leave a syncobj in an undetermined state in the fence. */
4146 uint32_t syncobj_handle = *syncobj;
4147 if (!syncobj_handle) {
4148 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4149 if (ret) {
4150 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4151 }
4152 }
4153
4154 if (fd == -1) {
4155 device->ws->signal_syncobj(device->ws, syncobj_handle);
4156 } else {
4157 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4158 if (ret != 0)
4159 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4160 }
4161
4162 *syncobj = syncobj_handle;
4163 if (fd != -1)
4164 close(fd);
4165
4166 return VK_SUCCESS;
4167 }
4168
4169 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4170 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4171 {
4172 RADV_FROM_HANDLE(radv_device, device, _device);
4173 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4174 uint32_t *syncobj_dst = NULL;
4175
4176 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4177 syncobj_dst = &sem->temp_syncobj;
4178 } else {
4179 syncobj_dst = &sem->syncobj;
4180 }
4181
4182 switch(pImportSemaphoreFdInfo->handleType) {
4183 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4184 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4185 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4186 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4187 default:
4188 unreachable("Unhandled semaphore handle type");
4189 }
4190 }
4191
4192 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4193 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4194 int *pFd)
4195 {
4196 RADV_FROM_HANDLE(radv_device, device, _device);
4197 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4198 int ret;
4199 uint32_t syncobj_handle;
4200
4201 if (sem->temp_syncobj)
4202 syncobj_handle = sem->temp_syncobj;
4203 else
4204 syncobj_handle = sem->syncobj;
4205
4206 switch(pGetFdInfo->handleType) {
4207 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4208 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4209 break;
4210 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4211 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4212 if (!ret) {
4213 if (sem->temp_syncobj) {
4214 close (sem->temp_syncobj);
4215 sem->temp_syncobj = 0;
4216 } else {
4217 device->ws->reset_syncobj(device->ws, syncobj_handle);
4218 }
4219 }
4220 break;
4221 default:
4222 unreachable("Unhandled semaphore handle type");
4223 }
4224
4225 if (ret)
4226 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4227 return VK_SUCCESS;
4228 }
4229
4230 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4231 VkPhysicalDevice physicalDevice,
4232 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4233 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4234 {
4235 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4236
4237 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4238 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4239 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4240 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4241 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4242 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4243 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4244 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4245 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4246 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4247 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4248 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4249 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4250 } else {
4251 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4252 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4253 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4254 }
4255 }
4256
4257 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4258 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4259 {
4260 RADV_FROM_HANDLE(radv_device, device, _device);
4261 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4262 uint32_t *syncobj_dst = NULL;
4263
4264
4265 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4266 syncobj_dst = &fence->temp_syncobj;
4267 } else {
4268 syncobj_dst = &fence->syncobj;
4269 }
4270
4271 switch(pImportFenceFdInfo->handleType) {
4272 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4273 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4274 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4275 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4276 default:
4277 unreachable("Unhandled fence handle type");
4278 }
4279 }
4280
4281 VkResult radv_GetFenceFdKHR(VkDevice _device,
4282 const VkFenceGetFdInfoKHR *pGetFdInfo,
4283 int *pFd)
4284 {
4285 RADV_FROM_HANDLE(radv_device, device, _device);
4286 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4287 int ret;
4288 uint32_t syncobj_handle;
4289
4290 if (fence->temp_syncobj)
4291 syncobj_handle = fence->temp_syncobj;
4292 else
4293 syncobj_handle = fence->syncobj;
4294
4295 switch(pGetFdInfo->handleType) {
4296 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4297 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4298 break;
4299 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4300 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4301 if (!ret) {
4302 if (fence->temp_syncobj) {
4303 close (fence->temp_syncobj);
4304 fence->temp_syncobj = 0;
4305 } else {
4306 device->ws->reset_syncobj(device->ws, syncobj_handle);
4307 }
4308 }
4309 break;
4310 default:
4311 unreachable("Unhandled fence handle type");
4312 }
4313
4314 if (ret)
4315 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4316 return VK_SUCCESS;
4317 }
4318
4319 void radv_GetPhysicalDeviceExternalFenceProperties(
4320 VkPhysicalDevice physicalDevice,
4321 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4322 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4323 {
4324 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4325
4326 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4327 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4328 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4329 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4330 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4331 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4332 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4333 } else {
4334 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4335 pExternalFenceProperties->compatibleHandleTypes = 0;
4336 pExternalFenceProperties->externalFenceFeatures = 0;
4337 }
4338 }
4339
4340 VkResult
4341 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4342 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4343 const VkAllocationCallbacks* pAllocator,
4344 VkDebugReportCallbackEXT* pCallback)
4345 {
4346 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4347 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4348 pCreateInfo, pAllocator, &instance->alloc,
4349 pCallback);
4350 }
4351
4352 void
4353 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4354 VkDebugReportCallbackEXT _callback,
4355 const VkAllocationCallbacks* pAllocator)
4356 {
4357 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4358 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4359 _callback, pAllocator, &instance->alloc);
4360 }
4361
4362 void
4363 radv_DebugReportMessageEXT(VkInstance _instance,
4364 VkDebugReportFlagsEXT flags,
4365 VkDebugReportObjectTypeEXT objectType,
4366 uint64_t object,
4367 size_t location,
4368 int32_t messageCode,
4369 const char* pLayerPrefix,
4370 const char* pMessage)
4371 {
4372 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4373 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4374 object, location, messageCode, pLayerPrefix, pMessage);
4375 }
4376
4377 void
4378 radv_GetDeviceGroupPeerMemoryFeatures(
4379 VkDevice device,
4380 uint32_t heapIndex,
4381 uint32_t localDeviceIndex,
4382 uint32_t remoteDeviceIndex,
4383 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4384 {
4385 assert(localDeviceIndex == remoteDeviceIndex);
4386
4387 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4388 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4389 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4390 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4391 }