2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/debug.h"
50 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
52 uint32_t mesa_timestamp
, llvm_timestamp
;
54 memset(uuid
, 0, VK_UUID_SIZE
);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
59 memcpy(uuid
, &mesa_timestamp
, 4);
60 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
61 memcpy((char*)uuid
+ 8, &f
, 2);
62 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
67 radv_get_driver_uuid(void *uuid
)
69 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
73 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
75 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
79 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
81 const char *chip_string
;
82 char llvm_string
[32] = {};
85 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
89 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
92 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
93 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS
: chip_string
= "AMD RADV MULLINS"; break;
95 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
96 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
103 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA"; break;
104 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
105 default: chip_string
= "AMD RADV unknown"; break;
109 snprintf(llvm_string
, sizeof(llvm_string
),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM
>> 8) & 0xff,
111 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
114 snprintf(name
, name_len
, "%s%s", chip_string
, llvm_string
);
118 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
121 uint64_t visible_vram_size
= MIN2(device
->rad_info
.vram_size
,
122 device
->rad_info
.vram_vis_size
);
124 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
125 device
->memory_properties
.memoryHeapCount
= 0;
126 if (device
->rad_info
.vram_size
- visible_vram_size
> 0) {
127 vram_index
= device
->memory_properties
.memoryHeapCount
++;
128 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
129 .size
= device
->rad_info
.vram_size
- visible_vram_size
,
130 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
133 if (visible_vram_size
) {
134 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
135 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
136 .size
= visible_vram_size
,
137 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
140 if (device
->rad_info
.gart_size
> 0) {
141 gart_index
= device
->memory_properties
.memoryHeapCount
++;
142 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
143 .size
= device
->rad_info
.gart_size
,
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
149 unsigned type_count
= 0;
150 if (vram_index
>= 0) {
151 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
152 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
153 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
154 .heapIndex
= vram_index
,
157 if (gart_index
>= 0) {
158 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
159 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
160 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
162 .heapIndex
= gart_index
,
165 if (visible_vram_index
>= 0) {
166 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
167 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
168 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
171 .heapIndex
= visible_vram_index
,
174 if (gart_index
>= 0) {
175 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
176 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
177 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
180 .heapIndex
= gart_index
,
183 device
->memory_properties
.memoryTypeCount
= type_count
;
187 radv_physical_device_init(struct radv_physical_device
*device
,
188 struct radv_instance
*instance
,
189 drmDevicePtr drm_device
)
191 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
193 drmVersionPtr version
;
196 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER
);
200 version
= drmGetVersion(fd
);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
204 "failed to get version %s: %m", path
);
207 if (strcmp(version
->name
, "amdgpu")) {
208 drmFreeVersion(version
);
210 return VK_ERROR_INCOMPATIBLE_DRIVER
;
212 drmFreeVersion(version
);
214 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
215 device
->instance
= instance
;
216 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
217 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
219 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
220 instance
->perftest_flags
);
222 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
226 device
->local_fd
= fd
;
227 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
229 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
231 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
232 device
->ws
->destroy(device
->ws
);
233 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
234 "cannot generate UUID");
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags
=
240 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
241 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
246 char buf
[VK_UUID_SIZE
* 2 + 1];
247 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
248 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
250 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
252 radv_get_driver_uuid(&device
->device_uuid
);
253 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
255 if (device
->rad_info
.family
== CHIP_STONEY
||
256 device
->rad_info
.chip_class
>= GFX9
) {
257 device
->has_rbplus
= true;
258 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
;
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
264 device
->has_clear_state
= device
->rad_info
.chip_class
>= CIK
;
266 radv_physical_device_init_mem_types(device
);
268 result
= radv_init_wsi(device
);
269 if (result
!= VK_SUCCESS
) {
270 device
->ws
->destroy(device
->ws
);
282 radv_physical_device_finish(struct radv_physical_device
*device
)
284 radv_finish_wsi(device
);
285 device
->ws
->destroy(device
->ws
);
286 disk_cache_destroy(device
->disk_cache
);
287 close(device
->local_fd
);
291 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
292 VkSystemAllocationScope allocationScope
)
298 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
299 size_t align
, VkSystemAllocationScope allocationScope
)
301 return realloc(pOriginal
, size
);
305 default_free_func(void *pUserData
, void *pMemory
)
310 static const VkAllocationCallbacks default_alloc
= {
312 .pfnAllocation
= default_alloc_func
,
313 .pfnReallocation
= default_realloc_func
,
314 .pfnFree
= default_free_func
,
317 static const struct debug_control radv_debug_options
[] = {
318 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
319 {"nodcc", RADV_DEBUG_NO_DCC
},
320 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
321 {"nocache", RADV_DEBUG_NO_CACHE
},
322 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
323 {"nohiz", RADV_DEBUG_NO_HIZ
},
324 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
325 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
326 {"allbos", RADV_DEBUG_ALL_BOS
},
327 {"noibs", RADV_DEBUG_NO_IBS
},
328 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
329 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
330 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
331 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
332 {"nosisched", RADV_DEBUG_NO_SISCHED
},
337 radv_get_debug_option_name(int id
)
339 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
340 return radv_debug_options
[id
].string
;
343 static const struct debug_control radv_perftest_options
[] = {
344 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
345 {"sisched", RADV_PERFTEST_SISCHED
},
350 radv_get_perftest_option_name(int id
)
352 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
353 return radv_perftest_options
[id
].string
;
357 radv_handle_per_app_options(struct radv_instance
*instance
,
358 const VkApplicationInfo
*info
)
360 const char *name
= info
? info
->pApplicationName
: NULL
;
365 if (!strcmp(name
, "Talos - Linux - 32bit") ||
366 !strcmp(name
, "Talos - Linux - 64bit")) {
367 /* Force enable LLVM sisched for Talos because it looks safe
368 * and it gives few more FPS.
370 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
374 VkResult
radv_CreateInstance(
375 const VkInstanceCreateInfo
* pCreateInfo
,
376 const VkAllocationCallbacks
* pAllocator
,
377 VkInstance
* pInstance
)
379 struct radv_instance
*instance
;
381 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
383 uint32_t client_version
;
384 if (pCreateInfo
->pApplicationInfo
&&
385 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
386 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
388 client_version
= VK_MAKE_VERSION(1, 0, 0);
391 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
392 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
393 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
394 "Client requested version %d.%d.%d",
395 VK_VERSION_MAJOR(client_version
),
396 VK_VERSION_MINOR(client_version
),
397 VK_VERSION_PATCH(client_version
));
400 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
401 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
402 if (!radv_instance_extension_supported(ext_name
))
403 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
406 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
407 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
409 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
411 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
414 instance
->alloc
= *pAllocator
;
416 instance
->alloc
= default_alloc
;
418 instance
->apiVersion
= client_version
;
419 instance
->physicalDeviceCount
= -1;
423 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
425 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
428 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
429 radv_perftest_options
);
431 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
433 if (instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
) {
434 /* Disable sisched when the user requests it, this is mostly
435 * useful when the driver force-enable sisched for the given
438 instance
->perftest_flags
&= ~RADV_PERFTEST_SISCHED
;
441 *pInstance
= radv_instance_to_handle(instance
);
446 void radv_DestroyInstance(
447 VkInstance _instance
,
448 const VkAllocationCallbacks
* pAllocator
)
450 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
455 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
456 radv_physical_device_finish(instance
->physicalDevices
+ i
);
459 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
463 vk_free(&instance
->alloc
, instance
);
467 radv_enumerate_devices(struct radv_instance
*instance
)
469 /* TODO: Check for more devices ? */
470 drmDevicePtr devices
[8];
471 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
474 instance
->physicalDeviceCount
= 0;
476 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
478 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER
);
480 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
481 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
482 devices
[i
]->bustype
== DRM_BUS_PCI
&&
483 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
485 result
= radv_physical_device_init(instance
->physicalDevices
+
486 instance
->physicalDeviceCount
,
489 if (result
== VK_SUCCESS
)
490 ++instance
->physicalDeviceCount
;
491 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
495 drmFreeDevices(devices
, max_devices
);
500 VkResult
radv_EnumeratePhysicalDevices(
501 VkInstance _instance
,
502 uint32_t* pPhysicalDeviceCount
,
503 VkPhysicalDevice
* pPhysicalDevices
)
505 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
508 if (instance
->physicalDeviceCount
< 0) {
509 result
= radv_enumerate_devices(instance
);
510 if (result
!= VK_SUCCESS
&&
511 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
515 if (!pPhysicalDevices
) {
516 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
518 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
519 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
520 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
523 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
527 void radv_GetPhysicalDeviceFeatures(
528 VkPhysicalDevice physicalDevice
,
529 VkPhysicalDeviceFeatures
* pFeatures
)
531 memset(pFeatures
, 0, sizeof(*pFeatures
));
533 *pFeatures
= (VkPhysicalDeviceFeatures
) {
534 .robustBufferAccess
= true,
535 .fullDrawIndexUint32
= true,
536 .imageCubeArray
= true,
537 .independentBlend
= true,
538 .geometryShader
= true,
539 .tessellationShader
= true,
540 .sampleRateShading
= true,
541 .dualSrcBlend
= true,
543 .multiDrawIndirect
= true,
544 .drawIndirectFirstInstance
= true,
546 .depthBiasClamp
= true,
547 .fillModeNonSolid
= true,
552 .multiViewport
= true,
553 .samplerAnisotropy
= true,
554 .textureCompressionETC2
= false,
555 .textureCompressionASTC_LDR
= false,
556 .textureCompressionBC
= true,
557 .occlusionQueryPrecise
= true,
558 .pipelineStatisticsQuery
= true,
559 .vertexPipelineStoresAndAtomics
= true,
560 .fragmentStoresAndAtomics
= true,
561 .shaderTessellationAndGeometryPointSize
= true,
562 .shaderImageGatherExtended
= true,
563 .shaderStorageImageExtendedFormats
= true,
564 .shaderStorageImageMultisample
= false,
565 .shaderUniformBufferArrayDynamicIndexing
= true,
566 .shaderSampledImageArrayDynamicIndexing
= true,
567 .shaderStorageBufferArrayDynamicIndexing
= true,
568 .shaderStorageImageArrayDynamicIndexing
= true,
569 .shaderStorageImageReadWithoutFormat
= true,
570 .shaderStorageImageWriteWithoutFormat
= true,
571 .shaderClipDistance
= true,
572 .shaderCullDistance
= true,
573 .shaderFloat64
= true,
575 .shaderInt16
= false,
576 .sparseBinding
= true,
577 .variableMultisampleRate
= true,
578 .inheritedQueries
= true,
582 void radv_GetPhysicalDeviceFeatures2KHR(
583 VkPhysicalDevice physicalDevice
,
584 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
586 vk_foreach_struct(ext
, pFeatures
->pNext
) {
587 switch (ext
->sType
) {
588 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR
: {
589 VkPhysicalDeviceVariablePointerFeaturesKHR
*features
= (void *)ext
;
590 features
->variablePointersStorageBuffer
= true;
591 features
->variablePointers
= false;
594 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX
: {
595 VkPhysicalDeviceMultiviewFeaturesKHX
*features
= (VkPhysicalDeviceMultiviewFeaturesKHX
*)ext
;
596 features
->multiview
= true;
597 features
->multiviewGeometryShader
= true;
598 features
->multiviewTessellationShader
= true;
605 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
608 void radv_GetPhysicalDeviceProperties(
609 VkPhysicalDevice physicalDevice
,
610 VkPhysicalDeviceProperties
* pProperties
)
612 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
613 VkSampleCountFlags sample_counts
= 0xf;
615 /* make sure that the entire descriptor set is addressable with a signed
616 * 32-bit int. So the sum of all limits scaled by descriptor size has to
617 * be at most 2 GiB. the combined image & samples object count as one of
618 * both. This limit is for the pipeline layout, not for the set layout, but
619 * there is no set limit, so we just set a pipeline limit. I don't think
620 * any app is going to hit this soon. */
621 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
622 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
623 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
624 32 /* sampler, largest when combined with image */ +
625 64 /* sampled image */ +
626 64 /* storage image */);
628 VkPhysicalDeviceLimits limits
= {
629 .maxImageDimension1D
= (1 << 14),
630 .maxImageDimension2D
= (1 << 14),
631 .maxImageDimension3D
= (1 << 11),
632 .maxImageDimensionCube
= (1 << 14),
633 .maxImageArrayLayers
= (1 << 11),
634 .maxTexelBufferElements
= 128 * 1024 * 1024,
635 .maxUniformBufferRange
= UINT32_MAX
,
636 .maxStorageBufferRange
= UINT32_MAX
,
637 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
638 .maxMemoryAllocationCount
= UINT32_MAX
,
639 .maxSamplerAllocationCount
= 64 * 1024,
640 .bufferImageGranularity
= 64, /* A cache line */
641 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
642 .maxBoundDescriptorSets
= MAX_SETS
,
643 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
644 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
645 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
646 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
647 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
648 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
649 .maxPerStageResources
= max_descriptor_set_size
,
650 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
651 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
652 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
653 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
654 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
655 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
656 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
657 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
658 .maxVertexInputAttributes
= 32,
659 .maxVertexInputBindings
= 32,
660 .maxVertexInputAttributeOffset
= 2047,
661 .maxVertexInputBindingStride
= 2048,
662 .maxVertexOutputComponents
= 128,
663 .maxTessellationGenerationLevel
= 64,
664 .maxTessellationPatchSize
= 32,
665 .maxTessellationControlPerVertexInputComponents
= 128,
666 .maxTessellationControlPerVertexOutputComponents
= 128,
667 .maxTessellationControlPerPatchOutputComponents
= 120,
668 .maxTessellationControlTotalOutputComponents
= 4096,
669 .maxTessellationEvaluationInputComponents
= 128,
670 .maxTessellationEvaluationOutputComponents
= 128,
671 .maxGeometryShaderInvocations
= 127,
672 .maxGeometryInputComponents
= 64,
673 .maxGeometryOutputComponents
= 128,
674 .maxGeometryOutputVertices
= 256,
675 .maxGeometryTotalOutputComponents
= 1024,
676 .maxFragmentInputComponents
= 128,
677 .maxFragmentOutputAttachments
= 8,
678 .maxFragmentDualSrcAttachments
= 1,
679 .maxFragmentCombinedOutputResources
= 8,
680 .maxComputeSharedMemorySize
= 32768,
681 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
682 .maxComputeWorkGroupInvocations
= 2048,
683 .maxComputeWorkGroupSize
= {
688 .subPixelPrecisionBits
= 4 /* FIXME */,
689 .subTexelPrecisionBits
= 4 /* FIXME */,
690 .mipmapPrecisionBits
= 4 /* FIXME */,
691 .maxDrawIndexedIndexValue
= UINT32_MAX
,
692 .maxDrawIndirectCount
= UINT32_MAX
,
693 .maxSamplerLodBias
= 16,
694 .maxSamplerAnisotropy
= 16,
695 .maxViewports
= MAX_VIEWPORTS
,
696 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
697 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
698 .viewportSubPixelBits
= 13, /* We take a float? */
699 .minMemoryMapAlignment
= 4096, /* A page */
700 .minTexelBufferOffsetAlignment
= 1,
701 .minUniformBufferOffsetAlignment
= 4,
702 .minStorageBufferOffsetAlignment
= 4,
703 .minTexelOffset
= -32,
704 .maxTexelOffset
= 31,
705 .minTexelGatherOffset
= -32,
706 .maxTexelGatherOffset
= 31,
707 .minInterpolationOffset
= -2,
708 .maxInterpolationOffset
= 2,
709 .subPixelInterpolationOffsetBits
= 8,
710 .maxFramebufferWidth
= (1 << 14),
711 .maxFramebufferHeight
= (1 << 14),
712 .maxFramebufferLayers
= (1 << 10),
713 .framebufferColorSampleCounts
= sample_counts
,
714 .framebufferDepthSampleCounts
= sample_counts
,
715 .framebufferStencilSampleCounts
= sample_counts
,
716 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
717 .maxColorAttachments
= MAX_RTS
,
718 .sampledImageColorSampleCounts
= sample_counts
,
719 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
720 .sampledImageDepthSampleCounts
= sample_counts
,
721 .sampledImageStencilSampleCounts
= sample_counts
,
722 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
723 .maxSampleMaskWords
= 1,
724 .timestampComputeAndGraphics
= true,
725 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
726 .maxClipDistances
= 8,
727 .maxCullDistances
= 8,
728 .maxCombinedClipAndCullDistances
= 8,
729 .discreteQueuePriorities
= 1,
730 .pointSizeRange
= { 0.125, 255.875 },
731 .lineWidthRange
= { 0.0, 7.9921875 },
732 .pointSizeGranularity
= (1.0 / 8.0),
733 .lineWidthGranularity
= (1.0 / 128.0),
734 .strictLines
= false, /* FINISHME */
735 .standardSampleLocations
= true,
736 .optimalBufferCopyOffsetAlignment
= 128,
737 .optimalBufferCopyRowPitchAlignment
= 128,
738 .nonCoherentAtomSize
= 64,
741 *pProperties
= (VkPhysicalDeviceProperties
) {
742 .apiVersion
= radv_physical_device_api_version(pdevice
),
743 .driverVersion
= vk_get_driver_version(),
744 .vendorID
= ATI_VENDOR_ID
,
745 .deviceID
= pdevice
->rad_info
.pci_id
,
746 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
748 .sparseProperties
= {0},
751 strcpy(pProperties
->deviceName
, pdevice
->name
);
752 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
755 void radv_GetPhysicalDeviceProperties2KHR(
756 VkPhysicalDevice physicalDevice
,
757 VkPhysicalDeviceProperties2KHR
*pProperties
)
759 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
760 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
762 vk_foreach_struct(ext
, pProperties
->pNext
) {
763 switch (ext
->sType
) {
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
765 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
766 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
767 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR
: {
771 VkPhysicalDeviceIDPropertiesKHR
*properties
= (VkPhysicalDeviceIDPropertiesKHR
*)ext
;
772 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
773 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
774 properties
->deviceLUIDValid
= false;
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX
: {
778 VkPhysicalDeviceMultiviewPropertiesKHX
*properties
= (VkPhysicalDeviceMultiviewPropertiesKHX
*)ext
;
779 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
780 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR
: {
784 VkPhysicalDevicePointClippingPropertiesKHR
*properties
=
785 (VkPhysicalDevicePointClippingPropertiesKHR
*)ext
;
786 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR
;
795 static void radv_get_physical_device_queue_family_properties(
796 struct radv_physical_device
* pdevice
,
798 VkQueueFamilyProperties
** pQueueFamilyProperties
)
800 int num_queue_families
= 1;
802 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
803 pdevice
->rad_info
.chip_class
>= CIK
&&
804 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
805 num_queue_families
++;
807 if (pQueueFamilyProperties
== NULL
) {
808 *pCount
= num_queue_families
;
817 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
818 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
819 VK_QUEUE_COMPUTE_BIT
|
820 VK_QUEUE_TRANSFER_BIT
|
821 VK_QUEUE_SPARSE_BINDING_BIT
,
823 .timestampValidBits
= 64,
824 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
829 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
830 pdevice
->rad_info
.chip_class
>= CIK
&&
831 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
833 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
834 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
835 VK_QUEUE_TRANSFER_BIT
|
836 VK_QUEUE_SPARSE_BINDING_BIT
,
837 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
838 .timestampValidBits
= 64,
839 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
847 void radv_GetPhysicalDeviceQueueFamilyProperties(
848 VkPhysicalDevice physicalDevice
,
850 VkQueueFamilyProperties
* pQueueFamilyProperties
)
852 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
853 if (!pQueueFamilyProperties
) {
854 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
857 VkQueueFamilyProperties
*properties
[] = {
858 pQueueFamilyProperties
+ 0,
859 pQueueFamilyProperties
+ 1,
860 pQueueFamilyProperties
+ 2,
862 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
863 assert(*pCount
<= 3);
866 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
867 VkPhysicalDevice physicalDevice
,
869 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
871 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
872 if (!pQueueFamilyProperties
) {
873 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
876 VkQueueFamilyProperties
*properties
[] = {
877 &pQueueFamilyProperties
[0].queueFamilyProperties
,
878 &pQueueFamilyProperties
[1].queueFamilyProperties
,
879 &pQueueFamilyProperties
[2].queueFamilyProperties
,
881 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
882 assert(*pCount
<= 3);
885 void radv_GetPhysicalDeviceMemoryProperties(
886 VkPhysicalDevice physicalDevice
,
887 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
889 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
891 *pMemoryProperties
= physical_device
->memory_properties
;
894 void radv_GetPhysicalDeviceMemoryProperties2KHR(
895 VkPhysicalDevice physicalDevice
,
896 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
898 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
899 &pMemoryProperties
->memoryProperties
);
902 static enum radeon_ctx_priority
903 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
905 /* Default to MEDIUM when a specific global priority isn't requested */
907 return RADEON_CTX_PRIORITY_MEDIUM
;
909 switch(pObj
->globalPriority
) {
910 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
911 return RADEON_CTX_PRIORITY_REALTIME
;
912 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
913 return RADEON_CTX_PRIORITY_HIGH
;
914 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
915 return RADEON_CTX_PRIORITY_MEDIUM
;
916 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
917 return RADEON_CTX_PRIORITY_LOW
;
919 unreachable("Illegal global priority value");
920 return RADEON_CTX_PRIORITY_INVALID
;
925 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
926 uint32_t queue_family_index
, int idx
,
927 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
929 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
930 queue
->device
= device
;
931 queue
->queue_family_index
= queue_family_index
;
932 queue
->queue_idx
= idx
;
933 queue
->priority
= radv_get_queue_global_priority(global_priority
);
935 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
937 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
943 radv_queue_finish(struct radv_queue
*queue
)
946 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
948 if (queue
->initial_full_flush_preamble_cs
)
949 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
950 if (queue
->initial_preamble_cs
)
951 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
952 if (queue
->continue_preamble_cs
)
953 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
954 if (queue
->descriptor_bo
)
955 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
956 if (queue
->scratch_bo
)
957 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
958 if (queue
->esgs_ring_bo
)
959 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
960 if (queue
->gsvs_ring_bo
)
961 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
962 if (queue
->tess_factor_ring_bo
)
963 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
964 if (queue
->tess_offchip_ring_bo
)
965 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
966 if (queue
->compute_scratch_bo
)
967 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
971 radv_device_init_gs_info(struct radv_device
*device
)
973 switch (device
->physical_device
->rad_info
.family
) {
982 device
->gs_table_depth
= 16;
996 device
->gs_table_depth
= 32;
999 unreachable("unknown GPU");
1003 VkResult
radv_CreateDevice(
1004 VkPhysicalDevice physicalDevice
,
1005 const VkDeviceCreateInfo
* pCreateInfo
,
1006 const VkAllocationCallbacks
* pAllocator
,
1009 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1011 struct radv_device
*device
;
1013 bool keep_shader_info
= false;
1015 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1016 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1017 if (!radv_physical_device_extension_supported(physical_device
, ext_name
))
1018 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
1020 if (strcmp(ext_name
, VK_AMD_SHADER_INFO_EXTENSION_NAME
) == 0)
1021 keep_shader_info
= true;
1024 /* Check enabled features */
1025 if (pCreateInfo
->pEnabledFeatures
) {
1026 VkPhysicalDeviceFeatures supported_features
;
1027 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1028 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1029 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1030 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1031 for (uint32_t i
= 0; i
< num_features
; i
++) {
1032 if (enabled_feature
[i
] && !supported_feature
[i
])
1033 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
1037 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1039 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1041 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1043 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1044 device
->instance
= physical_device
->instance
;
1045 device
->physical_device
= physical_device
;
1047 device
->ws
= physical_device
->ws
;
1049 device
->alloc
= *pAllocator
;
1051 device
->alloc
= physical_device
->instance
->alloc
;
1053 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1054 list_inithead(&device
->shader_slabs
);
1056 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1057 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1058 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1059 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1060 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1062 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1064 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1065 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1066 if (!device
->queues
[qfi
]) {
1067 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1071 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1073 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1075 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1076 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
, global_priority
);
1077 if (result
!= VK_SUCCESS
)
1082 #if HAVE_LLVM < 0x0400
1083 device
->llvm_supports_spill
= false;
1085 device
->llvm_supports_spill
= true;
1088 /* The maximum number of scratch waves. Scratch space isn't divided
1089 * evenly between CUs. The number is only a function of the number of CUs.
1090 * We can decrease the constant to decrease the scratch buffer size.
1092 * sctx->scratch_waves must be >= the maximum posible size of
1093 * 1 threadgroup, so that the hw doesn't hang from being unable
1096 * The recommended value is 4 per CU at most. Higher numbers don't
1097 * bring much benefit, but they still occupy chip resources (think
1098 * async compute). I've seen ~2% performance difference between 4 and 32.
1100 uint32_t max_threads_per_block
= 2048;
1101 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1102 max_threads_per_block
/ 64);
1104 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
1105 S_00B800_FORCE_START_AT_000(1);
1107 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1108 /* If the KMD allows it (there is a KMD hw register for it),
1109 * allow launching waves out-of-order.
1111 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1114 radv_device_init_gs_info(device
);
1116 device
->tess_offchip_block_dw_size
=
1117 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1118 device
->has_distributed_tess
=
1119 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1120 device
->physical_device
->rad_info
.max_se
>= 2;
1122 if (getenv("RADV_TRACE_FILE")) {
1123 keep_shader_info
= true;
1125 if (!radv_init_trace(device
))
1129 device
->keep_shader_info
= keep_shader_info
;
1131 result
= radv_device_init_meta(device
);
1132 if (result
!= VK_SUCCESS
)
1135 radv_device_init_msaa(device
);
1137 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1138 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1140 case RADV_QUEUE_GENERAL
:
1141 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1142 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1143 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1145 case RADV_QUEUE_COMPUTE
:
1146 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1147 radeon_emit(device
->empty_cs
[family
], 0);
1150 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1153 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1154 cik_create_gfx_config(device
);
1156 VkPipelineCacheCreateInfo ci
;
1157 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1160 ci
.pInitialData
= NULL
;
1161 ci
.initialDataSize
= 0;
1163 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1165 if (result
!= VK_SUCCESS
)
1168 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1170 *pDevice
= radv_device_to_handle(device
);
1174 if (device
->trace_bo
)
1175 device
->ws
->buffer_destroy(device
->trace_bo
);
1177 if (device
->gfx_init
)
1178 device
->ws
->buffer_destroy(device
->gfx_init
);
1180 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1181 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1182 radv_queue_finish(&device
->queues
[i
][q
]);
1183 if (device
->queue_count
[i
])
1184 vk_free(&device
->alloc
, device
->queues
[i
]);
1187 vk_free(&device
->alloc
, device
);
1191 void radv_DestroyDevice(
1193 const VkAllocationCallbacks
* pAllocator
)
1195 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1200 if (device
->trace_bo
)
1201 device
->ws
->buffer_destroy(device
->trace_bo
);
1203 if (device
->gfx_init
)
1204 device
->ws
->buffer_destroy(device
->gfx_init
);
1206 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1207 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1208 radv_queue_finish(&device
->queues
[i
][q
]);
1209 if (device
->queue_count
[i
])
1210 vk_free(&device
->alloc
, device
->queues
[i
]);
1211 if (device
->empty_cs
[i
])
1212 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1214 radv_device_finish_meta(device
);
1216 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1217 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1219 radv_destroy_shader_slabs(device
);
1221 vk_free(&device
->alloc
, device
);
1224 VkResult
radv_EnumerateInstanceLayerProperties(
1225 uint32_t* pPropertyCount
,
1226 VkLayerProperties
* pProperties
)
1228 if (pProperties
== NULL
) {
1229 *pPropertyCount
= 0;
1233 /* None supported at this time */
1234 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1237 VkResult
radv_EnumerateDeviceLayerProperties(
1238 VkPhysicalDevice physicalDevice
,
1239 uint32_t* pPropertyCount
,
1240 VkLayerProperties
* pProperties
)
1242 if (pProperties
== NULL
) {
1243 *pPropertyCount
= 0;
1247 /* None supported at this time */
1248 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1251 void radv_GetDeviceQueue(
1253 uint32_t queueFamilyIndex
,
1254 uint32_t queueIndex
,
1257 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1259 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1263 fill_geom_tess_rings(struct radv_queue
*queue
,
1265 bool add_sample_positions
,
1266 uint32_t esgs_ring_size
,
1267 struct radeon_winsys_bo
*esgs_ring_bo
,
1268 uint32_t gsvs_ring_size
,
1269 struct radeon_winsys_bo
*gsvs_ring_bo
,
1270 uint32_t tess_factor_ring_size
,
1271 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1272 uint32_t tess_offchip_ring_size
,
1273 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1275 uint64_t esgs_va
= 0, gsvs_va
= 0;
1276 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1277 uint32_t *desc
= &map
[4];
1280 esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
1282 gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
1283 if (tess_factor_ring_bo
)
1284 tess_factor_va
= radv_buffer_get_va(tess_factor_ring_bo
);
1285 if (tess_offchip_ring_bo
)
1286 tess_offchip_va
= radv_buffer_get_va(tess_offchip_ring_bo
);
1288 /* stride 0, num records - size, add tid, swizzle, elsize4,
1291 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1292 S_008F04_STRIDE(0) |
1293 S_008F04_SWIZZLE_ENABLE(true);
1294 desc
[2] = esgs_ring_size
;
1295 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1296 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1297 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1298 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1299 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1300 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1301 S_008F0C_ELEMENT_SIZE(1) |
1302 S_008F0C_INDEX_STRIDE(3) |
1303 S_008F0C_ADD_TID_ENABLE(true);
1306 /* GS entry for ES->GS ring */
1307 /* stride 0, num records - size, elsize0,
1310 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1311 S_008F04_STRIDE(0) |
1312 S_008F04_SWIZZLE_ENABLE(false);
1313 desc
[2] = esgs_ring_size
;
1314 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1315 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1316 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1317 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1318 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1319 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1320 S_008F0C_ELEMENT_SIZE(0) |
1321 S_008F0C_INDEX_STRIDE(0) |
1322 S_008F0C_ADD_TID_ENABLE(false);
1325 /* VS entry for GS->VS ring */
1326 /* stride 0, num records - size, elsize0,
1329 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1330 S_008F04_STRIDE(0) |
1331 S_008F04_SWIZZLE_ENABLE(false);
1332 desc
[2] = gsvs_ring_size
;
1333 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1334 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1335 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1336 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1337 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1338 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1339 S_008F0C_ELEMENT_SIZE(0) |
1340 S_008F0C_INDEX_STRIDE(0) |
1341 S_008F0C_ADD_TID_ENABLE(false);
1344 /* stride gsvs_itemsize, num records 64
1345 elsize 4, index stride 16 */
1346 /* shader will patch stride and desc[2] */
1348 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1349 S_008F04_STRIDE(0) |
1350 S_008F04_SWIZZLE_ENABLE(true);
1352 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1353 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1354 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1355 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1356 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1357 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1358 S_008F0C_ELEMENT_SIZE(1) |
1359 S_008F0C_INDEX_STRIDE(1) |
1360 S_008F0C_ADD_TID_ENABLE(true);
1363 desc
[0] = tess_factor_va
;
1364 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1365 S_008F04_STRIDE(0) |
1366 S_008F04_SWIZZLE_ENABLE(false);
1367 desc
[2] = tess_factor_ring_size
;
1368 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1369 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1370 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1371 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1372 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1373 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1374 S_008F0C_ELEMENT_SIZE(0) |
1375 S_008F0C_INDEX_STRIDE(0) |
1376 S_008F0C_ADD_TID_ENABLE(false);
1379 desc
[0] = tess_offchip_va
;
1380 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1381 S_008F04_STRIDE(0) |
1382 S_008F04_SWIZZLE_ENABLE(false);
1383 desc
[2] = tess_offchip_ring_size
;
1384 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1385 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1386 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1387 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1388 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1389 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1390 S_008F0C_ELEMENT_SIZE(0) |
1391 S_008F0C_INDEX_STRIDE(0) |
1392 S_008F0C_ADD_TID_ENABLE(false);
1395 /* add sample positions after all rings */
1396 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1398 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1400 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1402 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1404 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1408 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1410 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1411 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1412 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1413 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1414 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1415 device
->physical_device
->rad_info
.max_se
;
1416 unsigned offchip_granularity
;
1417 unsigned hs_offchip_param
;
1418 switch (device
->tess_offchip_block_dw_size
) {
1423 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1426 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1430 switch (device
->physical_device
->rad_info
.chip_class
) {
1432 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1438 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1442 *max_offchip_buffers_p
= max_offchip_buffers
;
1443 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1444 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1445 --max_offchip_buffers
;
1447 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1448 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1451 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1453 return hs_offchip_param
;
1457 radv_get_preamble_cs(struct radv_queue
*queue
,
1458 uint32_t scratch_size
,
1459 uint32_t compute_scratch_size
,
1460 uint32_t esgs_ring_size
,
1461 uint32_t gsvs_ring_size
,
1462 bool needs_tess_rings
,
1463 bool needs_sample_positions
,
1464 struct radeon_winsys_cs
**initial_full_flush_preamble_cs
,
1465 struct radeon_winsys_cs
**initial_preamble_cs
,
1466 struct radeon_winsys_cs
**continue_preamble_cs
)
1468 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1469 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1470 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1471 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1472 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1473 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1474 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1475 struct radeon_winsys_cs
*dest_cs
[3] = {0};
1476 bool add_tess_rings
= false, add_sample_positions
= false;
1477 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1478 unsigned max_offchip_buffers
;
1479 unsigned hs_offchip_param
= 0;
1480 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1481 if (!queue
->has_tess_rings
) {
1482 if (needs_tess_rings
)
1483 add_tess_rings
= true;
1485 if (!queue
->has_sample_positions
) {
1486 if (needs_sample_positions
)
1487 add_sample_positions
= true;
1489 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1490 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1491 &max_offchip_buffers
);
1492 tess_offchip_ring_size
= max_offchip_buffers
*
1493 queue
->device
->tess_offchip_block_dw_size
* 4;
1495 if (scratch_size
<= queue
->scratch_size
&&
1496 compute_scratch_size
<= queue
->compute_scratch_size
&&
1497 esgs_ring_size
<= queue
->esgs_ring_size
&&
1498 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1499 !add_tess_rings
&& !add_sample_positions
&&
1500 queue
->initial_preamble_cs
) {
1501 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
1502 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1503 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1504 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1505 *continue_preamble_cs
= NULL
;
1509 if (scratch_size
> queue
->scratch_size
) {
1510 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1518 scratch_bo
= queue
->scratch_bo
;
1520 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1521 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1522 compute_scratch_size
,
1526 if (!compute_scratch_bo
)
1530 compute_scratch_bo
= queue
->compute_scratch_bo
;
1532 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1533 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1541 esgs_ring_bo
= queue
->esgs_ring_bo
;
1542 esgs_ring_size
= queue
->esgs_ring_size
;
1545 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1546 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1554 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1555 gsvs_ring_size
= queue
->gsvs_ring_size
;
1558 if (add_tess_rings
) {
1559 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1560 tess_factor_ring_size
,
1564 if (!tess_factor_ring_bo
)
1566 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1567 tess_offchip_ring_size
,
1571 if (!tess_offchip_ring_bo
)
1574 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1575 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1578 if (scratch_bo
!= queue
->scratch_bo
||
1579 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1580 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1581 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1582 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1584 if (gsvs_ring_bo
|| esgs_ring_bo
||
1585 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1586 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1587 if (add_sample_positions
)
1588 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1590 else if (scratch_bo
)
1591 size
= 8; /* 2 dword */
1593 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1597 RADEON_FLAG_CPU_ACCESS
|RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1601 descriptor_bo
= queue
->descriptor_bo
;
1603 for(int i
= 0; i
< 3; ++i
) {
1604 struct radeon_winsys_cs
*cs
= NULL
;
1605 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1606 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1613 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
, 8);
1616 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
, 8);
1619 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
, 8);
1621 if (tess_factor_ring_bo
)
1622 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_factor_ring_bo
, 8);
1624 if (tess_offchip_ring_bo
)
1625 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_offchip_ring_bo
, 8);
1628 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
, 8);
1630 if (descriptor_bo
!= queue
->descriptor_bo
) {
1631 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1634 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
1635 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1636 S_008F04_SWIZZLE_ENABLE(1);
1637 map
[0] = scratch_va
;
1641 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1642 add_sample_positions
)
1643 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1644 esgs_ring_size
, esgs_ring_bo
,
1645 gsvs_ring_size
, gsvs_ring_bo
,
1646 tess_factor_ring_size
, tess_factor_ring_bo
,
1647 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1649 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1652 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1653 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1654 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1655 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1656 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1659 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1660 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1661 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1662 radeon_emit(cs
, esgs_ring_size
>> 8);
1663 radeon_emit(cs
, gsvs_ring_size
>> 8);
1665 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1666 radeon_emit(cs
, esgs_ring_size
>> 8);
1667 radeon_emit(cs
, gsvs_ring_size
>> 8);
1671 if (tess_factor_ring_bo
) {
1672 uint64_t tf_va
= radv_buffer_get_va(tess_factor_ring_bo
);
1673 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1674 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1675 S_030938_SIZE(tess_factor_ring_size
/ 4));
1676 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1678 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1679 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
1682 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1684 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1685 S_008988_SIZE(tess_factor_ring_size
/ 4));
1686 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1688 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1693 if (descriptor_bo
) {
1694 uint64_t va
= radv_buffer_get_va(descriptor_bo
);
1695 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1696 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1697 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1698 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
1699 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
1701 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1702 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1703 radeon_emit(cs
, va
);
1704 radeon_emit(cs
, va
>> 32);
1707 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1708 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1709 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1710 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1711 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1712 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1714 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1715 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1716 radeon_emit(cs
, va
);
1717 radeon_emit(cs
, va
>> 32);
1722 if (compute_scratch_bo
) {
1723 uint64_t scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
1724 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1725 S_008F04_SWIZZLE_ENABLE(1);
1727 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
, 8);
1729 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1730 radeon_emit(cs
, scratch_va
);
1731 radeon_emit(cs
, rsrc1
);
1735 si_cs_emit_cache_flush(cs
,
1737 queue
->device
->physical_device
->rad_info
.chip_class
,
1739 queue
->queue_family_index
== RING_COMPUTE
&&
1740 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1741 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
1742 RADV_CMD_FLAG_INV_ICACHE
|
1743 RADV_CMD_FLAG_INV_SMEM_L1
|
1744 RADV_CMD_FLAG_INV_VMEM_L1
|
1745 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1746 } else if (i
== 1) {
1747 si_cs_emit_cache_flush(cs
,
1749 queue
->device
->physical_device
->rad_info
.chip_class
,
1751 queue
->queue_family_index
== RING_COMPUTE
&&
1752 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1753 RADV_CMD_FLAG_INV_ICACHE
|
1754 RADV_CMD_FLAG_INV_SMEM_L1
|
1755 RADV_CMD_FLAG_INV_VMEM_L1
|
1756 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1759 if (!queue
->device
->ws
->cs_finalize(cs
))
1763 if (queue
->initial_full_flush_preamble_cs
)
1764 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1766 if (queue
->initial_preamble_cs
)
1767 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1769 if (queue
->continue_preamble_cs
)
1770 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1772 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
1773 queue
->initial_preamble_cs
= dest_cs
[1];
1774 queue
->continue_preamble_cs
= dest_cs
[2];
1776 if (scratch_bo
!= queue
->scratch_bo
) {
1777 if (queue
->scratch_bo
)
1778 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1779 queue
->scratch_bo
= scratch_bo
;
1780 queue
->scratch_size
= scratch_size
;
1783 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1784 if (queue
->compute_scratch_bo
)
1785 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1786 queue
->compute_scratch_bo
= compute_scratch_bo
;
1787 queue
->compute_scratch_size
= compute_scratch_size
;
1790 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1791 if (queue
->esgs_ring_bo
)
1792 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1793 queue
->esgs_ring_bo
= esgs_ring_bo
;
1794 queue
->esgs_ring_size
= esgs_ring_size
;
1797 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1798 if (queue
->gsvs_ring_bo
)
1799 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1800 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1801 queue
->gsvs_ring_size
= gsvs_ring_size
;
1804 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1805 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1808 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1809 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1810 queue
->has_tess_rings
= true;
1813 if (descriptor_bo
!= queue
->descriptor_bo
) {
1814 if (queue
->descriptor_bo
)
1815 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1817 queue
->descriptor_bo
= descriptor_bo
;
1820 if (add_sample_positions
)
1821 queue
->has_sample_positions
= true;
1823 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
1824 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1825 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1826 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1827 *continue_preamble_cs
= NULL
;
1830 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1832 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1833 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1834 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1835 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1836 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1837 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1838 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1839 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1840 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1841 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1842 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1843 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1844 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1845 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1846 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1847 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1850 static VkResult
radv_alloc_sem_counts(struct radv_winsys_sem_counts
*counts
,
1852 const VkSemaphore
*sems
,
1856 int syncobj_idx
= 0, sem_idx
= 0;
1858 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
1861 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1862 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1864 if (sem
->temp_syncobj
|| sem
->syncobj
)
1865 counts
->syncobj_count
++;
1867 counts
->sem_count
++;
1870 if (_fence
!= VK_NULL_HANDLE
) {
1871 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1872 if (fence
->temp_syncobj
|| fence
->syncobj
)
1873 counts
->syncobj_count
++;
1876 if (counts
->syncobj_count
) {
1877 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
1878 if (!counts
->syncobj
)
1879 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1882 if (counts
->sem_count
) {
1883 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
1885 free(counts
->syncobj
);
1886 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
1890 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1891 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1893 if (sem
->temp_syncobj
) {
1894 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
1896 else if (sem
->syncobj
)
1897 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
1900 counts
->sem
[sem_idx
++] = sem
->sem
;
1904 if (_fence
!= VK_NULL_HANDLE
) {
1905 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1906 if (fence
->temp_syncobj
)
1907 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
1908 else if (fence
->syncobj
)
1909 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
1915 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
1917 free(sem_info
->wait
.syncobj
);
1918 free(sem_info
->wait
.sem
);
1919 free(sem_info
->signal
.syncobj
);
1920 free(sem_info
->signal
.sem
);
1924 static void radv_free_temp_syncobjs(struct radv_device
*device
,
1926 const VkSemaphore
*sems
)
1928 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1929 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1931 if (sem
->temp_syncobj
) {
1932 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
1933 sem
->temp_syncobj
= 0;
1938 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1940 const VkSemaphore
*wait_sems
,
1941 int num_signal_sems
,
1942 const VkSemaphore
*signal_sems
,
1946 memset(sem_info
, 0, sizeof(*sem_info
));
1948 ret
= radv_alloc_sem_counts(&sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
1951 ret
= radv_alloc_sem_counts(&sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
1953 radv_free_sem_info(sem_info
);
1955 /* caller can override these */
1956 sem_info
->cs_emit_wait
= true;
1957 sem_info
->cs_emit_signal
= true;
1961 VkResult
radv_QueueSubmit(
1963 uint32_t submitCount
,
1964 const VkSubmitInfo
* pSubmits
,
1967 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1968 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1969 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1970 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1972 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1973 uint32_t scratch_size
= 0;
1974 uint32_t compute_scratch_size
= 0;
1975 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1976 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1978 bool fence_emitted
= false;
1979 bool tess_rings_needed
= false;
1980 bool sample_positions_needed
= false;
1982 /* Do this first so failing to allocate scratch buffers can't result in
1983 * partially executed submissions. */
1984 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1985 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1986 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1987 pSubmits
[i
].pCommandBuffers
[j
]);
1989 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1990 compute_scratch_size
= MAX2(compute_scratch_size
,
1991 cmd_buffer
->compute_scratch_size_needed
);
1992 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1993 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1994 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1995 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1999 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2000 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2001 sample_positions_needed
, &initial_flush_preamble_cs
,
2002 &initial_preamble_cs
, &continue_preamble_cs
);
2003 if (result
!= VK_SUCCESS
)
2006 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2007 struct radeon_winsys_cs
**cs_array
;
2008 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2009 bool can_patch
= true;
2011 struct radv_winsys_sem_info sem_info
;
2013 result
= radv_alloc_sem_info(&sem_info
,
2014 pSubmits
[i
].waitSemaphoreCount
,
2015 pSubmits
[i
].pWaitSemaphores
,
2016 pSubmits
[i
].signalSemaphoreCount
,
2017 pSubmits
[i
].pSignalSemaphores
,
2019 if (result
!= VK_SUCCESS
)
2022 if (!pSubmits
[i
].commandBufferCount
) {
2023 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2024 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2025 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2030 radv_loge("failed to submit CS %d\n", i
);
2033 fence_emitted
= true;
2035 radv_free_sem_info(&sem_info
);
2039 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
2040 (pSubmits
[i
].commandBufferCount
));
2042 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2043 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2044 pSubmits
[i
].pCommandBuffers
[j
]);
2045 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2047 cs_array
[j
] = cmd_buffer
->cs
;
2048 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
2051 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
2054 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
2055 struct radeon_winsys_cs
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
2056 advance
= MIN2(max_cs_submission
,
2057 pSubmits
[i
].commandBufferCount
- j
);
2059 if (queue
->device
->trace_bo
)
2060 *queue
->device
->trace_id_ptr
= 0;
2062 sem_info
.cs_emit_wait
= j
== 0;
2063 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
2065 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
2066 advance
, initial_preamble
, continue_preamble_cs
,
2068 can_patch
, base_fence
);
2071 radv_loge("failed to submit CS %d\n", i
);
2074 fence_emitted
= true;
2075 if (queue
->device
->trace_bo
) {
2076 radv_check_gpu_hangs(queue
, cs_array
[j
]);
2080 radv_free_temp_syncobjs(queue
->device
,
2081 pSubmits
[i
].waitSemaphoreCount
,
2082 pSubmits
[i
].pWaitSemaphores
);
2083 radv_free_sem_info(&sem_info
);
2088 if (!fence_emitted
) {
2089 struct radv_winsys_sem_info sem_info
;
2091 result
= radv_alloc_sem_info(&sem_info
, 0, NULL
, 0, NULL
,
2093 if (result
!= VK_SUCCESS
)
2096 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2097 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2098 1, NULL
, NULL
, &sem_info
,
2100 radv_free_sem_info(&sem_info
);
2102 fence
->submitted
= true;
2108 VkResult
radv_QueueWaitIdle(
2111 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2113 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2114 radv_queue_family_to_ring(queue
->queue_family_index
),
2119 VkResult
radv_DeviceWaitIdle(
2122 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2124 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2125 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2126 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2132 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2133 VkInstance instance
,
2136 return radv_lookup_entrypoint(pName
);
2139 /* The loader wants us to expose a second GetInstanceProcAddr function
2140 * to work around certain LD_PRELOAD issues seen in apps.
2143 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2144 VkInstance instance
,
2148 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2149 VkInstance instance
,
2152 return radv_GetInstanceProcAddr(instance
, pName
);
2155 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2159 return radv_lookup_entrypoint(pName
);
2162 bool radv_get_memory_fd(struct radv_device
*device
,
2163 struct radv_device_memory
*memory
,
2166 struct radeon_bo_metadata metadata
;
2168 if (memory
->image
) {
2169 radv_init_metadata(device
, memory
->image
, &metadata
);
2170 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2173 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2177 static VkResult
radv_alloc_memory(struct radv_device
*device
,
2178 const VkMemoryAllocateInfo
* pAllocateInfo
,
2179 const VkAllocationCallbacks
* pAllocator
,
2180 VkDeviceMemory
* pMem
)
2182 struct radv_device_memory
*mem
;
2184 enum radeon_bo_domain domain
;
2186 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
2188 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2190 if (pAllocateInfo
->allocationSize
== 0) {
2191 /* Apparently, this is allowed */
2192 *pMem
= VK_NULL_HANDLE
;
2196 const VkImportMemoryFdInfoKHR
*import_info
=
2197 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
2198 const VkMemoryDedicatedAllocateInfoKHR
*dedicate_info
=
2199 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO_KHR
);
2200 const VkExportMemoryAllocateInfoKHR
*export_info
=
2201 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO_KHR
);
2203 const struct wsi_memory_allocate_info
*wsi_info
=
2204 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
2206 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2207 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2209 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2211 if (wsi_info
&& wsi_info
->implicit_sync
)
2212 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
2214 if (dedicate_info
) {
2215 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2216 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2223 assert(import_info
->handleType
==
2224 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
||
2225 import_info
->handleType
==
2226 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
2227 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2230 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
2233 close(import_info
->fd
);
2238 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2239 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2240 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
2241 domain
= RADEON_DOMAIN_GTT
;
2243 domain
= RADEON_DOMAIN_VRAM
;
2245 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
2246 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2248 flags
|= RADEON_FLAG_CPU_ACCESS
;
2250 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2251 flags
|= RADEON_FLAG_GTT_WC
;
2253 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
))
2254 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2256 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
2260 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2263 mem
->type_index
= mem_type_index
;
2265 *pMem
= radv_device_memory_to_handle(mem
);
2270 vk_free2(&device
->alloc
, pAllocator
, mem
);
2275 VkResult
radv_AllocateMemory(
2277 const VkMemoryAllocateInfo
* pAllocateInfo
,
2278 const VkAllocationCallbacks
* pAllocator
,
2279 VkDeviceMemory
* pMem
)
2281 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2282 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
2285 void radv_FreeMemory(
2287 VkDeviceMemory _mem
,
2288 const VkAllocationCallbacks
* pAllocator
)
2290 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2291 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2296 device
->ws
->buffer_destroy(mem
->bo
);
2299 vk_free2(&device
->alloc
, pAllocator
, mem
);
2302 VkResult
radv_MapMemory(
2304 VkDeviceMemory _memory
,
2305 VkDeviceSize offset
,
2307 VkMemoryMapFlags flags
,
2310 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2311 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2318 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2324 return vk_error(VK_ERROR_MEMORY_MAP_FAILED
);
2327 void radv_UnmapMemory(
2329 VkDeviceMemory _memory
)
2331 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2332 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2337 device
->ws
->buffer_unmap(mem
->bo
);
2340 VkResult
radv_FlushMappedMemoryRanges(
2342 uint32_t memoryRangeCount
,
2343 const VkMappedMemoryRange
* pMemoryRanges
)
2348 VkResult
radv_InvalidateMappedMemoryRanges(
2350 uint32_t memoryRangeCount
,
2351 const VkMappedMemoryRange
* pMemoryRanges
)
2356 void radv_GetBufferMemoryRequirements(
2359 VkMemoryRequirements
* pMemoryRequirements
)
2361 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2362 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2364 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
2366 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2367 pMemoryRequirements
->alignment
= 4096;
2369 pMemoryRequirements
->alignment
= 16;
2371 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2374 void radv_GetBufferMemoryRequirements2KHR(
2376 const VkBufferMemoryRequirementsInfo2KHR
* pInfo
,
2377 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2379 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
2380 &pMemoryRequirements
->memoryRequirements
);
2381 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
2382 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2383 switch (ext
->sType
) {
2384 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2385 VkMemoryDedicatedRequirementsKHR
*req
=
2386 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2387 req
->requiresDedicatedAllocation
= buffer
->shareable
;
2388 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2397 void radv_GetImageMemoryRequirements(
2400 VkMemoryRequirements
* pMemoryRequirements
)
2402 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2403 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2405 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
2407 pMemoryRequirements
->size
= image
->size
;
2408 pMemoryRequirements
->alignment
= image
->alignment
;
2411 void radv_GetImageMemoryRequirements2KHR(
2413 const VkImageMemoryRequirementsInfo2KHR
* pInfo
,
2414 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2416 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
2417 &pMemoryRequirements
->memoryRequirements
);
2419 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
2421 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2422 switch (ext
->sType
) {
2423 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2424 VkMemoryDedicatedRequirementsKHR
*req
=
2425 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2426 req
->requiresDedicatedAllocation
= image
->shareable
;
2427 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2436 void radv_GetImageSparseMemoryRequirements(
2439 uint32_t* pSparseMemoryRequirementCount
,
2440 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2445 void radv_GetImageSparseMemoryRequirements2KHR(
2447 const VkImageSparseMemoryRequirementsInfo2KHR
* pInfo
,
2448 uint32_t* pSparseMemoryRequirementCount
,
2449 VkSparseImageMemoryRequirements2KHR
* pSparseMemoryRequirements
)
2454 void radv_GetDeviceMemoryCommitment(
2456 VkDeviceMemory memory
,
2457 VkDeviceSize
* pCommittedMemoryInBytes
)
2459 *pCommittedMemoryInBytes
= 0;
2462 VkResult
radv_BindBufferMemory2KHR(VkDevice device
,
2463 uint32_t bindInfoCount
,
2464 const VkBindBufferMemoryInfoKHR
*pBindInfos
)
2466 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2467 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
2468 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
2471 buffer
->bo
= mem
->bo
;
2472 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
2480 VkResult
radv_BindBufferMemory(
2483 VkDeviceMemory memory
,
2484 VkDeviceSize memoryOffset
)
2486 const VkBindBufferMemoryInfoKHR info
= {
2487 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
2490 .memoryOffset
= memoryOffset
2493 return radv_BindBufferMemory2KHR(device
, 1, &info
);
2496 VkResult
radv_BindImageMemory2KHR(VkDevice device
,
2497 uint32_t bindInfoCount
,
2498 const VkBindImageMemoryInfoKHR
*pBindInfos
)
2500 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2501 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
2502 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
2505 image
->bo
= mem
->bo
;
2506 image
->offset
= pBindInfos
[i
].memoryOffset
;
2516 VkResult
radv_BindImageMemory(
2519 VkDeviceMemory memory
,
2520 VkDeviceSize memoryOffset
)
2522 const VkBindImageMemoryInfoKHR info
= {
2523 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
2526 .memoryOffset
= memoryOffset
2529 return radv_BindImageMemory2KHR(device
, 1, &info
);
2534 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2535 const VkSparseBufferMemoryBindInfo
*bind
)
2537 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2539 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2540 struct radv_device_memory
*mem
= NULL
;
2542 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2543 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2545 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2546 bind
->pBinds
[i
].resourceOffset
,
2547 bind
->pBinds
[i
].size
,
2548 mem
? mem
->bo
: NULL
,
2549 bind
->pBinds
[i
].memoryOffset
);
2554 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2555 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2557 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2559 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2560 struct radv_device_memory
*mem
= NULL
;
2562 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2563 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2565 device
->ws
->buffer_virtual_bind(image
->bo
,
2566 bind
->pBinds
[i
].resourceOffset
,
2567 bind
->pBinds
[i
].size
,
2568 mem
? mem
->bo
: NULL
,
2569 bind
->pBinds
[i
].memoryOffset
);
2573 VkResult
radv_QueueBindSparse(
2575 uint32_t bindInfoCount
,
2576 const VkBindSparseInfo
* pBindInfo
,
2579 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2580 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2581 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2582 bool fence_emitted
= false;
2584 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2585 struct radv_winsys_sem_info sem_info
;
2586 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2587 radv_sparse_buffer_bind_memory(queue
->device
,
2588 pBindInfo
[i
].pBufferBinds
+ j
);
2591 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2592 radv_sparse_image_opaque_bind_memory(queue
->device
,
2593 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2597 result
= radv_alloc_sem_info(&sem_info
,
2598 pBindInfo
[i
].waitSemaphoreCount
,
2599 pBindInfo
[i
].pWaitSemaphores
,
2600 pBindInfo
[i
].signalSemaphoreCount
,
2601 pBindInfo
[i
].pSignalSemaphores
,
2603 if (result
!= VK_SUCCESS
)
2606 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2607 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2608 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2612 fence_emitted
= true;
2614 fence
->submitted
= true;
2617 radv_free_sem_info(&sem_info
);
2621 if (fence
&& !fence_emitted
) {
2622 fence
->signalled
= true;
2628 VkResult
radv_CreateFence(
2630 const VkFenceCreateInfo
* pCreateInfo
,
2631 const VkAllocationCallbacks
* pAllocator
,
2634 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2635 const VkExportFenceCreateInfoKHR
*export
=
2636 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO_KHR
);
2637 VkExternalFenceHandleTypeFlagsKHR handleTypes
=
2638 export
? export
->handleTypes
: 0;
2640 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2642 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2645 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2647 fence
->submitted
= false;
2648 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2649 fence
->temp_syncobj
= 0;
2651 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
2653 vk_free2(&device
->alloc
, pAllocator
, fence
);
2654 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2656 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
2657 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
2659 fence
->fence
= NULL
;
2661 fence
->fence
= device
->ws
->create_fence();
2662 if (!fence
->fence
) {
2663 vk_free2(&device
->alloc
, pAllocator
, fence
);
2664 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2669 *pFence
= radv_fence_to_handle(fence
);
2674 void radv_DestroyFence(
2677 const VkAllocationCallbacks
* pAllocator
)
2679 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2680 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2685 if (fence
->temp_syncobj
)
2686 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
2688 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
2690 device
->ws
->destroy_fence(fence
->fence
);
2691 vk_free2(&device
->alloc
, pAllocator
, fence
);
2694 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2696 uint64_t current_time
;
2699 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2700 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2702 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2704 return current_time
+ timeout
;
2707 VkResult
radv_WaitForFences(
2709 uint32_t fenceCount
,
2710 const VkFence
* pFences
,
2714 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2715 timeout
= radv_get_absolute_timeout(timeout
);
2717 if (!waitAll
&& fenceCount
> 1) {
2718 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2721 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2722 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2723 bool expired
= false;
2725 if (fence
->temp_syncobj
) {
2726 if (!device
->ws
->wait_syncobj(device
->ws
, fence
->temp_syncobj
, timeout
))
2731 if (fence
->syncobj
) {
2732 if (!device
->ws
->wait_syncobj(device
->ws
, fence
->syncobj
, timeout
))
2737 if (fence
->signalled
)
2740 if (!fence
->submitted
)
2743 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2747 fence
->signalled
= true;
2753 VkResult
radv_ResetFences(VkDevice _device
,
2754 uint32_t fenceCount
,
2755 const VkFence
*pFences
)
2757 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2759 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2760 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2761 fence
->submitted
= fence
->signalled
= false;
2763 /* Per spec, we first restore the permanent payload, and then reset, so
2764 * having a temp syncobj should not skip resetting the permanent syncobj. */
2765 if (fence
->temp_syncobj
) {
2766 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
2767 fence
->temp_syncobj
= 0;
2770 if (fence
->syncobj
) {
2771 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
2778 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2780 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2781 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2783 if (fence
->temp_syncobj
) {
2784 bool success
= device
->ws
->wait_syncobj(device
->ws
, fence
->temp_syncobj
, 0);
2785 return success
? VK_SUCCESS
: VK_NOT_READY
;
2788 if (fence
->syncobj
) {
2789 bool success
= device
->ws
->wait_syncobj(device
->ws
, fence
->syncobj
, 0);
2790 return success
? VK_SUCCESS
: VK_NOT_READY
;
2793 if (fence
->signalled
)
2795 if (!fence
->submitted
)
2796 return VK_NOT_READY
;
2797 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2798 return VK_NOT_READY
;
2804 // Queue semaphore functions
2806 VkResult
radv_CreateSemaphore(
2808 const VkSemaphoreCreateInfo
* pCreateInfo
,
2809 const VkAllocationCallbacks
* pAllocator
,
2810 VkSemaphore
* pSemaphore
)
2812 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2813 const VkExportSemaphoreCreateInfoKHR
*export
=
2814 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO_KHR
);
2815 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes
=
2816 export
? export
->handleTypes
: 0;
2818 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
2820 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2822 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2824 sem
->temp_syncobj
= 0;
2825 /* create a syncobject if we are going to export this semaphore */
2827 assert (device
->physical_device
->rad_info
.has_syncobj
);
2828 assert (handleTypes
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2829 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
2831 vk_free2(&device
->alloc
, pAllocator
, sem
);
2832 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2836 sem
->sem
= device
->ws
->create_sem(device
->ws
);
2838 vk_free2(&device
->alloc
, pAllocator
, sem
);
2839 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2844 *pSemaphore
= radv_semaphore_to_handle(sem
);
2848 void radv_DestroySemaphore(
2850 VkSemaphore _semaphore
,
2851 const VkAllocationCallbacks
* pAllocator
)
2853 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2854 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
2859 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
2861 device
->ws
->destroy_sem(sem
->sem
);
2862 vk_free2(&device
->alloc
, pAllocator
, sem
);
2865 VkResult
radv_CreateEvent(
2867 const VkEventCreateInfo
* pCreateInfo
,
2868 const VkAllocationCallbacks
* pAllocator
,
2871 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2872 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2874 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2877 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2879 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2881 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
);
2883 vk_free2(&device
->alloc
, pAllocator
, event
);
2884 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2887 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2889 *pEvent
= radv_event_to_handle(event
);
2894 void radv_DestroyEvent(
2897 const VkAllocationCallbacks
* pAllocator
)
2899 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2900 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2904 device
->ws
->buffer_destroy(event
->bo
);
2905 vk_free2(&device
->alloc
, pAllocator
, event
);
2908 VkResult
radv_GetEventStatus(
2912 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2914 if (*event
->map
== 1)
2915 return VK_EVENT_SET
;
2916 return VK_EVENT_RESET
;
2919 VkResult
radv_SetEvent(
2923 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2929 VkResult
radv_ResetEvent(
2933 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2939 VkResult
radv_CreateBuffer(
2941 const VkBufferCreateInfo
* pCreateInfo
,
2942 const VkAllocationCallbacks
* pAllocator
,
2945 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2946 struct radv_buffer
*buffer
;
2948 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2950 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2951 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2953 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2955 buffer
->size
= pCreateInfo
->size
;
2956 buffer
->usage
= pCreateInfo
->usage
;
2959 buffer
->flags
= pCreateInfo
->flags
;
2961 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
2962 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR
) != NULL
;
2964 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2965 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2966 align64(buffer
->size
, 4096),
2967 4096, 0, RADEON_FLAG_VIRTUAL
);
2969 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2970 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2974 *pBuffer
= radv_buffer_to_handle(buffer
);
2979 void radv_DestroyBuffer(
2982 const VkAllocationCallbacks
* pAllocator
)
2984 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2985 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2990 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2991 device
->ws
->buffer_destroy(buffer
->bo
);
2993 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2996 static inline unsigned
2997 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
3000 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
3002 return image
->surface
.u
.legacy
.tiling_index
[level
];
3005 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
3007 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
3011 radv_initialise_color_surface(struct radv_device
*device
,
3012 struct radv_color_buffer_info
*cb
,
3013 struct radv_image_view
*iview
)
3015 const struct vk_format_description
*desc
;
3016 unsigned ntype
, format
, swap
, endian
;
3017 unsigned blend_clamp
= 0, blend_bypass
= 0;
3019 const struct radeon_surf
*surf
= &iview
->image
->surface
;
3021 desc
= vk_format_description(iview
->vk_format
);
3023 memset(cb
, 0, sizeof(*cb
));
3025 /* Intensity is implemented as Red, so treat it that way. */
3026 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
3028 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3030 cb
->cb_color_base
= va
>> 8;
3032 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3033 struct gfx9_surf_meta_flags meta
;
3034 if (iview
->image
->dcc_offset
)
3035 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
3037 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
3039 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3040 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
3041 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
3042 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
3044 cb
->cb_color_base
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
3045 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
3047 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
3048 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
3050 cb
->cb_color_base
+= level_info
->offset
>> 8;
3051 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
3052 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
3054 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
3055 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
3056 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
3058 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
3059 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
3060 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
3062 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
3064 if (iview
->image
->fmask
.size
) {
3065 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
3066 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
3067 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
3068 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
3070 /* This must be set for fast clear to work without FMASK. */
3071 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
3072 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
3073 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
3074 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
3078 /* CMASK variables */
3079 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3080 va
+= iview
->image
->cmask
.offset
;
3081 cb
->cb_color_cmask
= va
>> 8;
3083 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3084 va
+= iview
->image
->dcc_offset
;
3085 cb
->cb_dcc_base
= va
>> 8;
3086 cb
->cb_dcc_base
|= iview
->image
->surface
.tile_swizzle
;
3088 uint32_t max_slice
= radv_surface_layer_count(iview
);
3089 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
3090 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
3092 if (iview
->image
->info
.samples
> 1) {
3093 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
3095 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
3096 S_028C74_NUM_FRAGMENTS(log_samples
);
3099 if (iview
->image
->fmask
.size
) {
3100 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
3101 cb
->cb_color_fmask
= va
>> 8;
3102 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
3104 cb
->cb_color_fmask
= cb
->cb_color_base
;
3107 ntype
= radv_translate_color_numformat(iview
->vk_format
,
3109 vk_format_get_first_non_void_channel(iview
->vk_format
));
3110 format
= radv_translate_colorformat(iview
->vk_format
);
3111 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
3112 radv_finishme("Illegal color\n");
3113 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
3114 endian
= radv_colorformat_endian_swap(format
);
3116 /* blend clamp should be set for all NORM/SRGB types */
3117 if (ntype
== V_028C70_NUMBER_UNORM
||
3118 ntype
== V_028C70_NUMBER_SNORM
||
3119 ntype
== V_028C70_NUMBER_SRGB
)
3122 /* set blend bypass according to docs if SINT/UINT or
3123 8/24 COLOR variants */
3124 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
3125 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
3126 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
3131 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
3132 (format
== V_028C70_COLOR_8
||
3133 format
== V_028C70_COLOR_8_8
||
3134 format
== V_028C70_COLOR_8_8_8_8
))
3135 ->color_is_int8
= true;
3137 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
3138 S_028C70_COMP_SWAP(swap
) |
3139 S_028C70_BLEND_CLAMP(blend_clamp
) |
3140 S_028C70_BLEND_BYPASS(blend_bypass
) |
3141 S_028C70_SIMPLE_FLOAT(1) |
3142 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
3143 ntype
!= V_028C70_NUMBER_SNORM
&&
3144 ntype
!= V_028C70_NUMBER_SRGB
&&
3145 format
!= V_028C70_COLOR_8_24
&&
3146 format
!= V_028C70_COLOR_24_8
) |
3147 S_028C70_NUMBER_TYPE(ntype
) |
3148 S_028C70_ENDIAN(endian
);
3149 if ((iview
->image
->info
.samples
> 1) && iview
->image
->fmask
.size
) {
3150 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
3151 if (device
->physical_device
->rad_info
.chip_class
== SI
) {
3152 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
3153 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
3157 if (iview
->image
->cmask
.size
&&
3158 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
3159 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
3161 if (radv_vi_dcc_enabled(iview
->image
, iview
->base_mip
))
3162 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
3164 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
3165 unsigned max_uncompressed_block_size
= 2;
3166 if (iview
->image
->info
.samples
> 1) {
3167 if (iview
->image
->surface
.bpe
== 1)
3168 max_uncompressed_block_size
= 0;
3169 else if (iview
->image
->surface
.bpe
== 2)
3170 max_uncompressed_block_size
= 1;
3173 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
3174 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3177 /* This must be set for fast clear to work without FMASK. */
3178 if (!iview
->image
->fmask
.size
&&
3179 device
->physical_device
->rad_info
.chip_class
== SI
) {
3180 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
3181 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
3184 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3185 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
3186 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
3188 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
3189 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
3190 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
3191 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->extent
.width
- 1) |
3192 S_028C68_MIP0_HEIGHT(iview
->extent
.height
- 1) |
3193 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
3198 radv_initialise_ds_surface(struct radv_device
*device
,
3199 struct radv_ds_buffer_info
*ds
,
3200 struct radv_image_view
*iview
)
3202 unsigned level
= iview
->base_mip
;
3203 unsigned format
, stencil_format
;
3204 uint64_t va
, s_offs
, z_offs
;
3205 bool stencil_only
= false;
3206 memset(ds
, 0, sizeof(*ds
));
3207 switch (iview
->image
->vk_format
) {
3208 case VK_FORMAT_D24_UNORM_S8_UINT
:
3209 case VK_FORMAT_X8_D24_UNORM_PACK32
:
3210 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3211 ds
->offset_scale
= 2.0f
;
3213 case VK_FORMAT_D16_UNORM
:
3214 case VK_FORMAT_D16_UNORM_S8_UINT
:
3215 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3216 ds
->offset_scale
= 4.0f
;
3218 case VK_FORMAT_D32_SFLOAT
:
3219 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
3220 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3221 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3222 ds
->offset_scale
= 1.0f
;
3224 case VK_FORMAT_S8_UINT
:
3225 stencil_only
= true;
3231 format
= radv_translate_dbformat(iview
->image
->vk_format
);
3232 stencil_format
= iview
->image
->surface
.has_stencil
?
3233 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
3235 uint32_t max_slice
= radv_surface_layer_count(iview
);
3236 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
3237 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
3239 ds
->db_htile_data_base
= 0;
3240 ds
->db_htile_surface
= 0;
3242 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3243 s_offs
= z_offs
= va
;
3245 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3246 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
3247 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
3249 ds
->db_z_info
= S_028038_FORMAT(format
) |
3250 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
3251 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3252 S_028038_MAXMIP(iview
->image
->info
.levels
- 1);
3253 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
3254 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
3256 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3257 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
3258 ds
->db_depth_view
|= S_028008_MIPID(level
);
3260 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
3261 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
3263 if (radv_htile_enabled(iview
->image
, level
)) {
3264 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
3266 if (iview
->image
->tc_compatible_htile
) {
3267 unsigned max_zplanes
= 4;
3269 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
3270 iview
->image
->info
.samples
> 1)
3273 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
3274 S_028038_ITERATE_FLUSH(1);
3275 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
3278 if (!iview
->image
->surface
.has_stencil
)
3279 /* Use all of the htile_buffer for depth if there's no stencil. */
3280 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
3281 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3282 iview
->image
->htile_offset
;
3283 ds
->db_htile_data_base
= va
>> 8;
3284 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
3285 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
3286 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
3289 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
3292 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
3294 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
3295 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
3297 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!iview
->image
->tc_compatible_htile
);
3298 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
3299 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
3301 if (iview
->image
->info
.samples
> 1)
3302 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
3304 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3305 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
3306 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
3307 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
3308 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
3309 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
3310 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
3311 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
3314 tile_mode
= stencil_tile_mode
;
3316 ds
->db_depth_info
|=
3317 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
3318 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
3319 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
3320 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
3321 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
3322 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
3323 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
3324 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
3326 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
3327 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3328 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
3329 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
3331 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3334 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
3335 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
3336 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
3338 if (radv_htile_enabled(iview
->image
, level
)) {
3339 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
3341 if (!iview
->image
->surface
.has_stencil
&&
3342 !iview
->image
->tc_compatible_htile
)
3343 /* Use all of the htile_buffer for depth if there's no stencil. */
3344 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3346 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3347 iview
->image
->htile_offset
;
3348 ds
->db_htile_data_base
= va
>> 8;
3349 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
3351 if (iview
->image
->tc_compatible_htile
) {
3352 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
3354 if (iview
->image
->info
.samples
<= 1)
3355 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3356 else if (iview
->image
->info
.samples
<= 4)
3357 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3359 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3364 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
3365 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
3368 VkResult
radv_CreateFramebuffer(
3370 const VkFramebufferCreateInfo
* pCreateInfo
,
3371 const VkAllocationCallbacks
* pAllocator
,
3372 VkFramebuffer
* pFramebuffer
)
3374 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3375 struct radv_framebuffer
*framebuffer
;
3377 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
3379 size_t size
= sizeof(*framebuffer
) +
3380 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
3381 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
3382 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3383 if (framebuffer
== NULL
)
3384 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3386 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
3387 framebuffer
->width
= pCreateInfo
->width
;
3388 framebuffer
->height
= pCreateInfo
->height
;
3389 framebuffer
->layers
= pCreateInfo
->layers
;
3390 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
3391 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
3392 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
3393 framebuffer
->attachments
[i
].attachment
= iview
;
3394 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3395 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
3396 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3397 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
3399 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
3400 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
3401 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
3404 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
3408 void radv_DestroyFramebuffer(
3411 const VkAllocationCallbacks
* pAllocator
)
3413 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3414 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3418 vk_free2(&device
->alloc
, pAllocator
, fb
);
3421 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3423 switch (address_mode
) {
3424 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3425 return V_008F30_SQ_TEX_WRAP
;
3426 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3427 return V_008F30_SQ_TEX_MIRROR
;
3428 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3429 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3430 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3431 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3432 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3433 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3435 unreachable("illegal tex wrap mode");
3441 radv_tex_compare(VkCompareOp op
)
3444 case VK_COMPARE_OP_NEVER
:
3445 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3446 case VK_COMPARE_OP_LESS
:
3447 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3448 case VK_COMPARE_OP_EQUAL
:
3449 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3450 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3451 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3452 case VK_COMPARE_OP_GREATER
:
3453 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3454 case VK_COMPARE_OP_NOT_EQUAL
:
3455 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3456 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3457 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3458 case VK_COMPARE_OP_ALWAYS
:
3459 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3461 unreachable("illegal compare mode");
3467 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3470 case VK_FILTER_NEAREST
:
3471 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3472 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3473 case VK_FILTER_LINEAR
:
3474 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3475 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3476 case VK_FILTER_CUBIC_IMG
:
3478 fprintf(stderr
, "illegal texture filter");
3484 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3487 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3488 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3489 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3490 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3492 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3497 radv_tex_bordercolor(VkBorderColor bcolor
)
3500 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3501 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3502 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3503 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3504 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3505 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3506 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3507 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3508 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3516 radv_tex_aniso_filter(unsigned filter
)
3530 radv_init_sampler(struct radv_device
*device
,
3531 struct radv_sampler
*sampler
,
3532 const VkSamplerCreateInfo
*pCreateInfo
)
3534 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3535 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3536 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3537 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3539 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3540 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3541 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3542 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3543 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3544 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3545 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3546 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3547 S_008F30_DISABLE_CUBE_WRAP(0) |
3548 S_008F30_COMPAT_MODE(is_vi
));
3549 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3550 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3551 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3552 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3553 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3554 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3555 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3556 S_008F38_MIP_POINT_PRECLAMP(0) |
3557 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= VI
) |
3558 S_008F38_FILTER_PREC_FIX(1) |
3559 S_008F38_ANISO_OVERRIDE(is_vi
));
3560 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3561 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3564 VkResult
radv_CreateSampler(
3566 const VkSamplerCreateInfo
* pCreateInfo
,
3567 const VkAllocationCallbacks
* pAllocator
,
3568 VkSampler
* pSampler
)
3570 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3571 struct radv_sampler
*sampler
;
3573 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3575 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3576 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3578 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3580 radv_init_sampler(device
, sampler
, pCreateInfo
);
3581 *pSampler
= radv_sampler_to_handle(sampler
);
3586 void radv_DestroySampler(
3589 const VkAllocationCallbacks
* pAllocator
)
3591 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3592 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3596 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3599 /* vk_icd.h does not declare this function, so we declare it here to
3600 * suppress Wmissing-prototypes.
3602 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3603 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3605 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3606 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3608 /* For the full details on loader interface versioning, see
3609 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3610 * What follows is a condensed summary, to help you navigate the large and
3611 * confusing official doc.
3613 * - Loader interface v0 is incompatible with later versions. We don't
3616 * - In loader interface v1:
3617 * - The first ICD entrypoint called by the loader is
3618 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3620 * - The ICD must statically expose no other Vulkan symbol unless it is
3621 * linked with -Bsymbolic.
3622 * - Each dispatchable Vulkan handle created by the ICD must be
3623 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3624 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3625 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3626 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3627 * such loader-managed surfaces.
3629 * - Loader interface v2 differs from v1 in:
3630 * - The first ICD entrypoint called by the loader is
3631 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3632 * statically expose this entrypoint.
3634 * - Loader interface v3 differs from v2 in:
3635 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3636 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3637 * because the loader no longer does so.
3639 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3643 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
3644 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
3647 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3648 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
3650 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
3652 /* At the moment, we support only the below handle types. */
3653 assert(pGetFdInfo
->handleType
==
3654 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
||
3655 pGetFdInfo
->handleType
==
3656 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3658 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3660 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3664 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
3665 VkExternalMemoryHandleTypeFlagBitsKHR handleType
,
3667 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
3669 switch (handleType
) {
3670 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
3671 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
3675 /* The valid usage section for this function says:
3677 * "handleType must not be one of the handle types defined as
3680 * So opaque handle types fall into the default "unsupported" case.
3682 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3686 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
3687 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
3689 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3690 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
3691 uint32_t syncobj_handle
= 0;
3692 uint32_t *syncobj_dst
= NULL
;
3693 assert(pImportSemaphoreFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3695 int ret
= device
->ws
->import_syncobj(device
->ws
, pImportSemaphoreFdInfo
->fd
, &syncobj_handle
);
3697 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3699 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR
) {
3700 syncobj_dst
= &sem
->temp_syncobj
;
3702 syncobj_dst
= &sem
->syncobj
;
3706 device
->ws
->destroy_syncobj(device
->ws
, *syncobj_dst
);
3708 *syncobj_dst
= syncobj_handle
;
3709 close(pImportSemaphoreFdInfo
->fd
);
3713 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
3714 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
3717 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3718 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
3720 uint32_t syncobj_handle
;
3722 assert(pGetFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3723 if (sem
->temp_syncobj
)
3724 syncobj_handle
= sem
->temp_syncobj
;
3726 syncobj_handle
= sem
->syncobj
;
3727 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
3729 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3733 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3734 VkPhysicalDevice physicalDevice
,
3735 const VkPhysicalDeviceExternalSemaphoreInfoKHR
* pExternalSemaphoreInfo
,
3736 VkExternalSemaphorePropertiesKHR
* pExternalSemaphoreProperties
)
3738 if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
) {
3739 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3740 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3741 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR
|
3742 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
3744 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
3745 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
3746 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
3750 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
3751 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
3753 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3754 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
3755 uint32_t syncobj_handle
= 0;
3756 uint32_t *syncobj_dst
= NULL
;
3757 assert(pImportFenceFdInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3759 int ret
= device
->ws
->import_syncobj(device
->ws
, pImportFenceFdInfo
->fd
, &syncobj_handle
);
3761 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3763 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT_KHR
) {
3764 syncobj_dst
= &fence
->temp_syncobj
;
3766 syncobj_dst
= &fence
->syncobj
;
3770 device
->ws
->destroy_syncobj(device
->ws
, *syncobj_dst
);
3772 *syncobj_dst
= syncobj_handle
;
3773 close(pImportFenceFdInfo
->fd
);
3777 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
3778 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
3781 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3782 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
3784 uint32_t syncobj_handle
;
3786 assert(pGetFdInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3787 if (fence
->temp_syncobj
)
3788 syncobj_handle
= fence
->temp_syncobj
;
3790 syncobj_handle
= fence
->syncobj
;
3791 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
3793 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3797 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
3798 VkPhysicalDevice physicalDevice
,
3799 const VkPhysicalDeviceExternalFenceInfoKHR
* pExternalFenceInfo
,
3800 VkExternalFencePropertiesKHR
* pExternalFenceProperties
)
3802 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
3804 if (pdevice
->rad_info
.has_syncobj_wait
&&
3805 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
) {
3806 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3807 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3808 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR
|
3809 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
3811 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
3812 pExternalFenceProperties
->compatibleHandleTypes
= 0;
3813 pExternalFenceProperties
->externalFenceFeatures
= 0;