2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdatomic.h>
41 #include <sys/prctl.h>
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
50 #include "util/disk_cache.h"
54 #include "drm-uapi/amdgpu_drm.h"
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "winsys/null/radv_null_winsys_public.h"
57 #include "ac_llvm_util.h"
58 #include "vk_format.h"
61 #include "util/build_id.h"
62 #include "util/debug.h"
63 #include "util/mesa-sha1.h"
64 #include "util/timespec.h"
65 #include "util/u_atomic.h"
66 #include "compiler/glsl_types.h"
67 #include "util/driconf.h"
69 static struct radv_timeline_point
*
70 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
71 struct radv_timeline
*timeline
,
74 static struct radv_timeline_point
*
75 radv_timeline_add_point_locked(struct radv_device
*device
,
76 struct radv_timeline
*timeline
,
80 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
81 struct list_head
*processing_list
);
84 void radv_destroy_semaphore_part(struct radv_device
*device
,
85 struct radv_semaphore_part
*part
);
88 radv_create_pthread_cond(pthread_cond_t
*cond
);
90 uint64_t radv_get_current_time(void)
93 clock_gettime(CLOCK_MONOTONIC
, &tv
);
94 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
97 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
99 uint64_t current_time
= radv_get_current_time();
101 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
103 return current_time
+ timeout
;
107 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
109 struct mesa_sha1 ctx
;
110 unsigned char sha1
[20];
111 unsigned ptr_size
= sizeof(void*);
113 memset(uuid
, 0, VK_UUID_SIZE
);
114 _mesa_sha1_init(&ctx
);
116 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
117 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
120 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
121 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
122 _mesa_sha1_final(&ctx
, sha1
);
124 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
129 radv_get_driver_uuid(void *uuid
)
131 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
135 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
137 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
141 radv_get_visible_vram_size(struct radv_physical_device
*device
)
143 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
147 radv_get_vram_size(struct radv_physical_device
*device
)
149 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
153 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
155 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
156 uint64_t vram_size
= radv_get_vram_size(device
);
157 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
158 device
->memory_properties
.memoryHeapCount
= 0;
160 vram_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
163 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 if (device
->rad_info
.gart_size
> 0) {
168 gart_index
= device
->memory_properties
.memoryHeapCount
++;
169 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
170 .size
= device
->rad_info
.gart_size
,
175 if (visible_vram_size
) {
176 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
177 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
178 .size
= visible_vram_size
,
179 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
183 unsigned type_count
= 0;
185 if (vram_index
>= 0 || visible_vram_index
>= 0) {
186 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
187 device
->memory_flags
[type_count
] = RADEON_FLAG_NO_CPU_ACCESS
;
188 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
189 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
190 .heapIndex
= vram_index
>= 0 ? vram_index
: visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
196 device
->memory_flags
[type_count
] = RADEON_FLAG_GTT_WC
| RADEON_FLAG_CPU_ACCESS
;
197 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
198 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
199 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
200 .heapIndex
= gart_index
,
203 if (visible_vram_index
>= 0) {
204 device
->memory_domains
[type_count
] = RADEON_DOMAIN_VRAM
;
205 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
206 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
207 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
208 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
209 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
210 .heapIndex
= visible_vram_index
,
214 if (gart_index
>= 0) {
215 device
->memory_domains
[type_count
] = RADEON_DOMAIN_GTT
;
216 device
->memory_flags
[type_count
] = RADEON_FLAG_CPU_ACCESS
;
217 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
218 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
219 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
220 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
221 .heapIndex
= gart_index
,
224 device
->memory_properties
.memoryTypeCount
= type_count
;
226 if (device
->rad_info
.has_l2_uncached
) {
227 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
228 VkMemoryType mem_type
= device
->memory_properties
.memoryTypes
[i
];
230 if ((mem_type
.propertyFlags
& (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
231 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
)) ||
232 mem_type
.propertyFlags
== VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
) {
234 VkMemoryPropertyFlags property_flags
= mem_type
.propertyFlags
|
235 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD
|
236 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD
;
238 device
->memory_domains
[type_count
] = device
->memory_domains
[i
];
239 device
->memory_flags
[type_count
] = device
->memory_flags
[i
] | RADEON_FLAG_VA_UNCACHED
;
240 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
241 .propertyFlags
= property_flags
,
242 .heapIndex
= mem_type
.heapIndex
,
246 device
->memory_properties
.memoryTypeCount
= type_count
;
251 radv_get_compiler_string(struct radv_physical_device
*pdevice
)
253 if (!pdevice
->use_llvm
) {
254 /* Some games like SotTR apply shader workarounds if the LLVM
255 * version is too old or if the LLVM version string is
256 * missing. This gives 2-5% performance with SotTR and ACO.
258 if (driQueryOptionb(&pdevice
->instance
->dri_options
,
259 "radv_report_llvm9_version_string")) {
260 return "ACO/LLVM 9.0.1";
266 return "LLVM " MESA_LLVM_VERSION_STRING
;
270 radv_physical_device_try_create(struct radv_instance
*instance
,
271 drmDevicePtr drm_device
,
272 struct radv_physical_device
**device_out
)
279 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
280 drmVersionPtr version
;
282 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
284 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
285 radv_logi("Could not open device '%s'", path
);
287 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
290 version
= drmGetVersion(fd
);
294 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
295 radv_logi("Could not get the kernel driver version for device '%s'", path
);
297 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
298 "failed to get version %s: %m", path
);
301 if (strcmp(version
->name
, "amdgpu")) {
302 drmFreeVersion(version
);
305 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
306 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
308 return VK_ERROR_INCOMPATIBLE_DRIVER
;
310 drmFreeVersion(version
);
312 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
313 radv_logi("Found compatible device '%s'.", path
);
316 struct radv_physical_device
*device
=
317 vk_zalloc2(&instance
->alloc
, NULL
, sizeof(*device
), 8,
318 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
320 result
= vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
324 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
325 device
->instance
= instance
;
328 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
329 instance
->perftest_flags
);
331 device
->ws
= radv_null_winsys_create();
335 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
336 "failed to initialize winsys");
340 if (drm_device
&& instance
->enabled_extensions
.KHR_display
) {
341 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
342 if (master_fd
>= 0) {
343 uint32_t accel_working
= 0;
344 struct drm_amdgpu_info request
= {
345 .return_pointer
= (uintptr_t)&accel_working
,
346 .return_size
= sizeof(accel_working
),
347 .query
= AMDGPU_INFO_ACCEL_WORKING
350 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
357 device
->master_fd
= master_fd
;
358 device
->local_fd
= fd
;
359 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
361 device
->use_llvm
= instance
->debug_flags
& RADV_DEBUG_LLVM
;
363 snprintf(device
->name
, sizeof(device
->name
),
365 device
->rad_info
.name
, radv_get_compiler_string(device
));
367 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
368 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
369 "cannot generate UUID");
373 /* These flags affect shader compilation. */
374 uint64_t shader_env_flags
= (device
->use_llvm
? 0 : 0x2);
376 /* The gpu id is already embedded in the uuid so we just pass "radv"
377 * when creating the cache.
379 char buf
[VK_UUID_SIZE
* 2 + 1];
380 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
381 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
383 if (device
->rad_info
.chip_class
< GFX8
|| !device
->use_llvm
)
384 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
386 radv_get_driver_uuid(&device
->driver_uuid
);
387 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
389 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
390 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
392 device
->dcc_msaa_allowed
=
393 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
395 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
396 device
->rad_info
.family
!= CHIP_NAVI14
&&
397 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
399 /* TODO: Implement NGG GS with ACO. */
400 device
->use_ngg_gs
= device
->use_ngg
&& device
->use_llvm
;
401 device
->use_ngg_streamout
= false;
403 /* Determine the number of threads per wave for all stages. */
404 device
->cs_wave_size
= 64;
405 device
->ps_wave_size
= 64;
406 device
->ge_wave_size
= 64;
408 if (device
->rad_info
.chip_class
>= GFX10
) {
409 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
410 device
->cs_wave_size
= 32;
412 /* For pixel shaders, wave64 is recommanded. */
413 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
414 device
->ps_wave_size
= 32;
416 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
417 device
->ge_wave_size
= 32;
420 radv_physical_device_init_mem_types(device
);
422 radv_physical_device_get_supported_extensions(device
,
423 &device
->supported_extensions
);
426 device
->bus_info
= *drm_device
->businfo
.pci
;
428 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
429 ac_print_gpu_info(&device
->rad_info
);
431 /* The WSI is structured as a layer on top of the driver, so this has
432 * to be the last part of initialization (at least until we get other
435 result
= radv_init_wsi(device
);
436 if (result
!= VK_SUCCESS
) {
437 vk_error(instance
, result
);
438 goto fail_disk_cache
;
441 *device_out
= device
;
446 disk_cache_destroy(device
->disk_cache
);
448 device
->ws
->destroy(device
->ws
);
450 vk_free(&instance
->alloc
, device
);
460 radv_physical_device_destroy(struct radv_physical_device
*device
)
462 radv_finish_wsi(device
);
463 device
->ws
->destroy(device
->ws
);
464 disk_cache_destroy(device
->disk_cache
);
465 close(device
->local_fd
);
466 if (device
->master_fd
!= -1)
467 close(device
->master_fd
);
468 vk_free(&device
->instance
->alloc
, device
);
472 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
473 VkSystemAllocationScope allocationScope
)
479 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
480 size_t align
, VkSystemAllocationScope allocationScope
)
482 return realloc(pOriginal
, size
);
486 default_free_func(void *pUserData
, void *pMemory
)
491 static const VkAllocationCallbacks default_alloc
= {
493 .pfnAllocation
= default_alloc_func
,
494 .pfnReallocation
= default_realloc_func
,
495 .pfnFree
= default_free_func
,
498 static const struct debug_control radv_debug_options
[] = {
499 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
500 {"nodcc", RADV_DEBUG_NO_DCC
},
501 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
502 {"nocache", RADV_DEBUG_NO_CACHE
},
503 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
504 {"nohiz", RADV_DEBUG_NO_HIZ
},
505 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
506 {"allbos", RADV_DEBUG_ALL_BOS
},
507 {"noibs", RADV_DEBUG_NO_IBS
},
508 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
509 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
510 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
511 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
512 {"preoptir", RADV_DEBUG_PREOPTIR
},
513 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
514 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
515 {"info", RADV_DEBUG_INFO
},
516 {"errors", RADV_DEBUG_ERRORS
},
517 {"startup", RADV_DEBUG_STARTUP
},
518 {"checkir", RADV_DEBUG_CHECKIR
},
519 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
520 {"nobinning", RADV_DEBUG_NOBINNING
},
521 {"nongg", RADV_DEBUG_NO_NGG
},
522 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
523 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
524 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
525 {"llvm", RADV_DEBUG_LLVM
},
530 radv_get_debug_option_name(int id
)
532 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
533 return radv_debug_options
[id
].string
;
536 static const struct debug_control radv_perftest_options
[] = {
537 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
538 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
539 {"bolist", RADV_PERFTEST_BO_LIST
},
540 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
541 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
542 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
543 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
544 {"dfsm", RADV_PERFTEST_DFSM
},
549 radv_get_perftest_option_name(int id
)
551 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
552 return radv_perftest_options
[id
].string
;
556 radv_handle_per_app_options(struct radv_instance
*instance
,
557 const VkApplicationInfo
*info
)
559 const char *name
= info
? info
->pApplicationName
: NULL
;
560 const char *engine_name
= info
? info
->pEngineName
: NULL
;
563 if (!strcmp(name
, "DOOM_VFR")) {
564 /* Work around a Doom VFR game bug */
565 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
566 } else if (!strcmp(name
, "Fledge")) {
568 * Zero VRAM for "The Surge 2"
570 * This avoid a hang when when rendering any level. Likely
571 * uninitialized data in an indirect draw.
573 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
574 } else if (!strcmp(name
, "No Man's Sky")) {
575 /* Work around a NMS game bug */
576 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
577 } else if (!strcmp(name
, "DOOMEternal")) {
578 /* Zero VRAM for Doom Eternal to fix rendering issues. */
579 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
580 } else if (!strcmp(name
, "Red Dead Redemption 2")) {
581 /* Work around a RDR2 game bug */
582 instance
->debug_flags
|= RADV_DEBUG_DISCARD_TO_DEMOTE
;
587 if (!strcmp(engine_name
, "vkd3d")) {
588 /* Zero VRAM for all VKD3D (DX12->VK) games to fix
591 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
592 } else if (!strcmp(engine_name
, "Quantic Dream Engine")) {
593 /* Fix various artifacts in Detroit: Become Human */
594 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
|
595 RADV_DEBUG_DISCARD_TO_DEMOTE
;
599 instance
->enable_mrt_output_nan_fixup
=
600 driQueryOptionb(&instance
->dri_options
,
601 "radv_enable_mrt_output_nan_fixup");
603 if (driQueryOptionb(&instance
->dri_options
, "radv_no_dynamic_bounds"))
604 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
607 static const char radv_dri_options_xml
[] =
609 DRI_CONF_SECTION_PERFORMANCE
610 DRI_CONF_ADAPTIVE_SYNC("true")
611 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
612 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
613 DRI_CONF_VK_X11_ENSURE_MIN_IMAGE_COUNT("false")
614 DRI_CONF_RADV_REPORT_LLVM9_VERSION_STRING("false")
615 DRI_CONF_RADV_ENABLE_MRT_OUTPUT_NAN_FIXUP("false")
616 DRI_CONF_RADV_NO_DYNAMIC_BOUNDS("false")
619 DRI_CONF_SECTION_DEBUG
620 DRI_CONF_VK_WSI_FORCE_BGRA8_UNORM_FIRST("false")
624 static void radv_init_dri_options(struct radv_instance
*instance
)
626 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
627 driParseConfigFiles(&instance
->dri_options
,
628 &instance
->available_dri_options
,
630 instance
->engineName
,
631 instance
->engineVersion
);
634 VkResult
radv_CreateInstance(
635 const VkInstanceCreateInfo
* pCreateInfo
,
636 const VkAllocationCallbacks
* pAllocator
,
637 VkInstance
* pInstance
)
639 struct radv_instance
*instance
;
642 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
643 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
645 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
647 vk_object_base_init(NULL
, &instance
->base
, VK_OBJECT_TYPE_INSTANCE
);
650 instance
->alloc
= *pAllocator
;
652 instance
->alloc
= default_alloc
;
654 if (pCreateInfo
->pApplicationInfo
) {
655 const VkApplicationInfo
*app
= pCreateInfo
->pApplicationInfo
;
657 instance
->engineName
=
658 vk_strdup(&instance
->alloc
, app
->pEngineName
,
659 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
660 instance
->engineVersion
= app
->engineVersion
;
661 instance
->apiVersion
= app
->apiVersion
;
664 if (instance
->apiVersion
== 0)
665 instance
->apiVersion
= VK_API_VERSION_1_0
;
667 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
670 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
671 radv_perftest_options
);
673 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
674 radv_logi("Created an instance");
676 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
678 for (idx
= 0; idx
< RADV_INSTANCE_EXTENSION_COUNT
; idx
++) {
679 if (!strcmp(pCreateInfo
->ppEnabledExtensionNames
[i
],
680 radv_instance_extensions
[idx
].extensionName
))
684 if (idx
>= RADV_INSTANCE_EXTENSION_COUNT
||
685 !radv_instance_extensions_supported
.extensions
[idx
]) {
686 vk_object_base_finish(&instance
->base
);
687 vk_free2(&default_alloc
, pAllocator
, instance
);
688 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
691 instance
->enabled_extensions
.extensions
[idx
] = true;
694 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
696 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->dispatch
.entrypoints
); i
++) {
697 /* Vulkan requires that entrypoints for extensions which have
698 * not been enabled must not be advertised.
701 !radv_instance_entrypoint_is_enabled(i
, instance
->apiVersion
,
702 &instance
->enabled_extensions
)) {
703 instance
->dispatch
.entrypoints
[i
] = NULL
;
705 instance
->dispatch
.entrypoints
[i
] =
706 radv_instance_dispatch_table
.entrypoints
[i
];
710 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->physical_device_dispatch
.entrypoints
); i
++) {
711 /* Vulkan requires that entrypoints for extensions which have
712 * not been enabled must not be advertised.
715 !radv_physical_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
716 &instance
->enabled_extensions
)) {
717 instance
->physical_device_dispatch
.entrypoints
[i
] = NULL
;
719 instance
->physical_device_dispatch
.entrypoints
[i
] =
720 radv_physical_device_dispatch_table
.entrypoints
[i
];
724 for (unsigned i
= 0; i
< ARRAY_SIZE(instance
->device_dispatch
.entrypoints
); i
++) {
725 /* Vulkan requires that entrypoints for extensions which have
726 * not been enabled must not be advertised.
729 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
730 &instance
->enabled_extensions
, NULL
)) {
731 instance
->device_dispatch
.entrypoints
[i
] = NULL
;
733 instance
->device_dispatch
.entrypoints
[i
] =
734 radv_device_dispatch_table
.entrypoints
[i
];
738 instance
->physical_devices_enumerated
= false;
739 list_inithead(&instance
->physical_devices
);
741 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
742 if (result
!= VK_SUCCESS
) {
743 vk_object_base_finish(&instance
->base
);
744 vk_free2(&default_alloc
, pAllocator
, instance
);
745 return vk_error(instance
, result
);
748 glsl_type_singleton_init_or_ref();
750 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
752 radv_init_dri_options(instance
);
753 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
755 *pInstance
= radv_instance_to_handle(instance
);
760 void radv_DestroyInstance(
761 VkInstance _instance
,
762 const VkAllocationCallbacks
* pAllocator
)
764 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
769 list_for_each_entry_safe(struct radv_physical_device
, pdevice
,
770 &instance
->physical_devices
, link
) {
771 radv_physical_device_destroy(pdevice
);
774 vk_free(&instance
->alloc
, instance
->engineName
);
776 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
778 glsl_type_singleton_decref();
780 driDestroyOptionCache(&instance
->dri_options
);
781 driDestroyOptionInfo(&instance
->available_dri_options
);
783 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
785 vk_object_base_finish(&instance
->base
);
786 vk_free(&instance
->alloc
, instance
);
790 radv_enumerate_physical_devices(struct radv_instance
*instance
)
792 if (instance
->physical_devices_enumerated
)
795 instance
->physical_devices_enumerated
= true;
797 /* TODO: Check for more devices ? */
798 drmDevicePtr devices
[8];
799 VkResult result
= VK_SUCCESS
;
802 if (getenv("RADV_FORCE_FAMILY")) {
803 /* When RADV_FORCE_FAMILY is set, the driver creates a nul
804 * device that allows to test the compiler without having an
807 struct radv_physical_device
*pdevice
;
809 result
= radv_physical_device_try_create(instance
, NULL
, &pdevice
);
810 if (result
!= VK_SUCCESS
)
813 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
817 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
819 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
820 radv_logi("Found %d drm nodes", max_devices
);
823 return vk_error(instance
, VK_SUCCESS
);
825 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
826 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
827 devices
[i
]->bustype
== DRM_BUS_PCI
&&
828 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
830 struct radv_physical_device
*pdevice
;
831 result
= radv_physical_device_try_create(instance
, devices
[i
],
833 /* Incompatible DRM device, skip. */
834 if (result
== VK_ERROR_INCOMPATIBLE_DRIVER
) {
839 /* Error creating the physical device, report the error. */
840 if (result
!= VK_SUCCESS
)
843 list_addtail(&pdevice
->link
, &instance
->physical_devices
);
846 drmFreeDevices(devices
, max_devices
);
848 /* If we successfully enumerated any devices, call it success */
852 VkResult
radv_EnumeratePhysicalDevices(
853 VkInstance _instance
,
854 uint32_t* pPhysicalDeviceCount
,
855 VkPhysicalDevice
* pPhysicalDevices
)
857 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
858 VK_OUTARRAY_MAKE(out
, pPhysicalDevices
, pPhysicalDeviceCount
);
860 VkResult result
= radv_enumerate_physical_devices(instance
);
861 if (result
!= VK_SUCCESS
)
864 list_for_each_entry(struct radv_physical_device
, pdevice
,
865 &instance
->physical_devices
, link
) {
866 vk_outarray_append(&out
, i
) {
867 *i
= radv_physical_device_to_handle(pdevice
);
871 return vk_outarray_status(&out
);
874 VkResult
radv_EnumeratePhysicalDeviceGroups(
875 VkInstance _instance
,
876 uint32_t* pPhysicalDeviceGroupCount
,
877 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
879 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
880 VK_OUTARRAY_MAKE(out
, pPhysicalDeviceGroupProperties
,
881 pPhysicalDeviceGroupCount
);
883 VkResult result
= radv_enumerate_physical_devices(instance
);
884 if (result
!= VK_SUCCESS
)
887 list_for_each_entry(struct radv_physical_device
, pdevice
,
888 &instance
->physical_devices
, link
) {
889 vk_outarray_append(&out
, p
) {
890 p
->physicalDeviceCount
= 1;
891 memset(p
->physicalDevices
, 0, sizeof(p
->physicalDevices
));
892 p
->physicalDevices
[0] = radv_physical_device_to_handle(pdevice
);
893 p
->subsetAllocation
= false;
897 return vk_outarray_status(&out
);
900 void radv_GetPhysicalDeviceFeatures(
901 VkPhysicalDevice physicalDevice
,
902 VkPhysicalDeviceFeatures
* pFeatures
)
904 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
905 memset(pFeatures
, 0, sizeof(*pFeatures
));
907 *pFeatures
= (VkPhysicalDeviceFeatures
) {
908 .robustBufferAccess
= true,
909 .fullDrawIndexUint32
= true,
910 .imageCubeArray
= true,
911 .independentBlend
= true,
912 .geometryShader
= true,
913 .tessellationShader
= true,
914 .sampleRateShading
= true,
915 .dualSrcBlend
= true,
917 .multiDrawIndirect
= true,
918 .drawIndirectFirstInstance
= true,
920 .depthBiasClamp
= true,
921 .fillModeNonSolid
= true,
926 .multiViewport
= true,
927 .samplerAnisotropy
= true,
928 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
929 .textureCompressionASTC_LDR
= false,
930 .textureCompressionBC
= true,
931 .occlusionQueryPrecise
= true,
932 .pipelineStatisticsQuery
= true,
933 .vertexPipelineStoresAndAtomics
= true,
934 .fragmentStoresAndAtomics
= true,
935 .shaderTessellationAndGeometryPointSize
= true,
936 .shaderImageGatherExtended
= true,
937 .shaderStorageImageExtendedFormats
= true,
938 .shaderStorageImageMultisample
= true,
939 .shaderUniformBufferArrayDynamicIndexing
= true,
940 .shaderSampledImageArrayDynamicIndexing
= true,
941 .shaderStorageBufferArrayDynamicIndexing
= true,
942 .shaderStorageImageArrayDynamicIndexing
= true,
943 .shaderStorageImageReadWithoutFormat
= true,
944 .shaderStorageImageWriteWithoutFormat
= true,
945 .shaderClipDistance
= true,
946 .shaderCullDistance
= true,
947 .shaderFloat64
= true,
950 .sparseBinding
= true,
951 .variableMultisampleRate
= true,
952 .shaderResourceMinLod
= true,
953 .inheritedQueries
= true,
958 radv_get_physical_device_features_1_1(struct radv_physical_device
*pdevice
,
959 VkPhysicalDeviceVulkan11Features
*f
)
961 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
);
963 f
->storageBuffer16BitAccess
= true;
964 f
->uniformAndStorageBuffer16BitAccess
= true;
965 f
->storagePushConstant16
= true;
966 f
->storageInputOutput16
= pdevice
->rad_info
.has_packed_math_16bit
&& (LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
);
968 f
->multiviewGeometryShader
= true;
969 f
->multiviewTessellationShader
= true;
970 f
->variablePointersStorageBuffer
= true;
971 f
->variablePointers
= true;
972 f
->protectedMemory
= false;
973 f
->samplerYcbcrConversion
= true;
974 f
->shaderDrawParameters
= true;
978 radv_get_physical_device_features_1_2(struct radv_physical_device
*pdevice
,
979 VkPhysicalDeviceVulkan12Features
*f
)
981 assert(f
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
);
983 f
->samplerMirrorClampToEdge
= true;
984 f
->drawIndirectCount
= true;
985 f
->storageBuffer8BitAccess
= true;
986 f
->uniformAndStorageBuffer8BitAccess
= true;
987 f
->storagePushConstant8
= true;
988 f
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
989 f
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
990 f
->shaderFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
991 f
->shaderInt8
= true;
993 f
->descriptorIndexing
= true;
994 f
->shaderInputAttachmentArrayDynamicIndexing
= true;
995 f
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
996 f
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
997 f
->shaderUniformBufferArrayNonUniformIndexing
= true;
998 f
->shaderSampledImageArrayNonUniformIndexing
= true;
999 f
->shaderStorageBufferArrayNonUniformIndexing
= true;
1000 f
->shaderStorageImageArrayNonUniformIndexing
= true;
1001 f
->shaderInputAttachmentArrayNonUniformIndexing
= true;
1002 f
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
1003 f
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
1004 f
->descriptorBindingUniformBufferUpdateAfterBind
= true;
1005 f
->descriptorBindingSampledImageUpdateAfterBind
= true;
1006 f
->descriptorBindingStorageImageUpdateAfterBind
= true;
1007 f
->descriptorBindingStorageBufferUpdateAfterBind
= true;
1008 f
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
1009 f
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
1010 f
->descriptorBindingUpdateUnusedWhilePending
= true;
1011 f
->descriptorBindingPartiallyBound
= true;
1012 f
->descriptorBindingVariableDescriptorCount
= true;
1013 f
->runtimeDescriptorArray
= true;
1015 f
->samplerFilterMinmax
= true;
1016 f
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
1017 f
->imagelessFramebuffer
= true;
1018 f
->uniformBufferStandardLayout
= true;
1019 f
->shaderSubgroupExtendedTypes
= true;
1020 f
->separateDepthStencilLayouts
= true;
1021 f
->hostQueryReset
= true;
1022 f
->timelineSemaphore
= pdevice
->rad_info
.has_syncobj_wait_for_submit
;
1023 f
->bufferDeviceAddress
= true;
1024 f
->bufferDeviceAddressCaptureReplay
= false;
1025 f
->bufferDeviceAddressMultiDevice
= false;
1026 f
->vulkanMemoryModel
= false;
1027 f
->vulkanMemoryModelDeviceScope
= false;
1028 f
->vulkanMemoryModelAvailabilityVisibilityChains
= false;
1029 f
->shaderOutputViewportIndex
= true;
1030 f
->shaderOutputLayer
= true;
1031 f
->subgroupBroadcastDynamicId
= true;
1034 void radv_GetPhysicalDeviceFeatures2(
1035 VkPhysicalDevice physicalDevice
,
1036 VkPhysicalDeviceFeatures2
*pFeatures
)
1038 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1039 radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1041 VkPhysicalDeviceVulkan11Features core_1_1
= {
1042 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
,
1044 radv_get_physical_device_features_1_1(pdevice
, &core_1_1
);
1046 VkPhysicalDeviceVulkan12Features core_1_2
= {
1047 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
,
1049 radv_get_physical_device_features_1_2(pdevice
, &core_1_2
);
1051 #define CORE_FEATURE(major, minor, feature) \
1052 features->feature = core_##major##_##minor.feature
1054 vk_foreach_struct(ext
, pFeatures
->pNext
) {
1055 switch (ext
->sType
) {
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
1057 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
1058 CORE_FEATURE(1, 1, variablePointersStorageBuffer
);
1059 CORE_FEATURE(1, 1, variablePointers
);
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
1063 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
1064 CORE_FEATURE(1, 1, multiview
);
1065 CORE_FEATURE(1, 1, multiviewGeometryShader
);
1066 CORE_FEATURE(1, 1, multiviewTessellationShader
);
1069 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
1070 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
1071 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
1072 CORE_FEATURE(1, 1, shaderDrawParameters
);
1075 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
1076 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
1077 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
1078 CORE_FEATURE(1, 1, protectedMemory
);
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
1082 VkPhysicalDevice16BitStorageFeatures
*features
=
1083 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
1084 CORE_FEATURE(1, 1, storageBuffer16BitAccess
);
1085 CORE_FEATURE(1, 1, uniformAndStorageBuffer16BitAccess
);
1086 CORE_FEATURE(1, 1, storagePushConstant16
);
1087 CORE_FEATURE(1, 1, storageInputOutput16
);
1090 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
1091 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
1092 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
1093 CORE_FEATURE(1, 1, samplerYcbcrConversion
);
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES
: {
1097 VkPhysicalDeviceDescriptorIndexingFeatures
*features
=
1098 (VkPhysicalDeviceDescriptorIndexingFeatures
*)ext
;
1099 CORE_FEATURE(1, 2, shaderInputAttachmentArrayDynamicIndexing
);
1100 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayDynamicIndexing
);
1101 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayDynamicIndexing
);
1102 CORE_FEATURE(1, 2, shaderUniformBufferArrayNonUniformIndexing
);
1103 CORE_FEATURE(1, 2, shaderSampledImageArrayNonUniformIndexing
);
1104 CORE_FEATURE(1, 2, shaderStorageBufferArrayNonUniformIndexing
);
1105 CORE_FEATURE(1, 2, shaderStorageImageArrayNonUniformIndexing
);
1106 CORE_FEATURE(1, 2, shaderInputAttachmentArrayNonUniformIndexing
);
1107 CORE_FEATURE(1, 2, shaderUniformTexelBufferArrayNonUniformIndexing
);
1108 CORE_FEATURE(1, 2, shaderStorageTexelBufferArrayNonUniformIndexing
);
1109 CORE_FEATURE(1, 2, descriptorBindingUniformBufferUpdateAfterBind
);
1110 CORE_FEATURE(1, 2, descriptorBindingSampledImageUpdateAfterBind
);
1111 CORE_FEATURE(1, 2, descriptorBindingStorageImageUpdateAfterBind
);
1112 CORE_FEATURE(1, 2, descriptorBindingStorageBufferUpdateAfterBind
);
1113 CORE_FEATURE(1, 2, descriptorBindingUniformTexelBufferUpdateAfterBind
);
1114 CORE_FEATURE(1, 2, descriptorBindingStorageTexelBufferUpdateAfterBind
);
1115 CORE_FEATURE(1, 2, descriptorBindingUpdateUnusedWhilePending
);
1116 CORE_FEATURE(1, 2, descriptorBindingPartiallyBound
);
1117 CORE_FEATURE(1, 2, descriptorBindingVariableDescriptorCount
);
1118 CORE_FEATURE(1, 2, runtimeDescriptorArray
);
1121 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
1122 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
1123 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
1124 features
->conditionalRendering
= true;
1125 features
->inheritedConditionalRendering
= false;
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
1129 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
1130 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
1131 features
->vertexAttributeInstanceRateDivisor
= true;
1132 features
->vertexAttributeInstanceRateZeroDivisor
= true;
1135 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
1136 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
1137 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
1138 features
->transformFeedback
= true;
1139 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES
: {
1143 VkPhysicalDeviceScalarBlockLayoutFeatures
*features
=
1144 (VkPhysicalDeviceScalarBlockLayoutFeatures
*)ext
;
1145 CORE_FEATURE(1, 2, scalarBlockLayout
);
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
1149 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
1150 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
1151 features
->memoryPriority
= true;
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
1155 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
1156 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
1157 features
->bufferDeviceAddress
= true;
1158 features
->bufferDeviceAddressCaptureReplay
= false;
1159 features
->bufferDeviceAddressMultiDevice
= false;
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES
: {
1163 VkPhysicalDeviceBufferDeviceAddressFeatures
*features
=
1164 (VkPhysicalDeviceBufferDeviceAddressFeatures
*)ext
;
1165 CORE_FEATURE(1, 2, bufferDeviceAddress
);
1166 CORE_FEATURE(1, 2, bufferDeviceAddressCaptureReplay
);
1167 CORE_FEATURE(1, 2, bufferDeviceAddressMultiDevice
);
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
1171 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
1172 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
1173 features
->depthClipEnable
= true;
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES
: {
1177 VkPhysicalDeviceHostQueryResetFeatures
*features
=
1178 (VkPhysicalDeviceHostQueryResetFeatures
*)ext
;
1179 CORE_FEATURE(1, 2, hostQueryReset
);
1182 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES
: {
1183 VkPhysicalDevice8BitStorageFeatures
*features
=
1184 (VkPhysicalDevice8BitStorageFeatures
*)ext
;
1185 CORE_FEATURE(1, 2, storageBuffer8BitAccess
);
1186 CORE_FEATURE(1, 2, uniformAndStorageBuffer8BitAccess
);
1187 CORE_FEATURE(1, 2, storagePushConstant8
);
1190 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES
: {
1191 VkPhysicalDeviceShaderFloat16Int8Features
*features
=
1192 (VkPhysicalDeviceShaderFloat16Int8Features
*)ext
;
1193 CORE_FEATURE(1, 2, shaderFloat16
);
1194 CORE_FEATURE(1, 2, shaderInt8
);
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES
: {
1198 VkPhysicalDeviceShaderAtomicInt64Features
*features
=
1199 (VkPhysicalDeviceShaderAtomicInt64Features
*)ext
;
1200 CORE_FEATURE(1, 2, shaderBufferInt64Atomics
);
1201 CORE_FEATURE(1, 2, shaderSharedInt64Atomics
);
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1205 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1206 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1207 features
->shaderDemoteToHelperInvocation
= LLVM_VERSION_MAJOR
>= 9 || !pdevice
->use_llvm
;
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1211 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1212 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1214 features
->inlineUniformBlock
= true;
1215 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1219 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1220 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1221 features
->computeDerivativeGroupQuads
= false;
1222 features
->computeDerivativeGroupLinear
= true;
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1226 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1227 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1228 features
->ycbcrImageArrays
= true;
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES
: {
1232 VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*features
=
1233 (VkPhysicalDeviceUniformBufferStandardLayoutFeatures
*)ext
;
1234 CORE_FEATURE(1, 2, uniformBufferStandardLayout
);
1237 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1238 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1239 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1240 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1243 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES
: {
1244 VkPhysicalDeviceImagelessFramebufferFeatures
*features
=
1245 (VkPhysicalDeviceImagelessFramebufferFeatures
*)ext
;
1246 CORE_FEATURE(1, 2, imagelessFramebuffer
);
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1250 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1251 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1252 features
->pipelineExecutableInfo
= true;
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1256 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1257 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1258 features
->shaderSubgroupClock
= true;
1259 features
->shaderDeviceClock
= pdevice
->rad_info
.chip_class
>= GFX8
;
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1263 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1264 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1265 features
->texelBufferAlignment
= true;
1268 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES
: {
1269 VkPhysicalDeviceTimelineSemaphoreFeatures
*features
=
1270 (VkPhysicalDeviceTimelineSemaphoreFeatures
*) ext
;
1271 CORE_FEATURE(1, 2, timelineSemaphore
);
1274 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT
: {
1275 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*features
=
1276 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT
*)ext
;
1277 features
->subgroupSizeControl
= true;
1278 features
->computeFullSubgroups
= true;
1281 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD
: {
1282 VkPhysicalDeviceCoherentMemoryFeaturesAMD
*features
=
1283 (VkPhysicalDeviceCoherentMemoryFeaturesAMD
*)ext
;
1284 features
->deviceCoherentMemory
= pdevice
->rad_info
.has_l2_uncached
;
1287 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES
: {
1288 VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*features
=
1289 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeatures
*)ext
;
1290 CORE_FEATURE(1, 2, shaderSubgroupExtendedTypes
);
1293 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SEPARATE_DEPTH_STENCIL_LAYOUTS_FEATURES_KHR
: {
1294 VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*features
=
1295 (VkPhysicalDeviceSeparateDepthStencilLayoutsFeaturesKHR
*)ext
;
1296 CORE_FEATURE(1, 2, separateDepthStencilLayouts
);
1299 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_FEATURES
: {
1300 radv_get_physical_device_features_1_1(pdevice
, (void *)ext
);
1303 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_FEATURES
: {
1304 radv_get_physical_device_features_1_2(pdevice
, (void *)ext
);
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_FEATURES_EXT
: {
1308 VkPhysicalDeviceLineRasterizationFeaturesEXT
*features
=
1309 (VkPhysicalDeviceLineRasterizationFeaturesEXT
*)ext
;
1310 features
->rectangularLines
= false;
1311 features
->bresenhamLines
= true;
1312 features
->smoothLines
= false;
1313 features
->stippledRectangularLines
= false;
1314 features
->stippledBresenhamLines
= true;
1315 features
->stippledSmoothLines
= false;
1318 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
1319 VkDeviceMemoryOverallocationCreateInfoAMD
*features
=
1320 (VkDeviceMemoryOverallocationCreateInfoAMD
*)ext
;
1321 features
->overallocationBehavior
= true;
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_FEATURES_EXT
: {
1325 VkPhysicalDeviceRobustness2FeaturesEXT
*features
=
1326 (VkPhysicalDeviceRobustness2FeaturesEXT
*)ext
;
1327 features
->robustBufferAccess2
= true;
1328 features
->robustImageAccess2
= true;
1329 features
->nullDescriptor
= true;
1332 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
1333 VkPhysicalDeviceCustomBorderColorFeaturesEXT
*features
=
1334 (VkPhysicalDeviceCustomBorderColorFeaturesEXT
*)ext
;
1335 features
->customBorderColors
= true;
1336 features
->customBorderColorWithoutFormat
= true;
1339 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PRIVATE_DATA_FEATURES_EXT
: {
1340 VkPhysicalDevicePrivateDataFeaturesEXT
*features
=
1341 (VkPhysicalDevicePrivateDataFeaturesEXT
*)ext
;
1342 features
->privateData
= true;
1345 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_CREATION_CACHE_CONTROL_FEATURES_EXT
: {
1346 VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*features
=
1347 (VkPhysicalDevicePipelineCreationCacheControlFeaturesEXT
*)ext
;
1348 features
-> pipelineCreationCacheControl
= true;
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTENDED_DYNAMIC_STATE_FEATURES_EXT
: {
1352 VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*features
=
1353 (VkPhysicalDeviceExtendedDynamicStateFeaturesEXT
*) ext
;
1354 features
->extendedDynamicState
= true;
1357 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGE_ROBUSTNESS_FEATURES_EXT
: {
1358 VkPhysicalDeviceImageRobustnessFeaturesEXT
*features
=
1359 (VkPhysicalDeviceImageRobustnessFeaturesEXT
*)ext
;
1360 features
->robustImageAccess
= true;
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_FLOAT_FEATURES_EXT
: {
1364 VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*features
=
1365 (VkPhysicalDeviceShaderAtomicFloatFeaturesEXT
*)ext
;
1366 features
->shaderBufferFloat32Atomics
= true;
1367 features
->shaderBufferFloat32AtomicAdd
= false;
1368 features
->shaderBufferFloat64Atomics
= true;
1369 features
->shaderBufferFloat64AtomicAdd
= false;
1370 features
->shaderSharedFloat32Atomics
= true;
1371 features
->shaderSharedFloat32AtomicAdd
= pdevice
->rad_info
.chip_class
>= GFX8
&&
1372 (!pdevice
->use_llvm
|| LLVM_VERSION_MAJOR
>= 10);
1373 features
->shaderSharedFloat64Atomics
= true;
1374 features
->shaderSharedFloat64AtomicAdd
= false;
1375 features
->shaderImageFloat32Atomics
= true;
1376 features
->shaderImageFloat32AtomicAdd
= false;
1377 features
->sparseImageFloat32Atomics
= false;
1378 features
->sparseImageFloat32AtomicAdd
= false;
1389 radv_max_descriptor_set_size()
1391 /* make sure that the entire descriptor set is addressable with a signed
1392 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1393 * be at most 2 GiB. the combined image & samples object count as one of
1394 * both. This limit is for the pipeline layout, not for the set layout, but
1395 * there is no set limit, so we just set a pipeline limit. I don't think
1396 * any app is going to hit this soon. */
1397 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1398 - MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1399 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1400 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1401 32 /* sampler, largest when combined with image */ +
1402 64 /* sampled image */ +
1403 64 /* storage image */);
1406 void radv_GetPhysicalDeviceProperties(
1407 VkPhysicalDevice physicalDevice
,
1408 VkPhysicalDeviceProperties
* pProperties
)
1410 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1411 VkSampleCountFlags sample_counts
= 0xf;
1413 size_t max_descriptor_set_size
= radv_max_descriptor_set_size();
1415 VkPhysicalDeviceLimits limits
= {
1416 .maxImageDimension1D
= (1 << 14),
1417 .maxImageDimension2D
= (1 << 14),
1418 .maxImageDimension3D
= (1 << 11),
1419 .maxImageDimensionCube
= (1 << 14),
1420 .maxImageArrayLayers
= (1 << 11),
1421 .maxTexelBufferElements
= UINT32_MAX
,
1422 .maxUniformBufferRange
= UINT32_MAX
,
1423 .maxStorageBufferRange
= UINT32_MAX
,
1424 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1425 .maxMemoryAllocationCount
= UINT32_MAX
,
1426 .maxSamplerAllocationCount
= 64 * 1024,
1427 .bufferImageGranularity
= 64, /* A cache line */
1428 .sparseAddressSpaceSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
, /* buffer max size */
1429 .maxBoundDescriptorSets
= MAX_SETS
,
1430 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1431 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1432 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1433 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1434 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1435 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1436 .maxPerStageResources
= max_descriptor_set_size
,
1437 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1438 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1439 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1440 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1441 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1442 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1443 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1444 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1445 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1446 .maxVertexInputBindings
= MAX_VBS
,
1447 .maxVertexInputAttributeOffset
= 2047,
1448 .maxVertexInputBindingStride
= 2048,
1449 .maxVertexOutputComponents
= 128,
1450 .maxTessellationGenerationLevel
= 64,
1451 .maxTessellationPatchSize
= 32,
1452 .maxTessellationControlPerVertexInputComponents
= 128,
1453 .maxTessellationControlPerVertexOutputComponents
= 128,
1454 .maxTessellationControlPerPatchOutputComponents
= 120,
1455 .maxTessellationControlTotalOutputComponents
= 4096,
1456 .maxTessellationEvaluationInputComponents
= 128,
1457 .maxTessellationEvaluationOutputComponents
= 128,
1458 .maxGeometryShaderInvocations
= 127,
1459 .maxGeometryInputComponents
= 64,
1460 .maxGeometryOutputComponents
= 128,
1461 .maxGeometryOutputVertices
= 256,
1462 .maxGeometryTotalOutputComponents
= 1024,
1463 .maxFragmentInputComponents
= 128,
1464 .maxFragmentOutputAttachments
= 8,
1465 .maxFragmentDualSrcAttachments
= 1,
1466 .maxFragmentCombinedOutputResources
= 8,
1467 .maxComputeSharedMemorySize
= 32768,
1468 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1469 .maxComputeWorkGroupInvocations
= 1024,
1470 .maxComputeWorkGroupSize
= {
1475 .subPixelPrecisionBits
= 8,
1476 .subTexelPrecisionBits
= 8,
1477 .mipmapPrecisionBits
= 8,
1478 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1479 .maxDrawIndirectCount
= UINT32_MAX
,
1480 .maxSamplerLodBias
= 16,
1481 .maxSamplerAnisotropy
= 16,
1482 .maxViewports
= MAX_VIEWPORTS
,
1483 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1484 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1485 .viewportSubPixelBits
= 8,
1486 .minMemoryMapAlignment
= 4096, /* A page */
1487 .minTexelBufferOffsetAlignment
= 4,
1488 .minUniformBufferOffsetAlignment
= 4,
1489 .minStorageBufferOffsetAlignment
= 4,
1490 .minTexelOffset
= -32,
1491 .maxTexelOffset
= 31,
1492 .minTexelGatherOffset
= -32,
1493 .maxTexelGatherOffset
= 31,
1494 .minInterpolationOffset
= -2,
1495 .maxInterpolationOffset
= 2,
1496 .subPixelInterpolationOffsetBits
= 8,
1497 .maxFramebufferWidth
= (1 << 14),
1498 .maxFramebufferHeight
= (1 << 14),
1499 .maxFramebufferLayers
= (1 << 10),
1500 .framebufferColorSampleCounts
= sample_counts
,
1501 .framebufferDepthSampleCounts
= sample_counts
,
1502 .framebufferStencilSampleCounts
= sample_counts
,
1503 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1504 .maxColorAttachments
= MAX_RTS
,
1505 .sampledImageColorSampleCounts
= sample_counts
,
1506 .sampledImageIntegerSampleCounts
= sample_counts
,
1507 .sampledImageDepthSampleCounts
= sample_counts
,
1508 .sampledImageStencilSampleCounts
= sample_counts
,
1509 .storageImageSampleCounts
= sample_counts
,
1510 .maxSampleMaskWords
= 1,
1511 .timestampComputeAndGraphics
= true,
1512 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1513 .maxClipDistances
= 8,
1514 .maxCullDistances
= 8,
1515 .maxCombinedClipAndCullDistances
= 8,
1516 .discreteQueuePriorities
= 2,
1517 .pointSizeRange
= { 0.0, 8191.875 },
1518 .lineWidthRange
= { 0.0, 8191.875 },
1519 .pointSizeGranularity
= (1.0 / 8.0),
1520 .lineWidthGranularity
= (1.0 / 8.0),
1521 .strictLines
= false, /* FINISHME */
1522 .standardSampleLocations
= true,
1523 .optimalBufferCopyOffsetAlignment
= 128,
1524 .optimalBufferCopyRowPitchAlignment
= 128,
1525 .nonCoherentAtomSize
= 64,
1528 *pProperties
= (VkPhysicalDeviceProperties
) {
1529 .apiVersion
= radv_physical_device_api_version(pdevice
),
1530 .driverVersion
= vk_get_driver_version(),
1531 .vendorID
= ATI_VENDOR_ID
,
1532 .deviceID
= pdevice
->rad_info
.pci_id
,
1533 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1535 .sparseProperties
= {0},
1538 strcpy(pProperties
->deviceName
, pdevice
->name
);
1539 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1543 radv_get_physical_device_properties_1_1(struct radv_physical_device
*pdevice
,
1544 VkPhysicalDeviceVulkan11Properties
*p
)
1546 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
);
1548 memcpy(p
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1549 memcpy(p
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1550 memset(p
->deviceLUID
, 0, VK_LUID_SIZE
);
1551 /* The LUID is for Windows. */
1552 p
->deviceLUIDValid
= false;
1553 p
->deviceNodeMask
= 0;
1555 p
->subgroupSize
= RADV_SUBGROUP_SIZE
;
1556 p
->subgroupSupportedStages
= VK_SHADER_STAGE_ALL_GRAPHICS
|
1557 VK_SHADER_STAGE_COMPUTE_BIT
;
1558 p
->subgroupSupportedOperations
= VK_SUBGROUP_FEATURE_BASIC_BIT
|
1559 VK_SUBGROUP_FEATURE_VOTE_BIT
|
1560 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1561 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1562 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1563 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1564 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1565 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1566 p
->subgroupQuadOperationsInAllStages
= true;
1568 p
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1569 p
->maxMultiviewViewCount
= MAX_VIEWS
;
1570 p
->maxMultiviewInstanceIndex
= INT_MAX
;
1571 p
->protectedNoFault
= false;
1572 p
->maxPerSetDescriptors
= RADV_MAX_PER_SET_DESCRIPTORS
;
1573 p
->maxMemoryAllocationSize
= RADV_MAX_MEMORY_ALLOCATION_SIZE
;
1577 radv_get_physical_device_properties_1_2(struct radv_physical_device
*pdevice
,
1578 VkPhysicalDeviceVulkan12Properties
*p
)
1580 assert(p
->sType
== VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
);
1582 p
->driverID
= VK_DRIVER_ID_MESA_RADV
;
1583 snprintf(p
->driverName
, VK_MAX_DRIVER_NAME_SIZE
, "radv");
1584 snprintf(p
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE
,
1585 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
" (%s)",
1586 radv_get_compiler_string(pdevice
));
1587 p
->conformanceVersion
= (VkConformanceVersion
) {
1594 /* On AMD hardware, denormals and rounding modes for fp16/fp64 are
1595 * controlled by the same config register.
1597 if (pdevice
->rad_info
.has_packed_math_16bit
) {
1598 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1599 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1601 p
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1602 p
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_ALL_KHR
;
1605 /* With LLVM, do not allow both preserving and flushing denorms because
1606 * different shaders in the same pipeline can have different settings and
1607 * this won't work for merged shaders. To make it work, this requires LLVM
1608 * support for changing the register. The same logic applies for the
1609 * rounding modes because they are configured with the same config
1612 p
->shaderDenormFlushToZeroFloat32
= true;
1613 p
->shaderDenormPreserveFloat32
= !pdevice
->use_llvm
;
1614 p
->shaderRoundingModeRTEFloat32
= true;
1615 p
->shaderRoundingModeRTZFloat32
= !pdevice
->use_llvm
;
1616 p
->shaderSignedZeroInfNanPreserveFloat32
= true;
1618 p
->shaderDenormFlushToZeroFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1619 p
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1620 p
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1621 p
->shaderRoundingModeRTZFloat16
= pdevice
->rad_info
.has_packed_math_16bit
&& !pdevice
->use_llvm
;
1622 p
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.has_packed_math_16bit
;
1624 p
->shaderDenormFlushToZeroFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1625 p
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1626 p
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1627 p
->shaderRoundingModeRTZFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_llvm
;
1628 p
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1630 p
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1631 p
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1632 p
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1633 p
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1634 p
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1635 p
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1636 p
->robustBufferAccessUpdateAfterBind
= false;
1637 p
->quadDivergentImplicitLod
= false;
1639 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1640 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1641 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1642 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1643 32 /* sampler, largest when combined with image */ +
1644 64 /* sampled image */ +
1645 64 /* storage image */);
1646 p
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1647 p
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1648 p
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1649 p
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1650 p
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1651 p
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1652 p
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1653 p
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1654 p
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1655 p
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1656 p
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1657 p
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1658 p
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1659 p
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1660 p
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1662 /* We support all of the depth resolve modes */
1663 p
->supportedDepthResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1664 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1665 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1666 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1668 /* Average doesn't make sense for stencil so we don't support that */
1669 p
->supportedStencilResolveModes
= VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1670 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1671 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1673 p
->independentResolveNone
= true;
1674 p
->independentResolve
= true;
1676 /* GFX6-8 only support single channel min/max filter. */
1677 p
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1678 p
->filterMinmaxSingleComponentFormats
= true;
1680 p
->maxTimelineSemaphoreValueDifference
= UINT64_MAX
;
1682 p
->framebufferIntegerColorSampleCounts
= VK_SAMPLE_COUNT_1_BIT
;
1685 void radv_GetPhysicalDeviceProperties2(
1686 VkPhysicalDevice physicalDevice
,
1687 VkPhysicalDeviceProperties2
*pProperties
)
1689 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1690 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1692 VkPhysicalDeviceVulkan11Properties core_1_1
= {
1693 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
,
1695 radv_get_physical_device_properties_1_1(pdevice
, &core_1_1
);
1697 VkPhysicalDeviceVulkan12Properties core_1_2
= {
1698 .sType
= VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
,
1700 radv_get_physical_device_properties_1_2(pdevice
, &core_1_2
);
1702 #define CORE_RENAMED_PROPERTY(major, minor, ext_property, core_property) \
1703 memcpy(&properties->ext_property, &core_##major##_##minor.core_property, \
1704 sizeof(core_##major##_##minor.core_property))
1706 #define CORE_PROPERTY(major, minor, property) \
1707 CORE_RENAMED_PROPERTY(major, minor, property, property)
1709 vk_foreach_struct(ext
, pProperties
->pNext
) {
1710 switch (ext
->sType
) {
1711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1712 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1713 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1714 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1718 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1719 CORE_PROPERTY(1, 1, deviceUUID
);
1720 CORE_PROPERTY(1, 1, driverUUID
);
1721 CORE_PROPERTY(1, 1, deviceLUID
);
1722 CORE_PROPERTY(1, 1, deviceLUIDValid
);
1725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1726 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1727 CORE_PROPERTY(1, 1, maxMultiviewViewCount
);
1728 CORE_PROPERTY(1, 1, maxMultiviewInstanceIndex
);
1731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1732 VkPhysicalDevicePointClippingProperties
*properties
=
1733 (VkPhysicalDevicePointClippingProperties
*)ext
;
1734 CORE_PROPERTY(1, 1, pointClippingBehavior
);
1737 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1738 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1739 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1740 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1743 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1744 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1745 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1746 properties
->minImportedHostPointerAlignment
= 4096;
1749 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1750 VkPhysicalDeviceSubgroupProperties
*properties
=
1751 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1752 CORE_PROPERTY(1, 1, subgroupSize
);
1753 CORE_RENAMED_PROPERTY(1, 1, supportedStages
,
1754 subgroupSupportedStages
);
1755 CORE_RENAMED_PROPERTY(1, 1, supportedOperations
,
1756 subgroupSupportedOperations
);
1757 CORE_RENAMED_PROPERTY(1, 1, quadOperationsInAllStages
,
1758 subgroupQuadOperationsInAllStages
);
1761 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1762 VkPhysicalDeviceMaintenance3Properties
*properties
=
1763 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1764 CORE_PROPERTY(1, 1, maxPerSetDescriptors
);
1765 CORE_PROPERTY(1, 1, maxMemoryAllocationSize
);
1768 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES
: {
1769 VkPhysicalDeviceSamplerFilterMinmaxProperties
*properties
=
1770 (VkPhysicalDeviceSamplerFilterMinmaxProperties
*)ext
;
1771 CORE_PROPERTY(1, 2, filterMinmaxImageComponentMapping
);
1772 CORE_PROPERTY(1, 2, filterMinmaxSingleComponentFormats
);
1775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1776 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1777 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1779 /* Shader engines. */
1780 properties
->shaderEngineCount
=
1781 pdevice
->rad_info
.max_se
;
1782 properties
->shaderArraysPerEngineCount
=
1783 pdevice
->rad_info
.max_sh_per_se
;
1784 properties
->computeUnitsPerShaderArray
=
1785 pdevice
->rad_info
.min_good_cu_per_sa
;
1786 properties
->simdPerComputeUnit
=
1787 pdevice
->rad_info
.num_simd_per_compute_unit
;
1788 properties
->wavefrontsPerSimd
=
1789 pdevice
->rad_info
.max_wave64_per_simd
;
1790 properties
->wavefrontSize
= 64;
1793 properties
->sgprsPerSimd
=
1794 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1795 properties
->minSgprAllocation
=
1796 pdevice
->rad_info
.min_sgpr_alloc
;
1797 properties
->maxSgprAllocation
=
1798 pdevice
->rad_info
.max_sgpr_alloc
;
1799 properties
->sgprAllocationGranularity
=
1800 pdevice
->rad_info
.sgpr_alloc_granularity
;
1803 properties
->vgprsPerSimd
=
1804 pdevice
->rad_info
.num_physical_wave64_vgprs_per_simd
;
1805 properties
->minVgprAllocation
=
1806 pdevice
->rad_info
.min_wave64_vgpr_alloc
;
1807 properties
->maxVgprAllocation
=
1808 pdevice
->rad_info
.max_vgpr_alloc
;
1809 properties
->vgprAllocationGranularity
=
1810 pdevice
->rad_info
.wave64_vgpr_alloc_granularity
;
1813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1814 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1815 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1817 properties
->shaderCoreFeatures
= 0;
1818 properties
->activeComputeUnitCount
=
1819 pdevice
->rad_info
.num_good_compute_units
;
1822 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1823 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1824 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1825 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1828 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES
: {
1829 VkPhysicalDeviceDescriptorIndexingProperties
*properties
=
1830 (VkPhysicalDeviceDescriptorIndexingProperties
*)ext
;
1831 CORE_PROPERTY(1, 2, maxUpdateAfterBindDescriptorsInAllPools
);
1832 CORE_PROPERTY(1, 2, shaderUniformBufferArrayNonUniformIndexingNative
);
1833 CORE_PROPERTY(1, 2, shaderSampledImageArrayNonUniformIndexingNative
);
1834 CORE_PROPERTY(1, 2, shaderStorageBufferArrayNonUniformIndexingNative
);
1835 CORE_PROPERTY(1, 2, shaderStorageImageArrayNonUniformIndexingNative
);
1836 CORE_PROPERTY(1, 2, shaderInputAttachmentArrayNonUniformIndexingNative
);
1837 CORE_PROPERTY(1, 2, robustBufferAccessUpdateAfterBind
);
1838 CORE_PROPERTY(1, 2, quadDivergentImplicitLod
);
1839 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSamplers
);
1840 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindUniformBuffers
);
1841 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageBuffers
);
1842 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindSampledImages
);
1843 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindStorageImages
);
1844 CORE_PROPERTY(1, 2, maxPerStageDescriptorUpdateAfterBindInputAttachments
);
1845 CORE_PROPERTY(1, 2, maxPerStageUpdateAfterBindResources
);
1846 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSamplers
);
1847 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffers
);
1848 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
);
1849 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffers
);
1850 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
);
1851 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindSampledImages
);
1852 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindStorageImages
);
1853 CORE_PROPERTY(1, 2, maxDescriptorSetUpdateAfterBindInputAttachments
);
1856 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1857 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1858 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1859 CORE_PROPERTY(1, 1, protectedNoFault
);
1862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1863 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1864 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1865 properties
->primitiveOverestimationSize
= 0;
1866 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1867 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1868 properties
->primitiveUnderestimation
= false;
1869 properties
->conservativePointAndLineRasterization
= false;
1870 properties
->degenerateTrianglesRasterized
= false;
1871 properties
->degenerateLinesRasterized
= false;
1872 properties
->fullyCoveredFragmentShaderInputVariable
= false;
1873 properties
->conservativeRasterizationPostDepthCoverage
= false;
1876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1877 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1878 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1879 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1880 properties
->pciBus
= pdevice
->bus_info
.bus
;
1881 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1882 properties
->pciFunction
= pdevice
->bus_info
.func
;
1885 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES
: {
1886 VkPhysicalDeviceDriverProperties
*properties
=
1887 (VkPhysicalDeviceDriverProperties
*) ext
;
1888 CORE_PROPERTY(1, 2, driverID
);
1889 CORE_PROPERTY(1, 2, driverName
);
1890 CORE_PROPERTY(1, 2, driverInfo
);
1891 CORE_PROPERTY(1, 2, conformanceVersion
);
1894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1895 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1896 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1897 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1898 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1899 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1900 properties
->maxTransformFeedbackStreamDataSize
= 512;
1901 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1902 properties
->maxTransformFeedbackBufferDataStride
= 512;
1903 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1904 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1905 properties
->transformFeedbackRasterizationStreamSelect
= false;
1906 properties
->transformFeedbackDraw
= true;
1909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1910 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1911 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1913 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1914 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1915 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1916 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1917 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1921 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1922 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1923 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1924 VK_SAMPLE_COUNT_4_BIT
|
1925 VK_SAMPLE_COUNT_8_BIT
;
1926 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1927 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1928 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1929 properties
->sampleLocationSubPixelBits
= 4;
1930 properties
->variableSampleLocations
= false;
1933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES
: {
1934 VkPhysicalDeviceDepthStencilResolveProperties
*properties
=
1935 (VkPhysicalDeviceDepthStencilResolveProperties
*)ext
;
1936 CORE_PROPERTY(1, 2, supportedDepthResolveModes
);
1937 CORE_PROPERTY(1, 2, supportedStencilResolveModes
);
1938 CORE_PROPERTY(1, 2, independentResolveNone
);
1939 CORE_PROPERTY(1, 2, independentResolve
);
1942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1943 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1944 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1945 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1946 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1947 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1948 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES
: {
1952 VkPhysicalDeviceFloatControlsProperties
*properties
=
1953 (VkPhysicalDeviceFloatControlsProperties
*)ext
;
1954 CORE_PROPERTY(1, 2, denormBehaviorIndependence
);
1955 CORE_PROPERTY(1, 2, roundingModeIndependence
);
1956 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat16
);
1957 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat16
);
1958 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat16
);
1959 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat16
);
1960 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat16
);
1961 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat32
);
1962 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat32
);
1963 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat32
);
1964 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat32
);
1965 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat32
);
1966 CORE_PROPERTY(1, 2, shaderDenormFlushToZeroFloat64
);
1967 CORE_PROPERTY(1, 2, shaderDenormPreserveFloat64
);
1968 CORE_PROPERTY(1, 2, shaderRoundingModeRTEFloat64
);
1969 CORE_PROPERTY(1, 2, shaderRoundingModeRTZFloat64
);
1970 CORE_PROPERTY(1, 2, shaderSignedZeroInfNanPreserveFloat64
);
1973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES
: {
1974 VkPhysicalDeviceTimelineSemaphoreProperties
*properties
=
1975 (VkPhysicalDeviceTimelineSemaphoreProperties
*) ext
;
1976 CORE_PROPERTY(1, 2, maxTimelineSemaphoreValueDifference
);
1979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT
: {
1980 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*props
=
1981 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT
*)ext
;
1982 props
->minSubgroupSize
= 64;
1983 props
->maxSubgroupSize
= 64;
1984 props
->maxComputeWorkgroupSubgroups
= UINT32_MAX
;
1985 props
->requiredSubgroupSizeStages
= 0;
1987 if (pdevice
->rad_info
.chip_class
>= GFX10
) {
1988 /* Only GFX10+ supports wave32. */
1989 props
->minSubgroupSize
= 32;
1990 props
->requiredSubgroupSizeStages
= VK_SHADER_STAGE_COMPUTE_BIT
;
1994 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_1_PROPERTIES
:
1995 radv_get_physical_device_properties_1_1(pdevice
, (void *)ext
);
1997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VULKAN_1_2_PROPERTIES
:
1998 radv_get_physical_device_properties_1_2(pdevice
, (void *)ext
);
2000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_LINE_RASTERIZATION_PROPERTIES_EXT
: {
2001 VkPhysicalDeviceLineRasterizationPropertiesEXT
*props
=
2002 (VkPhysicalDeviceLineRasterizationPropertiesEXT
*)ext
;
2003 props
->lineSubPixelPrecisionBits
= 4;
2006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ROBUSTNESS_2_PROPERTIES_EXT
: {
2007 VkPhysicalDeviceRobustness2PropertiesEXT
*properties
=
2008 (VkPhysicalDeviceRobustness2PropertiesEXT
*)ext
;
2009 properties
->robustStorageBufferAccessSizeAlignment
= 4;
2010 properties
->robustUniformBufferAccessSizeAlignment
= 4;
2013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_PROPERTIES_EXT
: {
2014 VkPhysicalDeviceCustomBorderColorPropertiesEXT
*props
=
2015 (VkPhysicalDeviceCustomBorderColorPropertiesEXT
*)ext
;
2016 props
->maxCustomBorderColorSamplers
= RADV_BORDER_COLOR_COUNT
;
2025 static void radv_get_physical_device_queue_family_properties(
2026 struct radv_physical_device
* pdevice
,
2028 VkQueueFamilyProperties
** pQueueFamilyProperties
)
2030 int num_queue_families
= 1;
2032 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2033 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
2034 num_queue_families
++;
2036 if (pQueueFamilyProperties
== NULL
) {
2037 *pCount
= num_queue_families
;
2046 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2047 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
2048 VK_QUEUE_COMPUTE_BIT
|
2049 VK_QUEUE_TRANSFER_BIT
|
2050 VK_QUEUE_SPARSE_BINDING_BIT
,
2052 .timestampValidBits
= 64,
2053 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2058 if (pdevice
->rad_info
.num_rings
[RING_COMPUTE
] > 0 &&
2059 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
2060 if (*pCount
> idx
) {
2061 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
2062 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
2063 VK_QUEUE_TRANSFER_BIT
|
2064 VK_QUEUE_SPARSE_BINDING_BIT
,
2065 .queueCount
= pdevice
->rad_info
.num_rings
[RING_COMPUTE
],
2066 .timestampValidBits
= 64,
2067 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
2075 void radv_GetPhysicalDeviceQueueFamilyProperties(
2076 VkPhysicalDevice physicalDevice
,
2078 VkQueueFamilyProperties
* pQueueFamilyProperties
)
2080 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2081 if (!pQueueFamilyProperties
) {
2082 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2085 VkQueueFamilyProperties
*properties
[] = {
2086 pQueueFamilyProperties
+ 0,
2087 pQueueFamilyProperties
+ 1,
2088 pQueueFamilyProperties
+ 2,
2090 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2091 assert(*pCount
<= 3);
2094 void radv_GetPhysicalDeviceQueueFamilyProperties2(
2095 VkPhysicalDevice physicalDevice
,
2097 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
2099 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
2100 if (!pQueueFamilyProperties
) {
2101 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
2104 VkQueueFamilyProperties
*properties
[] = {
2105 &pQueueFamilyProperties
[0].queueFamilyProperties
,
2106 &pQueueFamilyProperties
[1].queueFamilyProperties
,
2107 &pQueueFamilyProperties
[2].queueFamilyProperties
,
2109 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
2110 assert(*pCount
<= 3);
2113 void radv_GetPhysicalDeviceMemoryProperties(
2114 VkPhysicalDevice physicalDevice
,
2115 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
2117 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2119 *pMemoryProperties
= physical_device
->memory_properties
;
2123 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
2124 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
2126 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2127 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
2128 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
2129 uint64_t vram_size
= radv_get_vram_size(device
);
2130 uint64_t gtt_size
= device
->rad_info
.gart_size
;
2131 uint64_t heap_budget
, heap_usage
;
2133 /* For all memory heaps, the computation of budget is as follow:
2134 * heap_budget = heap_size - global_heap_usage + app_heap_usage
2136 * The Vulkan spec 1.1.97 says that the budget should include any
2137 * currently allocated device memory.
2139 * Note that the application heap usages are not really accurate (eg.
2140 * in presence of shared buffers).
2142 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
2143 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
2145 if ((device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) && (device
->memory_flags
[i
] & RADEON_FLAG_NO_CPU_ACCESS
)) {
2146 heap_usage
= device
->ws
->query_value(device
->ws
,
2147 RADEON_ALLOCATED_VRAM
);
2149 heap_budget
= vram_size
-
2150 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
2153 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2154 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2155 } else if (device
->memory_domains
[i
] & RADEON_DOMAIN_VRAM
) {
2156 heap_usage
= device
->ws
->query_value(device
->ws
,
2157 RADEON_ALLOCATED_VRAM_VIS
);
2159 heap_budget
= visible_vram_size
-
2160 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
2163 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2164 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2166 assert(device
->memory_domains
[i
] & RADEON_DOMAIN_GTT
);
2168 heap_usage
= device
->ws
->query_value(device
->ws
,
2169 RADEON_ALLOCATED_GTT
);
2171 heap_budget
= gtt_size
-
2172 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
2175 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
2176 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
2180 /* The heapBudget and heapUsage values must be zero for array elements
2181 * greater than or equal to
2182 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
2184 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
2185 memoryBudget
->heapBudget
[i
] = 0;
2186 memoryBudget
->heapUsage
[i
] = 0;
2190 void radv_GetPhysicalDeviceMemoryProperties2(
2191 VkPhysicalDevice physicalDevice
,
2192 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
2194 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
2195 &pMemoryProperties
->memoryProperties
);
2197 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
2198 vk_find_struct(pMemoryProperties
->pNext
,
2199 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
2201 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
2204 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
2206 VkExternalMemoryHandleTypeFlagBits handleType
,
2207 const void *pHostPointer
,
2208 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
2210 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2214 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
2215 const struct radv_physical_device
*physical_device
= device
->physical_device
;
2216 uint32_t memoryTypeBits
= 0;
2217 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
2218 if (physical_device
->memory_domains
[i
] == RADEON_DOMAIN_GTT
&&
2219 !(physical_device
->memory_flags
[i
] & RADEON_FLAG_GTT_WC
)) {
2220 memoryTypeBits
= (1 << i
);
2224 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
2228 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
2232 static enum radeon_ctx_priority
2233 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
2235 /* Default to MEDIUM when a specific global priority isn't requested */
2237 return RADEON_CTX_PRIORITY_MEDIUM
;
2239 switch(pObj
->globalPriority
) {
2240 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
2241 return RADEON_CTX_PRIORITY_REALTIME
;
2242 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
2243 return RADEON_CTX_PRIORITY_HIGH
;
2244 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
2245 return RADEON_CTX_PRIORITY_MEDIUM
;
2246 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
2247 return RADEON_CTX_PRIORITY_LOW
;
2249 unreachable("Illegal global priority value");
2250 return RADEON_CTX_PRIORITY_INVALID
;
2255 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
2256 uint32_t queue_family_index
, int idx
,
2257 VkDeviceQueueCreateFlags flags
,
2258 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
2260 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2261 queue
->device
= device
;
2262 queue
->queue_family_index
= queue_family_index
;
2263 queue
->queue_idx
= idx
;
2264 queue
->priority
= radv_get_queue_global_priority(global_priority
);
2265 queue
->flags
= flags
;
2266 queue
->hw_ctx
= NULL
;
2268 VkResult result
= device
->ws
->ctx_create(device
->ws
, queue
->priority
, &queue
->hw_ctx
);
2269 if (result
!= VK_SUCCESS
)
2270 return vk_error(device
->instance
, result
);
2272 list_inithead(&queue
->pending_submissions
);
2273 pthread_mutex_init(&queue
->pending_mutex
, NULL
);
2275 pthread_mutex_init(&queue
->thread_mutex
, NULL
);
2276 queue
->thread_submission
= NULL
;
2277 queue
->thread_running
= queue
->thread_exit
= false;
2278 result
= radv_create_pthread_cond(&queue
->thread_cond
);
2279 if (result
!= VK_SUCCESS
)
2280 return vk_error(device
->instance
, result
);
2286 radv_queue_finish(struct radv_queue
*queue
)
2288 if (queue
->thread_running
) {
2289 p_atomic_set(&queue
->thread_exit
, true);
2290 pthread_cond_broadcast(&queue
->thread_cond
);
2291 pthread_join(queue
->submission_thread
, NULL
);
2293 pthread_cond_destroy(&queue
->thread_cond
);
2294 pthread_mutex_destroy(&queue
->pending_mutex
);
2295 pthread_mutex_destroy(&queue
->thread_mutex
);
2298 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
2300 if (queue
->initial_full_flush_preamble_cs
)
2301 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2302 if (queue
->initial_preamble_cs
)
2303 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2304 if (queue
->continue_preamble_cs
)
2305 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2306 if (queue
->descriptor_bo
)
2307 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2308 if (queue
->scratch_bo
)
2309 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2310 if (queue
->esgs_ring_bo
)
2311 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2312 if (queue
->gsvs_ring_bo
)
2313 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2314 if (queue
->tess_rings_bo
)
2315 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
2317 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
2318 if (queue
->gds_oa_bo
)
2319 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
2320 if (queue
->compute_scratch_bo
)
2321 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2325 radv_bo_list_init(struct radv_bo_list
*bo_list
)
2327 pthread_mutex_init(&bo_list
->mutex
, NULL
);
2328 bo_list
->list
.count
= bo_list
->capacity
= 0;
2329 bo_list
->list
.bos
= NULL
;
2333 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
2335 free(bo_list
->list
.bos
);
2336 pthread_mutex_destroy(&bo_list
->mutex
);
2339 VkResult
radv_bo_list_add(struct radv_device
*device
,
2340 struct radeon_winsys_bo
*bo
)
2342 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2347 if (unlikely(!device
->use_global_bo_list
))
2350 pthread_mutex_lock(&bo_list
->mutex
);
2351 if (bo_list
->list
.count
== bo_list
->capacity
) {
2352 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
2353 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
2356 pthread_mutex_unlock(&bo_list
->mutex
);
2357 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2360 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
2361 bo_list
->capacity
= capacity
;
2364 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
2365 pthread_mutex_unlock(&bo_list
->mutex
);
2369 void radv_bo_list_remove(struct radv_device
*device
,
2370 struct radeon_winsys_bo
*bo
)
2372 struct radv_bo_list
*bo_list
= &device
->bo_list
;
2377 if (unlikely(!device
->use_global_bo_list
))
2380 pthread_mutex_lock(&bo_list
->mutex
);
2381 /* Loop the list backwards so we find the most recently added
2383 for(unsigned i
= bo_list
->list
.count
; i
-- > 0;) {
2384 if (bo_list
->list
.bos
[i
] == bo
) {
2385 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
2386 --bo_list
->list
.count
;
2390 pthread_mutex_unlock(&bo_list
->mutex
);
2394 radv_device_init_gs_info(struct radv_device
*device
)
2396 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
2397 device
->physical_device
->rad_info
.family
);
2400 static int radv_get_device_extension_index(const char *name
)
2402 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
2403 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
2410 radv_get_int_debug_option(const char *name
, int default_value
)
2417 result
= default_value
;
2421 result
= strtol(str
, &endptr
, 0);
2422 if (str
== endptr
) {
2423 /* No digits founs. */
2424 result
= default_value
;
2432 radv_device_init_dispatch(struct radv_device
*device
)
2434 const struct radv_instance
*instance
= device
->physical_device
->instance
;
2435 const struct radv_device_dispatch_table
*dispatch_table_layer
= NULL
;
2436 bool unchecked
= instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
;
2437 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2439 if (radv_thread_trace
>= 0) {
2440 /* Use device entrypoints from the SQTT layer if enabled. */
2441 dispatch_table_layer
= &sqtt_device_dispatch_table
;
2444 for (unsigned i
= 0; i
< ARRAY_SIZE(device
->dispatch
.entrypoints
); i
++) {
2445 /* Vulkan requires that entrypoints for extensions which have not been
2446 * enabled must not be advertised.
2449 !radv_device_entrypoint_is_enabled(i
, instance
->apiVersion
,
2450 &instance
->enabled_extensions
,
2451 &device
->enabled_extensions
)) {
2452 device
->dispatch
.entrypoints
[i
] = NULL
;
2453 } else if (dispatch_table_layer
&&
2454 dispatch_table_layer
->entrypoints
[i
]) {
2455 device
->dispatch
.entrypoints
[i
] =
2456 dispatch_table_layer
->entrypoints
[i
];
2458 device
->dispatch
.entrypoints
[i
] =
2459 radv_device_dispatch_table
.entrypoints
[i
];
2465 radv_create_pthread_cond(pthread_cond_t
*cond
)
2467 pthread_condattr_t condattr
;
2468 if (pthread_condattr_init(&condattr
)) {
2469 return VK_ERROR_INITIALIZATION_FAILED
;
2472 if (pthread_condattr_setclock(&condattr
, CLOCK_MONOTONIC
)) {
2473 pthread_condattr_destroy(&condattr
);
2474 return VK_ERROR_INITIALIZATION_FAILED
;
2476 if (pthread_cond_init(cond
, &condattr
)) {
2477 pthread_condattr_destroy(&condattr
);
2478 return VK_ERROR_INITIALIZATION_FAILED
;
2480 pthread_condattr_destroy(&condattr
);
2485 check_physical_device_features(VkPhysicalDevice physicalDevice
,
2486 const VkPhysicalDeviceFeatures
*features
)
2488 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2489 VkPhysicalDeviceFeatures supported_features
;
2490 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2491 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2492 VkBool32
*enabled_feature
= (VkBool32
*)features
;
2493 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2494 for (uint32_t i
= 0; i
< num_features
; i
++) {
2495 if (enabled_feature
[i
] && !supported_feature
[i
])
2496 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2502 static VkResult
radv_device_init_border_color(struct radv_device
*device
)
2504 device
->border_color_data
.bo
=
2505 device
->ws
->buffer_create(device
->ws
,
2506 RADV_BORDER_COLOR_BUFFER_SIZE
,
2509 RADEON_FLAG_CPU_ACCESS
|
2510 RADEON_FLAG_READ_ONLY
|
2511 RADEON_FLAG_NO_INTERPROCESS_SHARING
,
2512 RADV_BO_PRIORITY_SHADER
);
2514 if (device
->border_color_data
.bo
== NULL
)
2515 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2517 device
->border_color_data
.colors_gpu_ptr
=
2518 device
->ws
->buffer_map(device
->border_color_data
.bo
);
2519 if (!device
->border_color_data
.colors_gpu_ptr
)
2520 return vk_error(device
->physical_device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2521 pthread_mutex_init(&device
->border_color_data
.mutex
, NULL
);
2526 static void radv_device_finish_border_color(struct radv_device
*device
)
2528 if (device
->border_color_data
.bo
) {
2529 device
->ws
->buffer_destroy(device
->border_color_data
.bo
);
2531 pthread_mutex_destroy(&device
->border_color_data
.mutex
);
2535 VkResult
radv_CreateDevice(
2536 VkPhysicalDevice physicalDevice
,
2537 const VkDeviceCreateInfo
* pCreateInfo
,
2538 const VkAllocationCallbacks
* pAllocator
,
2541 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2543 struct radv_device
*device
;
2545 bool keep_shader_info
= false;
2546 bool robust_buffer_access
= false;
2547 bool overallocation_disallowed
= false;
2548 bool custom_border_colors
= false;
2550 /* Check enabled features */
2551 if (pCreateInfo
->pEnabledFeatures
) {
2552 result
= check_physical_device_features(physicalDevice
,
2553 pCreateInfo
->pEnabledFeatures
);
2554 if (result
!= VK_SUCCESS
)
2557 if (pCreateInfo
->pEnabledFeatures
->robustBufferAccess
)
2558 robust_buffer_access
= true;
2561 vk_foreach_struct_const(ext
, pCreateInfo
->pNext
) {
2562 switch (ext
->sType
) {
2563 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FEATURES_2
: {
2564 const VkPhysicalDeviceFeatures2
*features
= (const void *)ext
;
2565 result
= check_physical_device_features(physicalDevice
,
2566 &features
->features
);
2567 if (result
!= VK_SUCCESS
)
2570 if (features
->features
.robustBufferAccess
)
2571 robust_buffer_access
= true;
2574 case VK_STRUCTURE_TYPE_DEVICE_MEMORY_OVERALLOCATION_CREATE_INFO_AMD
: {
2575 const VkDeviceMemoryOverallocationCreateInfoAMD
*overallocation
= (const void *)ext
;
2576 if (overallocation
->overallocationBehavior
== VK_MEMORY_OVERALLOCATION_BEHAVIOR_DISALLOWED_AMD
)
2577 overallocation_disallowed
= true;
2580 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CUSTOM_BORDER_COLOR_FEATURES_EXT
: {
2581 const VkPhysicalDeviceCustomBorderColorFeaturesEXT
*border_color_features
= (const void *)ext
;
2582 custom_border_colors
= border_color_features
->customBorderColors
;
2590 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2592 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2594 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2596 vk_device_init(&device
->vk
, pCreateInfo
,
2597 &physical_device
->instance
->alloc
, pAllocator
);
2599 device
->instance
= physical_device
->instance
;
2600 device
->physical_device
= physical_device
;
2602 device
->ws
= physical_device
->ws
;
2604 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2605 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2606 int index
= radv_get_device_extension_index(ext_name
);
2607 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2608 vk_free(&device
->vk
.alloc
, device
);
2609 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2612 device
->enabled_extensions
.extensions
[index
] = true;
2615 radv_device_init_dispatch(device
);
2617 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2619 /* With update after bind we can't attach bo's to the command buffer
2620 * from the descriptor set anymore, so we have to use a global BO list.
2622 device
->use_global_bo_list
=
2623 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2624 device
->enabled_extensions
.EXT_descriptor_indexing
||
2625 device
->enabled_extensions
.EXT_buffer_device_address
||
2626 device
->enabled_extensions
.KHR_buffer_device_address
;
2628 device
->robust_buffer_access
= robust_buffer_access
;
2630 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2631 list_inithead(&device
->shader_slabs
);
2633 device
->overallocation_disallowed
= overallocation_disallowed
;
2634 mtx_init(&device
->overallocation_mutex
, mtx_plain
);
2636 radv_bo_list_init(&device
->bo_list
);
2638 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2639 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2640 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2641 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2642 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2644 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2646 device
->queues
[qfi
] = vk_alloc(&device
->vk
.alloc
,
2647 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2648 if (!device
->queues
[qfi
]) {
2649 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2653 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2655 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2657 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2658 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2659 qfi
, q
, queue_create
->flags
,
2661 if (result
!= VK_SUCCESS
)
2666 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2667 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2669 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2670 device
->dfsm_allowed
= device
->pbb_allowed
&&
2671 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2673 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2675 /* The maximum number of scratch waves. Scratch space isn't divided
2676 * evenly between CUs. The number is only a function of the number of CUs.
2677 * We can decrease the constant to decrease the scratch buffer size.
2679 * sctx->scratch_waves must be >= the maximum possible size of
2680 * 1 threadgroup, so that the hw doesn't hang from being unable
2683 * The recommended value is 4 per CU at most. Higher numbers don't
2684 * bring much benefit, but they still occupy chip resources (think
2685 * async compute). I've seen ~2% performance difference between 4 and 32.
2687 uint32_t max_threads_per_block
= 2048;
2688 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2689 max_threads_per_block
/ 64);
2691 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
2693 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2694 /* If the KMD allows it (there is a KMD hw register for it),
2695 * allow launching waves out-of-order.
2697 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2700 radv_device_init_gs_info(device
);
2702 device
->tess_offchip_block_dw_size
=
2703 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2705 if (getenv("RADV_TRACE_FILE")) {
2706 const char *filename
= getenv("RADV_TRACE_FILE");
2708 keep_shader_info
= true;
2710 if (!radv_init_trace(device
))
2713 fprintf(stderr
, "*****************************************************************************\n");
2714 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2715 fprintf(stderr
, "*****************************************************************************\n");
2717 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2718 radv_dump_enabled_options(device
, stderr
);
2721 int radv_thread_trace
= radv_get_int_debug_option("RADV_THREAD_TRACE", -1);
2722 if (radv_thread_trace
>= 0) {
2723 fprintf(stderr
, "*************************************************\n");
2724 fprintf(stderr
, "* WARNING: Thread trace support is experimental *\n");
2725 fprintf(stderr
, "*************************************************\n");
2727 if (device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2728 fprintf(stderr
, "GPU hardware not supported: refer to "
2729 "the RGP documentation for the list of "
2730 "supported GPUs!\n");
2734 /* Default buffer size set to 1MB per SE. */
2735 device
->thread_trace_buffer_size
=
2736 radv_get_int_debug_option("RADV_THREAD_TRACE_BUFFER_SIZE", 1024 * 1024);
2737 device
->thread_trace_start_frame
= radv_thread_trace
;
2739 if (!radv_thread_trace_init(device
))
2743 device
->keep_shader_info
= keep_shader_info
;
2744 result
= radv_device_init_meta(device
);
2745 if (result
!= VK_SUCCESS
)
2748 radv_device_init_msaa(device
);
2750 /* If the border color extension is enabled, let's create the buffer we need. */
2751 if (custom_border_colors
) {
2752 result
= radv_device_init_border_color(device
);
2753 if (result
!= VK_SUCCESS
)
2757 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2758 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2759 if (!device
->empty_cs
[family
])
2763 case RADV_QUEUE_GENERAL
:
2764 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2765 radeon_emit(device
->empty_cs
[family
], CC0_UPDATE_LOAD_ENABLES(1));
2766 radeon_emit(device
->empty_cs
[family
], CC1_UPDATE_SHADOW_ENABLES(1));
2768 case RADV_QUEUE_COMPUTE
:
2769 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2770 radeon_emit(device
->empty_cs
[family
], 0);
2774 result
= device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2775 if (result
!= VK_SUCCESS
)
2779 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2780 cik_create_gfx_config(device
);
2782 VkPipelineCacheCreateInfo ci
;
2783 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2786 ci
.pInitialData
= NULL
;
2787 ci
.initialDataSize
= 0;
2789 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2791 if (result
!= VK_SUCCESS
)
2794 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2796 result
= radv_create_pthread_cond(&device
->timeline_cond
);
2797 if (result
!= VK_SUCCESS
)
2798 goto fail_mem_cache
;
2800 device
->force_aniso
=
2801 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2802 if (device
->force_aniso
>= 0) {
2803 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2804 1 << util_logbase2(device
->force_aniso
));
2807 *pDevice
= radv_device_to_handle(device
);
2811 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2813 radv_device_finish_meta(device
);
2815 radv_bo_list_finish(&device
->bo_list
);
2817 radv_thread_trace_finish(device
);
2819 if (device
->trace_bo
)
2820 device
->ws
->buffer_destroy(device
->trace_bo
);
2822 if (device
->gfx_init
)
2823 device
->ws
->buffer_destroy(device
->gfx_init
);
2825 radv_device_finish_border_color(device
);
2827 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2828 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2829 radv_queue_finish(&device
->queues
[i
][q
]);
2830 if (device
->queue_count
[i
])
2831 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2834 vk_free(&device
->vk
.alloc
, device
);
2838 void radv_DestroyDevice(
2840 const VkAllocationCallbacks
* pAllocator
)
2842 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2847 if (device
->trace_bo
)
2848 device
->ws
->buffer_destroy(device
->trace_bo
);
2850 if (device
->gfx_init
)
2851 device
->ws
->buffer_destroy(device
->gfx_init
);
2853 radv_device_finish_border_color(device
);
2855 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2856 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2857 radv_queue_finish(&device
->queues
[i
][q
]);
2858 if (device
->queue_count
[i
])
2859 vk_free(&device
->vk
.alloc
, device
->queues
[i
]);
2860 if (device
->empty_cs
[i
])
2861 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2863 radv_device_finish_meta(device
);
2865 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2866 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2868 radv_destroy_shader_slabs(device
);
2870 pthread_cond_destroy(&device
->timeline_cond
);
2871 radv_bo_list_finish(&device
->bo_list
);
2873 radv_thread_trace_finish(device
);
2875 vk_free(&device
->vk
.alloc
, device
);
2878 VkResult
radv_EnumerateInstanceLayerProperties(
2879 uint32_t* pPropertyCount
,
2880 VkLayerProperties
* pProperties
)
2882 if (pProperties
== NULL
) {
2883 *pPropertyCount
= 0;
2887 /* None supported at this time */
2888 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2891 VkResult
radv_EnumerateDeviceLayerProperties(
2892 VkPhysicalDevice physicalDevice
,
2893 uint32_t* pPropertyCount
,
2894 VkLayerProperties
* pProperties
)
2896 if (pProperties
== NULL
) {
2897 *pPropertyCount
= 0;
2901 /* None supported at this time */
2902 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2905 void radv_GetDeviceQueue2(
2907 const VkDeviceQueueInfo2
* pQueueInfo
,
2910 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2911 struct radv_queue
*queue
;
2913 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2914 if (pQueueInfo
->flags
!= queue
->flags
) {
2915 /* From the Vulkan 1.1.70 spec:
2917 * "The queue returned by vkGetDeviceQueue2 must have the same
2918 * flags value from this structure as that used at device
2919 * creation time in a VkDeviceQueueCreateInfo instance. If no
2920 * matching flags were specified at device creation time then
2921 * pQueue will return VK_NULL_HANDLE."
2923 *pQueue
= VK_NULL_HANDLE
;
2927 *pQueue
= radv_queue_to_handle(queue
);
2930 void radv_GetDeviceQueue(
2932 uint32_t queueFamilyIndex
,
2933 uint32_t queueIndex
,
2936 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2937 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2938 .queueFamilyIndex
= queueFamilyIndex
,
2939 .queueIndex
= queueIndex
2942 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2946 fill_geom_tess_rings(struct radv_queue
*queue
,
2948 bool add_sample_positions
,
2949 uint32_t esgs_ring_size
,
2950 struct radeon_winsys_bo
*esgs_ring_bo
,
2951 uint32_t gsvs_ring_size
,
2952 struct radeon_winsys_bo
*gsvs_ring_bo
,
2953 uint32_t tess_factor_ring_size
,
2954 uint32_t tess_offchip_ring_offset
,
2955 uint32_t tess_offchip_ring_size
,
2956 struct radeon_winsys_bo
*tess_rings_bo
)
2958 uint32_t *desc
= &map
[4];
2961 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2963 /* stride 0, num records - size, add tid, swizzle, elsize4,
2966 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2967 S_008F04_SWIZZLE_ENABLE(true);
2968 desc
[2] = esgs_ring_size
;
2969 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2970 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2971 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2972 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2973 S_008F0C_INDEX_STRIDE(3) |
2974 S_008F0C_ADD_TID_ENABLE(1);
2976 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2977 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2978 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
2979 S_008F0C_RESOURCE_LEVEL(1);
2981 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2982 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2983 S_008F0C_ELEMENT_SIZE(1);
2986 /* GS entry for ES->GS ring */
2987 /* stride 0, num records - size, elsize0,
2990 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2991 desc
[6] = esgs_ring_size
;
2992 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2993 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2994 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2995 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2997 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2998 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2999 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3000 S_008F0C_RESOURCE_LEVEL(1);
3002 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3003 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3010 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
3012 /* VS entry for GS->VS ring */
3013 /* stride 0, num records - size, elsize0,
3016 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
3017 desc
[2] = gsvs_ring_size
;
3018 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3019 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3020 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3021 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3023 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3024 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3025 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3026 S_008F0C_RESOURCE_LEVEL(1);
3028 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3029 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3032 /* stride gsvs_itemsize, num records 64
3033 elsize 4, index stride 16 */
3034 /* shader will patch stride and desc[2] */
3036 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
3037 S_008F04_SWIZZLE_ENABLE(1);
3039 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3040 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3041 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3042 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
3043 S_008F0C_INDEX_STRIDE(1) |
3044 S_008F0C_ADD_TID_ENABLE(true);
3046 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3047 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3048 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_DISABLED
) |
3049 S_008F0C_RESOURCE_LEVEL(1);
3051 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3052 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
3053 S_008F0C_ELEMENT_SIZE(1);
3060 if (tess_rings_bo
) {
3061 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
3062 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
3065 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
3066 desc
[2] = tess_factor_ring_size
;
3067 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3068 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3069 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3070 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3072 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3073 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3074 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3075 S_008F0C_RESOURCE_LEVEL(1);
3077 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3078 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3081 desc
[4] = tess_offchip_va
;
3082 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
3083 desc
[6] = tess_offchip_ring_size
;
3084 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
3085 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
3086 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
3087 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
3089 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3090 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
3091 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
3092 S_008F0C_RESOURCE_LEVEL(1);
3094 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
3095 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
3101 if (add_sample_positions
) {
3102 /* add sample positions after all rings */
3103 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
3105 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
3107 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
3109 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
3114 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
3116 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
3117 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
3118 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
3119 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
3120 unsigned max_offchip_buffers
;
3121 unsigned offchip_granularity
;
3122 unsigned hs_offchip_param
;
3126 * This must be one less than the maximum number due to a hw limitation.
3127 * Various hardware bugs need thGFX7
3130 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3131 * Gfx7 should limit max_offchip_buffers to 508
3132 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3134 * Follow AMDVLK here.
3136 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3137 max_offchip_buffers_per_se
= 256;
3138 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
3139 device
->physical_device
->rad_info
.chip_class
== GFX7
||
3140 device
->physical_device
->rad_info
.chip_class
== GFX6
)
3141 --max_offchip_buffers_per_se
;
3143 max_offchip_buffers
= max_offchip_buffers_per_se
*
3144 device
->physical_device
->rad_info
.max_se
;
3146 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3147 * around by setting 4K granularity.
3149 if (device
->tess_offchip_block_dw_size
== 4096) {
3150 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
3151 offchip_granularity
= V_03093C_X_4K_DWORDS
;
3153 assert(device
->tess_offchip_block_dw_size
== 8192);
3154 offchip_granularity
= V_03093C_X_8K_DWORDS
;
3157 switch (device
->physical_device
->rad_info
.chip_class
) {
3159 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
3164 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
3172 *max_offchip_buffers_p
= max_offchip_buffers
;
3173 if (device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) {
3174 hs_offchip_param
= S_03093C_OFFCHIP_BUFFERING_GFX103(max_offchip_buffers
- 1) |
3175 S_03093C_OFFCHIP_GRANULARITY_GFX103(offchip_granularity
);
3176 } else if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3177 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
3178 --max_offchip_buffers
;
3180 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
3181 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
3184 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
3186 return hs_offchip_param
;
3190 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3191 struct radeon_winsys_bo
*esgs_ring_bo
,
3192 uint32_t esgs_ring_size
,
3193 struct radeon_winsys_bo
*gsvs_ring_bo
,
3194 uint32_t gsvs_ring_size
)
3196 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
3200 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
3203 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
3205 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3206 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
3207 radeon_emit(cs
, esgs_ring_size
>> 8);
3208 radeon_emit(cs
, gsvs_ring_size
>> 8);
3210 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
3211 radeon_emit(cs
, esgs_ring_size
>> 8);
3212 radeon_emit(cs
, gsvs_ring_size
>> 8);
3217 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3218 unsigned hs_offchip_param
, unsigned tf_ring_size
,
3219 struct radeon_winsys_bo
*tess_rings_bo
)
3226 tf_va
= radv_buffer_get_va(tess_rings_bo
);
3228 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
3230 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
3231 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3232 S_030938_SIZE(tf_ring_size
/ 4));
3233 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
3236 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3237 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3238 S_030984_BASE_HI(tf_va
>> 40));
3239 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3240 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3241 S_030944_BASE_HI(tf_va
>> 40));
3243 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3246 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
3247 S_008988_SIZE(tf_ring_size
/ 4));
3248 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
3250 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3256 radv_emit_graphics_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3257 uint32_t size_per_wave
, uint32_t waves
,
3258 struct radeon_winsys_bo
*scratch_bo
)
3260 if (queue
->queue_family_index
!= RADV_QUEUE_GENERAL
)
3266 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3268 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
3269 S_0286E8_WAVES(waves
) |
3270 S_0286E8_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3274 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
3275 uint32_t size_per_wave
, uint32_t waves
,
3276 struct radeon_winsys_bo
*compute_scratch_bo
)
3278 uint64_t scratch_va
;
3280 if (!compute_scratch_bo
)
3283 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
3285 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
3287 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
3288 radeon_emit(cs
, scratch_va
);
3289 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3290 S_008F04_SWIZZLE_ENABLE(1));
3292 radeon_set_sh_reg(cs
, R_00B860_COMPUTE_TMPRING_SIZE
,
3293 S_00B860_WAVES(waves
) |
3294 S_00B860_WAVESIZE(round_up_u32(size_per_wave
, 1024)));
3298 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
3299 struct radeon_cmdbuf
*cs
,
3300 struct radeon_winsys_bo
*descriptor_bo
)
3307 va
= radv_buffer_get_va(descriptor_bo
);
3309 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
3311 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3312 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3313 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3314 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3315 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3317 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3318 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3321 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3322 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3323 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3324 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
3325 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
3327 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3328 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3332 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
3333 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
3334 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
3335 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
3336 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
3337 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
3339 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
3340 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3347 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3349 struct radv_device
*device
= queue
->device
;
3351 if (device
->gfx_init
) {
3352 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3354 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3355 radeon_emit(cs
, va
);
3356 radeon_emit(cs
, va
>> 32);
3357 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3359 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3361 si_emit_graphics(device
, cs
);
3366 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3368 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3369 si_emit_compute(physical_device
, cs
);
3373 radv_get_preamble_cs(struct radv_queue
*queue
,
3374 uint32_t scratch_size_per_wave
,
3375 uint32_t scratch_waves
,
3376 uint32_t compute_scratch_size_per_wave
,
3377 uint32_t compute_scratch_waves
,
3378 uint32_t esgs_ring_size
,
3379 uint32_t gsvs_ring_size
,
3380 bool needs_tess_rings
,
3383 bool needs_sample_positions
,
3384 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3385 struct radeon_cmdbuf
**initial_preamble_cs
,
3386 struct radeon_cmdbuf
**continue_preamble_cs
)
3388 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3389 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3390 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3391 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3392 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3393 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3394 struct radeon_winsys_bo
*gds_bo
= NULL
;
3395 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3396 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3397 bool add_tess_rings
= false, add_gds
= false, add_gds_oa
= false, add_sample_positions
= false;
3398 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3399 unsigned max_offchip_buffers
;
3400 unsigned hs_offchip_param
= 0;
3401 unsigned tess_offchip_ring_offset
;
3402 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3403 if (!queue
->has_tess_rings
) {
3404 if (needs_tess_rings
)
3405 add_tess_rings
= true;
3407 if (!queue
->has_gds
) {
3411 if (!queue
->has_gds_oa
) {
3415 if (!queue
->has_sample_positions
) {
3416 if (needs_sample_positions
)
3417 add_sample_positions
= true;
3419 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3420 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3421 &max_offchip_buffers
);
3422 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3423 tess_offchip_ring_size
= max_offchip_buffers
*
3424 queue
->device
->tess_offchip_block_dw_size
* 4;
3426 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, queue
->scratch_size_per_wave
);
3427 if (scratch_size_per_wave
)
3428 scratch_waves
= MIN2(scratch_waves
, UINT32_MAX
/ scratch_size_per_wave
);
3432 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
, queue
->compute_scratch_size_per_wave
);
3433 if (compute_scratch_size_per_wave
)
3434 compute_scratch_waves
= MIN2(compute_scratch_waves
, UINT32_MAX
/ compute_scratch_size_per_wave
);
3436 compute_scratch_waves
= 0;
3438 if (scratch_size_per_wave
<= queue
->scratch_size_per_wave
&&
3439 scratch_waves
<= queue
->scratch_waves
&&
3440 compute_scratch_size_per_wave
<= queue
->compute_scratch_size_per_wave
&&
3441 compute_scratch_waves
<= queue
->compute_scratch_waves
&&
3442 esgs_ring_size
<= queue
->esgs_ring_size
&&
3443 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3444 !add_tess_rings
&& !add_gds
&& !add_gds_oa
&& !add_sample_positions
&&
3445 queue
->initial_preamble_cs
) {
3446 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3447 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3448 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3449 if (!scratch_size_per_wave
&& !compute_scratch_size_per_wave
&&
3450 !esgs_ring_size
&& !gsvs_ring_size
&& !needs_tess_rings
&&
3451 !needs_gds
&& !needs_gds_oa
&& !needs_sample_positions
)
3452 *continue_preamble_cs
= NULL
;
3456 uint32_t scratch_size
= scratch_size_per_wave
* scratch_waves
;
3457 uint32_t queue_scratch_size
= queue
->scratch_size_per_wave
* queue
->scratch_waves
;
3458 if (scratch_size
> queue_scratch_size
) {
3459 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3464 RADV_BO_PRIORITY_SCRATCH
);
3468 scratch_bo
= queue
->scratch_bo
;
3470 uint32_t compute_scratch_size
= compute_scratch_size_per_wave
* compute_scratch_waves
;
3471 uint32_t compute_queue_scratch_size
= queue
->compute_scratch_size_per_wave
* queue
->compute_scratch_waves
;
3472 if (compute_scratch_size
> compute_queue_scratch_size
) {
3473 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3474 compute_scratch_size
,
3478 RADV_BO_PRIORITY_SCRATCH
);
3479 if (!compute_scratch_bo
)
3483 compute_scratch_bo
= queue
->compute_scratch_bo
;
3485 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3486 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3491 RADV_BO_PRIORITY_SCRATCH
);
3495 esgs_ring_bo
= queue
->esgs_ring_bo
;
3496 esgs_ring_size
= queue
->esgs_ring_size
;
3499 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3500 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3505 RADV_BO_PRIORITY_SCRATCH
);
3509 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3510 gsvs_ring_size
= queue
->gsvs_ring_size
;
3513 if (add_tess_rings
) {
3514 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3515 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3519 RADV_BO_PRIORITY_SCRATCH
);
3523 tess_rings_bo
= queue
->tess_rings_bo
;
3527 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3529 /* 4 streamout GDS counters.
3530 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3532 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3536 RADV_BO_PRIORITY_SCRATCH
);
3540 gds_bo
= queue
->gds_bo
;
3544 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3546 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3550 RADV_BO_PRIORITY_SCRATCH
);
3554 gds_oa_bo
= queue
->gds_oa_bo
;
3557 if (scratch_bo
!= queue
->scratch_bo
||
3558 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3559 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3560 tess_rings_bo
!= queue
->tess_rings_bo
||
3561 add_sample_positions
) {
3563 if (gsvs_ring_bo
|| esgs_ring_bo
||
3564 tess_rings_bo
|| add_sample_positions
) {
3565 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3566 if (add_sample_positions
)
3567 size
+= 128; /* 64+32+16+8 = 120 bytes */
3569 else if (scratch_bo
)
3570 size
= 8; /* 2 dword */
3572 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3576 RADEON_FLAG_CPU_ACCESS
|
3577 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3578 RADEON_FLAG_READ_ONLY
,
3579 RADV_BO_PRIORITY_DESCRIPTOR
);
3583 descriptor_bo
= queue
->descriptor_bo
;
3585 if (descriptor_bo
!= queue
->descriptor_bo
) {
3586 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3591 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3592 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3593 S_008F04_SWIZZLE_ENABLE(1);
3594 map
[0] = scratch_va
;
3598 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3599 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3600 esgs_ring_size
, esgs_ring_bo
,
3601 gsvs_ring_size
, gsvs_ring_bo
,
3602 tess_factor_ring_size
,
3603 tess_offchip_ring_offset
,
3604 tess_offchip_ring_size
,
3607 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3610 for(int i
= 0; i
< 3; ++i
) {
3611 struct radeon_cmdbuf
*cs
= NULL
;
3612 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3613 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3620 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3622 /* Emit initial configuration. */
3623 switch (queue
->queue_family_index
) {
3624 case RADV_QUEUE_GENERAL
:
3625 radv_init_graphics_state(cs
, queue
);
3627 case RADV_QUEUE_COMPUTE
:
3628 radv_init_compute_state(cs
, queue
);
3630 case RADV_QUEUE_TRANSFER
:
3634 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3635 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3636 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3638 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3639 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3642 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3643 gsvs_ring_bo
, gsvs_ring_size
);
3644 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3645 tess_factor_ring_size
, tess_rings_bo
);
3646 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3647 radv_emit_compute_scratch(queue
, cs
, compute_scratch_size_per_wave
,
3648 compute_scratch_waves
, compute_scratch_bo
);
3649 radv_emit_graphics_scratch(queue
, cs
, scratch_size_per_wave
,
3650 scratch_waves
, scratch_bo
);
3653 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3655 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3657 if (queue
->device
->trace_bo
)
3658 radv_cs_add_buffer(queue
->device
->ws
, cs
, queue
->device
->trace_bo
);
3660 if (queue
->device
->border_color_data
.bo
)
3661 radv_cs_add_buffer(queue
->device
->ws
, cs
,
3662 queue
->device
->border_color_data
.bo
);
3665 si_cs_emit_cache_flush(cs
,
3666 queue
->device
->physical_device
->rad_info
.chip_class
,
3668 queue
->queue_family_index
== RING_COMPUTE
&&
3669 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3670 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3671 RADV_CMD_FLAG_INV_ICACHE
|
3672 RADV_CMD_FLAG_INV_SCACHE
|
3673 RADV_CMD_FLAG_INV_VCACHE
|
3674 RADV_CMD_FLAG_INV_L2
|
3675 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3676 } else if (i
== 1) {
3677 si_cs_emit_cache_flush(cs
,
3678 queue
->device
->physical_device
->rad_info
.chip_class
,
3680 queue
->queue_family_index
== RING_COMPUTE
&&
3681 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3682 RADV_CMD_FLAG_INV_ICACHE
|
3683 RADV_CMD_FLAG_INV_SCACHE
|
3684 RADV_CMD_FLAG_INV_VCACHE
|
3685 RADV_CMD_FLAG_INV_L2
|
3686 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3689 if (queue
->device
->ws
->cs_finalize(cs
) != VK_SUCCESS
)
3693 if (queue
->initial_full_flush_preamble_cs
)
3694 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3696 if (queue
->initial_preamble_cs
)
3697 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3699 if (queue
->continue_preamble_cs
)
3700 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3702 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3703 queue
->initial_preamble_cs
= dest_cs
[1];
3704 queue
->continue_preamble_cs
= dest_cs
[2];
3706 if (scratch_bo
!= queue
->scratch_bo
) {
3707 if (queue
->scratch_bo
)
3708 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3709 queue
->scratch_bo
= scratch_bo
;
3711 queue
->scratch_size_per_wave
= scratch_size_per_wave
;
3712 queue
->scratch_waves
= scratch_waves
;
3714 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3715 if (queue
->compute_scratch_bo
)
3716 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3717 queue
->compute_scratch_bo
= compute_scratch_bo
;
3719 queue
->compute_scratch_size_per_wave
= compute_scratch_size_per_wave
;
3720 queue
->compute_scratch_waves
= compute_scratch_waves
;
3722 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3723 if (queue
->esgs_ring_bo
)
3724 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3725 queue
->esgs_ring_bo
= esgs_ring_bo
;
3726 queue
->esgs_ring_size
= esgs_ring_size
;
3729 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3730 if (queue
->gsvs_ring_bo
)
3731 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3732 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3733 queue
->gsvs_ring_size
= gsvs_ring_size
;
3736 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3737 queue
->tess_rings_bo
= tess_rings_bo
;
3738 queue
->has_tess_rings
= true;
3741 if (gds_bo
!= queue
->gds_bo
) {
3742 queue
->gds_bo
= gds_bo
;
3743 queue
->has_gds
= true;
3746 if (gds_oa_bo
!= queue
->gds_oa_bo
) {
3747 queue
->gds_oa_bo
= gds_oa_bo
;
3748 queue
->has_gds_oa
= true;
3751 if (descriptor_bo
!= queue
->descriptor_bo
) {
3752 if (queue
->descriptor_bo
)
3753 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3755 queue
->descriptor_bo
= descriptor_bo
;
3758 if (add_sample_positions
)
3759 queue
->has_sample_positions
= true;
3761 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3762 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3763 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3764 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3765 *continue_preamble_cs
= NULL
;
3768 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
3770 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
3771 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
3772 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
3773 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
3774 queue
->device
->ws
->buffer_destroy(scratch_bo
);
3775 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
3776 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
3777 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
3778 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
3779 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
3780 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
3781 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
3782 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
3783 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
3784 queue
->device
->ws
->buffer_destroy(gds_bo
);
3785 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
3786 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
3788 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3791 static VkResult
radv_alloc_sem_counts(struct radv_device
*device
,
3792 struct radv_winsys_sem_counts
*counts
,
3794 struct radv_semaphore_part
**sems
,
3795 const uint64_t *timeline_values
,
3799 int syncobj_idx
= 0, non_reset_idx
= 0, sem_idx
= 0;
3801 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
3804 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3805 switch(sems
[i
]->kind
) {
3806 case RADV_SEMAPHORE_SYNCOBJ
:
3807 counts
->syncobj_count
++;
3808 counts
->syncobj_reset_count
++;
3810 case RADV_SEMAPHORE_WINSYS
:
3811 counts
->sem_count
++;
3813 case RADV_SEMAPHORE_NONE
:
3815 case RADV_SEMAPHORE_TIMELINE
:
3816 counts
->syncobj_count
++;
3821 if (_fence
!= VK_NULL_HANDLE
) {
3822 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3824 struct radv_fence_part
*part
=
3825 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3826 &fence
->temporary
: &fence
->permanent
;
3827 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3828 counts
->syncobj_count
++;
3831 if (counts
->syncobj_count
) {
3832 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
3833 if (!counts
->syncobj
)
3834 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3837 if (counts
->sem_count
) {
3838 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
3840 free(counts
->syncobj
);
3841 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3845 non_reset_idx
= counts
->syncobj_reset_count
;
3847 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3848 switch(sems
[i
]->kind
) {
3849 case RADV_SEMAPHORE_NONE
:
3850 unreachable("Empty semaphore");
3852 case RADV_SEMAPHORE_SYNCOBJ
:
3853 counts
->syncobj
[syncobj_idx
++] = sems
[i
]->syncobj
;
3855 case RADV_SEMAPHORE_WINSYS
:
3856 counts
->sem
[sem_idx
++] = sems
[i
]->ws_sem
;
3858 case RADV_SEMAPHORE_TIMELINE
: {
3859 pthread_mutex_lock(&sems
[i
]->timeline
.mutex
);
3860 struct radv_timeline_point
*point
= NULL
;
3862 point
= radv_timeline_add_point_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
3864 point
= radv_timeline_find_point_at_least_locked(device
, &sems
[i
]->timeline
, timeline_values
[i
]);
3867 pthread_mutex_unlock(&sems
[i
]->timeline
.mutex
);
3870 counts
->syncobj
[non_reset_idx
++] = point
->syncobj
;
3872 /* Explicitly remove the semaphore so we might not find
3873 * a point later post-submit. */
3881 if (_fence
!= VK_NULL_HANDLE
) {
3882 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3884 struct radv_fence_part
*part
=
3885 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
3886 &fence
->temporary
: &fence
->permanent
;
3887 if (part
->kind
== RADV_FENCE_SYNCOBJ
)
3888 counts
->syncobj
[non_reset_idx
++] = part
->syncobj
;
3891 assert(MAX2(syncobj_idx
, non_reset_idx
) <= counts
->syncobj_count
);
3892 counts
->syncobj_count
= MAX2(syncobj_idx
, non_reset_idx
);
3898 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
3900 free(sem_info
->wait
.syncobj
);
3901 free(sem_info
->wait
.sem
);
3902 free(sem_info
->signal
.syncobj
);
3903 free(sem_info
->signal
.sem
);
3907 static void radv_free_temp_syncobjs(struct radv_device
*device
,
3909 struct radv_semaphore_part
*sems
)
3911 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3912 radv_destroy_semaphore_part(device
, sems
+ i
);
3917 radv_alloc_sem_info(struct radv_device
*device
,
3918 struct radv_winsys_sem_info
*sem_info
,
3920 struct radv_semaphore_part
**wait_sems
,
3921 const uint64_t *wait_values
,
3922 int num_signal_sems
,
3923 struct radv_semaphore_part
**signal_sems
,
3924 const uint64_t *signal_values
,
3928 memset(sem_info
, 0, sizeof(*sem_info
));
3930 ret
= radv_alloc_sem_counts(device
, &sem_info
->wait
, num_wait_sems
, wait_sems
, wait_values
, VK_NULL_HANDLE
, false);
3933 ret
= radv_alloc_sem_counts(device
, &sem_info
->signal
, num_signal_sems
, signal_sems
, signal_values
, fence
, true);
3935 radv_free_sem_info(sem_info
);
3937 /* caller can override these */
3938 sem_info
->cs_emit_wait
= true;
3939 sem_info
->cs_emit_signal
= true;
3944 radv_finalize_timelines(struct radv_device
*device
,
3945 uint32_t num_wait_sems
,
3946 struct radv_semaphore_part
**wait_sems
,
3947 const uint64_t *wait_values
,
3948 uint32_t num_signal_sems
,
3949 struct radv_semaphore_part
**signal_sems
,
3950 const uint64_t *signal_values
,
3951 struct list_head
*processing_list
)
3953 for (uint32_t i
= 0; i
< num_wait_sems
; ++i
) {
3954 if (wait_sems
[i
] && wait_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
3955 pthread_mutex_lock(&wait_sems
[i
]->timeline
.mutex
);
3956 struct radv_timeline_point
*point
=
3957 radv_timeline_find_point_at_least_locked(device
, &wait_sems
[i
]->timeline
, wait_values
[i
]);
3958 point
->wait_count
-= 2;
3959 pthread_mutex_unlock(&wait_sems
[i
]->timeline
.mutex
);
3962 for (uint32_t i
= 0; i
< num_signal_sems
; ++i
) {
3963 if (signal_sems
[i
] && signal_sems
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
3964 pthread_mutex_lock(&signal_sems
[i
]->timeline
.mutex
);
3965 struct radv_timeline_point
*point
=
3966 radv_timeline_find_point_at_least_locked(device
, &signal_sems
[i
]->timeline
, signal_values
[i
]);
3967 signal_sems
[i
]->timeline
.highest_submitted
=
3968 MAX2(signal_sems
[i
]->timeline
.highest_submitted
, point
->value
);
3969 point
->wait_count
-= 2;
3970 radv_timeline_trigger_waiters_locked(&signal_sems
[i
]->timeline
, processing_list
);
3971 pthread_mutex_unlock(&signal_sems
[i
]->timeline
.mutex
);
3977 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3978 const VkSparseBufferMemoryBindInfo
*bind
)
3980 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3983 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3984 struct radv_device_memory
*mem
= NULL
;
3986 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3987 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3989 result
= device
->ws
->buffer_virtual_bind(buffer
->bo
,
3990 bind
->pBinds
[i
].resourceOffset
,
3991 bind
->pBinds
[i
].size
,
3992 mem
? mem
->bo
: NULL
,
3993 bind
->pBinds
[i
].memoryOffset
);
3994 if (result
!= VK_SUCCESS
)
4002 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
4003 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
4005 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
4008 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
4009 struct radv_device_memory
*mem
= NULL
;
4011 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
4012 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
4014 result
= device
->ws
->buffer_virtual_bind(image
->bo
,
4015 bind
->pBinds
[i
].resourceOffset
,
4016 bind
->pBinds
[i
].size
,
4017 mem
? mem
->bo
: NULL
,
4018 bind
->pBinds
[i
].memoryOffset
);
4019 if (result
!= VK_SUCCESS
)
4027 radv_get_preambles(struct radv_queue
*queue
,
4028 const VkCommandBuffer
*cmd_buffers
,
4029 uint32_t cmd_buffer_count
,
4030 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
4031 struct radeon_cmdbuf
**initial_preamble_cs
,
4032 struct radeon_cmdbuf
**continue_preamble_cs
)
4034 uint32_t scratch_size_per_wave
= 0, waves_wanted
= 0;
4035 uint32_t compute_scratch_size_per_wave
= 0, compute_waves_wanted
= 0;
4036 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
4037 bool tess_rings_needed
= false;
4038 bool gds_needed
= false;
4039 bool gds_oa_needed
= false;
4040 bool sample_positions_needed
= false;
4042 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
4043 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
4046 scratch_size_per_wave
= MAX2(scratch_size_per_wave
, cmd_buffer
->scratch_size_per_wave_needed
);
4047 waves_wanted
= MAX2(waves_wanted
, cmd_buffer
->scratch_waves_wanted
);
4048 compute_scratch_size_per_wave
= MAX2(compute_scratch_size_per_wave
,
4049 cmd_buffer
->compute_scratch_size_per_wave_needed
);
4050 compute_waves_wanted
= MAX2(compute_waves_wanted
,
4051 cmd_buffer
->compute_scratch_waves_wanted
);
4052 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
4053 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
4054 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
4055 gds_needed
|= cmd_buffer
->gds_needed
;
4056 gds_oa_needed
|= cmd_buffer
->gds_oa_needed
;
4057 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
4060 return radv_get_preamble_cs(queue
, scratch_size_per_wave
, waves_wanted
,
4061 compute_scratch_size_per_wave
, compute_waves_wanted
,
4062 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
4063 gds_needed
, gds_oa_needed
, sample_positions_needed
,
4064 initial_full_flush_preamble_cs
,
4065 initial_preamble_cs
, continue_preamble_cs
);
4068 struct radv_deferred_queue_submission
{
4069 struct radv_queue
*queue
;
4070 VkCommandBuffer
*cmd_buffers
;
4071 uint32_t cmd_buffer_count
;
4073 /* Sparse bindings that happen on a queue. */
4074 VkSparseBufferMemoryBindInfo
*buffer_binds
;
4075 uint32_t buffer_bind_count
;
4076 VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4077 uint32_t image_opaque_bind_count
;
4080 VkShaderStageFlags wait_dst_stage_mask
;
4081 struct radv_semaphore_part
**wait_semaphores
;
4082 uint32_t wait_semaphore_count
;
4083 struct radv_semaphore_part
**signal_semaphores
;
4084 uint32_t signal_semaphore_count
;
4087 uint64_t *wait_values
;
4088 uint64_t *signal_values
;
4090 struct radv_semaphore_part
*temporary_semaphore_parts
;
4091 uint32_t temporary_semaphore_part_count
;
4093 struct list_head queue_pending_list
;
4094 uint32_t submission_wait_count
;
4095 struct radv_timeline_waiter
*wait_nodes
;
4097 struct list_head processing_list
;
4100 struct radv_queue_submission
{
4101 const VkCommandBuffer
*cmd_buffers
;
4102 uint32_t cmd_buffer_count
;
4104 /* Sparse bindings that happen on a queue. */
4105 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
4106 uint32_t buffer_bind_count
;
4107 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
4108 uint32_t image_opaque_bind_count
;
4111 VkPipelineStageFlags wait_dst_stage_mask
;
4112 const VkSemaphore
*wait_semaphores
;
4113 uint32_t wait_semaphore_count
;
4114 const VkSemaphore
*signal_semaphores
;
4115 uint32_t signal_semaphore_count
;
4118 const uint64_t *wait_values
;
4119 uint32_t wait_value_count
;
4120 const uint64_t *signal_values
;
4121 uint32_t signal_value_count
;
4125 radv_queue_trigger_submission(struct radv_deferred_queue_submission
*submission
,
4127 struct list_head
*processing_list
);
4130 radv_create_deferred_submission(struct radv_queue
*queue
,
4131 const struct radv_queue_submission
*submission
,
4132 struct radv_deferred_queue_submission
**out
)
4134 struct radv_deferred_queue_submission
*deferred
= NULL
;
4135 size_t size
= sizeof(struct radv_deferred_queue_submission
);
4137 uint32_t temporary_count
= 0;
4138 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4139 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4140 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
)
4144 size
+= submission
->cmd_buffer_count
* sizeof(VkCommandBuffer
);
4145 size
+= submission
->buffer_bind_count
* sizeof(VkSparseBufferMemoryBindInfo
);
4146 size
+= submission
->image_opaque_bind_count
* sizeof(VkSparseImageOpaqueMemoryBindInfo
);
4147 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4148 size
+= temporary_count
* sizeof(struct radv_semaphore_part
);
4149 size
+= submission
->signal_semaphore_count
* sizeof(struct radv_semaphore_part
*);
4150 size
+= submission
->wait_value_count
* sizeof(uint64_t);
4151 size
+= submission
->signal_value_count
* sizeof(uint64_t);
4152 size
+= submission
->wait_semaphore_count
* sizeof(struct radv_timeline_waiter
);
4154 deferred
= calloc(1, size
);
4156 return VK_ERROR_OUT_OF_HOST_MEMORY
;
4158 deferred
->queue
= queue
;
4160 deferred
->cmd_buffers
= (void*)(deferred
+ 1);
4161 deferred
->cmd_buffer_count
= submission
->cmd_buffer_count
;
4162 memcpy(deferred
->cmd_buffers
, submission
->cmd_buffers
,
4163 submission
->cmd_buffer_count
* sizeof(*deferred
->cmd_buffers
));
4165 deferred
->buffer_binds
= (void*)(deferred
->cmd_buffers
+ submission
->cmd_buffer_count
);
4166 deferred
->buffer_bind_count
= submission
->buffer_bind_count
;
4167 memcpy(deferred
->buffer_binds
, submission
->buffer_binds
,
4168 submission
->buffer_bind_count
* sizeof(*deferred
->buffer_binds
));
4170 deferred
->image_opaque_binds
= (void*)(deferred
->buffer_binds
+ submission
->buffer_bind_count
);
4171 deferred
->image_opaque_bind_count
= submission
->image_opaque_bind_count
;
4172 memcpy(deferred
->image_opaque_binds
, submission
->image_opaque_binds
,
4173 submission
->image_opaque_bind_count
* sizeof(*deferred
->image_opaque_binds
));
4175 deferred
->flush_caches
= submission
->flush_caches
;
4176 deferred
->wait_dst_stage_mask
= submission
->wait_dst_stage_mask
;
4178 deferred
->wait_semaphores
= (void*)(deferred
->image_opaque_binds
+ deferred
->image_opaque_bind_count
);
4179 deferred
->wait_semaphore_count
= submission
->wait_semaphore_count
;
4181 deferred
->signal_semaphores
= (void*)(deferred
->wait_semaphores
+ deferred
->wait_semaphore_count
);
4182 deferred
->signal_semaphore_count
= submission
->signal_semaphore_count
;
4184 deferred
->fence
= submission
->fence
;
4186 deferred
->temporary_semaphore_parts
= (void*)(deferred
->signal_semaphores
+ deferred
->signal_semaphore_count
);
4187 deferred
->temporary_semaphore_part_count
= temporary_count
;
4189 uint32_t temporary_idx
= 0;
4190 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4191 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->wait_semaphores
[i
]);
4192 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4193 deferred
->wait_semaphores
[i
] = &deferred
->temporary_semaphore_parts
[temporary_idx
];
4194 deferred
->temporary_semaphore_parts
[temporary_idx
] = semaphore
->temporary
;
4195 semaphore
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
4198 deferred
->wait_semaphores
[i
] = &semaphore
->permanent
;
4201 for (uint32_t i
= 0; i
< submission
->signal_semaphore_count
; ++i
) {
4202 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, submission
->signal_semaphores
[i
]);
4203 if (semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
4204 deferred
->signal_semaphores
[i
] = &semaphore
->temporary
;
4206 deferred
->signal_semaphores
[i
] = &semaphore
->permanent
;
4210 deferred
->wait_values
= (void*)(deferred
->temporary_semaphore_parts
+ temporary_count
);
4211 memcpy(deferred
->wait_values
, submission
->wait_values
, submission
->wait_value_count
* sizeof(uint64_t));
4212 deferred
->signal_values
= deferred
->wait_values
+ submission
->wait_value_count
;
4213 memcpy(deferred
->signal_values
, submission
->signal_values
, submission
->signal_value_count
* sizeof(uint64_t));
4215 deferred
->wait_nodes
= (void*)(deferred
->signal_values
+ submission
->signal_value_count
);
4216 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4217 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4218 deferred
->submission_wait_count
= 1 + submission
->wait_semaphore_count
;
4225 radv_queue_enqueue_submission(struct radv_deferred_queue_submission
*submission
,
4226 struct list_head
*processing_list
)
4228 uint32_t wait_cnt
= 0;
4229 struct radv_timeline_waiter
*waiter
= submission
->wait_nodes
;
4230 for (uint32_t i
= 0; i
< submission
->wait_semaphore_count
; ++i
) {
4231 if (submission
->wait_semaphores
[i
]->kind
== RADV_SEMAPHORE_TIMELINE
) {
4232 pthread_mutex_lock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4233 if (submission
->wait_semaphores
[i
]->timeline
.highest_submitted
< submission
->wait_values
[i
]) {
4235 waiter
->value
= submission
->wait_values
[i
];
4236 waiter
->submission
= submission
;
4237 list_addtail(&waiter
->list
, &submission
->wait_semaphores
[i
]->timeline
.waiters
);
4240 pthread_mutex_unlock(&submission
->wait_semaphores
[i
]->timeline
.mutex
);
4244 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4246 bool is_first
= list_is_empty(&submission
->queue
->pending_submissions
);
4247 list_addtail(&submission
->queue_pending_list
, &submission
->queue
->pending_submissions
);
4249 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4251 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4252 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4254 uint32_t decrement
= submission
->wait_semaphore_count
- wait_cnt
+ (is_first
? 1 : 0);
4255 return radv_queue_trigger_submission(submission
, decrement
, processing_list
);
4259 radv_queue_submission_update_queue(struct radv_deferred_queue_submission
*submission
,
4260 struct list_head
*processing_list
)
4262 pthread_mutex_lock(&submission
->queue
->pending_mutex
);
4263 list_del(&submission
->queue_pending_list
);
4265 /* trigger the next submission in the queue. */
4266 if (!list_is_empty(&submission
->queue
->pending_submissions
)) {
4267 struct radv_deferred_queue_submission
*next_submission
=
4268 list_first_entry(&submission
->queue
->pending_submissions
,
4269 struct radv_deferred_queue_submission
,
4270 queue_pending_list
);
4271 radv_queue_trigger_submission(next_submission
, 1, processing_list
);
4273 pthread_mutex_unlock(&submission
->queue
->pending_mutex
);
4275 pthread_cond_broadcast(&submission
->queue
->device
->timeline_cond
);
4279 radv_queue_submit_deferred(struct radv_deferred_queue_submission
*submission
,
4280 struct list_head
*processing_list
)
4282 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
4283 struct radv_queue
*queue
= submission
->queue
;
4284 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4285 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
4286 struct radeon_winsys_fence
*base_fence
= NULL
;
4287 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
4288 bool can_patch
= true;
4290 struct radv_winsys_sem_info sem_info
;
4292 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
4293 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
4294 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
4297 /* Under most circumstances, out fences won't be temporary.
4298 * However, the spec does allow it for opaque_fd.
4300 * From the Vulkan 1.0.53 spec:
4302 * "If the import is temporary, the implementation must
4303 * restore the semaphore to its prior permanent state after
4304 * submitting the next semaphore wait operation."
4306 struct radv_fence_part
*part
=
4307 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
4308 &fence
->temporary
: &fence
->permanent
;
4309 if (part
->kind
== RADV_FENCE_WINSYS
)
4310 base_fence
= part
->fence
;
4313 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
4314 submission
->cmd_buffer_count
,
4315 &initial_preamble_cs
,
4316 &initial_flush_preamble_cs
,
4317 &continue_preamble_cs
);
4318 if (result
!= VK_SUCCESS
)
4321 result
= radv_alloc_sem_info(queue
->device
,
4323 submission
->wait_semaphore_count
,
4324 submission
->wait_semaphores
,
4325 submission
->wait_values
,
4326 submission
->signal_semaphore_count
,
4327 submission
->signal_semaphores
,
4328 submission
->signal_values
,
4330 if (result
!= VK_SUCCESS
)
4333 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
4334 result
= radv_sparse_buffer_bind_memory(queue
->device
,
4335 submission
->buffer_binds
+ i
);
4336 if (result
!= VK_SUCCESS
)
4340 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
4341 result
= radv_sparse_image_opaque_bind_memory(queue
->device
,
4342 submission
->image_opaque_binds
+ i
);
4343 if (result
!= VK_SUCCESS
)
4347 if (!submission
->cmd_buffer_count
) {
4348 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
4349 &queue
->device
->empty_cs
[queue
->queue_family_index
],
4353 if (result
!= VK_SUCCESS
)
4356 struct radeon_cmdbuf
**cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
4357 (submission
->cmd_buffer_count
));
4359 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
4360 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
4361 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
4363 cs_array
[j
] = cmd_buffer
->cs
;
4364 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
4367 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
4370 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
4371 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
4372 const struct radv_winsys_bo_list
*bo_list
= NULL
;
4374 advance
= MIN2(max_cs_submission
,
4375 submission
->cmd_buffer_count
- j
);
4377 if (queue
->device
->trace_bo
)
4378 *queue
->device
->trace_id_ptr
= 0;
4380 sem_info
.cs_emit_wait
= j
== 0;
4381 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
4383 if (unlikely(queue
->device
->use_global_bo_list
)) {
4384 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
4385 bo_list
= &queue
->device
->bo_list
.list
;
4388 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
4389 advance
, initial_preamble
, continue_preamble_cs
,
4391 can_patch
, base_fence
);
4393 if (unlikely(queue
->device
->use_global_bo_list
))
4394 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
4396 if (result
!= VK_SUCCESS
)
4399 if (queue
->device
->trace_bo
) {
4400 radv_check_gpu_hangs(queue
, cs_array
[j
]);
4407 radv_free_temp_syncobjs(queue
->device
,
4408 submission
->temporary_semaphore_part_count
,
4409 submission
->temporary_semaphore_parts
);
4410 radv_finalize_timelines(queue
->device
,
4411 submission
->wait_semaphore_count
,
4412 submission
->wait_semaphores
,
4413 submission
->wait_values
,
4414 submission
->signal_semaphore_count
,
4415 submission
->signal_semaphores
,
4416 submission
->signal_values
,
4418 /* Has to happen after timeline finalization to make sure the
4419 * condition variable is only triggered when timelines and queue have
4421 radv_queue_submission_update_queue(submission
, processing_list
);
4422 radv_free_sem_info(&sem_info
);
4427 if (result
!= VK_SUCCESS
&& result
!= VK_ERROR_DEVICE_LOST
) {
4428 /* When something bad happened during the submission, such as
4429 * an out of memory issue, it might be hard to recover from
4430 * this inconsistent state. To avoid this sort of problem, we
4431 * assume that we are in a really bad situation and return
4432 * VK_ERROR_DEVICE_LOST to ensure the clients do not attempt
4433 * to submit the same job again to this device.
4435 result
= VK_ERROR_DEVICE_LOST
;
4438 radv_free_temp_syncobjs(queue
->device
,
4439 submission
->temporary_semaphore_part_count
,
4440 submission
->temporary_semaphore_parts
);
4446 radv_process_submissions(struct list_head
*processing_list
)
4448 while(!list_is_empty(processing_list
)) {
4449 struct radv_deferred_queue_submission
*submission
=
4450 list_first_entry(processing_list
, struct radv_deferred_queue_submission
, processing_list
);
4451 list_del(&submission
->processing_list
);
4453 VkResult result
= radv_queue_submit_deferred(submission
, processing_list
);
4454 if (result
!= VK_SUCCESS
)
4461 wait_for_submission_timelines_available(struct radv_deferred_queue_submission
*submission
,
4464 return VK_SUCCESS
; /* TODO: when we implement timeline syncobj. */
4467 static void* radv_queue_submission_thread_run(void *q
)
4469 struct radv_queue
*queue
= q
;
4471 pthread_mutex_lock(&queue
->thread_mutex
);
4472 while (!p_atomic_read(&queue
->thread_exit
)) {
4473 struct radv_deferred_queue_submission
*submission
= queue
->thread_submission
;
4474 struct list_head processing_list
;
4475 VkResult result
= VK_SUCCESS
;
4477 pthread_cond_wait(&queue
->thread_cond
, &queue
->thread_mutex
);
4480 pthread_mutex_unlock(&queue
->thread_mutex
);
4482 /* Wait at most 5 seconds so we have a chance to notice shutdown when
4483 * a semaphore never gets signaled. If it takes longer we just retry
4484 * the wait next iteration. */
4485 result
= wait_for_submission_timelines_available(submission
,
4486 radv_get_absolute_timeout(5000000000));
4487 if (result
!= VK_SUCCESS
) {
4488 pthread_mutex_lock(&queue
->thread_mutex
);
4492 /* The lock isn't held but nobody will add one until we finish
4493 * the current submission. */
4494 p_atomic_set(&queue
->thread_submission
, NULL
);
4496 list_inithead(&processing_list
);
4497 list_addtail(&submission
->processing_list
, &processing_list
);
4498 result
= radv_process_submissions(&processing_list
);
4500 pthread_mutex_lock(&queue
->thread_mutex
);
4502 pthread_mutex_unlock(&queue
->thread_mutex
);
4507 radv_queue_trigger_submission(struct radv_deferred_queue_submission
*submission
,
4509 struct list_head
*processing_list
)
4511 struct radv_queue
*queue
= submission
->queue
;
4513 if (p_atomic_add_return(&submission
->submission_wait_count
, -decrement
))
4516 if (wait_for_submission_timelines_available(submission
, radv_get_absolute_timeout(0)) == VK_SUCCESS
) {
4517 list_addtail(&submission
->processing_list
, processing_list
);
4521 pthread_mutex_lock(&queue
->thread_mutex
);
4523 /* A submission can only be ready for the thread if it doesn't have
4524 * any predecessors in the same queue, so there can only be one such
4525 * submission at a time. */
4526 assert(queue
->thread_submission
== NULL
);
4528 /* Only start the thread on demand to save resources for the many games
4529 * which only use binary semaphores. */
4530 if (!queue
->thread_running
) {
4531 ret
= pthread_create(&queue
->submission_thread
, NULL
,
4532 radv_queue_submission_thread_run
, queue
);
4534 pthread_mutex_unlock(&queue
->thread_mutex
);
4535 return vk_errorf(queue
->device
->instance
,
4536 VK_ERROR_DEVICE_LOST
,
4537 "Failed to start submission thread");
4539 queue
->thread_running
= true;
4542 queue
->thread_submission
= submission
;
4543 pthread_mutex_unlock(&queue
->thread_mutex
);
4545 pthread_cond_signal(&queue
->thread_cond
);
4549 static VkResult
radv_queue_submit(struct radv_queue
*queue
,
4550 const struct radv_queue_submission
*submission
)
4552 struct radv_deferred_queue_submission
*deferred
= NULL
;
4554 VkResult result
= radv_create_deferred_submission(queue
, submission
, &deferred
);
4555 if (result
!= VK_SUCCESS
)
4558 struct list_head processing_list
;
4559 list_inithead(&processing_list
);
4561 result
= radv_queue_enqueue_submission(deferred
, &processing_list
);
4562 if (result
!= VK_SUCCESS
) {
4563 /* If anything is in the list we leak. */
4564 assert(list_is_empty(&processing_list
));
4567 return radv_process_submissions(&processing_list
);
4571 radv_queue_internal_submit(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
)
4573 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
4574 struct radv_winsys_sem_info sem_info
;
4577 result
= radv_alloc_sem_info(queue
->device
, &sem_info
, 0, NULL
, 0, 0,
4578 0, NULL
, VK_NULL_HANDLE
);
4579 if (result
!= VK_SUCCESS
)
4582 result
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, &cs
, 1,
4583 NULL
, NULL
, &sem_info
, NULL
,
4585 radv_free_sem_info(&sem_info
);
4586 if (result
!= VK_SUCCESS
)
4593 /* Signals fence as soon as all the work currently put on queue is done. */
4594 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
4597 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4602 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
4604 return info
->commandBufferCount
||
4605 info
->waitSemaphoreCount
||
4606 info
->signalSemaphoreCount
;
4609 VkResult
radv_QueueSubmit(
4611 uint32_t submitCount
,
4612 const VkSubmitInfo
* pSubmits
,
4615 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4617 uint32_t fence_idx
= 0;
4618 bool flushed_caches
= false;
4620 if (fence
!= VK_NULL_HANDLE
) {
4621 for (uint32_t i
= 0; i
< submitCount
; ++i
)
4622 if (radv_submit_has_effects(pSubmits
+ i
))
4625 fence_idx
= UINT32_MAX
;
4627 for (uint32_t i
= 0; i
< submitCount
; i
++) {
4628 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
4631 VkPipelineStageFlags wait_dst_stage_mask
= 0;
4632 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
4633 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
4636 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
4637 vk_find_struct_const(pSubmits
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
4639 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4640 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
4641 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
4642 .wait_dst_stage_mask
= wait_dst_stage_mask
,
4643 .flush_caches
= !flushed_caches
,
4644 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
4645 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
4646 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
4647 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
4648 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4649 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
4650 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
4651 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
4652 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
4654 if (result
!= VK_SUCCESS
)
4657 flushed_caches
= true;
4660 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
4661 result
= radv_signal_fence(queue
, fence
);
4662 if (result
!= VK_SUCCESS
)
4669 VkResult
radv_QueueWaitIdle(
4672 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4674 pthread_mutex_lock(&queue
->pending_mutex
);
4675 while (!list_is_empty(&queue
->pending_submissions
)) {
4676 pthread_cond_wait(&queue
->device
->timeline_cond
, &queue
->pending_mutex
);
4678 pthread_mutex_unlock(&queue
->pending_mutex
);
4680 if (!queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
4681 radv_queue_family_to_ring(queue
->queue_family_index
),
4683 return VK_ERROR_DEVICE_LOST
;
4688 VkResult
radv_DeviceWaitIdle(
4691 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4693 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
4694 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
4696 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
4698 if (result
!= VK_SUCCESS
)
4705 VkResult
radv_EnumerateInstanceExtensionProperties(
4706 const char* pLayerName
,
4707 uint32_t* pPropertyCount
,
4708 VkExtensionProperties
* pProperties
)
4710 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4712 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
4713 if (radv_instance_extensions_supported
.extensions
[i
]) {
4714 vk_outarray_append(&out
, prop
) {
4715 *prop
= radv_instance_extensions
[i
];
4720 return vk_outarray_status(&out
);
4723 VkResult
radv_EnumerateDeviceExtensionProperties(
4724 VkPhysicalDevice physicalDevice
,
4725 const char* pLayerName
,
4726 uint32_t* pPropertyCount
,
4727 VkExtensionProperties
* pProperties
)
4729 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
4730 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
4732 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
4733 if (device
->supported_extensions
.extensions
[i
]) {
4734 vk_outarray_append(&out
, prop
) {
4735 *prop
= radv_device_extensions
[i
];
4740 return vk_outarray_status(&out
);
4743 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
4744 VkInstance _instance
,
4747 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4749 /* The Vulkan 1.0 spec for vkGetInstanceProcAddr has a table of exactly
4750 * when we have to return valid function pointers, NULL, or it's left
4751 * undefined. See the table for exact details.
4756 #define LOOKUP_RADV_ENTRYPOINT(entrypoint) \
4757 if (strcmp(pName, "vk" #entrypoint) == 0) \
4758 return (PFN_vkVoidFunction)radv_##entrypoint
4760 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceExtensionProperties
);
4761 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceLayerProperties
);
4762 LOOKUP_RADV_ENTRYPOINT(EnumerateInstanceVersion
);
4763 LOOKUP_RADV_ENTRYPOINT(CreateInstance
);
4765 /* GetInstanceProcAddr() can also be called with a NULL instance.
4766 * See https://gitlab.khronos.org/vulkan/vulkan/issues/2057
4768 LOOKUP_RADV_ENTRYPOINT(GetInstanceProcAddr
);
4770 #undef LOOKUP_RADV_ENTRYPOINT
4772 if (instance
== NULL
)
4775 int idx
= radv_get_instance_entrypoint_index(pName
);
4777 return instance
->dispatch
.entrypoints
[idx
];
4779 idx
= radv_get_physical_device_entrypoint_index(pName
);
4781 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4783 idx
= radv_get_device_entrypoint_index(pName
);
4785 return instance
->device_dispatch
.entrypoints
[idx
];
4790 /* The loader wants us to expose a second GetInstanceProcAddr function
4791 * to work around certain LD_PRELOAD issues seen in apps.
4794 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4795 VkInstance instance
,
4799 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
4800 VkInstance instance
,
4803 return radv_GetInstanceProcAddr(instance
, pName
);
4807 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4808 VkInstance _instance
,
4812 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
4813 VkInstance _instance
,
4816 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4818 if (!pName
|| !instance
)
4821 int idx
= radv_get_physical_device_entrypoint_index(pName
);
4825 return instance
->physical_device_dispatch
.entrypoints
[idx
];
4828 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
4832 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4834 if (!device
|| !pName
)
4837 int idx
= radv_get_device_entrypoint_index(pName
);
4841 return device
->dispatch
.entrypoints
[idx
];
4844 bool radv_get_memory_fd(struct radv_device
*device
,
4845 struct radv_device_memory
*memory
,
4848 struct radeon_bo_metadata metadata
;
4850 if (memory
->image
) {
4851 if (memory
->image
->tiling
!= VK_IMAGE_TILING_LINEAR
)
4852 radv_init_metadata(device
, memory
->image
, &metadata
);
4853 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
4856 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
4862 radv_free_memory(struct radv_device
*device
,
4863 const VkAllocationCallbacks
* pAllocator
,
4864 struct radv_device_memory
*mem
)
4869 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4870 if (mem
->android_hardware_buffer
)
4871 AHardwareBuffer_release(mem
->android_hardware_buffer
);
4875 if (device
->overallocation_disallowed
) {
4876 mtx_lock(&device
->overallocation_mutex
);
4877 device
->allocated_memory_size
[mem
->heap_index
] -= mem
->alloc_size
;
4878 mtx_unlock(&device
->overallocation_mutex
);
4881 radv_bo_list_remove(device
, mem
->bo
);
4882 device
->ws
->buffer_destroy(mem
->bo
);
4886 vk_object_base_finish(&mem
->base
);
4887 vk_free2(&device
->vk
.alloc
, pAllocator
, mem
);
4890 static VkResult
radv_alloc_memory(struct radv_device
*device
,
4891 const VkMemoryAllocateInfo
* pAllocateInfo
,
4892 const VkAllocationCallbacks
* pAllocator
,
4893 VkDeviceMemory
* pMem
)
4895 struct radv_device_memory
*mem
;
4897 enum radeon_bo_domain domain
;
4900 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
4902 const VkImportMemoryFdInfoKHR
*import_info
=
4903 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
4904 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
4905 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
4906 const VkExportMemoryAllocateInfo
*export_info
=
4907 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
4908 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
4909 vk_find_struct_const(pAllocateInfo
->pNext
,
4910 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
4911 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
4912 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
4914 const struct wsi_memory_allocate_info
*wsi_info
=
4915 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
4917 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
4918 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
4919 /* Apparently, this is allowed */
4920 *pMem
= VK_NULL_HANDLE
;
4924 mem
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*mem
), 8,
4925 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4927 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4929 vk_object_base_init(&device
->vk
, &mem
->base
,
4930 VK_OBJECT_TYPE_DEVICE_MEMORY
);
4932 if (wsi_info
&& wsi_info
->implicit_sync
)
4933 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4935 if (dedicate_info
) {
4936 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4937 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4943 float priority_float
= 0.5;
4944 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4945 vk_find_struct_const(pAllocateInfo
->pNext
,
4946 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4948 priority_float
= priority_ext
->priority
;
4950 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4951 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4953 mem
->user_ptr
= NULL
;
4956 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4957 mem
->android_hardware_buffer
= NULL
;
4960 if (ahb_import_info
) {
4961 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4962 if (result
!= VK_SUCCESS
)
4964 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4965 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
4966 if (result
!= VK_SUCCESS
)
4968 } else if (import_info
) {
4969 assert(import_info
->handleType
==
4970 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4971 import_info
->handleType
==
4972 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4973 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
4976 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
4979 close(import_info
->fd
);
4981 } else if (host_ptr_info
) {
4982 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
4983 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
4984 pAllocateInfo
->allocationSize
,
4987 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
4990 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
4993 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
4994 uint32_t heap_index
;
4996 heap_index
= device
->physical_device
->memory_properties
.memoryTypes
[pAllocateInfo
->memoryTypeIndex
].heapIndex
;
4997 domain
= device
->physical_device
->memory_domains
[pAllocateInfo
->memoryTypeIndex
];
4998 flags
|= device
->physical_device
->memory_flags
[pAllocateInfo
->memoryTypeIndex
];
5000 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
5001 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
5002 if (device
->use_global_bo_list
) {
5003 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
5007 if (device
->overallocation_disallowed
) {
5008 uint64_t total_size
=
5009 device
->physical_device
->memory_properties
.memoryHeaps
[heap_index
].size
;
5011 mtx_lock(&device
->overallocation_mutex
);
5012 if (device
->allocated_memory_size
[heap_index
] + alloc_size
> total_size
) {
5013 mtx_unlock(&device
->overallocation_mutex
);
5014 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5017 device
->allocated_memory_size
[heap_index
] += alloc_size
;
5018 mtx_unlock(&device
->overallocation_mutex
);
5021 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
5022 domain
, flags
, priority
);
5025 if (device
->overallocation_disallowed
) {
5026 mtx_lock(&device
->overallocation_mutex
);
5027 device
->allocated_memory_size
[heap_index
] -= alloc_size
;
5028 mtx_unlock(&device
->overallocation_mutex
);
5030 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
5034 mem
->heap_index
= heap_index
;
5035 mem
->alloc_size
= alloc_size
;
5039 result
= radv_bo_list_add(device
, mem
->bo
);
5040 if (result
!= VK_SUCCESS
)
5044 *pMem
= radv_device_memory_to_handle(mem
);
5049 radv_free_memory(device
, pAllocator
,mem
);
5054 VkResult
radv_AllocateMemory(
5056 const VkMemoryAllocateInfo
* pAllocateInfo
,
5057 const VkAllocationCallbacks
* pAllocator
,
5058 VkDeviceMemory
* pMem
)
5060 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5061 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
5064 void radv_FreeMemory(
5066 VkDeviceMemory _mem
,
5067 const VkAllocationCallbacks
* pAllocator
)
5069 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5070 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
5072 radv_free_memory(device
, pAllocator
, mem
);
5075 VkResult
radv_MapMemory(
5077 VkDeviceMemory _memory
,
5078 VkDeviceSize offset
,
5080 VkMemoryMapFlags flags
,
5083 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5084 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5092 *ppData
= mem
->user_ptr
;
5094 *ppData
= device
->ws
->buffer_map(mem
->bo
);
5101 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
5104 void radv_UnmapMemory(
5106 VkDeviceMemory _memory
)
5108 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5109 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
5114 if (mem
->user_ptr
== NULL
)
5115 device
->ws
->buffer_unmap(mem
->bo
);
5118 VkResult
radv_FlushMappedMemoryRanges(
5120 uint32_t memoryRangeCount
,
5121 const VkMappedMemoryRange
* pMemoryRanges
)
5126 VkResult
radv_InvalidateMappedMemoryRanges(
5128 uint32_t memoryRangeCount
,
5129 const VkMappedMemoryRange
* pMemoryRanges
)
5134 void radv_GetBufferMemoryRequirements(
5137 VkMemoryRequirements
* pMemoryRequirements
)
5139 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5140 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
5142 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5144 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
5145 pMemoryRequirements
->alignment
= 4096;
5147 pMemoryRequirements
->alignment
= 16;
5149 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
5152 void radv_GetBufferMemoryRequirements2(
5154 const VkBufferMemoryRequirementsInfo2
*pInfo
,
5155 VkMemoryRequirements2
*pMemoryRequirements
)
5157 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
5158 &pMemoryRequirements
->memoryRequirements
);
5159 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5160 switch (ext
->sType
) {
5161 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5162 VkMemoryDedicatedRequirements
*req
=
5163 (VkMemoryDedicatedRequirements
*) ext
;
5164 req
->requiresDedicatedAllocation
= false;
5165 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5174 void radv_GetImageMemoryRequirements(
5177 VkMemoryRequirements
* pMemoryRequirements
)
5179 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5180 RADV_FROM_HANDLE(radv_image
, image
, _image
);
5182 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
5184 pMemoryRequirements
->size
= image
->size
;
5185 pMemoryRequirements
->alignment
= image
->alignment
;
5188 void radv_GetImageMemoryRequirements2(
5190 const VkImageMemoryRequirementsInfo2
*pInfo
,
5191 VkMemoryRequirements2
*pMemoryRequirements
)
5193 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
5194 &pMemoryRequirements
->memoryRequirements
);
5196 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
5198 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
5199 switch (ext
->sType
) {
5200 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
5201 VkMemoryDedicatedRequirements
*req
=
5202 (VkMemoryDedicatedRequirements
*) ext
;
5203 req
->requiresDedicatedAllocation
= image
->shareable
&&
5204 image
->tiling
!= VK_IMAGE_TILING_LINEAR
;
5205 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
5214 void radv_GetImageSparseMemoryRequirements(
5217 uint32_t* pSparseMemoryRequirementCount
,
5218 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
5223 void radv_GetImageSparseMemoryRequirements2(
5225 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
5226 uint32_t* pSparseMemoryRequirementCount
,
5227 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
5232 void radv_GetDeviceMemoryCommitment(
5234 VkDeviceMemory memory
,
5235 VkDeviceSize
* pCommittedMemoryInBytes
)
5237 *pCommittedMemoryInBytes
= 0;
5240 VkResult
radv_BindBufferMemory2(VkDevice device
,
5241 uint32_t bindInfoCount
,
5242 const VkBindBufferMemoryInfo
*pBindInfos
)
5244 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5245 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5246 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
5249 buffer
->bo
= mem
->bo
;
5250 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
5258 VkResult
radv_BindBufferMemory(
5261 VkDeviceMemory memory
,
5262 VkDeviceSize memoryOffset
)
5264 const VkBindBufferMemoryInfo info
= {
5265 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5268 .memoryOffset
= memoryOffset
5271 return radv_BindBufferMemory2(device
, 1, &info
);
5274 VkResult
radv_BindImageMemory2(VkDevice device
,
5275 uint32_t bindInfoCount
,
5276 const VkBindImageMemoryInfo
*pBindInfos
)
5278 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5279 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
5280 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
5283 image
->bo
= mem
->bo
;
5284 image
->offset
= pBindInfos
[i
].memoryOffset
;
5294 VkResult
radv_BindImageMemory(
5297 VkDeviceMemory memory
,
5298 VkDeviceSize memoryOffset
)
5300 const VkBindImageMemoryInfo info
= {
5301 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
5304 .memoryOffset
= memoryOffset
5307 return radv_BindImageMemory2(device
, 1, &info
);
5310 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
5312 return info
->bufferBindCount
||
5313 info
->imageOpaqueBindCount
||
5314 info
->imageBindCount
||
5315 info
->waitSemaphoreCount
||
5316 info
->signalSemaphoreCount
;
5319 VkResult
radv_QueueBindSparse(
5321 uint32_t bindInfoCount
,
5322 const VkBindSparseInfo
* pBindInfo
,
5325 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
5327 uint32_t fence_idx
= 0;
5329 if (fence
!= VK_NULL_HANDLE
) {
5330 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
5331 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
5334 fence_idx
= UINT32_MAX
;
5336 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
5337 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
5340 const VkTimelineSemaphoreSubmitInfo
*timeline_info
=
5341 vk_find_struct_const(pBindInfo
[i
].pNext
, TIMELINE_SEMAPHORE_SUBMIT_INFO
);
5343 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
5344 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
5345 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
5346 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
5347 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
5348 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
5349 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
5350 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
5351 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
5352 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
5353 .wait_values
= timeline_info
? timeline_info
->pWaitSemaphoreValues
: NULL
,
5354 .wait_value_count
= timeline_info
&& timeline_info
->pWaitSemaphoreValues
? timeline_info
->waitSemaphoreValueCount
: 0,
5355 .signal_values
= timeline_info
? timeline_info
->pSignalSemaphoreValues
: NULL
,
5356 .signal_value_count
= timeline_info
&& timeline_info
->pSignalSemaphoreValues
? timeline_info
->signalSemaphoreValueCount
: 0,
5359 if (result
!= VK_SUCCESS
)
5363 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
5364 result
= radv_signal_fence(queue
, fence
);
5365 if (result
!= VK_SUCCESS
)
5373 radv_destroy_fence_part(struct radv_device
*device
,
5374 struct radv_fence_part
*part
)
5376 switch (part
->kind
) {
5377 case RADV_FENCE_NONE
:
5379 case RADV_FENCE_WINSYS
:
5380 device
->ws
->destroy_fence(part
->fence
);
5382 case RADV_FENCE_SYNCOBJ
:
5383 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5385 case RADV_FENCE_WSI
:
5386 part
->fence_wsi
->destroy(part
->fence_wsi
);
5389 unreachable("Invalid fence type");
5392 part
->kind
= RADV_FENCE_NONE
;
5396 radv_destroy_fence(struct radv_device
*device
,
5397 const VkAllocationCallbacks
*pAllocator
,
5398 struct radv_fence
*fence
)
5400 radv_destroy_fence_part(device
, &fence
->temporary
);
5401 radv_destroy_fence_part(device
, &fence
->permanent
);
5403 vk_object_base_finish(&fence
->base
);
5404 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5407 VkResult
radv_CreateFence(
5409 const VkFenceCreateInfo
* pCreateInfo
,
5410 const VkAllocationCallbacks
* pAllocator
,
5413 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5414 const VkExportFenceCreateInfo
*export
=
5415 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
5416 VkExternalFenceHandleTypeFlags handleTypes
=
5417 export
? export
->handleTypes
: 0;
5418 struct radv_fence
*fence
;
5420 fence
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*fence
), 8,
5421 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5423 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5425 vk_object_base_init(&device
->vk
, &fence
->base
, VK_OBJECT_TYPE_FENCE
);
5427 if (device
->always_use_syncobj
|| handleTypes
) {
5428 fence
->permanent
.kind
= RADV_FENCE_SYNCOBJ
;
5430 bool create_signaled
= false;
5431 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5432 create_signaled
= true;
5434 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
5435 &fence
->permanent
.syncobj
);
5437 radv_destroy_fence(device
, pAllocator
, fence
);
5438 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5441 fence
->permanent
.kind
= RADV_FENCE_WINSYS
;
5443 fence
->permanent
.fence
= device
->ws
->create_fence();
5444 if (!fence
->permanent
.fence
) {
5445 vk_free2(&device
->vk
.alloc
, pAllocator
, fence
);
5446 radv_destroy_fence(device
, pAllocator
, fence
);
5447 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5449 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
5450 device
->ws
->signal_fence(fence
->permanent
.fence
);
5453 *pFence
= radv_fence_to_handle(fence
);
5459 void radv_DestroyFence(
5462 const VkAllocationCallbacks
* pAllocator
)
5464 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5465 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5470 radv_destroy_fence(device
, pAllocator
, fence
);
5473 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
5474 uint32_t fenceCount
, const VkFence
*pFences
)
5476 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5477 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5479 struct radv_fence_part
*part
=
5480 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5481 &fence
->temporary
: &fence
->permanent
;
5482 if (part
->kind
!= RADV_FENCE_WINSYS
||
5483 !device
->ws
->is_fence_waitable(part
->fence
))
5489 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
5491 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5492 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5494 struct radv_fence_part
*part
=
5495 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5496 &fence
->temporary
: &fence
->permanent
;
5497 if (part
->kind
!= RADV_FENCE_SYNCOBJ
)
5503 VkResult
radv_WaitForFences(
5505 uint32_t fenceCount
,
5506 const VkFence
* pFences
,
5510 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5511 timeout
= radv_get_absolute_timeout(timeout
);
5513 if (device
->always_use_syncobj
&&
5514 radv_all_fences_syncobj(fenceCount
, pFences
))
5516 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
5518 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5520 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5521 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5523 struct radv_fence_part
*part
=
5524 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5525 &fence
->temporary
: &fence
->permanent
;
5527 assert(part
->kind
== RADV_FENCE_SYNCOBJ
);
5528 handles
[i
] = part
->syncobj
;
5531 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
5534 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5537 if (!waitAll
&& fenceCount
> 1) {
5538 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5539 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
5540 uint32_t wait_count
= 0;
5541 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
5543 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5545 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5546 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5548 struct radv_fence_part
*part
=
5549 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5550 &fence
->temporary
: &fence
->permanent
;
5551 assert(part
->kind
== RADV_FENCE_WINSYS
);
5553 if (device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0)) {
5558 fences
[wait_count
++] = part
->fence
;
5561 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
5562 waitAll
, timeout
- radv_get_current_time());
5565 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5568 while(radv_get_current_time() <= timeout
) {
5569 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5570 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
5577 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
5578 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5579 bool expired
= false;
5581 struct radv_fence_part
*part
=
5582 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5583 &fence
->temporary
: &fence
->permanent
;
5585 switch (part
->kind
) {
5586 case RADV_FENCE_NONE
:
5588 case RADV_FENCE_WINSYS
:
5589 if (!device
->ws
->is_fence_waitable(part
->fence
)) {
5590 while (!device
->ws
->is_fence_waitable(part
->fence
) &&
5591 radv_get_current_time() <= timeout
)
5595 expired
= device
->ws
->fence_wait(device
->ws
,
5601 case RADV_FENCE_SYNCOBJ
:
5602 if (!device
->ws
->wait_syncobj(device
->ws
,
5603 &part
->syncobj
, 1, true,
5607 case RADV_FENCE_WSI
: {
5608 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, timeout
);
5609 if (result
!= VK_SUCCESS
)
5614 unreachable("Invalid fence type");
5621 VkResult
radv_ResetFences(VkDevice _device
,
5622 uint32_t fenceCount
,
5623 const VkFence
*pFences
)
5625 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5627 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
5628 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
5630 /* From the Vulkan 1.0.53 spec:
5632 * "If any member of pFences currently has its payload
5633 * imported with temporary permanence, that fence’s prior
5634 * permanent payload is irst restored. The remaining
5635 * operations described therefore operate on the restored
5638 if (fence
->temporary
.kind
!= RADV_FENCE_NONE
)
5639 radv_destroy_fence_part(device
, &fence
->temporary
);
5641 struct radv_fence_part
*part
= &fence
->permanent
;
5643 switch (part
->kind
) {
5644 case RADV_FENCE_WSI
:
5645 device
->ws
->reset_fence(part
->fence
);
5647 case RADV_FENCE_SYNCOBJ
:
5648 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
5651 unreachable("Invalid fence type");
5658 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
5660 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5661 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
5663 struct radv_fence_part
*part
=
5664 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
5665 &fence
->temporary
: &fence
->permanent
;
5667 switch (part
->kind
) {
5668 case RADV_FENCE_NONE
:
5670 case RADV_FENCE_WINSYS
:
5671 if (!device
->ws
->fence_wait(device
->ws
, part
->fence
, false, 0))
5672 return VK_NOT_READY
;
5674 case RADV_FENCE_SYNCOBJ
: {
5675 bool success
= device
->ws
->wait_syncobj(device
->ws
,
5676 &part
->syncobj
, 1, true, 0);
5678 return VK_NOT_READY
;
5681 case RADV_FENCE_WSI
: {
5682 VkResult result
= part
->fence_wsi
->wait(part
->fence_wsi
, 0);
5683 if (result
!= VK_SUCCESS
) {
5684 if (result
== VK_TIMEOUT
)
5685 return VK_NOT_READY
;
5691 unreachable("Invalid fence type");
5698 // Queue semaphore functions
5701 radv_create_timeline(struct radv_timeline
*timeline
, uint64_t value
)
5703 timeline
->highest_signaled
= value
;
5704 timeline
->highest_submitted
= value
;
5705 list_inithead(&timeline
->points
);
5706 list_inithead(&timeline
->free_points
);
5707 list_inithead(&timeline
->waiters
);
5708 pthread_mutex_init(&timeline
->mutex
, NULL
);
5712 radv_destroy_timeline(struct radv_device
*device
,
5713 struct radv_timeline
*timeline
)
5715 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5716 &timeline
->free_points
, list
) {
5717 list_del(&point
->list
);
5718 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5721 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5722 &timeline
->points
, list
) {
5723 list_del(&point
->list
);
5724 device
->ws
->destroy_syncobj(device
->ws
, point
->syncobj
);
5727 pthread_mutex_destroy(&timeline
->mutex
);
5731 radv_timeline_gc_locked(struct radv_device
*device
,
5732 struct radv_timeline
*timeline
)
5734 list_for_each_entry_safe(struct radv_timeline_point
, point
,
5735 &timeline
->points
, list
) {
5736 if (point
->wait_count
|| point
->value
> timeline
->highest_submitted
)
5739 if (device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, 0)) {
5740 timeline
->highest_signaled
= point
->value
;
5741 list_del(&point
->list
);
5742 list_add(&point
->list
, &timeline
->free_points
);
5747 static struct radv_timeline_point
*
5748 radv_timeline_find_point_at_least_locked(struct radv_device
*device
,
5749 struct radv_timeline
*timeline
,
5752 radv_timeline_gc_locked(device
, timeline
);
5754 if (p
<= timeline
->highest_signaled
)
5757 list_for_each_entry(struct radv_timeline_point
, point
,
5758 &timeline
->points
, list
) {
5759 if (point
->value
>= p
) {
5760 ++point
->wait_count
;
5767 static struct radv_timeline_point
*
5768 radv_timeline_add_point_locked(struct radv_device
*device
,
5769 struct radv_timeline
*timeline
,
5772 radv_timeline_gc_locked(device
, timeline
);
5774 struct radv_timeline_point
*ret
= NULL
;
5775 struct radv_timeline_point
*prev
= NULL
;
5778 if (p
<= timeline
->highest_signaled
)
5781 list_for_each_entry(struct radv_timeline_point
, point
,
5782 &timeline
->points
, list
) {
5783 if (point
->value
== p
) {
5787 if (point
->value
< p
)
5791 if (list_is_empty(&timeline
->free_points
)) {
5792 ret
= malloc(sizeof(struct radv_timeline_point
));
5793 r
= device
->ws
->create_syncobj(device
->ws
, false, &ret
->syncobj
);
5799 ret
= list_first_entry(&timeline
->free_points
, struct radv_timeline_point
, list
);
5800 list_del(&ret
->list
);
5802 device
->ws
->reset_syncobj(device
->ws
, ret
->syncobj
);
5806 ret
->wait_count
= 1;
5809 list_add(&ret
->list
, &prev
->list
);
5811 list_addtail(&ret
->list
, &timeline
->points
);
5818 radv_timeline_wait_locked(struct radv_device
*device
,
5819 struct radv_timeline
*timeline
,
5821 uint64_t abs_timeout
)
5823 while(timeline
->highest_submitted
< value
) {
5824 struct timespec abstime
;
5825 timespec_from_nsec(&abstime
, abs_timeout
);
5827 pthread_cond_timedwait(&device
->timeline_cond
, &timeline
->mutex
, &abstime
);
5829 if (radv_get_current_time() >= abs_timeout
&& timeline
->highest_submitted
< value
)
5833 struct radv_timeline_point
*point
= radv_timeline_find_point_at_least_locked(device
, timeline
, value
);
5837 pthread_mutex_unlock(&timeline
->mutex
);
5839 bool success
= device
->ws
->wait_syncobj(device
->ws
, &point
->syncobj
, 1, true, abs_timeout
);
5841 pthread_mutex_lock(&timeline
->mutex
);
5842 point
->wait_count
--;
5843 return success
? VK_SUCCESS
: VK_TIMEOUT
;
5847 radv_timeline_trigger_waiters_locked(struct radv_timeline
*timeline
,
5848 struct list_head
*processing_list
)
5850 list_for_each_entry_safe(struct radv_timeline_waiter
, waiter
,
5851 &timeline
->waiters
, list
) {
5852 if (waiter
->value
> timeline
->highest_submitted
)
5855 radv_queue_trigger_submission(waiter
->submission
, 1, processing_list
);
5856 list_del(&waiter
->list
);
5861 void radv_destroy_semaphore_part(struct radv_device
*device
,
5862 struct radv_semaphore_part
*part
)
5864 switch(part
->kind
) {
5865 case RADV_SEMAPHORE_NONE
:
5867 case RADV_SEMAPHORE_WINSYS
:
5868 device
->ws
->destroy_sem(part
->ws_sem
);
5870 case RADV_SEMAPHORE_TIMELINE
:
5871 radv_destroy_timeline(device
, &part
->timeline
);
5873 case RADV_SEMAPHORE_SYNCOBJ
:
5874 device
->ws
->destroy_syncobj(device
->ws
, part
->syncobj
);
5877 part
->kind
= RADV_SEMAPHORE_NONE
;
5880 static VkSemaphoreTypeKHR
5881 radv_get_semaphore_type(const void *pNext
, uint64_t *initial_value
)
5883 const VkSemaphoreTypeCreateInfo
*type_info
=
5884 vk_find_struct_const(pNext
, SEMAPHORE_TYPE_CREATE_INFO
);
5887 return VK_SEMAPHORE_TYPE_BINARY
;
5890 *initial_value
= type_info
->initialValue
;
5891 return type_info
->semaphoreType
;
5895 radv_destroy_semaphore(struct radv_device
*device
,
5896 const VkAllocationCallbacks
*pAllocator
,
5897 struct radv_semaphore
*sem
)
5899 radv_destroy_semaphore_part(device
, &sem
->temporary
);
5900 radv_destroy_semaphore_part(device
, &sem
->permanent
);
5901 vk_object_base_finish(&sem
->base
);
5902 vk_free2(&device
->vk
.alloc
, pAllocator
, sem
);
5905 VkResult
radv_CreateSemaphore(
5907 const VkSemaphoreCreateInfo
* pCreateInfo
,
5908 const VkAllocationCallbacks
* pAllocator
,
5909 VkSemaphore
* pSemaphore
)
5911 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5912 const VkExportSemaphoreCreateInfo
*export
=
5913 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
5914 VkExternalSemaphoreHandleTypeFlags handleTypes
=
5915 export
? export
->handleTypes
: 0;
5916 uint64_t initial_value
= 0;
5917 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pCreateInfo
->pNext
, &initial_value
);
5919 struct radv_semaphore
*sem
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
5921 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5923 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5925 vk_object_base_init(&device
->vk
, &sem
->base
,
5926 VK_OBJECT_TYPE_SEMAPHORE
);
5928 sem
->temporary
.kind
= RADV_SEMAPHORE_NONE
;
5929 sem
->permanent
.kind
= RADV_SEMAPHORE_NONE
;
5931 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
5932 radv_create_timeline(&sem
->permanent
.timeline
, initial_value
);
5933 sem
->permanent
.kind
= RADV_SEMAPHORE_TIMELINE
;
5934 } else if (device
->always_use_syncobj
|| handleTypes
) {
5935 assert (device
->physical_device
->rad_info
.has_syncobj
);
5936 int ret
= device
->ws
->create_syncobj(device
->ws
, false,
5937 &sem
->permanent
.syncobj
);
5939 radv_destroy_semaphore(device
, pAllocator
, sem
);
5940 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5942 sem
->permanent
.kind
= RADV_SEMAPHORE_SYNCOBJ
;
5944 sem
->permanent
.ws_sem
= device
->ws
->create_sem(device
->ws
);
5945 if (!sem
->permanent
.ws_sem
) {
5946 radv_destroy_semaphore(device
, pAllocator
, sem
);
5947 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5949 sem
->permanent
.kind
= RADV_SEMAPHORE_WINSYS
;
5952 *pSemaphore
= radv_semaphore_to_handle(sem
);
5956 void radv_DestroySemaphore(
5958 VkSemaphore _semaphore
,
5959 const VkAllocationCallbacks
* pAllocator
)
5961 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5962 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
5966 radv_destroy_semaphore(device
, pAllocator
, sem
);
5970 radv_GetSemaphoreCounterValue(VkDevice _device
,
5971 VkSemaphore _semaphore
,
5974 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5975 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, _semaphore
);
5977 struct radv_semaphore_part
*part
=
5978 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
5980 switch (part
->kind
) {
5981 case RADV_SEMAPHORE_TIMELINE
: {
5982 pthread_mutex_lock(&part
->timeline
.mutex
);
5983 radv_timeline_gc_locked(device
, &part
->timeline
);
5984 *pValue
= part
->timeline
.highest_signaled
;
5985 pthread_mutex_unlock(&part
->timeline
.mutex
);
5988 case RADV_SEMAPHORE_NONE
:
5989 case RADV_SEMAPHORE_SYNCOBJ
:
5990 case RADV_SEMAPHORE_WINSYS
:
5991 unreachable("Invalid semaphore type");
5993 unreachable("Unhandled semaphore type");
5998 radv_wait_timelines(struct radv_device
*device
,
5999 const VkSemaphoreWaitInfo
* pWaitInfo
,
6000 uint64_t abs_timeout
)
6002 if ((pWaitInfo
->flags
& VK_SEMAPHORE_WAIT_ANY_BIT_KHR
) && pWaitInfo
->semaphoreCount
> 1) {
6004 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6005 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6006 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
6007 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], 0);
6008 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
6010 if (result
== VK_SUCCESS
)
6013 if (radv_get_current_time() > abs_timeout
)
6018 for(uint32_t i
= 0; i
< pWaitInfo
->semaphoreCount
; ++i
) {
6019 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pWaitInfo
->pSemaphores
[i
]);
6020 pthread_mutex_lock(&semaphore
->permanent
.timeline
.mutex
);
6021 VkResult result
= radv_timeline_wait_locked(device
, &semaphore
->permanent
.timeline
, pWaitInfo
->pValues
[i
], abs_timeout
);
6022 pthread_mutex_unlock(&semaphore
->permanent
.timeline
.mutex
);
6024 if (result
!= VK_SUCCESS
)
6030 radv_WaitSemaphores(VkDevice _device
,
6031 const VkSemaphoreWaitInfo
* pWaitInfo
,
6034 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6035 uint64_t abs_timeout
= radv_get_absolute_timeout(timeout
);
6036 return radv_wait_timelines(device
, pWaitInfo
, abs_timeout
);
6040 radv_SignalSemaphore(VkDevice _device
,
6041 const VkSemaphoreSignalInfo
* pSignalInfo
)
6043 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6044 RADV_FROM_HANDLE(radv_semaphore
, semaphore
, pSignalInfo
->semaphore
);
6046 struct radv_semaphore_part
*part
=
6047 semaphore
->temporary
.kind
!= RADV_SEMAPHORE_NONE
? &semaphore
->temporary
: &semaphore
->permanent
;
6049 switch(part
->kind
) {
6050 case RADV_SEMAPHORE_TIMELINE
: {
6051 pthread_mutex_lock(&part
->timeline
.mutex
);
6052 radv_timeline_gc_locked(device
, &part
->timeline
);
6053 part
->timeline
.highest_submitted
= MAX2(part
->timeline
.highest_submitted
, pSignalInfo
->value
);
6054 part
->timeline
.highest_signaled
= MAX2(part
->timeline
.highest_signaled
, pSignalInfo
->value
);
6056 struct list_head processing_list
;
6057 list_inithead(&processing_list
);
6058 radv_timeline_trigger_waiters_locked(&part
->timeline
, &processing_list
);
6059 pthread_mutex_unlock(&part
->timeline
.mutex
);
6061 return radv_process_submissions(&processing_list
);
6063 case RADV_SEMAPHORE_NONE
:
6064 case RADV_SEMAPHORE_SYNCOBJ
:
6065 case RADV_SEMAPHORE_WINSYS
:
6066 unreachable("Invalid semaphore type");
6071 static void radv_destroy_event(struct radv_device
*device
,
6072 const VkAllocationCallbacks
* pAllocator
,
6073 struct radv_event
*event
)
6076 device
->ws
->buffer_destroy(event
->bo
);
6078 vk_object_base_finish(&event
->base
);
6079 vk_free2(&device
->vk
.alloc
, pAllocator
, event
);
6082 VkResult
radv_CreateEvent(
6084 const VkEventCreateInfo
* pCreateInfo
,
6085 const VkAllocationCallbacks
* pAllocator
,
6088 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6089 struct radv_event
*event
= vk_alloc2(&device
->vk
.alloc
, pAllocator
,
6091 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6094 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6096 vk_object_base_init(&device
->vk
, &event
->base
, VK_OBJECT_TYPE_EVENT
);
6098 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
6100 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
6101 RADV_BO_PRIORITY_FENCE
);
6103 radv_destroy_event(device
, pAllocator
, event
);
6104 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6107 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
6109 radv_destroy_event(device
, pAllocator
, event
);
6110 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6113 *pEvent
= radv_event_to_handle(event
);
6118 void radv_DestroyEvent(
6121 const VkAllocationCallbacks
* pAllocator
)
6123 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6124 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6129 radv_destroy_event(device
, pAllocator
, event
);
6132 VkResult
radv_GetEventStatus(
6136 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6138 if (*event
->map
== 1)
6139 return VK_EVENT_SET
;
6140 return VK_EVENT_RESET
;
6143 VkResult
radv_SetEvent(
6147 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6153 VkResult
radv_ResetEvent(
6157 RADV_FROM_HANDLE(radv_event
, event
, _event
);
6164 radv_destroy_buffer(struct radv_device
*device
,
6165 const VkAllocationCallbacks
*pAllocator
,
6166 struct radv_buffer
*buffer
)
6168 if ((buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) && buffer
->bo
)
6169 device
->ws
->buffer_destroy(buffer
->bo
);
6171 vk_object_base_finish(&buffer
->base
);
6172 vk_free2(&device
->vk
.alloc
, pAllocator
, buffer
);
6175 VkResult
radv_CreateBuffer(
6177 const VkBufferCreateInfo
* pCreateInfo
,
6178 const VkAllocationCallbacks
* pAllocator
,
6181 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6182 struct radv_buffer
*buffer
;
6184 if (pCreateInfo
->size
> RADV_MAX_MEMORY_ALLOCATION_SIZE
)
6185 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
6187 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
6189 buffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*buffer
), 8,
6190 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6192 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6194 vk_object_base_init(&device
->vk
, &buffer
->base
, VK_OBJECT_TYPE_BUFFER
);
6196 buffer
->size
= pCreateInfo
->size
;
6197 buffer
->usage
= pCreateInfo
->usage
;
6200 buffer
->flags
= pCreateInfo
->flags
;
6202 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
6203 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
6205 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
6206 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
6207 align64(buffer
->size
, 4096),
6208 4096, 0, RADEON_FLAG_VIRTUAL
,
6209 RADV_BO_PRIORITY_VIRTUAL
);
6211 radv_destroy_buffer(device
, pAllocator
, buffer
);
6212 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
6216 *pBuffer
= radv_buffer_to_handle(buffer
);
6221 void radv_DestroyBuffer(
6224 const VkAllocationCallbacks
* pAllocator
)
6226 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6227 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
6232 radv_destroy_buffer(device
, pAllocator
, buffer
);
6235 VkDeviceAddress
radv_GetBufferDeviceAddress(
6237 const VkBufferDeviceAddressInfo
* pInfo
)
6239 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
6240 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
6244 uint64_t radv_GetBufferOpaqueCaptureAddress(VkDevice device
,
6245 const VkBufferDeviceAddressInfo
* pInfo
)
6250 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddress(VkDevice device
,
6251 const VkDeviceMemoryOpaqueCaptureAddressInfo
* pInfo
)
6256 static inline unsigned
6257 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
6260 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
6262 return plane
->surface
.u
.legacy
.tiling_index
[level
];
6265 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
6267 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
6271 radv_init_dcc_control_reg(struct radv_device
*device
,
6272 struct radv_image_view
*iview
)
6274 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
6275 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
6276 unsigned max_compressed_block_size
;
6277 unsigned independent_128b_blocks
;
6278 unsigned independent_64b_blocks
;
6280 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6283 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
6284 /* amdvlk: [min-compressed-block-size] should be set to 32 for
6285 * dGPU and 64 for APU because all of our APUs to date use
6286 * DIMMs which have a request granularity size of 64B while all
6287 * other chips have a 32B request size.
6289 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
6292 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6293 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6294 independent_64b_blocks
= 0;
6295 independent_128b_blocks
= 1;
6297 independent_128b_blocks
= 0;
6299 if (iview
->image
->info
.samples
> 1) {
6300 if (iview
->image
->planes
[0].surface
.bpe
== 1)
6301 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6302 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
6303 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
6306 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
6307 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
6308 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
6309 /* If this DCC image is potentially going to be used in texture
6310 * fetches, we need some special settings.
6312 independent_64b_blocks
= 1;
6313 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
6315 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6316 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6317 * big as possible for better compression state.
6319 independent_64b_blocks
= 0;
6320 max_compressed_block_size
= max_uncompressed_block_size
;
6324 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
6325 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
6326 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
6327 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
6328 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
6332 radv_initialise_color_surface(struct radv_device
*device
,
6333 struct radv_color_buffer_info
*cb
,
6334 struct radv_image_view
*iview
)
6336 const struct vk_format_description
*desc
;
6337 unsigned ntype
, format
, swap
, endian
;
6338 unsigned blend_clamp
= 0, blend_bypass
= 0;
6340 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
6341 const struct radeon_surf
*surf
= &plane
->surface
;
6343 desc
= vk_format_description(iview
->vk_format
);
6345 memset(cb
, 0, sizeof(*cb
));
6347 /* Intensity is implemented as Red, so treat it that way. */
6348 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
6350 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
6352 cb
->cb_color_base
= va
>> 8;
6354 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6355 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6356 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6357 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6358 S_028EE0_CMASK_PIPE_ALIGNED(1) |
6359 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
6361 struct gfx9_surf_meta_flags meta
= {
6366 if (surf
->dcc_offset
)
6367 meta
= surf
->u
.gfx9
.dcc
;
6369 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6370 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
6371 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
6372 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
6373 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6376 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
6377 cb
->cb_color_base
|= surf
->tile_swizzle
;
6379 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
6380 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
6382 cb
->cb_color_base
+= level_info
->offset
>> 8;
6383 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
6384 cb
->cb_color_base
|= surf
->tile_swizzle
;
6386 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
6387 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
6388 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
6390 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
6391 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
6392 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
6394 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
6396 if (radv_image_has_fmask(iview
->image
)) {
6397 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6398 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
6399 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
6400 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
6402 /* This must be set for fast clear to work without FMASK. */
6403 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
6404 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
6405 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
6406 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
6410 /* CMASK variables */
6411 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6412 va
+= surf
->cmask_offset
;
6413 cb
->cb_color_cmask
= va
>> 8;
6415 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6416 va
+= surf
->dcc_offset
;
6418 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
6419 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
6420 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
6422 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
6423 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
6425 cb
->cb_dcc_base
= va
>> 8;
6426 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
6428 /* GFX10 field has the same base shift as the GFX6 field. */
6429 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6430 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
6431 S_028C6C_SLICE_MAX_GFX10(max_slice
);
6433 if (iview
->image
->info
.samples
> 1) {
6434 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
6436 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
6437 S_028C74_NUM_FRAGMENTS(log_samples
);
6440 if (radv_image_has_fmask(iview
->image
)) {
6441 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ surf
->fmask_offset
;
6442 cb
->cb_color_fmask
= va
>> 8;
6443 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
6445 cb
->cb_color_fmask
= cb
->cb_color_base
;
6448 ntype
= radv_translate_color_numformat(iview
->vk_format
,
6450 vk_format_get_first_non_void_channel(iview
->vk_format
));
6451 format
= radv_translate_colorformat(iview
->vk_format
);
6452 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
6453 radv_finishme("Illegal color\n");
6454 swap
= radv_translate_colorswap(iview
->vk_format
, false);
6455 endian
= radv_colorformat_endian_swap(format
);
6457 /* blend clamp should be set for all NORM/SRGB types */
6458 if (ntype
== V_028C70_NUMBER_UNORM
||
6459 ntype
== V_028C70_NUMBER_SNORM
||
6460 ntype
== V_028C70_NUMBER_SRGB
)
6463 /* set blend bypass according to docs if SINT/UINT or
6464 8/24 COLOR variants */
6465 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
6466 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
6467 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
6472 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
6473 (format
== V_028C70_COLOR_8
||
6474 format
== V_028C70_COLOR_8_8
||
6475 format
== V_028C70_COLOR_8_8_8_8
))
6476 ->color_is_int8
= true;
6478 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
6479 S_028C70_COMP_SWAP(swap
) |
6480 S_028C70_BLEND_CLAMP(blend_clamp
) |
6481 S_028C70_BLEND_BYPASS(blend_bypass
) |
6482 S_028C70_SIMPLE_FLOAT(1) |
6483 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
6484 ntype
!= V_028C70_NUMBER_SNORM
&&
6485 ntype
!= V_028C70_NUMBER_SRGB
&&
6486 format
!= V_028C70_COLOR_8_24
&&
6487 format
!= V_028C70_COLOR_24_8
) |
6488 S_028C70_NUMBER_TYPE(ntype
) |
6489 S_028C70_ENDIAN(endian
);
6490 if (radv_image_has_fmask(iview
->image
)) {
6491 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
6492 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6493 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
6494 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
6497 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
6498 /* Allow the texture block to read FMASK directly
6499 * without decompressing it. This bit must be cleared
6500 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6501 * otherwise the operation doesn't happen.
6503 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6505 /* Set CMASK into a tiling format that allows the
6506 * texture block to read it.
6508 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
6512 if (radv_image_has_cmask(iview
->image
) &&
6513 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
6514 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
6516 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
6517 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
6519 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
6521 /* This must be set for fast clear to work without FMASK. */
6522 if (!radv_image_has_fmask(iview
->image
) &&
6523 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
6524 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
6525 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
6528 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6529 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
6531 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
6532 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
6533 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
6534 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
6536 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6537 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
6539 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
6540 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
6541 S_028EE0_RESOURCE_LEVEL(1);
6543 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
6544 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
6545 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
6548 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
6549 S_028C68_MIP0_HEIGHT(height
- 1) |
6550 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
6555 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
6556 struct radv_image_view
*iview
)
6558 unsigned max_zplanes
= 0;
6560 assert(radv_image_is_tc_compat_htile(iview
->image
));
6562 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6563 /* Default value for 32-bit depth surfaces. */
6566 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
6567 iview
->image
->info
.samples
> 1)
6570 max_zplanes
= max_zplanes
+ 1;
6572 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
6573 /* Do not enable Z plane compression for 16-bit depth
6574 * surfaces because isn't supported on GFX8. Only
6575 * 32-bit depth surfaces are supported by the hardware.
6576 * This allows to maintain shader compatibility and to
6577 * reduce the number of depth decompressions.
6581 if (iview
->image
->info
.samples
<= 1)
6583 else if (iview
->image
->info
.samples
<= 4)
6594 radv_initialise_ds_surface(struct radv_device
*device
,
6595 struct radv_ds_buffer_info
*ds
,
6596 struct radv_image_view
*iview
)
6598 unsigned level
= iview
->base_mip
;
6599 unsigned format
, stencil_format
;
6600 uint64_t va
, s_offs
, z_offs
;
6601 bool stencil_only
= false;
6602 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
6603 const struct radeon_surf
*surf
= &plane
->surface
;
6605 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
6607 memset(ds
, 0, sizeof(*ds
));
6608 switch (iview
->image
->vk_format
) {
6609 case VK_FORMAT_D24_UNORM_S8_UINT
:
6610 case VK_FORMAT_X8_D24_UNORM_PACK32
:
6611 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6612 ds
->offset_scale
= 2.0f
;
6614 case VK_FORMAT_D16_UNORM
:
6615 case VK_FORMAT_D16_UNORM_S8_UINT
:
6616 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6617 ds
->offset_scale
= 4.0f
;
6619 case VK_FORMAT_D32_SFLOAT
:
6620 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
6621 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6622 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6623 ds
->offset_scale
= 1.0f
;
6625 case VK_FORMAT_S8_UINT
:
6626 stencil_only
= true;
6632 format
= radv_translate_dbformat(iview
->image
->vk_format
);
6633 stencil_format
= surf
->has_stencil
?
6634 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
6636 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
6637 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
6638 S_028008_SLICE_MAX(max_slice
);
6639 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6640 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
6641 S_028008_SLICE_MAX_HI(max_slice
>> 11);
6644 ds
->db_htile_data_base
= 0;
6645 ds
->db_htile_surface
= 0;
6647 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
6648 s_offs
= z_offs
= va
;
6650 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
6651 assert(surf
->u
.gfx9
.surf_offset
== 0);
6652 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
6654 ds
->db_z_info
= S_028038_FORMAT(format
) |
6655 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
6656 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
6657 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
6658 S_028038_ZRANGE_PRECISION(1);
6659 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
6660 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
6662 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6663 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
6664 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
6667 ds
->db_depth_view
|= S_028008_MIPID(level
);
6668 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
6669 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
6671 if (radv_htile_enabled(iview
->image
, level
)) {
6672 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
6674 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6675 unsigned max_zplanes
=
6676 radv_calc_decompress_on_z_planes(device
, iview
);
6678 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6680 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
6681 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
6682 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
6684 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
6685 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
6689 if (!surf
->has_stencil
)
6690 /* Use all of the htile_buffer for depth if there's no stencil. */
6691 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
6692 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6694 ds
->db_htile_data_base
= va
>> 8;
6695 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
6696 S_028ABC_PIPE_ALIGNED(1);
6698 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
6699 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(1);
6703 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
6706 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
6708 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
6709 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
6711 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
6712 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
6713 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
6715 if (iview
->image
->info
.samples
> 1)
6716 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
6718 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
6719 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
6720 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
6721 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
6722 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
6723 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
6724 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
6725 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
6728 tile_mode
= stencil_tile_mode
;
6730 ds
->db_depth_info
|=
6731 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
6732 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
6733 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
6734 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
6735 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
6736 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
6737 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
6738 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
6740 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
6741 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6742 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
6743 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
6745 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
6748 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
6749 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
6750 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
6752 if (radv_htile_enabled(iview
->image
, level
)) {
6753 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
6755 if (!surf
->has_stencil
&&
6756 !radv_image_is_tc_compat_htile(iview
->image
))
6757 /* Use all of the htile_buffer for depth if there's no stencil. */
6758 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
6760 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
6762 ds
->db_htile_data_base
= va
>> 8;
6763 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
6765 if (radv_image_is_tc_compat_htile(iview
->image
)) {
6766 unsigned max_zplanes
=
6767 radv_calc_decompress_on_z_planes(device
, iview
);
6769 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
6770 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
6775 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
6776 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
6779 VkResult
radv_CreateFramebuffer(
6781 const VkFramebufferCreateInfo
* pCreateInfo
,
6782 const VkAllocationCallbacks
* pAllocator
,
6783 VkFramebuffer
* pFramebuffer
)
6785 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6786 struct radv_framebuffer
*framebuffer
;
6787 const VkFramebufferAttachmentsCreateInfo
*imageless_create_info
=
6788 vk_find_struct_const(pCreateInfo
->pNext
,
6789 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO
);
6791 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
6793 size_t size
= sizeof(*framebuffer
);
6794 if (!imageless_create_info
)
6795 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
6796 framebuffer
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, size
, 8,
6797 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
6798 if (framebuffer
== NULL
)
6799 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
6801 vk_object_base_init(&device
->vk
, &framebuffer
->base
,
6802 VK_OBJECT_TYPE_FRAMEBUFFER
);
6804 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
6805 framebuffer
->width
= pCreateInfo
->width
;
6806 framebuffer
->height
= pCreateInfo
->height
;
6807 framebuffer
->layers
= pCreateInfo
->layers
;
6808 if (imageless_create_info
) {
6809 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
6810 const VkFramebufferAttachmentImageInfo
*attachment
=
6811 imageless_create_info
->pAttachmentImageInfos
+ i
;
6812 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
6813 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
6814 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
6817 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
6818 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
6819 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
6820 framebuffer
->attachments
[i
] = iview
;
6821 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
6822 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
6823 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
6827 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
6831 void radv_DestroyFramebuffer(
6834 const VkAllocationCallbacks
* pAllocator
)
6836 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6837 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
6841 vk_object_base_finish(&fb
->base
);
6842 vk_free2(&device
->vk
.alloc
, pAllocator
, fb
);
6845 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
6847 switch (address_mode
) {
6848 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
6849 return V_008F30_SQ_TEX_WRAP
;
6850 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
6851 return V_008F30_SQ_TEX_MIRROR
;
6852 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
6853 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
6854 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
6855 return V_008F30_SQ_TEX_CLAMP_BORDER
;
6856 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
6857 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
6859 unreachable("illegal tex wrap mode");
6865 radv_tex_compare(VkCompareOp op
)
6868 case VK_COMPARE_OP_NEVER
:
6869 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
6870 case VK_COMPARE_OP_LESS
:
6871 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
6872 case VK_COMPARE_OP_EQUAL
:
6873 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
6874 case VK_COMPARE_OP_LESS_OR_EQUAL
:
6875 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
6876 case VK_COMPARE_OP_GREATER
:
6877 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
6878 case VK_COMPARE_OP_NOT_EQUAL
:
6879 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
6880 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
6881 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
6882 case VK_COMPARE_OP_ALWAYS
:
6883 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
6885 unreachable("illegal compare mode");
6891 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
6894 case VK_FILTER_NEAREST
:
6895 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
6896 V_008F38_SQ_TEX_XY_FILTER_POINT
);
6897 case VK_FILTER_LINEAR
:
6898 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
6899 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
6900 case VK_FILTER_CUBIC_IMG
:
6902 fprintf(stderr
, "illegal texture filter");
6908 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
6911 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
6912 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
6913 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
6914 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
6916 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
6921 radv_tex_bordercolor(VkBorderColor bcolor
)
6924 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
6925 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
6926 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
6927 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
6928 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
6929 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
6930 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
6931 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
6932 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
6933 case VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
:
6934 case VK_BORDER_COLOR_INT_CUSTOM_EXT
:
6935 return V_008F3C_SQ_TEX_BORDER_COLOR_REGISTER
;
6943 radv_tex_aniso_filter(unsigned filter
)
6957 radv_tex_filter_mode(VkSamplerReductionMode mode
)
6960 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
6961 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
6962 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
6963 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
6964 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
6965 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
6973 radv_get_max_anisotropy(struct radv_device
*device
,
6974 const VkSamplerCreateInfo
*pCreateInfo
)
6976 if (device
->force_aniso
>= 0)
6977 return device
->force_aniso
;
6979 if (pCreateInfo
->anisotropyEnable
&&
6980 pCreateInfo
->maxAnisotropy
> 1.0f
)
6981 return (uint32_t)pCreateInfo
->maxAnisotropy
;
6986 static inline int S_FIXED(float value
, unsigned frac_bits
)
6988 return value
* (1 << frac_bits
);
6991 static uint32_t radv_register_border_color(struct radv_device
*device
,
6992 VkClearColorValue value
)
6996 pthread_mutex_lock(&device
->border_color_data
.mutex
);
6998 for (slot
= 0; slot
< RADV_BORDER_COLOR_COUNT
; slot
++) {
6999 if (!device
->border_color_data
.used
[slot
]) {
7000 /* Copy to the GPU wrt endian-ness. */
7001 util_memcpy_cpu_to_le32(&device
->border_color_data
.colors_gpu_ptr
[slot
],
7003 sizeof(VkClearColorValue
));
7005 device
->border_color_data
.used
[slot
] = true;
7010 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
7015 static void radv_unregister_border_color(struct radv_device
*device
,
7018 pthread_mutex_lock(&device
->border_color_data
.mutex
);
7020 device
->border_color_data
.used
[slot
] = false;
7022 pthread_mutex_unlock(&device
->border_color_data
.mutex
);
7026 radv_init_sampler(struct radv_device
*device
,
7027 struct radv_sampler
*sampler
,
7028 const VkSamplerCreateInfo
*pCreateInfo
)
7030 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
7031 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
7032 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
7033 device
->physical_device
->rad_info
.chip_class
== GFX9
;
7034 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
7035 unsigned depth_compare_func
= V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
7036 bool trunc_coord
= pCreateInfo
->minFilter
== VK_FILTER_NEAREST
&& pCreateInfo
->magFilter
== VK_FILTER_NEAREST
;
7037 bool uses_border_color
= pCreateInfo
->addressModeU
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
7038 pCreateInfo
->addressModeV
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
||
7039 pCreateInfo
->addressModeW
== VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
;
7040 VkBorderColor border_color
= uses_border_color
? pCreateInfo
->borderColor
: VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
7041 uint32_t border_color_ptr
;
7043 const struct VkSamplerReductionModeCreateInfo
*sampler_reduction
=
7044 vk_find_struct_const(pCreateInfo
->pNext
,
7045 SAMPLER_REDUCTION_MODE_CREATE_INFO
);
7046 if (sampler_reduction
)
7047 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
7049 if (pCreateInfo
->compareEnable
)
7050 depth_compare_func
= radv_tex_compare(pCreateInfo
->compareOp
);
7052 sampler
->border_color_slot
= RADV_BORDER_COLOR_COUNT
;
7054 if (border_color
== VK_BORDER_COLOR_FLOAT_CUSTOM_EXT
|| border_color
== VK_BORDER_COLOR_INT_CUSTOM_EXT
) {
7055 const VkSamplerCustomBorderColorCreateInfoEXT
*custom_border_color
=
7056 vk_find_struct_const(pCreateInfo
->pNext
,
7057 SAMPLER_CUSTOM_BORDER_COLOR_CREATE_INFO_EXT
);
7059 assert(custom_border_color
);
7061 sampler
->border_color_slot
=
7062 radv_register_border_color(device
, custom_border_color
->customBorderColor
);
7064 /* Did we fail to find a slot? */
7065 if (sampler
->border_color_slot
== RADV_BORDER_COLOR_COUNT
) {
7066 fprintf(stderr
, "WARNING: no free border color slots, defaulting to TRANS_BLACK.\n");
7067 border_color
= VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
;
7071 /* If we don't have a custom color, set the ptr to 0 */
7072 border_color_ptr
= sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
7073 ? sampler
->border_color_slot
7076 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
7077 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
7078 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
7079 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
7080 S_008F30_DEPTH_COMPARE_FUNC(depth_compare_func
) |
7081 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
7082 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
7083 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
7084 S_008F30_DISABLE_CUBE_WRAP(0) |
7085 S_008F30_COMPAT_MODE(compat_mode
) |
7086 S_008F30_FILTER_MODE(filter_mode
) |
7087 S_008F30_TRUNC_COORD(trunc_coord
));
7088 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
7089 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
7090 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
7091 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
7092 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
7093 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
7094 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
7095 S_008F38_MIP_POINT_PRECLAMP(0));
7096 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(border_color_ptr
) |
7097 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(border_color
)));
7099 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
7100 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
7102 sampler
->state
[2] |=
7103 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
7104 S_008F38_FILTER_PREC_FIX(1) |
7105 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
7109 VkResult
radv_CreateSampler(
7111 const VkSamplerCreateInfo
* pCreateInfo
,
7112 const VkAllocationCallbacks
* pAllocator
,
7113 VkSampler
* pSampler
)
7115 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7116 struct radv_sampler
*sampler
;
7118 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
7119 vk_find_struct_const(pCreateInfo
->pNext
,
7120 SAMPLER_YCBCR_CONVERSION_INFO
);
7122 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
7124 sampler
= vk_alloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*sampler
), 8,
7125 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
7127 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7129 vk_object_base_init(&device
->vk
, &sampler
->base
,
7130 VK_OBJECT_TYPE_SAMPLER
);
7132 radv_init_sampler(device
, sampler
, pCreateInfo
);
7134 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
7135 *pSampler
= radv_sampler_to_handle(sampler
);
7140 void radv_DestroySampler(
7143 const VkAllocationCallbacks
* pAllocator
)
7145 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7146 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
7151 if (sampler
->border_color_slot
!= RADV_BORDER_COLOR_COUNT
)
7152 radv_unregister_border_color(device
, sampler
->border_color_slot
);
7154 vk_object_base_finish(&sampler
->base
);
7155 vk_free2(&device
->vk
.alloc
, pAllocator
, sampler
);
7158 /* vk_icd.h does not declare this function, so we declare it here to
7159 * suppress Wmissing-prototypes.
7161 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7162 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
7164 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
7165 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
7167 /* For the full details on loader interface versioning, see
7168 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
7169 * What follows is a condensed summary, to help you navigate the large and
7170 * confusing official doc.
7172 * - Loader interface v0 is incompatible with later versions. We don't
7175 * - In loader interface v1:
7176 * - The first ICD entrypoint called by the loader is
7177 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
7179 * - The ICD must statically expose no other Vulkan symbol unless it is
7180 * linked with -Bsymbolic.
7181 * - Each dispatchable Vulkan handle created by the ICD must be
7182 * a pointer to a struct whose first member is VK_LOADER_DATA. The
7183 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
7184 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
7185 * vkDestroySurfaceKHR(). The ICD must be capable of working with
7186 * such loader-managed surfaces.
7188 * - Loader interface v2 differs from v1 in:
7189 * - The first ICD entrypoint called by the loader is
7190 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
7191 * statically expose this entrypoint.
7193 * - Loader interface v3 differs from v2 in:
7194 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
7195 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
7196 * because the loader no longer does so.
7198 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
7202 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
7203 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
7206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7207 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
7209 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
7211 /* At the moment, we support only the below handle types. */
7212 assert(pGetFdInfo
->handleType
==
7213 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
7214 pGetFdInfo
->handleType
==
7215 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
7217 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
7219 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
7223 static uint32_t radv_compute_valid_memory_types_attempt(struct radv_physical_device
*dev
,
7224 enum radeon_bo_domain domains
,
7225 enum radeon_bo_flag flags
,
7226 enum radeon_bo_flag ignore_flags
)
7228 /* Don't count GTT/CPU as relevant:
7230 * - We're not fully consistent between the two.
7231 * - Sometimes VRAM gets VRAM|GTT.
7233 const enum radeon_bo_domain relevant_domains
= RADEON_DOMAIN_VRAM
|
7237 for (unsigned i
= 0; i
< dev
->memory_properties
.memoryTypeCount
; ++i
) {
7238 if ((domains
& relevant_domains
) != (dev
->memory_domains
[i
] & relevant_domains
))
7241 if ((flags
& ~ignore_flags
) != (dev
->memory_flags
[i
] & ~ignore_flags
))
7250 static uint32_t radv_compute_valid_memory_types(struct radv_physical_device
*dev
,
7251 enum radeon_bo_domain domains
,
7252 enum radeon_bo_flag flags
)
7254 enum radeon_bo_flag ignore_flags
= ~(RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_GTT_WC
);
7255 uint32_t bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7258 ignore_flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
7259 bits
= radv_compute_valid_memory_types_attempt(dev
, domains
, flags
, ignore_flags
);
7264 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
7265 VkExternalMemoryHandleTypeFlagBits handleType
,
7267 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
7269 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7271 switch (handleType
) {
7272 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
: {
7273 enum radeon_bo_domain domains
;
7274 enum radeon_bo_flag flags
;
7275 if (!device
->ws
->buffer_get_flags_from_fd(device
->ws
, fd
, &domains
, &flags
))
7276 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7278 pMemoryFdProperties
->memoryTypeBits
= radv_compute_valid_memory_types(device
->physical_device
, domains
, flags
);
7282 /* The valid usage section for this function says:
7284 * "handleType must not be one of the handle types defined as
7287 * So opaque handle types fall into the default "unsupported" case.
7289 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7293 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
7297 uint32_t syncobj_handle
= 0;
7298 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
7300 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7303 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
7305 *syncobj
= syncobj_handle
;
7311 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
7315 /* If we create a syncobj we do it locally so that if we have an error, we don't
7316 * leave a syncobj in an undetermined state in the fence. */
7317 uint32_t syncobj_handle
= *syncobj
;
7318 if (!syncobj_handle
) {
7319 bool create_signaled
= fd
== -1 ? true : false;
7321 int ret
= device
->ws
->create_syncobj(device
->ws
, create_signaled
,
7324 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
7328 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
7332 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
7334 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
7338 *syncobj
= syncobj_handle
;
7343 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
7344 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
7346 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7347 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
7349 struct radv_semaphore_part
*dst
= NULL
;
7351 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
7352 dst
= &sem
->temporary
;
7354 dst
= &sem
->permanent
;
7357 uint32_t syncobj
= dst
->kind
== RADV_SEMAPHORE_SYNCOBJ
? dst
->syncobj
: 0;
7359 switch(pImportSemaphoreFdInfo
->handleType
) {
7360 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7361 result
= radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7363 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7364 result
= radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, &syncobj
);
7367 unreachable("Unhandled semaphore handle type");
7370 if (result
== VK_SUCCESS
) {
7371 dst
->syncobj
= syncobj
;
7372 dst
->kind
= RADV_SEMAPHORE_SYNCOBJ
;
7378 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
7379 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
7382 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7383 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
7385 uint32_t syncobj_handle
;
7387 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7388 assert(sem
->temporary
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7389 syncobj_handle
= sem
->temporary
.syncobj
;
7391 assert(sem
->permanent
.kind
== RADV_SEMAPHORE_SYNCOBJ
);
7392 syncobj_handle
= sem
->permanent
.syncobj
;
7395 switch(pGetFdInfo
->handleType
) {
7396 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7397 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
7399 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7401 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
7402 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
7404 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7406 if (sem
->temporary
.kind
!= RADV_SEMAPHORE_NONE
) {
7407 radv_destroy_semaphore_part(device
, &sem
->temporary
);
7409 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
7413 unreachable("Unhandled semaphore handle type");
7419 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
7420 VkPhysicalDevice physicalDevice
,
7421 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
7422 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
7424 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7425 VkSemaphoreTypeKHR type
= radv_get_semaphore_type(pExternalSemaphoreInfo
->pNext
, NULL
);
7427 if (type
== VK_SEMAPHORE_TYPE_TIMELINE
) {
7428 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7429 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7430 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7432 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
7433 } else if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7434 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7435 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7436 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7437 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
7438 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7439 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7440 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
7441 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7442 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
7443 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
7444 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7446 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
7447 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
7448 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
7452 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
7453 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
7455 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7456 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
7457 struct radv_fence_part
*dst
= NULL
;
7460 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
7461 dst
= &fence
->temporary
;
7463 dst
= &fence
->permanent
;
7466 uint32_t syncobj
= dst
->kind
== RADV_FENCE_SYNCOBJ
? dst
->syncobj
: 0;
7468 switch(pImportFenceFdInfo
->handleType
) {
7469 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7470 result
= radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7472 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7473 result
= radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, &syncobj
);
7476 unreachable("Unhandled fence handle type");
7479 if (result
== VK_SUCCESS
) {
7480 dst
->syncobj
= syncobj
;
7481 dst
->kind
= RADV_FENCE_SYNCOBJ
;
7487 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
7488 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
7491 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7492 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
7495 struct radv_fence_part
*part
=
7496 fence
->temporary
.kind
!= RADV_FENCE_NONE
?
7497 &fence
->temporary
: &fence
->permanent
;
7499 switch(pGetFdInfo
->handleType
) {
7500 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
7501 ret
= device
->ws
->export_syncobj(device
->ws
, part
->syncobj
, pFd
);
7503 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7505 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
7506 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
,
7507 part
->syncobj
, pFd
);
7509 return vk_error(device
->instance
, VK_ERROR_TOO_MANY_OBJECTS
);
7511 if (part
== &fence
->temporary
) {
7512 radv_destroy_fence_part(device
, part
);
7514 device
->ws
->reset_syncobj(device
->ws
, part
->syncobj
);
7518 unreachable("Unhandled fence handle type");
7524 void radv_GetPhysicalDeviceExternalFenceProperties(
7525 VkPhysicalDevice physicalDevice
,
7526 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
7527 VkExternalFenceProperties
*pExternalFenceProperties
)
7529 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
7531 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
7532 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
7533 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
7534 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7535 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
7536 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
7537 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
7539 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
7540 pExternalFenceProperties
->compatibleHandleTypes
= 0;
7541 pExternalFenceProperties
->externalFenceFeatures
= 0;
7546 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
7547 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
7548 const VkAllocationCallbacks
* pAllocator
,
7549 VkDebugReportCallbackEXT
* pCallback
)
7551 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7552 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
7553 pCreateInfo
, pAllocator
, &instance
->alloc
,
7558 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
7559 VkDebugReportCallbackEXT _callback
,
7560 const VkAllocationCallbacks
* pAllocator
)
7562 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7563 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
7564 _callback
, pAllocator
, &instance
->alloc
);
7568 radv_DebugReportMessageEXT(VkInstance _instance
,
7569 VkDebugReportFlagsEXT flags
,
7570 VkDebugReportObjectTypeEXT objectType
,
7573 int32_t messageCode
,
7574 const char* pLayerPrefix
,
7575 const char* pMessage
)
7577 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
7578 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
7579 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
7583 radv_GetDeviceGroupPeerMemoryFeatures(
7586 uint32_t localDeviceIndex
,
7587 uint32_t remoteDeviceIndex
,
7588 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
7590 assert(localDeviceIndex
== remoteDeviceIndex
);
7592 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
7593 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
7594 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
7595 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
7598 static const VkTimeDomainEXT radv_time_domains
[] = {
7599 VK_TIME_DOMAIN_DEVICE_EXT
,
7600 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
7601 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
7604 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7605 VkPhysicalDevice physicalDevice
,
7606 uint32_t *pTimeDomainCount
,
7607 VkTimeDomainEXT
*pTimeDomains
)
7610 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
7612 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
7613 vk_outarray_append(&out
, i
) {
7614 *i
= radv_time_domains
[d
];
7618 return vk_outarray_status(&out
);
7622 radv_clock_gettime(clockid_t clock_id
)
7624 struct timespec current
;
7627 ret
= clock_gettime(clock_id
, ¤t
);
7628 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
7629 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
7633 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
7636 VkResult
radv_GetCalibratedTimestampsEXT(
7638 uint32_t timestampCount
,
7639 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
7640 uint64_t *pTimestamps
,
7641 uint64_t *pMaxDeviation
)
7643 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7644 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
7646 uint64_t begin
, end
;
7647 uint64_t max_clock_period
= 0;
7649 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7651 for (d
= 0; d
< timestampCount
; d
++) {
7652 switch (pTimestampInfos
[d
].timeDomain
) {
7653 case VK_TIME_DOMAIN_DEVICE_EXT
:
7654 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
7656 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
7657 max_clock_period
= MAX2(max_clock_period
, device_period
);
7659 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
7660 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
7661 max_clock_period
= MAX2(max_clock_period
, 1);
7664 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
7665 pTimestamps
[d
] = begin
;
7673 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
7676 * The maximum deviation is the sum of the interval over which we
7677 * perform the sampling and the maximum period of any sampled
7678 * clock. That's because the maximum skew between any two sampled
7679 * clock edges is when the sampled clock with the largest period is
7680 * sampled at the end of that period but right at the beginning of the
7681 * sampling interval and some other clock is sampled right at the
7682 * begining of its sampling period and right at the end of the
7683 * sampling interval. Let's assume the GPU has the longest clock
7684 * period and that the application is sampling GPU and monotonic:
7687 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7688 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7692 * GPU -----_____-----_____-----_____-----_____
7695 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7696 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7698 * Interval <----------------->
7699 * Deviation <-------------------------->
7703 * m = read(monotonic) 2
7706 * We round the sample interval up by one tick to cover sampling error
7707 * in the interval clock
7710 uint64_t sample_interval
= end
- begin
+ 1;
7712 *pMaxDeviation
= sample_interval
+ max_clock_period
;
7717 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7718 VkPhysicalDevice physicalDevice
,
7719 VkSampleCountFlagBits samples
,
7720 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
7722 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
7723 VK_SAMPLE_COUNT_4_BIT
|
7724 VK_SAMPLE_COUNT_8_BIT
)) {
7725 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
7727 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };
7731 VkResult
radv_CreatePrivateDataSlotEXT(
7733 const VkPrivateDataSlotCreateInfoEXT
* pCreateInfo
,
7734 const VkAllocationCallbacks
* pAllocator
,
7735 VkPrivateDataSlotEXT
* pPrivateDataSlot
)
7737 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7738 return vk_private_data_slot_create(&device
->vk
, pCreateInfo
, pAllocator
,
7742 void radv_DestroyPrivateDataSlotEXT(
7744 VkPrivateDataSlotEXT privateDataSlot
,
7745 const VkAllocationCallbacks
* pAllocator
)
7747 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7748 vk_private_data_slot_destroy(&device
->vk
, privateDataSlot
, pAllocator
);
7751 VkResult
radv_SetPrivateDataEXT(
7753 VkObjectType objectType
,
7754 uint64_t objectHandle
,
7755 VkPrivateDataSlotEXT privateDataSlot
,
7758 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7759 return vk_object_base_set_private_data(&device
->vk
, objectType
,
7760 objectHandle
, privateDataSlot
,
7764 void radv_GetPrivateDataEXT(
7766 VkObjectType objectType
,
7767 uint64_t objectHandle
,
7768 VkPrivateDataSlotEXT privateDataSlot
,
7771 RADV_FROM_HANDLE(radv_device
, device
, _device
);
7772 vk_object_base_get_private_data(&device
->vk
, objectType
, objectHandle
,
7773 privateDataSlot
, pData
);