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radv: Implement VK_EXT_pci_bus_info.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static bool
53 radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
54 {
55 uint32_t timestamp;
56
57 #ifdef HAVE_DL_ITERATE_PHDR
58 const struct build_id_note *note = NULL;
59 if ((note = build_id_find_nhdr_for_addr(ptr))) {
60 _mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
61 } else
62 #endif
63 if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
64 _mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
65 } else
66 return false;
67 return true;
68 }
69
70 static int
71 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
72 {
73 struct mesa_sha1 ctx;
74 unsigned char sha1[20];
75 unsigned ptr_size = sizeof(void*);
76
77 memset(uuid, 0, VK_UUID_SIZE);
78 _mesa_sha1_init(&ctx);
79
80 if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
81 !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
82 return -1;
83
84 _mesa_sha1_update(&ctx, &family, sizeof(family));
85 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
86 _mesa_sha1_final(&ctx, sha1);
87
88 memcpy(uuid, sha1, VK_UUID_SIZE);
89 return 0;
90 }
91
92 static void
93 radv_get_driver_uuid(void *uuid)
94 {
95 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
96 }
97
98 static void
99 radv_get_device_uuid(struct radeon_info *info, void *uuid)
100 {
101 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
102 }
103
104 static void
105 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
106 {
107 const char *chip_string;
108 char llvm_string[32] = {};
109
110 switch (family) {
111 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
112 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
113 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
114 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
115 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
116 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
117 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
118 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
119 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
120 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
121 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
122 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
123 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
124 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
125 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
126 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
127 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
128 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
129 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
130 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
131 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
132 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
133 default: chip_string = "AMD RADV unknown"; break;
134 }
135
136 snprintf(llvm_string, sizeof(llvm_string),
137 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
138 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
139 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
140 }
141
142 static void
143 radv_physical_device_init_mem_types(struct radv_physical_device *device)
144 {
145 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
146 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
147 device->rad_info.vram_vis_size);
148
149 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
150 device->memory_properties.memoryHeapCount = 0;
151 if (device->rad_info.vram_size - visible_vram_size > 0) {
152 vram_index = device->memory_properties.memoryHeapCount++;
153 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
154 .size = device->rad_info.vram_size - visible_vram_size,
155 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
156 };
157 }
158 if (visible_vram_size) {
159 visible_vram_index = device->memory_properties.memoryHeapCount++;
160 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
161 .size = visible_vram_size,
162 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
163 };
164 }
165 if (device->rad_info.gart_size > 0) {
166 gart_index = device->memory_properties.memoryHeapCount++;
167 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
168 .size = device->rad_info.gart_size,
169 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
170 };
171 }
172
173 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
174 unsigned type_count = 0;
175 if (vram_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
179 .heapIndex = vram_index,
180 };
181 }
182 if (gart_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
186 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
187 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
188 .heapIndex = gart_index,
189 };
190 }
191 if (visible_vram_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
195 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
197 .heapIndex = visible_vram_index,
198 };
199 }
200 if (gart_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
204 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
205 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
206 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
207 .heapIndex = gart_index,
208 };
209 }
210 device->memory_properties.memoryTypeCount = type_count;
211 }
212
213 static void
214 radv_handle_env_var_force_family(struct radv_physical_device *device)
215 {
216 const char *family = getenv("RADV_FORCE_FAMILY");
217 unsigned i;
218
219 if (!family)
220 return;
221
222 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
223 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
224 /* Override family and chip_class. */
225 device->rad_info.family = i;
226
227 if (i >= CHIP_VEGA10)
228 device->rad_info.chip_class = GFX9;
229 else if (i >= CHIP_TONGA)
230 device->rad_info.chip_class = VI;
231 else if (i >= CHIP_BONAIRE)
232 device->rad_info.chip_class = CIK;
233 else
234 device->rad_info.chip_class = SI;
235
236 return;
237 }
238 }
239
240 fprintf(stderr, "radv: Unknown family: %s\n", family);
241 exit(1);
242 }
243
244 static VkResult
245 radv_physical_device_init(struct radv_physical_device *device,
246 struct radv_instance *instance,
247 drmDevicePtr drm_device)
248 {
249 const char *path = drm_device->nodes[DRM_NODE_RENDER];
250 VkResult result;
251 drmVersionPtr version;
252 int fd;
253 int master_fd = -1;
254
255 fd = open(path, O_RDWR | O_CLOEXEC);
256 if (fd < 0) {
257 if (instance->debug_flags & RADV_DEBUG_STARTUP)
258 radv_logi("Could not open device '%s'", path);
259
260 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
261 }
262
263 version = drmGetVersion(fd);
264 if (!version) {
265 close(fd);
266
267 if (instance->debug_flags & RADV_DEBUG_STARTUP)
268 radv_logi("Could not get the kernel driver version for device '%s'", path);
269
270 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
271 "failed to get version %s: %m", path);
272 }
273
274 if (strcmp(version->name, "amdgpu")) {
275 drmFreeVersion(version);
276 close(fd);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
280
281 return VK_ERROR_INCOMPATIBLE_DRIVER;
282 }
283 drmFreeVersion(version);
284
285 if (instance->debug_flags & RADV_DEBUG_STARTUP)
286 radv_logi("Found compatible device '%s'.", path);
287
288 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
289 device->instance = instance;
290 assert(strlen(path) < ARRAY_SIZE(device->path));
291 strncpy(device->path, path, ARRAY_SIZE(device->path));
292
293 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
294 instance->perftest_flags);
295 if (!device->ws) {
296 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
297 goto fail;
298 }
299
300 if (instance->enabled_extensions.KHR_display) {
301 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
302 if (master_fd >= 0) {
303 uint32_t accel_working = 0;
304 struct drm_amdgpu_info request = {
305 .return_pointer = (uintptr_t)&accel_working,
306 .return_size = sizeof(accel_working),
307 .query = AMDGPU_INFO_ACCEL_WORKING
308 };
309
310 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
311 close(master_fd);
312 master_fd = -1;
313 }
314 }
315 }
316
317 device->master_fd = master_fd;
318 device->local_fd = fd;
319 device->ws->query_info(device->ws, &device->rad_info);
320
321 radv_handle_env_var_force_family(device);
322
323 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
324
325 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
326 device->ws->destroy(device->ws);
327 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
328 "cannot generate UUID");
329 goto fail;
330 }
331
332 /* These flags affect shader compilation. */
333 uint64_t shader_env_flags =
334 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
335 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
336
337 /* The gpu id is already embedded in the uuid so we just pass "radv"
338 * when creating the cache.
339 */
340 char buf[VK_UUID_SIZE * 2 + 1];
341 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
342 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
343
344 if (device->rad_info.chip_class < VI ||
345 device->rad_info.chip_class > GFX9)
346 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
347
348 radv_get_driver_uuid(&device->device_uuid);
349 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
350
351 if (device->rad_info.family == CHIP_STONEY ||
352 device->rad_info.chip_class >= GFX9) {
353 device->has_rbplus = true;
354 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
355 device->rad_info.family == CHIP_VEGA12 ||
356 device->rad_info.family == CHIP_RAVEN;
357 }
358
359 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
360 * on SI.
361 */
362 device->has_clear_state = device->rad_info.chip_class >= CIK;
363
364 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
365
366 /* Vega10/Raven need a special workaround for a hardware bug. */
367 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
368 device->rad_info.family == CHIP_RAVEN;
369
370 /* Out-of-order primitive rasterization. */
371 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
372 device->rad_info.max_se >= 2;
373 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
374 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
375
376 device->dcc_msaa_allowed =
377 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
378
379 radv_physical_device_init_mem_types(device);
380 radv_fill_device_extension_table(device, &device->supported_extensions);
381
382 result = radv_init_wsi(device);
383 if (result != VK_SUCCESS) {
384 device->ws->destroy(device->ws);
385 vk_error(instance, result);
386 goto fail;
387 }
388
389 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
390 ac_print_gpu_info(&device->rad_info);
391
392 device->bus_info = *drm_device->businfo.pci;
393 return VK_SUCCESS;
394
395 fail:
396 close(fd);
397 if (master_fd != -1)
398 close(master_fd);
399 return result;
400 }
401
402 static void
403 radv_physical_device_finish(struct radv_physical_device *device)
404 {
405 radv_finish_wsi(device);
406 device->ws->destroy(device->ws);
407 disk_cache_destroy(device->disk_cache);
408 close(device->local_fd);
409 if (device->master_fd != -1)
410 close(device->master_fd);
411 }
412
413 static void *
414 default_alloc_func(void *pUserData, size_t size, size_t align,
415 VkSystemAllocationScope allocationScope)
416 {
417 return malloc(size);
418 }
419
420 static void *
421 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
422 size_t align, VkSystemAllocationScope allocationScope)
423 {
424 return realloc(pOriginal, size);
425 }
426
427 static void
428 default_free_func(void *pUserData, void *pMemory)
429 {
430 free(pMemory);
431 }
432
433 static const VkAllocationCallbacks default_alloc = {
434 .pUserData = NULL,
435 .pfnAllocation = default_alloc_func,
436 .pfnReallocation = default_realloc_func,
437 .pfnFree = default_free_func,
438 };
439
440 static const struct debug_control radv_debug_options[] = {
441 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
442 {"nodcc", RADV_DEBUG_NO_DCC},
443 {"shaders", RADV_DEBUG_DUMP_SHADERS},
444 {"nocache", RADV_DEBUG_NO_CACHE},
445 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
446 {"nohiz", RADV_DEBUG_NO_HIZ},
447 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
448 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
449 {"allbos", RADV_DEBUG_ALL_BOS},
450 {"noibs", RADV_DEBUG_NO_IBS},
451 {"spirv", RADV_DEBUG_DUMP_SPIRV},
452 {"vmfaults", RADV_DEBUG_VM_FAULTS},
453 {"zerovram", RADV_DEBUG_ZERO_VRAM},
454 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
455 {"nosisched", RADV_DEBUG_NO_SISCHED},
456 {"preoptir", RADV_DEBUG_PREOPTIR},
457 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
458 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
459 {"info", RADV_DEBUG_INFO},
460 {"errors", RADV_DEBUG_ERRORS},
461 {"startup", RADV_DEBUG_STARTUP},
462 {"checkir", RADV_DEBUG_CHECKIR},
463 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
464 {NULL, 0}
465 };
466
467 const char *
468 radv_get_debug_option_name(int id)
469 {
470 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
471 return radv_debug_options[id].string;
472 }
473
474 static const struct debug_control radv_perftest_options[] = {
475 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
476 {"sisched", RADV_PERFTEST_SISCHED},
477 {"localbos", RADV_PERFTEST_LOCAL_BOS},
478 {"binning", RADV_PERFTEST_BINNING},
479 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
480 {NULL, 0}
481 };
482
483 const char *
484 radv_get_perftest_option_name(int id)
485 {
486 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
487 return radv_perftest_options[id].string;
488 }
489
490 static void
491 radv_handle_per_app_options(struct radv_instance *instance,
492 const VkApplicationInfo *info)
493 {
494 const char *name = info ? info->pApplicationName : NULL;
495
496 if (!name)
497 return;
498
499 if (!strcmp(name, "Talos - Linux - 32bit") ||
500 !strcmp(name, "Talos - Linux - 64bit")) {
501 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
502 /* Force enable LLVM sisched for Talos because it looks
503 * safe and it gives few more FPS.
504 */
505 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
506 }
507 } else if (!strcmp(name, "DOOM_VFR")) {
508 /* Work around a Doom VFR game bug */
509 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
510 }
511 }
512
513 static int radv_get_instance_extension_index(const char *name)
514 {
515 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
516 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
517 return i;
518 }
519 return -1;
520 }
521
522
523 VkResult radv_CreateInstance(
524 const VkInstanceCreateInfo* pCreateInfo,
525 const VkAllocationCallbacks* pAllocator,
526 VkInstance* pInstance)
527 {
528 struct radv_instance *instance;
529 VkResult result;
530
531 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
532
533 uint32_t client_version;
534 if (pCreateInfo->pApplicationInfo &&
535 pCreateInfo->pApplicationInfo->apiVersion != 0) {
536 client_version = pCreateInfo->pApplicationInfo->apiVersion;
537 } else {
538 radv_EnumerateInstanceVersion(&client_version);
539 }
540
541 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
542 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
543 if (!instance)
544 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
545
546 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
547
548 if (pAllocator)
549 instance->alloc = *pAllocator;
550 else
551 instance->alloc = default_alloc;
552
553 instance->apiVersion = client_version;
554 instance->physicalDeviceCount = -1;
555
556 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
557 radv_debug_options);
558
559 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
560 radv_perftest_options);
561
562
563 if (instance->debug_flags & RADV_DEBUG_STARTUP)
564 radv_logi("Created an instance");
565
566 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
567 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
568 int index = radv_get_instance_extension_index(ext_name);
569
570 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
571 vk_free2(&default_alloc, pAllocator, instance);
572 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
573 }
574
575 instance->enabled_extensions.extensions[index] = true;
576 }
577
578 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
579 if (result != VK_SUCCESS) {
580 vk_free2(&default_alloc, pAllocator, instance);
581 return vk_error(instance, result);
582 }
583
584 _mesa_locale_init();
585
586 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
587
588 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
589
590 *pInstance = radv_instance_to_handle(instance);
591
592 return VK_SUCCESS;
593 }
594
595 void radv_DestroyInstance(
596 VkInstance _instance,
597 const VkAllocationCallbacks* pAllocator)
598 {
599 RADV_FROM_HANDLE(radv_instance, instance, _instance);
600
601 if (!instance)
602 return;
603
604 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
605 radv_physical_device_finish(instance->physicalDevices + i);
606 }
607
608 VG(VALGRIND_DESTROY_MEMPOOL(instance));
609
610 _mesa_locale_fini();
611
612 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
613
614 vk_free(&instance->alloc, instance);
615 }
616
617 static VkResult
618 radv_enumerate_devices(struct radv_instance *instance)
619 {
620 /* TODO: Check for more devices ? */
621 drmDevicePtr devices[8];
622 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
623 int max_devices;
624
625 instance->physicalDeviceCount = 0;
626
627 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
628
629 if (instance->debug_flags & RADV_DEBUG_STARTUP)
630 radv_logi("Found %d drm nodes", max_devices);
631
632 if (max_devices < 1)
633 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
634
635 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
636 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
637 devices[i]->bustype == DRM_BUS_PCI &&
638 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
639
640 result = radv_physical_device_init(instance->physicalDevices +
641 instance->physicalDeviceCount,
642 instance,
643 devices[i]);
644 if (result == VK_SUCCESS)
645 ++instance->physicalDeviceCount;
646 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
647 break;
648 }
649 }
650 drmFreeDevices(devices, max_devices);
651
652 return result;
653 }
654
655 VkResult radv_EnumeratePhysicalDevices(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceCount,
658 VkPhysicalDevice* pPhysicalDevices)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDevices) {
671 *pPhysicalDeviceCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
675 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
676 }
677
678 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
679 : VK_SUCCESS;
680 }
681
682 VkResult radv_EnumeratePhysicalDeviceGroups(
683 VkInstance _instance,
684 uint32_t* pPhysicalDeviceGroupCount,
685 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
686 {
687 RADV_FROM_HANDLE(radv_instance, instance, _instance);
688 VkResult result;
689
690 if (instance->physicalDeviceCount < 0) {
691 result = radv_enumerate_devices(instance);
692 if (result != VK_SUCCESS &&
693 result != VK_ERROR_INCOMPATIBLE_DRIVER)
694 return result;
695 }
696
697 if (!pPhysicalDeviceGroupProperties) {
698 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
699 } else {
700 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
701 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
702 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
703 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
704 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
705 }
706 }
707 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
708 : VK_SUCCESS;
709 }
710
711 void radv_GetPhysicalDeviceFeatures(
712 VkPhysicalDevice physicalDevice,
713 VkPhysicalDeviceFeatures* pFeatures)
714 {
715 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
716 memset(pFeatures, 0, sizeof(*pFeatures));
717
718 *pFeatures = (VkPhysicalDeviceFeatures) {
719 .robustBufferAccess = true,
720 .fullDrawIndexUint32 = true,
721 .imageCubeArray = true,
722 .independentBlend = true,
723 .geometryShader = true,
724 .tessellationShader = true,
725 .sampleRateShading = true,
726 .dualSrcBlend = true,
727 .logicOp = true,
728 .multiDrawIndirect = true,
729 .drawIndirectFirstInstance = true,
730 .depthClamp = true,
731 .depthBiasClamp = true,
732 .fillModeNonSolid = true,
733 .depthBounds = true,
734 .wideLines = true,
735 .largePoints = true,
736 .alphaToOne = true,
737 .multiViewport = true,
738 .samplerAnisotropy = true,
739 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
740 pdevice->rad_info.family == CHIP_STONEY,
741 .textureCompressionASTC_LDR = false,
742 .textureCompressionBC = true,
743 .occlusionQueryPrecise = true,
744 .pipelineStatisticsQuery = true,
745 .vertexPipelineStoresAndAtomics = true,
746 .fragmentStoresAndAtomics = true,
747 .shaderTessellationAndGeometryPointSize = true,
748 .shaderImageGatherExtended = true,
749 .shaderStorageImageExtendedFormats = true,
750 .shaderStorageImageMultisample = false,
751 .shaderUniformBufferArrayDynamicIndexing = true,
752 .shaderSampledImageArrayDynamicIndexing = true,
753 .shaderStorageBufferArrayDynamicIndexing = true,
754 .shaderStorageImageArrayDynamicIndexing = true,
755 .shaderStorageImageReadWithoutFormat = true,
756 .shaderStorageImageWriteWithoutFormat = true,
757 .shaderClipDistance = true,
758 .shaderCullDistance = true,
759 .shaderFloat64 = true,
760 .shaderInt64 = true,
761 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && HAVE_LLVM >= 0x700,
762 .sparseBinding = true,
763 .variableMultisampleRate = true,
764 .inheritedQueries = true,
765 };
766 }
767
768 void radv_GetPhysicalDeviceFeatures2(
769 VkPhysicalDevice physicalDevice,
770 VkPhysicalDeviceFeatures2KHR *pFeatures)
771 {
772 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
773 vk_foreach_struct(ext, pFeatures->pNext) {
774 switch (ext->sType) {
775 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
776 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
777 features->variablePointersStorageBuffer = true;
778 features->variablePointers = false;
779 break;
780 }
781 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
782 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
783 features->multiview = true;
784 features->multiviewGeometryShader = true;
785 features->multiviewTessellationShader = true;
786 break;
787 }
788 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
789 VkPhysicalDeviceShaderDrawParameterFeatures *features =
790 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
791 features->shaderDrawParameters = true;
792 break;
793 }
794 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
795 VkPhysicalDeviceProtectedMemoryFeatures *features =
796 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
797 features->protectedMemory = false;
798 break;
799 }
800 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
801 VkPhysicalDevice16BitStorageFeatures *features =
802 (VkPhysicalDevice16BitStorageFeatures*)ext;
803 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
804 features->storageBuffer16BitAccess = enabled;
805 features->uniformAndStorageBuffer16BitAccess = enabled;
806 features->storagePushConstant16 = enabled;
807 features->storageInputOutput16 = enabled;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
811 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
812 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
813 features->samplerYcbcrConversion = false;
814 break;
815 }
816 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
817 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
818 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
819 features->shaderInputAttachmentArrayDynamicIndexing = true;
820 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
821 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
822 features->shaderUniformBufferArrayNonUniformIndexing = false;
823 features->shaderSampledImageArrayNonUniformIndexing = false;
824 features->shaderStorageBufferArrayNonUniformIndexing = false;
825 features->shaderStorageImageArrayNonUniformIndexing = false;
826 features->shaderInputAttachmentArrayNonUniformIndexing = false;
827 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
828 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
829 features->descriptorBindingUniformBufferUpdateAfterBind = true;
830 features->descriptorBindingSampledImageUpdateAfterBind = true;
831 features->descriptorBindingStorageImageUpdateAfterBind = true;
832 features->descriptorBindingStorageBufferUpdateAfterBind = true;
833 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
834 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
835 features->descriptorBindingUpdateUnusedWhilePending = true;
836 features->descriptorBindingPartiallyBound = true;
837 features->descriptorBindingVariableDescriptorCount = true;
838 features->runtimeDescriptorArray = true;
839 break;
840 }
841 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
842 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
843 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
844 features->conditionalRendering = true;
845 features->inheritedConditionalRendering = false;
846 break;
847 }
848 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
849 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
850 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
851 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
852 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
853 break;
854 }
855 default:
856 break;
857 }
858 }
859 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
860 }
861
862 void radv_GetPhysicalDeviceProperties(
863 VkPhysicalDevice physicalDevice,
864 VkPhysicalDeviceProperties* pProperties)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 VkSampleCountFlags sample_counts = 0xf;
868
869 /* make sure that the entire descriptor set is addressable with a signed
870 * 32-bit int. So the sum of all limits scaled by descriptor size has to
871 * be at most 2 GiB. the combined image & samples object count as one of
872 * both. This limit is for the pipeline layout, not for the set layout, but
873 * there is no set limit, so we just set a pipeline limit. I don't think
874 * any app is going to hit this soon. */
875 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
876 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
877 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
878 32 /* sampler, largest when combined with image */ +
879 64 /* sampled image */ +
880 64 /* storage image */);
881
882 VkPhysicalDeviceLimits limits = {
883 .maxImageDimension1D = (1 << 14),
884 .maxImageDimension2D = (1 << 14),
885 .maxImageDimension3D = (1 << 11),
886 .maxImageDimensionCube = (1 << 14),
887 .maxImageArrayLayers = (1 << 11),
888 .maxTexelBufferElements = 128 * 1024 * 1024,
889 .maxUniformBufferRange = UINT32_MAX,
890 .maxStorageBufferRange = UINT32_MAX,
891 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
892 .maxMemoryAllocationCount = UINT32_MAX,
893 .maxSamplerAllocationCount = 64 * 1024,
894 .bufferImageGranularity = 64, /* A cache line */
895 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
896 .maxBoundDescriptorSets = MAX_SETS,
897 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
898 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
899 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
900 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
901 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
902 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
903 .maxPerStageResources = max_descriptor_set_size,
904 .maxDescriptorSetSamplers = max_descriptor_set_size,
905 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
906 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
907 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
908 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
909 .maxDescriptorSetSampledImages = max_descriptor_set_size,
910 .maxDescriptorSetStorageImages = max_descriptor_set_size,
911 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
912 .maxVertexInputAttributes = 32,
913 .maxVertexInputBindings = 32,
914 .maxVertexInputAttributeOffset = 2047,
915 .maxVertexInputBindingStride = 2048,
916 .maxVertexOutputComponents = 128,
917 .maxTessellationGenerationLevel = 64,
918 .maxTessellationPatchSize = 32,
919 .maxTessellationControlPerVertexInputComponents = 128,
920 .maxTessellationControlPerVertexOutputComponents = 128,
921 .maxTessellationControlPerPatchOutputComponents = 120,
922 .maxTessellationControlTotalOutputComponents = 4096,
923 .maxTessellationEvaluationInputComponents = 128,
924 .maxTessellationEvaluationOutputComponents = 128,
925 .maxGeometryShaderInvocations = 127,
926 .maxGeometryInputComponents = 64,
927 .maxGeometryOutputComponents = 128,
928 .maxGeometryOutputVertices = 256,
929 .maxGeometryTotalOutputComponents = 1024,
930 .maxFragmentInputComponents = 128,
931 .maxFragmentOutputAttachments = 8,
932 .maxFragmentDualSrcAttachments = 1,
933 .maxFragmentCombinedOutputResources = 8,
934 .maxComputeSharedMemorySize = 32768,
935 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
936 .maxComputeWorkGroupInvocations = 2048,
937 .maxComputeWorkGroupSize = {
938 2048,
939 2048,
940 2048
941 },
942 .subPixelPrecisionBits = 4 /* FIXME */,
943 .subTexelPrecisionBits = 4 /* FIXME */,
944 .mipmapPrecisionBits = 4 /* FIXME */,
945 .maxDrawIndexedIndexValue = UINT32_MAX,
946 .maxDrawIndirectCount = UINT32_MAX,
947 .maxSamplerLodBias = 16,
948 .maxSamplerAnisotropy = 16,
949 .maxViewports = MAX_VIEWPORTS,
950 .maxViewportDimensions = { (1 << 14), (1 << 14) },
951 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
952 .viewportSubPixelBits = 8,
953 .minMemoryMapAlignment = 4096, /* A page */
954 .minTexelBufferOffsetAlignment = 1,
955 .minUniformBufferOffsetAlignment = 4,
956 .minStorageBufferOffsetAlignment = 4,
957 .minTexelOffset = -32,
958 .maxTexelOffset = 31,
959 .minTexelGatherOffset = -32,
960 .maxTexelGatherOffset = 31,
961 .minInterpolationOffset = -2,
962 .maxInterpolationOffset = 2,
963 .subPixelInterpolationOffsetBits = 8,
964 .maxFramebufferWidth = (1 << 14),
965 .maxFramebufferHeight = (1 << 14),
966 .maxFramebufferLayers = (1 << 10),
967 .framebufferColorSampleCounts = sample_counts,
968 .framebufferDepthSampleCounts = sample_counts,
969 .framebufferStencilSampleCounts = sample_counts,
970 .framebufferNoAttachmentsSampleCounts = sample_counts,
971 .maxColorAttachments = MAX_RTS,
972 .sampledImageColorSampleCounts = sample_counts,
973 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
974 .sampledImageDepthSampleCounts = sample_counts,
975 .sampledImageStencilSampleCounts = sample_counts,
976 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
977 .maxSampleMaskWords = 1,
978 .timestampComputeAndGraphics = true,
979 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
980 .maxClipDistances = 8,
981 .maxCullDistances = 8,
982 .maxCombinedClipAndCullDistances = 8,
983 .discreteQueuePriorities = 1,
984 .pointSizeRange = { 0.125, 255.875 },
985 .lineWidthRange = { 0.0, 7.9921875 },
986 .pointSizeGranularity = (1.0 / 8.0),
987 .lineWidthGranularity = (1.0 / 128.0),
988 .strictLines = false, /* FINISHME */
989 .standardSampleLocations = true,
990 .optimalBufferCopyOffsetAlignment = 128,
991 .optimalBufferCopyRowPitchAlignment = 128,
992 .nonCoherentAtomSize = 64,
993 };
994
995 *pProperties = (VkPhysicalDeviceProperties) {
996 .apiVersion = radv_physical_device_api_version(pdevice),
997 .driverVersion = vk_get_driver_version(),
998 .vendorID = ATI_VENDOR_ID,
999 .deviceID = pdevice->rad_info.pci_id,
1000 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1001 .limits = limits,
1002 .sparseProperties = {0},
1003 };
1004
1005 strcpy(pProperties->deviceName, pdevice->name);
1006 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1007 }
1008
1009 void radv_GetPhysicalDeviceProperties2(
1010 VkPhysicalDevice physicalDevice,
1011 VkPhysicalDeviceProperties2KHR *pProperties)
1012 {
1013 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1014 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1015
1016 vk_foreach_struct(ext, pProperties->pNext) {
1017 switch (ext->sType) {
1018 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1019 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1020 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1021 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1022 break;
1023 }
1024 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1025 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1026 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1027 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1028 properties->deviceLUIDValid = false;
1029 break;
1030 }
1031 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1032 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1033 properties->maxMultiviewViewCount = MAX_VIEWS;
1034 properties->maxMultiviewInstanceIndex = INT_MAX;
1035 break;
1036 }
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1038 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1039 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1040 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1041 break;
1042 }
1043 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1044 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1045 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1046 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1050 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1051 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1052 properties->minImportedHostPointerAlignment = 4096;
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1056 VkPhysicalDeviceSubgroupProperties *properties =
1057 (VkPhysicalDeviceSubgroupProperties*)ext;
1058 properties->subgroupSize = 64;
1059 properties->supportedStages = VK_SHADER_STAGE_ALL;
1060 properties->supportedOperations =
1061 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1062 VK_SUBGROUP_FEATURE_BASIC_BIT |
1063 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1064 VK_SUBGROUP_FEATURE_QUAD_BIT |
1065 VK_SUBGROUP_FEATURE_VOTE_BIT;
1066 if (pdevice->rad_info.chip_class >= VI) {
1067 properties->supportedOperations |=
1068 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1069 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1070 }
1071 properties->quadOperationsInAllStages = true;
1072 break;
1073 }
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1075 VkPhysicalDeviceMaintenance3Properties *properties =
1076 (VkPhysicalDeviceMaintenance3Properties*)ext;
1077 /* Make sure everything is addressable by a signed 32-bit int, and
1078 * our largest descriptors are 96 bytes. */
1079 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1080 /* Our buffer size fields allow only this much */
1081 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1082 break;
1083 }
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1085 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1086 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1087 /* GFX6-8 only support single channel min/max filter. */
1088 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1089 properties->filterMinmaxSingleComponentFormats = true;
1090 break;
1091 }
1092 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1093 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1094 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1095
1096 /* Shader engines. */
1097 properties->shaderEngineCount =
1098 pdevice->rad_info.max_se;
1099 properties->shaderArraysPerEngineCount =
1100 pdevice->rad_info.max_sh_per_se;
1101 properties->computeUnitsPerShaderArray =
1102 pdevice->rad_info.num_good_compute_units /
1103 (pdevice->rad_info.max_se *
1104 pdevice->rad_info.max_sh_per_se);
1105 properties->simdPerComputeUnit = 4;
1106 properties->wavefrontsPerSimd =
1107 pdevice->rad_info.family == CHIP_TONGA ||
1108 pdevice->rad_info.family == CHIP_ICELAND ||
1109 pdevice->rad_info.family == CHIP_POLARIS10 ||
1110 pdevice->rad_info.family == CHIP_POLARIS11 ||
1111 pdevice->rad_info.family == CHIP_POLARIS12 ||
1112 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1113 properties->wavefrontSize = 64;
1114
1115 /* SGPR. */
1116 properties->sgprsPerSimd =
1117 radv_get_num_physical_sgprs(pdevice);
1118 properties->minSgprAllocation =
1119 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1120 properties->maxSgprAllocation =
1121 pdevice->rad_info.family == CHIP_TONGA ||
1122 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1123 properties->sgprAllocationGranularity =
1124 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1125
1126 /* VGPR. */
1127 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1128 properties->minVgprAllocation = 4;
1129 properties->maxVgprAllocation = 256;
1130 properties->vgprAllocationGranularity = 4;
1131 break;
1132 }
1133 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1134 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1135 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1136 properties->maxVertexAttribDivisor = UINT32_MAX;
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1140 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1141 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1142 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1143 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1144 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1145 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1146 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1147 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1148 properties->robustBufferAccessUpdateAfterBind = false;
1149 properties->quadDivergentImplicitLod = false;
1150
1151 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1152 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1153 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1154 32 /* sampler, largest when combined with image */ +
1155 64 /* sampled image */ +
1156 64 /* storage image */);
1157 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1158 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1159 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1160 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1161 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1162 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1163 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1164 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1165 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1166 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1167 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1168 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1169 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1170 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1171 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1172 break;
1173 }
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1175 VkPhysicalDeviceProtectedMemoryProperties *properties =
1176 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1177 properties->protectedNoFault = false;
1178 break;
1179 }
1180 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1181 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1182 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1183 properties->primitiveOverestimationSize = 0;
1184 properties->maxExtraPrimitiveOverestimationSize = 0;
1185 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1186 properties->primitiveUnderestimation = VK_FALSE;
1187 properties->conservativePointAndLineRasterization = VK_FALSE;
1188 properties->degenerateTrianglesRasterized = VK_FALSE;
1189 properties->degenerateLinesRasterized = VK_FALSE;
1190 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1191 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1192 break;
1193 }
1194 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1195 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1196 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1197 properties->pciDomain = pdevice->bus_info.domain;
1198 properties->pciBus = pdevice->bus_info.bus;
1199 properties->pciDevice = pdevice->bus_info.dev;
1200 properties->pciFunction = pdevice->bus_info.func;
1201 break;
1202 }
1203 default:
1204 break;
1205 }
1206 }
1207 }
1208
1209 static void radv_get_physical_device_queue_family_properties(
1210 struct radv_physical_device* pdevice,
1211 uint32_t* pCount,
1212 VkQueueFamilyProperties** pQueueFamilyProperties)
1213 {
1214 int num_queue_families = 1;
1215 int idx;
1216 if (pdevice->rad_info.num_compute_rings > 0 &&
1217 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1218 num_queue_families++;
1219
1220 if (pQueueFamilyProperties == NULL) {
1221 *pCount = num_queue_families;
1222 return;
1223 }
1224
1225 if (!*pCount)
1226 return;
1227
1228 idx = 0;
1229 if (*pCount >= 1) {
1230 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1231 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1232 VK_QUEUE_COMPUTE_BIT |
1233 VK_QUEUE_TRANSFER_BIT |
1234 VK_QUEUE_SPARSE_BINDING_BIT,
1235 .queueCount = 1,
1236 .timestampValidBits = 64,
1237 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1238 };
1239 idx++;
1240 }
1241
1242 if (pdevice->rad_info.num_compute_rings > 0 &&
1243 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1244 if (*pCount > idx) {
1245 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1246 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1247 VK_QUEUE_TRANSFER_BIT |
1248 VK_QUEUE_SPARSE_BINDING_BIT,
1249 .queueCount = pdevice->rad_info.num_compute_rings,
1250 .timestampValidBits = 64,
1251 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1252 };
1253 idx++;
1254 }
1255 }
1256 *pCount = idx;
1257 }
1258
1259 void radv_GetPhysicalDeviceQueueFamilyProperties(
1260 VkPhysicalDevice physicalDevice,
1261 uint32_t* pCount,
1262 VkQueueFamilyProperties* pQueueFamilyProperties)
1263 {
1264 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1265 if (!pQueueFamilyProperties) {
1266 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1267 return;
1268 }
1269 VkQueueFamilyProperties *properties[] = {
1270 pQueueFamilyProperties + 0,
1271 pQueueFamilyProperties + 1,
1272 pQueueFamilyProperties + 2,
1273 };
1274 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1275 assert(*pCount <= 3);
1276 }
1277
1278 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1279 VkPhysicalDevice physicalDevice,
1280 uint32_t* pCount,
1281 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1282 {
1283 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1284 if (!pQueueFamilyProperties) {
1285 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1286 return;
1287 }
1288 VkQueueFamilyProperties *properties[] = {
1289 &pQueueFamilyProperties[0].queueFamilyProperties,
1290 &pQueueFamilyProperties[1].queueFamilyProperties,
1291 &pQueueFamilyProperties[2].queueFamilyProperties,
1292 };
1293 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1294 assert(*pCount <= 3);
1295 }
1296
1297 void radv_GetPhysicalDeviceMemoryProperties(
1298 VkPhysicalDevice physicalDevice,
1299 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1300 {
1301 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1302
1303 *pMemoryProperties = physical_device->memory_properties;
1304 }
1305
1306 void radv_GetPhysicalDeviceMemoryProperties2(
1307 VkPhysicalDevice physicalDevice,
1308 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1309 {
1310 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1311 &pMemoryProperties->memoryProperties);
1312 }
1313
1314 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1315 VkDevice _device,
1316 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1317 const void *pHostPointer,
1318 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1319 {
1320 RADV_FROM_HANDLE(radv_device, device, _device);
1321
1322 switch (handleType)
1323 {
1324 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1325 const struct radv_physical_device *physical_device = device->physical_device;
1326 uint32_t memoryTypeBits = 0;
1327 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1328 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1329 memoryTypeBits = (1 << i);
1330 break;
1331 }
1332 }
1333 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1334 return VK_SUCCESS;
1335 }
1336 default:
1337 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1338 }
1339 }
1340
1341 static enum radeon_ctx_priority
1342 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1343 {
1344 /* Default to MEDIUM when a specific global priority isn't requested */
1345 if (!pObj)
1346 return RADEON_CTX_PRIORITY_MEDIUM;
1347
1348 switch(pObj->globalPriority) {
1349 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1350 return RADEON_CTX_PRIORITY_REALTIME;
1351 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1352 return RADEON_CTX_PRIORITY_HIGH;
1353 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1354 return RADEON_CTX_PRIORITY_MEDIUM;
1355 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1356 return RADEON_CTX_PRIORITY_LOW;
1357 default:
1358 unreachable("Illegal global priority value");
1359 return RADEON_CTX_PRIORITY_INVALID;
1360 }
1361 }
1362
1363 static int
1364 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1365 uint32_t queue_family_index, int idx,
1366 VkDeviceQueueCreateFlags flags,
1367 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1368 {
1369 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1370 queue->device = device;
1371 queue->queue_family_index = queue_family_index;
1372 queue->queue_idx = idx;
1373 queue->priority = radv_get_queue_global_priority(global_priority);
1374 queue->flags = flags;
1375
1376 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1377 if (!queue->hw_ctx)
1378 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1379
1380 return VK_SUCCESS;
1381 }
1382
1383 static void
1384 radv_queue_finish(struct radv_queue *queue)
1385 {
1386 if (queue->hw_ctx)
1387 queue->device->ws->ctx_destroy(queue->hw_ctx);
1388
1389 if (queue->initial_full_flush_preamble_cs)
1390 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1391 if (queue->initial_preamble_cs)
1392 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1393 if (queue->continue_preamble_cs)
1394 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1395 if (queue->descriptor_bo)
1396 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1397 if (queue->scratch_bo)
1398 queue->device->ws->buffer_destroy(queue->scratch_bo);
1399 if (queue->esgs_ring_bo)
1400 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1401 if (queue->gsvs_ring_bo)
1402 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1403 if (queue->tess_rings_bo)
1404 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1405 if (queue->compute_scratch_bo)
1406 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1407 }
1408
1409 static void
1410 radv_bo_list_init(struct radv_bo_list *bo_list)
1411 {
1412 pthread_mutex_init(&bo_list->mutex, NULL);
1413 bo_list->list.count = bo_list->capacity = 0;
1414 bo_list->list.bos = NULL;
1415 }
1416
1417 static void
1418 radv_bo_list_finish(struct radv_bo_list *bo_list)
1419 {
1420 free(bo_list->list.bos);
1421 pthread_mutex_destroy(&bo_list->mutex);
1422 }
1423
1424 static VkResult radv_bo_list_add(struct radv_device *device,
1425 struct radeon_winsys_bo *bo)
1426 {
1427 struct radv_bo_list *bo_list = &device->bo_list;
1428
1429 if (unlikely(!device->use_global_bo_list))
1430 return VK_SUCCESS;
1431
1432 pthread_mutex_lock(&bo_list->mutex);
1433 if (bo_list->list.count == bo_list->capacity) {
1434 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1435 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1436
1437 if (!data) {
1438 pthread_mutex_unlock(&bo_list->mutex);
1439 return VK_ERROR_OUT_OF_HOST_MEMORY;
1440 }
1441
1442 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1443 bo_list->capacity = capacity;
1444 }
1445
1446 bo_list->list.bos[bo_list->list.count++] = bo;
1447 pthread_mutex_unlock(&bo_list->mutex);
1448 return VK_SUCCESS;
1449 }
1450
1451 static void radv_bo_list_remove(struct radv_device *device,
1452 struct radeon_winsys_bo *bo)
1453 {
1454 struct radv_bo_list *bo_list = &device->bo_list;
1455
1456 if (unlikely(!device->use_global_bo_list))
1457 return;
1458
1459 pthread_mutex_lock(&bo_list->mutex);
1460 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1461 if (bo_list->list.bos[i] == bo) {
1462 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1463 --bo_list->list.count;
1464 break;
1465 }
1466 }
1467 pthread_mutex_unlock(&bo_list->mutex);
1468 }
1469
1470 static void
1471 radv_device_init_gs_info(struct radv_device *device)
1472 {
1473 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1474 device->physical_device->rad_info.family);
1475 }
1476
1477 static int radv_get_device_extension_index(const char *name)
1478 {
1479 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1480 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1481 return i;
1482 }
1483 return -1;
1484 }
1485
1486 static int
1487 radv_get_int_debug_option(const char *name, int default_value)
1488 {
1489 const char *str;
1490 int result;
1491
1492 str = getenv(name);
1493 if (!str) {
1494 result = default_value;
1495 } else {
1496 char *endptr;
1497
1498 result = strtol(str, &endptr, 0);
1499 if (str == endptr) {
1500 /* No digits founs. */
1501 result = default_value;
1502 }
1503 }
1504
1505 return result;
1506 }
1507
1508 VkResult radv_CreateDevice(
1509 VkPhysicalDevice physicalDevice,
1510 const VkDeviceCreateInfo* pCreateInfo,
1511 const VkAllocationCallbacks* pAllocator,
1512 VkDevice* pDevice)
1513 {
1514 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1515 VkResult result;
1516 struct radv_device *device;
1517
1518 bool keep_shader_info = false;
1519
1520 /* Check enabled features */
1521 if (pCreateInfo->pEnabledFeatures) {
1522 VkPhysicalDeviceFeatures supported_features;
1523 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1524 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1525 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1526 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1527 for (uint32_t i = 0; i < num_features; i++) {
1528 if (enabled_feature[i] && !supported_feature[i])
1529 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1530 }
1531 }
1532
1533 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1534 sizeof(*device), 8,
1535 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1536 if (!device)
1537 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1538
1539 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1540 device->instance = physical_device->instance;
1541 device->physical_device = physical_device;
1542
1543 device->ws = physical_device->ws;
1544 if (pAllocator)
1545 device->alloc = *pAllocator;
1546 else
1547 device->alloc = physical_device->instance->alloc;
1548
1549 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1550 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1551 int index = radv_get_device_extension_index(ext_name);
1552 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1553 vk_free(&device->alloc, device);
1554 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1555 }
1556
1557 device->enabled_extensions.extensions[index] = true;
1558 }
1559
1560 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1561
1562 /* With update after bind we can't attach bo's to the command buffer
1563 * from the descriptor set anymore, so we have to use a global BO list.
1564 */
1565 device->use_global_bo_list =
1566 device->enabled_extensions.EXT_descriptor_indexing;
1567
1568 mtx_init(&device->shader_slab_mutex, mtx_plain);
1569 list_inithead(&device->shader_slabs);
1570
1571 radv_bo_list_init(&device->bo_list);
1572
1573 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1574 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1575 uint32_t qfi = queue_create->queueFamilyIndex;
1576 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1577 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1578
1579 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1580
1581 device->queues[qfi] = vk_alloc(&device->alloc,
1582 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1583 if (!device->queues[qfi]) {
1584 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1585 goto fail;
1586 }
1587
1588 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1589
1590 device->queue_count[qfi] = queue_create->queueCount;
1591
1592 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1593 result = radv_queue_init(device, &device->queues[qfi][q],
1594 qfi, q, queue_create->flags,
1595 global_priority);
1596 if (result != VK_SUCCESS)
1597 goto fail;
1598 }
1599 }
1600
1601 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1602 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1603 device->physical_device->rad_info.family == CHIP_RAVEN);
1604
1605 /* Disabled and not implemented for now. */
1606 device->dfsm_allowed = device->pbb_allowed &&
1607 device->physical_device->rad_info.family == CHIP_RAVEN;
1608
1609 #ifdef ANDROID
1610 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1611 #endif
1612
1613 /* The maximum number of scratch waves. Scratch space isn't divided
1614 * evenly between CUs. The number is only a function of the number of CUs.
1615 * We can decrease the constant to decrease the scratch buffer size.
1616 *
1617 * sctx->scratch_waves must be >= the maximum possible size of
1618 * 1 threadgroup, so that the hw doesn't hang from being unable
1619 * to start any.
1620 *
1621 * The recommended value is 4 per CU at most. Higher numbers don't
1622 * bring much benefit, but they still occupy chip resources (think
1623 * async compute). I've seen ~2% performance difference between 4 and 32.
1624 */
1625 uint32_t max_threads_per_block = 2048;
1626 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1627 max_threads_per_block / 64);
1628
1629 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1630
1631 if (device->physical_device->rad_info.chip_class >= CIK) {
1632 /* If the KMD allows it (there is a KMD hw register for it),
1633 * allow launching waves out-of-order.
1634 */
1635 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1636 }
1637
1638 radv_device_init_gs_info(device);
1639
1640 device->tess_offchip_block_dw_size =
1641 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1642 device->has_distributed_tess =
1643 device->physical_device->rad_info.chip_class >= VI &&
1644 device->physical_device->rad_info.max_se >= 2;
1645
1646 if (getenv("RADV_TRACE_FILE")) {
1647 const char *filename = getenv("RADV_TRACE_FILE");
1648
1649 keep_shader_info = true;
1650
1651 if (!radv_init_trace(device))
1652 goto fail;
1653
1654 fprintf(stderr, "*****************************************************************************\n");
1655 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1656 fprintf(stderr, "*****************************************************************************\n");
1657
1658 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1659 radv_dump_enabled_options(device, stderr);
1660 }
1661
1662 device->keep_shader_info = keep_shader_info;
1663
1664 result = radv_device_init_meta(device);
1665 if (result != VK_SUCCESS)
1666 goto fail;
1667
1668 radv_device_init_msaa(device);
1669
1670 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1671 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1672 switch (family) {
1673 case RADV_QUEUE_GENERAL:
1674 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1675 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1676 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1677 break;
1678 case RADV_QUEUE_COMPUTE:
1679 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1680 radeon_emit(device->empty_cs[family], 0);
1681 break;
1682 }
1683 device->ws->cs_finalize(device->empty_cs[family]);
1684 }
1685
1686 if (device->physical_device->rad_info.chip_class >= CIK)
1687 cik_create_gfx_config(device);
1688
1689 VkPipelineCacheCreateInfo ci;
1690 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1691 ci.pNext = NULL;
1692 ci.flags = 0;
1693 ci.pInitialData = NULL;
1694 ci.initialDataSize = 0;
1695 VkPipelineCache pc;
1696 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1697 &ci, NULL, &pc);
1698 if (result != VK_SUCCESS)
1699 goto fail_meta;
1700
1701 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1702
1703 device->force_aniso =
1704 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1705 if (device->force_aniso >= 0) {
1706 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1707 1 << util_logbase2(device->force_aniso));
1708 }
1709
1710 *pDevice = radv_device_to_handle(device);
1711 return VK_SUCCESS;
1712
1713 fail_meta:
1714 radv_device_finish_meta(device);
1715 fail:
1716 radv_bo_list_finish(&device->bo_list);
1717
1718 if (device->trace_bo)
1719 device->ws->buffer_destroy(device->trace_bo);
1720
1721 if (device->gfx_init)
1722 device->ws->buffer_destroy(device->gfx_init);
1723
1724 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1725 for (unsigned q = 0; q < device->queue_count[i]; q++)
1726 radv_queue_finish(&device->queues[i][q]);
1727 if (device->queue_count[i])
1728 vk_free(&device->alloc, device->queues[i]);
1729 }
1730
1731 vk_free(&device->alloc, device);
1732 return result;
1733 }
1734
1735 void radv_DestroyDevice(
1736 VkDevice _device,
1737 const VkAllocationCallbacks* pAllocator)
1738 {
1739 RADV_FROM_HANDLE(radv_device, device, _device);
1740
1741 if (!device)
1742 return;
1743
1744 if (device->trace_bo)
1745 device->ws->buffer_destroy(device->trace_bo);
1746
1747 if (device->gfx_init)
1748 device->ws->buffer_destroy(device->gfx_init);
1749
1750 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1751 for (unsigned q = 0; q < device->queue_count[i]; q++)
1752 radv_queue_finish(&device->queues[i][q]);
1753 if (device->queue_count[i])
1754 vk_free(&device->alloc, device->queues[i]);
1755 if (device->empty_cs[i])
1756 device->ws->cs_destroy(device->empty_cs[i]);
1757 }
1758 radv_device_finish_meta(device);
1759
1760 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1761 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1762
1763 radv_destroy_shader_slabs(device);
1764
1765 radv_bo_list_finish(&device->bo_list);
1766 vk_free(&device->alloc, device);
1767 }
1768
1769 VkResult radv_EnumerateInstanceLayerProperties(
1770 uint32_t* pPropertyCount,
1771 VkLayerProperties* pProperties)
1772 {
1773 if (pProperties == NULL) {
1774 *pPropertyCount = 0;
1775 return VK_SUCCESS;
1776 }
1777
1778 /* None supported at this time */
1779 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1780 }
1781
1782 VkResult radv_EnumerateDeviceLayerProperties(
1783 VkPhysicalDevice physicalDevice,
1784 uint32_t* pPropertyCount,
1785 VkLayerProperties* pProperties)
1786 {
1787 if (pProperties == NULL) {
1788 *pPropertyCount = 0;
1789 return VK_SUCCESS;
1790 }
1791
1792 /* None supported at this time */
1793 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1794 }
1795
1796 void radv_GetDeviceQueue2(
1797 VkDevice _device,
1798 const VkDeviceQueueInfo2* pQueueInfo,
1799 VkQueue* pQueue)
1800 {
1801 RADV_FROM_HANDLE(radv_device, device, _device);
1802 struct radv_queue *queue;
1803
1804 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1805 if (pQueueInfo->flags != queue->flags) {
1806 /* From the Vulkan 1.1.70 spec:
1807 *
1808 * "The queue returned by vkGetDeviceQueue2 must have the same
1809 * flags value from this structure as that used at device
1810 * creation time in a VkDeviceQueueCreateInfo instance. If no
1811 * matching flags were specified at device creation time then
1812 * pQueue will return VK_NULL_HANDLE."
1813 */
1814 *pQueue = VK_NULL_HANDLE;
1815 return;
1816 }
1817
1818 *pQueue = radv_queue_to_handle(queue);
1819 }
1820
1821 void radv_GetDeviceQueue(
1822 VkDevice _device,
1823 uint32_t queueFamilyIndex,
1824 uint32_t queueIndex,
1825 VkQueue* pQueue)
1826 {
1827 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1828 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1829 .queueFamilyIndex = queueFamilyIndex,
1830 .queueIndex = queueIndex
1831 };
1832
1833 radv_GetDeviceQueue2(_device, &info, pQueue);
1834 }
1835
1836 static void
1837 fill_geom_tess_rings(struct radv_queue *queue,
1838 uint32_t *map,
1839 bool add_sample_positions,
1840 uint32_t esgs_ring_size,
1841 struct radeon_winsys_bo *esgs_ring_bo,
1842 uint32_t gsvs_ring_size,
1843 struct radeon_winsys_bo *gsvs_ring_bo,
1844 uint32_t tess_factor_ring_size,
1845 uint32_t tess_offchip_ring_offset,
1846 uint32_t tess_offchip_ring_size,
1847 struct radeon_winsys_bo *tess_rings_bo)
1848 {
1849 uint64_t esgs_va = 0, gsvs_va = 0;
1850 uint64_t tess_va = 0, tess_offchip_va = 0;
1851 uint32_t *desc = &map[4];
1852
1853 if (esgs_ring_bo)
1854 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1855 if (gsvs_ring_bo)
1856 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1857 if (tess_rings_bo) {
1858 tess_va = radv_buffer_get_va(tess_rings_bo);
1859 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1860 }
1861
1862 /* stride 0, num records - size, add tid, swizzle, elsize4,
1863 index stride 64 */
1864 desc[0] = esgs_va;
1865 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1866 S_008F04_STRIDE(0) |
1867 S_008F04_SWIZZLE_ENABLE(true);
1868 desc[2] = esgs_ring_size;
1869 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1870 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1871 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1872 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1873 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1874 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1875 S_008F0C_ELEMENT_SIZE(1) |
1876 S_008F0C_INDEX_STRIDE(3) |
1877 S_008F0C_ADD_TID_ENABLE(true);
1878
1879 desc += 4;
1880 /* GS entry for ES->GS ring */
1881 /* stride 0, num records - size, elsize0,
1882 index stride 0 */
1883 desc[0] = esgs_va;
1884 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1885 S_008F04_STRIDE(0) |
1886 S_008F04_SWIZZLE_ENABLE(false);
1887 desc[2] = esgs_ring_size;
1888 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1889 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1890 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1891 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1892 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1893 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1894 S_008F0C_ELEMENT_SIZE(0) |
1895 S_008F0C_INDEX_STRIDE(0) |
1896 S_008F0C_ADD_TID_ENABLE(false);
1897
1898 desc += 4;
1899 /* VS entry for GS->VS ring */
1900 /* stride 0, num records - size, elsize0,
1901 index stride 0 */
1902 desc[0] = gsvs_va;
1903 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1904 S_008F04_STRIDE(0) |
1905 S_008F04_SWIZZLE_ENABLE(false);
1906 desc[2] = gsvs_ring_size;
1907 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1908 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1909 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1910 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1911 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1912 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1913 S_008F0C_ELEMENT_SIZE(0) |
1914 S_008F0C_INDEX_STRIDE(0) |
1915 S_008F0C_ADD_TID_ENABLE(false);
1916 desc += 4;
1917
1918 /* stride gsvs_itemsize, num records 64
1919 elsize 4, index stride 16 */
1920 /* shader will patch stride and desc[2] */
1921 desc[0] = gsvs_va;
1922 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1923 S_008F04_STRIDE(0) |
1924 S_008F04_SWIZZLE_ENABLE(true);
1925 desc[2] = 0;
1926 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1927 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1928 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1929 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1930 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1931 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1932 S_008F0C_ELEMENT_SIZE(1) |
1933 S_008F0C_INDEX_STRIDE(1) |
1934 S_008F0C_ADD_TID_ENABLE(true);
1935 desc += 4;
1936
1937 desc[0] = tess_va;
1938 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1939 S_008F04_STRIDE(0) |
1940 S_008F04_SWIZZLE_ENABLE(false);
1941 desc[2] = tess_factor_ring_size;
1942 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1943 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1944 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1945 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1946 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1947 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1948 S_008F0C_ELEMENT_SIZE(0) |
1949 S_008F0C_INDEX_STRIDE(0) |
1950 S_008F0C_ADD_TID_ENABLE(false);
1951 desc += 4;
1952
1953 desc[0] = tess_offchip_va;
1954 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1955 S_008F04_STRIDE(0) |
1956 S_008F04_SWIZZLE_ENABLE(false);
1957 desc[2] = tess_offchip_ring_size;
1958 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1959 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1960 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1961 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1962 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1963 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1964 S_008F0C_ELEMENT_SIZE(0) |
1965 S_008F0C_INDEX_STRIDE(0) |
1966 S_008F0C_ADD_TID_ENABLE(false);
1967 desc += 4;
1968
1969 /* add sample positions after all rings */
1970 memcpy(desc, queue->device->sample_locations_1x, 8);
1971 desc += 2;
1972 memcpy(desc, queue->device->sample_locations_2x, 16);
1973 desc += 4;
1974 memcpy(desc, queue->device->sample_locations_4x, 32);
1975 desc += 8;
1976 memcpy(desc, queue->device->sample_locations_8x, 64);
1977 desc += 16;
1978 memcpy(desc, queue->device->sample_locations_16x, 128);
1979 }
1980
1981 static unsigned
1982 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1983 {
1984 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1985 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1986 device->physical_device->rad_info.family != CHIP_STONEY;
1987 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1988 unsigned max_offchip_buffers;
1989 unsigned offchip_granularity;
1990 unsigned hs_offchip_param;
1991
1992 /*
1993 * Per RadeonSI:
1994 * This must be one less than the maximum number due to a hw limitation.
1995 * Various hardware bugs in SI, CIK, and GFX9 need this.
1996 *
1997 * Per AMDVLK:
1998 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1999 * Gfx7 should limit max_offchip_buffers to 508
2000 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2001 *
2002 * Follow AMDVLK here.
2003 */
2004 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2005 device->physical_device->rad_info.chip_class == CIK ||
2006 device->physical_device->rad_info.chip_class == SI)
2007 --max_offchip_buffers_per_se;
2008
2009 max_offchip_buffers = max_offchip_buffers_per_se *
2010 device->physical_device->rad_info.max_se;
2011
2012 switch (device->tess_offchip_block_dw_size) {
2013 default:
2014 assert(0);
2015 /* fall through */
2016 case 8192:
2017 offchip_granularity = V_03093C_X_8K_DWORDS;
2018 break;
2019 case 4096:
2020 offchip_granularity = V_03093C_X_4K_DWORDS;
2021 break;
2022 }
2023
2024 switch (device->physical_device->rad_info.chip_class) {
2025 case SI:
2026 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2027 break;
2028 case CIK:
2029 case VI:
2030 case GFX9:
2031 default:
2032 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2033 break;
2034 }
2035
2036 *max_offchip_buffers_p = max_offchip_buffers;
2037 if (device->physical_device->rad_info.chip_class >= CIK) {
2038 if (device->physical_device->rad_info.chip_class >= VI)
2039 --max_offchip_buffers;
2040 hs_offchip_param =
2041 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2042 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2043 } else {
2044 hs_offchip_param =
2045 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2046 }
2047 return hs_offchip_param;
2048 }
2049
2050 static void
2051 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2052 struct radeon_winsys_bo *esgs_ring_bo,
2053 uint32_t esgs_ring_size,
2054 struct radeon_winsys_bo *gsvs_ring_bo,
2055 uint32_t gsvs_ring_size)
2056 {
2057 if (!esgs_ring_bo && !gsvs_ring_bo)
2058 return;
2059
2060 if (esgs_ring_bo)
2061 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2062
2063 if (gsvs_ring_bo)
2064 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2065
2066 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2067 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2068 radeon_emit(cs, esgs_ring_size >> 8);
2069 radeon_emit(cs, gsvs_ring_size >> 8);
2070 } else {
2071 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2072 radeon_emit(cs, esgs_ring_size >> 8);
2073 radeon_emit(cs, gsvs_ring_size >> 8);
2074 }
2075 }
2076
2077 static void
2078 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2079 unsigned hs_offchip_param, unsigned tf_ring_size,
2080 struct radeon_winsys_bo *tess_rings_bo)
2081 {
2082 uint64_t tf_va;
2083
2084 if (!tess_rings_bo)
2085 return;
2086
2087 tf_va = radv_buffer_get_va(tess_rings_bo);
2088
2089 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2090
2091 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2092 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2093 S_030938_SIZE(tf_ring_size / 4));
2094 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2095 tf_va >> 8);
2096 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2097 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2098 S_030944_BASE_HI(tf_va >> 40));
2099 }
2100 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2101 hs_offchip_param);
2102 } else {
2103 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2104 S_008988_SIZE(tf_ring_size / 4));
2105 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2106 tf_va >> 8);
2107 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2108 hs_offchip_param);
2109 }
2110 }
2111
2112 static void
2113 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2114 struct radeon_winsys_bo *compute_scratch_bo)
2115 {
2116 uint64_t scratch_va;
2117
2118 if (!compute_scratch_bo)
2119 return;
2120
2121 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2122
2123 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2124
2125 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2126 radeon_emit(cs, scratch_va);
2127 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2128 S_008F04_SWIZZLE_ENABLE(1));
2129 }
2130
2131 static void
2132 radv_emit_global_shader_pointers(struct radv_queue *queue,
2133 struct radeon_cmdbuf *cs,
2134 struct radeon_winsys_bo *descriptor_bo)
2135 {
2136 uint64_t va;
2137
2138 if (!descriptor_bo)
2139 return;
2140
2141 va = radv_buffer_get_va(descriptor_bo);
2142
2143 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2144
2145 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2146 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2147 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2148 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2149 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2150
2151 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2152 radv_emit_shader_pointer(queue->device, cs, regs[i],
2153 va, true);
2154 }
2155 } else {
2156 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2157 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2158 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2159 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2160 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2161 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2162
2163 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2164 radv_emit_shader_pointer(queue->device, cs, regs[i],
2165 va, true);
2166 }
2167 }
2168 }
2169
2170 static void
2171 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2172 {
2173 struct radv_device *device = queue->device;
2174
2175 if (device->gfx_init) {
2176 uint64_t va = radv_buffer_get_va(device->gfx_init);
2177
2178 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2179 radeon_emit(cs, va);
2180 radeon_emit(cs, va >> 32);
2181 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2182
2183 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2184 } else {
2185 struct radv_physical_device *physical_device = device->physical_device;
2186 si_emit_graphics(physical_device, cs);
2187 }
2188 }
2189
2190 static void
2191 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2192 {
2193 struct radv_physical_device *physical_device = queue->device->physical_device;
2194 si_emit_compute(physical_device, cs);
2195 }
2196
2197 static VkResult
2198 radv_get_preamble_cs(struct radv_queue *queue,
2199 uint32_t scratch_size,
2200 uint32_t compute_scratch_size,
2201 uint32_t esgs_ring_size,
2202 uint32_t gsvs_ring_size,
2203 bool needs_tess_rings,
2204 bool needs_sample_positions,
2205 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2206 struct radeon_cmdbuf **initial_preamble_cs,
2207 struct radeon_cmdbuf **continue_preamble_cs)
2208 {
2209 struct radeon_winsys_bo *scratch_bo = NULL;
2210 struct radeon_winsys_bo *descriptor_bo = NULL;
2211 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2212 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2213 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2214 struct radeon_winsys_bo *tess_rings_bo = NULL;
2215 struct radeon_cmdbuf *dest_cs[3] = {0};
2216 bool add_tess_rings = false, add_sample_positions = false;
2217 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2218 unsigned max_offchip_buffers;
2219 unsigned hs_offchip_param = 0;
2220 unsigned tess_offchip_ring_offset;
2221 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2222 if (!queue->has_tess_rings) {
2223 if (needs_tess_rings)
2224 add_tess_rings = true;
2225 }
2226 if (!queue->has_sample_positions) {
2227 if (needs_sample_positions)
2228 add_sample_positions = true;
2229 }
2230 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2231 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2232 &max_offchip_buffers);
2233 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2234 tess_offchip_ring_size = max_offchip_buffers *
2235 queue->device->tess_offchip_block_dw_size * 4;
2236
2237 if (scratch_size <= queue->scratch_size &&
2238 compute_scratch_size <= queue->compute_scratch_size &&
2239 esgs_ring_size <= queue->esgs_ring_size &&
2240 gsvs_ring_size <= queue->gsvs_ring_size &&
2241 !add_tess_rings && !add_sample_positions &&
2242 queue->initial_preamble_cs) {
2243 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2244 *initial_preamble_cs = queue->initial_preamble_cs;
2245 *continue_preamble_cs = queue->continue_preamble_cs;
2246 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2247 *continue_preamble_cs = NULL;
2248 return VK_SUCCESS;
2249 }
2250
2251 if (scratch_size > queue->scratch_size) {
2252 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2253 scratch_size,
2254 4096,
2255 RADEON_DOMAIN_VRAM,
2256 ring_bo_flags);
2257 if (!scratch_bo)
2258 goto fail;
2259 } else
2260 scratch_bo = queue->scratch_bo;
2261
2262 if (compute_scratch_size > queue->compute_scratch_size) {
2263 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2264 compute_scratch_size,
2265 4096,
2266 RADEON_DOMAIN_VRAM,
2267 ring_bo_flags);
2268 if (!compute_scratch_bo)
2269 goto fail;
2270
2271 } else
2272 compute_scratch_bo = queue->compute_scratch_bo;
2273
2274 if (esgs_ring_size > queue->esgs_ring_size) {
2275 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2276 esgs_ring_size,
2277 4096,
2278 RADEON_DOMAIN_VRAM,
2279 ring_bo_flags);
2280 if (!esgs_ring_bo)
2281 goto fail;
2282 } else {
2283 esgs_ring_bo = queue->esgs_ring_bo;
2284 esgs_ring_size = queue->esgs_ring_size;
2285 }
2286
2287 if (gsvs_ring_size > queue->gsvs_ring_size) {
2288 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2289 gsvs_ring_size,
2290 4096,
2291 RADEON_DOMAIN_VRAM,
2292 ring_bo_flags);
2293 if (!gsvs_ring_bo)
2294 goto fail;
2295 } else {
2296 gsvs_ring_bo = queue->gsvs_ring_bo;
2297 gsvs_ring_size = queue->gsvs_ring_size;
2298 }
2299
2300 if (add_tess_rings) {
2301 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2302 tess_offchip_ring_offset + tess_offchip_ring_size,
2303 256,
2304 RADEON_DOMAIN_VRAM,
2305 ring_bo_flags);
2306 if (!tess_rings_bo)
2307 goto fail;
2308 } else {
2309 tess_rings_bo = queue->tess_rings_bo;
2310 }
2311
2312 if (scratch_bo != queue->scratch_bo ||
2313 esgs_ring_bo != queue->esgs_ring_bo ||
2314 gsvs_ring_bo != queue->gsvs_ring_bo ||
2315 tess_rings_bo != queue->tess_rings_bo ||
2316 add_sample_positions) {
2317 uint32_t size = 0;
2318 if (gsvs_ring_bo || esgs_ring_bo ||
2319 tess_rings_bo || add_sample_positions) {
2320 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2321 if (add_sample_positions)
2322 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2323 }
2324 else if (scratch_bo)
2325 size = 8; /* 2 dword */
2326
2327 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2328 size,
2329 4096,
2330 RADEON_DOMAIN_VRAM,
2331 RADEON_FLAG_CPU_ACCESS |
2332 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2333 RADEON_FLAG_READ_ONLY);
2334 if (!descriptor_bo)
2335 goto fail;
2336 } else
2337 descriptor_bo = queue->descriptor_bo;
2338
2339 for(int i = 0; i < 3; ++i) {
2340 struct radeon_cmdbuf *cs = NULL;
2341 cs = queue->device->ws->cs_create(queue->device->ws,
2342 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2343 if (!cs)
2344 goto fail;
2345
2346 dest_cs[i] = cs;
2347
2348 if (scratch_bo)
2349 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2350
2351 /* Emit initial configuration. */
2352 switch (queue->queue_family_index) {
2353 case RADV_QUEUE_GENERAL:
2354 radv_init_graphics_state(cs, queue);
2355 break;
2356 case RADV_QUEUE_COMPUTE:
2357 radv_init_compute_state(cs, queue);
2358 break;
2359 case RADV_QUEUE_TRANSFER:
2360 break;
2361 }
2362
2363 if (descriptor_bo != queue->descriptor_bo) {
2364 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2365
2366 if (scratch_bo) {
2367 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2368 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2369 S_008F04_SWIZZLE_ENABLE(1);
2370 map[0] = scratch_va;
2371 map[1] = rsrc1;
2372 }
2373
2374 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2375 add_sample_positions)
2376 fill_geom_tess_rings(queue, map, add_sample_positions,
2377 esgs_ring_size, esgs_ring_bo,
2378 gsvs_ring_size, gsvs_ring_bo,
2379 tess_factor_ring_size,
2380 tess_offchip_ring_offset,
2381 tess_offchip_ring_size,
2382 tess_rings_bo);
2383
2384 queue->device->ws->buffer_unmap(descriptor_bo);
2385 }
2386
2387 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2388 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2389 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2390 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2391 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2392 }
2393
2394 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2395 gsvs_ring_bo, gsvs_ring_size);
2396 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2397 tess_factor_ring_size, tess_rings_bo);
2398 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2399 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2400
2401 if (i == 0) {
2402 si_cs_emit_cache_flush(cs,
2403 queue->device->physical_device->rad_info.chip_class,
2404 NULL, 0,
2405 queue->queue_family_index == RING_COMPUTE &&
2406 queue->device->physical_device->rad_info.chip_class >= CIK,
2407 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2408 RADV_CMD_FLAG_INV_ICACHE |
2409 RADV_CMD_FLAG_INV_SMEM_L1 |
2410 RADV_CMD_FLAG_INV_VMEM_L1 |
2411 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2412 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2413 } else if (i == 1) {
2414 si_cs_emit_cache_flush(cs,
2415 queue->device->physical_device->rad_info.chip_class,
2416 NULL, 0,
2417 queue->queue_family_index == RING_COMPUTE &&
2418 queue->device->physical_device->rad_info.chip_class >= CIK,
2419 RADV_CMD_FLAG_INV_ICACHE |
2420 RADV_CMD_FLAG_INV_SMEM_L1 |
2421 RADV_CMD_FLAG_INV_VMEM_L1 |
2422 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2423 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2424 }
2425
2426 if (!queue->device->ws->cs_finalize(cs))
2427 goto fail;
2428 }
2429
2430 if (queue->initial_full_flush_preamble_cs)
2431 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2432
2433 if (queue->initial_preamble_cs)
2434 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2435
2436 if (queue->continue_preamble_cs)
2437 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2438
2439 queue->initial_full_flush_preamble_cs = dest_cs[0];
2440 queue->initial_preamble_cs = dest_cs[1];
2441 queue->continue_preamble_cs = dest_cs[2];
2442
2443 if (scratch_bo != queue->scratch_bo) {
2444 if (queue->scratch_bo)
2445 queue->device->ws->buffer_destroy(queue->scratch_bo);
2446 queue->scratch_bo = scratch_bo;
2447 queue->scratch_size = scratch_size;
2448 }
2449
2450 if (compute_scratch_bo != queue->compute_scratch_bo) {
2451 if (queue->compute_scratch_bo)
2452 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2453 queue->compute_scratch_bo = compute_scratch_bo;
2454 queue->compute_scratch_size = compute_scratch_size;
2455 }
2456
2457 if (esgs_ring_bo != queue->esgs_ring_bo) {
2458 if (queue->esgs_ring_bo)
2459 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2460 queue->esgs_ring_bo = esgs_ring_bo;
2461 queue->esgs_ring_size = esgs_ring_size;
2462 }
2463
2464 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2465 if (queue->gsvs_ring_bo)
2466 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2467 queue->gsvs_ring_bo = gsvs_ring_bo;
2468 queue->gsvs_ring_size = gsvs_ring_size;
2469 }
2470
2471 if (tess_rings_bo != queue->tess_rings_bo) {
2472 queue->tess_rings_bo = tess_rings_bo;
2473 queue->has_tess_rings = true;
2474 }
2475
2476 if (descriptor_bo != queue->descriptor_bo) {
2477 if (queue->descriptor_bo)
2478 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2479
2480 queue->descriptor_bo = descriptor_bo;
2481 }
2482
2483 if (add_sample_positions)
2484 queue->has_sample_positions = true;
2485
2486 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2487 *initial_preamble_cs = queue->initial_preamble_cs;
2488 *continue_preamble_cs = queue->continue_preamble_cs;
2489 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2490 *continue_preamble_cs = NULL;
2491 return VK_SUCCESS;
2492 fail:
2493 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2494 if (dest_cs[i])
2495 queue->device->ws->cs_destroy(dest_cs[i]);
2496 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2497 queue->device->ws->buffer_destroy(descriptor_bo);
2498 if (scratch_bo && scratch_bo != queue->scratch_bo)
2499 queue->device->ws->buffer_destroy(scratch_bo);
2500 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2501 queue->device->ws->buffer_destroy(compute_scratch_bo);
2502 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2503 queue->device->ws->buffer_destroy(esgs_ring_bo);
2504 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2505 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2506 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2507 queue->device->ws->buffer_destroy(tess_rings_bo);
2508 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2509 }
2510
2511 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2512 struct radv_winsys_sem_counts *counts,
2513 int num_sems,
2514 const VkSemaphore *sems,
2515 VkFence _fence,
2516 bool reset_temp)
2517 {
2518 int syncobj_idx = 0, sem_idx = 0;
2519
2520 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2521 return VK_SUCCESS;
2522
2523 for (uint32_t i = 0; i < num_sems; i++) {
2524 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2525
2526 if (sem->temp_syncobj || sem->syncobj)
2527 counts->syncobj_count++;
2528 else
2529 counts->sem_count++;
2530 }
2531
2532 if (_fence != VK_NULL_HANDLE) {
2533 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2534 if (fence->temp_syncobj || fence->syncobj)
2535 counts->syncobj_count++;
2536 }
2537
2538 if (counts->syncobj_count) {
2539 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2540 if (!counts->syncobj)
2541 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2542 }
2543
2544 if (counts->sem_count) {
2545 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2546 if (!counts->sem) {
2547 free(counts->syncobj);
2548 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2549 }
2550 }
2551
2552 for (uint32_t i = 0; i < num_sems; i++) {
2553 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2554
2555 if (sem->temp_syncobj) {
2556 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2557 }
2558 else if (sem->syncobj)
2559 counts->syncobj[syncobj_idx++] = sem->syncobj;
2560 else {
2561 assert(sem->sem);
2562 counts->sem[sem_idx++] = sem->sem;
2563 }
2564 }
2565
2566 if (_fence != VK_NULL_HANDLE) {
2567 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2568 if (fence->temp_syncobj)
2569 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2570 else if (fence->syncobj)
2571 counts->syncobj[syncobj_idx++] = fence->syncobj;
2572 }
2573
2574 return VK_SUCCESS;
2575 }
2576
2577 static void
2578 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2579 {
2580 free(sem_info->wait.syncobj);
2581 free(sem_info->wait.sem);
2582 free(sem_info->signal.syncobj);
2583 free(sem_info->signal.sem);
2584 }
2585
2586
2587 static void radv_free_temp_syncobjs(struct radv_device *device,
2588 int num_sems,
2589 const VkSemaphore *sems)
2590 {
2591 for (uint32_t i = 0; i < num_sems; i++) {
2592 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2593
2594 if (sem->temp_syncobj) {
2595 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2596 sem->temp_syncobj = 0;
2597 }
2598 }
2599 }
2600
2601 static VkResult
2602 radv_alloc_sem_info(struct radv_instance *instance,
2603 struct radv_winsys_sem_info *sem_info,
2604 int num_wait_sems,
2605 const VkSemaphore *wait_sems,
2606 int num_signal_sems,
2607 const VkSemaphore *signal_sems,
2608 VkFence fence)
2609 {
2610 VkResult ret;
2611 memset(sem_info, 0, sizeof(*sem_info));
2612
2613 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2614 if (ret)
2615 return ret;
2616 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2617 if (ret)
2618 radv_free_sem_info(sem_info);
2619
2620 /* caller can override these */
2621 sem_info->cs_emit_wait = true;
2622 sem_info->cs_emit_signal = true;
2623 return ret;
2624 }
2625
2626 /* Signals fence as soon as all the work currently put on queue is done. */
2627 static VkResult radv_signal_fence(struct radv_queue *queue,
2628 struct radv_fence *fence)
2629 {
2630 int ret;
2631 VkResult result;
2632 struct radv_winsys_sem_info sem_info;
2633
2634 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2635 radv_fence_to_handle(fence));
2636 if (result != VK_SUCCESS)
2637 return result;
2638
2639 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2640 &queue->device->empty_cs[queue->queue_family_index],
2641 1, NULL, NULL, &sem_info, NULL,
2642 false, fence->fence);
2643 radv_free_sem_info(&sem_info);
2644
2645 if (ret)
2646 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2647
2648 return VK_SUCCESS;
2649 }
2650
2651 VkResult radv_QueueSubmit(
2652 VkQueue _queue,
2653 uint32_t submitCount,
2654 const VkSubmitInfo* pSubmits,
2655 VkFence _fence)
2656 {
2657 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2658 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2659 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2660 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2661 int ret;
2662 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2663 uint32_t scratch_size = 0;
2664 uint32_t compute_scratch_size = 0;
2665 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2666 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2667 VkResult result;
2668 bool fence_emitted = false;
2669 bool tess_rings_needed = false;
2670 bool sample_positions_needed = false;
2671
2672 /* Do this first so failing to allocate scratch buffers can't result in
2673 * partially executed submissions. */
2674 for (uint32_t i = 0; i < submitCount; i++) {
2675 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2676 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2677 pSubmits[i].pCommandBuffers[j]);
2678
2679 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2680 compute_scratch_size = MAX2(compute_scratch_size,
2681 cmd_buffer->compute_scratch_size_needed);
2682 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2683 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2684 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2685 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2686 }
2687 }
2688
2689 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2690 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2691 sample_positions_needed, &initial_flush_preamble_cs,
2692 &initial_preamble_cs, &continue_preamble_cs);
2693 if (result != VK_SUCCESS)
2694 return result;
2695
2696 for (uint32_t i = 0; i < submitCount; i++) {
2697 struct radeon_cmdbuf **cs_array;
2698 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2699 bool can_patch = true;
2700 uint32_t advance;
2701 struct radv_winsys_sem_info sem_info;
2702
2703 result = radv_alloc_sem_info(queue->device->instance,
2704 &sem_info,
2705 pSubmits[i].waitSemaphoreCount,
2706 pSubmits[i].pWaitSemaphores,
2707 pSubmits[i].signalSemaphoreCount,
2708 pSubmits[i].pSignalSemaphores,
2709 _fence);
2710 if (result != VK_SUCCESS)
2711 return result;
2712
2713 if (!pSubmits[i].commandBufferCount) {
2714 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2715 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2716 &queue->device->empty_cs[queue->queue_family_index],
2717 1, NULL, NULL,
2718 &sem_info, NULL,
2719 false, base_fence);
2720 if (ret) {
2721 radv_loge("failed to submit CS %d\n", i);
2722 abort();
2723 }
2724 fence_emitted = true;
2725 }
2726 radv_free_sem_info(&sem_info);
2727 continue;
2728 }
2729
2730 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2731 (pSubmits[i].commandBufferCount));
2732
2733 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2734 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2735 pSubmits[i].pCommandBuffers[j]);
2736 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2737
2738 cs_array[j] = cmd_buffer->cs;
2739 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2740 can_patch = false;
2741
2742 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2743 }
2744
2745 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2746 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2747 const struct radv_winsys_bo_list *bo_list = NULL;
2748
2749 advance = MIN2(max_cs_submission,
2750 pSubmits[i].commandBufferCount - j);
2751
2752 if (queue->device->trace_bo)
2753 *queue->device->trace_id_ptr = 0;
2754
2755 sem_info.cs_emit_wait = j == 0;
2756 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2757
2758 if (unlikely(queue->device->use_global_bo_list)) {
2759 pthread_mutex_lock(&queue->device->bo_list.mutex);
2760 bo_list = &queue->device->bo_list.list;
2761 }
2762
2763 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2764 advance, initial_preamble, continue_preamble_cs,
2765 &sem_info, bo_list,
2766 can_patch, base_fence);
2767
2768 if (unlikely(queue->device->use_global_bo_list))
2769 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2770
2771 if (ret) {
2772 radv_loge("failed to submit CS %d\n", i);
2773 abort();
2774 }
2775 fence_emitted = true;
2776 if (queue->device->trace_bo) {
2777 radv_check_gpu_hangs(queue, cs_array[j]);
2778 }
2779 }
2780
2781 radv_free_temp_syncobjs(queue->device,
2782 pSubmits[i].waitSemaphoreCount,
2783 pSubmits[i].pWaitSemaphores);
2784 radv_free_sem_info(&sem_info);
2785 free(cs_array);
2786 }
2787
2788 if (fence) {
2789 if (!fence_emitted) {
2790 result = radv_signal_fence(queue, fence);
2791 if (result != VK_SUCCESS)
2792 return result;
2793 }
2794 fence->submitted = true;
2795 }
2796
2797 return VK_SUCCESS;
2798 }
2799
2800 VkResult radv_QueueWaitIdle(
2801 VkQueue _queue)
2802 {
2803 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2804
2805 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2806 radv_queue_family_to_ring(queue->queue_family_index),
2807 queue->queue_idx);
2808 return VK_SUCCESS;
2809 }
2810
2811 VkResult radv_DeviceWaitIdle(
2812 VkDevice _device)
2813 {
2814 RADV_FROM_HANDLE(radv_device, device, _device);
2815
2816 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2817 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2818 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2819 }
2820 }
2821 return VK_SUCCESS;
2822 }
2823
2824 VkResult radv_EnumerateInstanceExtensionProperties(
2825 const char* pLayerName,
2826 uint32_t* pPropertyCount,
2827 VkExtensionProperties* pProperties)
2828 {
2829 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2830
2831 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2832 if (radv_supported_instance_extensions.extensions[i]) {
2833 vk_outarray_append(&out, prop) {
2834 *prop = radv_instance_extensions[i];
2835 }
2836 }
2837 }
2838
2839 return vk_outarray_status(&out);
2840 }
2841
2842 VkResult radv_EnumerateDeviceExtensionProperties(
2843 VkPhysicalDevice physicalDevice,
2844 const char* pLayerName,
2845 uint32_t* pPropertyCount,
2846 VkExtensionProperties* pProperties)
2847 {
2848 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2849 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2850
2851 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2852 if (device->supported_extensions.extensions[i]) {
2853 vk_outarray_append(&out, prop) {
2854 *prop = radv_device_extensions[i];
2855 }
2856 }
2857 }
2858
2859 return vk_outarray_status(&out);
2860 }
2861
2862 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2863 VkInstance _instance,
2864 const char* pName)
2865 {
2866 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2867
2868 return radv_lookup_entrypoint_checked(pName,
2869 instance ? instance->apiVersion : 0,
2870 instance ? &instance->enabled_extensions : NULL,
2871 NULL);
2872 }
2873
2874 /* The loader wants us to expose a second GetInstanceProcAddr function
2875 * to work around certain LD_PRELOAD issues seen in apps.
2876 */
2877 PUBLIC
2878 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2879 VkInstance instance,
2880 const char* pName);
2881
2882 PUBLIC
2883 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2884 VkInstance instance,
2885 const char* pName)
2886 {
2887 return radv_GetInstanceProcAddr(instance, pName);
2888 }
2889
2890 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2891 VkDevice _device,
2892 const char* pName)
2893 {
2894 RADV_FROM_HANDLE(radv_device, device, _device);
2895
2896 return radv_lookup_entrypoint_checked(pName,
2897 device->instance->apiVersion,
2898 &device->instance->enabled_extensions,
2899 &device->enabled_extensions);
2900 }
2901
2902 bool radv_get_memory_fd(struct radv_device *device,
2903 struct radv_device_memory *memory,
2904 int *pFD)
2905 {
2906 struct radeon_bo_metadata metadata;
2907
2908 if (memory->image) {
2909 radv_init_metadata(device, memory->image, &metadata);
2910 device->ws->buffer_set_metadata(memory->bo, &metadata);
2911 }
2912
2913 return device->ws->buffer_get_fd(device->ws, memory->bo,
2914 pFD);
2915 }
2916
2917 static VkResult radv_alloc_memory(struct radv_device *device,
2918 const VkMemoryAllocateInfo* pAllocateInfo,
2919 const VkAllocationCallbacks* pAllocator,
2920 VkDeviceMemory* pMem)
2921 {
2922 struct radv_device_memory *mem;
2923 VkResult result;
2924 enum radeon_bo_domain domain;
2925 uint32_t flags = 0;
2926 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2927
2928 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2929
2930 if (pAllocateInfo->allocationSize == 0) {
2931 /* Apparently, this is allowed */
2932 *pMem = VK_NULL_HANDLE;
2933 return VK_SUCCESS;
2934 }
2935
2936 const VkImportMemoryFdInfoKHR *import_info =
2937 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2938 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2939 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2940 const VkExportMemoryAllocateInfoKHR *export_info =
2941 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2942 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2943 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2944
2945 const struct wsi_memory_allocate_info *wsi_info =
2946 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2947
2948 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2949 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2950 if (mem == NULL)
2951 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2952
2953 if (wsi_info && wsi_info->implicit_sync)
2954 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2955
2956 if (dedicate_info) {
2957 mem->image = radv_image_from_handle(dedicate_info->image);
2958 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2959 } else {
2960 mem->image = NULL;
2961 mem->buffer = NULL;
2962 }
2963
2964 mem->user_ptr = NULL;
2965
2966 if (import_info) {
2967 assert(import_info->handleType ==
2968 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2969 import_info->handleType ==
2970 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2971 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2972 NULL, NULL);
2973 if (!mem->bo) {
2974 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2975 goto fail;
2976 } else {
2977 close(import_info->fd);
2978 }
2979 } else if (host_ptr_info) {
2980 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2981 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2982 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2983 pAllocateInfo->allocationSize);
2984 if (!mem->bo) {
2985 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2986 goto fail;
2987 } else {
2988 mem->user_ptr = host_ptr_info->pHostPointer;
2989 }
2990 } else {
2991 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2992 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2993 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2994 domain = RADEON_DOMAIN_GTT;
2995 else
2996 domain = RADEON_DOMAIN_VRAM;
2997
2998 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2999 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3000 else
3001 flags |= RADEON_FLAG_CPU_ACCESS;
3002
3003 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3004 flags |= RADEON_FLAG_GTT_WC;
3005
3006 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3007 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3008
3009 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3010 domain, flags);
3011
3012 if (!mem->bo) {
3013 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3014 goto fail;
3015 }
3016 mem->type_index = mem_type_index;
3017 }
3018
3019 result = radv_bo_list_add(device, mem->bo);
3020 if (result != VK_SUCCESS)
3021 goto fail_bo;
3022
3023 *pMem = radv_device_memory_to_handle(mem);
3024
3025 return VK_SUCCESS;
3026
3027 fail_bo:
3028 device->ws->buffer_destroy(mem->bo);
3029 fail:
3030 vk_free2(&device->alloc, pAllocator, mem);
3031
3032 return result;
3033 }
3034
3035 VkResult radv_AllocateMemory(
3036 VkDevice _device,
3037 const VkMemoryAllocateInfo* pAllocateInfo,
3038 const VkAllocationCallbacks* pAllocator,
3039 VkDeviceMemory* pMem)
3040 {
3041 RADV_FROM_HANDLE(radv_device, device, _device);
3042 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3043 }
3044
3045 void radv_FreeMemory(
3046 VkDevice _device,
3047 VkDeviceMemory _mem,
3048 const VkAllocationCallbacks* pAllocator)
3049 {
3050 RADV_FROM_HANDLE(radv_device, device, _device);
3051 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3052
3053 if (mem == NULL)
3054 return;
3055
3056 radv_bo_list_remove(device, mem->bo);
3057 device->ws->buffer_destroy(mem->bo);
3058 mem->bo = NULL;
3059
3060 vk_free2(&device->alloc, pAllocator, mem);
3061 }
3062
3063 VkResult radv_MapMemory(
3064 VkDevice _device,
3065 VkDeviceMemory _memory,
3066 VkDeviceSize offset,
3067 VkDeviceSize size,
3068 VkMemoryMapFlags flags,
3069 void** ppData)
3070 {
3071 RADV_FROM_HANDLE(radv_device, device, _device);
3072 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3073
3074 if (mem == NULL) {
3075 *ppData = NULL;
3076 return VK_SUCCESS;
3077 }
3078
3079 if (mem->user_ptr)
3080 *ppData = mem->user_ptr;
3081 else
3082 *ppData = device->ws->buffer_map(mem->bo);
3083
3084 if (*ppData) {
3085 *ppData += offset;
3086 return VK_SUCCESS;
3087 }
3088
3089 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3090 }
3091
3092 void radv_UnmapMemory(
3093 VkDevice _device,
3094 VkDeviceMemory _memory)
3095 {
3096 RADV_FROM_HANDLE(radv_device, device, _device);
3097 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3098
3099 if (mem == NULL)
3100 return;
3101
3102 if (mem->user_ptr == NULL)
3103 device->ws->buffer_unmap(mem->bo);
3104 }
3105
3106 VkResult radv_FlushMappedMemoryRanges(
3107 VkDevice _device,
3108 uint32_t memoryRangeCount,
3109 const VkMappedMemoryRange* pMemoryRanges)
3110 {
3111 return VK_SUCCESS;
3112 }
3113
3114 VkResult radv_InvalidateMappedMemoryRanges(
3115 VkDevice _device,
3116 uint32_t memoryRangeCount,
3117 const VkMappedMemoryRange* pMemoryRanges)
3118 {
3119 return VK_SUCCESS;
3120 }
3121
3122 void radv_GetBufferMemoryRequirements(
3123 VkDevice _device,
3124 VkBuffer _buffer,
3125 VkMemoryRequirements* pMemoryRequirements)
3126 {
3127 RADV_FROM_HANDLE(radv_device, device, _device);
3128 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3129
3130 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3131
3132 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3133 pMemoryRequirements->alignment = 4096;
3134 else
3135 pMemoryRequirements->alignment = 16;
3136
3137 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3138 }
3139
3140 void radv_GetBufferMemoryRequirements2(
3141 VkDevice device,
3142 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3143 VkMemoryRequirements2KHR* pMemoryRequirements)
3144 {
3145 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3146 &pMemoryRequirements->memoryRequirements);
3147 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3148 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3149 switch (ext->sType) {
3150 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3151 VkMemoryDedicatedRequirementsKHR *req =
3152 (VkMemoryDedicatedRequirementsKHR *) ext;
3153 req->requiresDedicatedAllocation = buffer->shareable;
3154 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3155 break;
3156 }
3157 default:
3158 break;
3159 }
3160 }
3161 }
3162
3163 void radv_GetImageMemoryRequirements(
3164 VkDevice _device,
3165 VkImage _image,
3166 VkMemoryRequirements* pMemoryRequirements)
3167 {
3168 RADV_FROM_HANDLE(radv_device, device, _device);
3169 RADV_FROM_HANDLE(radv_image, image, _image);
3170
3171 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3172
3173 pMemoryRequirements->size = image->size;
3174 pMemoryRequirements->alignment = image->alignment;
3175 }
3176
3177 void radv_GetImageMemoryRequirements2(
3178 VkDevice device,
3179 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3180 VkMemoryRequirements2KHR* pMemoryRequirements)
3181 {
3182 radv_GetImageMemoryRequirements(device, pInfo->image,
3183 &pMemoryRequirements->memoryRequirements);
3184
3185 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3186
3187 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3188 switch (ext->sType) {
3189 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3190 VkMemoryDedicatedRequirementsKHR *req =
3191 (VkMemoryDedicatedRequirementsKHR *) ext;
3192 req->requiresDedicatedAllocation = image->shareable;
3193 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3194 break;
3195 }
3196 default:
3197 break;
3198 }
3199 }
3200 }
3201
3202 void radv_GetImageSparseMemoryRequirements(
3203 VkDevice device,
3204 VkImage image,
3205 uint32_t* pSparseMemoryRequirementCount,
3206 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3207 {
3208 stub();
3209 }
3210
3211 void radv_GetImageSparseMemoryRequirements2(
3212 VkDevice device,
3213 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3214 uint32_t* pSparseMemoryRequirementCount,
3215 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3216 {
3217 stub();
3218 }
3219
3220 void radv_GetDeviceMemoryCommitment(
3221 VkDevice device,
3222 VkDeviceMemory memory,
3223 VkDeviceSize* pCommittedMemoryInBytes)
3224 {
3225 *pCommittedMemoryInBytes = 0;
3226 }
3227
3228 VkResult radv_BindBufferMemory2(VkDevice device,
3229 uint32_t bindInfoCount,
3230 const VkBindBufferMemoryInfoKHR *pBindInfos)
3231 {
3232 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3233 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3234 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3235
3236 if (mem) {
3237 buffer->bo = mem->bo;
3238 buffer->offset = pBindInfos[i].memoryOffset;
3239 } else {
3240 buffer->bo = NULL;
3241 }
3242 }
3243 return VK_SUCCESS;
3244 }
3245
3246 VkResult radv_BindBufferMemory(
3247 VkDevice device,
3248 VkBuffer buffer,
3249 VkDeviceMemory memory,
3250 VkDeviceSize memoryOffset)
3251 {
3252 const VkBindBufferMemoryInfoKHR info = {
3253 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3254 .buffer = buffer,
3255 .memory = memory,
3256 .memoryOffset = memoryOffset
3257 };
3258
3259 return radv_BindBufferMemory2(device, 1, &info);
3260 }
3261
3262 VkResult radv_BindImageMemory2(VkDevice device,
3263 uint32_t bindInfoCount,
3264 const VkBindImageMemoryInfoKHR *pBindInfos)
3265 {
3266 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3267 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3268 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3269
3270 if (mem) {
3271 image->bo = mem->bo;
3272 image->offset = pBindInfos[i].memoryOffset;
3273 } else {
3274 image->bo = NULL;
3275 image->offset = 0;
3276 }
3277 }
3278 return VK_SUCCESS;
3279 }
3280
3281
3282 VkResult radv_BindImageMemory(
3283 VkDevice device,
3284 VkImage image,
3285 VkDeviceMemory memory,
3286 VkDeviceSize memoryOffset)
3287 {
3288 const VkBindImageMemoryInfoKHR info = {
3289 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3290 .image = image,
3291 .memory = memory,
3292 .memoryOffset = memoryOffset
3293 };
3294
3295 return radv_BindImageMemory2(device, 1, &info);
3296 }
3297
3298
3299 static void
3300 radv_sparse_buffer_bind_memory(struct radv_device *device,
3301 const VkSparseBufferMemoryBindInfo *bind)
3302 {
3303 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3304
3305 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3306 struct radv_device_memory *mem = NULL;
3307
3308 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3309 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3310
3311 device->ws->buffer_virtual_bind(buffer->bo,
3312 bind->pBinds[i].resourceOffset,
3313 bind->pBinds[i].size,
3314 mem ? mem->bo : NULL,
3315 bind->pBinds[i].memoryOffset);
3316 }
3317 }
3318
3319 static void
3320 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3321 const VkSparseImageOpaqueMemoryBindInfo *bind)
3322 {
3323 RADV_FROM_HANDLE(radv_image, image, bind->image);
3324
3325 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3326 struct radv_device_memory *mem = NULL;
3327
3328 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3329 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3330
3331 device->ws->buffer_virtual_bind(image->bo,
3332 bind->pBinds[i].resourceOffset,
3333 bind->pBinds[i].size,
3334 mem ? mem->bo : NULL,
3335 bind->pBinds[i].memoryOffset);
3336 }
3337 }
3338
3339 VkResult radv_QueueBindSparse(
3340 VkQueue _queue,
3341 uint32_t bindInfoCount,
3342 const VkBindSparseInfo* pBindInfo,
3343 VkFence _fence)
3344 {
3345 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3346 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3347 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3348 bool fence_emitted = false;
3349 VkResult result;
3350 int ret;
3351
3352 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3353 struct radv_winsys_sem_info sem_info;
3354 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3355 radv_sparse_buffer_bind_memory(queue->device,
3356 pBindInfo[i].pBufferBinds + j);
3357 }
3358
3359 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3360 radv_sparse_image_opaque_bind_memory(queue->device,
3361 pBindInfo[i].pImageOpaqueBinds + j);
3362 }
3363
3364 VkResult result;
3365 result = radv_alloc_sem_info(queue->device->instance,
3366 &sem_info,
3367 pBindInfo[i].waitSemaphoreCount,
3368 pBindInfo[i].pWaitSemaphores,
3369 pBindInfo[i].signalSemaphoreCount,
3370 pBindInfo[i].pSignalSemaphores,
3371 _fence);
3372 if (result != VK_SUCCESS)
3373 return result;
3374
3375 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3376 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3377 &queue->device->empty_cs[queue->queue_family_index],
3378 1, NULL, NULL,
3379 &sem_info, NULL,
3380 false, base_fence);
3381 if (ret) {
3382 radv_loge("failed to submit CS %d\n", i);
3383 abort();
3384 }
3385
3386 fence_emitted = true;
3387 if (fence)
3388 fence->submitted = true;
3389 }
3390
3391 radv_free_sem_info(&sem_info);
3392
3393 }
3394
3395 if (fence) {
3396 if (!fence_emitted) {
3397 result = radv_signal_fence(queue, fence);
3398 if (result != VK_SUCCESS)
3399 return result;
3400 }
3401 fence->submitted = true;
3402 }
3403
3404 return VK_SUCCESS;
3405 }
3406
3407 VkResult radv_CreateFence(
3408 VkDevice _device,
3409 const VkFenceCreateInfo* pCreateInfo,
3410 const VkAllocationCallbacks* pAllocator,
3411 VkFence* pFence)
3412 {
3413 RADV_FROM_HANDLE(radv_device, device, _device);
3414 const VkExportFenceCreateInfoKHR *export =
3415 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3416 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3417 export ? export->handleTypes : 0;
3418
3419 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3420 sizeof(*fence), 8,
3421 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3422
3423 if (!fence)
3424 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3425
3426 fence->fence_wsi = NULL;
3427 fence->submitted = false;
3428 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3429 fence->temp_syncobj = 0;
3430 if (device->always_use_syncobj || handleTypes) {
3431 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3432 if (ret) {
3433 vk_free2(&device->alloc, pAllocator, fence);
3434 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3435 }
3436 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3437 device->ws->signal_syncobj(device->ws, fence->syncobj);
3438 }
3439 fence->fence = NULL;
3440 } else {
3441 fence->fence = device->ws->create_fence();
3442 if (!fence->fence) {
3443 vk_free2(&device->alloc, pAllocator, fence);
3444 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3445 }
3446 fence->syncobj = 0;
3447 }
3448
3449 *pFence = radv_fence_to_handle(fence);
3450
3451 return VK_SUCCESS;
3452 }
3453
3454 void radv_DestroyFence(
3455 VkDevice _device,
3456 VkFence _fence,
3457 const VkAllocationCallbacks* pAllocator)
3458 {
3459 RADV_FROM_HANDLE(radv_device, device, _device);
3460 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3461
3462 if (!fence)
3463 return;
3464
3465 if (fence->temp_syncobj)
3466 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3467 if (fence->syncobj)
3468 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3469 if (fence->fence)
3470 device->ws->destroy_fence(fence->fence);
3471 if (fence->fence_wsi)
3472 fence->fence_wsi->destroy(fence->fence_wsi);
3473 vk_free2(&device->alloc, pAllocator, fence);
3474 }
3475
3476
3477 static uint64_t radv_get_current_time()
3478 {
3479 struct timespec tv;
3480 clock_gettime(CLOCK_MONOTONIC, &tv);
3481 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3482 }
3483
3484 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3485 {
3486 uint64_t current_time = radv_get_current_time();
3487
3488 timeout = MIN2(UINT64_MAX - current_time, timeout);
3489
3490 return current_time + timeout;
3491 }
3492
3493
3494 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3495 {
3496 for (uint32_t i = 0; i < fenceCount; ++i) {
3497 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3498 if (fence->fence == NULL || fence->syncobj ||
3499 fence->temp_syncobj ||
3500 (!fence->signalled && !fence->submitted))
3501 return false;
3502 }
3503 return true;
3504 }
3505
3506 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3507 {
3508 for (uint32_t i = 0; i < fenceCount; ++i) {
3509 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3510 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3511 return false;
3512 }
3513 return true;
3514 }
3515
3516 VkResult radv_WaitForFences(
3517 VkDevice _device,
3518 uint32_t fenceCount,
3519 const VkFence* pFences,
3520 VkBool32 waitAll,
3521 uint64_t timeout)
3522 {
3523 RADV_FROM_HANDLE(radv_device, device, _device);
3524 timeout = radv_get_absolute_timeout(timeout);
3525
3526 if (device->always_use_syncobj &&
3527 radv_all_fences_syncobj(fenceCount, pFences))
3528 {
3529 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3530 if (!handles)
3531 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3532
3533 for (uint32_t i = 0; i < fenceCount; ++i) {
3534 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3535 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3536 }
3537
3538 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3539
3540 free(handles);
3541 return success ? VK_SUCCESS : VK_TIMEOUT;
3542 }
3543
3544 if (!waitAll && fenceCount > 1) {
3545 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3546 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3547 uint32_t wait_count = 0;
3548 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3549 if (!fences)
3550 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3551
3552 for (uint32_t i = 0; i < fenceCount; ++i) {
3553 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3554
3555 if (fence->signalled) {
3556 free(fences);
3557 return VK_SUCCESS;
3558 }
3559
3560 fences[wait_count++] = fence->fence;
3561 }
3562
3563 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3564 waitAll, timeout - radv_get_current_time());
3565
3566 free(fences);
3567 return success ? VK_SUCCESS : VK_TIMEOUT;
3568 }
3569
3570 while(radv_get_current_time() <= timeout) {
3571 for (uint32_t i = 0; i < fenceCount; ++i) {
3572 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3573 return VK_SUCCESS;
3574 }
3575 }
3576 return VK_TIMEOUT;
3577 }
3578
3579 for (uint32_t i = 0; i < fenceCount; ++i) {
3580 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3581 bool expired = false;
3582
3583 if (fence->temp_syncobj) {
3584 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3585 return VK_TIMEOUT;
3586 continue;
3587 }
3588
3589 if (fence->syncobj) {
3590 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3591 return VK_TIMEOUT;
3592 continue;
3593 }
3594
3595 if (fence->signalled)
3596 continue;
3597
3598 if (fence->fence) {
3599 if (!fence->submitted) {
3600 while(radv_get_current_time() <= timeout &&
3601 !fence->submitted)
3602 /* Do nothing */;
3603
3604 if (!fence->submitted)
3605 return VK_TIMEOUT;
3606
3607 /* Recheck as it may have been set by
3608 * submitting operations. */
3609
3610 if (fence->signalled)
3611 continue;
3612 }
3613
3614 expired = device->ws->fence_wait(device->ws,
3615 fence->fence,
3616 true, timeout);
3617 if (!expired)
3618 return VK_TIMEOUT;
3619 }
3620
3621 if (fence->fence_wsi) {
3622 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3623 if (result != VK_SUCCESS)
3624 return result;
3625 }
3626
3627 fence->signalled = true;
3628 }
3629
3630 return VK_SUCCESS;
3631 }
3632
3633 VkResult radv_ResetFences(VkDevice _device,
3634 uint32_t fenceCount,
3635 const VkFence *pFences)
3636 {
3637 RADV_FROM_HANDLE(radv_device, device, _device);
3638
3639 for (unsigned i = 0; i < fenceCount; ++i) {
3640 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3641 fence->submitted = fence->signalled = false;
3642
3643 /* Per spec, we first restore the permanent payload, and then reset, so
3644 * having a temp syncobj should not skip resetting the permanent syncobj. */
3645 if (fence->temp_syncobj) {
3646 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3647 fence->temp_syncobj = 0;
3648 }
3649
3650 if (fence->syncobj) {
3651 device->ws->reset_syncobj(device->ws, fence->syncobj);
3652 }
3653 }
3654
3655 return VK_SUCCESS;
3656 }
3657
3658 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3659 {
3660 RADV_FROM_HANDLE(radv_device, device, _device);
3661 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3662
3663 if (fence->temp_syncobj) {
3664 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3665 return success ? VK_SUCCESS : VK_NOT_READY;
3666 }
3667
3668 if (fence->syncobj) {
3669 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3670 return success ? VK_SUCCESS : VK_NOT_READY;
3671 }
3672
3673 if (fence->signalled)
3674 return VK_SUCCESS;
3675 if (!fence->submitted)
3676 return VK_NOT_READY;
3677 if (fence->fence) {
3678 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3679 return VK_NOT_READY;
3680 }
3681 if (fence->fence_wsi) {
3682 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3683
3684 if (result != VK_SUCCESS) {
3685 if (result == VK_TIMEOUT)
3686 return VK_NOT_READY;
3687 return result;
3688 }
3689 }
3690 return VK_SUCCESS;
3691 }
3692
3693
3694 // Queue semaphore functions
3695
3696 VkResult radv_CreateSemaphore(
3697 VkDevice _device,
3698 const VkSemaphoreCreateInfo* pCreateInfo,
3699 const VkAllocationCallbacks* pAllocator,
3700 VkSemaphore* pSemaphore)
3701 {
3702 RADV_FROM_HANDLE(radv_device, device, _device);
3703 const VkExportSemaphoreCreateInfoKHR *export =
3704 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3705 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3706 export ? export->handleTypes : 0;
3707
3708 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3709 sizeof(*sem), 8,
3710 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3711 if (!sem)
3712 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3713
3714 sem->temp_syncobj = 0;
3715 /* create a syncobject if we are going to export this semaphore */
3716 if (device->always_use_syncobj || handleTypes) {
3717 assert (device->physical_device->rad_info.has_syncobj);
3718 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3719 if (ret) {
3720 vk_free2(&device->alloc, pAllocator, sem);
3721 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3722 }
3723 sem->sem = NULL;
3724 } else {
3725 sem->sem = device->ws->create_sem(device->ws);
3726 if (!sem->sem) {
3727 vk_free2(&device->alloc, pAllocator, sem);
3728 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3729 }
3730 sem->syncobj = 0;
3731 }
3732
3733 *pSemaphore = radv_semaphore_to_handle(sem);
3734 return VK_SUCCESS;
3735 }
3736
3737 void radv_DestroySemaphore(
3738 VkDevice _device,
3739 VkSemaphore _semaphore,
3740 const VkAllocationCallbacks* pAllocator)
3741 {
3742 RADV_FROM_HANDLE(radv_device, device, _device);
3743 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3744 if (!_semaphore)
3745 return;
3746
3747 if (sem->syncobj)
3748 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3749 else
3750 device->ws->destroy_sem(sem->sem);
3751 vk_free2(&device->alloc, pAllocator, sem);
3752 }
3753
3754 VkResult radv_CreateEvent(
3755 VkDevice _device,
3756 const VkEventCreateInfo* pCreateInfo,
3757 const VkAllocationCallbacks* pAllocator,
3758 VkEvent* pEvent)
3759 {
3760 RADV_FROM_HANDLE(radv_device, device, _device);
3761 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3762 sizeof(*event), 8,
3763 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3764
3765 if (!event)
3766 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3767
3768 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3769 RADEON_DOMAIN_GTT,
3770 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3771 if (!event->bo) {
3772 vk_free2(&device->alloc, pAllocator, event);
3773 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3774 }
3775
3776 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3777
3778 *pEvent = radv_event_to_handle(event);
3779
3780 return VK_SUCCESS;
3781 }
3782
3783 void radv_DestroyEvent(
3784 VkDevice _device,
3785 VkEvent _event,
3786 const VkAllocationCallbacks* pAllocator)
3787 {
3788 RADV_FROM_HANDLE(radv_device, device, _device);
3789 RADV_FROM_HANDLE(radv_event, event, _event);
3790
3791 if (!event)
3792 return;
3793 device->ws->buffer_destroy(event->bo);
3794 vk_free2(&device->alloc, pAllocator, event);
3795 }
3796
3797 VkResult radv_GetEventStatus(
3798 VkDevice _device,
3799 VkEvent _event)
3800 {
3801 RADV_FROM_HANDLE(radv_event, event, _event);
3802
3803 if (*event->map == 1)
3804 return VK_EVENT_SET;
3805 return VK_EVENT_RESET;
3806 }
3807
3808 VkResult radv_SetEvent(
3809 VkDevice _device,
3810 VkEvent _event)
3811 {
3812 RADV_FROM_HANDLE(radv_event, event, _event);
3813 *event->map = 1;
3814
3815 return VK_SUCCESS;
3816 }
3817
3818 VkResult radv_ResetEvent(
3819 VkDevice _device,
3820 VkEvent _event)
3821 {
3822 RADV_FROM_HANDLE(radv_event, event, _event);
3823 *event->map = 0;
3824
3825 return VK_SUCCESS;
3826 }
3827
3828 VkResult radv_CreateBuffer(
3829 VkDevice _device,
3830 const VkBufferCreateInfo* pCreateInfo,
3831 const VkAllocationCallbacks* pAllocator,
3832 VkBuffer* pBuffer)
3833 {
3834 RADV_FROM_HANDLE(radv_device, device, _device);
3835 struct radv_buffer *buffer;
3836
3837 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3838
3839 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3840 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3841 if (buffer == NULL)
3842 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3843
3844 buffer->size = pCreateInfo->size;
3845 buffer->usage = pCreateInfo->usage;
3846 buffer->bo = NULL;
3847 buffer->offset = 0;
3848 buffer->flags = pCreateInfo->flags;
3849
3850 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3851 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3852
3853 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3854 buffer->bo = device->ws->buffer_create(device->ws,
3855 align64(buffer->size, 4096),
3856 4096, 0, RADEON_FLAG_VIRTUAL);
3857 if (!buffer->bo) {
3858 vk_free2(&device->alloc, pAllocator, buffer);
3859 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3860 }
3861 }
3862
3863 *pBuffer = radv_buffer_to_handle(buffer);
3864
3865 return VK_SUCCESS;
3866 }
3867
3868 void radv_DestroyBuffer(
3869 VkDevice _device,
3870 VkBuffer _buffer,
3871 const VkAllocationCallbacks* pAllocator)
3872 {
3873 RADV_FROM_HANDLE(radv_device, device, _device);
3874 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3875
3876 if (!buffer)
3877 return;
3878
3879 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3880 device->ws->buffer_destroy(buffer->bo);
3881
3882 vk_free2(&device->alloc, pAllocator, buffer);
3883 }
3884
3885 static inline unsigned
3886 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3887 {
3888 if (stencil)
3889 return image->surface.u.legacy.stencil_tiling_index[level];
3890 else
3891 return image->surface.u.legacy.tiling_index[level];
3892 }
3893
3894 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3895 {
3896 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3897 }
3898
3899 static uint32_t
3900 radv_init_dcc_control_reg(struct radv_device *device,
3901 struct radv_image_view *iview)
3902 {
3903 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3904 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3905 unsigned max_compressed_block_size;
3906 unsigned independent_64b_blocks;
3907
3908 if (!radv_image_has_dcc(iview->image))
3909 return 0;
3910
3911 if (iview->image->info.samples > 1) {
3912 if (iview->image->surface.bpe == 1)
3913 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3914 else if (iview->image->surface.bpe == 2)
3915 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3916 }
3917
3918 if (!device->physical_device->rad_info.has_dedicated_vram) {
3919 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3920 * dGPU and 64 for APU because all of our APUs to date use
3921 * DIMMs which have a request granularity size of 64B while all
3922 * other chips have a 32B request size.
3923 */
3924 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3925 }
3926
3927 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3928 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3929 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3930 /* If this DCC image is potentially going to be used in texture
3931 * fetches, we need some special settings.
3932 */
3933 independent_64b_blocks = 1;
3934 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3935 } else {
3936 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3937 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3938 * big as possible for better compression state.
3939 */
3940 independent_64b_blocks = 0;
3941 max_compressed_block_size = max_uncompressed_block_size;
3942 }
3943
3944 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3945 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3946 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3947 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3948 }
3949
3950 static void
3951 radv_initialise_color_surface(struct radv_device *device,
3952 struct radv_color_buffer_info *cb,
3953 struct radv_image_view *iview)
3954 {
3955 const struct vk_format_description *desc;
3956 unsigned ntype, format, swap, endian;
3957 unsigned blend_clamp = 0, blend_bypass = 0;
3958 uint64_t va;
3959 const struct radeon_surf *surf = &iview->image->surface;
3960
3961 desc = vk_format_description(iview->vk_format);
3962
3963 memset(cb, 0, sizeof(*cb));
3964
3965 /* Intensity is implemented as Red, so treat it that way. */
3966 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3967
3968 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3969
3970 cb->cb_color_base = va >> 8;
3971
3972 if (device->physical_device->rad_info.chip_class >= GFX9) {
3973 struct gfx9_surf_meta_flags meta;
3974 if (iview->image->dcc_offset)
3975 meta = iview->image->surface.u.gfx9.dcc;
3976 else
3977 meta = iview->image->surface.u.gfx9.cmask;
3978
3979 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3980 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3981 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3982 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3983
3984 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3985 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3986 } else {
3987 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3988 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3989
3990 cb->cb_color_base += level_info->offset >> 8;
3991 if (level_info->mode == RADEON_SURF_MODE_2D)
3992 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3993
3994 pitch_tile_max = level_info->nblk_x / 8 - 1;
3995 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3996 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3997
3998 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3999 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4000 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4001
4002 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4003
4004 if (radv_image_has_fmask(iview->image)) {
4005 if (device->physical_device->rad_info.chip_class >= CIK)
4006 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4007 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4008 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4009 } else {
4010 /* This must be set for fast clear to work without FMASK. */
4011 if (device->physical_device->rad_info.chip_class >= CIK)
4012 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4013 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4014 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4015 }
4016 }
4017
4018 /* CMASK variables */
4019 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4020 va += iview->image->cmask.offset;
4021 cb->cb_color_cmask = va >> 8;
4022
4023 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4024 va += iview->image->dcc_offset;
4025 cb->cb_dcc_base = va >> 8;
4026 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4027
4028 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4029 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4030 S_028C6C_SLICE_MAX(max_slice);
4031
4032 if (iview->image->info.samples > 1) {
4033 unsigned log_samples = util_logbase2(iview->image->info.samples);
4034
4035 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4036 S_028C74_NUM_FRAGMENTS(log_samples);
4037 }
4038
4039 if (radv_image_has_fmask(iview->image)) {
4040 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4041 cb->cb_color_fmask = va >> 8;
4042 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4043 } else {
4044 cb->cb_color_fmask = cb->cb_color_base;
4045 }
4046
4047 ntype = radv_translate_color_numformat(iview->vk_format,
4048 desc,
4049 vk_format_get_first_non_void_channel(iview->vk_format));
4050 format = radv_translate_colorformat(iview->vk_format);
4051 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4052 radv_finishme("Illegal color\n");
4053 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4054 endian = radv_colorformat_endian_swap(format);
4055
4056 /* blend clamp should be set for all NORM/SRGB types */
4057 if (ntype == V_028C70_NUMBER_UNORM ||
4058 ntype == V_028C70_NUMBER_SNORM ||
4059 ntype == V_028C70_NUMBER_SRGB)
4060 blend_clamp = 1;
4061
4062 /* set blend bypass according to docs if SINT/UINT or
4063 8/24 COLOR variants */
4064 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4065 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4066 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4067 blend_clamp = 0;
4068 blend_bypass = 1;
4069 }
4070 #if 0
4071 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4072 (format == V_028C70_COLOR_8 ||
4073 format == V_028C70_COLOR_8_8 ||
4074 format == V_028C70_COLOR_8_8_8_8))
4075 ->color_is_int8 = true;
4076 #endif
4077 cb->cb_color_info = S_028C70_FORMAT(format) |
4078 S_028C70_COMP_SWAP(swap) |
4079 S_028C70_BLEND_CLAMP(blend_clamp) |
4080 S_028C70_BLEND_BYPASS(blend_bypass) |
4081 S_028C70_SIMPLE_FLOAT(1) |
4082 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4083 ntype != V_028C70_NUMBER_SNORM &&
4084 ntype != V_028C70_NUMBER_SRGB &&
4085 format != V_028C70_COLOR_8_24 &&
4086 format != V_028C70_COLOR_24_8) |
4087 S_028C70_NUMBER_TYPE(ntype) |
4088 S_028C70_ENDIAN(endian);
4089 if (radv_image_has_fmask(iview->image)) {
4090 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4091 if (device->physical_device->rad_info.chip_class == SI) {
4092 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4093 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4094 }
4095 }
4096
4097 if (radv_image_has_cmask(iview->image) &&
4098 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4099 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4100
4101 if (radv_dcc_enabled(iview->image, iview->base_mip))
4102 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4103
4104 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4105
4106 /* This must be set for fast clear to work without FMASK. */
4107 if (!radv_image_has_fmask(iview->image) &&
4108 device->physical_device->rad_info.chip_class == SI) {
4109 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4110 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4111 }
4112
4113 if (device->physical_device->rad_info.chip_class >= GFX9) {
4114 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4115 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4116
4117 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4118 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4119 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4120 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4121 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4122 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4123 }
4124 }
4125
4126 static unsigned
4127 radv_calc_decompress_on_z_planes(struct radv_device *device,
4128 struct radv_image_view *iview)
4129 {
4130 unsigned max_zplanes = 0;
4131
4132 assert(radv_image_is_tc_compat_htile(iview->image));
4133
4134 if (device->physical_device->rad_info.chip_class >= GFX9) {
4135 /* Default value for 32-bit depth surfaces. */
4136 max_zplanes = 4;
4137
4138 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4139 iview->image->info.samples > 1)
4140 max_zplanes = 2;
4141
4142 max_zplanes = max_zplanes + 1;
4143 } else {
4144 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4145 /* Do not enable Z plane compression for 16-bit depth
4146 * surfaces because isn't supported on GFX8. Only
4147 * 32-bit depth surfaces are supported by the hardware.
4148 * This allows to maintain shader compatibility and to
4149 * reduce the number of depth decompressions.
4150 */
4151 max_zplanes = 1;
4152 } else {
4153 if (iview->image->info.samples <= 1)
4154 max_zplanes = 5;
4155 else if (iview->image->info.samples <= 4)
4156 max_zplanes = 3;
4157 else
4158 max_zplanes = 2;
4159 }
4160 }
4161
4162 return max_zplanes;
4163 }
4164
4165 static void
4166 radv_initialise_ds_surface(struct radv_device *device,
4167 struct radv_ds_buffer_info *ds,
4168 struct radv_image_view *iview)
4169 {
4170 unsigned level = iview->base_mip;
4171 unsigned format, stencil_format;
4172 uint64_t va, s_offs, z_offs;
4173 bool stencil_only = false;
4174 memset(ds, 0, sizeof(*ds));
4175 switch (iview->image->vk_format) {
4176 case VK_FORMAT_D24_UNORM_S8_UINT:
4177 case VK_FORMAT_X8_D24_UNORM_PACK32:
4178 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4179 ds->offset_scale = 2.0f;
4180 break;
4181 case VK_FORMAT_D16_UNORM:
4182 case VK_FORMAT_D16_UNORM_S8_UINT:
4183 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4184 ds->offset_scale = 4.0f;
4185 break;
4186 case VK_FORMAT_D32_SFLOAT:
4187 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4188 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4189 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4190 ds->offset_scale = 1.0f;
4191 break;
4192 case VK_FORMAT_S8_UINT:
4193 stencil_only = true;
4194 break;
4195 default:
4196 break;
4197 }
4198
4199 format = radv_translate_dbformat(iview->image->vk_format);
4200 stencil_format = iview->image->surface.has_stencil ?
4201 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4202
4203 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4204 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4205 S_028008_SLICE_MAX(max_slice);
4206
4207 ds->db_htile_data_base = 0;
4208 ds->db_htile_surface = 0;
4209
4210 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4211 s_offs = z_offs = va;
4212
4213 if (device->physical_device->rad_info.chip_class >= GFX9) {
4214 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4215 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4216
4217 ds->db_z_info = S_028038_FORMAT(format) |
4218 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4219 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4220 S_028038_MAXMIP(iview->image->info.levels - 1) |
4221 S_028038_ZRANGE_PRECISION(1);
4222 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4223 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4224
4225 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4226 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4227 ds->db_depth_view |= S_028008_MIPID(level);
4228
4229 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4230 S_02801C_Y_MAX(iview->image->info.height - 1);
4231
4232 if (radv_htile_enabled(iview->image, level)) {
4233 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4234
4235 if (radv_image_is_tc_compat_htile(iview->image)) {
4236 unsigned max_zplanes =
4237 radv_calc_decompress_on_z_planes(device, iview);
4238
4239 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4240 S_028038_ITERATE_FLUSH(1);
4241 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4242 }
4243
4244 if (!iview->image->surface.has_stencil)
4245 /* Use all of the htile_buffer for depth if there's no stencil. */
4246 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4247 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4248 iview->image->htile_offset;
4249 ds->db_htile_data_base = va >> 8;
4250 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4251 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4252 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4253 }
4254 } else {
4255 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4256
4257 if (stencil_only)
4258 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4259
4260 z_offs += iview->image->surface.u.legacy.level[level].offset;
4261 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4262
4263 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4264 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4265 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4266
4267 if (iview->image->info.samples > 1)
4268 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4269
4270 if (device->physical_device->rad_info.chip_class >= CIK) {
4271 struct radeon_info *info = &device->physical_device->rad_info;
4272 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4273 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4274 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4275 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4276 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4277 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4278
4279 if (stencil_only)
4280 tile_mode = stencil_tile_mode;
4281
4282 ds->db_depth_info |=
4283 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4284 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4285 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4286 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4287 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4288 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4289 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4290 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4291 } else {
4292 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4293 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4294 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4295 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4296 if (stencil_only)
4297 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4298 }
4299
4300 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4301 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4302 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4303
4304 if (radv_htile_enabled(iview->image, level)) {
4305 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4306
4307 if (!iview->image->surface.has_stencil &&
4308 !radv_image_is_tc_compat_htile(iview->image))
4309 /* Use all of the htile_buffer for depth if there's no stencil. */
4310 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4311
4312 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4313 iview->image->htile_offset;
4314 ds->db_htile_data_base = va >> 8;
4315 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4316
4317 if (radv_image_is_tc_compat_htile(iview->image)) {
4318 unsigned max_zplanes =
4319 radv_calc_decompress_on_z_planes(device, iview);
4320
4321 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4322 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4323 }
4324 }
4325 }
4326
4327 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4328 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4329 }
4330
4331 VkResult radv_CreateFramebuffer(
4332 VkDevice _device,
4333 const VkFramebufferCreateInfo* pCreateInfo,
4334 const VkAllocationCallbacks* pAllocator,
4335 VkFramebuffer* pFramebuffer)
4336 {
4337 RADV_FROM_HANDLE(radv_device, device, _device);
4338 struct radv_framebuffer *framebuffer;
4339
4340 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4341
4342 size_t size = sizeof(*framebuffer) +
4343 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4344 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4345 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4346 if (framebuffer == NULL)
4347 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4348
4349 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4350 framebuffer->width = pCreateInfo->width;
4351 framebuffer->height = pCreateInfo->height;
4352 framebuffer->layers = pCreateInfo->layers;
4353 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4354 VkImageView _iview = pCreateInfo->pAttachments[i];
4355 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4356 framebuffer->attachments[i].attachment = iview;
4357 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4358 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4359 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4360 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4361 }
4362 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4363 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4364 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4365 }
4366
4367 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4368 return VK_SUCCESS;
4369 }
4370
4371 void radv_DestroyFramebuffer(
4372 VkDevice _device,
4373 VkFramebuffer _fb,
4374 const VkAllocationCallbacks* pAllocator)
4375 {
4376 RADV_FROM_HANDLE(radv_device, device, _device);
4377 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4378
4379 if (!fb)
4380 return;
4381 vk_free2(&device->alloc, pAllocator, fb);
4382 }
4383
4384 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4385 {
4386 switch (address_mode) {
4387 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4388 return V_008F30_SQ_TEX_WRAP;
4389 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4390 return V_008F30_SQ_TEX_MIRROR;
4391 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4392 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4393 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4394 return V_008F30_SQ_TEX_CLAMP_BORDER;
4395 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4396 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4397 default:
4398 unreachable("illegal tex wrap mode");
4399 break;
4400 }
4401 }
4402
4403 static unsigned
4404 radv_tex_compare(VkCompareOp op)
4405 {
4406 switch (op) {
4407 case VK_COMPARE_OP_NEVER:
4408 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4409 case VK_COMPARE_OP_LESS:
4410 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4411 case VK_COMPARE_OP_EQUAL:
4412 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4413 case VK_COMPARE_OP_LESS_OR_EQUAL:
4414 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4415 case VK_COMPARE_OP_GREATER:
4416 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4417 case VK_COMPARE_OP_NOT_EQUAL:
4418 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4419 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4420 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4421 case VK_COMPARE_OP_ALWAYS:
4422 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4423 default:
4424 unreachable("illegal compare mode");
4425 break;
4426 }
4427 }
4428
4429 static unsigned
4430 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4431 {
4432 switch (filter) {
4433 case VK_FILTER_NEAREST:
4434 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4435 V_008F38_SQ_TEX_XY_FILTER_POINT);
4436 case VK_FILTER_LINEAR:
4437 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4438 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4439 case VK_FILTER_CUBIC_IMG:
4440 default:
4441 fprintf(stderr, "illegal texture filter");
4442 return 0;
4443 }
4444 }
4445
4446 static unsigned
4447 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4448 {
4449 switch (mode) {
4450 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4451 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4452 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4453 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4454 default:
4455 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4456 }
4457 }
4458
4459 static unsigned
4460 radv_tex_bordercolor(VkBorderColor bcolor)
4461 {
4462 switch (bcolor) {
4463 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4464 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4465 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4466 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4467 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4468 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4469 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4470 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4471 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4472 default:
4473 break;
4474 }
4475 return 0;
4476 }
4477
4478 static unsigned
4479 radv_tex_aniso_filter(unsigned filter)
4480 {
4481 if (filter < 2)
4482 return 0;
4483 if (filter < 4)
4484 return 1;
4485 if (filter < 8)
4486 return 2;
4487 if (filter < 16)
4488 return 3;
4489 return 4;
4490 }
4491
4492 static unsigned
4493 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4494 {
4495 switch (mode) {
4496 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4497 return SQ_IMG_FILTER_MODE_BLEND;
4498 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4499 return SQ_IMG_FILTER_MODE_MIN;
4500 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4501 return SQ_IMG_FILTER_MODE_MAX;
4502 default:
4503 break;
4504 }
4505 return 0;
4506 }
4507
4508 static uint32_t
4509 radv_get_max_anisotropy(struct radv_device *device,
4510 const VkSamplerCreateInfo *pCreateInfo)
4511 {
4512 if (device->force_aniso >= 0)
4513 return device->force_aniso;
4514
4515 if (pCreateInfo->anisotropyEnable &&
4516 pCreateInfo->maxAnisotropy > 1.0f)
4517 return (uint32_t)pCreateInfo->maxAnisotropy;
4518
4519 return 0;
4520 }
4521
4522 static void
4523 radv_init_sampler(struct radv_device *device,
4524 struct radv_sampler *sampler,
4525 const VkSamplerCreateInfo *pCreateInfo)
4526 {
4527 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4528 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4529 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4530 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4531
4532 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4533 vk_find_struct_const(pCreateInfo->pNext,
4534 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4535 if (sampler_reduction)
4536 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4537
4538 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4539 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4540 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4541 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4542 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4543 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4544 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4545 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4546 S_008F30_DISABLE_CUBE_WRAP(0) |
4547 S_008F30_COMPAT_MODE(is_vi) |
4548 S_008F30_FILTER_MODE(filter_mode));
4549 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4550 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4551 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4552 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4553 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4554 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4555 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4556 S_008F38_MIP_POINT_PRECLAMP(0) |
4557 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4558 S_008F38_FILTER_PREC_FIX(1) |
4559 S_008F38_ANISO_OVERRIDE(is_vi));
4560 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4561 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4562 }
4563
4564 VkResult radv_CreateSampler(
4565 VkDevice _device,
4566 const VkSamplerCreateInfo* pCreateInfo,
4567 const VkAllocationCallbacks* pAllocator,
4568 VkSampler* pSampler)
4569 {
4570 RADV_FROM_HANDLE(radv_device, device, _device);
4571 struct radv_sampler *sampler;
4572
4573 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4574
4575 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4576 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4577 if (!sampler)
4578 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4579
4580 radv_init_sampler(device, sampler, pCreateInfo);
4581 *pSampler = radv_sampler_to_handle(sampler);
4582
4583 return VK_SUCCESS;
4584 }
4585
4586 void radv_DestroySampler(
4587 VkDevice _device,
4588 VkSampler _sampler,
4589 const VkAllocationCallbacks* pAllocator)
4590 {
4591 RADV_FROM_HANDLE(radv_device, device, _device);
4592 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4593
4594 if (!sampler)
4595 return;
4596 vk_free2(&device->alloc, pAllocator, sampler);
4597 }
4598
4599 /* vk_icd.h does not declare this function, so we declare it here to
4600 * suppress Wmissing-prototypes.
4601 */
4602 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4603 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4604
4605 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4606 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4607 {
4608 /* For the full details on loader interface versioning, see
4609 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4610 * What follows is a condensed summary, to help you navigate the large and
4611 * confusing official doc.
4612 *
4613 * - Loader interface v0 is incompatible with later versions. We don't
4614 * support it.
4615 *
4616 * - In loader interface v1:
4617 * - The first ICD entrypoint called by the loader is
4618 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4619 * entrypoint.
4620 * - The ICD must statically expose no other Vulkan symbol unless it is
4621 * linked with -Bsymbolic.
4622 * - Each dispatchable Vulkan handle created by the ICD must be
4623 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4624 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4625 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4626 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4627 * such loader-managed surfaces.
4628 *
4629 * - Loader interface v2 differs from v1 in:
4630 * - The first ICD entrypoint called by the loader is
4631 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4632 * statically expose this entrypoint.
4633 *
4634 * - Loader interface v3 differs from v2 in:
4635 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4636 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4637 * because the loader no longer does so.
4638 */
4639 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4640 return VK_SUCCESS;
4641 }
4642
4643 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4644 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4645 int *pFD)
4646 {
4647 RADV_FROM_HANDLE(radv_device, device, _device);
4648 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4649
4650 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4651
4652 /* At the moment, we support only the below handle types. */
4653 assert(pGetFdInfo->handleType ==
4654 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4655 pGetFdInfo->handleType ==
4656 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4657
4658 bool ret = radv_get_memory_fd(device, memory, pFD);
4659 if (ret == false)
4660 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4661 return VK_SUCCESS;
4662 }
4663
4664 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4665 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4666 int fd,
4667 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4668 {
4669 RADV_FROM_HANDLE(radv_device, device, _device);
4670
4671 switch (handleType) {
4672 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4673 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4674 return VK_SUCCESS;
4675
4676 default:
4677 /* The valid usage section for this function says:
4678 *
4679 * "handleType must not be one of the handle types defined as
4680 * opaque."
4681 *
4682 * So opaque handle types fall into the default "unsupported" case.
4683 */
4684 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4685 }
4686 }
4687
4688 static VkResult radv_import_opaque_fd(struct radv_device *device,
4689 int fd,
4690 uint32_t *syncobj)
4691 {
4692 uint32_t syncobj_handle = 0;
4693 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4694 if (ret != 0)
4695 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4696
4697 if (*syncobj)
4698 device->ws->destroy_syncobj(device->ws, *syncobj);
4699
4700 *syncobj = syncobj_handle;
4701 close(fd);
4702
4703 return VK_SUCCESS;
4704 }
4705
4706 static VkResult radv_import_sync_fd(struct radv_device *device,
4707 int fd,
4708 uint32_t *syncobj)
4709 {
4710 /* If we create a syncobj we do it locally so that if we have an error, we don't
4711 * leave a syncobj in an undetermined state in the fence. */
4712 uint32_t syncobj_handle = *syncobj;
4713 if (!syncobj_handle) {
4714 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4715 if (ret) {
4716 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4717 }
4718 }
4719
4720 if (fd == -1) {
4721 device->ws->signal_syncobj(device->ws, syncobj_handle);
4722 } else {
4723 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4724 if (ret != 0)
4725 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4726 }
4727
4728 *syncobj = syncobj_handle;
4729 if (fd != -1)
4730 close(fd);
4731
4732 return VK_SUCCESS;
4733 }
4734
4735 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4736 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4737 {
4738 RADV_FROM_HANDLE(radv_device, device, _device);
4739 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4740 uint32_t *syncobj_dst = NULL;
4741
4742 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4743 syncobj_dst = &sem->temp_syncobj;
4744 } else {
4745 syncobj_dst = &sem->syncobj;
4746 }
4747
4748 switch(pImportSemaphoreFdInfo->handleType) {
4749 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4750 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4751 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4752 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4753 default:
4754 unreachable("Unhandled semaphore handle type");
4755 }
4756 }
4757
4758 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4759 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4760 int *pFd)
4761 {
4762 RADV_FROM_HANDLE(radv_device, device, _device);
4763 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4764 int ret;
4765 uint32_t syncobj_handle;
4766
4767 if (sem->temp_syncobj)
4768 syncobj_handle = sem->temp_syncobj;
4769 else
4770 syncobj_handle = sem->syncobj;
4771
4772 switch(pGetFdInfo->handleType) {
4773 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4774 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4775 break;
4776 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4777 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4778 if (!ret) {
4779 if (sem->temp_syncobj) {
4780 close (sem->temp_syncobj);
4781 sem->temp_syncobj = 0;
4782 } else {
4783 device->ws->reset_syncobj(device->ws, syncobj_handle);
4784 }
4785 }
4786 break;
4787 default:
4788 unreachable("Unhandled semaphore handle type");
4789 }
4790
4791 if (ret)
4792 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4793 return VK_SUCCESS;
4794 }
4795
4796 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4797 VkPhysicalDevice physicalDevice,
4798 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4799 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4800 {
4801 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4802
4803 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4804 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4805 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4806 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4807 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4808 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4809 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4810 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4811 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4812 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4813 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4814 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4815 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4816 } else {
4817 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4818 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4819 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4820 }
4821 }
4822
4823 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4824 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4825 {
4826 RADV_FROM_HANDLE(radv_device, device, _device);
4827 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4828 uint32_t *syncobj_dst = NULL;
4829
4830
4831 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4832 syncobj_dst = &fence->temp_syncobj;
4833 } else {
4834 syncobj_dst = &fence->syncobj;
4835 }
4836
4837 switch(pImportFenceFdInfo->handleType) {
4838 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4839 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4840 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4841 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4842 default:
4843 unreachable("Unhandled fence handle type");
4844 }
4845 }
4846
4847 VkResult radv_GetFenceFdKHR(VkDevice _device,
4848 const VkFenceGetFdInfoKHR *pGetFdInfo,
4849 int *pFd)
4850 {
4851 RADV_FROM_HANDLE(radv_device, device, _device);
4852 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4853 int ret;
4854 uint32_t syncobj_handle;
4855
4856 if (fence->temp_syncobj)
4857 syncobj_handle = fence->temp_syncobj;
4858 else
4859 syncobj_handle = fence->syncobj;
4860
4861 switch(pGetFdInfo->handleType) {
4862 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4863 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4864 break;
4865 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4866 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4867 if (!ret) {
4868 if (fence->temp_syncobj) {
4869 close (fence->temp_syncobj);
4870 fence->temp_syncobj = 0;
4871 } else {
4872 device->ws->reset_syncobj(device->ws, syncobj_handle);
4873 }
4874 }
4875 break;
4876 default:
4877 unreachable("Unhandled fence handle type");
4878 }
4879
4880 if (ret)
4881 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4882 return VK_SUCCESS;
4883 }
4884
4885 void radv_GetPhysicalDeviceExternalFenceProperties(
4886 VkPhysicalDevice physicalDevice,
4887 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4888 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4889 {
4890 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4891
4892 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4893 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4894 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4895 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4896 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4897 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4898 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4899 } else {
4900 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4901 pExternalFenceProperties->compatibleHandleTypes = 0;
4902 pExternalFenceProperties->externalFenceFeatures = 0;
4903 }
4904 }
4905
4906 VkResult
4907 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4908 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4909 const VkAllocationCallbacks* pAllocator,
4910 VkDebugReportCallbackEXT* pCallback)
4911 {
4912 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4913 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4914 pCreateInfo, pAllocator, &instance->alloc,
4915 pCallback);
4916 }
4917
4918 void
4919 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4920 VkDebugReportCallbackEXT _callback,
4921 const VkAllocationCallbacks* pAllocator)
4922 {
4923 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4924 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4925 _callback, pAllocator, &instance->alloc);
4926 }
4927
4928 void
4929 radv_DebugReportMessageEXT(VkInstance _instance,
4930 VkDebugReportFlagsEXT flags,
4931 VkDebugReportObjectTypeEXT objectType,
4932 uint64_t object,
4933 size_t location,
4934 int32_t messageCode,
4935 const char* pLayerPrefix,
4936 const char* pMessage)
4937 {
4938 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4939 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4940 object, location, messageCode, pLayerPrefix, pMessage);
4941 }
4942
4943 void
4944 radv_GetDeviceGroupPeerMemoryFeatures(
4945 VkDevice device,
4946 uint32_t heapIndex,
4947 uint32_t localDeviceIndex,
4948 uint32_t remoteDeviceIndex,
4949 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4950 {
4951 assert(localDeviceIndex == remoteDeviceIndex);
4952
4953 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4954 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4955 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4956 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4957 }