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radv: Add LLVM version to the device name string
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 radv_physical_device_init_mem_types(device);
267
268 result = radv_init_wsi(device);
269 if (result != VK_SUCCESS) {
270 device->ws->destroy(device->ws);
271 goto fail;
272 }
273
274 return VK_SUCCESS;
275
276 fail:
277 close(fd);
278 return result;
279 }
280
281 static void
282 radv_physical_device_finish(struct radv_physical_device *device)
283 {
284 radv_finish_wsi(device);
285 device->ws->destroy(device->ws);
286 disk_cache_destroy(device->disk_cache);
287 close(device->local_fd);
288 }
289
290 static void *
291 default_alloc_func(void *pUserData, size_t size, size_t align,
292 VkSystemAllocationScope allocationScope)
293 {
294 return malloc(size);
295 }
296
297 static void *
298 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
299 size_t align, VkSystemAllocationScope allocationScope)
300 {
301 return realloc(pOriginal, size);
302 }
303
304 static void
305 default_free_func(void *pUserData, void *pMemory)
306 {
307 free(pMemory);
308 }
309
310 static const VkAllocationCallbacks default_alloc = {
311 .pUserData = NULL,
312 .pfnAllocation = default_alloc_func,
313 .pfnReallocation = default_realloc_func,
314 .pfnFree = default_free_func,
315 };
316
317 static const struct debug_control radv_debug_options[] = {
318 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
319 {"nodcc", RADV_DEBUG_NO_DCC},
320 {"shaders", RADV_DEBUG_DUMP_SHADERS},
321 {"nocache", RADV_DEBUG_NO_CACHE},
322 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
323 {"nohiz", RADV_DEBUG_NO_HIZ},
324 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
325 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
326 {"allbos", RADV_DEBUG_ALL_BOS},
327 {"noibs", RADV_DEBUG_NO_IBS},
328 {"spirv", RADV_DEBUG_DUMP_SPIRV},
329 {"vmfaults", RADV_DEBUG_VM_FAULTS},
330 {"zerovram", RADV_DEBUG_ZERO_VRAM},
331 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
332 {"nosisched", RADV_DEBUG_NO_SISCHED},
333 {NULL, 0}
334 };
335
336 const char *
337 radv_get_debug_option_name(int id)
338 {
339 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
340 return radv_debug_options[id].string;
341 }
342
343 static const struct debug_control radv_perftest_options[] = {
344 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
345 {"sisched", RADV_PERFTEST_SISCHED},
346 {NULL, 0}
347 };
348
349 const char *
350 radv_get_perftest_option_name(int id)
351 {
352 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
353 return radv_perftest_options[id].string;
354 }
355
356 static void
357 radv_handle_per_app_options(struct radv_instance *instance,
358 const VkApplicationInfo *info)
359 {
360 const char *name = info ? info->pApplicationName : NULL;
361
362 if (!name)
363 return;
364
365 if (!strcmp(name, "Talos - Linux - 32bit") ||
366 !strcmp(name, "Talos - Linux - 64bit")) {
367 /* Force enable LLVM sisched for Talos because it looks safe
368 * and it gives few more FPS.
369 */
370 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
371 }
372 }
373
374 VkResult radv_CreateInstance(
375 const VkInstanceCreateInfo* pCreateInfo,
376 const VkAllocationCallbacks* pAllocator,
377 VkInstance* pInstance)
378 {
379 struct radv_instance *instance;
380
381 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
382
383 uint32_t client_version;
384 if (pCreateInfo->pApplicationInfo &&
385 pCreateInfo->pApplicationInfo->apiVersion != 0) {
386 client_version = pCreateInfo->pApplicationInfo->apiVersion;
387 } else {
388 client_version = VK_MAKE_VERSION(1, 0, 0);
389 }
390
391 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
392 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
393 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
394 "Client requested version %d.%d.%d",
395 VK_VERSION_MAJOR(client_version),
396 VK_VERSION_MINOR(client_version),
397 VK_VERSION_PATCH(client_version));
398 }
399
400 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
401 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
402 if (!radv_instance_extension_supported(ext_name))
403 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
404 }
405
406 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
407 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
408 if (!instance)
409 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
410
411 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
412
413 if (pAllocator)
414 instance->alloc = *pAllocator;
415 else
416 instance->alloc = default_alloc;
417
418 instance->apiVersion = client_version;
419 instance->physicalDeviceCount = -1;
420
421 _mesa_locale_init();
422
423 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
424
425 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
426 radv_debug_options);
427
428 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
429 radv_perftest_options);
430
431 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
432
433 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
434 /* Disable sisched when the user requests it, this is mostly
435 * useful when the driver force-enable sisched for the given
436 * application.
437 */
438 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
439 }
440
441 *pInstance = radv_instance_to_handle(instance);
442
443 return VK_SUCCESS;
444 }
445
446 void radv_DestroyInstance(
447 VkInstance _instance,
448 const VkAllocationCallbacks* pAllocator)
449 {
450 RADV_FROM_HANDLE(radv_instance, instance, _instance);
451
452 if (!instance)
453 return;
454
455 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
456 radv_physical_device_finish(instance->physicalDevices + i);
457 }
458
459 VG(VALGRIND_DESTROY_MEMPOOL(instance));
460
461 _mesa_locale_fini();
462
463 vk_free(&instance->alloc, instance);
464 }
465
466 static VkResult
467 radv_enumerate_devices(struct radv_instance *instance)
468 {
469 /* TODO: Check for more devices ? */
470 drmDevicePtr devices[8];
471 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
472 int max_devices;
473
474 instance->physicalDeviceCount = 0;
475
476 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
477 if (max_devices < 1)
478 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
479
480 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
481 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
482 devices[i]->bustype == DRM_BUS_PCI &&
483 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
484
485 result = radv_physical_device_init(instance->physicalDevices +
486 instance->physicalDeviceCount,
487 instance,
488 devices[i]);
489 if (result == VK_SUCCESS)
490 ++instance->physicalDeviceCount;
491 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
492 break;
493 }
494 }
495 drmFreeDevices(devices, max_devices);
496
497 return result;
498 }
499
500 VkResult radv_EnumeratePhysicalDevices(
501 VkInstance _instance,
502 uint32_t* pPhysicalDeviceCount,
503 VkPhysicalDevice* pPhysicalDevices)
504 {
505 RADV_FROM_HANDLE(radv_instance, instance, _instance);
506 VkResult result;
507
508 if (instance->physicalDeviceCount < 0) {
509 result = radv_enumerate_devices(instance);
510 if (result != VK_SUCCESS &&
511 result != VK_ERROR_INCOMPATIBLE_DRIVER)
512 return result;
513 }
514
515 if (!pPhysicalDevices) {
516 *pPhysicalDeviceCount = instance->physicalDeviceCount;
517 } else {
518 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
519 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
520 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
521 }
522
523 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
524 : VK_SUCCESS;
525 }
526
527 void radv_GetPhysicalDeviceFeatures(
528 VkPhysicalDevice physicalDevice,
529 VkPhysicalDeviceFeatures* pFeatures)
530 {
531 memset(pFeatures, 0, sizeof(*pFeatures));
532
533 *pFeatures = (VkPhysicalDeviceFeatures) {
534 .robustBufferAccess = true,
535 .fullDrawIndexUint32 = true,
536 .imageCubeArray = true,
537 .independentBlend = true,
538 .geometryShader = true,
539 .tessellationShader = true,
540 .sampleRateShading = true,
541 .dualSrcBlend = true,
542 .logicOp = true,
543 .multiDrawIndirect = true,
544 .drawIndirectFirstInstance = true,
545 .depthClamp = true,
546 .depthBiasClamp = true,
547 .fillModeNonSolid = true,
548 .depthBounds = true,
549 .wideLines = true,
550 .largePoints = true,
551 .alphaToOne = true,
552 .multiViewport = true,
553 .samplerAnisotropy = true,
554 .textureCompressionETC2 = false,
555 .textureCompressionASTC_LDR = false,
556 .textureCompressionBC = true,
557 .occlusionQueryPrecise = true,
558 .pipelineStatisticsQuery = true,
559 .vertexPipelineStoresAndAtomics = true,
560 .fragmentStoresAndAtomics = true,
561 .shaderTessellationAndGeometryPointSize = true,
562 .shaderImageGatherExtended = true,
563 .shaderStorageImageExtendedFormats = true,
564 .shaderStorageImageMultisample = false,
565 .shaderUniformBufferArrayDynamicIndexing = true,
566 .shaderSampledImageArrayDynamicIndexing = true,
567 .shaderStorageBufferArrayDynamicIndexing = true,
568 .shaderStorageImageArrayDynamicIndexing = true,
569 .shaderStorageImageReadWithoutFormat = true,
570 .shaderStorageImageWriteWithoutFormat = true,
571 .shaderClipDistance = true,
572 .shaderCullDistance = true,
573 .shaderFloat64 = true,
574 .shaderInt64 = true,
575 .shaderInt16 = false,
576 .sparseBinding = true,
577 .variableMultisampleRate = true,
578 .inheritedQueries = true,
579 };
580 }
581
582 void radv_GetPhysicalDeviceFeatures2KHR(
583 VkPhysicalDevice physicalDevice,
584 VkPhysicalDeviceFeatures2KHR *pFeatures)
585 {
586 vk_foreach_struct(ext, pFeatures->pNext) {
587 switch (ext->sType) {
588 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
589 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
590 features->variablePointersStorageBuffer = true;
591 features->variablePointers = false;
592 break;
593 }
594 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
595 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
596 features->multiview = true;
597 features->multiviewGeometryShader = true;
598 features->multiviewTessellationShader = true;
599 break;
600 }
601 default:
602 break;
603 }
604 }
605 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
606 }
607
608 void radv_GetPhysicalDeviceProperties(
609 VkPhysicalDevice physicalDevice,
610 VkPhysicalDeviceProperties* pProperties)
611 {
612 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
613 VkSampleCountFlags sample_counts = 0xf;
614
615 /* make sure that the entire descriptor set is addressable with a signed
616 * 32-bit int. So the sum of all limits scaled by descriptor size has to
617 * be at most 2 GiB. the combined image & samples object count as one of
618 * both. This limit is for the pipeline layout, not for the set layout, but
619 * there is no set limit, so we just set a pipeline limit. I don't think
620 * any app is going to hit this soon. */
621 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
622 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
623 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
624 32 /* sampler, largest when combined with image */ +
625 64 /* sampled image */ +
626 64 /* storage image */);
627
628 VkPhysicalDeviceLimits limits = {
629 .maxImageDimension1D = (1 << 14),
630 .maxImageDimension2D = (1 << 14),
631 .maxImageDimension3D = (1 << 11),
632 .maxImageDimensionCube = (1 << 14),
633 .maxImageArrayLayers = (1 << 11),
634 .maxTexelBufferElements = 128 * 1024 * 1024,
635 .maxUniformBufferRange = UINT32_MAX,
636 .maxStorageBufferRange = UINT32_MAX,
637 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
638 .maxMemoryAllocationCount = UINT32_MAX,
639 .maxSamplerAllocationCount = 64 * 1024,
640 .bufferImageGranularity = 64, /* A cache line */
641 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
642 .maxBoundDescriptorSets = MAX_SETS,
643 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
644 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
645 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
646 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
647 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
648 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
649 .maxPerStageResources = max_descriptor_set_size,
650 .maxDescriptorSetSamplers = max_descriptor_set_size,
651 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
652 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
653 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
654 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
655 .maxDescriptorSetSampledImages = max_descriptor_set_size,
656 .maxDescriptorSetStorageImages = max_descriptor_set_size,
657 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
658 .maxVertexInputAttributes = 32,
659 .maxVertexInputBindings = 32,
660 .maxVertexInputAttributeOffset = 2047,
661 .maxVertexInputBindingStride = 2048,
662 .maxVertexOutputComponents = 128,
663 .maxTessellationGenerationLevel = 64,
664 .maxTessellationPatchSize = 32,
665 .maxTessellationControlPerVertexInputComponents = 128,
666 .maxTessellationControlPerVertexOutputComponents = 128,
667 .maxTessellationControlPerPatchOutputComponents = 120,
668 .maxTessellationControlTotalOutputComponents = 4096,
669 .maxTessellationEvaluationInputComponents = 128,
670 .maxTessellationEvaluationOutputComponents = 128,
671 .maxGeometryShaderInvocations = 127,
672 .maxGeometryInputComponents = 64,
673 .maxGeometryOutputComponents = 128,
674 .maxGeometryOutputVertices = 256,
675 .maxGeometryTotalOutputComponents = 1024,
676 .maxFragmentInputComponents = 128,
677 .maxFragmentOutputAttachments = 8,
678 .maxFragmentDualSrcAttachments = 1,
679 .maxFragmentCombinedOutputResources = 8,
680 .maxComputeSharedMemorySize = 32768,
681 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
682 .maxComputeWorkGroupInvocations = 2048,
683 .maxComputeWorkGroupSize = {
684 2048,
685 2048,
686 2048
687 },
688 .subPixelPrecisionBits = 4 /* FIXME */,
689 .subTexelPrecisionBits = 4 /* FIXME */,
690 .mipmapPrecisionBits = 4 /* FIXME */,
691 .maxDrawIndexedIndexValue = UINT32_MAX,
692 .maxDrawIndirectCount = UINT32_MAX,
693 .maxSamplerLodBias = 16,
694 .maxSamplerAnisotropy = 16,
695 .maxViewports = MAX_VIEWPORTS,
696 .maxViewportDimensions = { (1 << 14), (1 << 14) },
697 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
698 .viewportSubPixelBits = 13, /* We take a float? */
699 .minMemoryMapAlignment = 4096, /* A page */
700 .minTexelBufferOffsetAlignment = 1,
701 .minUniformBufferOffsetAlignment = 4,
702 .minStorageBufferOffsetAlignment = 4,
703 .minTexelOffset = -32,
704 .maxTexelOffset = 31,
705 .minTexelGatherOffset = -32,
706 .maxTexelGatherOffset = 31,
707 .minInterpolationOffset = -2,
708 .maxInterpolationOffset = 2,
709 .subPixelInterpolationOffsetBits = 8,
710 .maxFramebufferWidth = (1 << 14),
711 .maxFramebufferHeight = (1 << 14),
712 .maxFramebufferLayers = (1 << 10),
713 .framebufferColorSampleCounts = sample_counts,
714 .framebufferDepthSampleCounts = sample_counts,
715 .framebufferStencilSampleCounts = sample_counts,
716 .framebufferNoAttachmentsSampleCounts = sample_counts,
717 .maxColorAttachments = MAX_RTS,
718 .sampledImageColorSampleCounts = sample_counts,
719 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
720 .sampledImageDepthSampleCounts = sample_counts,
721 .sampledImageStencilSampleCounts = sample_counts,
722 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
723 .maxSampleMaskWords = 1,
724 .timestampComputeAndGraphics = true,
725 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
726 .maxClipDistances = 8,
727 .maxCullDistances = 8,
728 .maxCombinedClipAndCullDistances = 8,
729 .discreteQueuePriorities = 1,
730 .pointSizeRange = { 0.125, 255.875 },
731 .lineWidthRange = { 0.0, 7.9921875 },
732 .pointSizeGranularity = (1.0 / 8.0),
733 .lineWidthGranularity = (1.0 / 128.0),
734 .strictLines = false, /* FINISHME */
735 .standardSampleLocations = true,
736 .optimalBufferCopyOffsetAlignment = 128,
737 .optimalBufferCopyRowPitchAlignment = 128,
738 .nonCoherentAtomSize = 64,
739 };
740
741 *pProperties = (VkPhysicalDeviceProperties) {
742 .apiVersion = radv_physical_device_api_version(pdevice),
743 .driverVersion = vk_get_driver_version(),
744 .vendorID = ATI_VENDOR_ID,
745 .deviceID = pdevice->rad_info.pci_id,
746 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
747 .limits = limits,
748 .sparseProperties = {0},
749 };
750
751 strcpy(pProperties->deviceName, pdevice->name);
752 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
753 }
754
755 void radv_GetPhysicalDeviceProperties2KHR(
756 VkPhysicalDevice physicalDevice,
757 VkPhysicalDeviceProperties2KHR *pProperties)
758 {
759 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
760 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
761
762 vk_foreach_struct(ext, pProperties->pNext) {
763 switch (ext->sType) {
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
765 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
766 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
767 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
771 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
772 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
773 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
774 properties->deviceLUIDValid = false;
775 break;
776 }
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
778 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
779 properties->maxMultiviewViewCount = MAX_VIEWS;
780 properties->maxMultiviewInstanceIndex = INT_MAX;
781 break;
782 }
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
784 VkPhysicalDevicePointClippingPropertiesKHR *properties =
785 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
786 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
787 break;
788 }
789 default:
790 break;
791 }
792 }
793 }
794
795 static void radv_get_physical_device_queue_family_properties(
796 struct radv_physical_device* pdevice,
797 uint32_t* pCount,
798 VkQueueFamilyProperties** pQueueFamilyProperties)
799 {
800 int num_queue_families = 1;
801 int idx;
802 if (pdevice->rad_info.num_compute_rings > 0 &&
803 pdevice->rad_info.chip_class >= CIK &&
804 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
805 num_queue_families++;
806
807 if (pQueueFamilyProperties == NULL) {
808 *pCount = num_queue_families;
809 return;
810 }
811
812 if (!*pCount)
813 return;
814
815 idx = 0;
816 if (*pCount >= 1) {
817 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
818 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
819 VK_QUEUE_COMPUTE_BIT |
820 VK_QUEUE_TRANSFER_BIT |
821 VK_QUEUE_SPARSE_BINDING_BIT,
822 .queueCount = 1,
823 .timestampValidBits = 64,
824 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
825 };
826 idx++;
827 }
828
829 if (pdevice->rad_info.num_compute_rings > 0 &&
830 pdevice->rad_info.chip_class >= CIK &&
831 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
832 if (*pCount > idx) {
833 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
834 .queueFlags = VK_QUEUE_COMPUTE_BIT |
835 VK_QUEUE_TRANSFER_BIT |
836 VK_QUEUE_SPARSE_BINDING_BIT,
837 .queueCount = pdevice->rad_info.num_compute_rings,
838 .timestampValidBits = 64,
839 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
840 };
841 idx++;
842 }
843 }
844 *pCount = idx;
845 }
846
847 void radv_GetPhysicalDeviceQueueFamilyProperties(
848 VkPhysicalDevice physicalDevice,
849 uint32_t* pCount,
850 VkQueueFamilyProperties* pQueueFamilyProperties)
851 {
852 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
853 if (!pQueueFamilyProperties) {
854 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
855 return;
856 }
857 VkQueueFamilyProperties *properties[] = {
858 pQueueFamilyProperties + 0,
859 pQueueFamilyProperties + 1,
860 pQueueFamilyProperties + 2,
861 };
862 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
863 assert(*pCount <= 3);
864 }
865
866 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
867 VkPhysicalDevice physicalDevice,
868 uint32_t* pCount,
869 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
870 {
871 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
872 if (!pQueueFamilyProperties) {
873 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
874 return;
875 }
876 VkQueueFamilyProperties *properties[] = {
877 &pQueueFamilyProperties[0].queueFamilyProperties,
878 &pQueueFamilyProperties[1].queueFamilyProperties,
879 &pQueueFamilyProperties[2].queueFamilyProperties,
880 };
881 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
882 assert(*pCount <= 3);
883 }
884
885 void radv_GetPhysicalDeviceMemoryProperties(
886 VkPhysicalDevice physicalDevice,
887 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
888 {
889 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
890
891 *pMemoryProperties = physical_device->memory_properties;
892 }
893
894 void radv_GetPhysicalDeviceMemoryProperties2KHR(
895 VkPhysicalDevice physicalDevice,
896 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
897 {
898 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
899 &pMemoryProperties->memoryProperties);
900 }
901
902 static enum radeon_ctx_priority
903 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
904 {
905 /* Default to MEDIUM when a specific global priority isn't requested */
906 if (!pObj)
907 return RADEON_CTX_PRIORITY_MEDIUM;
908
909 switch(pObj->globalPriority) {
910 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
911 return RADEON_CTX_PRIORITY_REALTIME;
912 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
913 return RADEON_CTX_PRIORITY_HIGH;
914 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
915 return RADEON_CTX_PRIORITY_MEDIUM;
916 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
917 return RADEON_CTX_PRIORITY_LOW;
918 default:
919 unreachable("Illegal global priority value");
920 return RADEON_CTX_PRIORITY_INVALID;
921 }
922 }
923
924 static int
925 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
926 uint32_t queue_family_index, int idx,
927 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
928 {
929 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
930 queue->device = device;
931 queue->queue_family_index = queue_family_index;
932 queue->queue_idx = idx;
933 queue->priority = radv_get_queue_global_priority(global_priority);
934
935 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
936 if (!queue->hw_ctx)
937 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
938
939 return VK_SUCCESS;
940 }
941
942 static void
943 radv_queue_finish(struct radv_queue *queue)
944 {
945 if (queue->hw_ctx)
946 queue->device->ws->ctx_destroy(queue->hw_ctx);
947
948 if (queue->initial_full_flush_preamble_cs)
949 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
950 if (queue->initial_preamble_cs)
951 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
952 if (queue->continue_preamble_cs)
953 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
954 if (queue->descriptor_bo)
955 queue->device->ws->buffer_destroy(queue->descriptor_bo);
956 if (queue->scratch_bo)
957 queue->device->ws->buffer_destroy(queue->scratch_bo);
958 if (queue->esgs_ring_bo)
959 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
960 if (queue->gsvs_ring_bo)
961 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
962 if (queue->tess_factor_ring_bo)
963 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
964 if (queue->tess_offchip_ring_bo)
965 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
966 if (queue->compute_scratch_bo)
967 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
968 }
969
970 static void
971 radv_device_init_gs_info(struct radv_device *device)
972 {
973 switch (device->physical_device->rad_info.family) {
974 case CHIP_OLAND:
975 case CHIP_HAINAN:
976 case CHIP_KAVERI:
977 case CHIP_KABINI:
978 case CHIP_MULLINS:
979 case CHIP_ICELAND:
980 case CHIP_CARRIZO:
981 case CHIP_STONEY:
982 device->gs_table_depth = 16;
983 return;
984 case CHIP_TAHITI:
985 case CHIP_PITCAIRN:
986 case CHIP_VERDE:
987 case CHIP_BONAIRE:
988 case CHIP_HAWAII:
989 case CHIP_TONGA:
990 case CHIP_FIJI:
991 case CHIP_POLARIS10:
992 case CHIP_POLARIS11:
993 case CHIP_POLARIS12:
994 case CHIP_VEGA10:
995 case CHIP_RAVEN:
996 device->gs_table_depth = 32;
997 return;
998 default:
999 unreachable("unknown GPU");
1000 }
1001 }
1002
1003 VkResult radv_CreateDevice(
1004 VkPhysicalDevice physicalDevice,
1005 const VkDeviceCreateInfo* pCreateInfo,
1006 const VkAllocationCallbacks* pAllocator,
1007 VkDevice* pDevice)
1008 {
1009 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1010 VkResult result;
1011 struct radv_device *device;
1012
1013 bool keep_shader_info = false;
1014
1015 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1016 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1017 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1018 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1019
1020 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1021 keep_shader_info = true;
1022 }
1023
1024 /* Check enabled features */
1025 if (pCreateInfo->pEnabledFeatures) {
1026 VkPhysicalDeviceFeatures supported_features;
1027 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1028 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1029 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1030 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1031 for (uint32_t i = 0; i < num_features; i++) {
1032 if (enabled_feature[i] && !supported_feature[i])
1033 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1034 }
1035 }
1036
1037 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1038 sizeof(*device), 8,
1039 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1040 if (!device)
1041 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1042
1043 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1044 device->instance = physical_device->instance;
1045 device->physical_device = physical_device;
1046
1047 device->ws = physical_device->ws;
1048 if (pAllocator)
1049 device->alloc = *pAllocator;
1050 else
1051 device->alloc = physical_device->instance->alloc;
1052
1053 mtx_init(&device->shader_slab_mutex, mtx_plain);
1054 list_inithead(&device->shader_slabs);
1055
1056 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1057 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1058 uint32_t qfi = queue_create->queueFamilyIndex;
1059 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1060 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1061
1062 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1063
1064 device->queues[qfi] = vk_alloc(&device->alloc,
1065 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1066 if (!device->queues[qfi]) {
1067 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1068 goto fail;
1069 }
1070
1071 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1072
1073 device->queue_count[qfi] = queue_create->queueCount;
1074
1075 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1076 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1077 if (result != VK_SUCCESS)
1078 goto fail;
1079 }
1080 }
1081
1082 #if HAVE_LLVM < 0x0400
1083 device->llvm_supports_spill = false;
1084 #else
1085 device->llvm_supports_spill = true;
1086 #endif
1087
1088 /* The maximum number of scratch waves. Scratch space isn't divided
1089 * evenly between CUs. The number is only a function of the number of CUs.
1090 * We can decrease the constant to decrease the scratch buffer size.
1091 *
1092 * sctx->scratch_waves must be >= the maximum posible size of
1093 * 1 threadgroup, so that the hw doesn't hang from being unable
1094 * to start any.
1095 *
1096 * The recommended value is 4 per CU at most. Higher numbers don't
1097 * bring much benefit, but they still occupy chip resources (think
1098 * async compute). I've seen ~2% performance difference between 4 and 32.
1099 */
1100 uint32_t max_threads_per_block = 2048;
1101 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1102 max_threads_per_block / 64);
1103
1104 radv_device_init_gs_info(device);
1105
1106 device->tess_offchip_block_dw_size =
1107 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1108 device->has_distributed_tess =
1109 device->physical_device->rad_info.chip_class >= VI &&
1110 device->physical_device->rad_info.max_se >= 2;
1111
1112 if (getenv("RADV_TRACE_FILE")) {
1113 keep_shader_info = true;
1114
1115 if (!radv_init_trace(device))
1116 goto fail;
1117 }
1118
1119 device->keep_shader_info = keep_shader_info;
1120
1121 result = radv_device_init_meta(device);
1122 if (result != VK_SUCCESS)
1123 goto fail;
1124
1125 radv_device_init_msaa(device);
1126
1127 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1128 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1129 switch (family) {
1130 case RADV_QUEUE_GENERAL:
1131 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1132 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1133 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1134 break;
1135 case RADV_QUEUE_COMPUTE:
1136 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1137 radeon_emit(device->empty_cs[family], 0);
1138 break;
1139 }
1140 device->ws->cs_finalize(device->empty_cs[family]);
1141 }
1142
1143 if (device->physical_device->rad_info.chip_class >= CIK)
1144 cik_create_gfx_config(device);
1145
1146 VkPipelineCacheCreateInfo ci;
1147 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1148 ci.pNext = NULL;
1149 ci.flags = 0;
1150 ci.pInitialData = NULL;
1151 ci.initialDataSize = 0;
1152 VkPipelineCache pc;
1153 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1154 &ci, NULL, &pc);
1155 if (result != VK_SUCCESS)
1156 goto fail;
1157
1158 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1159
1160 *pDevice = radv_device_to_handle(device);
1161 return VK_SUCCESS;
1162
1163 fail:
1164 if (device->trace_bo)
1165 device->ws->buffer_destroy(device->trace_bo);
1166
1167 if (device->gfx_init)
1168 device->ws->buffer_destroy(device->gfx_init);
1169
1170 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1171 for (unsigned q = 0; q < device->queue_count[i]; q++)
1172 radv_queue_finish(&device->queues[i][q]);
1173 if (device->queue_count[i])
1174 vk_free(&device->alloc, device->queues[i]);
1175 }
1176
1177 vk_free(&device->alloc, device);
1178 return result;
1179 }
1180
1181 void radv_DestroyDevice(
1182 VkDevice _device,
1183 const VkAllocationCallbacks* pAllocator)
1184 {
1185 RADV_FROM_HANDLE(radv_device, device, _device);
1186
1187 if (!device)
1188 return;
1189
1190 if (device->trace_bo)
1191 device->ws->buffer_destroy(device->trace_bo);
1192
1193 if (device->gfx_init)
1194 device->ws->buffer_destroy(device->gfx_init);
1195
1196 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1197 for (unsigned q = 0; q < device->queue_count[i]; q++)
1198 radv_queue_finish(&device->queues[i][q]);
1199 if (device->queue_count[i])
1200 vk_free(&device->alloc, device->queues[i]);
1201 if (device->empty_cs[i])
1202 device->ws->cs_destroy(device->empty_cs[i]);
1203 }
1204 radv_device_finish_meta(device);
1205
1206 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1207 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1208
1209 radv_destroy_shader_slabs(device);
1210
1211 vk_free(&device->alloc, device);
1212 }
1213
1214 VkResult radv_EnumerateInstanceLayerProperties(
1215 uint32_t* pPropertyCount,
1216 VkLayerProperties* pProperties)
1217 {
1218 if (pProperties == NULL) {
1219 *pPropertyCount = 0;
1220 return VK_SUCCESS;
1221 }
1222
1223 /* None supported at this time */
1224 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1225 }
1226
1227 VkResult radv_EnumerateDeviceLayerProperties(
1228 VkPhysicalDevice physicalDevice,
1229 uint32_t* pPropertyCount,
1230 VkLayerProperties* pProperties)
1231 {
1232 if (pProperties == NULL) {
1233 *pPropertyCount = 0;
1234 return VK_SUCCESS;
1235 }
1236
1237 /* None supported at this time */
1238 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1239 }
1240
1241 void radv_GetDeviceQueue(
1242 VkDevice _device,
1243 uint32_t queueFamilyIndex,
1244 uint32_t queueIndex,
1245 VkQueue* pQueue)
1246 {
1247 RADV_FROM_HANDLE(radv_device, device, _device);
1248
1249 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1250 }
1251
1252 static void
1253 fill_geom_tess_rings(struct radv_queue *queue,
1254 uint32_t *map,
1255 bool add_sample_positions,
1256 uint32_t esgs_ring_size,
1257 struct radeon_winsys_bo *esgs_ring_bo,
1258 uint32_t gsvs_ring_size,
1259 struct radeon_winsys_bo *gsvs_ring_bo,
1260 uint32_t tess_factor_ring_size,
1261 struct radeon_winsys_bo *tess_factor_ring_bo,
1262 uint32_t tess_offchip_ring_size,
1263 struct radeon_winsys_bo *tess_offchip_ring_bo)
1264 {
1265 uint64_t esgs_va = 0, gsvs_va = 0;
1266 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1267 uint32_t *desc = &map[4];
1268
1269 if (esgs_ring_bo)
1270 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1271 if (gsvs_ring_bo)
1272 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1273 if (tess_factor_ring_bo)
1274 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1275 if (tess_offchip_ring_bo)
1276 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1277
1278 /* stride 0, num records - size, add tid, swizzle, elsize4,
1279 index stride 64 */
1280 desc[0] = esgs_va;
1281 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1282 S_008F04_STRIDE(0) |
1283 S_008F04_SWIZZLE_ENABLE(true);
1284 desc[2] = esgs_ring_size;
1285 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1286 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1287 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1288 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1289 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1290 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1291 S_008F0C_ELEMENT_SIZE(1) |
1292 S_008F0C_INDEX_STRIDE(3) |
1293 S_008F0C_ADD_TID_ENABLE(true);
1294
1295 desc += 4;
1296 /* GS entry for ES->GS ring */
1297 /* stride 0, num records - size, elsize0,
1298 index stride 0 */
1299 desc[0] = esgs_va;
1300 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1301 S_008F04_STRIDE(0) |
1302 S_008F04_SWIZZLE_ENABLE(false);
1303 desc[2] = esgs_ring_size;
1304 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1305 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1306 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1307 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1308 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1310 S_008F0C_ELEMENT_SIZE(0) |
1311 S_008F0C_INDEX_STRIDE(0) |
1312 S_008F0C_ADD_TID_ENABLE(false);
1313
1314 desc += 4;
1315 /* VS entry for GS->VS ring */
1316 /* stride 0, num records - size, elsize0,
1317 index stride 0 */
1318 desc[0] = gsvs_va;
1319 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1320 S_008F04_STRIDE(0) |
1321 S_008F04_SWIZZLE_ENABLE(false);
1322 desc[2] = gsvs_ring_size;
1323 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1324 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1325 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1326 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1327 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1328 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1329 S_008F0C_ELEMENT_SIZE(0) |
1330 S_008F0C_INDEX_STRIDE(0) |
1331 S_008F0C_ADD_TID_ENABLE(false);
1332 desc += 4;
1333
1334 /* stride gsvs_itemsize, num records 64
1335 elsize 4, index stride 16 */
1336 /* shader will patch stride and desc[2] */
1337 desc[0] = gsvs_va;
1338 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1339 S_008F04_STRIDE(0) |
1340 S_008F04_SWIZZLE_ENABLE(true);
1341 desc[2] = 0;
1342 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1343 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1344 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1345 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1346 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1347 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1348 S_008F0C_ELEMENT_SIZE(1) |
1349 S_008F0C_INDEX_STRIDE(1) |
1350 S_008F0C_ADD_TID_ENABLE(true);
1351 desc += 4;
1352
1353 desc[0] = tess_factor_va;
1354 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1355 S_008F04_STRIDE(0) |
1356 S_008F04_SWIZZLE_ENABLE(false);
1357 desc[2] = tess_factor_ring_size;
1358 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1359 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1360 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1361 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1362 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1363 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1364 S_008F0C_ELEMENT_SIZE(0) |
1365 S_008F0C_INDEX_STRIDE(0) |
1366 S_008F0C_ADD_TID_ENABLE(false);
1367 desc += 4;
1368
1369 desc[0] = tess_offchip_va;
1370 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1371 S_008F04_STRIDE(0) |
1372 S_008F04_SWIZZLE_ENABLE(false);
1373 desc[2] = tess_offchip_ring_size;
1374 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1375 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1376 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1377 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1378 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1379 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1380 S_008F0C_ELEMENT_SIZE(0) |
1381 S_008F0C_INDEX_STRIDE(0) |
1382 S_008F0C_ADD_TID_ENABLE(false);
1383 desc += 4;
1384
1385 /* add sample positions after all rings */
1386 memcpy(desc, queue->device->sample_locations_1x, 8);
1387 desc += 2;
1388 memcpy(desc, queue->device->sample_locations_2x, 16);
1389 desc += 4;
1390 memcpy(desc, queue->device->sample_locations_4x, 32);
1391 desc += 8;
1392 memcpy(desc, queue->device->sample_locations_8x, 64);
1393 desc += 16;
1394 memcpy(desc, queue->device->sample_locations_16x, 128);
1395 }
1396
1397 static unsigned
1398 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1399 {
1400 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1401 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1402 device->physical_device->rad_info.family != CHIP_STONEY;
1403 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1404 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1405 device->physical_device->rad_info.max_se;
1406 unsigned offchip_granularity;
1407 unsigned hs_offchip_param;
1408 switch (device->tess_offchip_block_dw_size) {
1409 default:
1410 assert(0);
1411 /* fall through */
1412 case 8192:
1413 offchip_granularity = V_03093C_X_8K_DWORDS;
1414 break;
1415 case 4096:
1416 offchip_granularity = V_03093C_X_4K_DWORDS;
1417 break;
1418 }
1419
1420 switch (device->physical_device->rad_info.chip_class) {
1421 case SI:
1422 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1423 break;
1424 case CIK:
1425 case VI:
1426 case GFX9:
1427 default:
1428 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1429 break;
1430 }
1431
1432 *max_offchip_buffers_p = max_offchip_buffers;
1433 if (device->physical_device->rad_info.chip_class >= CIK) {
1434 if (device->physical_device->rad_info.chip_class >= VI)
1435 --max_offchip_buffers;
1436 hs_offchip_param =
1437 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1438 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1439 } else {
1440 hs_offchip_param =
1441 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1442 }
1443 return hs_offchip_param;
1444 }
1445
1446 static VkResult
1447 radv_get_preamble_cs(struct radv_queue *queue,
1448 uint32_t scratch_size,
1449 uint32_t compute_scratch_size,
1450 uint32_t esgs_ring_size,
1451 uint32_t gsvs_ring_size,
1452 bool needs_tess_rings,
1453 bool needs_sample_positions,
1454 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1455 struct radeon_winsys_cs **initial_preamble_cs,
1456 struct radeon_winsys_cs **continue_preamble_cs)
1457 {
1458 struct radeon_winsys_bo *scratch_bo = NULL;
1459 struct radeon_winsys_bo *descriptor_bo = NULL;
1460 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1461 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1462 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1463 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1464 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1465 struct radeon_winsys_cs *dest_cs[3] = {0};
1466 bool add_tess_rings = false, add_sample_positions = false;
1467 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1468 unsigned max_offchip_buffers;
1469 unsigned hs_offchip_param = 0;
1470 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1471 if (!queue->has_tess_rings) {
1472 if (needs_tess_rings)
1473 add_tess_rings = true;
1474 }
1475 if (!queue->has_sample_positions) {
1476 if (needs_sample_positions)
1477 add_sample_positions = true;
1478 }
1479 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1480 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1481 &max_offchip_buffers);
1482 tess_offchip_ring_size = max_offchip_buffers *
1483 queue->device->tess_offchip_block_dw_size * 4;
1484
1485 if (scratch_size <= queue->scratch_size &&
1486 compute_scratch_size <= queue->compute_scratch_size &&
1487 esgs_ring_size <= queue->esgs_ring_size &&
1488 gsvs_ring_size <= queue->gsvs_ring_size &&
1489 !add_tess_rings && !add_sample_positions &&
1490 queue->initial_preamble_cs) {
1491 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1492 *initial_preamble_cs = queue->initial_preamble_cs;
1493 *continue_preamble_cs = queue->continue_preamble_cs;
1494 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1495 *continue_preamble_cs = NULL;
1496 return VK_SUCCESS;
1497 }
1498
1499 if (scratch_size > queue->scratch_size) {
1500 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1501 scratch_size,
1502 4096,
1503 RADEON_DOMAIN_VRAM,
1504 ring_bo_flags);
1505 if (!scratch_bo)
1506 goto fail;
1507 } else
1508 scratch_bo = queue->scratch_bo;
1509
1510 if (compute_scratch_size > queue->compute_scratch_size) {
1511 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1512 compute_scratch_size,
1513 4096,
1514 RADEON_DOMAIN_VRAM,
1515 ring_bo_flags);
1516 if (!compute_scratch_bo)
1517 goto fail;
1518
1519 } else
1520 compute_scratch_bo = queue->compute_scratch_bo;
1521
1522 if (esgs_ring_size > queue->esgs_ring_size) {
1523 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1524 esgs_ring_size,
1525 4096,
1526 RADEON_DOMAIN_VRAM,
1527 ring_bo_flags);
1528 if (!esgs_ring_bo)
1529 goto fail;
1530 } else {
1531 esgs_ring_bo = queue->esgs_ring_bo;
1532 esgs_ring_size = queue->esgs_ring_size;
1533 }
1534
1535 if (gsvs_ring_size > queue->gsvs_ring_size) {
1536 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1537 gsvs_ring_size,
1538 4096,
1539 RADEON_DOMAIN_VRAM,
1540 ring_bo_flags);
1541 if (!gsvs_ring_bo)
1542 goto fail;
1543 } else {
1544 gsvs_ring_bo = queue->gsvs_ring_bo;
1545 gsvs_ring_size = queue->gsvs_ring_size;
1546 }
1547
1548 if (add_tess_rings) {
1549 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1550 tess_factor_ring_size,
1551 256,
1552 RADEON_DOMAIN_VRAM,
1553 ring_bo_flags);
1554 if (!tess_factor_ring_bo)
1555 goto fail;
1556 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1557 tess_offchip_ring_size,
1558 256,
1559 RADEON_DOMAIN_VRAM,
1560 ring_bo_flags);
1561 if (!tess_offchip_ring_bo)
1562 goto fail;
1563 } else {
1564 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1565 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1566 }
1567
1568 if (scratch_bo != queue->scratch_bo ||
1569 esgs_ring_bo != queue->esgs_ring_bo ||
1570 gsvs_ring_bo != queue->gsvs_ring_bo ||
1571 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1572 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1573 uint32_t size = 0;
1574 if (gsvs_ring_bo || esgs_ring_bo ||
1575 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1576 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1577 if (add_sample_positions)
1578 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1579 }
1580 else if (scratch_bo)
1581 size = 8; /* 2 dword */
1582
1583 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1584 size,
1585 4096,
1586 RADEON_DOMAIN_VRAM,
1587 RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
1588 if (!descriptor_bo)
1589 goto fail;
1590 } else
1591 descriptor_bo = queue->descriptor_bo;
1592
1593 for(int i = 0; i < 3; ++i) {
1594 struct radeon_winsys_cs *cs = NULL;
1595 cs = queue->device->ws->cs_create(queue->device->ws,
1596 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1597 if (!cs)
1598 goto fail;
1599
1600 dest_cs[i] = cs;
1601
1602 if (scratch_bo)
1603 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1604
1605 if (esgs_ring_bo)
1606 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1607
1608 if (gsvs_ring_bo)
1609 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1610
1611 if (tess_factor_ring_bo)
1612 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1613
1614 if (tess_offchip_ring_bo)
1615 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1616
1617 if (descriptor_bo)
1618 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1619
1620 if (descriptor_bo != queue->descriptor_bo) {
1621 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1622
1623 if (scratch_bo) {
1624 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1625 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1626 S_008F04_SWIZZLE_ENABLE(1);
1627 map[0] = scratch_va;
1628 map[1] = rsrc1;
1629 }
1630
1631 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1632 add_sample_positions)
1633 fill_geom_tess_rings(queue, map, add_sample_positions,
1634 esgs_ring_size, esgs_ring_bo,
1635 gsvs_ring_size, gsvs_ring_bo,
1636 tess_factor_ring_size, tess_factor_ring_bo,
1637 tess_offchip_ring_size, tess_offchip_ring_bo);
1638
1639 queue->device->ws->buffer_unmap(descriptor_bo);
1640 }
1641
1642 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1643 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1644 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1645 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1646 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1647 }
1648
1649 if (esgs_ring_bo || gsvs_ring_bo) {
1650 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1651 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1652 radeon_emit(cs, esgs_ring_size >> 8);
1653 radeon_emit(cs, gsvs_ring_size >> 8);
1654 } else {
1655 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1656 radeon_emit(cs, esgs_ring_size >> 8);
1657 radeon_emit(cs, gsvs_ring_size >> 8);
1658 }
1659 }
1660
1661 if (tess_factor_ring_bo) {
1662 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1663 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1664 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1665 S_030938_SIZE(tess_factor_ring_size / 4));
1666 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1667 tf_va >> 8);
1668 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1669 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1670 tf_va >> 40);
1671 }
1672 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1673 } else {
1674 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1675 S_008988_SIZE(tess_factor_ring_size / 4));
1676 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1677 tf_va >> 8);
1678 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1679 hs_offchip_param);
1680 }
1681 }
1682
1683 if (descriptor_bo) {
1684 uint64_t va = radv_buffer_get_va(descriptor_bo);
1685 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1686 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1687 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1688 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1689 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1690
1691 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1692 radeon_set_sh_reg_seq(cs, regs[i], 2);
1693 radeon_emit(cs, va);
1694 radeon_emit(cs, va >> 32);
1695 }
1696 } else {
1697 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1698 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1699 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1700 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1701 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1702 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1703
1704 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1705 radeon_set_sh_reg_seq(cs, regs[i], 2);
1706 radeon_emit(cs, va);
1707 radeon_emit(cs, va >> 32);
1708 }
1709 }
1710 }
1711
1712 if (compute_scratch_bo) {
1713 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1714 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1715 S_008F04_SWIZZLE_ENABLE(1);
1716
1717 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1718
1719 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1720 radeon_emit(cs, scratch_va);
1721 radeon_emit(cs, rsrc1);
1722 }
1723
1724 if (i == 0) {
1725 si_cs_emit_cache_flush(cs,
1726 false,
1727 queue->device->physical_device->rad_info.chip_class,
1728 NULL, 0,
1729 queue->queue_family_index == RING_COMPUTE &&
1730 queue->device->physical_device->rad_info.chip_class >= CIK,
1731 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1732 RADV_CMD_FLAG_INV_ICACHE |
1733 RADV_CMD_FLAG_INV_SMEM_L1 |
1734 RADV_CMD_FLAG_INV_VMEM_L1 |
1735 RADV_CMD_FLAG_INV_GLOBAL_L2);
1736 } else if (i == 1) {
1737 si_cs_emit_cache_flush(cs,
1738 false,
1739 queue->device->physical_device->rad_info.chip_class,
1740 NULL, 0,
1741 queue->queue_family_index == RING_COMPUTE &&
1742 queue->device->physical_device->rad_info.chip_class >= CIK,
1743 RADV_CMD_FLAG_INV_ICACHE |
1744 RADV_CMD_FLAG_INV_SMEM_L1 |
1745 RADV_CMD_FLAG_INV_VMEM_L1 |
1746 RADV_CMD_FLAG_INV_GLOBAL_L2);
1747 }
1748
1749 if (!queue->device->ws->cs_finalize(cs))
1750 goto fail;
1751 }
1752
1753 if (queue->initial_full_flush_preamble_cs)
1754 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1755
1756 if (queue->initial_preamble_cs)
1757 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1758
1759 if (queue->continue_preamble_cs)
1760 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1761
1762 queue->initial_full_flush_preamble_cs = dest_cs[0];
1763 queue->initial_preamble_cs = dest_cs[1];
1764 queue->continue_preamble_cs = dest_cs[2];
1765
1766 if (scratch_bo != queue->scratch_bo) {
1767 if (queue->scratch_bo)
1768 queue->device->ws->buffer_destroy(queue->scratch_bo);
1769 queue->scratch_bo = scratch_bo;
1770 queue->scratch_size = scratch_size;
1771 }
1772
1773 if (compute_scratch_bo != queue->compute_scratch_bo) {
1774 if (queue->compute_scratch_bo)
1775 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1776 queue->compute_scratch_bo = compute_scratch_bo;
1777 queue->compute_scratch_size = compute_scratch_size;
1778 }
1779
1780 if (esgs_ring_bo != queue->esgs_ring_bo) {
1781 if (queue->esgs_ring_bo)
1782 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1783 queue->esgs_ring_bo = esgs_ring_bo;
1784 queue->esgs_ring_size = esgs_ring_size;
1785 }
1786
1787 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1788 if (queue->gsvs_ring_bo)
1789 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1790 queue->gsvs_ring_bo = gsvs_ring_bo;
1791 queue->gsvs_ring_size = gsvs_ring_size;
1792 }
1793
1794 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1795 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1796 }
1797
1798 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1799 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1800 queue->has_tess_rings = true;
1801 }
1802
1803 if (descriptor_bo != queue->descriptor_bo) {
1804 if (queue->descriptor_bo)
1805 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1806
1807 queue->descriptor_bo = descriptor_bo;
1808 }
1809
1810 if (add_sample_positions)
1811 queue->has_sample_positions = true;
1812
1813 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1814 *initial_preamble_cs = queue->initial_preamble_cs;
1815 *continue_preamble_cs = queue->continue_preamble_cs;
1816 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1817 *continue_preamble_cs = NULL;
1818 return VK_SUCCESS;
1819 fail:
1820 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1821 if (dest_cs[i])
1822 queue->device->ws->cs_destroy(dest_cs[i]);
1823 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1824 queue->device->ws->buffer_destroy(descriptor_bo);
1825 if (scratch_bo && scratch_bo != queue->scratch_bo)
1826 queue->device->ws->buffer_destroy(scratch_bo);
1827 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1828 queue->device->ws->buffer_destroy(compute_scratch_bo);
1829 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1830 queue->device->ws->buffer_destroy(esgs_ring_bo);
1831 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1832 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1833 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1834 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1835 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1836 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1837 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1838 }
1839
1840 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1841 int num_sems,
1842 const VkSemaphore *sems,
1843 bool reset_temp)
1844 {
1845 int syncobj_idx = 0, sem_idx = 0;
1846
1847 if (num_sems == 0)
1848 return VK_SUCCESS;
1849 for (uint32_t i = 0; i < num_sems; i++) {
1850 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1851
1852 if (sem->temp_syncobj || sem->syncobj)
1853 counts->syncobj_count++;
1854 else
1855 counts->sem_count++;
1856 }
1857
1858 if (counts->syncobj_count) {
1859 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1860 if (!counts->syncobj)
1861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1862 }
1863
1864 if (counts->sem_count) {
1865 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1866 if (!counts->sem) {
1867 free(counts->syncobj);
1868 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1869 }
1870 }
1871
1872 for (uint32_t i = 0; i < num_sems; i++) {
1873 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1874
1875 if (sem->temp_syncobj) {
1876 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1877 }
1878 else if (sem->syncobj)
1879 counts->syncobj[syncobj_idx++] = sem->syncobj;
1880 else {
1881 assert(sem->sem);
1882 counts->sem[sem_idx++] = sem->sem;
1883 }
1884 }
1885
1886 return VK_SUCCESS;
1887 }
1888
1889 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1890 {
1891 free(sem_info->wait.syncobj);
1892 free(sem_info->wait.sem);
1893 free(sem_info->signal.syncobj);
1894 free(sem_info->signal.sem);
1895 }
1896
1897
1898 static void radv_free_temp_syncobjs(struct radv_device *device,
1899 int num_sems,
1900 const VkSemaphore *sems)
1901 {
1902 for (uint32_t i = 0; i < num_sems; i++) {
1903 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1904
1905 if (sem->temp_syncobj) {
1906 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1907 sem->temp_syncobj = 0;
1908 }
1909 }
1910 }
1911
1912 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1913 int num_wait_sems,
1914 const VkSemaphore *wait_sems,
1915 int num_signal_sems,
1916 const VkSemaphore *signal_sems)
1917 {
1918 VkResult ret;
1919 memset(sem_info, 0, sizeof(*sem_info));
1920
1921 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1922 if (ret)
1923 return ret;
1924 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1925 if (ret)
1926 radv_free_sem_info(sem_info);
1927
1928 /* caller can override these */
1929 sem_info->cs_emit_wait = true;
1930 sem_info->cs_emit_signal = true;
1931 return ret;
1932 }
1933
1934 VkResult radv_QueueSubmit(
1935 VkQueue _queue,
1936 uint32_t submitCount,
1937 const VkSubmitInfo* pSubmits,
1938 VkFence _fence)
1939 {
1940 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1941 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1942 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1943 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1944 int ret;
1945 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1946 uint32_t scratch_size = 0;
1947 uint32_t compute_scratch_size = 0;
1948 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1949 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1950 VkResult result;
1951 bool fence_emitted = false;
1952 bool tess_rings_needed = false;
1953 bool sample_positions_needed = false;
1954
1955 /* Do this first so failing to allocate scratch buffers can't result in
1956 * partially executed submissions. */
1957 for (uint32_t i = 0; i < submitCount; i++) {
1958 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1959 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1960 pSubmits[i].pCommandBuffers[j]);
1961
1962 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1963 compute_scratch_size = MAX2(compute_scratch_size,
1964 cmd_buffer->compute_scratch_size_needed);
1965 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1966 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1967 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1968 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1969 }
1970 }
1971
1972 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1973 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1974 sample_positions_needed, &initial_flush_preamble_cs,
1975 &initial_preamble_cs, &continue_preamble_cs);
1976 if (result != VK_SUCCESS)
1977 return result;
1978
1979 for (uint32_t i = 0; i < submitCount; i++) {
1980 struct radeon_winsys_cs **cs_array;
1981 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1982 bool can_patch = true;
1983 uint32_t advance;
1984 struct radv_winsys_sem_info sem_info;
1985
1986 result = radv_alloc_sem_info(&sem_info,
1987 pSubmits[i].waitSemaphoreCount,
1988 pSubmits[i].pWaitSemaphores,
1989 pSubmits[i].signalSemaphoreCount,
1990 pSubmits[i].pSignalSemaphores);
1991 if (result != VK_SUCCESS)
1992 return result;
1993
1994 if (!pSubmits[i].commandBufferCount) {
1995 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1996 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1997 &queue->device->empty_cs[queue->queue_family_index],
1998 1, NULL, NULL,
1999 &sem_info,
2000 false, base_fence);
2001 if (ret) {
2002 radv_loge("failed to submit CS %d\n", i);
2003 abort();
2004 }
2005 fence_emitted = true;
2006 }
2007 radv_free_sem_info(&sem_info);
2008 continue;
2009 }
2010
2011 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2012 (pSubmits[i].commandBufferCount));
2013
2014 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2016 pSubmits[i].pCommandBuffers[j]);
2017 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2018
2019 cs_array[j] = cmd_buffer->cs;
2020 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2021 can_patch = false;
2022 }
2023
2024 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2025 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2026 advance = MIN2(max_cs_submission,
2027 pSubmits[i].commandBufferCount - j);
2028
2029 if (queue->device->trace_bo)
2030 *queue->device->trace_id_ptr = 0;
2031
2032 sem_info.cs_emit_wait = j == 0;
2033 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2034
2035 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2036 advance, initial_preamble, continue_preamble_cs,
2037 &sem_info,
2038 can_patch, base_fence);
2039
2040 if (ret) {
2041 radv_loge("failed to submit CS %d\n", i);
2042 abort();
2043 }
2044 fence_emitted = true;
2045 if (queue->device->trace_bo) {
2046 radv_check_gpu_hangs(queue, cs_array[j]);
2047 }
2048 }
2049
2050 radv_free_temp_syncobjs(queue->device,
2051 pSubmits[i].waitSemaphoreCount,
2052 pSubmits[i].pWaitSemaphores);
2053 radv_free_sem_info(&sem_info);
2054 free(cs_array);
2055 }
2056
2057 if (fence) {
2058 if (!fence_emitted) {
2059 struct radv_winsys_sem_info sem_info = {0};
2060 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2061 &queue->device->empty_cs[queue->queue_family_index],
2062 1, NULL, NULL, &sem_info,
2063 false, base_fence);
2064 }
2065 fence->submitted = true;
2066 }
2067
2068 return VK_SUCCESS;
2069 }
2070
2071 VkResult radv_QueueWaitIdle(
2072 VkQueue _queue)
2073 {
2074 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2075
2076 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2077 radv_queue_family_to_ring(queue->queue_family_index),
2078 queue->queue_idx);
2079 return VK_SUCCESS;
2080 }
2081
2082 VkResult radv_DeviceWaitIdle(
2083 VkDevice _device)
2084 {
2085 RADV_FROM_HANDLE(radv_device, device, _device);
2086
2087 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2088 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2089 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2090 }
2091 }
2092 return VK_SUCCESS;
2093 }
2094
2095 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2096 VkInstance instance,
2097 const char* pName)
2098 {
2099 return radv_lookup_entrypoint(pName);
2100 }
2101
2102 /* The loader wants us to expose a second GetInstanceProcAddr function
2103 * to work around certain LD_PRELOAD issues seen in apps.
2104 */
2105 PUBLIC
2106 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2107 VkInstance instance,
2108 const char* pName);
2109
2110 PUBLIC
2111 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2112 VkInstance instance,
2113 const char* pName)
2114 {
2115 return radv_GetInstanceProcAddr(instance, pName);
2116 }
2117
2118 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2119 VkDevice device,
2120 const char* pName)
2121 {
2122 return radv_lookup_entrypoint(pName);
2123 }
2124
2125 bool radv_get_memory_fd(struct radv_device *device,
2126 struct radv_device_memory *memory,
2127 int *pFD)
2128 {
2129 struct radeon_bo_metadata metadata;
2130
2131 if (memory->image) {
2132 radv_init_metadata(device, memory->image, &metadata);
2133 device->ws->buffer_set_metadata(memory->bo, &metadata);
2134 }
2135
2136 return device->ws->buffer_get_fd(device->ws, memory->bo,
2137 pFD);
2138 }
2139
2140 static VkResult radv_alloc_memory(struct radv_device *device,
2141 const VkMemoryAllocateInfo* pAllocateInfo,
2142 const VkAllocationCallbacks* pAllocator,
2143 VkDeviceMemory* pMem)
2144 {
2145 struct radv_device_memory *mem;
2146 VkResult result;
2147 enum radeon_bo_domain domain;
2148 uint32_t flags = 0;
2149 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2150
2151 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2152
2153 if (pAllocateInfo->allocationSize == 0) {
2154 /* Apparently, this is allowed */
2155 *pMem = VK_NULL_HANDLE;
2156 return VK_SUCCESS;
2157 }
2158
2159 const VkImportMemoryFdInfoKHR *import_info =
2160 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2161 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2162 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2163
2164 const struct wsi_memory_allocate_info *wsi_info =
2165 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2166
2167 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2168 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2169 if (mem == NULL)
2170 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2171
2172 if (wsi_info && wsi_info->implicit_sync)
2173 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2174
2175 if (dedicate_info) {
2176 mem->image = radv_image_from_handle(dedicate_info->image);
2177 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2178 } else {
2179 mem->image = NULL;
2180 mem->buffer = NULL;
2181 }
2182
2183 if (import_info) {
2184 assert(import_info->handleType ==
2185 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2186 import_info->handleType ==
2187 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2188 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2189 NULL, NULL);
2190 if (!mem->bo) {
2191 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2192 goto fail;
2193 } else {
2194 close(import_info->fd);
2195 goto out_success;
2196 }
2197 }
2198
2199 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2200 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2201 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2202 domain = RADEON_DOMAIN_GTT;
2203 else
2204 domain = RADEON_DOMAIN_VRAM;
2205
2206 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2207 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2208 else
2209 flags |= RADEON_FLAG_CPU_ACCESS;
2210
2211 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2212 flags |= RADEON_FLAG_GTT_WC;
2213
2214 if (!dedicate_info && !import_info)
2215 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2216
2217 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2218 domain, flags);
2219
2220 if (!mem->bo) {
2221 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2222 goto fail;
2223 }
2224 mem->type_index = mem_type_index;
2225 out_success:
2226 *pMem = radv_device_memory_to_handle(mem);
2227
2228 return VK_SUCCESS;
2229
2230 fail:
2231 vk_free2(&device->alloc, pAllocator, mem);
2232
2233 return result;
2234 }
2235
2236 VkResult radv_AllocateMemory(
2237 VkDevice _device,
2238 const VkMemoryAllocateInfo* pAllocateInfo,
2239 const VkAllocationCallbacks* pAllocator,
2240 VkDeviceMemory* pMem)
2241 {
2242 RADV_FROM_HANDLE(radv_device, device, _device);
2243 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2244 }
2245
2246 void radv_FreeMemory(
2247 VkDevice _device,
2248 VkDeviceMemory _mem,
2249 const VkAllocationCallbacks* pAllocator)
2250 {
2251 RADV_FROM_HANDLE(radv_device, device, _device);
2252 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2253
2254 if (mem == NULL)
2255 return;
2256
2257 device->ws->buffer_destroy(mem->bo);
2258 mem->bo = NULL;
2259
2260 vk_free2(&device->alloc, pAllocator, mem);
2261 }
2262
2263 VkResult radv_MapMemory(
2264 VkDevice _device,
2265 VkDeviceMemory _memory,
2266 VkDeviceSize offset,
2267 VkDeviceSize size,
2268 VkMemoryMapFlags flags,
2269 void** ppData)
2270 {
2271 RADV_FROM_HANDLE(radv_device, device, _device);
2272 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2273
2274 if (mem == NULL) {
2275 *ppData = NULL;
2276 return VK_SUCCESS;
2277 }
2278
2279 *ppData = device->ws->buffer_map(mem->bo);
2280 if (*ppData) {
2281 *ppData += offset;
2282 return VK_SUCCESS;
2283 }
2284
2285 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2286 }
2287
2288 void radv_UnmapMemory(
2289 VkDevice _device,
2290 VkDeviceMemory _memory)
2291 {
2292 RADV_FROM_HANDLE(radv_device, device, _device);
2293 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2294
2295 if (mem == NULL)
2296 return;
2297
2298 device->ws->buffer_unmap(mem->bo);
2299 }
2300
2301 VkResult radv_FlushMappedMemoryRanges(
2302 VkDevice _device,
2303 uint32_t memoryRangeCount,
2304 const VkMappedMemoryRange* pMemoryRanges)
2305 {
2306 return VK_SUCCESS;
2307 }
2308
2309 VkResult radv_InvalidateMappedMemoryRanges(
2310 VkDevice _device,
2311 uint32_t memoryRangeCount,
2312 const VkMappedMemoryRange* pMemoryRanges)
2313 {
2314 return VK_SUCCESS;
2315 }
2316
2317 void radv_GetBufferMemoryRequirements(
2318 VkDevice _device,
2319 VkBuffer _buffer,
2320 VkMemoryRequirements* pMemoryRequirements)
2321 {
2322 RADV_FROM_HANDLE(radv_device, device, _device);
2323 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2324
2325 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2326
2327 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2328 pMemoryRequirements->alignment = 4096;
2329 else
2330 pMemoryRequirements->alignment = 16;
2331
2332 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2333 }
2334
2335 void radv_GetBufferMemoryRequirements2KHR(
2336 VkDevice device,
2337 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2338 VkMemoryRequirements2KHR* pMemoryRequirements)
2339 {
2340 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2341 &pMemoryRequirements->memoryRequirements);
2342 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2343 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2344 switch (ext->sType) {
2345 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2346 VkMemoryDedicatedRequirementsKHR *req =
2347 (VkMemoryDedicatedRequirementsKHR *) ext;
2348 req->requiresDedicatedAllocation = buffer->shareable;
2349 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2350 break;
2351 }
2352 default:
2353 break;
2354 }
2355 }
2356 }
2357
2358 void radv_GetImageMemoryRequirements(
2359 VkDevice _device,
2360 VkImage _image,
2361 VkMemoryRequirements* pMemoryRequirements)
2362 {
2363 RADV_FROM_HANDLE(radv_device, device, _device);
2364 RADV_FROM_HANDLE(radv_image, image, _image);
2365
2366 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2367
2368 pMemoryRequirements->size = image->size;
2369 pMemoryRequirements->alignment = image->alignment;
2370 }
2371
2372 void radv_GetImageMemoryRequirements2KHR(
2373 VkDevice device,
2374 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2375 VkMemoryRequirements2KHR* pMemoryRequirements)
2376 {
2377 radv_GetImageMemoryRequirements(device, pInfo->image,
2378 &pMemoryRequirements->memoryRequirements);
2379
2380 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2381
2382 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2383 switch (ext->sType) {
2384 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2385 VkMemoryDedicatedRequirementsKHR *req =
2386 (VkMemoryDedicatedRequirementsKHR *) ext;
2387 req->requiresDedicatedAllocation = image->shareable;
2388 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2389 break;
2390 }
2391 default:
2392 break;
2393 }
2394 }
2395 }
2396
2397 void radv_GetImageSparseMemoryRequirements(
2398 VkDevice device,
2399 VkImage image,
2400 uint32_t* pSparseMemoryRequirementCount,
2401 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2402 {
2403 stub();
2404 }
2405
2406 void radv_GetImageSparseMemoryRequirements2KHR(
2407 VkDevice device,
2408 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2409 uint32_t* pSparseMemoryRequirementCount,
2410 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2411 {
2412 stub();
2413 }
2414
2415 void radv_GetDeviceMemoryCommitment(
2416 VkDevice device,
2417 VkDeviceMemory memory,
2418 VkDeviceSize* pCommittedMemoryInBytes)
2419 {
2420 *pCommittedMemoryInBytes = 0;
2421 }
2422
2423 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2424 uint32_t bindInfoCount,
2425 const VkBindBufferMemoryInfoKHR *pBindInfos)
2426 {
2427 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2428 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2429 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2430
2431 if (mem) {
2432 buffer->bo = mem->bo;
2433 buffer->offset = pBindInfos[i].memoryOffset;
2434 } else {
2435 buffer->bo = NULL;
2436 }
2437 }
2438 return VK_SUCCESS;
2439 }
2440
2441 VkResult radv_BindBufferMemory(
2442 VkDevice device,
2443 VkBuffer buffer,
2444 VkDeviceMemory memory,
2445 VkDeviceSize memoryOffset)
2446 {
2447 const VkBindBufferMemoryInfoKHR info = {
2448 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2449 .buffer = buffer,
2450 .memory = memory,
2451 .memoryOffset = memoryOffset
2452 };
2453
2454 return radv_BindBufferMemory2KHR(device, 1, &info);
2455 }
2456
2457 VkResult radv_BindImageMemory2KHR(VkDevice device,
2458 uint32_t bindInfoCount,
2459 const VkBindImageMemoryInfoKHR *pBindInfos)
2460 {
2461 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2462 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2463 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2464
2465 if (mem) {
2466 image->bo = mem->bo;
2467 image->offset = pBindInfos[i].memoryOffset;
2468 } else {
2469 image->bo = NULL;
2470 image->offset = 0;
2471 }
2472 }
2473 return VK_SUCCESS;
2474 }
2475
2476
2477 VkResult radv_BindImageMemory(
2478 VkDevice device,
2479 VkImage image,
2480 VkDeviceMemory memory,
2481 VkDeviceSize memoryOffset)
2482 {
2483 const VkBindImageMemoryInfoKHR info = {
2484 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2485 .image = image,
2486 .memory = memory,
2487 .memoryOffset = memoryOffset
2488 };
2489
2490 return radv_BindImageMemory2KHR(device, 1, &info);
2491 }
2492
2493
2494 static void
2495 radv_sparse_buffer_bind_memory(struct radv_device *device,
2496 const VkSparseBufferMemoryBindInfo *bind)
2497 {
2498 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2499
2500 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2501 struct radv_device_memory *mem = NULL;
2502
2503 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2504 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2505
2506 device->ws->buffer_virtual_bind(buffer->bo,
2507 bind->pBinds[i].resourceOffset,
2508 bind->pBinds[i].size,
2509 mem ? mem->bo : NULL,
2510 bind->pBinds[i].memoryOffset);
2511 }
2512 }
2513
2514 static void
2515 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2516 const VkSparseImageOpaqueMemoryBindInfo *bind)
2517 {
2518 RADV_FROM_HANDLE(radv_image, image, bind->image);
2519
2520 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2521 struct radv_device_memory *mem = NULL;
2522
2523 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2524 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2525
2526 device->ws->buffer_virtual_bind(image->bo,
2527 bind->pBinds[i].resourceOffset,
2528 bind->pBinds[i].size,
2529 mem ? mem->bo : NULL,
2530 bind->pBinds[i].memoryOffset);
2531 }
2532 }
2533
2534 VkResult radv_QueueBindSparse(
2535 VkQueue _queue,
2536 uint32_t bindInfoCount,
2537 const VkBindSparseInfo* pBindInfo,
2538 VkFence _fence)
2539 {
2540 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2541 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2542 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2543 bool fence_emitted = false;
2544
2545 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2546 struct radv_winsys_sem_info sem_info;
2547 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2548 radv_sparse_buffer_bind_memory(queue->device,
2549 pBindInfo[i].pBufferBinds + j);
2550 }
2551
2552 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2553 radv_sparse_image_opaque_bind_memory(queue->device,
2554 pBindInfo[i].pImageOpaqueBinds + j);
2555 }
2556
2557 VkResult result;
2558 result = radv_alloc_sem_info(&sem_info,
2559 pBindInfo[i].waitSemaphoreCount,
2560 pBindInfo[i].pWaitSemaphores,
2561 pBindInfo[i].signalSemaphoreCount,
2562 pBindInfo[i].pSignalSemaphores);
2563 if (result != VK_SUCCESS)
2564 return result;
2565
2566 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2567 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2568 &queue->device->empty_cs[queue->queue_family_index],
2569 1, NULL, NULL,
2570 &sem_info,
2571 false, base_fence);
2572 fence_emitted = true;
2573 if (fence)
2574 fence->submitted = true;
2575 }
2576
2577 radv_free_sem_info(&sem_info);
2578
2579 }
2580
2581 if (fence && !fence_emitted) {
2582 fence->signalled = true;
2583 }
2584
2585 return VK_SUCCESS;
2586 }
2587
2588 VkResult radv_CreateFence(
2589 VkDevice _device,
2590 const VkFenceCreateInfo* pCreateInfo,
2591 const VkAllocationCallbacks* pAllocator,
2592 VkFence* pFence)
2593 {
2594 RADV_FROM_HANDLE(radv_device, device, _device);
2595 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2596 sizeof(*fence), 8,
2597 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2598
2599 if (!fence)
2600 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2601
2602 fence->submitted = false;
2603 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2604 fence->fence = device->ws->create_fence();
2605 if (!fence->fence) {
2606 vk_free2(&device->alloc, pAllocator, fence);
2607 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2608 }
2609
2610 *pFence = radv_fence_to_handle(fence);
2611
2612 return VK_SUCCESS;
2613 }
2614
2615 void radv_DestroyFence(
2616 VkDevice _device,
2617 VkFence _fence,
2618 const VkAllocationCallbacks* pAllocator)
2619 {
2620 RADV_FROM_HANDLE(radv_device, device, _device);
2621 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2622
2623 if (!fence)
2624 return;
2625 device->ws->destroy_fence(fence->fence);
2626 vk_free2(&device->alloc, pAllocator, fence);
2627 }
2628
2629 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2630 {
2631 uint64_t current_time;
2632 struct timespec tv;
2633
2634 clock_gettime(CLOCK_MONOTONIC, &tv);
2635 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2636
2637 timeout = MIN2(UINT64_MAX - current_time, timeout);
2638
2639 return current_time + timeout;
2640 }
2641
2642 VkResult radv_WaitForFences(
2643 VkDevice _device,
2644 uint32_t fenceCount,
2645 const VkFence* pFences,
2646 VkBool32 waitAll,
2647 uint64_t timeout)
2648 {
2649 RADV_FROM_HANDLE(radv_device, device, _device);
2650 timeout = radv_get_absolute_timeout(timeout);
2651
2652 if (!waitAll && fenceCount > 1) {
2653 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2654 }
2655
2656 for (uint32_t i = 0; i < fenceCount; ++i) {
2657 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2658 bool expired = false;
2659
2660 if (fence->signalled)
2661 continue;
2662
2663 if (!fence->submitted)
2664 return VK_TIMEOUT;
2665
2666 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2667 if (!expired)
2668 return VK_TIMEOUT;
2669
2670 fence->signalled = true;
2671 }
2672
2673 return VK_SUCCESS;
2674 }
2675
2676 VkResult radv_ResetFences(VkDevice device,
2677 uint32_t fenceCount,
2678 const VkFence *pFences)
2679 {
2680 for (unsigned i = 0; i < fenceCount; ++i) {
2681 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2682 fence->submitted = fence->signalled = false;
2683 }
2684
2685 return VK_SUCCESS;
2686 }
2687
2688 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2689 {
2690 RADV_FROM_HANDLE(radv_device, device, _device);
2691 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2692
2693 if (fence->signalled)
2694 return VK_SUCCESS;
2695 if (!fence->submitted)
2696 return VK_NOT_READY;
2697
2698 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2699 return VK_NOT_READY;
2700
2701 return VK_SUCCESS;
2702 }
2703
2704
2705 // Queue semaphore functions
2706
2707 VkResult radv_CreateSemaphore(
2708 VkDevice _device,
2709 const VkSemaphoreCreateInfo* pCreateInfo,
2710 const VkAllocationCallbacks* pAllocator,
2711 VkSemaphore* pSemaphore)
2712 {
2713 RADV_FROM_HANDLE(radv_device, device, _device);
2714 const VkExportSemaphoreCreateInfoKHR *export =
2715 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2716 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2717 export ? export->handleTypes : 0;
2718
2719 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2720 sizeof(*sem), 8,
2721 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2722 if (!sem)
2723 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2724
2725 sem->temp_syncobj = 0;
2726 /* create a syncobject if we are going to export this semaphore */
2727 if (handleTypes) {
2728 assert (device->physical_device->rad_info.has_syncobj);
2729 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2730 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2731 if (ret) {
2732 vk_free2(&device->alloc, pAllocator, sem);
2733 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2734 }
2735 sem->sem = NULL;
2736 } else {
2737 sem->sem = device->ws->create_sem(device->ws);
2738 if (!sem->sem) {
2739 vk_free2(&device->alloc, pAllocator, sem);
2740 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2741 }
2742 sem->syncobj = 0;
2743 }
2744
2745 *pSemaphore = radv_semaphore_to_handle(sem);
2746 return VK_SUCCESS;
2747 }
2748
2749 void radv_DestroySemaphore(
2750 VkDevice _device,
2751 VkSemaphore _semaphore,
2752 const VkAllocationCallbacks* pAllocator)
2753 {
2754 RADV_FROM_HANDLE(radv_device, device, _device);
2755 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2756 if (!_semaphore)
2757 return;
2758
2759 if (sem->syncobj)
2760 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2761 else
2762 device->ws->destroy_sem(sem->sem);
2763 vk_free2(&device->alloc, pAllocator, sem);
2764 }
2765
2766 VkResult radv_CreateEvent(
2767 VkDevice _device,
2768 const VkEventCreateInfo* pCreateInfo,
2769 const VkAllocationCallbacks* pAllocator,
2770 VkEvent* pEvent)
2771 {
2772 RADV_FROM_HANDLE(radv_device, device, _device);
2773 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2774 sizeof(*event), 8,
2775 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2776
2777 if (!event)
2778 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2779
2780 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2781 RADEON_DOMAIN_GTT,
2782 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2783 if (!event->bo) {
2784 vk_free2(&device->alloc, pAllocator, event);
2785 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2786 }
2787
2788 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2789
2790 *pEvent = radv_event_to_handle(event);
2791
2792 return VK_SUCCESS;
2793 }
2794
2795 void radv_DestroyEvent(
2796 VkDevice _device,
2797 VkEvent _event,
2798 const VkAllocationCallbacks* pAllocator)
2799 {
2800 RADV_FROM_HANDLE(radv_device, device, _device);
2801 RADV_FROM_HANDLE(radv_event, event, _event);
2802
2803 if (!event)
2804 return;
2805 device->ws->buffer_destroy(event->bo);
2806 vk_free2(&device->alloc, pAllocator, event);
2807 }
2808
2809 VkResult radv_GetEventStatus(
2810 VkDevice _device,
2811 VkEvent _event)
2812 {
2813 RADV_FROM_HANDLE(radv_event, event, _event);
2814
2815 if (*event->map == 1)
2816 return VK_EVENT_SET;
2817 return VK_EVENT_RESET;
2818 }
2819
2820 VkResult radv_SetEvent(
2821 VkDevice _device,
2822 VkEvent _event)
2823 {
2824 RADV_FROM_HANDLE(radv_event, event, _event);
2825 *event->map = 1;
2826
2827 return VK_SUCCESS;
2828 }
2829
2830 VkResult radv_ResetEvent(
2831 VkDevice _device,
2832 VkEvent _event)
2833 {
2834 RADV_FROM_HANDLE(radv_event, event, _event);
2835 *event->map = 0;
2836
2837 return VK_SUCCESS;
2838 }
2839
2840 VkResult radv_CreateBuffer(
2841 VkDevice _device,
2842 const VkBufferCreateInfo* pCreateInfo,
2843 const VkAllocationCallbacks* pAllocator,
2844 VkBuffer* pBuffer)
2845 {
2846 RADV_FROM_HANDLE(radv_device, device, _device);
2847 struct radv_buffer *buffer;
2848
2849 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2850
2851 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2852 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2853 if (buffer == NULL)
2854 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2855
2856 buffer->size = pCreateInfo->size;
2857 buffer->usage = pCreateInfo->usage;
2858 buffer->bo = NULL;
2859 buffer->offset = 0;
2860 buffer->flags = pCreateInfo->flags;
2861
2862 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2863 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2864
2865 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2866 buffer->bo = device->ws->buffer_create(device->ws,
2867 align64(buffer->size, 4096),
2868 4096, 0, RADEON_FLAG_VIRTUAL);
2869 if (!buffer->bo) {
2870 vk_free2(&device->alloc, pAllocator, buffer);
2871 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2872 }
2873 }
2874
2875 *pBuffer = radv_buffer_to_handle(buffer);
2876
2877 return VK_SUCCESS;
2878 }
2879
2880 void radv_DestroyBuffer(
2881 VkDevice _device,
2882 VkBuffer _buffer,
2883 const VkAllocationCallbacks* pAllocator)
2884 {
2885 RADV_FROM_HANDLE(radv_device, device, _device);
2886 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2887
2888 if (!buffer)
2889 return;
2890
2891 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2892 device->ws->buffer_destroy(buffer->bo);
2893
2894 vk_free2(&device->alloc, pAllocator, buffer);
2895 }
2896
2897 static inline unsigned
2898 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2899 {
2900 if (stencil)
2901 return image->surface.u.legacy.stencil_tiling_index[level];
2902 else
2903 return image->surface.u.legacy.tiling_index[level];
2904 }
2905
2906 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2907 {
2908 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2909 }
2910
2911 static void
2912 radv_initialise_color_surface(struct radv_device *device,
2913 struct radv_color_buffer_info *cb,
2914 struct radv_image_view *iview)
2915 {
2916 const struct vk_format_description *desc;
2917 unsigned ntype, format, swap, endian;
2918 unsigned blend_clamp = 0, blend_bypass = 0;
2919 uint64_t va;
2920 const struct radeon_surf *surf = &iview->image->surface;
2921
2922 desc = vk_format_description(iview->vk_format);
2923
2924 memset(cb, 0, sizeof(*cb));
2925
2926 /* Intensity is implemented as Red, so treat it that way. */
2927 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2928
2929 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2930
2931 cb->cb_color_base = va >> 8;
2932
2933 if (device->physical_device->rad_info.chip_class >= GFX9) {
2934 struct gfx9_surf_meta_flags meta;
2935 if (iview->image->dcc_offset)
2936 meta = iview->image->surface.u.gfx9.dcc;
2937 else
2938 meta = iview->image->surface.u.gfx9.cmask;
2939
2940 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2941 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2942 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2943 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2944
2945 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2946 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2947 } else {
2948 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2949 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2950
2951 cb->cb_color_base += level_info->offset >> 8;
2952 if (level_info->mode == RADEON_SURF_MODE_2D)
2953 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2954
2955 pitch_tile_max = level_info->nblk_x / 8 - 1;
2956 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2957 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2958
2959 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2960 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2961 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2962
2963 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2964
2965 if (iview->image->fmask.size) {
2966 if (device->physical_device->rad_info.chip_class >= CIK)
2967 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2968 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2969 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2970 } else {
2971 /* This must be set for fast clear to work without FMASK. */
2972 if (device->physical_device->rad_info.chip_class >= CIK)
2973 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2974 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2975 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2976 }
2977 }
2978
2979 /* CMASK variables */
2980 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2981 va += iview->image->cmask.offset;
2982 cb->cb_color_cmask = va >> 8;
2983
2984 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2985 va += iview->image->dcc_offset;
2986 cb->cb_dcc_base = va >> 8;
2987 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2988
2989 uint32_t max_slice = radv_surface_layer_count(iview);
2990 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2991 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2992
2993 if (iview->image->info.samples > 1) {
2994 unsigned log_samples = util_logbase2(iview->image->info.samples);
2995
2996 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2997 S_028C74_NUM_FRAGMENTS(log_samples);
2998 }
2999
3000 if (iview->image->fmask.size) {
3001 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3002 cb->cb_color_fmask = va >> 8;
3003 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3004 } else {
3005 cb->cb_color_fmask = cb->cb_color_base;
3006 }
3007
3008 ntype = radv_translate_color_numformat(iview->vk_format,
3009 desc,
3010 vk_format_get_first_non_void_channel(iview->vk_format));
3011 format = radv_translate_colorformat(iview->vk_format);
3012 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3013 radv_finishme("Illegal color\n");
3014 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3015 endian = radv_colorformat_endian_swap(format);
3016
3017 /* blend clamp should be set for all NORM/SRGB types */
3018 if (ntype == V_028C70_NUMBER_UNORM ||
3019 ntype == V_028C70_NUMBER_SNORM ||
3020 ntype == V_028C70_NUMBER_SRGB)
3021 blend_clamp = 1;
3022
3023 /* set blend bypass according to docs if SINT/UINT or
3024 8/24 COLOR variants */
3025 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3026 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3027 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3028 blend_clamp = 0;
3029 blend_bypass = 1;
3030 }
3031 #if 0
3032 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3033 (format == V_028C70_COLOR_8 ||
3034 format == V_028C70_COLOR_8_8 ||
3035 format == V_028C70_COLOR_8_8_8_8))
3036 ->color_is_int8 = true;
3037 #endif
3038 cb->cb_color_info = S_028C70_FORMAT(format) |
3039 S_028C70_COMP_SWAP(swap) |
3040 S_028C70_BLEND_CLAMP(blend_clamp) |
3041 S_028C70_BLEND_BYPASS(blend_bypass) |
3042 S_028C70_SIMPLE_FLOAT(1) |
3043 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3044 ntype != V_028C70_NUMBER_SNORM &&
3045 ntype != V_028C70_NUMBER_SRGB &&
3046 format != V_028C70_COLOR_8_24 &&
3047 format != V_028C70_COLOR_24_8) |
3048 S_028C70_NUMBER_TYPE(ntype) |
3049 S_028C70_ENDIAN(endian);
3050 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3051 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3052 if (device->physical_device->rad_info.chip_class == SI) {
3053 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3054 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3055 }
3056 }
3057
3058 if (iview->image->cmask.size &&
3059 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3060 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3061
3062 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3063 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3064
3065 if (device->physical_device->rad_info.chip_class >= VI) {
3066 unsigned max_uncompressed_block_size = 2;
3067 if (iview->image->info.samples > 1) {
3068 if (iview->image->surface.bpe == 1)
3069 max_uncompressed_block_size = 0;
3070 else if (iview->image->surface.bpe == 2)
3071 max_uncompressed_block_size = 1;
3072 }
3073
3074 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3075 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3076 }
3077
3078 /* This must be set for fast clear to work without FMASK. */
3079 if (!iview->image->fmask.size &&
3080 device->physical_device->rad_info.chip_class == SI) {
3081 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3082 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3083 }
3084
3085 if (device->physical_device->rad_info.chip_class >= GFX9) {
3086 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3087 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3088
3089 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3090 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3091 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3092 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3093 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3094 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3095 }
3096 }
3097
3098 static void
3099 radv_initialise_ds_surface(struct radv_device *device,
3100 struct radv_ds_buffer_info *ds,
3101 struct radv_image_view *iview)
3102 {
3103 unsigned level = iview->base_mip;
3104 unsigned format, stencil_format;
3105 uint64_t va, s_offs, z_offs;
3106 bool stencil_only = false;
3107 memset(ds, 0, sizeof(*ds));
3108 switch (iview->image->vk_format) {
3109 case VK_FORMAT_D24_UNORM_S8_UINT:
3110 case VK_FORMAT_X8_D24_UNORM_PACK32:
3111 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3112 ds->offset_scale = 2.0f;
3113 break;
3114 case VK_FORMAT_D16_UNORM:
3115 case VK_FORMAT_D16_UNORM_S8_UINT:
3116 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3117 ds->offset_scale = 4.0f;
3118 break;
3119 case VK_FORMAT_D32_SFLOAT:
3120 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3121 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3122 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3123 ds->offset_scale = 1.0f;
3124 break;
3125 case VK_FORMAT_S8_UINT:
3126 stencil_only = true;
3127 break;
3128 default:
3129 break;
3130 }
3131
3132 format = radv_translate_dbformat(iview->image->vk_format);
3133 stencil_format = iview->image->surface.has_stencil ?
3134 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3135
3136 uint32_t max_slice = radv_surface_layer_count(iview);
3137 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3138 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3139
3140 ds->db_htile_data_base = 0;
3141 ds->db_htile_surface = 0;
3142
3143 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3144 s_offs = z_offs = va;
3145
3146 if (device->physical_device->rad_info.chip_class >= GFX9) {
3147 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3148 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3149
3150 ds->db_z_info = S_028038_FORMAT(format) |
3151 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3152 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3153 S_028038_MAXMIP(iview->image->info.levels - 1);
3154 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3155 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3156
3157 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3158 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3159 ds->db_depth_view |= S_028008_MIPID(level);
3160
3161 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3162 S_02801C_Y_MAX(iview->image->info.height - 1);
3163
3164 if (radv_htile_enabled(iview->image, level)) {
3165 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3166
3167 if (iview->image->tc_compatible_htile) {
3168 unsigned max_zplanes = 4;
3169
3170 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3171 iview->image->info.samples > 1)
3172 max_zplanes = 2;
3173
3174 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3175 S_028038_ITERATE_FLUSH(1);
3176 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3177 }
3178
3179 if (!iview->image->surface.has_stencil)
3180 /* Use all of the htile_buffer for depth if there's no stencil. */
3181 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3182 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3183 iview->image->htile_offset;
3184 ds->db_htile_data_base = va >> 8;
3185 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3186 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3187 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3188 }
3189 } else {
3190 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3191
3192 if (stencil_only)
3193 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3194
3195 z_offs += iview->image->surface.u.legacy.level[level].offset;
3196 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3197
3198 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3199 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3200 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3201
3202 if (iview->image->info.samples > 1)
3203 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3204
3205 if (device->physical_device->rad_info.chip_class >= CIK) {
3206 struct radeon_info *info = &device->physical_device->rad_info;
3207 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3208 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3209 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3210 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3211 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3212 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3213
3214 if (stencil_only)
3215 tile_mode = stencil_tile_mode;
3216
3217 ds->db_depth_info |=
3218 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3219 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3220 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3221 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3222 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3223 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3224 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3225 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3226 } else {
3227 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3228 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3229 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3230 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3231 if (stencil_only)
3232 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3233 }
3234
3235 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3236 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3237 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3238
3239 if (radv_htile_enabled(iview->image, level)) {
3240 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3241
3242 if (!iview->image->surface.has_stencil &&
3243 !iview->image->tc_compatible_htile)
3244 /* Use all of the htile_buffer for depth if there's no stencil. */
3245 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3246
3247 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3248 iview->image->htile_offset;
3249 ds->db_htile_data_base = va >> 8;
3250 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3251
3252 if (iview->image->tc_compatible_htile) {
3253 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3254
3255 if (iview->image->info.samples <= 1)
3256 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3257 else if (iview->image->info.samples <= 4)
3258 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3259 else
3260 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3261 }
3262 }
3263 }
3264
3265 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3266 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3267 }
3268
3269 VkResult radv_CreateFramebuffer(
3270 VkDevice _device,
3271 const VkFramebufferCreateInfo* pCreateInfo,
3272 const VkAllocationCallbacks* pAllocator,
3273 VkFramebuffer* pFramebuffer)
3274 {
3275 RADV_FROM_HANDLE(radv_device, device, _device);
3276 struct radv_framebuffer *framebuffer;
3277
3278 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3279
3280 size_t size = sizeof(*framebuffer) +
3281 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3282 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3283 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3284 if (framebuffer == NULL)
3285 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3286
3287 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3288 framebuffer->width = pCreateInfo->width;
3289 framebuffer->height = pCreateInfo->height;
3290 framebuffer->layers = pCreateInfo->layers;
3291 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3292 VkImageView _iview = pCreateInfo->pAttachments[i];
3293 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3294 framebuffer->attachments[i].attachment = iview;
3295 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3296 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3297 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3298 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3299 }
3300 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3301 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3302 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3303 }
3304
3305 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3306 return VK_SUCCESS;
3307 }
3308
3309 void radv_DestroyFramebuffer(
3310 VkDevice _device,
3311 VkFramebuffer _fb,
3312 const VkAllocationCallbacks* pAllocator)
3313 {
3314 RADV_FROM_HANDLE(radv_device, device, _device);
3315 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3316
3317 if (!fb)
3318 return;
3319 vk_free2(&device->alloc, pAllocator, fb);
3320 }
3321
3322 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3323 {
3324 switch (address_mode) {
3325 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3326 return V_008F30_SQ_TEX_WRAP;
3327 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3328 return V_008F30_SQ_TEX_MIRROR;
3329 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3330 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3331 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3332 return V_008F30_SQ_TEX_CLAMP_BORDER;
3333 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3334 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3335 default:
3336 unreachable("illegal tex wrap mode");
3337 break;
3338 }
3339 }
3340
3341 static unsigned
3342 radv_tex_compare(VkCompareOp op)
3343 {
3344 switch (op) {
3345 case VK_COMPARE_OP_NEVER:
3346 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3347 case VK_COMPARE_OP_LESS:
3348 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3349 case VK_COMPARE_OP_EQUAL:
3350 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3351 case VK_COMPARE_OP_LESS_OR_EQUAL:
3352 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3353 case VK_COMPARE_OP_GREATER:
3354 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3355 case VK_COMPARE_OP_NOT_EQUAL:
3356 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3357 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3358 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3359 case VK_COMPARE_OP_ALWAYS:
3360 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3361 default:
3362 unreachable("illegal compare mode");
3363 break;
3364 }
3365 }
3366
3367 static unsigned
3368 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3369 {
3370 switch (filter) {
3371 case VK_FILTER_NEAREST:
3372 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3373 V_008F38_SQ_TEX_XY_FILTER_POINT);
3374 case VK_FILTER_LINEAR:
3375 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3376 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3377 case VK_FILTER_CUBIC_IMG:
3378 default:
3379 fprintf(stderr, "illegal texture filter");
3380 return 0;
3381 }
3382 }
3383
3384 static unsigned
3385 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3386 {
3387 switch (mode) {
3388 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3389 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3390 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3391 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3392 default:
3393 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3394 }
3395 }
3396
3397 static unsigned
3398 radv_tex_bordercolor(VkBorderColor bcolor)
3399 {
3400 switch (bcolor) {
3401 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3402 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3403 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3404 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3405 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3406 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3407 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3408 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3409 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3410 default:
3411 break;
3412 }
3413 return 0;
3414 }
3415
3416 static unsigned
3417 radv_tex_aniso_filter(unsigned filter)
3418 {
3419 if (filter < 2)
3420 return 0;
3421 if (filter < 4)
3422 return 1;
3423 if (filter < 8)
3424 return 2;
3425 if (filter < 16)
3426 return 3;
3427 return 4;
3428 }
3429
3430 static void
3431 radv_init_sampler(struct radv_device *device,
3432 struct radv_sampler *sampler,
3433 const VkSamplerCreateInfo *pCreateInfo)
3434 {
3435 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3436 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3437 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3438 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3439
3440 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3441 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3442 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3443 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3444 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3445 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3446 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3447 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3448 S_008F30_DISABLE_CUBE_WRAP(0) |
3449 S_008F30_COMPAT_MODE(is_vi));
3450 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3451 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3452 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3453 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3454 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3455 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3456 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3457 S_008F38_MIP_POINT_PRECLAMP(0) |
3458 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3459 S_008F38_FILTER_PREC_FIX(1) |
3460 S_008F38_ANISO_OVERRIDE(is_vi));
3461 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3462 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3463 }
3464
3465 VkResult radv_CreateSampler(
3466 VkDevice _device,
3467 const VkSamplerCreateInfo* pCreateInfo,
3468 const VkAllocationCallbacks* pAllocator,
3469 VkSampler* pSampler)
3470 {
3471 RADV_FROM_HANDLE(radv_device, device, _device);
3472 struct radv_sampler *sampler;
3473
3474 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3475
3476 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3477 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3478 if (!sampler)
3479 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3480
3481 radv_init_sampler(device, sampler, pCreateInfo);
3482 *pSampler = radv_sampler_to_handle(sampler);
3483
3484 return VK_SUCCESS;
3485 }
3486
3487 void radv_DestroySampler(
3488 VkDevice _device,
3489 VkSampler _sampler,
3490 const VkAllocationCallbacks* pAllocator)
3491 {
3492 RADV_FROM_HANDLE(radv_device, device, _device);
3493 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3494
3495 if (!sampler)
3496 return;
3497 vk_free2(&device->alloc, pAllocator, sampler);
3498 }
3499
3500 /* vk_icd.h does not declare this function, so we declare it here to
3501 * suppress Wmissing-prototypes.
3502 */
3503 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3504 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3505
3506 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3507 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3508 {
3509 /* For the full details on loader interface versioning, see
3510 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3511 * What follows is a condensed summary, to help you navigate the large and
3512 * confusing official doc.
3513 *
3514 * - Loader interface v0 is incompatible with later versions. We don't
3515 * support it.
3516 *
3517 * - In loader interface v1:
3518 * - The first ICD entrypoint called by the loader is
3519 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3520 * entrypoint.
3521 * - The ICD must statically expose no other Vulkan symbol unless it is
3522 * linked with -Bsymbolic.
3523 * - Each dispatchable Vulkan handle created by the ICD must be
3524 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3525 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3526 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3527 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3528 * such loader-managed surfaces.
3529 *
3530 * - Loader interface v2 differs from v1 in:
3531 * - The first ICD entrypoint called by the loader is
3532 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3533 * statically expose this entrypoint.
3534 *
3535 * - Loader interface v3 differs from v2 in:
3536 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3537 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3538 * because the loader no longer does so.
3539 */
3540 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3541 return VK_SUCCESS;
3542 }
3543
3544 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3545 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3546 int *pFD)
3547 {
3548 RADV_FROM_HANDLE(radv_device, device, _device);
3549 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3550
3551 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3552
3553 /* At the moment, we support only the below handle types. */
3554 assert(pGetFdInfo->handleType ==
3555 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3556 pGetFdInfo->handleType ==
3557 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3558
3559 bool ret = radv_get_memory_fd(device, memory, pFD);
3560 if (ret == false)
3561 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3562 return VK_SUCCESS;
3563 }
3564
3565 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3566 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3567 int fd,
3568 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3569 {
3570 switch (handleType) {
3571 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3572 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3573 return VK_SUCCESS;
3574
3575 default:
3576 /* The valid usage section for this function says:
3577 *
3578 * "handleType must not be one of the handle types defined as
3579 * opaque."
3580 *
3581 * So opaque handle types fall into the default "unsupported" case.
3582 */
3583 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3584 }
3585 }
3586
3587 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3588 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3592 uint32_t syncobj_handle = 0;
3593 uint32_t *syncobj_dst = NULL;
3594 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3595
3596 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3597 if (ret != 0)
3598 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3599
3600 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3601 syncobj_dst = &sem->temp_syncobj;
3602 } else {
3603 syncobj_dst = &sem->syncobj;
3604 }
3605
3606 if (*syncobj_dst)
3607 device->ws->destroy_syncobj(device->ws, *syncobj_dst);
3608
3609 *syncobj_dst = syncobj_handle;
3610 close(pImportSemaphoreFdInfo->fd);
3611 return VK_SUCCESS;
3612 }
3613
3614 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3615 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3616 int *pFd)
3617 {
3618 RADV_FROM_HANDLE(radv_device, device, _device);
3619 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3620 int ret;
3621 uint32_t syncobj_handle;
3622
3623 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3624 if (sem->temp_syncobj)
3625 syncobj_handle = sem->temp_syncobj;
3626 else
3627 syncobj_handle = sem->syncobj;
3628 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3629 if (ret)
3630 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3631 return VK_SUCCESS;
3632 }
3633
3634 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3635 VkPhysicalDevice physicalDevice,
3636 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3637 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3638 {
3639 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3640 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3641 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3642 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3643 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3644 } else {
3645 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3646 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3647 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3648 }
3649 }