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[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const char *
80 get_chip_name(enum radeon_family family)
81 {
82 switch (family) {
83 case CHIP_TAHITI: return "AMD RADV TAHITI";
84 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
85 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
86 case CHIP_OLAND: return "AMD RADV OLAND";
87 case CHIP_HAINAN: return "AMD RADV HAINAN";
88 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
89 case CHIP_KAVERI: return "AMD RADV KAVERI";
90 case CHIP_KABINI: return "AMD RADV KABINI";
91 case CHIP_HAWAII: return "AMD RADV HAWAII";
92 case CHIP_MULLINS: return "AMD RADV MULLINS";
93 case CHIP_TONGA: return "AMD RADV TONGA";
94 case CHIP_ICELAND: return "AMD RADV ICELAND";
95 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
96 case CHIP_FIJI: return "AMD RADV FIJI";
97 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
98 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
99 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
100 case CHIP_STONEY: return "AMD RADV STONEY";
101 case CHIP_VEGA10: return "AMD RADV VEGA";
102 case CHIP_RAVEN: return "AMD RADV RAVEN";
103 default: return "AMD RADV unknown";
104 }
105 }
106
107 static VkResult
108 radv_physical_device_init(struct radv_physical_device *device,
109 struct radv_instance *instance,
110 drmDevicePtr drm_device)
111 {
112 const char *path = drm_device->nodes[DRM_NODE_RENDER];
113 VkResult result;
114 drmVersionPtr version;
115 int fd;
116
117 fd = open(path, O_RDWR | O_CLOEXEC);
118 if (fd < 0)
119 return VK_ERROR_INCOMPATIBLE_DRIVER;
120
121 version = drmGetVersion(fd);
122 if (!version) {
123 close(fd);
124 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
125 "failed to get version %s: %m", path);
126 }
127
128 if (strcmp(version->name, "amdgpu")) {
129 drmFreeVersion(version);
130 close(fd);
131 return VK_ERROR_INCOMPATIBLE_DRIVER;
132 }
133 drmFreeVersion(version);
134
135 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
136 device->instance = instance;
137 assert(strlen(path) < ARRAY_SIZE(device->path));
138 strncpy(device->path, path, ARRAY_SIZE(device->path));
139
140 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
141 instance->perftest_flags);
142 if (!device->ws) {
143 result = VK_ERROR_INCOMPATIBLE_DRIVER;
144 goto fail;
145 }
146
147 device->local_fd = fd;
148 device->ws->query_info(device->ws, &device->rad_info);
149 result = radv_init_wsi(device);
150 if (result != VK_SUCCESS) {
151 device->ws->destroy(device->ws);
152 goto fail;
153 }
154
155 device->name = get_chip_name(device->rad_info.family);
156
157 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
158 radv_finish_wsi(device);
159 device->ws->destroy(device->ws);
160 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
161 "cannot generate UUID");
162 goto fail;
163 }
164
165 /* These flags affect shader compilation. */
166 uint64_t shader_env_flags =
167 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
168 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
169
170 /* The gpu id is already embeded in the uuid so we just pass "radv"
171 * when creating the cache.
172 */
173 char buf[VK_UUID_SIZE * 2 + 1];
174 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
175 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
176
177 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
178
179 radv_get_driver_uuid(&device->device_uuid);
180 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
181
182 if (device->rad_info.family == CHIP_STONEY ||
183 device->rad_info.chip_class >= GFX9) {
184 device->has_rbplus = true;
185 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
186 }
187
188 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
189 * on SI.
190 */
191 device->has_clear_state = device->rad_info.chip_class >= CIK;
192
193 return VK_SUCCESS;
194
195 fail:
196 close(fd);
197 return result;
198 }
199
200 static void
201 radv_physical_device_finish(struct radv_physical_device *device)
202 {
203 radv_finish_wsi(device);
204 device->ws->destroy(device->ws);
205 disk_cache_destroy(device->disk_cache);
206 close(device->local_fd);
207 }
208
209 static void *
210 default_alloc_func(void *pUserData, size_t size, size_t align,
211 VkSystemAllocationScope allocationScope)
212 {
213 return malloc(size);
214 }
215
216 static void *
217 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
218 size_t align, VkSystemAllocationScope allocationScope)
219 {
220 return realloc(pOriginal, size);
221 }
222
223 static void
224 default_free_func(void *pUserData, void *pMemory)
225 {
226 free(pMemory);
227 }
228
229 static const VkAllocationCallbacks default_alloc = {
230 .pUserData = NULL,
231 .pfnAllocation = default_alloc_func,
232 .pfnReallocation = default_realloc_func,
233 .pfnFree = default_free_func,
234 };
235
236 static const struct debug_control radv_debug_options[] = {
237 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
238 {"nodcc", RADV_DEBUG_NO_DCC},
239 {"shaders", RADV_DEBUG_DUMP_SHADERS},
240 {"nocache", RADV_DEBUG_NO_CACHE},
241 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
242 {"nohiz", RADV_DEBUG_NO_HIZ},
243 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
244 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
245 {"allbos", RADV_DEBUG_ALL_BOS},
246 {"noibs", RADV_DEBUG_NO_IBS},
247 {"spirv", RADV_DEBUG_DUMP_SPIRV},
248 {"vmfaults", RADV_DEBUG_VM_FAULTS},
249 {"zerovram", RADV_DEBUG_ZERO_VRAM},
250 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
251 {NULL, 0}
252 };
253
254 const char *
255 radv_get_debug_option_name(int id)
256 {
257 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
258 return radv_debug_options[id].string;
259 }
260
261 static const struct debug_control radv_perftest_options[] = {
262 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
263 {"sisched", RADV_PERFTEST_SISCHED},
264 {NULL, 0}
265 };
266
267 const char *
268 radv_get_perftest_option_name(int id)
269 {
270 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
271 return radv_perftest_options[id].string;
272 }
273
274 VkResult radv_CreateInstance(
275 const VkInstanceCreateInfo* pCreateInfo,
276 const VkAllocationCallbacks* pAllocator,
277 VkInstance* pInstance)
278 {
279 struct radv_instance *instance;
280
281 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
282
283 uint32_t client_version;
284 if (pCreateInfo->pApplicationInfo &&
285 pCreateInfo->pApplicationInfo->apiVersion != 0) {
286 client_version = pCreateInfo->pApplicationInfo->apiVersion;
287 } else {
288 client_version = VK_MAKE_VERSION(1, 0, 0);
289 }
290
291 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
292 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
293 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
294 "Client requested version %d.%d.%d",
295 VK_VERSION_MAJOR(client_version),
296 VK_VERSION_MINOR(client_version),
297 VK_VERSION_PATCH(client_version));
298 }
299
300 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
301 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
302 if (!radv_instance_extension_supported(ext_name))
303 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
304 }
305
306 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
307 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
308 if (!instance)
309 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
310
311 memset(instance, 0, sizeof(*instance));
312
313 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
314
315 if (pAllocator)
316 instance->alloc = *pAllocator;
317 else
318 instance->alloc = default_alloc;
319
320 instance->apiVersion = client_version;
321 instance->physicalDeviceCount = -1;
322
323 _mesa_locale_init();
324
325 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
326
327 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
328 radv_debug_options);
329
330 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
331 radv_perftest_options);
332
333 *pInstance = radv_instance_to_handle(instance);
334
335 return VK_SUCCESS;
336 }
337
338 void radv_DestroyInstance(
339 VkInstance _instance,
340 const VkAllocationCallbacks* pAllocator)
341 {
342 RADV_FROM_HANDLE(radv_instance, instance, _instance);
343
344 if (!instance)
345 return;
346
347 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
348 radv_physical_device_finish(instance->physicalDevices + i);
349 }
350
351 VG(VALGRIND_DESTROY_MEMPOOL(instance));
352
353 _mesa_locale_fini();
354
355 vk_free(&instance->alloc, instance);
356 }
357
358 static VkResult
359 radv_enumerate_devices(struct radv_instance *instance)
360 {
361 /* TODO: Check for more devices ? */
362 drmDevicePtr devices[8];
363 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
364 int max_devices;
365
366 instance->physicalDeviceCount = 0;
367
368 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
369 if (max_devices < 1)
370 return VK_ERROR_INCOMPATIBLE_DRIVER;
371
372 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
373 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
374 devices[i]->bustype == DRM_BUS_PCI &&
375 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
376
377 result = radv_physical_device_init(instance->physicalDevices +
378 instance->physicalDeviceCount,
379 instance,
380 devices[i]);
381 if (result == VK_SUCCESS)
382 ++instance->physicalDeviceCount;
383 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
384 break;
385 }
386 }
387 drmFreeDevices(devices, max_devices);
388
389 return result;
390 }
391
392 VkResult radv_EnumeratePhysicalDevices(
393 VkInstance _instance,
394 uint32_t* pPhysicalDeviceCount,
395 VkPhysicalDevice* pPhysicalDevices)
396 {
397 RADV_FROM_HANDLE(radv_instance, instance, _instance);
398 VkResult result;
399
400 if (instance->physicalDeviceCount < 0) {
401 result = radv_enumerate_devices(instance);
402 if (result != VK_SUCCESS &&
403 result != VK_ERROR_INCOMPATIBLE_DRIVER)
404 return result;
405 }
406
407 if (!pPhysicalDevices) {
408 *pPhysicalDeviceCount = instance->physicalDeviceCount;
409 } else {
410 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
411 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
412 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
413 }
414
415 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
416 : VK_SUCCESS;
417 }
418
419 void radv_GetPhysicalDeviceFeatures(
420 VkPhysicalDevice physicalDevice,
421 VkPhysicalDeviceFeatures* pFeatures)
422 {
423 memset(pFeatures, 0, sizeof(*pFeatures));
424
425 *pFeatures = (VkPhysicalDeviceFeatures) {
426 .robustBufferAccess = true,
427 .fullDrawIndexUint32 = true,
428 .imageCubeArray = true,
429 .independentBlend = true,
430 .geometryShader = true,
431 .tessellationShader = true,
432 .sampleRateShading = true,
433 .dualSrcBlend = true,
434 .logicOp = true,
435 .multiDrawIndirect = true,
436 .drawIndirectFirstInstance = true,
437 .depthClamp = true,
438 .depthBiasClamp = true,
439 .fillModeNonSolid = true,
440 .depthBounds = true,
441 .wideLines = true,
442 .largePoints = true,
443 .alphaToOne = true,
444 .multiViewport = true,
445 .samplerAnisotropy = true,
446 .textureCompressionETC2 = false,
447 .textureCompressionASTC_LDR = false,
448 .textureCompressionBC = true,
449 .occlusionQueryPrecise = true,
450 .pipelineStatisticsQuery = true,
451 .vertexPipelineStoresAndAtomics = true,
452 .fragmentStoresAndAtomics = true,
453 .shaderTessellationAndGeometryPointSize = true,
454 .shaderImageGatherExtended = true,
455 .shaderStorageImageExtendedFormats = true,
456 .shaderStorageImageMultisample = false,
457 .shaderUniformBufferArrayDynamicIndexing = true,
458 .shaderSampledImageArrayDynamicIndexing = true,
459 .shaderStorageBufferArrayDynamicIndexing = true,
460 .shaderStorageImageArrayDynamicIndexing = true,
461 .shaderStorageImageReadWithoutFormat = true,
462 .shaderStorageImageWriteWithoutFormat = true,
463 .shaderClipDistance = true,
464 .shaderCullDistance = true,
465 .shaderFloat64 = true,
466 .shaderInt64 = true,
467 .shaderInt16 = false,
468 .sparseBinding = true,
469 .variableMultisampleRate = true,
470 .inheritedQueries = true,
471 };
472 }
473
474 void radv_GetPhysicalDeviceFeatures2KHR(
475 VkPhysicalDevice physicalDevice,
476 VkPhysicalDeviceFeatures2KHR *pFeatures)
477 {
478 vk_foreach_struct(ext, pFeatures->pNext) {
479 switch (ext->sType) {
480 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
481 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
482 features->variablePointersStorageBuffer = true;
483 features->variablePointers = false;
484 break;
485 }
486 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
487 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
488 features->multiview = true;
489 features->multiviewGeometryShader = true;
490 features->multiviewTessellationShader = true;
491 break;
492 }
493 default:
494 break;
495 }
496 }
497 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
498 }
499
500 void radv_GetPhysicalDeviceProperties(
501 VkPhysicalDevice physicalDevice,
502 VkPhysicalDeviceProperties* pProperties)
503 {
504 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
505 VkSampleCountFlags sample_counts = 0xf;
506
507 /* make sure that the entire descriptor set is addressable with a signed
508 * 32-bit int. So the sum of all limits scaled by descriptor size has to
509 * be at most 2 GiB. the combined image & samples object count as one of
510 * both. This limit is for the pipeline layout, not for the set layout, but
511 * there is no set limit, so we just set a pipeline limit. I don't think
512 * any app is going to hit this soon. */
513 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
514 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
515 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
516 32 /* sampler, largest when combined with image */ +
517 64 /* sampled image */ +
518 64 /* storage image */);
519
520 VkPhysicalDeviceLimits limits = {
521 .maxImageDimension1D = (1 << 14),
522 .maxImageDimension2D = (1 << 14),
523 .maxImageDimension3D = (1 << 11),
524 .maxImageDimensionCube = (1 << 14),
525 .maxImageArrayLayers = (1 << 11),
526 .maxTexelBufferElements = 128 * 1024 * 1024,
527 .maxUniformBufferRange = UINT32_MAX,
528 .maxStorageBufferRange = UINT32_MAX,
529 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
530 .maxMemoryAllocationCount = UINT32_MAX,
531 .maxSamplerAllocationCount = 64 * 1024,
532 .bufferImageGranularity = 64, /* A cache line */
533 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
534 .maxBoundDescriptorSets = MAX_SETS,
535 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
536 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
537 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
538 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
539 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
540 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
541 .maxPerStageResources = max_descriptor_set_size,
542 .maxDescriptorSetSamplers = max_descriptor_set_size,
543 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
544 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
545 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
546 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
547 .maxDescriptorSetSampledImages = max_descriptor_set_size,
548 .maxDescriptorSetStorageImages = max_descriptor_set_size,
549 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
550 .maxVertexInputAttributes = 32,
551 .maxVertexInputBindings = 32,
552 .maxVertexInputAttributeOffset = 2047,
553 .maxVertexInputBindingStride = 2048,
554 .maxVertexOutputComponents = 128,
555 .maxTessellationGenerationLevel = 64,
556 .maxTessellationPatchSize = 32,
557 .maxTessellationControlPerVertexInputComponents = 128,
558 .maxTessellationControlPerVertexOutputComponents = 128,
559 .maxTessellationControlPerPatchOutputComponents = 120,
560 .maxTessellationControlTotalOutputComponents = 4096,
561 .maxTessellationEvaluationInputComponents = 128,
562 .maxTessellationEvaluationOutputComponents = 128,
563 .maxGeometryShaderInvocations = 127,
564 .maxGeometryInputComponents = 64,
565 .maxGeometryOutputComponents = 128,
566 .maxGeometryOutputVertices = 256,
567 .maxGeometryTotalOutputComponents = 1024,
568 .maxFragmentInputComponents = 128,
569 .maxFragmentOutputAttachments = 8,
570 .maxFragmentDualSrcAttachments = 1,
571 .maxFragmentCombinedOutputResources = 8,
572 .maxComputeSharedMemorySize = 32768,
573 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
574 .maxComputeWorkGroupInvocations = 2048,
575 .maxComputeWorkGroupSize = {
576 2048,
577 2048,
578 2048
579 },
580 .subPixelPrecisionBits = 4 /* FIXME */,
581 .subTexelPrecisionBits = 4 /* FIXME */,
582 .mipmapPrecisionBits = 4 /* FIXME */,
583 .maxDrawIndexedIndexValue = UINT32_MAX,
584 .maxDrawIndirectCount = UINT32_MAX,
585 .maxSamplerLodBias = 16,
586 .maxSamplerAnisotropy = 16,
587 .maxViewports = MAX_VIEWPORTS,
588 .maxViewportDimensions = { (1 << 14), (1 << 14) },
589 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
590 .viewportSubPixelBits = 13, /* We take a float? */
591 .minMemoryMapAlignment = 4096, /* A page */
592 .minTexelBufferOffsetAlignment = 1,
593 .minUniformBufferOffsetAlignment = 4,
594 .minStorageBufferOffsetAlignment = 4,
595 .minTexelOffset = -32,
596 .maxTexelOffset = 31,
597 .minTexelGatherOffset = -32,
598 .maxTexelGatherOffset = 31,
599 .minInterpolationOffset = -2,
600 .maxInterpolationOffset = 2,
601 .subPixelInterpolationOffsetBits = 8,
602 .maxFramebufferWidth = (1 << 14),
603 .maxFramebufferHeight = (1 << 14),
604 .maxFramebufferLayers = (1 << 10),
605 .framebufferColorSampleCounts = sample_counts,
606 .framebufferDepthSampleCounts = sample_counts,
607 .framebufferStencilSampleCounts = sample_counts,
608 .framebufferNoAttachmentsSampleCounts = sample_counts,
609 .maxColorAttachments = MAX_RTS,
610 .sampledImageColorSampleCounts = sample_counts,
611 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
612 .sampledImageDepthSampleCounts = sample_counts,
613 .sampledImageStencilSampleCounts = sample_counts,
614 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
615 .maxSampleMaskWords = 1,
616 .timestampComputeAndGraphics = true,
617 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
618 .maxClipDistances = 8,
619 .maxCullDistances = 8,
620 .maxCombinedClipAndCullDistances = 8,
621 .discreteQueuePriorities = 1,
622 .pointSizeRange = { 0.125, 255.875 },
623 .lineWidthRange = { 0.0, 7.9921875 },
624 .pointSizeGranularity = (1.0 / 8.0),
625 .lineWidthGranularity = (1.0 / 128.0),
626 .strictLines = false, /* FINISHME */
627 .standardSampleLocations = true,
628 .optimalBufferCopyOffsetAlignment = 128,
629 .optimalBufferCopyRowPitchAlignment = 128,
630 .nonCoherentAtomSize = 64,
631 };
632
633 *pProperties = (VkPhysicalDeviceProperties) {
634 .apiVersion = radv_physical_device_api_version(pdevice),
635 .driverVersion = vk_get_driver_version(),
636 .vendorID = ATI_VENDOR_ID,
637 .deviceID = pdevice->rad_info.pci_id,
638 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
639 .limits = limits,
640 .sparseProperties = {0},
641 };
642
643 strcpy(pProperties->deviceName, pdevice->name);
644 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
645 }
646
647 void radv_GetPhysicalDeviceProperties2KHR(
648 VkPhysicalDevice physicalDevice,
649 VkPhysicalDeviceProperties2KHR *pProperties)
650 {
651 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
652 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
653
654 vk_foreach_struct(ext, pProperties->pNext) {
655 switch (ext->sType) {
656 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
657 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
658 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
659 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
660 break;
661 }
662 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
663 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
664 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
665 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
666 properties->deviceLUIDValid = false;
667 break;
668 }
669 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
670 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
671 properties->maxMultiviewViewCount = MAX_VIEWS;
672 properties->maxMultiviewInstanceIndex = INT_MAX;
673 break;
674 }
675 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
676 VkPhysicalDevicePointClippingPropertiesKHR *properties =
677 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
678 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
679 break;
680 }
681 default:
682 break;
683 }
684 }
685 }
686
687 static void radv_get_physical_device_queue_family_properties(
688 struct radv_physical_device* pdevice,
689 uint32_t* pCount,
690 VkQueueFamilyProperties** pQueueFamilyProperties)
691 {
692 int num_queue_families = 1;
693 int idx;
694 if (pdevice->rad_info.num_compute_rings > 0 &&
695 pdevice->rad_info.chip_class >= CIK &&
696 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
697 num_queue_families++;
698
699 if (pQueueFamilyProperties == NULL) {
700 *pCount = num_queue_families;
701 return;
702 }
703
704 if (!*pCount)
705 return;
706
707 idx = 0;
708 if (*pCount >= 1) {
709 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
710 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
711 VK_QUEUE_COMPUTE_BIT |
712 VK_QUEUE_TRANSFER_BIT |
713 VK_QUEUE_SPARSE_BINDING_BIT,
714 .queueCount = 1,
715 .timestampValidBits = 64,
716 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
717 };
718 idx++;
719 }
720
721 if (pdevice->rad_info.num_compute_rings > 0 &&
722 pdevice->rad_info.chip_class >= CIK &&
723 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
724 if (*pCount > idx) {
725 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
726 .queueFlags = VK_QUEUE_COMPUTE_BIT |
727 VK_QUEUE_TRANSFER_BIT |
728 VK_QUEUE_SPARSE_BINDING_BIT,
729 .queueCount = pdevice->rad_info.num_compute_rings,
730 .timestampValidBits = 64,
731 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
732 };
733 idx++;
734 }
735 }
736 *pCount = idx;
737 }
738
739 void radv_GetPhysicalDeviceQueueFamilyProperties(
740 VkPhysicalDevice physicalDevice,
741 uint32_t* pCount,
742 VkQueueFamilyProperties* pQueueFamilyProperties)
743 {
744 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
745 if (!pQueueFamilyProperties) {
746 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
747 return;
748 }
749 VkQueueFamilyProperties *properties[] = {
750 pQueueFamilyProperties + 0,
751 pQueueFamilyProperties + 1,
752 pQueueFamilyProperties + 2,
753 };
754 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
755 assert(*pCount <= 3);
756 }
757
758 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
759 VkPhysicalDevice physicalDevice,
760 uint32_t* pCount,
761 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
762 {
763 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
764 if (!pQueueFamilyProperties) {
765 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
766 return;
767 }
768 VkQueueFamilyProperties *properties[] = {
769 &pQueueFamilyProperties[0].queueFamilyProperties,
770 &pQueueFamilyProperties[1].queueFamilyProperties,
771 &pQueueFamilyProperties[2].queueFamilyProperties,
772 };
773 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
774 assert(*pCount <= 3);
775 }
776
777 void radv_GetPhysicalDeviceMemoryProperties(
778 VkPhysicalDevice physicalDevice,
779 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
780 {
781 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
782
783 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
784
785 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
786 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
787 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
788 .heapIndex = RADV_MEM_HEAP_VRAM,
789 };
790 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
791 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
792 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
793 .heapIndex = RADV_MEM_HEAP_GTT,
794 };
795 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
796 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
797 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
798 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
799 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
800 };
801 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
802 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
803 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
804 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
805 .heapIndex = RADV_MEM_HEAP_GTT,
806 };
807
808 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
809 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
810 physical_device->rad_info.vram_vis_size);
811
812 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
813 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
814 .size = physical_device->rad_info.vram_size -
815 visible_vram_size,
816 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
817 };
818 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
819 .size = visible_vram_size,
820 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
821 };
822 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
823 .size = physical_device->rad_info.gart_size,
824 .flags = 0,
825 };
826 }
827
828 void radv_GetPhysicalDeviceMemoryProperties2KHR(
829 VkPhysicalDevice physicalDevice,
830 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
831 {
832 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
833 &pMemoryProperties->memoryProperties);
834 }
835
836 static enum radeon_ctx_priority
837 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
838 {
839 /* Default to MEDIUM when a specific global priority isn't requested */
840 if (!pObj)
841 return RADEON_CTX_PRIORITY_MEDIUM;
842
843 switch(pObj->globalPriority) {
844 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME:
845 return RADEON_CTX_PRIORITY_REALTIME;
846 case VK_QUEUE_GLOBAL_PRIORITY_HIGH:
847 return RADEON_CTX_PRIORITY_HIGH;
848 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM:
849 return RADEON_CTX_PRIORITY_MEDIUM;
850 case VK_QUEUE_GLOBAL_PRIORITY_LOW:
851 return RADEON_CTX_PRIORITY_LOW;
852 default:
853 unreachable("Illegal global priority value");
854 return RADEON_CTX_PRIORITY_INVALID;
855 }
856 }
857
858 static int
859 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
860 int queue_family_index, int idx,
861 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
862 {
863 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
864 queue->device = device;
865 queue->queue_family_index = queue_family_index;
866 queue->queue_idx = idx;
867 queue->priority = radv_get_queue_global_priority(global_priority);
868
869 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
870 if (!queue->hw_ctx)
871 return VK_ERROR_OUT_OF_HOST_MEMORY;
872
873 return VK_SUCCESS;
874 }
875
876 static void
877 radv_queue_finish(struct radv_queue *queue)
878 {
879 if (queue->hw_ctx)
880 queue->device->ws->ctx_destroy(queue->hw_ctx);
881
882 if (queue->initial_full_flush_preamble_cs)
883 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
884 if (queue->initial_preamble_cs)
885 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
886 if (queue->continue_preamble_cs)
887 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
888 if (queue->descriptor_bo)
889 queue->device->ws->buffer_destroy(queue->descriptor_bo);
890 if (queue->scratch_bo)
891 queue->device->ws->buffer_destroy(queue->scratch_bo);
892 if (queue->esgs_ring_bo)
893 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
894 if (queue->gsvs_ring_bo)
895 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
896 if (queue->tess_factor_ring_bo)
897 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
898 if (queue->tess_offchip_ring_bo)
899 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
900 if (queue->compute_scratch_bo)
901 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
902 }
903
904 static void
905 radv_device_init_gs_info(struct radv_device *device)
906 {
907 switch (device->physical_device->rad_info.family) {
908 case CHIP_OLAND:
909 case CHIP_HAINAN:
910 case CHIP_KAVERI:
911 case CHIP_KABINI:
912 case CHIP_MULLINS:
913 case CHIP_ICELAND:
914 case CHIP_CARRIZO:
915 case CHIP_STONEY:
916 device->gs_table_depth = 16;
917 return;
918 case CHIP_TAHITI:
919 case CHIP_PITCAIRN:
920 case CHIP_VERDE:
921 case CHIP_BONAIRE:
922 case CHIP_HAWAII:
923 case CHIP_TONGA:
924 case CHIP_FIJI:
925 case CHIP_POLARIS10:
926 case CHIP_POLARIS11:
927 case CHIP_POLARIS12:
928 case CHIP_VEGA10:
929 case CHIP_RAVEN:
930 device->gs_table_depth = 32;
931 return;
932 default:
933 unreachable("unknown GPU");
934 }
935 }
936
937 VkResult radv_CreateDevice(
938 VkPhysicalDevice physicalDevice,
939 const VkDeviceCreateInfo* pCreateInfo,
940 const VkAllocationCallbacks* pAllocator,
941 VkDevice* pDevice)
942 {
943 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
944 VkResult result;
945 struct radv_device *device;
946
947 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
948 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
949 if (!radv_physical_device_extension_supported(physical_device, ext_name))
950 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
951 }
952
953 /* Check enabled features */
954 if (pCreateInfo->pEnabledFeatures) {
955 VkPhysicalDeviceFeatures supported_features;
956 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
957 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
958 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
959 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
960 for (uint32_t i = 0; i < num_features; i++) {
961 if (enabled_feature[i] && !supported_feature[i])
962 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
963 }
964 }
965
966 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
967 sizeof(*device), 8,
968 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
969 if (!device)
970 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
971
972 memset(device, 0, sizeof(*device));
973
974 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
975 device->instance = physical_device->instance;
976 device->physical_device = physical_device;
977
978 device->ws = physical_device->ws;
979 if (pAllocator)
980 device->alloc = *pAllocator;
981 else
982 device->alloc = physical_device->instance->alloc;
983
984 mtx_init(&device->shader_slab_mutex, mtx_plain);
985 list_inithead(&device->shader_slabs);
986
987 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
988 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
989 uint32_t qfi = queue_create->queueFamilyIndex;
990 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
991 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
992
993 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
994
995 device->queues[qfi] = vk_alloc(&device->alloc,
996 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
997 if (!device->queues[qfi]) {
998 result = VK_ERROR_OUT_OF_HOST_MEMORY;
999 goto fail;
1000 }
1001
1002 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1003
1004 device->queue_count[qfi] = queue_create->queueCount;
1005
1006 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1007 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1008 if (result != VK_SUCCESS)
1009 goto fail;
1010 }
1011 }
1012
1013 #if HAVE_LLVM < 0x0400
1014 device->llvm_supports_spill = false;
1015 #else
1016 device->llvm_supports_spill = true;
1017 #endif
1018
1019 /* The maximum number of scratch waves. Scratch space isn't divided
1020 * evenly between CUs. The number is only a function of the number of CUs.
1021 * We can decrease the constant to decrease the scratch buffer size.
1022 *
1023 * sctx->scratch_waves must be >= the maximum posible size of
1024 * 1 threadgroup, so that the hw doesn't hang from being unable
1025 * to start any.
1026 *
1027 * The recommended value is 4 per CU at most. Higher numbers don't
1028 * bring much benefit, but they still occupy chip resources (think
1029 * async compute). I've seen ~2% performance difference between 4 and 32.
1030 */
1031 uint32_t max_threads_per_block = 2048;
1032 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1033 max_threads_per_block / 64);
1034
1035 radv_device_init_gs_info(device);
1036
1037 device->tess_offchip_block_dw_size =
1038 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1039 device->has_distributed_tess =
1040 device->physical_device->rad_info.chip_class >= VI &&
1041 device->physical_device->rad_info.max_se >= 2;
1042
1043 if (getenv("RADV_TRACE_FILE")) {
1044 if (!radv_init_trace(device))
1045 goto fail;
1046 }
1047
1048 result = radv_device_init_meta(device);
1049 if (result != VK_SUCCESS)
1050 goto fail;
1051
1052 radv_device_init_msaa(device);
1053
1054 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1055 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1056 switch (family) {
1057 case RADV_QUEUE_GENERAL:
1058 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1059 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1060 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1061 break;
1062 case RADV_QUEUE_COMPUTE:
1063 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1064 radeon_emit(device->empty_cs[family], 0);
1065 break;
1066 }
1067 device->ws->cs_finalize(device->empty_cs[family]);
1068 }
1069
1070 if (device->physical_device->rad_info.chip_class >= CIK)
1071 cik_create_gfx_config(device);
1072
1073 VkPipelineCacheCreateInfo ci;
1074 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1075 ci.pNext = NULL;
1076 ci.flags = 0;
1077 ci.pInitialData = NULL;
1078 ci.initialDataSize = 0;
1079 VkPipelineCache pc;
1080 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1081 &ci, NULL, &pc);
1082 if (result != VK_SUCCESS)
1083 goto fail;
1084
1085 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1086
1087 *pDevice = radv_device_to_handle(device);
1088 return VK_SUCCESS;
1089
1090 fail:
1091 if (device->trace_bo)
1092 device->ws->buffer_destroy(device->trace_bo);
1093
1094 if (device->gfx_init)
1095 device->ws->buffer_destroy(device->gfx_init);
1096
1097 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1098 for (unsigned q = 0; q < device->queue_count[i]; q++)
1099 radv_queue_finish(&device->queues[i][q]);
1100 if (device->queue_count[i])
1101 vk_free(&device->alloc, device->queues[i]);
1102 }
1103
1104 vk_free(&device->alloc, device);
1105 return result;
1106 }
1107
1108 void radv_DestroyDevice(
1109 VkDevice _device,
1110 const VkAllocationCallbacks* pAllocator)
1111 {
1112 RADV_FROM_HANDLE(radv_device, device, _device);
1113
1114 if (!device)
1115 return;
1116
1117 if (device->trace_bo)
1118 device->ws->buffer_destroy(device->trace_bo);
1119
1120 if (device->gfx_init)
1121 device->ws->buffer_destroy(device->gfx_init);
1122
1123 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1124 for (unsigned q = 0; q < device->queue_count[i]; q++)
1125 radv_queue_finish(&device->queues[i][q]);
1126 if (device->queue_count[i])
1127 vk_free(&device->alloc, device->queues[i]);
1128 if (device->empty_cs[i])
1129 device->ws->cs_destroy(device->empty_cs[i]);
1130 }
1131 radv_device_finish_meta(device);
1132
1133 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1134 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1135
1136 radv_destroy_shader_slabs(device);
1137
1138 vk_free(&device->alloc, device);
1139 }
1140
1141 VkResult radv_EnumerateInstanceLayerProperties(
1142 uint32_t* pPropertyCount,
1143 VkLayerProperties* pProperties)
1144 {
1145 if (pProperties == NULL) {
1146 *pPropertyCount = 0;
1147 return VK_SUCCESS;
1148 }
1149
1150 /* None supported at this time */
1151 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1152 }
1153
1154 VkResult radv_EnumerateDeviceLayerProperties(
1155 VkPhysicalDevice physicalDevice,
1156 uint32_t* pPropertyCount,
1157 VkLayerProperties* pProperties)
1158 {
1159 if (pProperties == NULL) {
1160 *pPropertyCount = 0;
1161 return VK_SUCCESS;
1162 }
1163
1164 /* None supported at this time */
1165 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1166 }
1167
1168 void radv_GetDeviceQueue(
1169 VkDevice _device,
1170 uint32_t queueFamilyIndex,
1171 uint32_t queueIndex,
1172 VkQueue* pQueue)
1173 {
1174 RADV_FROM_HANDLE(radv_device, device, _device);
1175
1176 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1177 }
1178
1179 static void
1180 fill_geom_tess_rings(struct radv_queue *queue,
1181 uint32_t *map,
1182 bool add_sample_positions,
1183 uint32_t esgs_ring_size,
1184 struct radeon_winsys_bo *esgs_ring_bo,
1185 uint32_t gsvs_ring_size,
1186 struct radeon_winsys_bo *gsvs_ring_bo,
1187 uint32_t tess_factor_ring_size,
1188 struct radeon_winsys_bo *tess_factor_ring_bo,
1189 uint32_t tess_offchip_ring_size,
1190 struct radeon_winsys_bo *tess_offchip_ring_bo)
1191 {
1192 uint64_t esgs_va = 0, gsvs_va = 0;
1193 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1194 uint32_t *desc = &map[4];
1195
1196 if (esgs_ring_bo)
1197 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1198 if (gsvs_ring_bo)
1199 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1200 if (tess_factor_ring_bo)
1201 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1202 if (tess_offchip_ring_bo)
1203 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1204
1205 /* stride 0, num records - size, add tid, swizzle, elsize4,
1206 index stride 64 */
1207 desc[0] = esgs_va;
1208 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1209 S_008F04_STRIDE(0) |
1210 S_008F04_SWIZZLE_ENABLE(true);
1211 desc[2] = esgs_ring_size;
1212 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1213 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1214 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1215 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1216 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1217 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1218 S_008F0C_ELEMENT_SIZE(1) |
1219 S_008F0C_INDEX_STRIDE(3) |
1220 S_008F0C_ADD_TID_ENABLE(true);
1221
1222 desc += 4;
1223 /* GS entry for ES->GS ring */
1224 /* stride 0, num records - size, elsize0,
1225 index stride 0 */
1226 desc[0] = esgs_va;
1227 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1228 S_008F04_STRIDE(0) |
1229 S_008F04_SWIZZLE_ENABLE(false);
1230 desc[2] = esgs_ring_size;
1231 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1232 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1233 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1234 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1235 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1236 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1237 S_008F0C_ELEMENT_SIZE(0) |
1238 S_008F0C_INDEX_STRIDE(0) |
1239 S_008F0C_ADD_TID_ENABLE(false);
1240
1241 desc += 4;
1242 /* VS entry for GS->VS ring */
1243 /* stride 0, num records - size, elsize0,
1244 index stride 0 */
1245 desc[0] = gsvs_va;
1246 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1247 S_008F04_STRIDE(0) |
1248 S_008F04_SWIZZLE_ENABLE(false);
1249 desc[2] = gsvs_ring_size;
1250 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1251 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1252 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1253 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1254 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1255 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1256 S_008F0C_ELEMENT_SIZE(0) |
1257 S_008F0C_INDEX_STRIDE(0) |
1258 S_008F0C_ADD_TID_ENABLE(false);
1259 desc += 4;
1260
1261 /* stride gsvs_itemsize, num records 64
1262 elsize 4, index stride 16 */
1263 /* shader will patch stride and desc[2] */
1264 desc[0] = gsvs_va;
1265 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1266 S_008F04_STRIDE(0) |
1267 S_008F04_SWIZZLE_ENABLE(true);
1268 desc[2] = 0;
1269 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1270 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1271 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1272 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1273 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1274 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1275 S_008F0C_ELEMENT_SIZE(1) |
1276 S_008F0C_INDEX_STRIDE(1) |
1277 S_008F0C_ADD_TID_ENABLE(true);
1278 desc += 4;
1279
1280 desc[0] = tess_factor_va;
1281 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1282 S_008F04_STRIDE(0) |
1283 S_008F04_SWIZZLE_ENABLE(false);
1284 desc[2] = tess_factor_ring_size;
1285 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1286 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1287 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1288 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1289 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1290 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1291 S_008F0C_ELEMENT_SIZE(0) |
1292 S_008F0C_INDEX_STRIDE(0) |
1293 S_008F0C_ADD_TID_ENABLE(false);
1294 desc += 4;
1295
1296 desc[0] = tess_offchip_va;
1297 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1298 S_008F04_STRIDE(0) |
1299 S_008F04_SWIZZLE_ENABLE(false);
1300 desc[2] = tess_offchip_ring_size;
1301 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1302 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1303 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1304 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1305 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1306 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1307 S_008F0C_ELEMENT_SIZE(0) |
1308 S_008F0C_INDEX_STRIDE(0) |
1309 S_008F0C_ADD_TID_ENABLE(false);
1310 desc += 4;
1311
1312 /* add sample positions after all rings */
1313 memcpy(desc, queue->device->sample_locations_1x, 8);
1314 desc += 2;
1315 memcpy(desc, queue->device->sample_locations_2x, 16);
1316 desc += 4;
1317 memcpy(desc, queue->device->sample_locations_4x, 32);
1318 desc += 8;
1319 memcpy(desc, queue->device->sample_locations_8x, 64);
1320 desc += 16;
1321 memcpy(desc, queue->device->sample_locations_16x, 128);
1322 }
1323
1324 static unsigned
1325 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1326 {
1327 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1328 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1329 device->physical_device->rad_info.family != CHIP_STONEY;
1330 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1331 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1332 device->physical_device->rad_info.max_se;
1333 unsigned offchip_granularity;
1334 unsigned hs_offchip_param;
1335 switch (device->tess_offchip_block_dw_size) {
1336 default:
1337 assert(0);
1338 /* fall through */
1339 case 8192:
1340 offchip_granularity = V_03093C_X_8K_DWORDS;
1341 break;
1342 case 4096:
1343 offchip_granularity = V_03093C_X_4K_DWORDS;
1344 break;
1345 }
1346
1347 switch (device->physical_device->rad_info.chip_class) {
1348 case SI:
1349 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1350 break;
1351 case CIK:
1352 case VI:
1353 case GFX9:
1354 default:
1355 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1356 break;
1357 }
1358
1359 *max_offchip_buffers_p = max_offchip_buffers;
1360 if (device->physical_device->rad_info.chip_class >= CIK) {
1361 if (device->physical_device->rad_info.chip_class >= VI)
1362 --max_offchip_buffers;
1363 hs_offchip_param =
1364 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1365 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1366 } else {
1367 hs_offchip_param =
1368 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1369 }
1370 return hs_offchip_param;
1371 }
1372
1373 static VkResult
1374 radv_get_preamble_cs(struct radv_queue *queue,
1375 uint32_t scratch_size,
1376 uint32_t compute_scratch_size,
1377 uint32_t esgs_ring_size,
1378 uint32_t gsvs_ring_size,
1379 bool needs_tess_rings,
1380 bool needs_sample_positions,
1381 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1382 struct radeon_winsys_cs **initial_preamble_cs,
1383 struct radeon_winsys_cs **continue_preamble_cs)
1384 {
1385 struct radeon_winsys_bo *scratch_bo = NULL;
1386 struct radeon_winsys_bo *descriptor_bo = NULL;
1387 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1388 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1389 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1390 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1391 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1392 struct radeon_winsys_cs *dest_cs[3] = {0};
1393 bool add_tess_rings = false, add_sample_positions = false;
1394 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1395 unsigned max_offchip_buffers;
1396 unsigned hs_offchip_param = 0;
1397 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1398 if (!queue->has_tess_rings) {
1399 if (needs_tess_rings)
1400 add_tess_rings = true;
1401 }
1402 if (!queue->has_sample_positions) {
1403 if (needs_sample_positions)
1404 add_sample_positions = true;
1405 }
1406 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1407 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1408 &max_offchip_buffers);
1409 tess_offchip_ring_size = max_offchip_buffers *
1410 queue->device->tess_offchip_block_dw_size * 4;
1411
1412 if (scratch_size <= queue->scratch_size &&
1413 compute_scratch_size <= queue->compute_scratch_size &&
1414 esgs_ring_size <= queue->esgs_ring_size &&
1415 gsvs_ring_size <= queue->gsvs_ring_size &&
1416 !add_tess_rings && !add_sample_positions &&
1417 queue->initial_preamble_cs) {
1418 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1419 *initial_preamble_cs = queue->initial_preamble_cs;
1420 *continue_preamble_cs = queue->continue_preamble_cs;
1421 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1422 *continue_preamble_cs = NULL;
1423 return VK_SUCCESS;
1424 }
1425
1426 if (scratch_size > queue->scratch_size) {
1427 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1428 scratch_size,
1429 4096,
1430 RADEON_DOMAIN_VRAM,
1431 ring_bo_flags);
1432 if (!scratch_bo)
1433 goto fail;
1434 } else
1435 scratch_bo = queue->scratch_bo;
1436
1437 if (compute_scratch_size > queue->compute_scratch_size) {
1438 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1439 compute_scratch_size,
1440 4096,
1441 RADEON_DOMAIN_VRAM,
1442 ring_bo_flags);
1443 if (!compute_scratch_bo)
1444 goto fail;
1445
1446 } else
1447 compute_scratch_bo = queue->compute_scratch_bo;
1448
1449 if (esgs_ring_size > queue->esgs_ring_size) {
1450 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1451 esgs_ring_size,
1452 4096,
1453 RADEON_DOMAIN_VRAM,
1454 ring_bo_flags);
1455 if (!esgs_ring_bo)
1456 goto fail;
1457 } else {
1458 esgs_ring_bo = queue->esgs_ring_bo;
1459 esgs_ring_size = queue->esgs_ring_size;
1460 }
1461
1462 if (gsvs_ring_size > queue->gsvs_ring_size) {
1463 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1464 gsvs_ring_size,
1465 4096,
1466 RADEON_DOMAIN_VRAM,
1467 ring_bo_flags);
1468 if (!gsvs_ring_bo)
1469 goto fail;
1470 } else {
1471 gsvs_ring_bo = queue->gsvs_ring_bo;
1472 gsvs_ring_size = queue->gsvs_ring_size;
1473 }
1474
1475 if (add_tess_rings) {
1476 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1477 tess_factor_ring_size,
1478 256,
1479 RADEON_DOMAIN_VRAM,
1480 ring_bo_flags);
1481 if (!tess_factor_ring_bo)
1482 goto fail;
1483 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1484 tess_offchip_ring_size,
1485 256,
1486 RADEON_DOMAIN_VRAM,
1487 ring_bo_flags);
1488 if (!tess_offchip_ring_bo)
1489 goto fail;
1490 } else {
1491 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1492 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1493 }
1494
1495 if (scratch_bo != queue->scratch_bo ||
1496 esgs_ring_bo != queue->esgs_ring_bo ||
1497 gsvs_ring_bo != queue->gsvs_ring_bo ||
1498 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1499 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1500 uint32_t size = 0;
1501 if (gsvs_ring_bo || esgs_ring_bo ||
1502 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1503 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1504 if (add_sample_positions)
1505 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1506 }
1507 else if (scratch_bo)
1508 size = 8; /* 2 dword */
1509
1510 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1511 size,
1512 4096,
1513 RADEON_DOMAIN_VRAM,
1514 RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
1515 if (!descriptor_bo)
1516 goto fail;
1517 } else
1518 descriptor_bo = queue->descriptor_bo;
1519
1520 for(int i = 0; i < 3; ++i) {
1521 struct radeon_winsys_cs *cs = NULL;
1522 cs = queue->device->ws->cs_create(queue->device->ws,
1523 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1524 if (!cs)
1525 goto fail;
1526
1527 dest_cs[i] = cs;
1528
1529 if (scratch_bo)
1530 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1531
1532 if (esgs_ring_bo)
1533 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1534
1535 if (gsvs_ring_bo)
1536 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1537
1538 if (tess_factor_ring_bo)
1539 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1540
1541 if (tess_offchip_ring_bo)
1542 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1543
1544 if (descriptor_bo)
1545 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1546
1547 if (descriptor_bo != queue->descriptor_bo) {
1548 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1549
1550 if (scratch_bo) {
1551 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1552 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1553 S_008F04_SWIZZLE_ENABLE(1);
1554 map[0] = scratch_va;
1555 map[1] = rsrc1;
1556 }
1557
1558 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1559 add_sample_positions)
1560 fill_geom_tess_rings(queue, map, add_sample_positions,
1561 esgs_ring_size, esgs_ring_bo,
1562 gsvs_ring_size, gsvs_ring_bo,
1563 tess_factor_ring_size, tess_factor_ring_bo,
1564 tess_offchip_ring_size, tess_offchip_ring_bo);
1565
1566 queue->device->ws->buffer_unmap(descriptor_bo);
1567 }
1568
1569 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1570 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1571 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1572 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1573 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1574 }
1575
1576 if (esgs_ring_bo || gsvs_ring_bo) {
1577 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1578 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1579 radeon_emit(cs, esgs_ring_size >> 8);
1580 radeon_emit(cs, gsvs_ring_size >> 8);
1581 } else {
1582 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1583 radeon_emit(cs, esgs_ring_size >> 8);
1584 radeon_emit(cs, gsvs_ring_size >> 8);
1585 }
1586 }
1587
1588 if (tess_factor_ring_bo) {
1589 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1590 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1591 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1592 S_030938_SIZE(tess_factor_ring_size / 4));
1593 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1594 tf_va >> 8);
1595 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1596 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1597 tf_va >> 40);
1598 }
1599 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1600 } else {
1601 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1602 S_008988_SIZE(tess_factor_ring_size / 4));
1603 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1604 tf_va >> 8);
1605 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1606 hs_offchip_param);
1607 }
1608 }
1609
1610 if (descriptor_bo) {
1611 uint64_t va = radv_buffer_get_va(descriptor_bo);
1612 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1613 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1614 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1615 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1616 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1617
1618 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1619 radeon_set_sh_reg_seq(cs, regs[i], 2);
1620 radeon_emit(cs, va);
1621 radeon_emit(cs, va >> 32);
1622 }
1623 } else {
1624 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1625 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1626 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1627 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1628 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1629 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1630
1631 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1632 radeon_set_sh_reg_seq(cs, regs[i], 2);
1633 radeon_emit(cs, va);
1634 radeon_emit(cs, va >> 32);
1635 }
1636 }
1637 }
1638
1639 if (compute_scratch_bo) {
1640 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1641 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1642 S_008F04_SWIZZLE_ENABLE(1);
1643
1644 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1645
1646 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1647 radeon_emit(cs, scratch_va);
1648 radeon_emit(cs, rsrc1);
1649 }
1650
1651 if (i == 0) {
1652 si_cs_emit_cache_flush(cs,
1653 false,
1654 queue->device->physical_device->rad_info.chip_class,
1655 NULL, 0,
1656 queue->queue_family_index == RING_COMPUTE &&
1657 queue->device->physical_device->rad_info.chip_class >= CIK,
1658 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1659 RADV_CMD_FLAG_INV_ICACHE |
1660 RADV_CMD_FLAG_INV_SMEM_L1 |
1661 RADV_CMD_FLAG_INV_VMEM_L1 |
1662 RADV_CMD_FLAG_INV_GLOBAL_L2);
1663 } else if (i == 1) {
1664 si_cs_emit_cache_flush(cs,
1665 false,
1666 queue->device->physical_device->rad_info.chip_class,
1667 NULL, 0,
1668 queue->queue_family_index == RING_COMPUTE &&
1669 queue->device->physical_device->rad_info.chip_class >= CIK,
1670 RADV_CMD_FLAG_INV_ICACHE |
1671 RADV_CMD_FLAG_INV_SMEM_L1 |
1672 RADV_CMD_FLAG_INV_VMEM_L1 |
1673 RADV_CMD_FLAG_INV_GLOBAL_L2);
1674 }
1675
1676 if (!queue->device->ws->cs_finalize(cs))
1677 goto fail;
1678 }
1679
1680 if (queue->initial_full_flush_preamble_cs)
1681 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1682
1683 if (queue->initial_preamble_cs)
1684 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1685
1686 if (queue->continue_preamble_cs)
1687 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1688
1689 queue->initial_full_flush_preamble_cs = dest_cs[0];
1690 queue->initial_preamble_cs = dest_cs[1];
1691 queue->continue_preamble_cs = dest_cs[2];
1692
1693 if (scratch_bo != queue->scratch_bo) {
1694 if (queue->scratch_bo)
1695 queue->device->ws->buffer_destroy(queue->scratch_bo);
1696 queue->scratch_bo = scratch_bo;
1697 queue->scratch_size = scratch_size;
1698 }
1699
1700 if (compute_scratch_bo != queue->compute_scratch_bo) {
1701 if (queue->compute_scratch_bo)
1702 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1703 queue->compute_scratch_bo = compute_scratch_bo;
1704 queue->compute_scratch_size = compute_scratch_size;
1705 }
1706
1707 if (esgs_ring_bo != queue->esgs_ring_bo) {
1708 if (queue->esgs_ring_bo)
1709 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1710 queue->esgs_ring_bo = esgs_ring_bo;
1711 queue->esgs_ring_size = esgs_ring_size;
1712 }
1713
1714 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1715 if (queue->gsvs_ring_bo)
1716 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1717 queue->gsvs_ring_bo = gsvs_ring_bo;
1718 queue->gsvs_ring_size = gsvs_ring_size;
1719 }
1720
1721 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1722 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1723 }
1724
1725 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1726 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1727 queue->has_tess_rings = true;
1728 }
1729
1730 if (descriptor_bo != queue->descriptor_bo) {
1731 if (queue->descriptor_bo)
1732 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1733
1734 queue->descriptor_bo = descriptor_bo;
1735 }
1736
1737 if (add_sample_positions)
1738 queue->has_sample_positions = true;
1739
1740 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1741 *initial_preamble_cs = queue->initial_preamble_cs;
1742 *continue_preamble_cs = queue->continue_preamble_cs;
1743 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1744 *continue_preamble_cs = NULL;
1745 return VK_SUCCESS;
1746 fail:
1747 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1748 if (dest_cs[i])
1749 queue->device->ws->cs_destroy(dest_cs[i]);
1750 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1751 queue->device->ws->buffer_destroy(descriptor_bo);
1752 if (scratch_bo && scratch_bo != queue->scratch_bo)
1753 queue->device->ws->buffer_destroy(scratch_bo);
1754 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1755 queue->device->ws->buffer_destroy(compute_scratch_bo);
1756 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1757 queue->device->ws->buffer_destroy(esgs_ring_bo);
1758 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1759 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1760 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1761 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1762 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1763 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1764 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1765 }
1766
1767 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1768 int num_sems,
1769 const VkSemaphore *sems,
1770 bool reset_temp)
1771 {
1772 int syncobj_idx = 0, sem_idx = 0;
1773
1774 if (num_sems == 0)
1775 return VK_SUCCESS;
1776 for (uint32_t i = 0; i < num_sems; i++) {
1777 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1778
1779 if (sem->temp_syncobj || sem->syncobj)
1780 counts->syncobj_count++;
1781 else
1782 counts->sem_count++;
1783 }
1784
1785 if (counts->syncobj_count) {
1786 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1787 if (!counts->syncobj)
1788 return VK_ERROR_OUT_OF_HOST_MEMORY;
1789 }
1790
1791 if (counts->sem_count) {
1792 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1793 if (!counts->sem) {
1794 free(counts->syncobj);
1795 return VK_ERROR_OUT_OF_HOST_MEMORY;
1796 }
1797 }
1798
1799 for (uint32_t i = 0; i < num_sems; i++) {
1800 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1801
1802 if (sem->temp_syncobj) {
1803 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1804 if (reset_temp) {
1805 /* after we wait on a temp import - drop it */
1806 sem->temp_syncobj = 0;
1807 }
1808 }
1809 else if (sem->syncobj)
1810 counts->syncobj[syncobj_idx++] = sem->syncobj;
1811 else {
1812 assert(sem->sem);
1813 counts->sem[sem_idx++] = sem->sem;
1814 }
1815 }
1816
1817 return VK_SUCCESS;
1818 }
1819
1820 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1821 {
1822 free(sem_info->wait.syncobj);
1823 free(sem_info->wait.sem);
1824 free(sem_info->signal.syncobj);
1825 free(sem_info->signal.sem);
1826 }
1827
1828 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1829 int num_wait_sems,
1830 const VkSemaphore *wait_sems,
1831 int num_signal_sems,
1832 const VkSemaphore *signal_sems)
1833 {
1834 VkResult ret;
1835 memset(sem_info, 0, sizeof(*sem_info));
1836
1837 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1838 if (ret)
1839 return ret;
1840 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1841 if (ret)
1842 radv_free_sem_info(sem_info);
1843
1844 /* caller can override these */
1845 sem_info->cs_emit_wait = true;
1846 sem_info->cs_emit_signal = true;
1847 return ret;
1848 }
1849
1850 VkResult radv_QueueSubmit(
1851 VkQueue _queue,
1852 uint32_t submitCount,
1853 const VkSubmitInfo* pSubmits,
1854 VkFence _fence)
1855 {
1856 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1857 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1858 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1859 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1860 int ret;
1861 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1862 uint32_t scratch_size = 0;
1863 uint32_t compute_scratch_size = 0;
1864 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1865 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1866 VkResult result;
1867 bool fence_emitted = false;
1868 bool tess_rings_needed = false;
1869 bool sample_positions_needed = false;
1870
1871 /* Do this first so failing to allocate scratch buffers can't result in
1872 * partially executed submissions. */
1873 for (uint32_t i = 0; i < submitCount; i++) {
1874 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1875 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1876 pSubmits[i].pCommandBuffers[j]);
1877
1878 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1879 compute_scratch_size = MAX2(compute_scratch_size,
1880 cmd_buffer->compute_scratch_size_needed);
1881 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1882 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1883 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1884 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1885 }
1886 }
1887
1888 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1889 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1890 sample_positions_needed, &initial_flush_preamble_cs,
1891 &initial_preamble_cs, &continue_preamble_cs);
1892 if (result != VK_SUCCESS)
1893 return result;
1894
1895 for (uint32_t i = 0; i < submitCount; i++) {
1896 struct radeon_winsys_cs **cs_array;
1897 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1898 bool can_patch = true;
1899 uint32_t advance;
1900 struct radv_winsys_sem_info sem_info;
1901
1902 result = radv_alloc_sem_info(&sem_info,
1903 pSubmits[i].waitSemaphoreCount,
1904 pSubmits[i].pWaitSemaphores,
1905 pSubmits[i].signalSemaphoreCount,
1906 pSubmits[i].pSignalSemaphores);
1907 if (result != VK_SUCCESS)
1908 return result;
1909
1910 if (!pSubmits[i].commandBufferCount) {
1911 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1912 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1913 &queue->device->empty_cs[queue->queue_family_index],
1914 1, NULL, NULL,
1915 &sem_info,
1916 false, base_fence);
1917 if (ret) {
1918 radv_loge("failed to submit CS %d\n", i);
1919 abort();
1920 }
1921 fence_emitted = true;
1922 }
1923 radv_free_sem_info(&sem_info);
1924 continue;
1925 }
1926
1927 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1928 (pSubmits[i].commandBufferCount));
1929
1930 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1931 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1932 pSubmits[i].pCommandBuffers[j]);
1933 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1934
1935 cs_array[j] = cmd_buffer->cs;
1936 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1937 can_patch = false;
1938 }
1939
1940 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1941 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
1942 advance = MIN2(max_cs_submission,
1943 pSubmits[i].commandBufferCount - j);
1944
1945 if (queue->device->trace_bo)
1946 *queue->device->trace_id_ptr = 0;
1947
1948 sem_info.cs_emit_wait = j == 0;
1949 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
1950
1951 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1952 advance, initial_preamble, continue_preamble_cs,
1953 &sem_info,
1954 can_patch, base_fence);
1955
1956 if (ret) {
1957 radv_loge("failed to submit CS %d\n", i);
1958 abort();
1959 }
1960 fence_emitted = true;
1961 if (queue->device->trace_bo) {
1962 radv_check_gpu_hangs(queue, cs_array[j]);
1963 }
1964 }
1965
1966 radv_free_sem_info(&sem_info);
1967 free(cs_array);
1968 }
1969
1970 if (fence) {
1971 if (!fence_emitted) {
1972 struct radv_winsys_sem_info sem_info = {0};
1973 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1974 &queue->device->empty_cs[queue->queue_family_index],
1975 1, NULL, NULL, &sem_info,
1976 false, base_fence);
1977 }
1978 fence->submitted = true;
1979 }
1980
1981 return VK_SUCCESS;
1982 }
1983
1984 VkResult radv_QueueWaitIdle(
1985 VkQueue _queue)
1986 {
1987 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1988
1989 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1990 radv_queue_family_to_ring(queue->queue_family_index),
1991 queue->queue_idx);
1992 return VK_SUCCESS;
1993 }
1994
1995 VkResult radv_DeviceWaitIdle(
1996 VkDevice _device)
1997 {
1998 RADV_FROM_HANDLE(radv_device, device, _device);
1999
2000 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2001 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2002 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2003 }
2004 }
2005 return VK_SUCCESS;
2006 }
2007
2008 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2009 VkInstance instance,
2010 const char* pName)
2011 {
2012 return radv_lookup_entrypoint(pName);
2013 }
2014
2015 /* The loader wants us to expose a second GetInstanceProcAddr function
2016 * to work around certain LD_PRELOAD issues seen in apps.
2017 */
2018 PUBLIC
2019 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2020 VkInstance instance,
2021 const char* pName);
2022
2023 PUBLIC
2024 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2025 VkInstance instance,
2026 const char* pName)
2027 {
2028 return radv_GetInstanceProcAddr(instance, pName);
2029 }
2030
2031 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2032 VkDevice device,
2033 const char* pName)
2034 {
2035 return radv_lookup_entrypoint(pName);
2036 }
2037
2038 bool radv_get_memory_fd(struct radv_device *device,
2039 struct radv_device_memory *memory,
2040 int *pFD)
2041 {
2042 struct radeon_bo_metadata metadata;
2043
2044 if (memory->image) {
2045 radv_init_metadata(device, memory->image, &metadata);
2046 device->ws->buffer_set_metadata(memory->bo, &metadata);
2047 }
2048
2049 return device->ws->buffer_get_fd(device->ws, memory->bo,
2050 pFD);
2051 }
2052
2053 VkResult radv_alloc_memory(VkDevice _device,
2054 const VkMemoryAllocateInfo* pAllocateInfo,
2055 const VkAllocationCallbacks* pAllocator,
2056 enum radv_mem_flags_bits mem_flags,
2057 VkDeviceMemory* pMem)
2058 {
2059 RADV_FROM_HANDLE(radv_device, device, _device);
2060 struct radv_device_memory *mem;
2061 VkResult result;
2062 enum radeon_bo_domain domain;
2063 uint32_t flags = 0;
2064
2065 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2066
2067 if (pAllocateInfo->allocationSize == 0) {
2068 /* Apparently, this is allowed */
2069 *pMem = VK_NULL_HANDLE;
2070 return VK_SUCCESS;
2071 }
2072
2073 const VkImportMemoryFdInfoKHR *import_info =
2074 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2075 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2076 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2077
2078 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2079 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2080 if (mem == NULL)
2081 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2082
2083 if (dedicate_info) {
2084 mem->image = radv_image_from_handle(dedicate_info->image);
2085 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2086 } else {
2087 mem->image = NULL;
2088 mem->buffer = NULL;
2089 }
2090
2091 if (import_info) {
2092 assert(import_info->handleType ==
2093 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2094 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2095 NULL, NULL);
2096 if (!mem->bo) {
2097 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2098 goto fail;
2099 } else {
2100 close(import_info->fd);
2101 goto out_success;
2102 }
2103 }
2104
2105 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2106 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2107 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2108 domain = RADEON_DOMAIN_GTT;
2109 else
2110 domain = RADEON_DOMAIN_VRAM;
2111
2112 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2113 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2114 else
2115 flags |= RADEON_FLAG_CPU_ACCESS;
2116
2117 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2118 flags |= RADEON_FLAG_GTT_WC;
2119
2120 if (mem_flags & RADV_MEM_IMPLICIT_SYNC)
2121 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2122
2123 if (!dedicate_info && !import_info)
2124 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2125
2126 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2127 domain, flags);
2128
2129 if (!mem->bo) {
2130 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2131 goto fail;
2132 }
2133 mem->type_index = pAllocateInfo->memoryTypeIndex;
2134 out_success:
2135 *pMem = radv_device_memory_to_handle(mem);
2136
2137 return VK_SUCCESS;
2138
2139 fail:
2140 vk_free2(&device->alloc, pAllocator, mem);
2141
2142 return result;
2143 }
2144
2145 VkResult radv_AllocateMemory(
2146 VkDevice _device,
2147 const VkMemoryAllocateInfo* pAllocateInfo,
2148 const VkAllocationCallbacks* pAllocator,
2149 VkDeviceMemory* pMem)
2150 {
2151 return radv_alloc_memory(_device, pAllocateInfo, pAllocator, 0, pMem);
2152 }
2153
2154 void radv_FreeMemory(
2155 VkDevice _device,
2156 VkDeviceMemory _mem,
2157 const VkAllocationCallbacks* pAllocator)
2158 {
2159 RADV_FROM_HANDLE(radv_device, device, _device);
2160 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2161
2162 if (mem == NULL)
2163 return;
2164
2165 device->ws->buffer_destroy(mem->bo);
2166 mem->bo = NULL;
2167
2168 vk_free2(&device->alloc, pAllocator, mem);
2169 }
2170
2171 VkResult radv_MapMemory(
2172 VkDevice _device,
2173 VkDeviceMemory _memory,
2174 VkDeviceSize offset,
2175 VkDeviceSize size,
2176 VkMemoryMapFlags flags,
2177 void** ppData)
2178 {
2179 RADV_FROM_HANDLE(radv_device, device, _device);
2180 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2181
2182 if (mem == NULL) {
2183 *ppData = NULL;
2184 return VK_SUCCESS;
2185 }
2186
2187 *ppData = device->ws->buffer_map(mem->bo);
2188 if (*ppData) {
2189 *ppData += offset;
2190 return VK_SUCCESS;
2191 }
2192
2193 return VK_ERROR_MEMORY_MAP_FAILED;
2194 }
2195
2196 void radv_UnmapMemory(
2197 VkDevice _device,
2198 VkDeviceMemory _memory)
2199 {
2200 RADV_FROM_HANDLE(radv_device, device, _device);
2201 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2202
2203 if (mem == NULL)
2204 return;
2205
2206 device->ws->buffer_unmap(mem->bo);
2207 }
2208
2209 VkResult radv_FlushMappedMemoryRanges(
2210 VkDevice _device,
2211 uint32_t memoryRangeCount,
2212 const VkMappedMemoryRange* pMemoryRanges)
2213 {
2214 return VK_SUCCESS;
2215 }
2216
2217 VkResult radv_InvalidateMappedMemoryRanges(
2218 VkDevice _device,
2219 uint32_t memoryRangeCount,
2220 const VkMappedMemoryRange* pMemoryRanges)
2221 {
2222 return VK_SUCCESS;
2223 }
2224
2225 void radv_GetBufferMemoryRequirements(
2226 VkDevice device,
2227 VkBuffer _buffer,
2228 VkMemoryRequirements* pMemoryRequirements)
2229 {
2230 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2231
2232 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2233
2234 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2235 pMemoryRequirements->alignment = 4096;
2236 else
2237 pMemoryRequirements->alignment = 16;
2238
2239 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2240 }
2241
2242 void radv_GetBufferMemoryRequirements2KHR(
2243 VkDevice device,
2244 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2245 VkMemoryRequirements2KHR* pMemoryRequirements)
2246 {
2247 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2248 &pMemoryRequirements->memoryRequirements);
2249
2250 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2251 switch (ext->sType) {
2252 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2253 VkMemoryDedicatedRequirementsKHR *req =
2254 (VkMemoryDedicatedRequirementsKHR *) ext;
2255 req->requiresDedicatedAllocation = false;
2256 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2257 break;
2258 }
2259 default:
2260 break;
2261 }
2262 }
2263 }
2264
2265 void radv_GetImageMemoryRequirements(
2266 VkDevice device,
2267 VkImage _image,
2268 VkMemoryRequirements* pMemoryRequirements)
2269 {
2270 RADV_FROM_HANDLE(radv_image, image, _image);
2271
2272 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2273
2274 pMemoryRequirements->size = image->size;
2275 pMemoryRequirements->alignment = image->alignment;
2276 }
2277
2278 void radv_GetImageMemoryRequirements2KHR(
2279 VkDevice device,
2280 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2281 VkMemoryRequirements2KHR* pMemoryRequirements)
2282 {
2283 radv_GetImageMemoryRequirements(device, pInfo->image,
2284 &pMemoryRequirements->memoryRequirements);
2285
2286 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2287
2288 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2289 switch (ext->sType) {
2290 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2291 VkMemoryDedicatedRequirementsKHR *req =
2292 (VkMemoryDedicatedRequirementsKHR *) ext;
2293 req->requiresDedicatedAllocation = image->shareable;
2294 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2295 break;
2296 }
2297 default:
2298 break;
2299 }
2300 }
2301 }
2302
2303 void radv_GetImageSparseMemoryRequirements(
2304 VkDevice device,
2305 VkImage image,
2306 uint32_t* pSparseMemoryRequirementCount,
2307 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2308 {
2309 stub();
2310 }
2311
2312 void radv_GetImageSparseMemoryRequirements2KHR(
2313 VkDevice device,
2314 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2315 uint32_t* pSparseMemoryRequirementCount,
2316 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2317 {
2318 stub();
2319 }
2320
2321 void radv_GetDeviceMemoryCommitment(
2322 VkDevice device,
2323 VkDeviceMemory memory,
2324 VkDeviceSize* pCommittedMemoryInBytes)
2325 {
2326 *pCommittedMemoryInBytes = 0;
2327 }
2328
2329 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2330 uint32_t bindInfoCount,
2331 const VkBindBufferMemoryInfoKHR *pBindInfos)
2332 {
2333 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2334 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2335 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2336
2337 if (mem) {
2338 buffer->bo = mem->bo;
2339 buffer->offset = pBindInfos[i].memoryOffset;
2340 } else {
2341 buffer->bo = NULL;
2342 }
2343 }
2344 return VK_SUCCESS;
2345 }
2346
2347 VkResult radv_BindBufferMemory(
2348 VkDevice device,
2349 VkBuffer buffer,
2350 VkDeviceMemory memory,
2351 VkDeviceSize memoryOffset)
2352 {
2353 const VkBindBufferMemoryInfoKHR info = {
2354 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2355 .buffer = buffer,
2356 .memory = memory,
2357 .memoryOffset = memoryOffset
2358 };
2359
2360 return radv_BindBufferMemory2KHR(device, 1, &info);
2361 }
2362
2363 VkResult radv_BindImageMemory2KHR(VkDevice device,
2364 uint32_t bindInfoCount,
2365 const VkBindImageMemoryInfoKHR *pBindInfos)
2366 {
2367 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2368 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2369 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2370
2371 if (mem) {
2372 image->bo = mem->bo;
2373 image->offset = pBindInfos[i].memoryOffset;
2374 } else {
2375 image->bo = NULL;
2376 image->offset = 0;
2377 }
2378 }
2379 return VK_SUCCESS;
2380 }
2381
2382
2383 VkResult radv_BindImageMemory(
2384 VkDevice device,
2385 VkImage image,
2386 VkDeviceMemory memory,
2387 VkDeviceSize memoryOffset)
2388 {
2389 const VkBindImageMemoryInfoKHR info = {
2390 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2391 .image = image,
2392 .memory = memory,
2393 .memoryOffset = memoryOffset
2394 };
2395
2396 return radv_BindImageMemory2KHR(device, 1, &info);
2397 }
2398
2399
2400 static void
2401 radv_sparse_buffer_bind_memory(struct radv_device *device,
2402 const VkSparseBufferMemoryBindInfo *bind)
2403 {
2404 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2405
2406 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2407 struct radv_device_memory *mem = NULL;
2408
2409 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2410 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2411
2412 device->ws->buffer_virtual_bind(buffer->bo,
2413 bind->pBinds[i].resourceOffset,
2414 bind->pBinds[i].size,
2415 mem ? mem->bo : NULL,
2416 bind->pBinds[i].memoryOffset);
2417 }
2418 }
2419
2420 static void
2421 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2422 const VkSparseImageOpaqueMemoryBindInfo *bind)
2423 {
2424 RADV_FROM_HANDLE(radv_image, image, bind->image);
2425
2426 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2427 struct radv_device_memory *mem = NULL;
2428
2429 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2430 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2431
2432 device->ws->buffer_virtual_bind(image->bo,
2433 bind->pBinds[i].resourceOffset,
2434 bind->pBinds[i].size,
2435 mem ? mem->bo : NULL,
2436 bind->pBinds[i].memoryOffset);
2437 }
2438 }
2439
2440 VkResult radv_QueueBindSparse(
2441 VkQueue _queue,
2442 uint32_t bindInfoCount,
2443 const VkBindSparseInfo* pBindInfo,
2444 VkFence _fence)
2445 {
2446 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2447 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2448 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2449 bool fence_emitted = false;
2450
2451 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2452 struct radv_winsys_sem_info sem_info;
2453 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2454 radv_sparse_buffer_bind_memory(queue->device,
2455 pBindInfo[i].pBufferBinds + j);
2456 }
2457
2458 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2459 radv_sparse_image_opaque_bind_memory(queue->device,
2460 pBindInfo[i].pImageOpaqueBinds + j);
2461 }
2462
2463 VkResult result;
2464 result = radv_alloc_sem_info(&sem_info,
2465 pBindInfo[i].waitSemaphoreCount,
2466 pBindInfo[i].pWaitSemaphores,
2467 pBindInfo[i].signalSemaphoreCount,
2468 pBindInfo[i].pSignalSemaphores);
2469 if (result != VK_SUCCESS)
2470 return result;
2471
2472 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2473 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2474 &queue->device->empty_cs[queue->queue_family_index],
2475 1, NULL, NULL,
2476 &sem_info,
2477 false, base_fence);
2478 fence_emitted = true;
2479 if (fence)
2480 fence->submitted = true;
2481 }
2482
2483 radv_free_sem_info(&sem_info);
2484
2485 }
2486
2487 if (fence && !fence_emitted) {
2488 fence->signalled = true;
2489 }
2490
2491 return VK_SUCCESS;
2492 }
2493
2494 VkResult radv_CreateFence(
2495 VkDevice _device,
2496 const VkFenceCreateInfo* pCreateInfo,
2497 const VkAllocationCallbacks* pAllocator,
2498 VkFence* pFence)
2499 {
2500 RADV_FROM_HANDLE(radv_device, device, _device);
2501 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2502 sizeof(*fence), 8,
2503 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2504
2505 if (!fence)
2506 return VK_ERROR_OUT_OF_HOST_MEMORY;
2507
2508 memset(fence, 0, sizeof(*fence));
2509 fence->submitted = false;
2510 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2511 fence->fence = device->ws->create_fence();
2512 if (!fence->fence) {
2513 vk_free2(&device->alloc, pAllocator, fence);
2514 return VK_ERROR_OUT_OF_HOST_MEMORY;
2515 }
2516
2517 *pFence = radv_fence_to_handle(fence);
2518
2519 return VK_SUCCESS;
2520 }
2521
2522 void radv_DestroyFence(
2523 VkDevice _device,
2524 VkFence _fence,
2525 const VkAllocationCallbacks* pAllocator)
2526 {
2527 RADV_FROM_HANDLE(radv_device, device, _device);
2528 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2529
2530 if (!fence)
2531 return;
2532 device->ws->destroy_fence(fence->fence);
2533 vk_free2(&device->alloc, pAllocator, fence);
2534 }
2535
2536 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2537 {
2538 uint64_t current_time;
2539 struct timespec tv;
2540
2541 clock_gettime(CLOCK_MONOTONIC, &tv);
2542 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2543
2544 timeout = MIN2(UINT64_MAX - current_time, timeout);
2545
2546 return current_time + timeout;
2547 }
2548
2549 VkResult radv_WaitForFences(
2550 VkDevice _device,
2551 uint32_t fenceCount,
2552 const VkFence* pFences,
2553 VkBool32 waitAll,
2554 uint64_t timeout)
2555 {
2556 RADV_FROM_HANDLE(radv_device, device, _device);
2557 timeout = radv_get_absolute_timeout(timeout);
2558
2559 if (!waitAll && fenceCount > 1) {
2560 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2561 }
2562
2563 for (uint32_t i = 0; i < fenceCount; ++i) {
2564 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2565 bool expired = false;
2566
2567 if (fence->signalled)
2568 continue;
2569
2570 if (!fence->submitted)
2571 return VK_TIMEOUT;
2572
2573 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2574 if (!expired)
2575 return VK_TIMEOUT;
2576
2577 fence->signalled = true;
2578 }
2579
2580 return VK_SUCCESS;
2581 }
2582
2583 VkResult radv_ResetFences(VkDevice device,
2584 uint32_t fenceCount,
2585 const VkFence *pFences)
2586 {
2587 for (unsigned i = 0; i < fenceCount; ++i) {
2588 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2589 fence->submitted = fence->signalled = false;
2590 }
2591
2592 return VK_SUCCESS;
2593 }
2594
2595 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2596 {
2597 RADV_FROM_HANDLE(radv_device, device, _device);
2598 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2599
2600 if (fence->signalled)
2601 return VK_SUCCESS;
2602 if (!fence->submitted)
2603 return VK_NOT_READY;
2604
2605 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2606 return VK_NOT_READY;
2607
2608 return VK_SUCCESS;
2609 }
2610
2611
2612 // Queue semaphore functions
2613
2614 VkResult radv_CreateSemaphore(
2615 VkDevice _device,
2616 const VkSemaphoreCreateInfo* pCreateInfo,
2617 const VkAllocationCallbacks* pAllocator,
2618 VkSemaphore* pSemaphore)
2619 {
2620 RADV_FROM_HANDLE(radv_device, device, _device);
2621 const VkExportSemaphoreCreateInfoKHR *export =
2622 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2623 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2624 export ? export->handleTypes : 0;
2625
2626 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2627 sizeof(*sem), 8,
2628 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2629 if (!sem)
2630 return VK_ERROR_OUT_OF_HOST_MEMORY;
2631
2632 sem->temp_syncobj = 0;
2633 /* create a syncobject if we are going to export this semaphore */
2634 if (handleTypes) {
2635 assert (device->physical_device->rad_info.has_syncobj);
2636 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2637 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2638 if (ret) {
2639 vk_free2(&device->alloc, pAllocator, sem);
2640 return VK_ERROR_OUT_OF_HOST_MEMORY;
2641 }
2642 sem->sem = NULL;
2643 } else {
2644 sem->sem = device->ws->create_sem(device->ws);
2645 if (!sem->sem) {
2646 vk_free2(&device->alloc, pAllocator, sem);
2647 return VK_ERROR_OUT_OF_HOST_MEMORY;
2648 }
2649 sem->syncobj = 0;
2650 }
2651
2652 *pSemaphore = radv_semaphore_to_handle(sem);
2653 return VK_SUCCESS;
2654 }
2655
2656 void radv_DestroySemaphore(
2657 VkDevice _device,
2658 VkSemaphore _semaphore,
2659 const VkAllocationCallbacks* pAllocator)
2660 {
2661 RADV_FROM_HANDLE(radv_device, device, _device);
2662 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2663 if (!_semaphore)
2664 return;
2665
2666 if (sem->syncobj)
2667 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2668 else
2669 device->ws->destroy_sem(sem->sem);
2670 vk_free2(&device->alloc, pAllocator, sem);
2671 }
2672
2673 VkResult radv_CreateEvent(
2674 VkDevice _device,
2675 const VkEventCreateInfo* pCreateInfo,
2676 const VkAllocationCallbacks* pAllocator,
2677 VkEvent* pEvent)
2678 {
2679 RADV_FROM_HANDLE(radv_device, device, _device);
2680 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2681 sizeof(*event), 8,
2682 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2683
2684 if (!event)
2685 return VK_ERROR_OUT_OF_HOST_MEMORY;
2686
2687 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2688 RADEON_DOMAIN_GTT,
2689 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2690 if (!event->bo) {
2691 vk_free2(&device->alloc, pAllocator, event);
2692 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2693 }
2694
2695 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2696
2697 *pEvent = radv_event_to_handle(event);
2698
2699 return VK_SUCCESS;
2700 }
2701
2702 void radv_DestroyEvent(
2703 VkDevice _device,
2704 VkEvent _event,
2705 const VkAllocationCallbacks* pAllocator)
2706 {
2707 RADV_FROM_HANDLE(radv_device, device, _device);
2708 RADV_FROM_HANDLE(radv_event, event, _event);
2709
2710 if (!event)
2711 return;
2712 device->ws->buffer_destroy(event->bo);
2713 vk_free2(&device->alloc, pAllocator, event);
2714 }
2715
2716 VkResult radv_GetEventStatus(
2717 VkDevice _device,
2718 VkEvent _event)
2719 {
2720 RADV_FROM_HANDLE(radv_event, event, _event);
2721
2722 if (*event->map == 1)
2723 return VK_EVENT_SET;
2724 return VK_EVENT_RESET;
2725 }
2726
2727 VkResult radv_SetEvent(
2728 VkDevice _device,
2729 VkEvent _event)
2730 {
2731 RADV_FROM_HANDLE(radv_event, event, _event);
2732 *event->map = 1;
2733
2734 return VK_SUCCESS;
2735 }
2736
2737 VkResult radv_ResetEvent(
2738 VkDevice _device,
2739 VkEvent _event)
2740 {
2741 RADV_FROM_HANDLE(radv_event, event, _event);
2742 *event->map = 0;
2743
2744 return VK_SUCCESS;
2745 }
2746
2747 VkResult radv_CreateBuffer(
2748 VkDevice _device,
2749 const VkBufferCreateInfo* pCreateInfo,
2750 const VkAllocationCallbacks* pAllocator,
2751 VkBuffer* pBuffer)
2752 {
2753 RADV_FROM_HANDLE(radv_device, device, _device);
2754 struct radv_buffer *buffer;
2755
2756 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2757
2758 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2759 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2760 if (buffer == NULL)
2761 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2762
2763 buffer->size = pCreateInfo->size;
2764 buffer->usage = pCreateInfo->usage;
2765 buffer->bo = NULL;
2766 buffer->offset = 0;
2767 buffer->flags = pCreateInfo->flags;
2768
2769 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2770 buffer->bo = device->ws->buffer_create(device->ws,
2771 align64(buffer->size, 4096),
2772 4096, 0, RADEON_FLAG_VIRTUAL);
2773 if (!buffer->bo) {
2774 vk_free2(&device->alloc, pAllocator, buffer);
2775 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2776 }
2777 }
2778
2779 *pBuffer = radv_buffer_to_handle(buffer);
2780
2781 return VK_SUCCESS;
2782 }
2783
2784 void radv_DestroyBuffer(
2785 VkDevice _device,
2786 VkBuffer _buffer,
2787 const VkAllocationCallbacks* pAllocator)
2788 {
2789 RADV_FROM_HANDLE(radv_device, device, _device);
2790 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2791
2792 if (!buffer)
2793 return;
2794
2795 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2796 device->ws->buffer_destroy(buffer->bo);
2797
2798 vk_free2(&device->alloc, pAllocator, buffer);
2799 }
2800
2801 static inline unsigned
2802 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2803 {
2804 if (stencil)
2805 return image->surface.u.legacy.stencil_tiling_index[level];
2806 else
2807 return image->surface.u.legacy.tiling_index[level];
2808 }
2809
2810 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2811 {
2812 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2813 }
2814
2815 static void
2816 radv_initialise_color_surface(struct radv_device *device,
2817 struct radv_color_buffer_info *cb,
2818 struct radv_image_view *iview)
2819 {
2820 const struct vk_format_description *desc;
2821 unsigned ntype, format, swap, endian;
2822 unsigned blend_clamp = 0, blend_bypass = 0;
2823 uint64_t va;
2824 const struct radeon_surf *surf = &iview->image->surface;
2825
2826 desc = vk_format_description(iview->vk_format);
2827
2828 memset(cb, 0, sizeof(*cb));
2829
2830 /* Intensity is implemented as Red, so treat it that way. */
2831 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2832
2833 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2834
2835 cb->cb_color_base = va >> 8;
2836
2837 if (device->physical_device->rad_info.chip_class >= GFX9) {
2838 struct gfx9_surf_meta_flags meta;
2839 if (iview->image->dcc_offset)
2840 meta = iview->image->surface.u.gfx9.dcc;
2841 else
2842 meta = iview->image->surface.u.gfx9.cmask;
2843
2844 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2845 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2846 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2847 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2848
2849 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2850 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2851 } else {
2852 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2853 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2854
2855 cb->cb_color_base += level_info->offset >> 8;
2856 if (level_info->mode == RADEON_SURF_MODE_2D)
2857 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2858
2859 pitch_tile_max = level_info->nblk_x / 8 - 1;
2860 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2861 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2862
2863 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2864 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2865 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2866
2867 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2868 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2869
2870 if (iview->image->fmask.size) {
2871 if (device->physical_device->rad_info.chip_class >= CIK)
2872 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2873 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2874 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2875 } else {
2876 /* This must be set for fast clear to work without FMASK. */
2877 if (device->physical_device->rad_info.chip_class >= CIK)
2878 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2879 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2880 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2881 }
2882 }
2883
2884 /* CMASK variables */
2885 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2886 va += iview->image->cmask.offset;
2887 cb->cb_color_cmask = va >> 8;
2888
2889 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2890 va += iview->image->dcc_offset;
2891 cb->cb_dcc_base = va >> 8;
2892 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2893
2894 uint32_t max_slice = radv_surface_layer_count(iview);
2895 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2896 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2897
2898 if (iview->image->info.samples > 1) {
2899 unsigned log_samples = util_logbase2(iview->image->info.samples);
2900
2901 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2902 S_028C74_NUM_FRAGMENTS(log_samples);
2903 }
2904
2905 if (iview->image->fmask.size) {
2906 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2907 cb->cb_color_fmask = va >> 8;
2908 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
2909 } else {
2910 cb->cb_color_fmask = cb->cb_color_base;
2911 }
2912
2913 ntype = radv_translate_color_numformat(iview->vk_format,
2914 desc,
2915 vk_format_get_first_non_void_channel(iview->vk_format));
2916 format = radv_translate_colorformat(iview->vk_format);
2917 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2918 radv_finishme("Illegal color\n");
2919 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2920 endian = radv_colorformat_endian_swap(format);
2921
2922 /* blend clamp should be set for all NORM/SRGB types */
2923 if (ntype == V_028C70_NUMBER_UNORM ||
2924 ntype == V_028C70_NUMBER_SNORM ||
2925 ntype == V_028C70_NUMBER_SRGB)
2926 blend_clamp = 1;
2927
2928 /* set blend bypass according to docs if SINT/UINT or
2929 8/24 COLOR variants */
2930 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2931 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2932 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2933 blend_clamp = 0;
2934 blend_bypass = 1;
2935 }
2936 #if 0
2937 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2938 (format == V_028C70_COLOR_8 ||
2939 format == V_028C70_COLOR_8_8 ||
2940 format == V_028C70_COLOR_8_8_8_8))
2941 ->color_is_int8 = true;
2942 #endif
2943 cb->cb_color_info = S_028C70_FORMAT(format) |
2944 S_028C70_COMP_SWAP(swap) |
2945 S_028C70_BLEND_CLAMP(blend_clamp) |
2946 S_028C70_BLEND_BYPASS(blend_bypass) |
2947 S_028C70_SIMPLE_FLOAT(1) |
2948 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2949 ntype != V_028C70_NUMBER_SNORM &&
2950 ntype != V_028C70_NUMBER_SRGB &&
2951 format != V_028C70_COLOR_8_24 &&
2952 format != V_028C70_COLOR_24_8) |
2953 S_028C70_NUMBER_TYPE(ntype) |
2954 S_028C70_ENDIAN(endian);
2955 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
2956 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2957 if (device->physical_device->rad_info.chip_class == SI) {
2958 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
2959 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2960 }
2961 }
2962
2963 if (iview->image->cmask.size &&
2964 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2965 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2966
2967 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
2968 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2969
2970 if (device->physical_device->rad_info.chip_class >= VI) {
2971 unsigned max_uncompressed_block_size = 2;
2972 if (iview->image->info.samples > 1) {
2973 if (iview->image->surface.bpe == 1)
2974 max_uncompressed_block_size = 0;
2975 else if (iview->image->surface.bpe == 2)
2976 max_uncompressed_block_size = 1;
2977 }
2978
2979 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2980 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2981 }
2982
2983 /* This must be set for fast clear to work without FMASK. */
2984 if (!iview->image->fmask.size &&
2985 device->physical_device->rad_info.chip_class == SI) {
2986 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
2987 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2988 }
2989
2990 if (device->physical_device->rad_info.chip_class >= GFX9) {
2991 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
2992 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
2993
2994 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
2995 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2996 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
2997 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
2998 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
2999 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3000
3001 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3002
3003 }
3004 }
3005
3006 static void
3007 radv_initialise_ds_surface(struct radv_device *device,
3008 struct radv_ds_buffer_info *ds,
3009 struct radv_image_view *iview)
3010 {
3011 unsigned level = iview->base_mip;
3012 unsigned format, stencil_format;
3013 uint64_t va, s_offs, z_offs;
3014 bool stencil_only = false;
3015 memset(ds, 0, sizeof(*ds));
3016 switch (iview->image->vk_format) {
3017 case VK_FORMAT_D24_UNORM_S8_UINT:
3018 case VK_FORMAT_X8_D24_UNORM_PACK32:
3019 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3020 ds->offset_scale = 2.0f;
3021 break;
3022 case VK_FORMAT_D16_UNORM:
3023 case VK_FORMAT_D16_UNORM_S8_UINT:
3024 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3025 ds->offset_scale = 4.0f;
3026 break;
3027 case VK_FORMAT_D32_SFLOAT:
3028 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3029 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3030 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3031 ds->offset_scale = 1.0f;
3032 break;
3033 case VK_FORMAT_S8_UINT:
3034 stencil_only = true;
3035 break;
3036 default:
3037 break;
3038 }
3039
3040 format = radv_translate_dbformat(iview->image->vk_format);
3041 stencil_format = iview->image->surface.has_stencil ?
3042 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3043
3044 uint32_t max_slice = radv_surface_layer_count(iview);
3045 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3046 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3047
3048 ds->db_htile_data_base = 0;
3049 ds->db_htile_surface = 0;
3050
3051 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3052 s_offs = z_offs = va;
3053
3054 if (device->physical_device->rad_info.chip_class >= GFX9) {
3055 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3056 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3057
3058 ds->db_z_info = S_028038_FORMAT(format) |
3059 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3060 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3061 S_028038_MAXMIP(iview->image->info.levels - 1);
3062 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3063 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3064
3065 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3066 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3067 ds->db_depth_view |= S_028008_MIPID(level);
3068
3069 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3070 S_02801C_Y_MAX(iview->image->info.height - 1);
3071
3072 if (radv_htile_enabled(iview->image, level)) {
3073 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3074
3075 if (iview->image->tc_compatible_htile) {
3076 unsigned max_zplanes = 4;
3077
3078 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3079 iview->image->info.samples > 1)
3080 max_zplanes = 2;
3081
3082 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3083 S_028038_ITERATE_FLUSH(1);
3084 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3085 }
3086
3087 if (!iview->image->surface.has_stencil)
3088 /* Use all of the htile_buffer for depth if there's no stencil. */
3089 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3090 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3091 iview->image->htile_offset;
3092 ds->db_htile_data_base = va >> 8;
3093 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3094 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3095 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3096 }
3097 } else {
3098 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3099
3100 if (stencil_only)
3101 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3102
3103 z_offs += iview->image->surface.u.legacy.level[level].offset;
3104 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3105
3106 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3107 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3108 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3109
3110 if (iview->image->info.samples > 1)
3111 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3112
3113 if (device->physical_device->rad_info.chip_class >= CIK) {
3114 struct radeon_info *info = &device->physical_device->rad_info;
3115 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3116 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3117 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3118 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3119 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3120 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3121
3122 if (stencil_only)
3123 tile_mode = stencil_tile_mode;
3124
3125 ds->db_depth_info |=
3126 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3127 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3128 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3129 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3130 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3131 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3132 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3133 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3134 } else {
3135 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3136 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3137 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3138 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3139 if (stencil_only)
3140 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3141 }
3142
3143 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3144 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3145 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3146
3147 if (radv_htile_enabled(iview->image, level)) {
3148 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3149
3150 if (!iview->image->surface.has_stencil &&
3151 !iview->image->tc_compatible_htile)
3152 /* Use all of the htile_buffer for depth if there's no stencil. */
3153 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3154
3155 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3156 iview->image->htile_offset;
3157 ds->db_htile_data_base = va >> 8;
3158 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3159
3160 if (iview->image->tc_compatible_htile) {
3161 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3162
3163 if (iview->image->info.samples <= 1)
3164 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3165 else if (iview->image->info.samples <= 4)
3166 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3167 else
3168 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3169 }
3170 }
3171 }
3172
3173 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3174 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3175 }
3176
3177 VkResult radv_CreateFramebuffer(
3178 VkDevice _device,
3179 const VkFramebufferCreateInfo* pCreateInfo,
3180 const VkAllocationCallbacks* pAllocator,
3181 VkFramebuffer* pFramebuffer)
3182 {
3183 RADV_FROM_HANDLE(radv_device, device, _device);
3184 struct radv_framebuffer *framebuffer;
3185
3186 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3187
3188 size_t size = sizeof(*framebuffer) +
3189 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3190 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3191 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3192 if (framebuffer == NULL)
3193 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3194
3195 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3196 framebuffer->width = pCreateInfo->width;
3197 framebuffer->height = pCreateInfo->height;
3198 framebuffer->layers = pCreateInfo->layers;
3199 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3200 VkImageView _iview = pCreateInfo->pAttachments[i];
3201 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3202 framebuffer->attachments[i].attachment = iview;
3203 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3204 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3205 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3206 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3207 }
3208 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3209 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3210 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3211 }
3212
3213 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3214 return VK_SUCCESS;
3215 }
3216
3217 void radv_DestroyFramebuffer(
3218 VkDevice _device,
3219 VkFramebuffer _fb,
3220 const VkAllocationCallbacks* pAllocator)
3221 {
3222 RADV_FROM_HANDLE(radv_device, device, _device);
3223 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3224
3225 if (!fb)
3226 return;
3227 vk_free2(&device->alloc, pAllocator, fb);
3228 }
3229
3230 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3231 {
3232 switch (address_mode) {
3233 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3234 return V_008F30_SQ_TEX_WRAP;
3235 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3236 return V_008F30_SQ_TEX_MIRROR;
3237 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3238 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3239 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3240 return V_008F30_SQ_TEX_CLAMP_BORDER;
3241 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3242 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3243 default:
3244 unreachable("illegal tex wrap mode");
3245 break;
3246 }
3247 }
3248
3249 static unsigned
3250 radv_tex_compare(VkCompareOp op)
3251 {
3252 switch (op) {
3253 case VK_COMPARE_OP_NEVER:
3254 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3255 case VK_COMPARE_OP_LESS:
3256 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3257 case VK_COMPARE_OP_EQUAL:
3258 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3259 case VK_COMPARE_OP_LESS_OR_EQUAL:
3260 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3261 case VK_COMPARE_OP_GREATER:
3262 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3263 case VK_COMPARE_OP_NOT_EQUAL:
3264 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3265 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3266 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3267 case VK_COMPARE_OP_ALWAYS:
3268 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3269 default:
3270 unreachable("illegal compare mode");
3271 break;
3272 }
3273 }
3274
3275 static unsigned
3276 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3277 {
3278 switch (filter) {
3279 case VK_FILTER_NEAREST:
3280 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3281 V_008F38_SQ_TEX_XY_FILTER_POINT);
3282 case VK_FILTER_LINEAR:
3283 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3284 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3285 case VK_FILTER_CUBIC_IMG:
3286 default:
3287 fprintf(stderr, "illegal texture filter");
3288 return 0;
3289 }
3290 }
3291
3292 static unsigned
3293 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3294 {
3295 switch (mode) {
3296 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3297 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3298 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3299 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3300 default:
3301 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3302 }
3303 }
3304
3305 static unsigned
3306 radv_tex_bordercolor(VkBorderColor bcolor)
3307 {
3308 switch (bcolor) {
3309 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3310 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3311 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3312 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3313 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3314 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3315 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3316 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3317 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3318 default:
3319 break;
3320 }
3321 return 0;
3322 }
3323
3324 static unsigned
3325 radv_tex_aniso_filter(unsigned filter)
3326 {
3327 if (filter < 2)
3328 return 0;
3329 if (filter < 4)
3330 return 1;
3331 if (filter < 8)
3332 return 2;
3333 if (filter < 16)
3334 return 3;
3335 return 4;
3336 }
3337
3338 static void
3339 radv_init_sampler(struct radv_device *device,
3340 struct radv_sampler *sampler,
3341 const VkSamplerCreateInfo *pCreateInfo)
3342 {
3343 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3344 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3345 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3346 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3347
3348 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3349 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3350 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3351 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3352 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3353 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3354 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3355 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3356 S_008F30_DISABLE_CUBE_WRAP(0) |
3357 S_008F30_COMPAT_MODE(is_vi));
3358 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3359 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3360 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3361 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3362 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3363 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3364 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3365 S_008F38_MIP_POINT_PRECLAMP(0) |
3366 S_008F38_DISABLE_LSB_CEIL(1) |
3367 S_008F38_FILTER_PREC_FIX(1) |
3368 S_008F38_ANISO_OVERRIDE(is_vi));
3369 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3370 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3371 }
3372
3373 VkResult radv_CreateSampler(
3374 VkDevice _device,
3375 const VkSamplerCreateInfo* pCreateInfo,
3376 const VkAllocationCallbacks* pAllocator,
3377 VkSampler* pSampler)
3378 {
3379 RADV_FROM_HANDLE(radv_device, device, _device);
3380 struct radv_sampler *sampler;
3381
3382 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3383
3384 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3385 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3386 if (!sampler)
3387 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3388
3389 radv_init_sampler(device, sampler, pCreateInfo);
3390 *pSampler = radv_sampler_to_handle(sampler);
3391
3392 return VK_SUCCESS;
3393 }
3394
3395 void radv_DestroySampler(
3396 VkDevice _device,
3397 VkSampler _sampler,
3398 const VkAllocationCallbacks* pAllocator)
3399 {
3400 RADV_FROM_HANDLE(radv_device, device, _device);
3401 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3402
3403 if (!sampler)
3404 return;
3405 vk_free2(&device->alloc, pAllocator, sampler);
3406 }
3407
3408 /* vk_icd.h does not declare this function, so we declare it here to
3409 * suppress Wmissing-prototypes.
3410 */
3411 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3412 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3413
3414 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3415 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3416 {
3417 /* For the full details on loader interface versioning, see
3418 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3419 * What follows is a condensed summary, to help you navigate the large and
3420 * confusing official doc.
3421 *
3422 * - Loader interface v0 is incompatible with later versions. We don't
3423 * support it.
3424 *
3425 * - In loader interface v1:
3426 * - The first ICD entrypoint called by the loader is
3427 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3428 * entrypoint.
3429 * - The ICD must statically expose no other Vulkan symbol unless it is
3430 * linked with -Bsymbolic.
3431 * - Each dispatchable Vulkan handle created by the ICD must be
3432 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3433 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3434 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3435 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3436 * such loader-managed surfaces.
3437 *
3438 * - Loader interface v2 differs from v1 in:
3439 * - The first ICD entrypoint called by the loader is
3440 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3441 * statically expose this entrypoint.
3442 *
3443 * - Loader interface v3 differs from v2 in:
3444 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3445 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3446 * because the loader no longer does so.
3447 */
3448 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3449 return VK_SUCCESS;
3450 }
3451
3452 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3453 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3454 int *pFD)
3455 {
3456 RADV_FROM_HANDLE(radv_device, device, _device);
3457 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3458
3459 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3460
3461 /* We support only one handle type. */
3462 assert(pGetFdInfo->handleType ==
3463 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3464
3465 bool ret = radv_get_memory_fd(device, memory, pFD);
3466 if (ret == false)
3467 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3468 return VK_SUCCESS;
3469 }
3470
3471 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3472 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3473 int fd,
3474 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3475 {
3476 /* The valid usage section for this function says:
3477 *
3478 * "handleType must not be one of the handle types defined as opaque."
3479 *
3480 * Since we only handle opaque handles for now, there are no FD properties.
3481 */
3482 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3483 }
3484
3485 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3486 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3487 {
3488 RADV_FROM_HANDLE(radv_device, device, _device);
3489 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3490 uint32_t syncobj_handle = 0;
3491 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3492
3493 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3494 if (ret != 0)
3495 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3496
3497 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3498 sem->temp_syncobj = syncobj_handle;
3499 } else {
3500 sem->syncobj = syncobj_handle;
3501 }
3502 close(pImportSemaphoreFdInfo->fd);
3503 return VK_SUCCESS;
3504 }
3505
3506 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3507 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3508 int *pFd)
3509 {
3510 RADV_FROM_HANDLE(radv_device, device, _device);
3511 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3512 int ret;
3513 uint32_t syncobj_handle;
3514
3515 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3516 if (sem->temp_syncobj)
3517 syncobj_handle = sem->temp_syncobj;
3518 else
3519 syncobj_handle = sem->syncobj;
3520 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3521 if (ret)
3522 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3523 return VK_SUCCESS;
3524 }
3525
3526 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3527 VkPhysicalDevice physicalDevice,
3528 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3529 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3530 {
3531 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3532 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3533 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3534 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3535 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3536 } else {
3537 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3538 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3539 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3540 }
3541 }