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Revert "anv/radv: release memory allocated by glsl types during spirv_to_nir"
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->driver_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
373 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
374 (device->rad_info.chip_class >= VI &&
375 device->rad_info.me_fw_feature >= 41);
376
377 radv_physical_device_init_mem_types(device);
378 radv_fill_device_extension_table(device, &device->supported_extensions);
379
380 device->bus_info = *drm_device->businfo.pci;
381
382 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
383 ac_print_gpu_info(&device->rad_info);
384
385 /* The WSI is structured as a layer on top of the driver, so this has
386 * to be the last part of initialization (at least until we get other
387 * semi-layers).
388 */
389 result = radv_init_wsi(device);
390 if (result != VK_SUCCESS) {
391 device->ws->destroy(device->ws);
392 vk_error(instance, result);
393 goto fail;
394 }
395
396 return VK_SUCCESS;
397
398 fail:
399 close(fd);
400 if (master_fd != -1)
401 close(master_fd);
402 return result;
403 }
404
405 static void
406 radv_physical_device_finish(struct radv_physical_device *device)
407 {
408 radv_finish_wsi(device);
409 device->ws->destroy(device->ws);
410 disk_cache_destroy(device->disk_cache);
411 close(device->local_fd);
412 if (device->master_fd != -1)
413 close(device->master_fd);
414 }
415
416 static void *
417 default_alloc_func(void *pUserData, size_t size, size_t align,
418 VkSystemAllocationScope allocationScope)
419 {
420 return malloc(size);
421 }
422
423 static void *
424 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
425 size_t align, VkSystemAllocationScope allocationScope)
426 {
427 return realloc(pOriginal, size);
428 }
429
430 static void
431 default_free_func(void *pUserData, void *pMemory)
432 {
433 free(pMemory);
434 }
435
436 static const VkAllocationCallbacks default_alloc = {
437 .pUserData = NULL,
438 .pfnAllocation = default_alloc_func,
439 .pfnReallocation = default_realloc_func,
440 .pfnFree = default_free_func,
441 };
442
443 static const struct debug_control radv_debug_options[] = {
444 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
445 {"nodcc", RADV_DEBUG_NO_DCC},
446 {"shaders", RADV_DEBUG_DUMP_SHADERS},
447 {"nocache", RADV_DEBUG_NO_CACHE},
448 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
449 {"nohiz", RADV_DEBUG_NO_HIZ},
450 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
451 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
452 {"allbos", RADV_DEBUG_ALL_BOS},
453 {"noibs", RADV_DEBUG_NO_IBS},
454 {"spirv", RADV_DEBUG_DUMP_SPIRV},
455 {"vmfaults", RADV_DEBUG_VM_FAULTS},
456 {"zerovram", RADV_DEBUG_ZERO_VRAM},
457 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
458 {"nosisched", RADV_DEBUG_NO_SISCHED},
459 {"preoptir", RADV_DEBUG_PREOPTIR},
460 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
461 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
462 {"info", RADV_DEBUG_INFO},
463 {"errors", RADV_DEBUG_ERRORS},
464 {"startup", RADV_DEBUG_STARTUP},
465 {"checkir", RADV_DEBUG_CHECKIR},
466 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
467 {"nobinning", RADV_DEBUG_NOBINNING},
468 {NULL, 0}
469 };
470
471 const char *
472 radv_get_debug_option_name(int id)
473 {
474 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
475 return radv_debug_options[id].string;
476 }
477
478 static const struct debug_control radv_perftest_options[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
480 {"sisched", RADV_PERFTEST_SISCHED},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525
526 VkResult radv_CreateInstance(
527 const VkInstanceCreateInfo* pCreateInfo,
528 const VkAllocationCallbacks* pAllocator,
529 VkInstance* pInstance)
530 {
531 struct radv_instance *instance;
532 VkResult result;
533
534 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
535
536 uint32_t client_version;
537 if (pCreateInfo->pApplicationInfo &&
538 pCreateInfo->pApplicationInfo->apiVersion != 0) {
539 client_version = pCreateInfo->pApplicationInfo->apiVersion;
540 } else {
541 client_version = VK_API_VERSION_1_0;
542 }
543
544 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
545 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
546 if (!instance)
547 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
550
551 if (pAllocator)
552 instance->alloc = *pAllocator;
553 else
554 instance->alloc = default_alloc;
555
556 instance->apiVersion = client_version;
557 instance->physicalDeviceCount = -1;
558
559 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
560 radv_debug_options);
561
562 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
563 radv_perftest_options);
564
565
566 if (instance->debug_flags & RADV_DEBUG_STARTUP)
567 radv_logi("Created an instance");
568
569 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
570 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
571 int index = radv_get_instance_extension_index(ext_name);
572
573 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
574 vk_free2(&default_alloc, pAllocator, instance);
575 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
576 }
577
578 instance->enabled_extensions.extensions[index] = true;
579 }
580
581 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
582 if (result != VK_SUCCESS) {
583 vk_free2(&default_alloc, pAllocator, instance);
584 return vk_error(instance, result);
585 }
586
587 _mesa_locale_init();
588
589 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
590
591 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
592
593 *pInstance = radv_instance_to_handle(instance);
594
595 return VK_SUCCESS;
596 }
597
598 void radv_DestroyInstance(
599 VkInstance _instance,
600 const VkAllocationCallbacks* pAllocator)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603
604 if (!instance)
605 return;
606
607 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
608 radv_physical_device_finish(instance->physicalDevices + i);
609 }
610
611 VG(VALGRIND_DESTROY_MEMPOOL(instance));
612
613 _mesa_locale_fini();
614
615 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
616
617 vk_free(&instance->alloc, instance);
618 }
619
620 static VkResult
621 radv_enumerate_devices(struct radv_instance *instance)
622 {
623 /* TODO: Check for more devices ? */
624 drmDevicePtr devices[8];
625 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
626 int max_devices;
627
628 instance->physicalDeviceCount = 0;
629
630 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
631
632 if (instance->debug_flags & RADV_DEBUG_STARTUP)
633 radv_logi("Found %d drm nodes", max_devices);
634
635 if (max_devices < 1)
636 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
637
638 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
639 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
640 devices[i]->bustype == DRM_BUS_PCI &&
641 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
642
643 result = radv_physical_device_init(instance->physicalDevices +
644 instance->physicalDeviceCount,
645 instance,
646 devices[i]);
647 if (result == VK_SUCCESS)
648 ++instance->physicalDeviceCount;
649 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
650 break;
651 }
652 }
653 drmFreeDevices(devices, max_devices);
654
655 return result;
656 }
657
658 VkResult radv_EnumeratePhysicalDevices(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceCount,
661 VkPhysicalDevice* pPhysicalDevices)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDevices) {
674 *pPhysicalDeviceCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
678 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
679 }
680
681 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
682 : VK_SUCCESS;
683 }
684
685 VkResult radv_EnumeratePhysicalDeviceGroups(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceGroupCount,
688 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDeviceGroupProperties) {
701 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
705 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
706 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
708 }
709 }
710 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
711 : VK_SUCCESS;
712 }
713
714 void radv_GetPhysicalDeviceFeatures(
715 VkPhysicalDevice physicalDevice,
716 VkPhysicalDeviceFeatures* pFeatures)
717 {
718 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
719 memset(pFeatures, 0, sizeof(*pFeatures));
720
721 *pFeatures = (VkPhysicalDeviceFeatures) {
722 .robustBufferAccess = true,
723 .fullDrawIndexUint32 = true,
724 .imageCubeArray = true,
725 .independentBlend = true,
726 .geometryShader = true,
727 .tessellationShader = true,
728 .sampleRateShading = true,
729 .dualSrcBlend = true,
730 .logicOp = true,
731 .multiDrawIndirect = true,
732 .drawIndirectFirstInstance = true,
733 .depthClamp = true,
734 .depthBiasClamp = true,
735 .fillModeNonSolid = true,
736 .depthBounds = true,
737 .wideLines = true,
738 .largePoints = true,
739 .alphaToOne = true,
740 .multiViewport = true,
741 .samplerAnisotropy = true,
742 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
743 .textureCompressionASTC_LDR = false,
744 .textureCompressionBC = true,
745 .occlusionQueryPrecise = true,
746 .pipelineStatisticsQuery = true,
747 .vertexPipelineStoresAndAtomics = true,
748 .fragmentStoresAndAtomics = true,
749 .shaderTessellationAndGeometryPointSize = true,
750 .shaderImageGatherExtended = true,
751 .shaderStorageImageExtendedFormats = true,
752 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
753 .shaderUniformBufferArrayDynamicIndexing = true,
754 .shaderSampledImageArrayDynamicIndexing = true,
755 .shaderStorageBufferArrayDynamicIndexing = true,
756 .shaderStorageImageArrayDynamicIndexing = true,
757 .shaderStorageImageReadWithoutFormat = true,
758 .shaderStorageImageWriteWithoutFormat = true,
759 .shaderClipDistance = true,
760 .shaderCullDistance = true,
761 .shaderFloat64 = true,
762 .shaderInt64 = true,
763 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
764 .sparseBinding = true,
765 .variableMultisampleRate = true,
766 .inheritedQueries = true,
767 };
768 }
769
770 void radv_GetPhysicalDeviceFeatures2(
771 VkPhysicalDevice physicalDevice,
772 VkPhysicalDeviceFeatures2 *pFeatures)
773 {
774 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
775 vk_foreach_struct(ext, pFeatures->pNext) {
776 switch (ext->sType) {
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
778 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
779 features->variablePointersStorageBuffer = true;
780 features->variablePointers = true;
781 break;
782 }
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
784 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
785 features->multiview = true;
786 features->multiviewGeometryShader = true;
787 features->multiviewTessellationShader = true;
788 break;
789 }
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
791 VkPhysicalDeviceShaderDrawParameterFeatures *features =
792 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
793 features->shaderDrawParameters = true;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
797 VkPhysicalDeviceProtectedMemoryFeatures *features =
798 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
799 features->protectedMemory = false;
800 break;
801 }
802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
803 VkPhysicalDevice16BitStorageFeatures *features =
804 (VkPhysicalDevice16BitStorageFeatures*)ext;
805 bool enabled = pdevice->rad_info.chip_class >= VI;
806 features->storageBuffer16BitAccess = enabled;
807 features->uniformAndStorageBuffer16BitAccess = enabled;
808 features->storagePushConstant16 = enabled;
809 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
810 break;
811 }
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
813 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
814 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
815 features->samplerYcbcrConversion = false;
816 break;
817 }
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
819 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
820 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
821 features->shaderInputAttachmentArrayDynamicIndexing = true;
822 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
823 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
824 features->shaderUniformBufferArrayNonUniformIndexing = false;
825 features->shaderSampledImageArrayNonUniformIndexing = false;
826 features->shaderStorageBufferArrayNonUniformIndexing = false;
827 features->shaderStorageImageArrayNonUniformIndexing = false;
828 features->shaderInputAttachmentArrayNonUniformIndexing = false;
829 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
830 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
831 features->descriptorBindingUniformBufferUpdateAfterBind = true;
832 features->descriptorBindingSampledImageUpdateAfterBind = true;
833 features->descriptorBindingStorageImageUpdateAfterBind = true;
834 features->descriptorBindingStorageBufferUpdateAfterBind = true;
835 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
836 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
837 features->descriptorBindingUpdateUnusedWhilePending = true;
838 features->descriptorBindingPartiallyBound = true;
839 features->descriptorBindingVariableDescriptorCount = true;
840 features->runtimeDescriptorArray = true;
841 break;
842 }
843 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
844 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
845 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
846 features->conditionalRendering = true;
847 features->inheritedConditionalRendering = false;
848 break;
849 }
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
851 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
852 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
853 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
854 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
858 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
859 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
860 features->transformFeedback = true;
861 features->geometryStreams = true;
862 break;
863 }
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
865 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
866 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
867 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
871 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
872 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
873 features->memoryPriority = VK_TRUE;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
877 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
878 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
879 features->bufferDeviceAddress = true;
880 features->bufferDeviceAddressCaptureReplay = false;
881 features->bufferDeviceAddressMultiDevice = false;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
885 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
886 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
887 features->depthClipEnable = true;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
891 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
892 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
893 features->hostQueryReset = true;
894 break;
895 }
896 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
897 VkPhysicalDevice8BitStorageFeaturesKHR *features =
898 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
899 bool enabled = pdevice->rad_info.chip_class >= VI;
900 features->storageBuffer8BitAccess = enabled;
901 features->uniformAndStorageBuffer8BitAccess = enabled;
902 features->storagePushConstant8 = enabled;
903 break;
904 }
905 default:
906 break;
907 }
908 }
909 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
910 }
911
912 void radv_GetPhysicalDeviceProperties(
913 VkPhysicalDevice physicalDevice,
914 VkPhysicalDeviceProperties* pProperties)
915 {
916 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
917 VkSampleCountFlags sample_counts = 0xf;
918
919 /* make sure that the entire descriptor set is addressable with a signed
920 * 32-bit int. So the sum of all limits scaled by descriptor size has to
921 * be at most 2 GiB. the combined image & samples object count as one of
922 * both. This limit is for the pipeline layout, not for the set layout, but
923 * there is no set limit, so we just set a pipeline limit. I don't think
924 * any app is going to hit this soon. */
925 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
926 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
927 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
928 32 /* sampler, largest when combined with image */ +
929 64 /* sampled image */ +
930 64 /* storage image */);
931
932 VkPhysicalDeviceLimits limits = {
933 .maxImageDimension1D = (1 << 14),
934 .maxImageDimension2D = (1 << 14),
935 .maxImageDimension3D = (1 << 11),
936 .maxImageDimensionCube = (1 << 14),
937 .maxImageArrayLayers = (1 << 11),
938 .maxTexelBufferElements = 128 * 1024 * 1024,
939 .maxUniformBufferRange = UINT32_MAX,
940 .maxStorageBufferRange = UINT32_MAX,
941 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
942 .maxMemoryAllocationCount = UINT32_MAX,
943 .maxSamplerAllocationCount = 64 * 1024,
944 .bufferImageGranularity = 64, /* A cache line */
945 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
946 .maxBoundDescriptorSets = MAX_SETS,
947 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
948 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
949 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
950 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
951 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
952 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
953 .maxPerStageResources = max_descriptor_set_size,
954 .maxDescriptorSetSamplers = max_descriptor_set_size,
955 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
956 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
957 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
958 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
959 .maxDescriptorSetSampledImages = max_descriptor_set_size,
960 .maxDescriptorSetStorageImages = max_descriptor_set_size,
961 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
962 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
963 .maxVertexInputBindings = MAX_VBS,
964 .maxVertexInputAttributeOffset = 2047,
965 .maxVertexInputBindingStride = 2048,
966 .maxVertexOutputComponents = 128,
967 .maxTessellationGenerationLevel = 64,
968 .maxTessellationPatchSize = 32,
969 .maxTessellationControlPerVertexInputComponents = 128,
970 .maxTessellationControlPerVertexOutputComponents = 128,
971 .maxTessellationControlPerPatchOutputComponents = 120,
972 .maxTessellationControlTotalOutputComponents = 4096,
973 .maxTessellationEvaluationInputComponents = 128,
974 .maxTessellationEvaluationOutputComponents = 128,
975 .maxGeometryShaderInvocations = 127,
976 .maxGeometryInputComponents = 64,
977 .maxGeometryOutputComponents = 128,
978 .maxGeometryOutputVertices = 256,
979 .maxGeometryTotalOutputComponents = 1024,
980 .maxFragmentInputComponents = 128,
981 .maxFragmentOutputAttachments = 8,
982 .maxFragmentDualSrcAttachments = 1,
983 .maxFragmentCombinedOutputResources = 8,
984 .maxComputeSharedMemorySize = 32768,
985 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
986 .maxComputeWorkGroupInvocations = 2048,
987 .maxComputeWorkGroupSize = {
988 2048,
989 2048,
990 2048
991 },
992 .subPixelPrecisionBits = 8,
993 .subTexelPrecisionBits = 8,
994 .mipmapPrecisionBits = 8,
995 .maxDrawIndexedIndexValue = UINT32_MAX,
996 .maxDrawIndirectCount = UINT32_MAX,
997 .maxSamplerLodBias = 16,
998 .maxSamplerAnisotropy = 16,
999 .maxViewports = MAX_VIEWPORTS,
1000 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1001 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1002 .viewportSubPixelBits = 8,
1003 .minMemoryMapAlignment = 4096, /* A page */
1004 .minTexelBufferOffsetAlignment = 1,
1005 .minUniformBufferOffsetAlignment = 4,
1006 .minStorageBufferOffsetAlignment = 4,
1007 .minTexelOffset = -32,
1008 .maxTexelOffset = 31,
1009 .minTexelGatherOffset = -32,
1010 .maxTexelGatherOffset = 31,
1011 .minInterpolationOffset = -2,
1012 .maxInterpolationOffset = 2,
1013 .subPixelInterpolationOffsetBits = 8,
1014 .maxFramebufferWidth = (1 << 14),
1015 .maxFramebufferHeight = (1 << 14),
1016 .maxFramebufferLayers = (1 << 10),
1017 .framebufferColorSampleCounts = sample_counts,
1018 .framebufferDepthSampleCounts = sample_counts,
1019 .framebufferStencilSampleCounts = sample_counts,
1020 .framebufferNoAttachmentsSampleCounts = sample_counts,
1021 .maxColorAttachments = MAX_RTS,
1022 .sampledImageColorSampleCounts = sample_counts,
1023 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1024 .sampledImageDepthSampleCounts = sample_counts,
1025 .sampledImageStencilSampleCounts = sample_counts,
1026 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1027 .maxSampleMaskWords = 1,
1028 .timestampComputeAndGraphics = true,
1029 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1030 .maxClipDistances = 8,
1031 .maxCullDistances = 8,
1032 .maxCombinedClipAndCullDistances = 8,
1033 .discreteQueuePriorities = 2,
1034 .pointSizeRange = { 0.0, 8192.0 },
1035 .lineWidthRange = { 0.0, 7.9921875 },
1036 .pointSizeGranularity = (1.0 / 8.0),
1037 .lineWidthGranularity = (1.0 / 128.0),
1038 .strictLines = false, /* FINISHME */
1039 .standardSampleLocations = true,
1040 .optimalBufferCopyOffsetAlignment = 128,
1041 .optimalBufferCopyRowPitchAlignment = 128,
1042 .nonCoherentAtomSize = 64,
1043 };
1044
1045 *pProperties = (VkPhysicalDeviceProperties) {
1046 .apiVersion = radv_physical_device_api_version(pdevice),
1047 .driverVersion = vk_get_driver_version(),
1048 .vendorID = ATI_VENDOR_ID,
1049 .deviceID = pdevice->rad_info.pci_id,
1050 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1051 .limits = limits,
1052 .sparseProperties = {0},
1053 };
1054
1055 strcpy(pProperties->deviceName, pdevice->name);
1056 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1057 }
1058
1059 void radv_GetPhysicalDeviceProperties2(
1060 VkPhysicalDevice physicalDevice,
1061 VkPhysicalDeviceProperties2 *pProperties)
1062 {
1063 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1064 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1065
1066 vk_foreach_struct(ext, pProperties->pNext) {
1067 switch (ext->sType) {
1068 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1069 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1070 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1071 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1072 break;
1073 }
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1075 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1076 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1077 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1078 properties->deviceLUIDValid = false;
1079 break;
1080 }
1081 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1082 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1083 properties->maxMultiviewViewCount = MAX_VIEWS;
1084 properties->maxMultiviewInstanceIndex = INT_MAX;
1085 break;
1086 }
1087 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1088 VkPhysicalDevicePointClippingProperties *properties =
1089 (VkPhysicalDevicePointClippingProperties*)ext;
1090 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1091 break;
1092 }
1093 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1094 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1095 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1096 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1097 break;
1098 }
1099 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1100 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1101 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1102 properties->minImportedHostPointerAlignment = 4096;
1103 break;
1104 }
1105 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1106 VkPhysicalDeviceSubgroupProperties *properties =
1107 (VkPhysicalDeviceSubgroupProperties*)ext;
1108 properties->subgroupSize = 64;
1109 properties->supportedStages = VK_SHADER_STAGE_ALL;
1110 properties->supportedOperations =
1111 VK_SUBGROUP_FEATURE_BASIC_BIT |
1112 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1113 VK_SUBGROUP_FEATURE_QUAD_BIT |
1114 VK_SUBGROUP_FEATURE_VOTE_BIT;
1115 if (pdevice->rad_info.chip_class >= VI) {
1116 properties->supportedOperations |=
1117 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1118 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1119 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1120 }
1121 properties->quadOperationsInAllStages = true;
1122 break;
1123 }
1124 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1125 VkPhysicalDeviceMaintenance3Properties *properties =
1126 (VkPhysicalDeviceMaintenance3Properties*)ext;
1127 /* Make sure everything is addressable by a signed 32-bit int, and
1128 * our largest descriptors are 96 bytes. */
1129 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1130 /* Our buffer size fields allow only this much */
1131 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1132 break;
1133 }
1134 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1135 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1136 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1137 /* GFX6-8 only support single channel min/max filter. */
1138 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1139 properties->filterMinmaxSingleComponentFormats = true;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1143 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1144 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1145
1146 /* Shader engines. */
1147 properties->shaderEngineCount =
1148 pdevice->rad_info.max_se;
1149 properties->shaderArraysPerEngineCount =
1150 pdevice->rad_info.max_sh_per_se;
1151 properties->computeUnitsPerShaderArray =
1152 pdevice->rad_info.num_good_cu_per_sh;
1153 properties->simdPerComputeUnit = 4;
1154 properties->wavefrontsPerSimd =
1155 pdevice->rad_info.family == CHIP_TONGA ||
1156 pdevice->rad_info.family == CHIP_ICELAND ||
1157 pdevice->rad_info.family == CHIP_POLARIS10 ||
1158 pdevice->rad_info.family == CHIP_POLARIS11 ||
1159 pdevice->rad_info.family == CHIP_POLARIS12 ||
1160 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1161 properties->wavefrontSize = 64;
1162
1163 /* SGPR. */
1164 properties->sgprsPerSimd =
1165 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1166 properties->minSgprAllocation =
1167 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1168 properties->maxSgprAllocation =
1169 pdevice->rad_info.family == CHIP_TONGA ||
1170 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1171 properties->sgprAllocationGranularity =
1172 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1173
1174 /* VGPR. */
1175 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1176 properties->minVgprAllocation = 4;
1177 properties->maxVgprAllocation = 256;
1178 properties->vgprAllocationGranularity = 4;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1182 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1183 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1184 properties->maxVertexAttribDivisor = UINT32_MAX;
1185 break;
1186 }
1187 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1188 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1189 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1190 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1191 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1192 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1193 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1194 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1195 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1196 properties->robustBufferAccessUpdateAfterBind = false;
1197 properties->quadDivergentImplicitLod = false;
1198
1199 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1200 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1201 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1202 32 /* sampler, largest when combined with image */ +
1203 64 /* sampled image */ +
1204 64 /* storage image */);
1205 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1206 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1207 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1208 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1209 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1210 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1211 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1212 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1213 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1214 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1215 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1216 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1217 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1218 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1219 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1220 break;
1221 }
1222 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1223 VkPhysicalDeviceProtectedMemoryProperties *properties =
1224 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1225 properties->protectedNoFault = false;
1226 break;
1227 }
1228 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1229 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1230 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1231 properties->primitiveOverestimationSize = 0;
1232 properties->maxExtraPrimitiveOverestimationSize = 0;
1233 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1234 properties->primitiveUnderestimation = VK_FALSE;
1235 properties->conservativePointAndLineRasterization = VK_FALSE;
1236 properties->degenerateTrianglesRasterized = VK_FALSE;
1237 properties->degenerateLinesRasterized = VK_FALSE;
1238 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1239 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1240 break;
1241 }
1242 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1243 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1244 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1245 properties->pciDomain = pdevice->bus_info.domain;
1246 properties->pciBus = pdevice->bus_info.bus;
1247 properties->pciDevice = pdevice->bus_info.dev;
1248 properties->pciFunction = pdevice->bus_info.func;
1249 break;
1250 }
1251 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1252 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1253 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1254
1255 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1256 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1257 strcpy(driver_props->driverName, "radv");
1258
1259 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1260 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1261 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1262 " (LLVM %d.%d.%d)",
1263 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1264 MESA_LLVM_VERSION_PATCH);
1265
1266 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1267 .major = 1,
1268 .minor = 1,
1269 .subminor = 2,
1270 .patch = 0,
1271 };
1272 break;
1273 }
1274 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1275 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1276 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1277 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1278 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1279 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1280 properties->maxTransformFeedbackStreamDataSize = 512;
1281 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1282 properties->maxTransformFeedbackBufferDataStride = 512;
1283 properties->transformFeedbackQueries = true;
1284 properties->transformFeedbackStreamsLinesTriangles = false;
1285 properties->transformFeedbackRasterizationStreamSelect = false;
1286 properties->transformFeedbackDraw = true;
1287 break;
1288 }
1289 default:
1290 break;
1291 }
1292 }
1293 }
1294
1295 static void radv_get_physical_device_queue_family_properties(
1296 struct radv_physical_device* pdevice,
1297 uint32_t* pCount,
1298 VkQueueFamilyProperties** pQueueFamilyProperties)
1299 {
1300 int num_queue_families = 1;
1301 int idx;
1302 if (pdevice->rad_info.num_compute_rings > 0 &&
1303 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1304 num_queue_families++;
1305
1306 if (pQueueFamilyProperties == NULL) {
1307 *pCount = num_queue_families;
1308 return;
1309 }
1310
1311 if (!*pCount)
1312 return;
1313
1314 idx = 0;
1315 if (*pCount >= 1) {
1316 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1317 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1318 VK_QUEUE_COMPUTE_BIT |
1319 VK_QUEUE_TRANSFER_BIT |
1320 VK_QUEUE_SPARSE_BINDING_BIT,
1321 .queueCount = 1,
1322 .timestampValidBits = 64,
1323 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1324 };
1325 idx++;
1326 }
1327
1328 if (pdevice->rad_info.num_compute_rings > 0 &&
1329 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1330 if (*pCount > idx) {
1331 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1332 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1333 VK_QUEUE_TRANSFER_BIT |
1334 VK_QUEUE_SPARSE_BINDING_BIT,
1335 .queueCount = pdevice->rad_info.num_compute_rings,
1336 .timestampValidBits = 64,
1337 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1338 };
1339 idx++;
1340 }
1341 }
1342 *pCount = idx;
1343 }
1344
1345 void radv_GetPhysicalDeviceQueueFamilyProperties(
1346 VkPhysicalDevice physicalDevice,
1347 uint32_t* pCount,
1348 VkQueueFamilyProperties* pQueueFamilyProperties)
1349 {
1350 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1351 if (!pQueueFamilyProperties) {
1352 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1353 return;
1354 }
1355 VkQueueFamilyProperties *properties[] = {
1356 pQueueFamilyProperties + 0,
1357 pQueueFamilyProperties + 1,
1358 pQueueFamilyProperties + 2,
1359 };
1360 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1361 assert(*pCount <= 3);
1362 }
1363
1364 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1365 VkPhysicalDevice physicalDevice,
1366 uint32_t* pCount,
1367 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1368 {
1369 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1370 if (!pQueueFamilyProperties) {
1371 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1372 return;
1373 }
1374 VkQueueFamilyProperties *properties[] = {
1375 &pQueueFamilyProperties[0].queueFamilyProperties,
1376 &pQueueFamilyProperties[1].queueFamilyProperties,
1377 &pQueueFamilyProperties[2].queueFamilyProperties,
1378 };
1379 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1380 assert(*pCount <= 3);
1381 }
1382
1383 void radv_GetPhysicalDeviceMemoryProperties(
1384 VkPhysicalDevice physicalDevice,
1385 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1386 {
1387 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1388
1389 *pMemoryProperties = physical_device->memory_properties;
1390 }
1391
1392 static void
1393 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1394 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1395 {
1396 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1397 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1398 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1399 uint64_t vram_size = radv_get_vram_size(device);
1400 uint64_t gtt_size = device->rad_info.gart_size;
1401 uint64_t heap_budget, heap_usage;
1402
1403 /* For all memory heaps, the computation of budget is as follow:
1404 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1405 *
1406 * The Vulkan spec 1.1.97 says that the budget should include any
1407 * currently allocated device memory.
1408 *
1409 * Note that the application heap usages are not really accurate (eg.
1410 * in presence of shared buffers).
1411 */
1412 if (vram_size) {
1413 heap_usage = device->ws->query_value(device->ws,
1414 RADEON_ALLOCATED_VRAM);
1415
1416 heap_budget = vram_size -
1417 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1418 heap_usage;
1419
1420 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1421 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1422 }
1423
1424 if (visible_vram_size) {
1425 heap_usage = device->ws->query_value(device->ws,
1426 RADEON_ALLOCATED_VRAM_VIS);
1427
1428 heap_budget = visible_vram_size -
1429 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1430 heap_usage;
1431
1432 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1433 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1434 }
1435
1436 if (gtt_size) {
1437 heap_usage = device->ws->query_value(device->ws,
1438 RADEON_ALLOCATED_GTT);
1439
1440 heap_budget = gtt_size -
1441 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1442 heap_usage;
1443
1444 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1445 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1446 }
1447
1448 /* The heapBudget and heapUsage values must be zero for array elements
1449 * greater than or equal to
1450 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1451 */
1452 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1453 memoryBudget->heapBudget[i] = 0;
1454 memoryBudget->heapUsage[i] = 0;
1455 }
1456 }
1457
1458 void radv_GetPhysicalDeviceMemoryProperties2(
1459 VkPhysicalDevice physicalDevice,
1460 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1461 {
1462 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1463 &pMemoryProperties->memoryProperties);
1464
1465 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1466 vk_find_struct(pMemoryProperties->pNext,
1467 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1468 if (memory_budget)
1469 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1470 }
1471
1472 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1473 VkDevice _device,
1474 VkExternalMemoryHandleTypeFlagBits handleType,
1475 const void *pHostPointer,
1476 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1477 {
1478 RADV_FROM_HANDLE(radv_device, device, _device);
1479
1480 switch (handleType)
1481 {
1482 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1483 const struct radv_physical_device *physical_device = device->physical_device;
1484 uint32_t memoryTypeBits = 0;
1485 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1486 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1487 memoryTypeBits = (1 << i);
1488 break;
1489 }
1490 }
1491 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1492 return VK_SUCCESS;
1493 }
1494 default:
1495 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1496 }
1497 }
1498
1499 static enum radeon_ctx_priority
1500 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1501 {
1502 /* Default to MEDIUM when a specific global priority isn't requested */
1503 if (!pObj)
1504 return RADEON_CTX_PRIORITY_MEDIUM;
1505
1506 switch(pObj->globalPriority) {
1507 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1508 return RADEON_CTX_PRIORITY_REALTIME;
1509 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1510 return RADEON_CTX_PRIORITY_HIGH;
1511 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1512 return RADEON_CTX_PRIORITY_MEDIUM;
1513 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1514 return RADEON_CTX_PRIORITY_LOW;
1515 default:
1516 unreachable("Illegal global priority value");
1517 return RADEON_CTX_PRIORITY_INVALID;
1518 }
1519 }
1520
1521 static int
1522 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1523 uint32_t queue_family_index, int idx,
1524 VkDeviceQueueCreateFlags flags,
1525 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1526 {
1527 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1528 queue->device = device;
1529 queue->queue_family_index = queue_family_index;
1530 queue->queue_idx = idx;
1531 queue->priority = radv_get_queue_global_priority(global_priority);
1532 queue->flags = flags;
1533
1534 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1535 if (!queue->hw_ctx)
1536 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1537
1538 return VK_SUCCESS;
1539 }
1540
1541 static void
1542 radv_queue_finish(struct radv_queue *queue)
1543 {
1544 if (queue->hw_ctx)
1545 queue->device->ws->ctx_destroy(queue->hw_ctx);
1546
1547 if (queue->initial_full_flush_preamble_cs)
1548 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1549 if (queue->initial_preamble_cs)
1550 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1551 if (queue->continue_preamble_cs)
1552 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1553 if (queue->descriptor_bo)
1554 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1555 if (queue->scratch_bo)
1556 queue->device->ws->buffer_destroy(queue->scratch_bo);
1557 if (queue->esgs_ring_bo)
1558 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1559 if (queue->gsvs_ring_bo)
1560 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1561 if (queue->tess_rings_bo)
1562 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1563 if (queue->compute_scratch_bo)
1564 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1565 }
1566
1567 static void
1568 radv_bo_list_init(struct radv_bo_list *bo_list)
1569 {
1570 pthread_mutex_init(&bo_list->mutex, NULL);
1571 bo_list->list.count = bo_list->capacity = 0;
1572 bo_list->list.bos = NULL;
1573 }
1574
1575 static void
1576 radv_bo_list_finish(struct radv_bo_list *bo_list)
1577 {
1578 free(bo_list->list.bos);
1579 pthread_mutex_destroy(&bo_list->mutex);
1580 }
1581
1582 static VkResult radv_bo_list_add(struct radv_device *device,
1583 struct radeon_winsys_bo *bo)
1584 {
1585 struct radv_bo_list *bo_list = &device->bo_list;
1586
1587 if (bo->is_local)
1588 return VK_SUCCESS;
1589
1590 if (unlikely(!device->use_global_bo_list))
1591 return VK_SUCCESS;
1592
1593 pthread_mutex_lock(&bo_list->mutex);
1594 if (bo_list->list.count == bo_list->capacity) {
1595 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1596 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1597
1598 if (!data) {
1599 pthread_mutex_unlock(&bo_list->mutex);
1600 return VK_ERROR_OUT_OF_HOST_MEMORY;
1601 }
1602
1603 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1604 bo_list->capacity = capacity;
1605 }
1606
1607 bo_list->list.bos[bo_list->list.count++] = bo;
1608 pthread_mutex_unlock(&bo_list->mutex);
1609 return VK_SUCCESS;
1610 }
1611
1612 static void radv_bo_list_remove(struct radv_device *device,
1613 struct radeon_winsys_bo *bo)
1614 {
1615 struct radv_bo_list *bo_list = &device->bo_list;
1616
1617 if (bo->is_local)
1618 return;
1619
1620 if (unlikely(!device->use_global_bo_list))
1621 return;
1622
1623 pthread_mutex_lock(&bo_list->mutex);
1624 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1625 if (bo_list->list.bos[i] == bo) {
1626 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1627 --bo_list->list.count;
1628 break;
1629 }
1630 }
1631 pthread_mutex_unlock(&bo_list->mutex);
1632 }
1633
1634 static void
1635 radv_device_init_gs_info(struct radv_device *device)
1636 {
1637 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1638 device->physical_device->rad_info.family);
1639 }
1640
1641 static int radv_get_device_extension_index(const char *name)
1642 {
1643 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1644 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1645 return i;
1646 }
1647 return -1;
1648 }
1649
1650 static int
1651 radv_get_int_debug_option(const char *name, int default_value)
1652 {
1653 const char *str;
1654 int result;
1655
1656 str = getenv(name);
1657 if (!str) {
1658 result = default_value;
1659 } else {
1660 char *endptr;
1661
1662 result = strtol(str, &endptr, 0);
1663 if (str == endptr) {
1664 /* No digits founs. */
1665 result = default_value;
1666 }
1667 }
1668
1669 return result;
1670 }
1671
1672 VkResult radv_CreateDevice(
1673 VkPhysicalDevice physicalDevice,
1674 const VkDeviceCreateInfo* pCreateInfo,
1675 const VkAllocationCallbacks* pAllocator,
1676 VkDevice* pDevice)
1677 {
1678 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1679 VkResult result;
1680 struct radv_device *device;
1681
1682 bool keep_shader_info = false;
1683
1684 /* Check enabled features */
1685 if (pCreateInfo->pEnabledFeatures) {
1686 VkPhysicalDeviceFeatures supported_features;
1687 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1688 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1689 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1690 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1691 for (uint32_t i = 0; i < num_features; i++) {
1692 if (enabled_feature[i] && !supported_feature[i])
1693 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1694 }
1695 }
1696
1697 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1698 sizeof(*device), 8,
1699 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1700 if (!device)
1701 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1702
1703 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1704 device->instance = physical_device->instance;
1705 device->physical_device = physical_device;
1706
1707 device->ws = physical_device->ws;
1708 if (pAllocator)
1709 device->alloc = *pAllocator;
1710 else
1711 device->alloc = physical_device->instance->alloc;
1712
1713 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1714 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1715 int index = radv_get_device_extension_index(ext_name);
1716 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1717 vk_free(&device->alloc, device);
1718 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1719 }
1720
1721 device->enabled_extensions.extensions[index] = true;
1722 }
1723
1724 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1725
1726 /* With update after bind we can't attach bo's to the command buffer
1727 * from the descriptor set anymore, so we have to use a global BO list.
1728 */
1729 device->use_global_bo_list =
1730 device->enabled_extensions.EXT_descriptor_indexing ||
1731 device->enabled_extensions.EXT_buffer_device_address;
1732
1733 mtx_init(&device->shader_slab_mutex, mtx_plain);
1734 list_inithead(&device->shader_slabs);
1735
1736 radv_bo_list_init(&device->bo_list);
1737
1738 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1739 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1740 uint32_t qfi = queue_create->queueFamilyIndex;
1741 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1742 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1743
1744 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1745
1746 device->queues[qfi] = vk_alloc(&device->alloc,
1747 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1748 if (!device->queues[qfi]) {
1749 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1750 goto fail;
1751 }
1752
1753 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1754
1755 device->queue_count[qfi] = queue_create->queueCount;
1756
1757 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1758 result = radv_queue_init(device, &device->queues[qfi][q],
1759 qfi, q, queue_create->flags,
1760 global_priority);
1761 if (result != VK_SUCCESS)
1762 goto fail;
1763 }
1764 }
1765
1766 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1767 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1768
1769 /* Disabled and not implemented for now. */
1770 device->dfsm_allowed = device->pbb_allowed &&
1771 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1772 device->physical_device->rad_info.family == CHIP_RAVEN2);
1773
1774 #ifdef ANDROID
1775 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1776 #endif
1777
1778 /* The maximum number of scratch waves. Scratch space isn't divided
1779 * evenly between CUs. The number is only a function of the number of CUs.
1780 * We can decrease the constant to decrease the scratch buffer size.
1781 *
1782 * sctx->scratch_waves must be >= the maximum possible size of
1783 * 1 threadgroup, so that the hw doesn't hang from being unable
1784 * to start any.
1785 *
1786 * The recommended value is 4 per CU at most. Higher numbers don't
1787 * bring much benefit, but they still occupy chip resources (think
1788 * async compute). I've seen ~2% performance difference between 4 and 32.
1789 */
1790 uint32_t max_threads_per_block = 2048;
1791 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1792 max_threads_per_block / 64);
1793
1794 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1795
1796 if (device->physical_device->rad_info.chip_class >= CIK) {
1797 /* If the KMD allows it (there is a KMD hw register for it),
1798 * allow launching waves out-of-order.
1799 */
1800 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1801 }
1802
1803 radv_device_init_gs_info(device);
1804
1805 device->tess_offchip_block_dw_size =
1806 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1807 device->has_distributed_tess =
1808 device->physical_device->rad_info.chip_class >= VI &&
1809 device->physical_device->rad_info.max_se >= 2;
1810
1811 if (getenv("RADV_TRACE_FILE")) {
1812 const char *filename = getenv("RADV_TRACE_FILE");
1813
1814 keep_shader_info = true;
1815
1816 if (!radv_init_trace(device))
1817 goto fail;
1818
1819 fprintf(stderr, "*****************************************************************************\n");
1820 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1821 fprintf(stderr, "*****************************************************************************\n");
1822
1823 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1824 radv_dump_enabled_options(device, stderr);
1825 }
1826
1827 device->keep_shader_info = keep_shader_info;
1828
1829 result = radv_device_init_meta(device);
1830 if (result != VK_SUCCESS)
1831 goto fail;
1832
1833 radv_device_init_msaa(device);
1834
1835 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1836 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1837 switch (family) {
1838 case RADV_QUEUE_GENERAL:
1839 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1840 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1841 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1842 break;
1843 case RADV_QUEUE_COMPUTE:
1844 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1845 radeon_emit(device->empty_cs[family], 0);
1846 break;
1847 }
1848 device->ws->cs_finalize(device->empty_cs[family]);
1849 }
1850
1851 if (device->physical_device->rad_info.chip_class >= CIK)
1852 cik_create_gfx_config(device);
1853
1854 VkPipelineCacheCreateInfo ci;
1855 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1856 ci.pNext = NULL;
1857 ci.flags = 0;
1858 ci.pInitialData = NULL;
1859 ci.initialDataSize = 0;
1860 VkPipelineCache pc;
1861 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1862 &ci, NULL, &pc);
1863 if (result != VK_SUCCESS)
1864 goto fail_meta;
1865
1866 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1867
1868 device->force_aniso =
1869 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1870 if (device->force_aniso >= 0) {
1871 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1872 1 << util_logbase2(device->force_aniso));
1873 }
1874
1875 *pDevice = radv_device_to_handle(device);
1876 return VK_SUCCESS;
1877
1878 fail_meta:
1879 radv_device_finish_meta(device);
1880 fail:
1881 radv_bo_list_finish(&device->bo_list);
1882
1883 if (device->trace_bo)
1884 device->ws->buffer_destroy(device->trace_bo);
1885
1886 if (device->gfx_init)
1887 device->ws->buffer_destroy(device->gfx_init);
1888
1889 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1890 for (unsigned q = 0; q < device->queue_count[i]; q++)
1891 radv_queue_finish(&device->queues[i][q]);
1892 if (device->queue_count[i])
1893 vk_free(&device->alloc, device->queues[i]);
1894 }
1895
1896 vk_free(&device->alloc, device);
1897 return result;
1898 }
1899
1900 void radv_DestroyDevice(
1901 VkDevice _device,
1902 const VkAllocationCallbacks* pAllocator)
1903 {
1904 RADV_FROM_HANDLE(radv_device, device, _device);
1905
1906 if (!device)
1907 return;
1908
1909 if (device->trace_bo)
1910 device->ws->buffer_destroy(device->trace_bo);
1911
1912 if (device->gfx_init)
1913 device->ws->buffer_destroy(device->gfx_init);
1914
1915 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1916 for (unsigned q = 0; q < device->queue_count[i]; q++)
1917 radv_queue_finish(&device->queues[i][q]);
1918 if (device->queue_count[i])
1919 vk_free(&device->alloc, device->queues[i]);
1920 if (device->empty_cs[i])
1921 device->ws->cs_destroy(device->empty_cs[i]);
1922 }
1923 radv_device_finish_meta(device);
1924
1925 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1926 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1927
1928 radv_destroy_shader_slabs(device);
1929
1930 radv_bo_list_finish(&device->bo_list);
1931 vk_free(&device->alloc, device);
1932 }
1933
1934 VkResult radv_EnumerateInstanceLayerProperties(
1935 uint32_t* pPropertyCount,
1936 VkLayerProperties* pProperties)
1937 {
1938 if (pProperties == NULL) {
1939 *pPropertyCount = 0;
1940 return VK_SUCCESS;
1941 }
1942
1943 /* None supported at this time */
1944 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1945 }
1946
1947 VkResult radv_EnumerateDeviceLayerProperties(
1948 VkPhysicalDevice physicalDevice,
1949 uint32_t* pPropertyCount,
1950 VkLayerProperties* pProperties)
1951 {
1952 if (pProperties == NULL) {
1953 *pPropertyCount = 0;
1954 return VK_SUCCESS;
1955 }
1956
1957 /* None supported at this time */
1958 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1959 }
1960
1961 void radv_GetDeviceQueue2(
1962 VkDevice _device,
1963 const VkDeviceQueueInfo2* pQueueInfo,
1964 VkQueue* pQueue)
1965 {
1966 RADV_FROM_HANDLE(radv_device, device, _device);
1967 struct radv_queue *queue;
1968
1969 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1970 if (pQueueInfo->flags != queue->flags) {
1971 /* From the Vulkan 1.1.70 spec:
1972 *
1973 * "The queue returned by vkGetDeviceQueue2 must have the same
1974 * flags value from this structure as that used at device
1975 * creation time in a VkDeviceQueueCreateInfo instance. If no
1976 * matching flags were specified at device creation time then
1977 * pQueue will return VK_NULL_HANDLE."
1978 */
1979 *pQueue = VK_NULL_HANDLE;
1980 return;
1981 }
1982
1983 *pQueue = radv_queue_to_handle(queue);
1984 }
1985
1986 void radv_GetDeviceQueue(
1987 VkDevice _device,
1988 uint32_t queueFamilyIndex,
1989 uint32_t queueIndex,
1990 VkQueue* pQueue)
1991 {
1992 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1993 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1994 .queueFamilyIndex = queueFamilyIndex,
1995 .queueIndex = queueIndex
1996 };
1997
1998 radv_GetDeviceQueue2(_device, &info, pQueue);
1999 }
2000
2001 static void
2002 fill_geom_tess_rings(struct radv_queue *queue,
2003 uint32_t *map,
2004 bool add_sample_positions,
2005 uint32_t esgs_ring_size,
2006 struct radeon_winsys_bo *esgs_ring_bo,
2007 uint32_t gsvs_ring_size,
2008 struct radeon_winsys_bo *gsvs_ring_bo,
2009 uint32_t tess_factor_ring_size,
2010 uint32_t tess_offchip_ring_offset,
2011 uint32_t tess_offchip_ring_size,
2012 struct radeon_winsys_bo *tess_rings_bo)
2013 {
2014 uint32_t *desc = &map[4];
2015
2016 if (esgs_ring_bo) {
2017 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2018
2019 /* stride 0, num records - size, add tid, swizzle, elsize4,
2020 index stride 64 */
2021 desc[0] = esgs_va;
2022 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2023 S_008F04_STRIDE(0) |
2024 S_008F04_SWIZZLE_ENABLE(true);
2025 desc[2] = esgs_ring_size;
2026 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2027 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2028 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2029 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2030 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2031 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2032 S_008F0C_ELEMENT_SIZE(1) |
2033 S_008F0C_INDEX_STRIDE(3) |
2034 S_008F0C_ADD_TID_ENABLE(true);
2035
2036 /* GS entry for ES->GS ring */
2037 /* stride 0, num records - size, elsize0,
2038 index stride 0 */
2039 desc[4] = esgs_va;
2040 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2041 S_008F04_STRIDE(0) |
2042 S_008F04_SWIZZLE_ENABLE(false);
2043 desc[6] = esgs_ring_size;
2044 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2045 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2046 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2047 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2048 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2049 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2050 S_008F0C_ELEMENT_SIZE(0) |
2051 S_008F0C_INDEX_STRIDE(0) |
2052 S_008F0C_ADD_TID_ENABLE(false);
2053 }
2054
2055 desc += 8;
2056
2057 if (gsvs_ring_bo) {
2058 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2059
2060 /* VS entry for GS->VS ring */
2061 /* stride 0, num records - size, elsize0,
2062 index stride 0 */
2063 desc[0] = gsvs_va;
2064 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2065 S_008F04_STRIDE(0) |
2066 S_008F04_SWIZZLE_ENABLE(false);
2067 desc[2] = gsvs_ring_size;
2068 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2069 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2070 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2071 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2072 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2073 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2074 S_008F0C_ELEMENT_SIZE(0) |
2075 S_008F0C_INDEX_STRIDE(0) |
2076 S_008F0C_ADD_TID_ENABLE(false);
2077
2078 /* stride gsvs_itemsize, num records 64
2079 elsize 4, index stride 16 */
2080 /* shader will patch stride and desc[2] */
2081 desc[4] = gsvs_va;
2082 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2083 S_008F04_STRIDE(0) |
2084 S_008F04_SWIZZLE_ENABLE(true);
2085 desc[6] = 0;
2086 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2087 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2088 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2089 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2090 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2091 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2092 S_008F0C_ELEMENT_SIZE(1) |
2093 S_008F0C_INDEX_STRIDE(1) |
2094 S_008F0C_ADD_TID_ENABLE(true);
2095 }
2096
2097 desc += 8;
2098
2099 if (tess_rings_bo) {
2100 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2101 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2102
2103 desc[0] = tess_va;
2104 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2105 S_008F04_STRIDE(0) |
2106 S_008F04_SWIZZLE_ENABLE(false);
2107 desc[2] = tess_factor_ring_size;
2108 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2109 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2110 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2111 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2112 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2113 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2114 S_008F0C_ELEMENT_SIZE(0) |
2115 S_008F0C_INDEX_STRIDE(0) |
2116 S_008F0C_ADD_TID_ENABLE(false);
2117
2118 desc[4] = tess_offchip_va;
2119 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2120 S_008F04_STRIDE(0) |
2121 S_008F04_SWIZZLE_ENABLE(false);
2122 desc[6] = tess_offchip_ring_size;
2123 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2124 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2125 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2126 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2127 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2128 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2129 S_008F0C_ELEMENT_SIZE(0) |
2130 S_008F0C_INDEX_STRIDE(0) |
2131 S_008F0C_ADD_TID_ENABLE(false);
2132 }
2133
2134 desc += 8;
2135
2136 if (add_sample_positions) {
2137 /* add sample positions after all rings */
2138 memcpy(desc, queue->device->sample_locations_1x, 8);
2139 desc += 2;
2140 memcpy(desc, queue->device->sample_locations_2x, 16);
2141 desc += 4;
2142 memcpy(desc, queue->device->sample_locations_4x, 32);
2143 desc += 8;
2144 memcpy(desc, queue->device->sample_locations_8x, 64);
2145 }
2146 }
2147
2148 static unsigned
2149 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2150 {
2151 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2152 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2153 device->physical_device->rad_info.family != CHIP_STONEY;
2154 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2155 unsigned max_offchip_buffers;
2156 unsigned offchip_granularity;
2157 unsigned hs_offchip_param;
2158
2159 /*
2160 * Per RadeonSI:
2161 * This must be one less than the maximum number due to a hw limitation.
2162 * Various hardware bugs in SI, CIK, and GFX9 need this.
2163 *
2164 * Per AMDVLK:
2165 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2166 * Gfx7 should limit max_offchip_buffers to 508
2167 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2168 *
2169 * Follow AMDVLK here.
2170 */
2171 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2172 device->physical_device->rad_info.chip_class == CIK ||
2173 device->physical_device->rad_info.chip_class == SI)
2174 --max_offchip_buffers_per_se;
2175
2176 max_offchip_buffers = max_offchip_buffers_per_se *
2177 device->physical_device->rad_info.max_se;
2178
2179 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2180 * around by setting 4K granularity.
2181 */
2182 if (device->tess_offchip_block_dw_size == 4096) {
2183 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2184 offchip_granularity = V_03093C_X_4K_DWORDS;
2185 } else {
2186 assert(device->tess_offchip_block_dw_size == 8192);
2187 offchip_granularity = V_03093C_X_8K_DWORDS;
2188 }
2189
2190 switch (device->physical_device->rad_info.chip_class) {
2191 case SI:
2192 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2193 break;
2194 case CIK:
2195 case VI:
2196 case GFX9:
2197 default:
2198 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2199 break;
2200 }
2201
2202 *max_offchip_buffers_p = max_offchip_buffers;
2203 if (device->physical_device->rad_info.chip_class >= CIK) {
2204 if (device->physical_device->rad_info.chip_class >= VI)
2205 --max_offchip_buffers;
2206 hs_offchip_param =
2207 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2208 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2209 } else {
2210 hs_offchip_param =
2211 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2212 }
2213 return hs_offchip_param;
2214 }
2215
2216 static void
2217 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2218 struct radeon_winsys_bo *esgs_ring_bo,
2219 uint32_t esgs_ring_size,
2220 struct radeon_winsys_bo *gsvs_ring_bo,
2221 uint32_t gsvs_ring_size)
2222 {
2223 if (!esgs_ring_bo && !gsvs_ring_bo)
2224 return;
2225
2226 if (esgs_ring_bo)
2227 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2228
2229 if (gsvs_ring_bo)
2230 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2231
2232 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2233 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2234 radeon_emit(cs, esgs_ring_size >> 8);
2235 radeon_emit(cs, gsvs_ring_size >> 8);
2236 } else {
2237 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2238 radeon_emit(cs, esgs_ring_size >> 8);
2239 radeon_emit(cs, gsvs_ring_size >> 8);
2240 }
2241 }
2242
2243 static void
2244 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2245 unsigned hs_offchip_param, unsigned tf_ring_size,
2246 struct radeon_winsys_bo *tess_rings_bo)
2247 {
2248 uint64_t tf_va;
2249
2250 if (!tess_rings_bo)
2251 return;
2252
2253 tf_va = radv_buffer_get_va(tess_rings_bo);
2254
2255 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2256
2257 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2258 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2259 S_030938_SIZE(tf_ring_size / 4));
2260 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2261 tf_va >> 8);
2262 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2263 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2264 S_030944_BASE_HI(tf_va >> 40));
2265 }
2266 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2267 hs_offchip_param);
2268 } else {
2269 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2270 S_008988_SIZE(tf_ring_size / 4));
2271 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2272 tf_va >> 8);
2273 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2274 hs_offchip_param);
2275 }
2276 }
2277
2278 static void
2279 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2280 struct radeon_winsys_bo *compute_scratch_bo)
2281 {
2282 uint64_t scratch_va;
2283
2284 if (!compute_scratch_bo)
2285 return;
2286
2287 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2288
2289 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2290
2291 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2292 radeon_emit(cs, scratch_va);
2293 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2294 S_008F04_SWIZZLE_ENABLE(1));
2295 }
2296
2297 static void
2298 radv_emit_global_shader_pointers(struct radv_queue *queue,
2299 struct radeon_cmdbuf *cs,
2300 struct radeon_winsys_bo *descriptor_bo)
2301 {
2302 uint64_t va;
2303
2304 if (!descriptor_bo)
2305 return;
2306
2307 va = radv_buffer_get_va(descriptor_bo);
2308
2309 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2310
2311 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2312 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2313 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2314 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2315 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2316
2317 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2318 radv_emit_shader_pointer(queue->device, cs, regs[i],
2319 va, true);
2320 }
2321 } else {
2322 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2323 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2324 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2325 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2326 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2327 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2328
2329 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2330 radv_emit_shader_pointer(queue->device, cs, regs[i],
2331 va, true);
2332 }
2333 }
2334 }
2335
2336 static void
2337 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2338 {
2339 struct radv_device *device = queue->device;
2340
2341 if (device->gfx_init) {
2342 uint64_t va = radv_buffer_get_va(device->gfx_init);
2343
2344 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2345 radeon_emit(cs, va);
2346 radeon_emit(cs, va >> 32);
2347 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2348
2349 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2350 } else {
2351 struct radv_physical_device *physical_device = device->physical_device;
2352 si_emit_graphics(physical_device, cs);
2353 }
2354 }
2355
2356 static void
2357 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2358 {
2359 struct radv_physical_device *physical_device = queue->device->physical_device;
2360 si_emit_compute(physical_device, cs);
2361 }
2362
2363 static VkResult
2364 radv_get_preamble_cs(struct radv_queue *queue,
2365 uint32_t scratch_size,
2366 uint32_t compute_scratch_size,
2367 uint32_t esgs_ring_size,
2368 uint32_t gsvs_ring_size,
2369 bool needs_tess_rings,
2370 bool needs_sample_positions,
2371 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2372 struct radeon_cmdbuf **initial_preamble_cs,
2373 struct radeon_cmdbuf **continue_preamble_cs)
2374 {
2375 struct radeon_winsys_bo *scratch_bo = NULL;
2376 struct radeon_winsys_bo *descriptor_bo = NULL;
2377 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2378 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2379 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2380 struct radeon_winsys_bo *tess_rings_bo = NULL;
2381 struct radeon_cmdbuf *dest_cs[3] = {0};
2382 bool add_tess_rings = false, add_sample_positions = false;
2383 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2384 unsigned max_offchip_buffers;
2385 unsigned hs_offchip_param = 0;
2386 unsigned tess_offchip_ring_offset;
2387 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2388 if (!queue->has_tess_rings) {
2389 if (needs_tess_rings)
2390 add_tess_rings = true;
2391 }
2392 if (!queue->has_sample_positions) {
2393 if (needs_sample_positions)
2394 add_sample_positions = true;
2395 }
2396 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2397 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2398 &max_offchip_buffers);
2399 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2400 tess_offchip_ring_size = max_offchip_buffers *
2401 queue->device->tess_offchip_block_dw_size * 4;
2402
2403 if (scratch_size <= queue->scratch_size &&
2404 compute_scratch_size <= queue->compute_scratch_size &&
2405 esgs_ring_size <= queue->esgs_ring_size &&
2406 gsvs_ring_size <= queue->gsvs_ring_size &&
2407 !add_tess_rings && !add_sample_positions &&
2408 queue->initial_preamble_cs) {
2409 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2410 *initial_preamble_cs = queue->initial_preamble_cs;
2411 *continue_preamble_cs = queue->continue_preamble_cs;
2412 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2413 *continue_preamble_cs = NULL;
2414 return VK_SUCCESS;
2415 }
2416
2417 if (scratch_size > queue->scratch_size) {
2418 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2419 scratch_size,
2420 4096,
2421 RADEON_DOMAIN_VRAM,
2422 ring_bo_flags,
2423 RADV_BO_PRIORITY_SCRATCH);
2424 if (!scratch_bo)
2425 goto fail;
2426 } else
2427 scratch_bo = queue->scratch_bo;
2428
2429 if (compute_scratch_size > queue->compute_scratch_size) {
2430 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2431 compute_scratch_size,
2432 4096,
2433 RADEON_DOMAIN_VRAM,
2434 ring_bo_flags,
2435 RADV_BO_PRIORITY_SCRATCH);
2436 if (!compute_scratch_bo)
2437 goto fail;
2438
2439 } else
2440 compute_scratch_bo = queue->compute_scratch_bo;
2441
2442 if (esgs_ring_size > queue->esgs_ring_size) {
2443 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2444 esgs_ring_size,
2445 4096,
2446 RADEON_DOMAIN_VRAM,
2447 ring_bo_flags,
2448 RADV_BO_PRIORITY_SCRATCH);
2449 if (!esgs_ring_bo)
2450 goto fail;
2451 } else {
2452 esgs_ring_bo = queue->esgs_ring_bo;
2453 esgs_ring_size = queue->esgs_ring_size;
2454 }
2455
2456 if (gsvs_ring_size > queue->gsvs_ring_size) {
2457 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2458 gsvs_ring_size,
2459 4096,
2460 RADEON_DOMAIN_VRAM,
2461 ring_bo_flags,
2462 RADV_BO_PRIORITY_SCRATCH);
2463 if (!gsvs_ring_bo)
2464 goto fail;
2465 } else {
2466 gsvs_ring_bo = queue->gsvs_ring_bo;
2467 gsvs_ring_size = queue->gsvs_ring_size;
2468 }
2469
2470 if (add_tess_rings) {
2471 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2472 tess_offchip_ring_offset + tess_offchip_ring_size,
2473 256,
2474 RADEON_DOMAIN_VRAM,
2475 ring_bo_flags,
2476 RADV_BO_PRIORITY_SCRATCH);
2477 if (!tess_rings_bo)
2478 goto fail;
2479 } else {
2480 tess_rings_bo = queue->tess_rings_bo;
2481 }
2482
2483 if (scratch_bo != queue->scratch_bo ||
2484 esgs_ring_bo != queue->esgs_ring_bo ||
2485 gsvs_ring_bo != queue->gsvs_ring_bo ||
2486 tess_rings_bo != queue->tess_rings_bo ||
2487 add_sample_positions) {
2488 uint32_t size = 0;
2489 if (gsvs_ring_bo || esgs_ring_bo ||
2490 tess_rings_bo || add_sample_positions) {
2491 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2492 if (add_sample_positions)
2493 size += 128; /* 64+32+16+8 = 120 bytes */
2494 }
2495 else if (scratch_bo)
2496 size = 8; /* 2 dword */
2497
2498 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2499 size,
2500 4096,
2501 RADEON_DOMAIN_VRAM,
2502 RADEON_FLAG_CPU_ACCESS |
2503 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2504 RADEON_FLAG_READ_ONLY,
2505 RADV_BO_PRIORITY_DESCRIPTOR);
2506 if (!descriptor_bo)
2507 goto fail;
2508 } else
2509 descriptor_bo = queue->descriptor_bo;
2510
2511 if (descriptor_bo != queue->descriptor_bo) {
2512 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2513
2514 if (scratch_bo) {
2515 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2516 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2517 S_008F04_SWIZZLE_ENABLE(1);
2518 map[0] = scratch_va;
2519 map[1] = rsrc1;
2520 }
2521
2522 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2523 fill_geom_tess_rings(queue, map, add_sample_positions,
2524 esgs_ring_size, esgs_ring_bo,
2525 gsvs_ring_size, gsvs_ring_bo,
2526 tess_factor_ring_size,
2527 tess_offchip_ring_offset,
2528 tess_offchip_ring_size,
2529 tess_rings_bo);
2530
2531 queue->device->ws->buffer_unmap(descriptor_bo);
2532 }
2533
2534 for(int i = 0; i < 3; ++i) {
2535 struct radeon_cmdbuf *cs = NULL;
2536 cs = queue->device->ws->cs_create(queue->device->ws,
2537 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2538 if (!cs)
2539 goto fail;
2540
2541 dest_cs[i] = cs;
2542
2543 if (scratch_bo)
2544 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2545
2546 /* Emit initial configuration. */
2547 switch (queue->queue_family_index) {
2548 case RADV_QUEUE_GENERAL:
2549 radv_init_graphics_state(cs, queue);
2550 break;
2551 case RADV_QUEUE_COMPUTE:
2552 radv_init_compute_state(cs, queue);
2553 break;
2554 case RADV_QUEUE_TRANSFER:
2555 break;
2556 }
2557
2558 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2559 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2560 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2561 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2562 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2563 }
2564
2565 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2566 gsvs_ring_bo, gsvs_ring_size);
2567 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2568 tess_factor_ring_size, tess_rings_bo);
2569 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2570 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2571
2572 if (i == 0) {
2573 si_cs_emit_cache_flush(cs,
2574 queue->device->physical_device->rad_info.chip_class,
2575 NULL, 0,
2576 queue->queue_family_index == RING_COMPUTE &&
2577 queue->device->physical_device->rad_info.chip_class >= CIK,
2578 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2579 RADV_CMD_FLAG_INV_ICACHE |
2580 RADV_CMD_FLAG_INV_SMEM_L1 |
2581 RADV_CMD_FLAG_INV_VMEM_L1 |
2582 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2583 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2584 } else if (i == 1) {
2585 si_cs_emit_cache_flush(cs,
2586 queue->device->physical_device->rad_info.chip_class,
2587 NULL, 0,
2588 queue->queue_family_index == RING_COMPUTE &&
2589 queue->device->physical_device->rad_info.chip_class >= CIK,
2590 RADV_CMD_FLAG_INV_ICACHE |
2591 RADV_CMD_FLAG_INV_SMEM_L1 |
2592 RADV_CMD_FLAG_INV_VMEM_L1 |
2593 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2594 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2595 }
2596
2597 if (!queue->device->ws->cs_finalize(cs))
2598 goto fail;
2599 }
2600
2601 if (queue->initial_full_flush_preamble_cs)
2602 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2603
2604 if (queue->initial_preamble_cs)
2605 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2606
2607 if (queue->continue_preamble_cs)
2608 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2609
2610 queue->initial_full_flush_preamble_cs = dest_cs[0];
2611 queue->initial_preamble_cs = dest_cs[1];
2612 queue->continue_preamble_cs = dest_cs[2];
2613
2614 if (scratch_bo != queue->scratch_bo) {
2615 if (queue->scratch_bo)
2616 queue->device->ws->buffer_destroy(queue->scratch_bo);
2617 queue->scratch_bo = scratch_bo;
2618 queue->scratch_size = scratch_size;
2619 }
2620
2621 if (compute_scratch_bo != queue->compute_scratch_bo) {
2622 if (queue->compute_scratch_bo)
2623 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2624 queue->compute_scratch_bo = compute_scratch_bo;
2625 queue->compute_scratch_size = compute_scratch_size;
2626 }
2627
2628 if (esgs_ring_bo != queue->esgs_ring_bo) {
2629 if (queue->esgs_ring_bo)
2630 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2631 queue->esgs_ring_bo = esgs_ring_bo;
2632 queue->esgs_ring_size = esgs_ring_size;
2633 }
2634
2635 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2636 if (queue->gsvs_ring_bo)
2637 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2638 queue->gsvs_ring_bo = gsvs_ring_bo;
2639 queue->gsvs_ring_size = gsvs_ring_size;
2640 }
2641
2642 if (tess_rings_bo != queue->tess_rings_bo) {
2643 queue->tess_rings_bo = tess_rings_bo;
2644 queue->has_tess_rings = true;
2645 }
2646
2647 if (descriptor_bo != queue->descriptor_bo) {
2648 if (queue->descriptor_bo)
2649 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2650
2651 queue->descriptor_bo = descriptor_bo;
2652 }
2653
2654 if (add_sample_positions)
2655 queue->has_sample_positions = true;
2656
2657 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2658 *initial_preamble_cs = queue->initial_preamble_cs;
2659 *continue_preamble_cs = queue->continue_preamble_cs;
2660 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2661 *continue_preamble_cs = NULL;
2662 return VK_SUCCESS;
2663 fail:
2664 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2665 if (dest_cs[i])
2666 queue->device->ws->cs_destroy(dest_cs[i]);
2667 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2668 queue->device->ws->buffer_destroy(descriptor_bo);
2669 if (scratch_bo && scratch_bo != queue->scratch_bo)
2670 queue->device->ws->buffer_destroy(scratch_bo);
2671 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2672 queue->device->ws->buffer_destroy(compute_scratch_bo);
2673 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2674 queue->device->ws->buffer_destroy(esgs_ring_bo);
2675 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2676 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2677 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2678 queue->device->ws->buffer_destroy(tess_rings_bo);
2679 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2680 }
2681
2682 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2683 struct radv_winsys_sem_counts *counts,
2684 int num_sems,
2685 const VkSemaphore *sems,
2686 VkFence _fence,
2687 bool reset_temp)
2688 {
2689 int syncobj_idx = 0, sem_idx = 0;
2690
2691 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2692 return VK_SUCCESS;
2693
2694 for (uint32_t i = 0; i < num_sems; i++) {
2695 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2696
2697 if (sem->temp_syncobj || sem->syncobj)
2698 counts->syncobj_count++;
2699 else
2700 counts->sem_count++;
2701 }
2702
2703 if (_fence != VK_NULL_HANDLE) {
2704 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2705 if (fence->temp_syncobj || fence->syncobj)
2706 counts->syncobj_count++;
2707 }
2708
2709 if (counts->syncobj_count) {
2710 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2711 if (!counts->syncobj)
2712 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2713 }
2714
2715 if (counts->sem_count) {
2716 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2717 if (!counts->sem) {
2718 free(counts->syncobj);
2719 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2720 }
2721 }
2722
2723 for (uint32_t i = 0; i < num_sems; i++) {
2724 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2725
2726 if (sem->temp_syncobj) {
2727 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2728 }
2729 else if (sem->syncobj)
2730 counts->syncobj[syncobj_idx++] = sem->syncobj;
2731 else {
2732 assert(sem->sem);
2733 counts->sem[sem_idx++] = sem->sem;
2734 }
2735 }
2736
2737 if (_fence != VK_NULL_HANDLE) {
2738 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2739 if (fence->temp_syncobj)
2740 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2741 else if (fence->syncobj)
2742 counts->syncobj[syncobj_idx++] = fence->syncobj;
2743 }
2744
2745 return VK_SUCCESS;
2746 }
2747
2748 static void
2749 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2750 {
2751 free(sem_info->wait.syncobj);
2752 free(sem_info->wait.sem);
2753 free(sem_info->signal.syncobj);
2754 free(sem_info->signal.sem);
2755 }
2756
2757
2758 static void radv_free_temp_syncobjs(struct radv_device *device,
2759 int num_sems,
2760 const VkSemaphore *sems)
2761 {
2762 for (uint32_t i = 0; i < num_sems; i++) {
2763 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2764
2765 if (sem->temp_syncobj) {
2766 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2767 sem->temp_syncobj = 0;
2768 }
2769 }
2770 }
2771
2772 static VkResult
2773 radv_alloc_sem_info(struct radv_instance *instance,
2774 struct radv_winsys_sem_info *sem_info,
2775 int num_wait_sems,
2776 const VkSemaphore *wait_sems,
2777 int num_signal_sems,
2778 const VkSemaphore *signal_sems,
2779 VkFence fence)
2780 {
2781 VkResult ret;
2782 memset(sem_info, 0, sizeof(*sem_info));
2783
2784 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2785 if (ret)
2786 return ret;
2787 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2788 if (ret)
2789 radv_free_sem_info(sem_info);
2790
2791 /* caller can override these */
2792 sem_info->cs_emit_wait = true;
2793 sem_info->cs_emit_signal = true;
2794 return ret;
2795 }
2796
2797 /* Signals fence as soon as all the work currently put on queue is done. */
2798 static VkResult radv_signal_fence(struct radv_queue *queue,
2799 struct radv_fence *fence)
2800 {
2801 int ret;
2802 VkResult result;
2803 struct radv_winsys_sem_info sem_info;
2804
2805 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2806 radv_fence_to_handle(fence));
2807 if (result != VK_SUCCESS)
2808 return result;
2809
2810 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2811 &queue->device->empty_cs[queue->queue_family_index],
2812 1, NULL, NULL, &sem_info, NULL,
2813 false, fence->fence);
2814 radv_free_sem_info(&sem_info);
2815
2816 if (ret)
2817 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2818
2819 return VK_SUCCESS;
2820 }
2821
2822 VkResult radv_QueueSubmit(
2823 VkQueue _queue,
2824 uint32_t submitCount,
2825 const VkSubmitInfo* pSubmits,
2826 VkFence _fence)
2827 {
2828 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2829 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2830 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2831 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2832 int ret;
2833 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2834 uint32_t scratch_size = 0;
2835 uint32_t compute_scratch_size = 0;
2836 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2837 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2838 VkResult result;
2839 bool fence_emitted = false;
2840 bool tess_rings_needed = false;
2841 bool sample_positions_needed = false;
2842
2843 /* Do this first so failing to allocate scratch buffers can't result in
2844 * partially executed submissions. */
2845 for (uint32_t i = 0; i < submitCount; i++) {
2846 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2848 pSubmits[i].pCommandBuffers[j]);
2849
2850 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2851 compute_scratch_size = MAX2(compute_scratch_size,
2852 cmd_buffer->compute_scratch_size_needed);
2853 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2854 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2855 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2856 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2857 }
2858 }
2859
2860 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2861 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2862 sample_positions_needed, &initial_flush_preamble_cs,
2863 &initial_preamble_cs, &continue_preamble_cs);
2864 if (result != VK_SUCCESS)
2865 return result;
2866
2867 for (uint32_t i = 0; i < submitCount; i++) {
2868 struct radeon_cmdbuf **cs_array;
2869 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2870 bool can_patch = true;
2871 uint32_t advance;
2872 struct radv_winsys_sem_info sem_info;
2873
2874 result = radv_alloc_sem_info(queue->device->instance,
2875 &sem_info,
2876 pSubmits[i].waitSemaphoreCount,
2877 pSubmits[i].pWaitSemaphores,
2878 pSubmits[i].signalSemaphoreCount,
2879 pSubmits[i].pSignalSemaphores,
2880 _fence);
2881 if (result != VK_SUCCESS)
2882 return result;
2883
2884 if (!pSubmits[i].commandBufferCount) {
2885 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2886 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2887 &queue->device->empty_cs[queue->queue_family_index],
2888 1, NULL, NULL,
2889 &sem_info, NULL,
2890 false, base_fence);
2891 if (ret) {
2892 radv_loge("failed to submit CS %d\n", i);
2893 abort();
2894 }
2895 fence_emitted = true;
2896 }
2897 radv_free_sem_info(&sem_info);
2898 continue;
2899 }
2900
2901 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2902 (pSubmits[i].commandBufferCount));
2903
2904 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2905 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2906 pSubmits[i].pCommandBuffers[j]);
2907 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2908
2909 cs_array[j] = cmd_buffer->cs;
2910 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2911 can_patch = false;
2912
2913 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2914 }
2915
2916 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2917 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2918 const struct radv_winsys_bo_list *bo_list = NULL;
2919
2920 advance = MIN2(max_cs_submission,
2921 pSubmits[i].commandBufferCount - j);
2922
2923 if (queue->device->trace_bo)
2924 *queue->device->trace_id_ptr = 0;
2925
2926 sem_info.cs_emit_wait = j == 0;
2927 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2928
2929 if (unlikely(queue->device->use_global_bo_list)) {
2930 pthread_mutex_lock(&queue->device->bo_list.mutex);
2931 bo_list = &queue->device->bo_list.list;
2932 }
2933
2934 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2935 advance, initial_preamble, continue_preamble_cs,
2936 &sem_info, bo_list,
2937 can_patch, base_fence);
2938
2939 if (unlikely(queue->device->use_global_bo_list))
2940 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2941
2942 if (ret) {
2943 radv_loge("failed to submit CS %d\n", i);
2944 abort();
2945 }
2946 fence_emitted = true;
2947 if (queue->device->trace_bo) {
2948 radv_check_gpu_hangs(queue, cs_array[j]);
2949 }
2950 }
2951
2952 radv_free_temp_syncobjs(queue->device,
2953 pSubmits[i].waitSemaphoreCount,
2954 pSubmits[i].pWaitSemaphores);
2955 radv_free_sem_info(&sem_info);
2956 free(cs_array);
2957 }
2958
2959 if (fence) {
2960 if (!fence_emitted) {
2961 result = radv_signal_fence(queue, fence);
2962 if (result != VK_SUCCESS)
2963 return result;
2964 }
2965 fence->submitted = true;
2966 }
2967
2968 return VK_SUCCESS;
2969 }
2970
2971 VkResult radv_QueueWaitIdle(
2972 VkQueue _queue)
2973 {
2974 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2975
2976 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2977 radv_queue_family_to_ring(queue->queue_family_index),
2978 queue->queue_idx);
2979 return VK_SUCCESS;
2980 }
2981
2982 VkResult radv_DeviceWaitIdle(
2983 VkDevice _device)
2984 {
2985 RADV_FROM_HANDLE(radv_device, device, _device);
2986
2987 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2988 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2989 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2990 }
2991 }
2992 return VK_SUCCESS;
2993 }
2994
2995 VkResult radv_EnumerateInstanceExtensionProperties(
2996 const char* pLayerName,
2997 uint32_t* pPropertyCount,
2998 VkExtensionProperties* pProperties)
2999 {
3000 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3001
3002 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3003 if (radv_supported_instance_extensions.extensions[i]) {
3004 vk_outarray_append(&out, prop) {
3005 *prop = radv_instance_extensions[i];
3006 }
3007 }
3008 }
3009
3010 return vk_outarray_status(&out);
3011 }
3012
3013 VkResult radv_EnumerateDeviceExtensionProperties(
3014 VkPhysicalDevice physicalDevice,
3015 const char* pLayerName,
3016 uint32_t* pPropertyCount,
3017 VkExtensionProperties* pProperties)
3018 {
3019 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3020 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3021
3022 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3023 if (device->supported_extensions.extensions[i]) {
3024 vk_outarray_append(&out, prop) {
3025 *prop = radv_device_extensions[i];
3026 }
3027 }
3028 }
3029
3030 return vk_outarray_status(&out);
3031 }
3032
3033 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3034 VkInstance _instance,
3035 const char* pName)
3036 {
3037 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3038
3039 return radv_lookup_entrypoint_checked(pName,
3040 instance ? instance->apiVersion : 0,
3041 instance ? &instance->enabled_extensions : NULL,
3042 NULL);
3043 }
3044
3045 /* The loader wants us to expose a second GetInstanceProcAddr function
3046 * to work around certain LD_PRELOAD issues seen in apps.
3047 */
3048 PUBLIC
3049 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3050 VkInstance instance,
3051 const char* pName);
3052
3053 PUBLIC
3054 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3055 VkInstance instance,
3056 const char* pName)
3057 {
3058 return radv_GetInstanceProcAddr(instance, pName);
3059 }
3060
3061 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3062 VkDevice _device,
3063 const char* pName)
3064 {
3065 RADV_FROM_HANDLE(radv_device, device, _device);
3066
3067 return radv_lookup_entrypoint_checked(pName,
3068 device->instance->apiVersion,
3069 &device->instance->enabled_extensions,
3070 &device->enabled_extensions);
3071 }
3072
3073 bool radv_get_memory_fd(struct radv_device *device,
3074 struct radv_device_memory *memory,
3075 int *pFD)
3076 {
3077 struct radeon_bo_metadata metadata;
3078
3079 if (memory->image) {
3080 radv_init_metadata(device, memory->image, &metadata);
3081 device->ws->buffer_set_metadata(memory->bo, &metadata);
3082 }
3083
3084 return device->ws->buffer_get_fd(device->ws, memory->bo,
3085 pFD);
3086 }
3087
3088 static VkResult radv_alloc_memory(struct radv_device *device,
3089 const VkMemoryAllocateInfo* pAllocateInfo,
3090 const VkAllocationCallbacks* pAllocator,
3091 VkDeviceMemory* pMem)
3092 {
3093 struct radv_device_memory *mem;
3094 VkResult result;
3095 enum radeon_bo_domain domain;
3096 uint32_t flags = 0;
3097 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3098
3099 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3100
3101 if (pAllocateInfo->allocationSize == 0) {
3102 /* Apparently, this is allowed */
3103 *pMem = VK_NULL_HANDLE;
3104 return VK_SUCCESS;
3105 }
3106
3107 const VkImportMemoryFdInfoKHR *import_info =
3108 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3109 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3110 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3111 const VkExportMemoryAllocateInfo *export_info =
3112 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3113 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3114 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3115
3116 const struct wsi_memory_allocate_info *wsi_info =
3117 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3118
3119 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3120 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3121 if (mem == NULL)
3122 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3123
3124 if (wsi_info && wsi_info->implicit_sync)
3125 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3126
3127 if (dedicate_info) {
3128 mem->image = radv_image_from_handle(dedicate_info->image);
3129 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3130 } else {
3131 mem->image = NULL;
3132 mem->buffer = NULL;
3133 }
3134
3135 float priority_float = 0.5;
3136 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3137 vk_find_struct_const(pAllocateInfo->pNext,
3138 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3139 if (priority_ext)
3140 priority_float = priority_ext->priority;
3141
3142 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3143 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3144
3145 mem->user_ptr = NULL;
3146
3147 if (import_info) {
3148 assert(import_info->handleType ==
3149 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3150 import_info->handleType ==
3151 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3152 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3153 priority, NULL, NULL);
3154 if (!mem->bo) {
3155 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3156 goto fail;
3157 } else {
3158 close(import_info->fd);
3159 }
3160 } else if (host_ptr_info) {
3161 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3162 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3163 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3164 pAllocateInfo->allocationSize,
3165 priority);
3166 if (!mem->bo) {
3167 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3168 goto fail;
3169 } else {
3170 mem->user_ptr = host_ptr_info->pHostPointer;
3171 }
3172 } else {
3173 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3174 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3175 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3176 domain = RADEON_DOMAIN_GTT;
3177 else
3178 domain = RADEON_DOMAIN_VRAM;
3179
3180 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3181 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3182 else
3183 flags |= RADEON_FLAG_CPU_ACCESS;
3184
3185 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3186 flags |= RADEON_FLAG_GTT_WC;
3187
3188 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3189 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3190
3191 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3192 domain, flags, priority);
3193
3194 if (!mem->bo) {
3195 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3196 goto fail;
3197 }
3198 mem->type_index = mem_type_index;
3199 }
3200
3201 result = radv_bo_list_add(device, mem->bo);
3202 if (result != VK_SUCCESS)
3203 goto fail_bo;
3204
3205 *pMem = radv_device_memory_to_handle(mem);
3206
3207 return VK_SUCCESS;
3208
3209 fail_bo:
3210 device->ws->buffer_destroy(mem->bo);
3211 fail:
3212 vk_free2(&device->alloc, pAllocator, mem);
3213
3214 return result;
3215 }
3216
3217 VkResult radv_AllocateMemory(
3218 VkDevice _device,
3219 const VkMemoryAllocateInfo* pAllocateInfo,
3220 const VkAllocationCallbacks* pAllocator,
3221 VkDeviceMemory* pMem)
3222 {
3223 RADV_FROM_HANDLE(radv_device, device, _device);
3224 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3225 }
3226
3227 void radv_FreeMemory(
3228 VkDevice _device,
3229 VkDeviceMemory _mem,
3230 const VkAllocationCallbacks* pAllocator)
3231 {
3232 RADV_FROM_HANDLE(radv_device, device, _device);
3233 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3234
3235 if (mem == NULL)
3236 return;
3237
3238 radv_bo_list_remove(device, mem->bo);
3239 device->ws->buffer_destroy(mem->bo);
3240 mem->bo = NULL;
3241
3242 vk_free2(&device->alloc, pAllocator, mem);
3243 }
3244
3245 VkResult radv_MapMemory(
3246 VkDevice _device,
3247 VkDeviceMemory _memory,
3248 VkDeviceSize offset,
3249 VkDeviceSize size,
3250 VkMemoryMapFlags flags,
3251 void** ppData)
3252 {
3253 RADV_FROM_HANDLE(radv_device, device, _device);
3254 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3255
3256 if (mem == NULL) {
3257 *ppData = NULL;
3258 return VK_SUCCESS;
3259 }
3260
3261 if (mem->user_ptr)
3262 *ppData = mem->user_ptr;
3263 else
3264 *ppData = device->ws->buffer_map(mem->bo);
3265
3266 if (*ppData) {
3267 *ppData += offset;
3268 return VK_SUCCESS;
3269 }
3270
3271 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3272 }
3273
3274 void radv_UnmapMemory(
3275 VkDevice _device,
3276 VkDeviceMemory _memory)
3277 {
3278 RADV_FROM_HANDLE(radv_device, device, _device);
3279 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3280
3281 if (mem == NULL)
3282 return;
3283
3284 if (mem->user_ptr == NULL)
3285 device->ws->buffer_unmap(mem->bo);
3286 }
3287
3288 VkResult radv_FlushMappedMemoryRanges(
3289 VkDevice _device,
3290 uint32_t memoryRangeCount,
3291 const VkMappedMemoryRange* pMemoryRanges)
3292 {
3293 return VK_SUCCESS;
3294 }
3295
3296 VkResult radv_InvalidateMappedMemoryRanges(
3297 VkDevice _device,
3298 uint32_t memoryRangeCount,
3299 const VkMappedMemoryRange* pMemoryRanges)
3300 {
3301 return VK_SUCCESS;
3302 }
3303
3304 void radv_GetBufferMemoryRequirements(
3305 VkDevice _device,
3306 VkBuffer _buffer,
3307 VkMemoryRequirements* pMemoryRequirements)
3308 {
3309 RADV_FROM_HANDLE(radv_device, device, _device);
3310 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3311
3312 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3313
3314 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3315 pMemoryRequirements->alignment = 4096;
3316 else
3317 pMemoryRequirements->alignment = 16;
3318
3319 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3320 }
3321
3322 void radv_GetBufferMemoryRequirements2(
3323 VkDevice device,
3324 const VkBufferMemoryRequirementsInfo2 *pInfo,
3325 VkMemoryRequirements2 *pMemoryRequirements)
3326 {
3327 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3328 &pMemoryRequirements->memoryRequirements);
3329 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3330 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3331 switch (ext->sType) {
3332 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3333 VkMemoryDedicatedRequirements *req =
3334 (VkMemoryDedicatedRequirements *) ext;
3335 req->requiresDedicatedAllocation = buffer->shareable;
3336 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3337 break;
3338 }
3339 default:
3340 break;
3341 }
3342 }
3343 }
3344
3345 void radv_GetImageMemoryRequirements(
3346 VkDevice _device,
3347 VkImage _image,
3348 VkMemoryRequirements* pMemoryRequirements)
3349 {
3350 RADV_FROM_HANDLE(radv_device, device, _device);
3351 RADV_FROM_HANDLE(radv_image, image, _image);
3352
3353 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3354
3355 pMemoryRequirements->size = image->size;
3356 pMemoryRequirements->alignment = image->alignment;
3357 }
3358
3359 void radv_GetImageMemoryRequirements2(
3360 VkDevice device,
3361 const VkImageMemoryRequirementsInfo2 *pInfo,
3362 VkMemoryRequirements2 *pMemoryRequirements)
3363 {
3364 radv_GetImageMemoryRequirements(device, pInfo->image,
3365 &pMemoryRequirements->memoryRequirements);
3366
3367 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3368
3369 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3370 switch (ext->sType) {
3371 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3372 VkMemoryDedicatedRequirements *req =
3373 (VkMemoryDedicatedRequirements *) ext;
3374 req->requiresDedicatedAllocation = image->shareable;
3375 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3376 break;
3377 }
3378 default:
3379 break;
3380 }
3381 }
3382 }
3383
3384 void radv_GetImageSparseMemoryRequirements(
3385 VkDevice device,
3386 VkImage image,
3387 uint32_t* pSparseMemoryRequirementCount,
3388 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3389 {
3390 stub();
3391 }
3392
3393 void radv_GetImageSparseMemoryRequirements2(
3394 VkDevice device,
3395 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3396 uint32_t* pSparseMemoryRequirementCount,
3397 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3398 {
3399 stub();
3400 }
3401
3402 void radv_GetDeviceMemoryCommitment(
3403 VkDevice device,
3404 VkDeviceMemory memory,
3405 VkDeviceSize* pCommittedMemoryInBytes)
3406 {
3407 *pCommittedMemoryInBytes = 0;
3408 }
3409
3410 VkResult radv_BindBufferMemory2(VkDevice device,
3411 uint32_t bindInfoCount,
3412 const VkBindBufferMemoryInfo *pBindInfos)
3413 {
3414 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3415 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3416 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3417
3418 if (mem) {
3419 buffer->bo = mem->bo;
3420 buffer->offset = pBindInfos[i].memoryOffset;
3421 } else {
3422 buffer->bo = NULL;
3423 }
3424 }
3425 return VK_SUCCESS;
3426 }
3427
3428 VkResult radv_BindBufferMemory(
3429 VkDevice device,
3430 VkBuffer buffer,
3431 VkDeviceMemory memory,
3432 VkDeviceSize memoryOffset)
3433 {
3434 const VkBindBufferMemoryInfo info = {
3435 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3436 .buffer = buffer,
3437 .memory = memory,
3438 .memoryOffset = memoryOffset
3439 };
3440
3441 return radv_BindBufferMemory2(device, 1, &info);
3442 }
3443
3444 VkResult radv_BindImageMemory2(VkDevice device,
3445 uint32_t bindInfoCount,
3446 const VkBindImageMemoryInfo *pBindInfos)
3447 {
3448 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3449 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3450 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3451
3452 if (mem) {
3453 image->bo = mem->bo;
3454 image->offset = pBindInfos[i].memoryOffset;
3455 } else {
3456 image->bo = NULL;
3457 image->offset = 0;
3458 }
3459 }
3460 return VK_SUCCESS;
3461 }
3462
3463
3464 VkResult radv_BindImageMemory(
3465 VkDevice device,
3466 VkImage image,
3467 VkDeviceMemory memory,
3468 VkDeviceSize memoryOffset)
3469 {
3470 const VkBindImageMemoryInfo info = {
3471 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3472 .image = image,
3473 .memory = memory,
3474 .memoryOffset = memoryOffset
3475 };
3476
3477 return radv_BindImageMemory2(device, 1, &info);
3478 }
3479
3480
3481 static void
3482 radv_sparse_buffer_bind_memory(struct radv_device *device,
3483 const VkSparseBufferMemoryBindInfo *bind)
3484 {
3485 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3486
3487 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3488 struct radv_device_memory *mem = NULL;
3489
3490 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3491 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3492
3493 device->ws->buffer_virtual_bind(buffer->bo,
3494 bind->pBinds[i].resourceOffset,
3495 bind->pBinds[i].size,
3496 mem ? mem->bo : NULL,
3497 bind->pBinds[i].memoryOffset);
3498 }
3499 }
3500
3501 static void
3502 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3503 const VkSparseImageOpaqueMemoryBindInfo *bind)
3504 {
3505 RADV_FROM_HANDLE(radv_image, image, bind->image);
3506
3507 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3508 struct radv_device_memory *mem = NULL;
3509
3510 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3511 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3512
3513 device->ws->buffer_virtual_bind(image->bo,
3514 bind->pBinds[i].resourceOffset,
3515 bind->pBinds[i].size,
3516 mem ? mem->bo : NULL,
3517 bind->pBinds[i].memoryOffset);
3518 }
3519 }
3520
3521 VkResult radv_QueueBindSparse(
3522 VkQueue _queue,
3523 uint32_t bindInfoCount,
3524 const VkBindSparseInfo* pBindInfo,
3525 VkFence _fence)
3526 {
3527 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3528 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3529 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3530 bool fence_emitted = false;
3531 VkResult result;
3532 int ret;
3533
3534 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3535 struct radv_winsys_sem_info sem_info;
3536 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3537 radv_sparse_buffer_bind_memory(queue->device,
3538 pBindInfo[i].pBufferBinds + j);
3539 }
3540
3541 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3542 radv_sparse_image_opaque_bind_memory(queue->device,
3543 pBindInfo[i].pImageOpaqueBinds + j);
3544 }
3545
3546 VkResult result;
3547 result = radv_alloc_sem_info(queue->device->instance,
3548 &sem_info,
3549 pBindInfo[i].waitSemaphoreCount,
3550 pBindInfo[i].pWaitSemaphores,
3551 pBindInfo[i].signalSemaphoreCount,
3552 pBindInfo[i].pSignalSemaphores,
3553 _fence);
3554 if (result != VK_SUCCESS)
3555 return result;
3556
3557 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3558 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3559 &queue->device->empty_cs[queue->queue_family_index],
3560 1, NULL, NULL,
3561 &sem_info, NULL,
3562 false, base_fence);
3563 if (ret) {
3564 radv_loge("failed to submit CS %d\n", i);
3565 abort();
3566 }
3567
3568 fence_emitted = true;
3569 if (fence)
3570 fence->submitted = true;
3571 }
3572
3573 radv_free_sem_info(&sem_info);
3574
3575 }
3576
3577 if (fence) {
3578 if (!fence_emitted) {
3579 result = radv_signal_fence(queue, fence);
3580 if (result != VK_SUCCESS)
3581 return result;
3582 }
3583 fence->submitted = true;
3584 }
3585
3586 return VK_SUCCESS;
3587 }
3588
3589 VkResult radv_CreateFence(
3590 VkDevice _device,
3591 const VkFenceCreateInfo* pCreateInfo,
3592 const VkAllocationCallbacks* pAllocator,
3593 VkFence* pFence)
3594 {
3595 RADV_FROM_HANDLE(radv_device, device, _device);
3596 const VkExportFenceCreateInfo *export =
3597 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3598 VkExternalFenceHandleTypeFlags handleTypes =
3599 export ? export->handleTypes : 0;
3600
3601 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3602 sizeof(*fence), 8,
3603 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3604
3605 if (!fence)
3606 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3607
3608 fence->fence_wsi = NULL;
3609 fence->submitted = false;
3610 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3611 fence->temp_syncobj = 0;
3612 if (device->always_use_syncobj || handleTypes) {
3613 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3614 if (ret) {
3615 vk_free2(&device->alloc, pAllocator, fence);
3616 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3617 }
3618 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3619 device->ws->signal_syncobj(device->ws, fence->syncobj);
3620 }
3621 fence->fence = NULL;
3622 } else {
3623 fence->fence = device->ws->create_fence();
3624 if (!fence->fence) {
3625 vk_free2(&device->alloc, pAllocator, fence);
3626 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3627 }
3628 fence->syncobj = 0;
3629 }
3630
3631 *pFence = radv_fence_to_handle(fence);
3632
3633 return VK_SUCCESS;
3634 }
3635
3636 void radv_DestroyFence(
3637 VkDevice _device,
3638 VkFence _fence,
3639 const VkAllocationCallbacks* pAllocator)
3640 {
3641 RADV_FROM_HANDLE(radv_device, device, _device);
3642 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3643
3644 if (!fence)
3645 return;
3646
3647 if (fence->temp_syncobj)
3648 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3649 if (fence->syncobj)
3650 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3651 if (fence->fence)
3652 device->ws->destroy_fence(fence->fence);
3653 if (fence->fence_wsi)
3654 fence->fence_wsi->destroy(fence->fence_wsi);
3655 vk_free2(&device->alloc, pAllocator, fence);
3656 }
3657
3658
3659 uint64_t radv_get_current_time(void)
3660 {
3661 struct timespec tv;
3662 clock_gettime(CLOCK_MONOTONIC, &tv);
3663 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3664 }
3665
3666 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3667 {
3668 uint64_t current_time = radv_get_current_time();
3669
3670 timeout = MIN2(UINT64_MAX - current_time, timeout);
3671
3672 return current_time + timeout;
3673 }
3674
3675
3676 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3677 {
3678 for (uint32_t i = 0; i < fenceCount; ++i) {
3679 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3680 if (fence->fence == NULL || fence->syncobj ||
3681 fence->temp_syncobj ||
3682 (!fence->signalled && !fence->submitted))
3683 return false;
3684 }
3685 return true;
3686 }
3687
3688 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3689 {
3690 for (uint32_t i = 0; i < fenceCount; ++i) {
3691 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3692 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3693 return false;
3694 }
3695 return true;
3696 }
3697
3698 VkResult radv_WaitForFences(
3699 VkDevice _device,
3700 uint32_t fenceCount,
3701 const VkFence* pFences,
3702 VkBool32 waitAll,
3703 uint64_t timeout)
3704 {
3705 RADV_FROM_HANDLE(radv_device, device, _device);
3706 timeout = radv_get_absolute_timeout(timeout);
3707
3708 if (device->always_use_syncobj &&
3709 radv_all_fences_syncobj(fenceCount, pFences))
3710 {
3711 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3712 if (!handles)
3713 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3714
3715 for (uint32_t i = 0; i < fenceCount; ++i) {
3716 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3717 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3718 }
3719
3720 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3721
3722 free(handles);
3723 return success ? VK_SUCCESS : VK_TIMEOUT;
3724 }
3725
3726 if (!waitAll && fenceCount > 1) {
3727 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3728 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3729 uint32_t wait_count = 0;
3730 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3731 if (!fences)
3732 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3733
3734 for (uint32_t i = 0; i < fenceCount; ++i) {
3735 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3736
3737 if (fence->signalled) {
3738 free(fences);
3739 return VK_SUCCESS;
3740 }
3741
3742 fences[wait_count++] = fence->fence;
3743 }
3744
3745 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3746 waitAll, timeout - radv_get_current_time());
3747
3748 free(fences);
3749 return success ? VK_SUCCESS : VK_TIMEOUT;
3750 }
3751
3752 while(radv_get_current_time() <= timeout) {
3753 for (uint32_t i = 0; i < fenceCount; ++i) {
3754 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3755 return VK_SUCCESS;
3756 }
3757 }
3758 return VK_TIMEOUT;
3759 }
3760
3761 for (uint32_t i = 0; i < fenceCount; ++i) {
3762 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3763 bool expired = false;
3764
3765 if (fence->temp_syncobj) {
3766 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3767 return VK_TIMEOUT;
3768 continue;
3769 }
3770
3771 if (fence->syncobj) {
3772 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3773 return VK_TIMEOUT;
3774 continue;
3775 }
3776
3777 if (fence->signalled)
3778 continue;
3779
3780 if (fence->fence) {
3781 if (!fence->submitted) {
3782 while(radv_get_current_time() <= timeout &&
3783 !fence->submitted)
3784 /* Do nothing */;
3785
3786 if (!fence->submitted)
3787 return VK_TIMEOUT;
3788
3789 /* Recheck as it may have been set by
3790 * submitting operations. */
3791
3792 if (fence->signalled)
3793 continue;
3794 }
3795
3796 expired = device->ws->fence_wait(device->ws,
3797 fence->fence,
3798 true, timeout);
3799 if (!expired)
3800 return VK_TIMEOUT;
3801 }
3802
3803 if (fence->fence_wsi) {
3804 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3805 if (result != VK_SUCCESS)
3806 return result;
3807 }
3808
3809 fence->signalled = true;
3810 }
3811
3812 return VK_SUCCESS;
3813 }
3814
3815 VkResult radv_ResetFences(VkDevice _device,
3816 uint32_t fenceCount,
3817 const VkFence *pFences)
3818 {
3819 RADV_FROM_HANDLE(radv_device, device, _device);
3820
3821 for (unsigned i = 0; i < fenceCount; ++i) {
3822 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3823 fence->submitted = fence->signalled = false;
3824
3825 /* Per spec, we first restore the permanent payload, and then reset, so
3826 * having a temp syncobj should not skip resetting the permanent syncobj. */
3827 if (fence->temp_syncobj) {
3828 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3829 fence->temp_syncobj = 0;
3830 }
3831
3832 if (fence->syncobj) {
3833 device->ws->reset_syncobj(device->ws, fence->syncobj);
3834 }
3835 }
3836
3837 return VK_SUCCESS;
3838 }
3839
3840 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3841 {
3842 RADV_FROM_HANDLE(radv_device, device, _device);
3843 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3844
3845 if (fence->temp_syncobj) {
3846 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3847 return success ? VK_SUCCESS : VK_NOT_READY;
3848 }
3849
3850 if (fence->syncobj) {
3851 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3852 return success ? VK_SUCCESS : VK_NOT_READY;
3853 }
3854
3855 if (fence->signalled)
3856 return VK_SUCCESS;
3857 if (!fence->submitted)
3858 return VK_NOT_READY;
3859 if (fence->fence) {
3860 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3861 return VK_NOT_READY;
3862 }
3863 if (fence->fence_wsi) {
3864 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3865
3866 if (result != VK_SUCCESS) {
3867 if (result == VK_TIMEOUT)
3868 return VK_NOT_READY;
3869 return result;
3870 }
3871 }
3872 return VK_SUCCESS;
3873 }
3874
3875
3876 // Queue semaphore functions
3877
3878 VkResult radv_CreateSemaphore(
3879 VkDevice _device,
3880 const VkSemaphoreCreateInfo* pCreateInfo,
3881 const VkAllocationCallbacks* pAllocator,
3882 VkSemaphore* pSemaphore)
3883 {
3884 RADV_FROM_HANDLE(radv_device, device, _device);
3885 const VkExportSemaphoreCreateInfo *export =
3886 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3887 VkExternalSemaphoreHandleTypeFlags handleTypes =
3888 export ? export->handleTypes : 0;
3889
3890 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3891 sizeof(*sem), 8,
3892 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3893 if (!sem)
3894 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3895
3896 sem->temp_syncobj = 0;
3897 /* create a syncobject if we are going to export this semaphore */
3898 if (device->always_use_syncobj || handleTypes) {
3899 assert (device->physical_device->rad_info.has_syncobj);
3900 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3901 if (ret) {
3902 vk_free2(&device->alloc, pAllocator, sem);
3903 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3904 }
3905 sem->sem = NULL;
3906 } else {
3907 sem->sem = device->ws->create_sem(device->ws);
3908 if (!sem->sem) {
3909 vk_free2(&device->alloc, pAllocator, sem);
3910 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3911 }
3912 sem->syncobj = 0;
3913 }
3914
3915 *pSemaphore = radv_semaphore_to_handle(sem);
3916 return VK_SUCCESS;
3917 }
3918
3919 void radv_DestroySemaphore(
3920 VkDevice _device,
3921 VkSemaphore _semaphore,
3922 const VkAllocationCallbacks* pAllocator)
3923 {
3924 RADV_FROM_HANDLE(radv_device, device, _device);
3925 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3926 if (!_semaphore)
3927 return;
3928
3929 if (sem->syncobj)
3930 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3931 else
3932 device->ws->destroy_sem(sem->sem);
3933 vk_free2(&device->alloc, pAllocator, sem);
3934 }
3935
3936 VkResult radv_CreateEvent(
3937 VkDevice _device,
3938 const VkEventCreateInfo* pCreateInfo,
3939 const VkAllocationCallbacks* pAllocator,
3940 VkEvent* pEvent)
3941 {
3942 RADV_FROM_HANDLE(radv_device, device, _device);
3943 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3944 sizeof(*event), 8,
3945 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3946
3947 if (!event)
3948 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3949
3950 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3951 RADEON_DOMAIN_GTT,
3952 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3953 RADV_BO_PRIORITY_FENCE);
3954 if (!event->bo) {
3955 vk_free2(&device->alloc, pAllocator, event);
3956 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3957 }
3958
3959 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3960
3961 *pEvent = radv_event_to_handle(event);
3962
3963 return VK_SUCCESS;
3964 }
3965
3966 void radv_DestroyEvent(
3967 VkDevice _device,
3968 VkEvent _event,
3969 const VkAllocationCallbacks* pAllocator)
3970 {
3971 RADV_FROM_HANDLE(radv_device, device, _device);
3972 RADV_FROM_HANDLE(radv_event, event, _event);
3973
3974 if (!event)
3975 return;
3976 device->ws->buffer_destroy(event->bo);
3977 vk_free2(&device->alloc, pAllocator, event);
3978 }
3979
3980 VkResult radv_GetEventStatus(
3981 VkDevice _device,
3982 VkEvent _event)
3983 {
3984 RADV_FROM_HANDLE(radv_event, event, _event);
3985
3986 if (*event->map == 1)
3987 return VK_EVENT_SET;
3988 return VK_EVENT_RESET;
3989 }
3990
3991 VkResult radv_SetEvent(
3992 VkDevice _device,
3993 VkEvent _event)
3994 {
3995 RADV_FROM_HANDLE(radv_event, event, _event);
3996 *event->map = 1;
3997
3998 return VK_SUCCESS;
3999 }
4000
4001 VkResult radv_ResetEvent(
4002 VkDevice _device,
4003 VkEvent _event)
4004 {
4005 RADV_FROM_HANDLE(radv_event, event, _event);
4006 *event->map = 0;
4007
4008 return VK_SUCCESS;
4009 }
4010
4011 VkResult radv_CreateBuffer(
4012 VkDevice _device,
4013 const VkBufferCreateInfo* pCreateInfo,
4014 const VkAllocationCallbacks* pAllocator,
4015 VkBuffer* pBuffer)
4016 {
4017 RADV_FROM_HANDLE(radv_device, device, _device);
4018 struct radv_buffer *buffer;
4019
4020 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4021
4022 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4023 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4024 if (buffer == NULL)
4025 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4026
4027 buffer->size = pCreateInfo->size;
4028 buffer->usage = pCreateInfo->usage;
4029 buffer->bo = NULL;
4030 buffer->offset = 0;
4031 buffer->flags = pCreateInfo->flags;
4032
4033 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4034 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4035
4036 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4037 buffer->bo = device->ws->buffer_create(device->ws,
4038 align64(buffer->size, 4096),
4039 4096, 0, RADEON_FLAG_VIRTUAL,
4040 RADV_BO_PRIORITY_VIRTUAL);
4041 if (!buffer->bo) {
4042 vk_free2(&device->alloc, pAllocator, buffer);
4043 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4044 }
4045 }
4046
4047 *pBuffer = radv_buffer_to_handle(buffer);
4048
4049 return VK_SUCCESS;
4050 }
4051
4052 void radv_DestroyBuffer(
4053 VkDevice _device,
4054 VkBuffer _buffer,
4055 const VkAllocationCallbacks* pAllocator)
4056 {
4057 RADV_FROM_HANDLE(radv_device, device, _device);
4058 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4059
4060 if (!buffer)
4061 return;
4062
4063 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4064 device->ws->buffer_destroy(buffer->bo);
4065
4066 vk_free2(&device->alloc, pAllocator, buffer);
4067 }
4068
4069 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4070 VkDevice device,
4071 const VkBufferDeviceAddressInfoEXT* pInfo)
4072 {
4073 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4074 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4075 }
4076
4077
4078 static inline unsigned
4079 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4080 {
4081 if (stencil)
4082 return image->surface.u.legacy.stencil_tiling_index[level];
4083 else
4084 return image->surface.u.legacy.tiling_index[level];
4085 }
4086
4087 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4088 {
4089 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4090 }
4091
4092 static uint32_t
4093 radv_init_dcc_control_reg(struct radv_device *device,
4094 struct radv_image_view *iview)
4095 {
4096 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4097 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4098 unsigned max_compressed_block_size;
4099 unsigned independent_64b_blocks;
4100
4101 if (!radv_image_has_dcc(iview->image))
4102 return 0;
4103
4104 if (iview->image->info.samples > 1) {
4105 if (iview->image->surface.bpe == 1)
4106 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4107 else if (iview->image->surface.bpe == 2)
4108 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4109 }
4110
4111 if (!device->physical_device->rad_info.has_dedicated_vram) {
4112 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4113 * dGPU and 64 for APU because all of our APUs to date use
4114 * DIMMs which have a request granularity size of 64B while all
4115 * other chips have a 32B request size.
4116 */
4117 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4118 }
4119
4120 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4121 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4122 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4123 /* If this DCC image is potentially going to be used in texture
4124 * fetches, we need some special settings.
4125 */
4126 independent_64b_blocks = 1;
4127 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4128 } else {
4129 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4130 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4131 * big as possible for better compression state.
4132 */
4133 independent_64b_blocks = 0;
4134 max_compressed_block_size = max_uncompressed_block_size;
4135 }
4136
4137 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4138 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4139 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4140 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4141 }
4142
4143 static void
4144 radv_initialise_color_surface(struct radv_device *device,
4145 struct radv_color_buffer_info *cb,
4146 struct radv_image_view *iview)
4147 {
4148 const struct vk_format_description *desc;
4149 unsigned ntype, format, swap, endian;
4150 unsigned blend_clamp = 0, blend_bypass = 0;
4151 uint64_t va;
4152 const struct radeon_surf *surf = &iview->image->surface;
4153
4154 desc = vk_format_description(iview->vk_format);
4155
4156 memset(cb, 0, sizeof(*cb));
4157
4158 /* Intensity is implemented as Red, so treat it that way. */
4159 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4160
4161 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4162
4163 cb->cb_color_base = va >> 8;
4164
4165 if (device->physical_device->rad_info.chip_class >= GFX9) {
4166 struct gfx9_surf_meta_flags meta;
4167 if (iview->image->dcc_offset)
4168 meta = iview->image->surface.u.gfx9.dcc;
4169 else
4170 meta = iview->image->surface.u.gfx9.cmask;
4171
4172 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4173 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4174 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4175 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4176
4177 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4178 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4179 } else {
4180 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4181 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4182
4183 cb->cb_color_base += level_info->offset >> 8;
4184 if (level_info->mode == RADEON_SURF_MODE_2D)
4185 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4186
4187 pitch_tile_max = level_info->nblk_x / 8 - 1;
4188 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4189 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4190
4191 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4192 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4193 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4194
4195 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4196
4197 if (radv_image_has_fmask(iview->image)) {
4198 if (device->physical_device->rad_info.chip_class >= CIK)
4199 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4200 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4201 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4202 } else {
4203 /* This must be set for fast clear to work without FMASK. */
4204 if (device->physical_device->rad_info.chip_class >= CIK)
4205 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4206 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4207 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4208 }
4209 }
4210
4211 /* CMASK variables */
4212 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4213 va += iview->image->cmask.offset;
4214 cb->cb_color_cmask = va >> 8;
4215
4216 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4217 va += iview->image->dcc_offset;
4218 cb->cb_dcc_base = va >> 8;
4219 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4220
4221 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4222 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4223 S_028C6C_SLICE_MAX(max_slice);
4224
4225 if (iview->image->info.samples > 1) {
4226 unsigned log_samples = util_logbase2(iview->image->info.samples);
4227
4228 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4229 S_028C74_NUM_FRAGMENTS(log_samples);
4230 }
4231
4232 if (radv_image_has_fmask(iview->image)) {
4233 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4234 cb->cb_color_fmask = va >> 8;
4235 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4236 } else {
4237 cb->cb_color_fmask = cb->cb_color_base;
4238 }
4239
4240 ntype = radv_translate_color_numformat(iview->vk_format,
4241 desc,
4242 vk_format_get_first_non_void_channel(iview->vk_format));
4243 format = radv_translate_colorformat(iview->vk_format);
4244 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4245 radv_finishme("Illegal color\n");
4246 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4247 endian = radv_colorformat_endian_swap(format);
4248
4249 /* blend clamp should be set for all NORM/SRGB types */
4250 if (ntype == V_028C70_NUMBER_UNORM ||
4251 ntype == V_028C70_NUMBER_SNORM ||
4252 ntype == V_028C70_NUMBER_SRGB)
4253 blend_clamp = 1;
4254
4255 /* set blend bypass according to docs if SINT/UINT or
4256 8/24 COLOR variants */
4257 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4258 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4259 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4260 blend_clamp = 0;
4261 blend_bypass = 1;
4262 }
4263 #if 0
4264 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4265 (format == V_028C70_COLOR_8 ||
4266 format == V_028C70_COLOR_8_8 ||
4267 format == V_028C70_COLOR_8_8_8_8))
4268 ->color_is_int8 = true;
4269 #endif
4270 cb->cb_color_info = S_028C70_FORMAT(format) |
4271 S_028C70_COMP_SWAP(swap) |
4272 S_028C70_BLEND_CLAMP(blend_clamp) |
4273 S_028C70_BLEND_BYPASS(blend_bypass) |
4274 S_028C70_SIMPLE_FLOAT(1) |
4275 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4276 ntype != V_028C70_NUMBER_SNORM &&
4277 ntype != V_028C70_NUMBER_SRGB &&
4278 format != V_028C70_COLOR_8_24 &&
4279 format != V_028C70_COLOR_24_8) |
4280 S_028C70_NUMBER_TYPE(ntype) |
4281 S_028C70_ENDIAN(endian);
4282 if (radv_image_has_fmask(iview->image)) {
4283 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4284 if (device->physical_device->rad_info.chip_class == SI) {
4285 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4286 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4287 }
4288 }
4289
4290 if (radv_image_has_cmask(iview->image) &&
4291 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4292 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4293
4294 if (radv_dcc_enabled(iview->image, iview->base_mip))
4295 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4296
4297 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4298
4299 /* This must be set for fast clear to work without FMASK. */
4300 if (!radv_image_has_fmask(iview->image) &&
4301 device->physical_device->rad_info.chip_class == SI) {
4302 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4303 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4304 }
4305
4306 if (device->physical_device->rad_info.chip_class >= GFX9) {
4307 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4308 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4309
4310 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4311 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4312 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4313 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4314 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4315 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4316 }
4317 }
4318
4319 static unsigned
4320 radv_calc_decompress_on_z_planes(struct radv_device *device,
4321 struct radv_image_view *iview)
4322 {
4323 unsigned max_zplanes = 0;
4324
4325 assert(radv_image_is_tc_compat_htile(iview->image));
4326
4327 if (device->physical_device->rad_info.chip_class >= GFX9) {
4328 /* Default value for 32-bit depth surfaces. */
4329 max_zplanes = 4;
4330
4331 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4332 iview->image->info.samples > 1)
4333 max_zplanes = 2;
4334
4335 max_zplanes = max_zplanes + 1;
4336 } else {
4337 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4338 /* Do not enable Z plane compression for 16-bit depth
4339 * surfaces because isn't supported on GFX8. Only
4340 * 32-bit depth surfaces are supported by the hardware.
4341 * This allows to maintain shader compatibility and to
4342 * reduce the number of depth decompressions.
4343 */
4344 max_zplanes = 1;
4345 } else {
4346 if (iview->image->info.samples <= 1)
4347 max_zplanes = 5;
4348 else if (iview->image->info.samples <= 4)
4349 max_zplanes = 3;
4350 else
4351 max_zplanes = 2;
4352 }
4353 }
4354
4355 return max_zplanes;
4356 }
4357
4358 static void
4359 radv_initialise_ds_surface(struct radv_device *device,
4360 struct radv_ds_buffer_info *ds,
4361 struct radv_image_view *iview)
4362 {
4363 unsigned level = iview->base_mip;
4364 unsigned format, stencil_format;
4365 uint64_t va, s_offs, z_offs;
4366 bool stencil_only = false;
4367 memset(ds, 0, sizeof(*ds));
4368 switch (iview->image->vk_format) {
4369 case VK_FORMAT_D24_UNORM_S8_UINT:
4370 case VK_FORMAT_X8_D24_UNORM_PACK32:
4371 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4372 ds->offset_scale = 2.0f;
4373 break;
4374 case VK_FORMAT_D16_UNORM:
4375 case VK_FORMAT_D16_UNORM_S8_UINT:
4376 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4377 ds->offset_scale = 4.0f;
4378 break;
4379 case VK_FORMAT_D32_SFLOAT:
4380 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4381 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4382 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4383 ds->offset_scale = 1.0f;
4384 break;
4385 case VK_FORMAT_S8_UINT:
4386 stencil_only = true;
4387 break;
4388 default:
4389 break;
4390 }
4391
4392 format = radv_translate_dbformat(iview->image->vk_format);
4393 stencil_format = iview->image->surface.has_stencil ?
4394 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4395
4396 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4397 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4398 S_028008_SLICE_MAX(max_slice);
4399
4400 ds->db_htile_data_base = 0;
4401 ds->db_htile_surface = 0;
4402
4403 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4404 s_offs = z_offs = va;
4405
4406 if (device->physical_device->rad_info.chip_class >= GFX9) {
4407 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4408 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4409
4410 ds->db_z_info = S_028038_FORMAT(format) |
4411 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4412 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4413 S_028038_MAXMIP(iview->image->info.levels - 1) |
4414 S_028038_ZRANGE_PRECISION(1);
4415 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4416 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4417
4418 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4419 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4420 ds->db_depth_view |= S_028008_MIPID(level);
4421
4422 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4423 S_02801C_Y_MAX(iview->image->info.height - 1);
4424
4425 if (radv_htile_enabled(iview->image, level)) {
4426 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4427
4428 if (radv_image_is_tc_compat_htile(iview->image)) {
4429 unsigned max_zplanes =
4430 radv_calc_decompress_on_z_planes(device, iview);
4431
4432 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4433 S_028038_ITERATE_FLUSH(1);
4434 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4435 }
4436
4437 if (!iview->image->surface.has_stencil)
4438 /* Use all of the htile_buffer for depth if there's no stencil. */
4439 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4440 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4441 iview->image->htile_offset;
4442 ds->db_htile_data_base = va >> 8;
4443 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4444 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4445 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4446 }
4447 } else {
4448 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4449
4450 if (stencil_only)
4451 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4452
4453 z_offs += iview->image->surface.u.legacy.level[level].offset;
4454 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4455
4456 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4457 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4458 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4459
4460 if (iview->image->info.samples > 1)
4461 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4462
4463 if (device->physical_device->rad_info.chip_class >= CIK) {
4464 struct radeon_info *info = &device->physical_device->rad_info;
4465 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4466 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4467 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4468 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4469 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4470 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4471
4472 if (stencil_only)
4473 tile_mode = stencil_tile_mode;
4474
4475 ds->db_depth_info |=
4476 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4477 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4478 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4479 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4480 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4481 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4482 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4483 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4484 } else {
4485 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4486 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4487 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4488 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4489 if (stencil_only)
4490 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4491 }
4492
4493 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4494 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4495 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4496
4497 if (radv_htile_enabled(iview->image, level)) {
4498 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4499
4500 if (!iview->image->surface.has_stencil &&
4501 !radv_image_is_tc_compat_htile(iview->image))
4502 /* Use all of the htile_buffer for depth if there's no stencil. */
4503 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4504
4505 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4506 iview->image->htile_offset;
4507 ds->db_htile_data_base = va >> 8;
4508 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4509
4510 if (radv_image_is_tc_compat_htile(iview->image)) {
4511 unsigned max_zplanes =
4512 radv_calc_decompress_on_z_planes(device, iview);
4513
4514 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4515 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4516 }
4517 }
4518 }
4519
4520 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4521 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4522 }
4523
4524 VkResult radv_CreateFramebuffer(
4525 VkDevice _device,
4526 const VkFramebufferCreateInfo* pCreateInfo,
4527 const VkAllocationCallbacks* pAllocator,
4528 VkFramebuffer* pFramebuffer)
4529 {
4530 RADV_FROM_HANDLE(radv_device, device, _device);
4531 struct radv_framebuffer *framebuffer;
4532
4533 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4534
4535 size_t size = sizeof(*framebuffer) +
4536 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4537 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4538 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4539 if (framebuffer == NULL)
4540 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4541
4542 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4543 framebuffer->width = pCreateInfo->width;
4544 framebuffer->height = pCreateInfo->height;
4545 framebuffer->layers = pCreateInfo->layers;
4546 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4547 VkImageView _iview = pCreateInfo->pAttachments[i];
4548 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4549 framebuffer->attachments[i].attachment = iview;
4550 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4551 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4552 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4553 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4554 }
4555 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4556 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4557 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4558 }
4559
4560 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4561 return VK_SUCCESS;
4562 }
4563
4564 void radv_DestroyFramebuffer(
4565 VkDevice _device,
4566 VkFramebuffer _fb,
4567 const VkAllocationCallbacks* pAllocator)
4568 {
4569 RADV_FROM_HANDLE(radv_device, device, _device);
4570 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4571
4572 if (!fb)
4573 return;
4574 vk_free2(&device->alloc, pAllocator, fb);
4575 }
4576
4577 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4578 {
4579 switch (address_mode) {
4580 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4581 return V_008F30_SQ_TEX_WRAP;
4582 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4583 return V_008F30_SQ_TEX_MIRROR;
4584 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4585 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4586 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4587 return V_008F30_SQ_TEX_CLAMP_BORDER;
4588 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4589 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4590 default:
4591 unreachable("illegal tex wrap mode");
4592 break;
4593 }
4594 }
4595
4596 static unsigned
4597 radv_tex_compare(VkCompareOp op)
4598 {
4599 switch (op) {
4600 case VK_COMPARE_OP_NEVER:
4601 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4602 case VK_COMPARE_OP_LESS:
4603 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4604 case VK_COMPARE_OP_EQUAL:
4605 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4606 case VK_COMPARE_OP_LESS_OR_EQUAL:
4607 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4608 case VK_COMPARE_OP_GREATER:
4609 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4610 case VK_COMPARE_OP_NOT_EQUAL:
4611 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4612 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4613 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4614 case VK_COMPARE_OP_ALWAYS:
4615 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4616 default:
4617 unreachable("illegal compare mode");
4618 break;
4619 }
4620 }
4621
4622 static unsigned
4623 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4624 {
4625 switch (filter) {
4626 case VK_FILTER_NEAREST:
4627 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4628 V_008F38_SQ_TEX_XY_FILTER_POINT);
4629 case VK_FILTER_LINEAR:
4630 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4631 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4632 case VK_FILTER_CUBIC_IMG:
4633 default:
4634 fprintf(stderr, "illegal texture filter");
4635 return 0;
4636 }
4637 }
4638
4639 static unsigned
4640 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4641 {
4642 switch (mode) {
4643 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4644 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4645 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4646 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4647 default:
4648 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4649 }
4650 }
4651
4652 static unsigned
4653 radv_tex_bordercolor(VkBorderColor bcolor)
4654 {
4655 switch (bcolor) {
4656 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4657 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4658 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4659 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4660 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4661 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4662 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4663 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4664 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4665 default:
4666 break;
4667 }
4668 return 0;
4669 }
4670
4671 static unsigned
4672 radv_tex_aniso_filter(unsigned filter)
4673 {
4674 if (filter < 2)
4675 return 0;
4676 if (filter < 4)
4677 return 1;
4678 if (filter < 8)
4679 return 2;
4680 if (filter < 16)
4681 return 3;
4682 return 4;
4683 }
4684
4685 static unsigned
4686 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4687 {
4688 switch (mode) {
4689 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4690 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4691 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4692 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4693 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4694 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4695 default:
4696 break;
4697 }
4698 return 0;
4699 }
4700
4701 static uint32_t
4702 radv_get_max_anisotropy(struct radv_device *device,
4703 const VkSamplerCreateInfo *pCreateInfo)
4704 {
4705 if (device->force_aniso >= 0)
4706 return device->force_aniso;
4707
4708 if (pCreateInfo->anisotropyEnable &&
4709 pCreateInfo->maxAnisotropy > 1.0f)
4710 return (uint32_t)pCreateInfo->maxAnisotropy;
4711
4712 return 0;
4713 }
4714
4715 static void
4716 radv_init_sampler(struct radv_device *device,
4717 struct radv_sampler *sampler,
4718 const VkSamplerCreateInfo *pCreateInfo)
4719 {
4720 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4721 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4722 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4723 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4724
4725 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4726 vk_find_struct_const(pCreateInfo->pNext,
4727 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4728 if (sampler_reduction)
4729 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4730
4731 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4732 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4733 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4734 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4735 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4736 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4737 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4738 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4739 S_008F30_DISABLE_CUBE_WRAP(0) |
4740 S_008F30_COMPAT_MODE(is_vi) |
4741 S_008F30_FILTER_MODE(filter_mode));
4742 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4743 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4744 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4745 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4746 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4747 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4748 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4749 S_008F38_MIP_POINT_PRECLAMP(0) |
4750 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4751 S_008F38_FILTER_PREC_FIX(1) |
4752 S_008F38_ANISO_OVERRIDE(is_vi));
4753 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4754 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4755 }
4756
4757 VkResult radv_CreateSampler(
4758 VkDevice _device,
4759 const VkSamplerCreateInfo* pCreateInfo,
4760 const VkAllocationCallbacks* pAllocator,
4761 VkSampler* pSampler)
4762 {
4763 RADV_FROM_HANDLE(radv_device, device, _device);
4764 struct radv_sampler *sampler;
4765
4766 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4767
4768 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4769 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4770 if (!sampler)
4771 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4772
4773 radv_init_sampler(device, sampler, pCreateInfo);
4774 *pSampler = radv_sampler_to_handle(sampler);
4775
4776 return VK_SUCCESS;
4777 }
4778
4779 void radv_DestroySampler(
4780 VkDevice _device,
4781 VkSampler _sampler,
4782 const VkAllocationCallbacks* pAllocator)
4783 {
4784 RADV_FROM_HANDLE(radv_device, device, _device);
4785 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4786
4787 if (!sampler)
4788 return;
4789 vk_free2(&device->alloc, pAllocator, sampler);
4790 }
4791
4792 /* vk_icd.h does not declare this function, so we declare it here to
4793 * suppress Wmissing-prototypes.
4794 */
4795 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4796 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4797
4798 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4799 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4800 {
4801 /* For the full details on loader interface versioning, see
4802 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4803 * What follows is a condensed summary, to help you navigate the large and
4804 * confusing official doc.
4805 *
4806 * - Loader interface v0 is incompatible with later versions. We don't
4807 * support it.
4808 *
4809 * - In loader interface v1:
4810 * - The first ICD entrypoint called by the loader is
4811 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4812 * entrypoint.
4813 * - The ICD must statically expose no other Vulkan symbol unless it is
4814 * linked with -Bsymbolic.
4815 * - Each dispatchable Vulkan handle created by the ICD must be
4816 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4817 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4818 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4819 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4820 * such loader-managed surfaces.
4821 *
4822 * - Loader interface v2 differs from v1 in:
4823 * - The first ICD entrypoint called by the loader is
4824 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4825 * statically expose this entrypoint.
4826 *
4827 * - Loader interface v3 differs from v2 in:
4828 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4829 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4830 * because the loader no longer does so.
4831 */
4832 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4833 return VK_SUCCESS;
4834 }
4835
4836 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4837 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4838 int *pFD)
4839 {
4840 RADV_FROM_HANDLE(radv_device, device, _device);
4841 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4842
4843 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4844
4845 /* At the moment, we support only the below handle types. */
4846 assert(pGetFdInfo->handleType ==
4847 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4848 pGetFdInfo->handleType ==
4849 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4850
4851 bool ret = radv_get_memory_fd(device, memory, pFD);
4852 if (ret == false)
4853 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4854 return VK_SUCCESS;
4855 }
4856
4857 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4858 VkExternalMemoryHandleTypeFlagBits handleType,
4859 int fd,
4860 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4861 {
4862 RADV_FROM_HANDLE(radv_device, device, _device);
4863
4864 switch (handleType) {
4865 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4866 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4867 return VK_SUCCESS;
4868
4869 default:
4870 /* The valid usage section for this function says:
4871 *
4872 * "handleType must not be one of the handle types defined as
4873 * opaque."
4874 *
4875 * So opaque handle types fall into the default "unsupported" case.
4876 */
4877 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4878 }
4879 }
4880
4881 static VkResult radv_import_opaque_fd(struct radv_device *device,
4882 int fd,
4883 uint32_t *syncobj)
4884 {
4885 uint32_t syncobj_handle = 0;
4886 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4887 if (ret != 0)
4888 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4889
4890 if (*syncobj)
4891 device->ws->destroy_syncobj(device->ws, *syncobj);
4892
4893 *syncobj = syncobj_handle;
4894 close(fd);
4895
4896 return VK_SUCCESS;
4897 }
4898
4899 static VkResult radv_import_sync_fd(struct radv_device *device,
4900 int fd,
4901 uint32_t *syncobj)
4902 {
4903 /* If we create a syncobj we do it locally so that if we have an error, we don't
4904 * leave a syncobj in an undetermined state in the fence. */
4905 uint32_t syncobj_handle = *syncobj;
4906 if (!syncobj_handle) {
4907 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4908 if (ret) {
4909 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4910 }
4911 }
4912
4913 if (fd == -1) {
4914 device->ws->signal_syncobj(device->ws, syncobj_handle);
4915 } else {
4916 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4917 if (ret != 0)
4918 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4919 }
4920
4921 *syncobj = syncobj_handle;
4922 if (fd != -1)
4923 close(fd);
4924
4925 return VK_SUCCESS;
4926 }
4927
4928 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4929 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4930 {
4931 RADV_FROM_HANDLE(radv_device, device, _device);
4932 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4933 uint32_t *syncobj_dst = NULL;
4934
4935 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4936 syncobj_dst = &sem->temp_syncobj;
4937 } else {
4938 syncobj_dst = &sem->syncobj;
4939 }
4940
4941 switch(pImportSemaphoreFdInfo->handleType) {
4942 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4943 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4944 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4945 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4946 default:
4947 unreachable("Unhandled semaphore handle type");
4948 }
4949 }
4950
4951 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4952 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4953 int *pFd)
4954 {
4955 RADV_FROM_HANDLE(radv_device, device, _device);
4956 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4957 int ret;
4958 uint32_t syncobj_handle;
4959
4960 if (sem->temp_syncobj)
4961 syncobj_handle = sem->temp_syncobj;
4962 else
4963 syncobj_handle = sem->syncobj;
4964
4965 switch(pGetFdInfo->handleType) {
4966 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4967 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4968 break;
4969 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4970 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4971 if (!ret) {
4972 if (sem->temp_syncobj) {
4973 close (sem->temp_syncobj);
4974 sem->temp_syncobj = 0;
4975 } else {
4976 device->ws->reset_syncobj(device->ws, syncobj_handle);
4977 }
4978 }
4979 break;
4980 default:
4981 unreachable("Unhandled semaphore handle type");
4982 }
4983
4984 if (ret)
4985 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4986 return VK_SUCCESS;
4987 }
4988
4989 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4990 VkPhysicalDevice physicalDevice,
4991 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4992 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4993 {
4994 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4995
4996 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4997 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4998 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4999 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5000 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5001 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5002 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5003 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5004 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5005 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5006 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5007 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5008 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5009 } else {
5010 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5011 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5012 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5013 }
5014 }
5015
5016 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5017 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5018 {
5019 RADV_FROM_HANDLE(radv_device, device, _device);
5020 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5021 uint32_t *syncobj_dst = NULL;
5022
5023
5024 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5025 syncobj_dst = &fence->temp_syncobj;
5026 } else {
5027 syncobj_dst = &fence->syncobj;
5028 }
5029
5030 switch(pImportFenceFdInfo->handleType) {
5031 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5032 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5033 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5034 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5035 default:
5036 unreachable("Unhandled fence handle type");
5037 }
5038 }
5039
5040 VkResult radv_GetFenceFdKHR(VkDevice _device,
5041 const VkFenceGetFdInfoKHR *pGetFdInfo,
5042 int *pFd)
5043 {
5044 RADV_FROM_HANDLE(radv_device, device, _device);
5045 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5046 int ret;
5047 uint32_t syncobj_handle;
5048
5049 if (fence->temp_syncobj)
5050 syncobj_handle = fence->temp_syncobj;
5051 else
5052 syncobj_handle = fence->syncobj;
5053
5054 switch(pGetFdInfo->handleType) {
5055 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5056 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5057 break;
5058 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5059 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5060 if (!ret) {
5061 if (fence->temp_syncobj) {
5062 close (fence->temp_syncobj);
5063 fence->temp_syncobj = 0;
5064 } else {
5065 device->ws->reset_syncobj(device->ws, syncobj_handle);
5066 }
5067 }
5068 break;
5069 default:
5070 unreachable("Unhandled fence handle type");
5071 }
5072
5073 if (ret)
5074 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5075 return VK_SUCCESS;
5076 }
5077
5078 void radv_GetPhysicalDeviceExternalFenceProperties(
5079 VkPhysicalDevice physicalDevice,
5080 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5081 VkExternalFenceProperties *pExternalFenceProperties)
5082 {
5083 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5084
5085 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5086 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5087 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5088 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5089 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5090 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5091 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5092 } else {
5093 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5094 pExternalFenceProperties->compatibleHandleTypes = 0;
5095 pExternalFenceProperties->externalFenceFeatures = 0;
5096 }
5097 }
5098
5099 VkResult
5100 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5101 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5102 const VkAllocationCallbacks* pAllocator,
5103 VkDebugReportCallbackEXT* pCallback)
5104 {
5105 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5106 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5107 pCreateInfo, pAllocator, &instance->alloc,
5108 pCallback);
5109 }
5110
5111 void
5112 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5113 VkDebugReportCallbackEXT _callback,
5114 const VkAllocationCallbacks* pAllocator)
5115 {
5116 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5117 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5118 _callback, pAllocator, &instance->alloc);
5119 }
5120
5121 void
5122 radv_DebugReportMessageEXT(VkInstance _instance,
5123 VkDebugReportFlagsEXT flags,
5124 VkDebugReportObjectTypeEXT objectType,
5125 uint64_t object,
5126 size_t location,
5127 int32_t messageCode,
5128 const char* pLayerPrefix,
5129 const char* pMessage)
5130 {
5131 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5132 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5133 object, location, messageCode, pLayerPrefix, pMessage);
5134 }
5135
5136 void
5137 radv_GetDeviceGroupPeerMemoryFeatures(
5138 VkDevice device,
5139 uint32_t heapIndex,
5140 uint32_t localDeviceIndex,
5141 uint32_t remoteDeviceIndex,
5142 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5143 {
5144 assert(localDeviceIndex == remoteDeviceIndex);
5145
5146 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5147 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5148 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5149 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5150 }
5151
5152 static const VkTimeDomainEXT radv_time_domains[] = {
5153 VK_TIME_DOMAIN_DEVICE_EXT,
5154 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5155 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5156 };
5157
5158 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5159 VkPhysicalDevice physicalDevice,
5160 uint32_t *pTimeDomainCount,
5161 VkTimeDomainEXT *pTimeDomains)
5162 {
5163 int d;
5164 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5165
5166 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5167 vk_outarray_append(&out, i) {
5168 *i = radv_time_domains[d];
5169 }
5170 }
5171
5172 return vk_outarray_status(&out);
5173 }
5174
5175 static uint64_t
5176 radv_clock_gettime(clockid_t clock_id)
5177 {
5178 struct timespec current;
5179 int ret;
5180
5181 ret = clock_gettime(clock_id, &current);
5182 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5183 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5184 if (ret < 0)
5185 return 0;
5186
5187 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5188 }
5189
5190 VkResult radv_GetCalibratedTimestampsEXT(
5191 VkDevice _device,
5192 uint32_t timestampCount,
5193 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5194 uint64_t *pTimestamps,
5195 uint64_t *pMaxDeviation)
5196 {
5197 RADV_FROM_HANDLE(radv_device, device, _device);
5198 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5199 int d;
5200 uint64_t begin, end;
5201 uint64_t max_clock_period = 0;
5202
5203 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5204
5205 for (d = 0; d < timestampCount; d++) {
5206 switch (pTimestampInfos[d].timeDomain) {
5207 case VK_TIME_DOMAIN_DEVICE_EXT:
5208 pTimestamps[d] = device->ws->query_value(device->ws,
5209 RADEON_TIMESTAMP);
5210 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5211 max_clock_period = MAX2(max_clock_period, device_period);
5212 break;
5213 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5214 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5215 max_clock_period = MAX2(max_clock_period, 1);
5216 break;
5217
5218 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5219 pTimestamps[d] = begin;
5220 break;
5221 default:
5222 pTimestamps[d] = 0;
5223 break;
5224 }
5225 }
5226
5227 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5228
5229 /*
5230 * The maximum deviation is the sum of the interval over which we
5231 * perform the sampling and the maximum period of any sampled
5232 * clock. That's because the maximum skew between any two sampled
5233 * clock edges is when the sampled clock with the largest period is
5234 * sampled at the end of that period but right at the beginning of the
5235 * sampling interval and some other clock is sampled right at the
5236 * begining of its sampling period and right at the end of the
5237 * sampling interval. Let's assume the GPU has the longest clock
5238 * period and that the application is sampling GPU and monotonic:
5239 *
5240 * s e
5241 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5242 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5243 *
5244 * g
5245 * 0 1 2 3
5246 * GPU -----_____-----_____-----_____-----_____
5247 *
5248 * m
5249 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5250 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5251 *
5252 * Interval <----------------->
5253 * Deviation <-------------------------->
5254 *
5255 * s = read(raw) 2
5256 * g = read(GPU) 1
5257 * m = read(monotonic) 2
5258 * e = read(raw) b
5259 *
5260 * We round the sample interval up by one tick to cover sampling error
5261 * in the interval clock
5262 */
5263
5264 uint64_t sample_interval = end - begin + 1;
5265
5266 *pMaxDeviation = sample_interval + max_clock_period;
5267
5268 return VK_SUCCESS;
5269 }