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e9e00eb96730ab978fea115240e8a3ae16e84d97
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "util/strtod.h"
34
35 #include <amdgpu.h>
36 #include <amdgpu_drm.h>
37 #include "amdgpu_id.h"
38 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
39 #include "ac_llvm_util.h"
40 #include "vk_format.h"
41 #include "sid.h"
42 #include "radv_timestamp.h"
43 #include "util/debug.h"
44 struct radv_dispatch_table dtable;
45
46 struct radv_fence {
47 struct radeon_winsys_fence *fence;
48 bool submitted;
49 bool signalled;
50 };
51
52 static VkResult
53 radv_physical_device_init(struct radv_physical_device *device,
54 struct radv_instance *instance,
55 const char *path)
56 {
57 VkResult result;
58 int fd;
59
60 fd = open(path, O_RDWR | O_CLOEXEC);
61 if (fd < 0)
62 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
63 "failed to open %s: %m", path);
64
65 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
66 device->instance = instance;
67 assert(strlen(path) < ARRAY_SIZE(device->path));
68 strncpy(device->path, path, ARRAY_SIZE(device->path));
69
70 device->ws = radv_amdgpu_winsys_create(fd);
71 if (!device->ws) {
72 result = VK_ERROR_INCOMPATIBLE_DRIVER;
73 goto fail;
74 }
75 device->ws->query_info(device->ws, &device->rad_info);
76 result = radv_init_wsi(device);
77 if (result != VK_SUCCESS)
78 goto fail;
79
80 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
81 device->name = device->rad_info.name;
82 return VK_SUCCESS;
83
84 fail:
85 close(fd);
86 return result;
87 }
88
89 static void
90 radv_physical_device_finish(struct radv_physical_device *device)
91 {
92 radv_finish_wsi(device);
93 device->ws->destroy(device->ws);
94 }
95
96 static const VkExtensionProperties global_extensions[] = {
97 {
98 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
99 .specVersion = 25,
100 },
101 #ifdef VK_USE_PLATFORM_XCB_KHR
102 {
103 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
104 .specVersion = 5,
105 },
106 #endif
107 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
108 {
109 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
110 .specVersion = 4,
111 },
112 #endif
113 };
114
115 static const VkExtensionProperties device_extensions[] = {
116 {
117 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
118 .specVersion = 67,
119 },
120 };
121
122 static void *
123 default_alloc_func(void *pUserData, size_t size, size_t align,
124 VkSystemAllocationScope allocationScope)
125 {
126 return malloc(size);
127 }
128
129 static void *
130 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
131 size_t align, VkSystemAllocationScope allocationScope)
132 {
133 return realloc(pOriginal, size);
134 }
135
136 static void
137 default_free_func(void *pUserData, void *pMemory)
138 {
139 free(pMemory);
140 }
141
142 static const VkAllocationCallbacks default_alloc = {
143 .pUserData = NULL,
144 .pfnAllocation = default_alloc_func,
145 .pfnReallocation = default_realloc_func,
146 .pfnFree = default_free_func,
147 };
148
149 VkResult radv_CreateInstance(
150 const VkInstanceCreateInfo* pCreateInfo,
151 const VkAllocationCallbacks* pAllocator,
152 VkInstance* pInstance)
153 {
154 struct radv_instance *instance;
155
156 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
157
158 uint32_t client_version;
159 if (pCreateInfo->pApplicationInfo &&
160 pCreateInfo->pApplicationInfo->apiVersion != 0) {
161 client_version = pCreateInfo->pApplicationInfo->apiVersion;
162 } else {
163 client_version = VK_MAKE_VERSION(1, 0, 0);
164 }
165
166 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
167 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
168 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
169 "Client requested version %d.%d.%d",
170 VK_VERSION_MAJOR(client_version),
171 VK_VERSION_MINOR(client_version),
172 VK_VERSION_PATCH(client_version));
173 }
174
175 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
176 bool found = false;
177 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
178 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
179 global_extensions[j].extensionName) == 0) {
180 found = true;
181 break;
182 }
183 }
184 if (!found)
185 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
186 }
187
188 instance = radv_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
189 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
190 if (!instance)
191 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
192
193 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
194
195 if (pAllocator)
196 instance->alloc = *pAllocator;
197 else
198 instance->alloc = default_alloc;
199
200 instance->apiVersion = client_version;
201 instance->physicalDeviceCount = -1;
202
203 _mesa_locale_init();
204
205 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
206
207 *pInstance = radv_instance_to_handle(instance);
208
209 return VK_SUCCESS;
210 }
211
212 void radv_DestroyInstance(
213 VkInstance _instance,
214 const VkAllocationCallbacks* pAllocator)
215 {
216 RADV_FROM_HANDLE(radv_instance, instance, _instance);
217
218 if (instance->physicalDeviceCount > 0) {
219 /* We support at most one physical device. */
220 assert(instance->physicalDeviceCount == 1);
221 radv_physical_device_finish(&instance->physicalDevice);
222 }
223
224 VG(VALGRIND_DESTROY_MEMPOOL(instance));
225
226 _mesa_locale_fini();
227
228 radv_free(&instance->alloc, instance);
229 }
230
231 VkResult radv_EnumeratePhysicalDevices(
232 VkInstance _instance,
233 uint32_t* pPhysicalDeviceCount,
234 VkPhysicalDevice* pPhysicalDevices)
235 {
236 RADV_FROM_HANDLE(radv_instance, instance, _instance);
237 VkResult result;
238
239 if (instance->physicalDeviceCount < 0) {
240 char path[20];
241 for (unsigned i = 0; i < 8; i++) {
242 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
243 result = radv_physical_device_init(&instance->physicalDevice,
244 instance, path);
245 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
246 break;
247 }
248
249 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
250 instance->physicalDeviceCount = 0;
251 } else if (result == VK_SUCCESS) {
252 instance->physicalDeviceCount = 1;
253 } else {
254 return result;
255 }
256 }
257
258 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
259 * otherwise it's an inout parameter.
260 *
261 * The Vulkan spec (git aaed022) says:
262 *
263 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
264 * that is initialized with the number of devices the application is
265 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
266 * an array of at least this many VkPhysicalDevice handles [...].
267 *
268 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
269 * overwrites the contents of the variable pointed to by
270 * pPhysicalDeviceCount with the number of physical devices in in the
271 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
272 * pPhysicalDeviceCount with the number of physical handles written to
273 * pPhysicalDevices.
274 */
275 if (!pPhysicalDevices) {
276 *pPhysicalDeviceCount = instance->physicalDeviceCount;
277 } else if (*pPhysicalDeviceCount >= 1) {
278 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
279 *pPhysicalDeviceCount = 1;
280 } else {
281 *pPhysicalDeviceCount = 0;
282 }
283
284 return VK_SUCCESS;
285 }
286
287 void radv_GetPhysicalDeviceFeatures(
288 VkPhysicalDevice physicalDevice,
289 VkPhysicalDeviceFeatures* pFeatures)
290 {
291 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
292
293 memset(pFeatures, 0, sizeof(*pFeatures));
294
295 *pFeatures = (VkPhysicalDeviceFeatures) {
296 .robustBufferAccess = true,
297 .fullDrawIndexUint32 = true,
298 .imageCubeArray = true,
299 .independentBlend = true,
300 .geometryShader = false,
301 .tessellationShader = false,
302 .sampleRateShading = false,
303 .dualSrcBlend = true,
304 .logicOp = true,
305 .multiDrawIndirect = true,
306 .drawIndirectFirstInstance = true,
307 .depthClamp = true,
308 .depthBiasClamp = true,
309 .fillModeNonSolid = true,
310 .depthBounds = true,
311 .wideLines = true,
312 .largePoints = true,
313 .alphaToOne = true,
314 .multiViewport = false,
315 .samplerAnisotropy = false, /* FINISHME */
316 .textureCompressionETC2 = false,
317 .textureCompressionASTC_LDR = false,
318 .textureCompressionBC = true,
319 .occlusionQueryPrecise = true,
320 .pipelineStatisticsQuery = false,
321 .vertexPipelineStoresAndAtomics = true,
322 .fragmentStoresAndAtomics = true,
323 .shaderTessellationAndGeometryPointSize = true,
324 .shaderImageGatherExtended = false,
325 .shaderStorageImageExtendedFormats = false,
326 .shaderStorageImageMultisample = false,
327 .shaderUniformBufferArrayDynamicIndexing = true,
328 .shaderSampledImageArrayDynamicIndexing = true,
329 .shaderStorageBufferArrayDynamicIndexing = true,
330 .shaderStorageImageArrayDynamicIndexing = true,
331 .shaderStorageImageReadWithoutFormat = false,
332 .shaderStorageImageWriteWithoutFormat = true,
333 .shaderClipDistance = true,
334 .shaderCullDistance = true,
335 .shaderFloat64 = false,
336 .shaderInt64 = false,
337 .shaderInt16 = false,
338 .alphaToOne = true,
339 .variableMultisampleRate = false,
340 .inheritedQueries = false,
341 };
342 }
343
344 void
345 radv_device_get_cache_uuid(void *uuid)
346 {
347 memset(uuid, 0, VK_UUID_SIZE);
348 snprintf(uuid, VK_UUID_SIZE, "radv-%s", RADV_TIMESTAMP);
349 }
350
351 void radv_GetPhysicalDeviceProperties(
352 VkPhysicalDevice physicalDevice,
353 VkPhysicalDeviceProperties* pProperties)
354 {
355 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
356 VkSampleCountFlags sample_counts = 0xf;
357 VkPhysicalDeviceLimits limits = {
358 .maxImageDimension1D = (1 << 14),
359 .maxImageDimension2D = (1 << 14),
360 .maxImageDimension3D = (1 << 11),
361 .maxImageDimensionCube = (1 << 14),
362 .maxImageArrayLayers = (1 << 11),
363 .maxTexelBufferElements = 128 * 1024 * 1024,
364 .maxUniformBufferRange = UINT32_MAX,
365 .maxStorageBufferRange = UINT32_MAX,
366 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
367 .maxMemoryAllocationCount = UINT32_MAX,
368 .maxSamplerAllocationCount = 64 * 1024,
369 .bufferImageGranularity = 64, /* A cache line */
370 .sparseAddressSpaceSize = 0,
371 .maxBoundDescriptorSets = MAX_SETS,
372 .maxPerStageDescriptorSamplers = 64,
373 .maxPerStageDescriptorUniformBuffers = 64,
374 .maxPerStageDescriptorStorageBuffers = 64,
375 .maxPerStageDescriptorSampledImages = 64,
376 .maxPerStageDescriptorStorageImages = 64,
377 .maxPerStageDescriptorInputAttachments = 64,
378 .maxPerStageResources = 128,
379 .maxDescriptorSetSamplers = 256,
380 .maxDescriptorSetUniformBuffers = 256,
381 .maxDescriptorSetUniformBuffersDynamic = 256,
382 .maxDescriptorSetStorageBuffers = 256,
383 .maxDescriptorSetStorageBuffersDynamic = 256,
384 .maxDescriptorSetSampledImages = 256,
385 .maxDescriptorSetStorageImages = 256,
386 .maxDescriptorSetInputAttachments = 256,
387 .maxVertexInputAttributes = 32,
388 .maxVertexInputBindings = 32,
389 .maxVertexInputAttributeOffset = 2047,
390 .maxVertexInputBindingStride = 2048,
391 .maxVertexOutputComponents = 128,
392 .maxTessellationGenerationLevel = 0,
393 .maxTessellationPatchSize = 0,
394 .maxTessellationControlPerVertexInputComponents = 0,
395 .maxTessellationControlPerVertexOutputComponents = 0,
396 .maxTessellationControlPerPatchOutputComponents = 0,
397 .maxTessellationControlTotalOutputComponents = 0,
398 .maxTessellationEvaluationInputComponents = 0,
399 .maxTessellationEvaluationOutputComponents = 0,
400 .maxGeometryShaderInvocations = 32,
401 .maxGeometryInputComponents = 64,
402 .maxGeometryOutputComponents = 128,
403 .maxGeometryOutputVertices = 256,
404 .maxGeometryTotalOutputComponents = 1024,
405 .maxFragmentInputComponents = 128,
406 .maxFragmentOutputAttachments = 8,
407 .maxFragmentDualSrcAttachments = 2,
408 .maxFragmentCombinedOutputResources = 8,
409 .maxComputeSharedMemorySize = 32768,
410 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
411 .maxComputeWorkGroupInvocations = 16 * 1024,
412 .maxComputeWorkGroupSize = {
413 16 * 1024/*devinfo->max_cs_threads*/,
414 16 * 1024,
415 16 * 1024
416 },
417 .subPixelPrecisionBits = 4 /* FIXME */,
418 .subTexelPrecisionBits = 4 /* FIXME */,
419 .mipmapPrecisionBits = 4 /* FIXME */,
420 .maxDrawIndexedIndexValue = UINT32_MAX,
421 .maxDrawIndirectCount = UINT32_MAX,
422 .maxSamplerLodBias = 16,
423 .maxSamplerAnisotropy = 16,
424 .maxViewports = MAX_VIEWPORTS,
425 .maxViewportDimensions = { (1 << 14), (1 << 14) },
426 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
427 .viewportSubPixelBits = 13, /* We take a float? */
428 .minMemoryMapAlignment = 4096, /* A page */
429 .minTexelBufferOffsetAlignment = 1,
430 .minUniformBufferOffsetAlignment = 4,
431 .minStorageBufferOffsetAlignment = 4,
432 .minTexelOffset = -8,
433 .maxTexelOffset = 7,
434 .minTexelGatherOffset = -8,
435 .maxTexelGatherOffset = 7,
436 .minInterpolationOffset = 0, /* FIXME */
437 .maxInterpolationOffset = 0, /* FIXME */
438 .subPixelInterpolationOffsetBits = 0, /* FIXME */
439 .maxFramebufferWidth = (1 << 14),
440 .maxFramebufferHeight = (1 << 14),
441 .maxFramebufferLayers = (1 << 10),
442 .framebufferColorSampleCounts = sample_counts,
443 .framebufferDepthSampleCounts = sample_counts,
444 .framebufferStencilSampleCounts = sample_counts,
445 .framebufferNoAttachmentsSampleCounts = sample_counts,
446 .maxColorAttachments = MAX_RTS,
447 .sampledImageColorSampleCounts = sample_counts,
448 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
449 .sampledImageDepthSampleCounts = sample_counts,
450 .sampledImageStencilSampleCounts = sample_counts,
451 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
452 .maxSampleMaskWords = 1,
453 .timestampComputeAndGraphics = false,
454 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
455 .maxClipDistances = 8,
456 .maxCullDistances = 8,
457 .maxCombinedClipAndCullDistances = 8,
458 .discreteQueuePriorities = 1,
459 .pointSizeRange = { 0.125, 255.875 },
460 .lineWidthRange = { 0.0, 7.9921875 },
461 .pointSizeGranularity = (1.0 / 8.0),
462 .lineWidthGranularity = (1.0 / 128.0),
463 .strictLines = false, /* FINISHME */
464 .standardSampleLocations = true,
465 .optimalBufferCopyOffsetAlignment = 128,
466 .optimalBufferCopyRowPitchAlignment = 128,
467 .nonCoherentAtomSize = 64,
468 };
469
470 *pProperties = (VkPhysicalDeviceProperties) {
471 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
472 .driverVersion = 1,
473 .vendorID = 0x1002,
474 .deviceID = pdevice->rad_info.pci_id,
475 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
476 .limits = limits,
477 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
478 };
479
480 strcpy(pProperties->deviceName, pdevice->name);
481 radv_device_get_cache_uuid(pProperties->pipelineCacheUUID);
482 }
483
484 void radv_GetPhysicalDeviceQueueFamilyProperties(
485 VkPhysicalDevice physicalDevice,
486 uint32_t* pCount,
487 VkQueueFamilyProperties* pQueueFamilyProperties)
488 {
489 if (pQueueFamilyProperties == NULL) {
490 *pCount = 1;
491 return;
492 }
493 assert(*pCount >= 1);
494
495 *pQueueFamilyProperties = (VkQueueFamilyProperties) {
496 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
497 VK_QUEUE_COMPUTE_BIT |
498 VK_QUEUE_TRANSFER_BIT,
499 .queueCount = 1,
500 .timestampValidBits = 64,
501 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
502 };
503 }
504
505 void radv_GetPhysicalDeviceMemoryProperties(
506 VkPhysicalDevice physicalDevice,
507 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
508 {
509 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
510
511 pMemoryProperties->memoryTypeCount = 3;
512 pMemoryProperties->memoryTypes[0] = (VkMemoryType) {
513 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
514 .heapIndex = 0,
515 };
516 pMemoryProperties->memoryTypes[1] = (VkMemoryType) {
517 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
518 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
519 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
520 .heapIndex = 0,
521 };
522 pMemoryProperties->memoryTypes[2] = (VkMemoryType) {
523 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT|
524 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
525 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
526 .heapIndex = 1,
527 };
528
529 pMemoryProperties->memoryHeapCount = 2;
530 pMemoryProperties->memoryHeaps[0] = (VkMemoryHeap) {
531 .size = physical_device->rad_info.vram_size,
532 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
533 };
534 pMemoryProperties->memoryHeaps[1] = (VkMemoryHeap) {
535 .size = physical_device->rad_info.gart_size,
536 .flags = 0,
537 };
538 }
539
540 static VkResult
541 radv_queue_init(struct radv_device *device, struct radv_queue *queue)
542 {
543 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
544 queue->device = device;
545
546 return VK_SUCCESS;
547 }
548
549 static void
550 radv_queue_finish(struct radv_queue *queue)
551 {
552 }
553
554 VkResult radv_CreateDevice(
555 VkPhysicalDevice physicalDevice,
556 const VkDeviceCreateInfo* pCreateInfo,
557 const VkAllocationCallbacks* pAllocator,
558 VkDevice* pDevice)
559 {
560 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
561 VkResult result;
562 struct radv_device *device;
563
564 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
565 bool found = false;
566 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
567 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
568 device_extensions[j].extensionName) == 0) {
569 found = true;
570 break;
571 }
572 }
573 if (!found)
574 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
575 }
576
577 device = radv_alloc2(&physical_device->instance->alloc, pAllocator,
578 sizeof(*device), 8,
579 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
580 if (!device)
581 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
582
583 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
584 device->instance = physical_device->instance;
585
586 device->ws = physical_device->ws;
587 if (pAllocator)
588 device->alloc = *pAllocator;
589 else
590 device->alloc = physical_device->instance->alloc;
591
592 device->hw_ctx = device->ws->ctx_create(device->ws);
593 if (!device->hw_ctx) {
594 result = VK_ERROR_OUT_OF_HOST_MEMORY;
595 goto fail_free;
596 }
597
598 radv_queue_init(device, &device->queue);
599
600 result = radv_device_init_meta(device);
601 if (result != VK_SUCCESS) {
602 device->ws->ctx_destroy(device->hw_ctx);
603 goto fail_free;
604 }
605 device->allow_fast_clears = env_var_as_boolean("RADV_FAST_CLEARS", false);
606 device->allow_dcc = !env_var_as_boolean("RADV_DCC_DISABLE", false);
607
608 if (device->allow_fast_clears && device->allow_dcc)
609 radv_finishme("DCC fast clears have not been tested\n");
610
611 radv_device_init_msaa(device);
612 device->empty_cs = device->ws->cs_create(device->ws, RING_GFX);
613 radeon_emit(device->empty_cs, PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
614 radeon_emit(device->empty_cs, CONTEXT_CONTROL_LOAD_ENABLE(1));
615 radeon_emit(device->empty_cs, CONTEXT_CONTROL_SHADOW_ENABLE(1));
616 device->ws->cs_finalize(device->empty_cs);
617 *pDevice = radv_device_to_handle(device);
618 return VK_SUCCESS;
619 fail_free:
620 radv_free(&device->alloc, device);
621 return result;
622 }
623
624 void radv_DestroyDevice(
625 VkDevice _device,
626 const VkAllocationCallbacks* pAllocator)
627 {
628 RADV_FROM_HANDLE(radv_device, device, _device);
629
630 device->ws->ctx_destroy(device->hw_ctx);
631 radv_queue_finish(&device->queue);
632 radv_device_finish_meta(device);
633
634 radv_free(&device->alloc, device);
635 }
636
637 VkResult radv_EnumerateInstanceExtensionProperties(
638 const char* pLayerName,
639 uint32_t* pPropertyCount,
640 VkExtensionProperties* pProperties)
641 {
642 unsigned i;
643 if (pProperties == NULL) {
644 *pPropertyCount = ARRAY_SIZE(global_extensions);
645 return VK_SUCCESS;
646 }
647
648 for (i = 0; i < *pPropertyCount; i++)
649 memcpy(&pProperties[i], &global_extensions[i], sizeof(VkExtensionProperties));
650
651 *pPropertyCount = i;
652 if (i < ARRAY_SIZE(global_extensions))
653 return VK_INCOMPLETE;
654
655 return VK_SUCCESS;
656 }
657
658 VkResult radv_EnumerateDeviceExtensionProperties(
659 VkPhysicalDevice physicalDevice,
660 const char* pLayerName,
661 uint32_t* pPropertyCount,
662 VkExtensionProperties* pProperties)
663 {
664 unsigned i;
665
666 if (pProperties == NULL) {
667 *pPropertyCount = ARRAY_SIZE(device_extensions);
668 return VK_SUCCESS;
669 }
670
671 for (i = 0; i < *pPropertyCount; i++)
672 memcpy(&pProperties[i], &device_extensions[i], sizeof(VkExtensionProperties));
673
674 *pPropertyCount = i;
675 if (i < ARRAY_SIZE(device_extensions))
676 return VK_INCOMPLETE;
677 return VK_SUCCESS;
678 }
679
680 VkResult radv_EnumerateInstanceLayerProperties(
681 uint32_t* pPropertyCount,
682 VkLayerProperties* pProperties)
683 {
684 if (pProperties == NULL) {
685 *pPropertyCount = 0;
686 return VK_SUCCESS;
687 }
688
689 /* None supported at this time */
690 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
691 }
692
693 VkResult radv_EnumerateDeviceLayerProperties(
694 VkPhysicalDevice physicalDevice,
695 uint32_t* pPropertyCount,
696 VkLayerProperties* pProperties)
697 {
698 if (pProperties == NULL) {
699 *pPropertyCount = 0;
700 return VK_SUCCESS;
701 }
702
703 /* None supported at this time */
704 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
705 }
706
707 void radv_GetDeviceQueue(
708 VkDevice _device,
709 uint32_t queueNodeIndex,
710 uint32_t queueIndex,
711 VkQueue* pQueue)
712 {
713 RADV_FROM_HANDLE(radv_device, device, _device);
714
715 assert(queueIndex == 0);
716
717 *pQueue = radv_queue_to_handle(&device->queue);
718 }
719
720 VkResult radv_QueueSubmit(
721 VkQueue _queue,
722 uint32_t submitCount,
723 const VkSubmitInfo* pSubmits,
724 VkFence _fence)
725 {
726 RADV_FROM_HANDLE(radv_queue, queue, _queue);
727 RADV_FROM_HANDLE(radv_fence, fence, _fence);
728 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
729 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
730 int ret;
731
732 for (uint32_t i = 0; i < submitCount; i++) {
733 struct radeon_winsys_cs **cs_array;
734 bool can_patch = true;
735
736 if (!pSubmits[i].commandBufferCount)
737 continue;
738
739 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
740 pSubmits[i].commandBufferCount);
741
742 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
743 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
744 pSubmits[i].pCommandBuffers[j]);
745 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
746
747 cs_array[j] = cmd_buffer->cs;
748 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
749 can_patch = false;
750 }
751 ret = queue->device->ws->cs_submit(ctx, cs_array,
752 pSubmits[i].commandBufferCount,
753 can_patch, base_fence);
754 if (ret)
755 radv_loge("failed to submit CS %d\n", i);
756 free(cs_array);
757 }
758
759 if (fence) {
760 if (!submitCount)
761 ret = queue->device->ws->cs_submit(ctx, &queue->device->empty_cs,
762 1, false, base_fence);
763
764 fence->submitted = true;
765 }
766
767 return VK_SUCCESS;
768 }
769
770 VkResult radv_QueueWaitIdle(
771 VkQueue _queue)
772 {
773 RADV_FROM_HANDLE(radv_queue, queue, _queue);
774
775 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx);
776 return VK_SUCCESS;
777 }
778
779 VkResult radv_DeviceWaitIdle(
780 VkDevice _device)
781 {
782 RADV_FROM_HANDLE(radv_device, device, _device);
783
784 device->ws->ctx_wait_idle(device->hw_ctx);
785 return VK_SUCCESS;
786 }
787
788 PFN_vkVoidFunction radv_GetInstanceProcAddr(
789 VkInstance instance,
790 const char* pName)
791 {
792 return radv_lookup_entrypoint(pName);
793 }
794
795 /* The loader wants us to expose a second GetInstanceProcAddr function
796 * to work around certain LD_PRELOAD issues seen in apps.
797 */
798 PUBLIC
799 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
800 VkInstance instance,
801 const char* pName);
802
803 PUBLIC
804 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
805 VkInstance instance,
806 const char* pName)
807 {
808 return radv_GetInstanceProcAddr(instance, pName);
809 }
810
811 PFN_vkVoidFunction radv_GetDeviceProcAddr(
812 VkDevice device,
813 const char* pName)
814 {
815 return radv_lookup_entrypoint(pName);
816 }
817
818 VkResult radv_AllocateMemory(
819 VkDevice _device,
820 const VkMemoryAllocateInfo* pAllocateInfo,
821 const VkAllocationCallbacks* pAllocator,
822 VkDeviceMemory* pMem)
823 {
824 RADV_FROM_HANDLE(radv_device, device, _device);
825 struct radv_device_memory *mem;
826 VkResult result;
827 enum radeon_bo_domain domain;
828 uint32_t flags = 0;
829 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
830
831 if (pAllocateInfo->allocationSize == 0) {
832 /* Apparently, this is allowed */
833 *pMem = VK_NULL_HANDLE;
834 return VK_SUCCESS;
835 }
836
837 mem = radv_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
838 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
839 if (mem == NULL)
840 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
841
842 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
843 if (pAllocateInfo->memoryTypeIndex == 2)
844 domain = RADEON_DOMAIN_GTT;
845 else
846 domain = RADEON_DOMAIN_VRAM;
847
848 if (pAllocateInfo->memoryTypeIndex == 0)
849 flags |= RADEON_FLAG_NO_CPU_ACCESS;
850 else
851 flags |= RADEON_FLAG_CPU_ACCESS;
852 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
853 domain, flags);
854
855 if (!mem->bo) {
856 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
857 goto fail;
858 }
859 mem->type_index = pAllocateInfo->memoryTypeIndex;
860
861 *pMem = radv_device_memory_to_handle(mem);
862
863 return VK_SUCCESS;
864
865 fail:
866 radv_free2(&device->alloc, pAllocator, mem);
867
868 return result;
869 }
870
871 void radv_FreeMemory(
872 VkDevice _device,
873 VkDeviceMemory _mem,
874 const VkAllocationCallbacks* pAllocator)
875 {
876 RADV_FROM_HANDLE(radv_device, device, _device);
877 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
878
879 if (mem == NULL)
880 return;
881
882 device->ws->buffer_destroy(mem->bo);
883 mem->bo = NULL;
884
885 radv_free2(&device->alloc, pAllocator, mem);
886 }
887
888 VkResult radv_MapMemory(
889 VkDevice _device,
890 VkDeviceMemory _memory,
891 VkDeviceSize offset,
892 VkDeviceSize size,
893 VkMemoryMapFlags flags,
894 void** ppData)
895 {
896 RADV_FROM_HANDLE(radv_device, device, _device);
897 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
898
899 if (mem == NULL) {
900 *ppData = NULL;
901 return VK_SUCCESS;
902 }
903
904 *ppData = device->ws->buffer_map(mem->bo);
905 if (*ppData) {
906 *ppData += offset;
907 return VK_SUCCESS;
908 }
909
910 return VK_ERROR_MEMORY_MAP_FAILED;
911 }
912
913 void radv_UnmapMemory(
914 VkDevice _device,
915 VkDeviceMemory _memory)
916 {
917 RADV_FROM_HANDLE(radv_device, device, _device);
918 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
919
920 if (mem == NULL)
921 return;
922
923 device->ws->buffer_unmap(mem->bo);
924 }
925
926 VkResult radv_FlushMappedMemoryRanges(
927 VkDevice _device,
928 uint32_t memoryRangeCount,
929 const VkMappedMemoryRange* pMemoryRanges)
930 {
931 return VK_SUCCESS;
932 }
933
934 VkResult radv_InvalidateMappedMemoryRanges(
935 VkDevice _device,
936 uint32_t memoryRangeCount,
937 const VkMappedMemoryRange* pMemoryRanges)
938 {
939 return VK_SUCCESS;
940 }
941
942 void radv_GetBufferMemoryRequirements(
943 VkDevice device,
944 VkBuffer _buffer,
945 VkMemoryRequirements* pMemoryRequirements)
946 {
947 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
948
949 /* The Vulkan spec (git aaed022) says:
950 *
951 * memoryTypeBits is a bitfield and contains one bit set for every
952 * supported memory type for the resource. The bit `1<<i` is set if and
953 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
954 * structure for the physical device is supported.
955 *
956 * We support exactly one memory type.
957 */
958 pMemoryRequirements->memoryTypeBits = 0x7;
959
960 pMemoryRequirements->size = buffer->size;
961 pMemoryRequirements->alignment = 16;
962 }
963
964 void radv_GetImageMemoryRequirements(
965 VkDevice device,
966 VkImage _image,
967 VkMemoryRequirements* pMemoryRequirements)
968 {
969 RADV_FROM_HANDLE(radv_image, image, _image);
970
971 /* The Vulkan spec (git aaed022) says:
972 *
973 * memoryTypeBits is a bitfield and contains one bit set for every
974 * supported memory type for the resource. The bit `1<<i` is set if and
975 * only if the memory type `i` in the VkPhysicalDeviceMemoryProperties
976 * structure for the physical device is supported.
977 *
978 * We support exactly one memory type.
979 */
980 pMemoryRequirements->memoryTypeBits = 0x7;
981
982 pMemoryRequirements->size = image->size;
983 pMemoryRequirements->alignment = image->alignment;
984 }
985
986 void radv_GetImageSparseMemoryRequirements(
987 VkDevice device,
988 VkImage image,
989 uint32_t* pSparseMemoryRequirementCount,
990 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
991 {
992 stub();
993 }
994
995 void radv_GetDeviceMemoryCommitment(
996 VkDevice device,
997 VkDeviceMemory memory,
998 VkDeviceSize* pCommittedMemoryInBytes)
999 {
1000 *pCommittedMemoryInBytes = 0;
1001 }
1002
1003 VkResult radv_BindBufferMemory(
1004 VkDevice device,
1005 VkBuffer _buffer,
1006 VkDeviceMemory _memory,
1007 VkDeviceSize memoryOffset)
1008 {
1009 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1010 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1011
1012 if (mem) {
1013 buffer->bo = mem->bo;
1014 buffer->offset = memoryOffset;
1015 } else {
1016 buffer->bo = NULL;
1017 buffer->offset = 0;
1018 }
1019
1020 return VK_SUCCESS;
1021 }
1022
1023 VkResult radv_BindImageMemory(
1024 VkDevice device,
1025 VkImage _image,
1026 VkDeviceMemory _memory,
1027 VkDeviceSize memoryOffset)
1028 {
1029 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1030 RADV_FROM_HANDLE(radv_image, image, _image);
1031
1032 if (mem) {
1033 image->bo = mem->bo;
1034 image->offset = memoryOffset;
1035 } else {
1036 image->bo = NULL;
1037 image->offset = 0;
1038 }
1039
1040 return VK_SUCCESS;
1041 }
1042
1043 VkResult radv_QueueBindSparse(
1044 VkQueue queue,
1045 uint32_t bindInfoCount,
1046 const VkBindSparseInfo* pBindInfo,
1047 VkFence fence)
1048 {
1049 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1050 }
1051
1052 VkResult radv_CreateFence(
1053 VkDevice _device,
1054 const VkFenceCreateInfo* pCreateInfo,
1055 const VkAllocationCallbacks* pAllocator,
1056 VkFence* pFence)
1057 {
1058 RADV_FROM_HANDLE(radv_device, device, _device);
1059 struct radv_fence *fence = radv_alloc2(&device->alloc, pAllocator,
1060 sizeof(*fence), 8,
1061 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1062
1063 if (!fence)
1064 return VK_ERROR_OUT_OF_HOST_MEMORY;
1065
1066 memset(fence, 0, sizeof(*fence));
1067 fence->submitted = false;
1068 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1069 fence->fence = device->ws->create_fence();
1070
1071
1072 *pFence = radv_fence_to_handle(fence);
1073
1074 return VK_SUCCESS;
1075 }
1076
1077 void radv_DestroyFence(
1078 VkDevice _device,
1079 VkFence _fence,
1080 const VkAllocationCallbacks* pAllocator)
1081 {
1082 RADV_FROM_HANDLE(radv_device, device, _device);
1083 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1084
1085 if (!fence)
1086 return;
1087 device->ws->destroy_fence(fence->fence);
1088 radv_free2(&device->alloc, pAllocator, fence);
1089 }
1090
1091 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1092 {
1093 uint64_t current_time;
1094 struct timespec tv;
1095
1096 clock_gettime(CLOCK_MONOTONIC, &tv);
1097 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1098
1099 timeout = MIN2(UINT64_MAX - current_time, timeout);
1100
1101 return current_time + timeout;
1102 }
1103
1104 VkResult radv_WaitForFences(
1105 VkDevice _device,
1106 uint32_t fenceCount,
1107 const VkFence* pFences,
1108 VkBool32 waitAll,
1109 uint64_t timeout)
1110 {
1111 RADV_FROM_HANDLE(radv_device, device, _device);
1112 timeout = radv_get_absolute_timeout(timeout);
1113
1114 if (!waitAll && fenceCount > 1) {
1115 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1116 }
1117
1118 for (uint32_t i = 0; i < fenceCount; ++i) {
1119 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1120 bool expired = false;
1121
1122 if (!fence->submitted)
1123 return VK_TIMEOUT;
1124
1125 if (fence->signalled)
1126 continue;
1127
1128 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1129 if (!expired)
1130 return VK_TIMEOUT;
1131
1132 fence->signalled = true;
1133 }
1134
1135 return VK_SUCCESS;
1136 }
1137
1138 VkResult radv_ResetFences(VkDevice device,
1139 uint32_t fenceCount,
1140 const VkFence *pFences)
1141 {
1142 for (unsigned i = 0; i < fenceCount; ++i) {
1143 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1144 fence->submitted = fence->signalled = false;
1145 }
1146
1147 return VK_SUCCESS;
1148 }
1149
1150 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1151 {
1152 RADV_FROM_HANDLE(radv_device, device, _device);
1153 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1154
1155 if (!fence->submitted)
1156 return VK_NOT_READY;
1157
1158 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1159 return VK_NOT_READY;
1160
1161 return VK_SUCCESS;
1162 }
1163
1164
1165 // Queue semaphore functions
1166
1167 VkResult radv_CreateSemaphore(
1168 VkDevice device,
1169 const VkSemaphoreCreateInfo* pCreateInfo,
1170 const VkAllocationCallbacks* pAllocator,
1171 VkSemaphore* pSemaphore)
1172 {
1173 /* The DRM execbuffer ioctl always execute in-oder, even between different
1174 * rings. As such, there's nothing to do for the user space semaphore.
1175 */
1176
1177 *pSemaphore = (VkSemaphore)1;
1178
1179 return VK_SUCCESS;
1180 }
1181
1182 void radv_DestroySemaphore(
1183 VkDevice device,
1184 VkSemaphore semaphore,
1185 const VkAllocationCallbacks* pAllocator)
1186 {
1187 }
1188
1189 VkResult radv_CreateEvent(
1190 VkDevice _device,
1191 const VkEventCreateInfo* pCreateInfo,
1192 const VkAllocationCallbacks* pAllocator,
1193 VkEvent* pEvent)
1194 {
1195 RADV_FROM_HANDLE(radv_device, device, _device);
1196 struct radv_event *event = radv_alloc2(&device->alloc, pAllocator,
1197 sizeof(*event), 8,
1198 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1199
1200 if (!event)
1201 return VK_ERROR_OUT_OF_HOST_MEMORY;
1202
1203 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1204 RADEON_DOMAIN_GTT,
1205 RADEON_FLAG_CPU_ACCESS);
1206 if (!event->bo) {
1207 radv_free2(&device->alloc, pAllocator, event);
1208 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1209 }
1210
1211 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1212
1213 *pEvent = radv_event_to_handle(event);
1214
1215 return VK_SUCCESS;
1216 }
1217
1218 void radv_DestroyEvent(
1219 VkDevice _device,
1220 VkEvent _event,
1221 const VkAllocationCallbacks* pAllocator)
1222 {
1223 RADV_FROM_HANDLE(radv_device, device, _device);
1224 RADV_FROM_HANDLE(radv_event, event, _event);
1225
1226 if (!event)
1227 return;
1228 device->ws->buffer_destroy(event->bo);
1229 radv_free2(&device->alloc, pAllocator, event);
1230 }
1231
1232 VkResult radv_GetEventStatus(
1233 VkDevice _device,
1234 VkEvent _event)
1235 {
1236 RADV_FROM_HANDLE(radv_event, event, _event);
1237
1238 if (*event->map == 1)
1239 return VK_EVENT_SET;
1240 return VK_EVENT_RESET;
1241 }
1242
1243 VkResult radv_SetEvent(
1244 VkDevice _device,
1245 VkEvent _event)
1246 {
1247 RADV_FROM_HANDLE(radv_event, event, _event);
1248 *event->map = 1;
1249
1250 return VK_SUCCESS;
1251 }
1252
1253 VkResult radv_ResetEvent(
1254 VkDevice _device,
1255 VkEvent _event)
1256 {
1257 RADV_FROM_HANDLE(radv_event, event, _event);
1258 *event->map = 0;
1259
1260 return VK_SUCCESS;
1261 }
1262
1263 VkResult radv_CreateBuffer(
1264 VkDevice _device,
1265 const VkBufferCreateInfo* pCreateInfo,
1266 const VkAllocationCallbacks* pAllocator,
1267 VkBuffer* pBuffer)
1268 {
1269 RADV_FROM_HANDLE(radv_device, device, _device);
1270 struct radv_buffer *buffer;
1271
1272 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1273
1274 buffer = radv_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1275 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1276 if (buffer == NULL)
1277 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1278
1279 buffer->size = pCreateInfo->size;
1280 buffer->usage = pCreateInfo->usage;
1281 buffer->bo = NULL;
1282 buffer->offset = 0;
1283
1284 *pBuffer = radv_buffer_to_handle(buffer);
1285
1286 return VK_SUCCESS;
1287 }
1288
1289 void radv_DestroyBuffer(
1290 VkDevice _device,
1291 VkBuffer _buffer,
1292 const VkAllocationCallbacks* pAllocator)
1293 {
1294 RADV_FROM_HANDLE(radv_device, device, _device);
1295 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1296
1297 if (!buffer)
1298 return;
1299
1300 radv_free2(&device->alloc, pAllocator, buffer);
1301 }
1302
1303 static inline unsigned
1304 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1305 {
1306 if (stencil)
1307 return image->surface.stencil_tiling_index[level];
1308 else
1309 return image->surface.tiling_index[level];
1310 }
1311
1312 static void
1313 radv_initialise_color_surface(struct radv_device *device,
1314 struct radv_color_buffer_info *cb,
1315 struct radv_image_view *iview)
1316 {
1317 const struct vk_format_description *desc;
1318 unsigned ntype, format, swap, endian;
1319 unsigned blend_clamp = 0, blend_bypass = 0;
1320 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1321 uint64_t va;
1322 const struct radeon_surf *surf = &iview->image->surface;
1323 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1324
1325 desc = vk_format_description(iview->vk_format);
1326
1327 memset(cb, 0, sizeof(*cb));
1328
1329 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1330 va += level_info->offset;
1331 cb->cb_color_base = va >> 8;
1332
1333 /* CMASK variables */
1334 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1335 va += iview->image->cmask.offset;
1336 cb->cb_color_cmask = va >> 8;
1337 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1338
1339 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1340 va += iview->image->dcc_offset;
1341 cb->cb_dcc_base = va >> 8;
1342
1343 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1344 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1345
1346 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1347 pitch_tile_max = level_info->nblk_x / 8 - 1;
1348 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1349 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1350
1351 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1352 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1353
1354 /* Intensity is implemented as Red, so treat it that way. */
1355 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1356 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1357
1358 if (iview->image->samples > 1) {
1359 unsigned log_samples = util_logbase2(iview->image->samples);
1360
1361 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1362 S_028C74_NUM_FRAGMENTS(log_samples);
1363 }
1364
1365 if (iview->image->fmask.size) {
1366 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1367 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1368 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1369 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1370 cb->cb_color_fmask = va >> 8;
1371 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1372 } else {
1373 /* This must be set for fast clear to work without FMASK. */
1374 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1375 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1376 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1377 cb->cb_color_fmask = cb->cb_color_base;
1378 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1379 }
1380
1381 ntype = radv_translate_color_numformat(iview->vk_format,
1382 desc,
1383 vk_format_get_first_non_void_channel(iview->vk_format));
1384 format = radv_translate_colorformat(iview->vk_format);
1385 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1386 radv_finishme("Illegal color\n");
1387 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1388 endian = radv_colorformat_endian_swap(format);
1389
1390 /* blend clamp should be set for all NORM/SRGB types */
1391 if (ntype == V_028C70_NUMBER_UNORM ||
1392 ntype == V_028C70_NUMBER_SNORM ||
1393 ntype == V_028C70_NUMBER_SRGB)
1394 blend_clamp = 1;
1395
1396 /* set blend bypass according to docs if SINT/UINT or
1397 8/24 COLOR variants */
1398 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1399 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1400 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1401 blend_clamp = 0;
1402 blend_bypass = 1;
1403 }
1404 #if 0
1405 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1406 (format == V_028C70_COLOR_8 ||
1407 format == V_028C70_COLOR_8_8 ||
1408 format == V_028C70_COLOR_8_8_8_8))
1409 ->color_is_int8 = true;
1410 #endif
1411 cb->cb_color_info = S_028C70_FORMAT(format) |
1412 S_028C70_COMP_SWAP(swap) |
1413 S_028C70_BLEND_CLAMP(blend_clamp) |
1414 S_028C70_BLEND_BYPASS(blend_bypass) |
1415 S_028C70_SIMPLE_FLOAT(1) |
1416 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1417 ntype != V_028C70_NUMBER_SNORM &&
1418 ntype != V_028C70_NUMBER_SRGB &&
1419 format != V_028C70_COLOR_8_24 &&
1420 format != V_028C70_COLOR_24_8) |
1421 S_028C70_NUMBER_TYPE(ntype) |
1422 S_028C70_ENDIAN(endian);
1423 if (iview->image->samples > 1)
1424 if (iview->image->fmask.size)
1425 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1426
1427 if (iview->image->cmask.size && device->allow_fast_clears)
1428 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1429
1430 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1431 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1432
1433 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1434 unsigned max_uncompressed_block_size = 2;
1435 if (iview->image->samples > 1) {
1436 if (iview->image->surface.bpe == 1)
1437 max_uncompressed_block_size = 0;
1438 else if (iview->image->surface.bpe == 2)
1439 max_uncompressed_block_size = 1;
1440 }
1441
1442 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1443 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1444 }
1445
1446 /* This must be set for fast clear to work without FMASK. */
1447 if (!iview->image->fmask.size &&
1448 device->instance->physicalDevice.rad_info.chip_class == SI) {
1449 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1450 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1451 }
1452 }
1453
1454 static void
1455 radv_initialise_ds_surface(struct radv_device *device,
1456 struct radv_ds_buffer_info *ds,
1457 struct radv_image_view *iview)
1458 {
1459 unsigned level = iview->base_mip;
1460 unsigned format;
1461 uint64_t va, s_offs, z_offs;
1462 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1463 memset(ds, 0, sizeof(*ds));
1464 switch (iview->vk_format) {
1465 case VK_FORMAT_D24_UNORM_S8_UINT:
1466 case VK_FORMAT_X8_D24_UNORM_PACK32:
1467 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1468 ds->offset_scale = 2.0f;
1469 break;
1470 case VK_FORMAT_D16_UNORM:
1471 case VK_FORMAT_D16_UNORM_S8_UINT:
1472 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1473 ds->offset_scale = 4.0f;
1474 break;
1475 case VK_FORMAT_D32_SFLOAT:
1476 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1477 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1478 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1479 ds->offset_scale = 1.0f;
1480 break;
1481 default:
1482 break;
1483 }
1484
1485 format = radv_translate_dbformat(iview->vk_format);
1486 if (format == V_028040_Z_INVALID) {
1487 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1488 }
1489
1490 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1491 s_offs = z_offs = va;
1492 z_offs += iview->image->surface.level[level].offset;
1493 s_offs += iview->image->surface.stencil_level[level].offset;
1494
1495 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1496 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1497 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1498 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1499
1500 if (iview->image->samples > 1)
1501 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1502
1503 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1504 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1505 else
1506 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1507
1508 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1509 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1510 unsigned tiling_index = iview->image->surface.tiling_index[level];
1511 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1512 unsigned macro_index = iview->image->surface.macro_tile_index;
1513 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1514 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1515 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1516
1517 ds->db_depth_info |=
1518 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1519 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1520 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1521 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1522 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1523 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1524 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1525 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1526 } else {
1527 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1528 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1529 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1530 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1531 }
1532
1533 if (iview->image->htile.size && !level) {
1534 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1535 S_028040_ALLOW_EXPCLEAR(1);
1536
1537 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1538 /* Workaround: For a not yet understood reason, the
1539 * combination of MSAA, fast stencil clear and stencil
1540 * decompress messes with subsequent stencil buffer
1541 * uses. Problem was reproduced on Verde, Bonaire,
1542 * Tonga, and Carrizo.
1543 *
1544 * Disabling EXPCLEAR works around the problem.
1545 *
1546 * Check piglit's arb_texture_multisample-stencil-clear
1547 * test if you want to try changing this.
1548 */
1549 if (iview->image->samples <= 1)
1550 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1551 } else
1552 /* Use all of the htile_buffer for depth if there's no stencil. */
1553 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1554
1555 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1556 iview->image->htile.offset;
1557 ds->db_htile_data_base = va >> 8;
1558 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1559 } else {
1560 ds->db_htile_data_base = 0;
1561 ds->db_htile_surface = 0;
1562 }
1563
1564 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1565 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1566
1567 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1568 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1569 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1570 }
1571
1572 VkResult radv_CreateFramebuffer(
1573 VkDevice _device,
1574 const VkFramebufferCreateInfo* pCreateInfo,
1575 const VkAllocationCallbacks* pAllocator,
1576 VkFramebuffer* pFramebuffer)
1577 {
1578 RADV_FROM_HANDLE(radv_device, device, _device);
1579 struct radv_framebuffer *framebuffer;
1580
1581 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1582
1583 size_t size = sizeof(*framebuffer) +
1584 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1585 framebuffer = radv_alloc2(&device->alloc, pAllocator, size, 8,
1586 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1587 if (framebuffer == NULL)
1588 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1589
1590 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1591 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1592 VkImageView _iview = pCreateInfo->pAttachments[i];
1593 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1594 framebuffer->attachments[i].attachment = iview;
1595 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1596 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1597 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1598 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1599 }
1600 }
1601
1602 framebuffer->width = pCreateInfo->width;
1603 framebuffer->height = pCreateInfo->height;
1604 framebuffer->layers = pCreateInfo->layers;
1605
1606 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1607 return VK_SUCCESS;
1608 }
1609
1610 void radv_DestroyFramebuffer(
1611 VkDevice _device,
1612 VkFramebuffer _fb,
1613 const VkAllocationCallbacks* pAllocator)
1614 {
1615 RADV_FROM_HANDLE(radv_device, device, _device);
1616 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1617
1618 if (!fb)
1619 return;
1620 radv_free2(&device->alloc, pAllocator, fb);
1621 }
1622
1623 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1624 {
1625 switch (address_mode) {
1626 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1627 return V_008F30_SQ_TEX_WRAP;
1628 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1629 return V_008F30_SQ_TEX_MIRROR;
1630 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1631 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1632 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1633 return V_008F30_SQ_TEX_CLAMP_BORDER;
1634 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1635 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1636 default:
1637 unreachable("illegal tex wrap mode");
1638 break;
1639 }
1640 }
1641
1642 static unsigned
1643 radv_tex_compare(VkCompareOp op)
1644 {
1645 switch (op) {
1646 case VK_COMPARE_OP_NEVER:
1647 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1648 case VK_COMPARE_OP_LESS:
1649 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1650 case VK_COMPARE_OP_EQUAL:
1651 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1652 case VK_COMPARE_OP_LESS_OR_EQUAL:
1653 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1654 case VK_COMPARE_OP_GREATER:
1655 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1656 case VK_COMPARE_OP_NOT_EQUAL:
1657 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1658 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1659 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1660 case VK_COMPARE_OP_ALWAYS:
1661 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1662 default:
1663 unreachable("illegal compare mode");
1664 break;
1665 }
1666 }
1667
1668 static unsigned
1669 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1670 {
1671 switch (filter) {
1672 case VK_FILTER_NEAREST:
1673 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1674 V_008F38_SQ_TEX_XY_FILTER_POINT);
1675 case VK_FILTER_LINEAR:
1676 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1677 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1678 case VK_FILTER_CUBIC_IMG:
1679 default:
1680 fprintf(stderr, "illegal texture filter");
1681 return 0;
1682 }
1683 }
1684
1685 static unsigned
1686 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1687 {
1688 switch (mode) {
1689 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1690 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1691 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1692 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1693 default:
1694 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1695 }
1696 }
1697
1698 static unsigned
1699 radv_tex_bordercolor(VkBorderColor bcolor)
1700 {
1701 switch (bcolor) {
1702 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1703 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1704 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1705 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1706 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1707 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1708 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1709 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1710 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1711 default:
1712 break;
1713 }
1714 return 0;
1715 }
1716
1717 static void
1718 radv_init_sampler(struct radv_device *device,
1719 struct radv_sampler *sampler,
1720 const VkSamplerCreateInfo *pCreateInfo)
1721 {
1722 uint32_t max_aniso = 0;
1723 uint32_t max_aniso_ratio = 0;//TODO
1724 bool is_vi;
1725 is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1726
1727 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1728 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1729 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1730 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1731 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1732 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1733 S_008F30_DISABLE_CUBE_WRAP(0) |
1734 S_008F30_COMPAT_MODE(is_vi));
1735 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1736 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)));
1737 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1738 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1739 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1740 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1741 S_008F38_MIP_POINT_PRECLAMP(1) |
1742 S_008F38_DISABLE_LSB_CEIL(1) |
1743 S_008F38_FILTER_PREC_FIX(1) |
1744 S_008F38_ANISO_OVERRIDE(is_vi));
1745 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1746 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1747 }
1748
1749 VkResult radv_CreateSampler(
1750 VkDevice _device,
1751 const VkSamplerCreateInfo* pCreateInfo,
1752 const VkAllocationCallbacks* pAllocator,
1753 VkSampler* pSampler)
1754 {
1755 RADV_FROM_HANDLE(radv_device, device, _device);
1756 struct radv_sampler *sampler;
1757
1758 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
1759
1760 sampler = radv_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
1761 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1762 if (!sampler)
1763 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1764
1765 radv_init_sampler(device, sampler, pCreateInfo);
1766 *pSampler = radv_sampler_to_handle(sampler);
1767
1768 return VK_SUCCESS;
1769 }
1770
1771 void radv_DestroySampler(
1772 VkDevice _device,
1773 VkSampler _sampler,
1774 const VkAllocationCallbacks* pAllocator)
1775 {
1776 RADV_FROM_HANDLE(radv_device, device, _device);
1777 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
1778
1779 if (!sampler)
1780 return;
1781 radv_free2(&device->alloc, pAllocator, sampler);
1782 }