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radv: fix multisample image copies
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 if (HAVE_LLVM > 0) {
112 snprintf(llvm_string, sizeof(llvm_string),
113 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
114 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
115 }
116
117 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
118 }
119
120 static void
121 radv_physical_device_init_mem_types(struct radv_physical_device *device)
122 {
123 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
124 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
125 device->rad_info.vram_vis_size);
126
127 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
128 device->memory_properties.memoryHeapCount = 0;
129 if (device->rad_info.vram_size - visible_vram_size > 0) {
130 vram_index = device->memory_properties.memoryHeapCount++;
131 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
132 .size = device->rad_info.vram_size - visible_vram_size,
133 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
134 };
135 }
136 if (visible_vram_size) {
137 visible_vram_index = device->memory_properties.memoryHeapCount++;
138 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
139 .size = visible_vram_size,
140 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
141 };
142 }
143 if (device->rad_info.gart_size > 0) {
144 gart_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
146 .size = device->rad_info.gart_size,
147 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150
151 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
152 unsigned type_count = 0;
153 if (vram_index >= 0) {
154 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
155 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
156 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
157 .heapIndex = vram_index,
158 };
159 }
160 if (gart_index >= 0) {
161 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
162 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
163 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
164 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
165 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
166 .heapIndex = gart_index,
167 };
168 }
169 if (visible_vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
173 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
174 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
175 .heapIndex = visible_vram_index,
176 };
177 }
178 if (gart_index >= 0) {
179 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
180 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
181 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
182 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
183 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
184 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
185 .heapIndex = gart_index,
186 };
187 }
188 device->memory_properties.memoryTypeCount = type_count;
189 }
190
191 static void
192 radv_handle_env_var_force_family(struct radv_physical_device *device)
193 {
194 const char *family = getenv("RADV_FORCE_FAMILY");
195 unsigned i;
196
197 if (!family)
198 return;
199
200 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
201 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
202 /* Override family and chip_class. */
203 device->rad_info.family = i;
204
205 if (i >= CHIP_VEGA10)
206 device->rad_info.chip_class = GFX9;
207 else if (i >= CHIP_TONGA)
208 device->rad_info.chip_class = VI;
209 else if (i >= CHIP_BONAIRE)
210 device->rad_info.chip_class = CIK;
211 else
212 device->rad_info.chip_class = SI;
213
214 return;
215 }
216 }
217
218 fprintf(stderr, "radv: Unknown family: %s\n", family);
219 exit(1);
220 }
221
222 static VkResult
223 radv_physical_device_init(struct radv_physical_device *device,
224 struct radv_instance *instance,
225 drmDevicePtr drm_device)
226 {
227 const char *path = drm_device->nodes[DRM_NODE_RENDER];
228 VkResult result;
229 drmVersionPtr version;
230 int fd;
231
232 fd = open(path, O_RDWR | O_CLOEXEC);
233 if (fd < 0)
234 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
235
236 version = drmGetVersion(fd);
237 if (!version) {
238 close(fd);
239 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
240 "failed to get version %s: %m", path);
241 }
242
243 if (strcmp(version->name, "amdgpu")) {
244 drmFreeVersion(version);
245 close(fd);
246 return VK_ERROR_INCOMPATIBLE_DRIVER;
247 }
248 drmFreeVersion(version);
249
250 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
251 device->instance = instance;
252 assert(strlen(path) < ARRAY_SIZE(device->path));
253 strncpy(device->path, path, ARRAY_SIZE(device->path));
254
255 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
256 instance->perftest_flags);
257 if (!device->ws) {
258 result = VK_ERROR_INCOMPATIBLE_DRIVER;
259 goto fail;
260 }
261
262 device->local_fd = fd;
263 device->ws->query_info(device->ws, &device->rad_info);
264
265 radv_handle_env_var_force_family(device);
266
267 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
268
269 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
270 device->ws->destroy(device->ws);
271 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
272 "cannot generate UUID");
273 goto fail;
274 }
275
276 /* These flags affect shader compilation. */
277 uint64_t shader_env_flags =
278 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
279 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
280
281 /* The gpu id is already embeded in the uuid so we just pass "radv"
282 * when creating the cache.
283 */
284 char buf[VK_UUID_SIZE * 2 + 1];
285 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
286 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
287
288 if (device->rad_info.chip_class < VI ||
289 device->rad_info.chip_class > GFX9)
290 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
291
292 radv_get_driver_uuid(&device->device_uuid);
293 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
294
295 if (device->rad_info.family == CHIP_STONEY ||
296 device->rad_info.chip_class >= GFX9) {
297 device->has_rbplus = true;
298 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
299 device->rad_info.family == CHIP_VEGA12 ||
300 device->rad_info.family == CHIP_RAVEN;
301 }
302
303 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
304 * on SI.
305 */
306 device->has_clear_state = device->rad_info.chip_class >= CIK;
307
308 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
309
310 /* Vega10/Raven need a special workaround for a hardware bug. */
311 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
312 device->rad_info.family == CHIP_RAVEN;
313
314 /* Out-of-order primitive rasterization. */
315 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
316 device->rad_info.max_se >= 2;
317 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
318 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
319
320 device->dcc_msaa_allowed = device->rad_info.chip_class == VI &&
321 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
322
323 radv_physical_device_init_mem_types(device);
324 radv_fill_device_extension_table(device, &device->supported_extensions);
325
326 result = radv_init_wsi(device);
327 if (result != VK_SUCCESS) {
328 device->ws->destroy(device->ws);
329 goto fail;
330 }
331
332 return VK_SUCCESS;
333
334 fail:
335 close(fd);
336 return result;
337 }
338
339 static void
340 radv_physical_device_finish(struct radv_physical_device *device)
341 {
342 radv_finish_wsi(device);
343 device->ws->destroy(device->ws);
344 disk_cache_destroy(device->disk_cache);
345 close(device->local_fd);
346 }
347
348 static void *
349 default_alloc_func(void *pUserData, size_t size, size_t align,
350 VkSystemAllocationScope allocationScope)
351 {
352 return malloc(size);
353 }
354
355 static void *
356 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
357 size_t align, VkSystemAllocationScope allocationScope)
358 {
359 return realloc(pOriginal, size);
360 }
361
362 static void
363 default_free_func(void *pUserData, void *pMemory)
364 {
365 free(pMemory);
366 }
367
368 static const VkAllocationCallbacks default_alloc = {
369 .pUserData = NULL,
370 .pfnAllocation = default_alloc_func,
371 .pfnReallocation = default_realloc_func,
372 .pfnFree = default_free_func,
373 };
374
375 static const struct debug_control radv_debug_options[] = {
376 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
377 {"nodcc", RADV_DEBUG_NO_DCC},
378 {"shaders", RADV_DEBUG_DUMP_SHADERS},
379 {"nocache", RADV_DEBUG_NO_CACHE},
380 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
381 {"nohiz", RADV_DEBUG_NO_HIZ},
382 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
383 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
384 {"allbos", RADV_DEBUG_ALL_BOS},
385 {"noibs", RADV_DEBUG_NO_IBS},
386 {"spirv", RADV_DEBUG_DUMP_SPIRV},
387 {"vmfaults", RADV_DEBUG_VM_FAULTS},
388 {"zerovram", RADV_DEBUG_ZERO_VRAM},
389 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
390 {"nosisched", RADV_DEBUG_NO_SISCHED},
391 {"preoptir", RADV_DEBUG_PREOPTIR},
392 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
393 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
394 {NULL, 0}
395 };
396
397 const char *
398 radv_get_debug_option_name(int id)
399 {
400 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
401 return radv_debug_options[id].string;
402 }
403
404 static const struct debug_control radv_perftest_options[] = {
405 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
406 {"sisched", RADV_PERFTEST_SISCHED},
407 {"localbos", RADV_PERFTEST_LOCAL_BOS},
408 {"binning", RADV_PERFTEST_BINNING},
409 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
410 {NULL, 0}
411 };
412
413 const char *
414 radv_get_perftest_option_name(int id)
415 {
416 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
417 return radv_perftest_options[id].string;
418 }
419
420 static void
421 radv_handle_per_app_options(struct radv_instance *instance,
422 const VkApplicationInfo *info)
423 {
424 const char *name = info ? info->pApplicationName : NULL;
425
426 if (!name)
427 return;
428
429 if (!strcmp(name, "Talos - Linux - 32bit") ||
430 !strcmp(name, "Talos - Linux - 64bit")) {
431 /* Force enable LLVM sisched for Talos because it looks safe
432 * and it gives few more FPS.
433 */
434 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
435 }
436 }
437
438 static int radv_get_instance_extension_index(const char *name)
439 {
440 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
441 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
442 return i;
443 }
444 return -1;
445 }
446
447
448 VkResult radv_CreateInstance(
449 const VkInstanceCreateInfo* pCreateInfo,
450 const VkAllocationCallbacks* pAllocator,
451 VkInstance* pInstance)
452 {
453 struct radv_instance *instance;
454 VkResult result;
455
456 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
457
458 uint32_t client_version;
459 if (pCreateInfo->pApplicationInfo &&
460 pCreateInfo->pApplicationInfo->apiVersion != 0) {
461 client_version = pCreateInfo->pApplicationInfo->apiVersion;
462 } else {
463 client_version = VK_MAKE_VERSION(1, 0, 0);
464 }
465
466 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
467 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
468 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
469 "Client requested version %d.%d.%d",
470 VK_VERSION_MAJOR(client_version),
471 VK_VERSION_MINOR(client_version),
472 VK_VERSION_PATCH(client_version));
473 }
474
475 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
476 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
477 if (!instance)
478 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
479
480 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
481
482 if (pAllocator)
483 instance->alloc = *pAllocator;
484 else
485 instance->alloc = default_alloc;
486
487 instance->apiVersion = client_version;
488 instance->physicalDeviceCount = -1;
489
490 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
491 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
492 int index = radv_get_instance_extension_index(ext_name);
493
494 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
495 vk_free2(&default_alloc, pAllocator, instance);
496 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
497 }
498
499 instance->enabled_extensions.extensions[index] = true;
500 }
501
502 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
503 if (result != VK_SUCCESS) {
504 vk_free2(&default_alloc, pAllocator, instance);
505 return vk_error(result);
506 }
507
508 _mesa_locale_init();
509
510 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
511
512 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
513 radv_debug_options);
514
515 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
516 radv_perftest_options);
517
518 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
519
520 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
521 /* Disable sisched when the user requests it, this is mostly
522 * useful when the driver force-enable sisched for the given
523 * application.
524 */
525 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
526 }
527
528 *pInstance = radv_instance_to_handle(instance);
529
530 return VK_SUCCESS;
531 }
532
533 void radv_DestroyInstance(
534 VkInstance _instance,
535 const VkAllocationCallbacks* pAllocator)
536 {
537 RADV_FROM_HANDLE(radv_instance, instance, _instance);
538
539 if (!instance)
540 return;
541
542 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
543 radv_physical_device_finish(instance->physicalDevices + i);
544 }
545
546 VG(VALGRIND_DESTROY_MEMPOOL(instance));
547
548 _mesa_locale_fini();
549
550 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
551
552 vk_free(&instance->alloc, instance);
553 }
554
555 static VkResult
556 radv_enumerate_devices(struct radv_instance *instance)
557 {
558 /* TODO: Check for more devices ? */
559 drmDevicePtr devices[8];
560 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
561 int max_devices;
562
563 instance->physicalDeviceCount = 0;
564
565 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
566 if (max_devices < 1)
567 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
568
569 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
570 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
571 devices[i]->bustype == DRM_BUS_PCI &&
572 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
573
574 result = radv_physical_device_init(instance->physicalDevices +
575 instance->physicalDeviceCount,
576 instance,
577 devices[i]);
578 if (result == VK_SUCCESS)
579 ++instance->physicalDeviceCount;
580 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
581 break;
582 }
583 }
584 drmFreeDevices(devices, max_devices);
585
586 return result;
587 }
588
589 VkResult radv_EnumeratePhysicalDevices(
590 VkInstance _instance,
591 uint32_t* pPhysicalDeviceCount,
592 VkPhysicalDevice* pPhysicalDevices)
593 {
594 RADV_FROM_HANDLE(radv_instance, instance, _instance);
595 VkResult result;
596
597 if (instance->physicalDeviceCount < 0) {
598 result = radv_enumerate_devices(instance);
599 if (result != VK_SUCCESS &&
600 result != VK_ERROR_INCOMPATIBLE_DRIVER)
601 return result;
602 }
603
604 if (!pPhysicalDevices) {
605 *pPhysicalDeviceCount = instance->physicalDeviceCount;
606 } else {
607 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
608 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
609 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
610 }
611
612 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
613 : VK_SUCCESS;
614 }
615
616 VkResult radv_EnumeratePhysicalDeviceGroups(
617 VkInstance _instance,
618 uint32_t* pPhysicalDeviceGroupCount,
619 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
620 {
621 RADV_FROM_HANDLE(radv_instance, instance, _instance);
622 VkResult result;
623
624 if (instance->physicalDeviceCount < 0) {
625 result = radv_enumerate_devices(instance);
626 if (result != VK_SUCCESS &&
627 result != VK_ERROR_INCOMPATIBLE_DRIVER)
628 return result;
629 }
630
631 if (!pPhysicalDeviceGroupProperties) {
632 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
633 } else {
634 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
635 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
636 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
637 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
638 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
639 }
640 }
641 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
642 : VK_SUCCESS;
643 }
644
645 void radv_GetPhysicalDeviceFeatures(
646 VkPhysicalDevice physicalDevice,
647 VkPhysicalDeviceFeatures* pFeatures)
648 {
649 memset(pFeatures, 0, sizeof(*pFeatures));
650
651 *pFeatures = (VkPhysicalDeviceFeatures) {
652 .robustBufferAccess = true,
653 .fullDrawIndexUint32 = true,
654 .imageCubeArray = true,
655 .independentBlend = true,
656 .geometryShader = true,
657 .tessellationShader = true,
658 .sampleRateShading = true,
659 .dualSrcBlend = true,
660 .logicOp = true,
661 .multiDrawIndirect = true,
662 .drawIndirectFirstInstance = true,
663 .depthClamp = true,
664 .depthBiasClamp = true,
665 .fillModeNonSolid = true,
666 .depthBounds = true,
667 .wideLines = true,
668 .largePoints = true,
669 .alphaToOne = true,
670 .multiViewport = true,
671 .samplerAnisotropy = true,
672 .textureCompressionETC2 = false,
673 .textureCompressionASTC_LDR = false,
674 .textureCompressionBC = true,
675 .occlusionQueryPrecise = true,
676 .pipelineStatisticsQuery = true,
677 .vertexPipelineStoresAndAtomics = true,
678 .fragmentStoresAndAtomics = true,
679 .shaderTessellationAndGeometryPointSize = true,
680 .shaderImageGatherExtended = true,
681 .shaderStorageImageExtendedFormats = true,
682 .shaderStorageImageMultisample = false,
683 .shaderUniformBufferArrayDynamicIndexing = true,
684 .shaderSampledImageArrayDynamicIndexing = true,
685 .shaderStorageBufferArrayDynamicIndexing = true,
686 .shaderStorageImageArrayDynamicIndexing = true,
687 .shaderStorageImageReadWithoutFormat = true,
688 .shaderStorageImageWriteWithoutFormat = true,
689 .shaderClipDistance = true,
690 .shaderCullDistance = true,
691 .shaderFloat64 = true,
692 .shaderInt64 = true,
693 .shaderInt16 = false,
694 .sparseBinding = true,
695 .variableMultisampleRate = true,
696 .inheritedQueries = true,
697 };
698 }
699
700 void radv_GetPhysicalDeviceFeatures2(
701 VkPhysicalDevice physicalDevice,
702 VkPhysicalDeviceFeatures2KHR *pFeatures)
703 {
704 vk_foreach_struct(ext, pFeatures->pNext) {
705 switch (ext->sType) {
706 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
707 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
708 features->variablePointersStorageBuffer = true;
709 features->variablePointers = false;
710 break;
711 }
712 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
713 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
714 features->multiview = true;
715 features->multiviewGeometryShader = true;
716 features->multiviewTessellationShader = true;
717 break;
718 }
719 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
720 VkPhysicalDeviceShaderDrawParameterFeatures *features =
721 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
722 features->shaderDrawParameters = true;
723 break;
724 }
725 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
726 VkPhysicalDeviceProtectedMemoryFeatures *features =
727 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
728 features->protectedMemory = false;
729 break;
730 }
731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
732 VkPhysicalDevice16BitStorageFeatures *features =
733 (VkPhysicalDevice16BitStorageFeatures*)ext;
734 features->storageBuffer16BitAccess = false;
735 features->uniformAndStorageBuffer16BitAccess = false;
736 features->storagePushConstant16 = false;
737 features->storageInputOutput16 = false;
738 break;
739 }
740 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
741 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
742 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
743 features->samplerYcbcrConversion = false;
744 break;
745 }
746 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
747 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
748 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)features;
749 features->shaderInputAttachmentArrayDynamicIndexing = true;
750 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
751 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
752 features->shaderUniformBufferArrayNonUniformIndexing = false;
753 features->shaderSampledImageArrayNonUniformIndexing = false;
754 features->shaderStorageBufferArrayNonUniformIndexing = false;
755 features->shaderStorageImageArrayNonUniformIndexing = false;
756 features->shaderInputAttachmentArrayNonUniformIndexing = false;
757 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
758 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
759 features->descriptorBindingUniformBufferUpdateAfterBind = true;
760 features->descriptorBindingSampledImageUpdateAfterBind = true;
761 features->descriptorBindingStorageImageUpdateAfterBind = true;
762 features->descriptorBindingStorageBufferUpdateAfterBind = true;
763 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
764 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
765 features->descriptorBindingUpdateUnusedWhilePending = true;
766 features->descriptorBindingPartiallyBound = true;
767 features->descriptorBindingVariableDescriptorCount = true;
768 features->runtimeDescriptorArray = true;
769 break;
770 }
771 default:
772 break;
773 }
774 }
775 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
776 }
777
778 void radv_GetPhysicalDeviceProperties(
779 VkPhysicalDevice physicalDevice,
780 VkPhysicalDeviceProperties* pProperties)
781 {
782 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
783 VkSampleCountFlags sample_counts = 0xf;
784
785 /* make sure that the entire descriptor set is addressable with a signed
786 * 32-bit int. So the sum of all limits scaled by descriptor size has to
787 * be at most 2 GiB. the combined image & samples object count as one of
788 * both. This limit is for the pipeline layout, not for the set layout, but
789 * there is no set limit, so we just set a pipeline limit. I don't think
790 * any app is going to hit this soon. */
791 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
792 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
793 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
794 32 /* sampler, largest when combined with image */ +
795 64 /* sampled image */ +
796 64 /* storage image */);
797
798 VkPhysicalDeviceLimits limits = {
799 .maxImageDimension1D = (1 << 14),
800 .maxImageDimension2D = (1 << 14),
801 .maxImageDimension3D = (1 << 11),
802 .maxImageDimensionCube = (1 << 14),
803 .maxImageArrayLayers = (1 << 11),
804 .maxTexelBufferElements = 128 * 1024 * 1024,
805 .maxUniformBufferRange = UINT32_MAX,
806 .maxStorageBufferRange = UINT32_MAX,
807 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
808 .maxMemoryAllocationCount = UINT32_MAX,
809 .maxSamplerAllocationCount = 64 * 1024,
810 .bufferImageGranularity = 64, /* A cache line */
811 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
812 .maxBoundDescriptorSets = MAX_SETS,
813 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
814 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
815 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
816 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
817 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
818 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
819 .maxPerStageResources = max_descriptor_set_size,
820 .maxDescriptorSetSamplers = max_descriptor_set_size,
821 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
822 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
823 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
824 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
825 .maxDescriptorSetSampledImages = max_descriptor_set_size,
826 .maxDescriptorSetStorageImages = max_descriptor_set_size,
827 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
828 .maxVertexInputAttributes = 32,
829 .maxVertexInputBindings = 32,
830 .maxVertexInputAttributeOffset = 2047,
831 .maxVertexInputBindingStride = 2048,
832 .maxVertexOutputComponents = 128,
833 .maxTessellationGenerationLevel = 64,
834 .maxTessellationPatchSize = 32,
835 .maxTessellationControlPerVertexInputComponents = 128,
836 .maxTessellationControlPerVertexOutputComponents = 128,
837 .maxTessellationControlPerPatchOutputComponents = 120,
838 .maxTessellationControlTotalOutputComponents = 4096,
839 .maxTessellationEvaluationInputComponents = 128,
840 .maxTessellationEvaluationOutputComponents = 128,
841 .maxGeometryShaderInvocations = 127,
842 .maxGeometryInputComponents = 64,
843 .maxGeometryOutputComponents = 128,
844 .maxGeometryOutputVertices = 256,
845 .maxGeometryTotalOutputComponents = 1024,
846 .maxFragmentInputComponents = 128,
847 .maxFragmentOutputAttachments = 8,
848 .maxFragmentDualSrcAttachments = 1,
849 .maxFragmentCombinedOutputResources = 8,
850 .maxComputeSharedMemorySize = 32768,
851 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
852 .maxComputeWorkGroupInvocations = 2048,
853 .maxComputeWorkGroupSize = {
854 2048,
855 2048,
856 2048
857 },
858 .subPixelPrecisionBits = 4 /* FIXME */,
859 .subTexelPrecisionBits = 4 /* FIXME */,
860 .mipmapPrecisionBits = 4 /* FIXME */,
861 .maxDrawIndexedIndexValue = UINT32_MAX,
862 .maxDrawIndirectCount = UINT32_MAX,
863 .maxSamplerLodBias = 16,
864 .maxSamplerAnisotropy = 16,
865 .maxViewports = MAX_VIEWPORTS,
866 .maxViewportDimensions = { (1 << 14), (1 << 14) },
867 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
868 .viewportSubPixelBits = 8,
869 .minMemoryMapAlignment = 4096, /* A page */
870 .minTexelBufferOffsetAlignment = 1,
871 .minUniformBufferOffsetAlignment = 4,
872 .minStorageBufferOffsetAlignment = 4,
873 .minTexelOffset = -32,
874 .maxTexelOffset = 31,
875 .minTexelGatherOffset = -32,
876 .maxTexelGatherOffset = 31,
877 .minInterpolationOffset = -2,
878 .maxInterpolationOffset = 2,
879 .subPixelInterpolationOffsetBits = 8,
880 .maxFramebufferWidth = (1 << 14),
881 .maxFramebufferHeight = (1 << 14),
882 .maxFramebufferLayers = (1 << 10),
883 .framebufferColorSampleCounts = sample_counts,
884 .framebufferDepthSampleCounts = sample_counts,
885 .framebufferStencilSampleCounts = sample_counts,
886 .framebufferNoAttachmentsSampleCounts = sample_counts,
887 .maxColorAttachments = MAX_RTS,
888 .sampledImageColorSampleCounts = sample_counts,
889 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
890 .sampledImageDepthSampleCounts = sample_counts,
891 .sampledImageStencilSampleCounts = sample_counts,
892 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
893 .maxSampleMaskWords = 1,
894 .timestampComputeAndGraphics = true,
895 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
896 .maxClipDistances = 8,
897 .maxCullDistances = 8,
898 .maxCombinedClipAndCullDistances = 8,
899 .discreteQueuePriorities = 1,
900 .pointSizeRange = { 0.125, 255.875 },
901 .lineWidthRange = { 0.0, 7.9921875 },
902 .pointSizeGranularity = (1.0 / 8.0),
903 .lineWidthGranularity = (1.0 / 128.0),
904 .strictLines = false, /* FINISHME */
905 .standardSampleLocations = true,
906 .optimalBufferCopyOffsetAlignment = 128,
907 .optimalBufferCopyRowPitchAlignment = 128,
908 .nonCoherentAtomSize = 64,
909 };
910
911 *pProperties = (VkPhysicalDeviceProperties) {
912 .apiVersion = radv_physical_device_api_version(pdevice),
913 .driverVersion = vk_get_driver_version(),
914 .vendorID = ATI_VENDOR_ID,
915 .deviceID = pdevice->rad_info.pci_id,
916 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
917 .limits = limits,
918 .sparseProperties = {0},
919 };
920
921 strcpy(pProperties->deviceName, pdevice->name);
922 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
923 }
924
925 void radv_GetPhysicalDeviceProperties2(
926 VkPhysicalDevice physicalDevice,
927 VkPhysicalDeviceProperties2KHR *pProperties)
928 {
929 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
930 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
931
932 vk_foreach_struct(ext, pProperties->pNext) {
933 switch (ext->sType) {
934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
935 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
936 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
937 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
938 break;
939 }
940 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
941 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
942 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
943 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
944 properties->deviceLUIDValid = false;
945 break;
946 }
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
948 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
949 properties->maxMultiviewViewCount = MAX_VIEWS;
950 properties->maxMultiviewInstanceIndex = INT_MAX;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
954 VkPhysicalDevicePointClippingPropertiesKHR *properties =
955 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
956 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
957 break;
958 }
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
960 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
961 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
962 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
963 break;
964 }
965 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
966 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
967 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
968 properties->minImportedHostPointerAlignment = 4096;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
972 VkPhysicalDeviceSubgroupProperties *properties =
973 (VkPhysicalDeviceSubgroupProperties*)ext;
974 properties->subgroupSize = 64;
975 properties->supportedStages = VK_SHADER_STAGE_ALL;
976 properties->supportedOperations =
977 VK_SUBGROUP_FEATURE_BASIC_BIT |
978 VK_SUBGROUP_FEATURE_BALLOT_BIT |
979 VK_SUBGROUP_FEATURE_QUAD_BIT |
980 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
981 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
982 VK_SUBGROUP_FEATURE_VOTE_BIT;
983 properties->quadOperationsInAllStages = true;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
987 VkPhysicalDeviceMaintenance3Properties *properties =
988 (VkPhysicalDeviceMaintenance3Properties*)ext;
989 /* Make sure everything is addressable by a signed 32-bit int, and
990 * our largest descriptors are 96 bytes. */
991 properties->maxPerSetDescriptors = (1ull << 31) / 96;
992 /* Our buffer size fields allow only this much */
993 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
994 break;
995 }
996 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
997 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
998 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
999 /* GFX6-8 only support single channel min/max filter. */
1000 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1001 properties->filterMinmaxSingleComponentFormats = true;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1005 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1006 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1007
1008 /* Shader engines. */
1009 properties->shaderEngineCount =
1010 pdevice->rad_info.max_se;
1011 properties->shaderArraysPerEngineCount =
1012 pdevice->rad_info.max_sh_per_se;
1013 properties->computeUnitsPerShaderArray =
1014 pdevice->rad_info.num_good_compute_units /
1015 (pdevice->rad_info.max_se *
1016 pdevice->rad_info.max_sh_per_se);
1017 properties->simdPerComputeUnit = 4;
1018 properties->wavefrontsPerSimd =
1019 pdevice->rad_info.family == CHIP_TONGA ||
1020 pdevice->rad_info.family == CHIP_ICELAND ||
1021 pdevice->rad_info.family == CHIP_POLARIS10 ||
1022 pdevice->rad_info.family == CHIP_POLARIS11 ||
1023 pdevice->rad_info.family == CHIP_POLARIS12 ||
1024 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1025 properties->wavefrontSize = 64;
1026
1027 /* SGPR. */
1028 properties->sgprsPerSimd =
1029 radv_get_num_physical_sgprs(pdevice);
1030 properties->minSgprAllocation =
1031 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1032 properties->maxSgprAllocation =
1033 pdevice->rad_info.family == CHIP_TONGA ||
1034 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1035 properties->sgprAllocationGranularity =
1036 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1037
1038 /* VGPR. */
1039 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1040 properties->minVgprAllocation = 4;
1041 properties->maxVgprAllocation = 256;
1042 properties->vgprAllocationGranularity = 4;
1043 break;
1044 }
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1046 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1047 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1048 properties->maxVertexAttribDivisor = UINT32_MAX;
1049 break;
1050 }
1051 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1052 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1053 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1054 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1055 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1056 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1057 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1058 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1059 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1060 properties->robustBufferAccessUpdateAfterBind = false;
1061 properties->quadDivergentImplicitLod = false;
1062
1063 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1064 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1065 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1066 32 /* sampler, largest when combined with image */ +
1067 64 /* sampled image */ +
1068 64 /* storage image */);
1069 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1070 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1071 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1072 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1073 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1074 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1075 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1076 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1077 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1078 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1079 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1080 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1081 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1082 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1083 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1084 break;
1085 }
1086 default:
1087 break;
1088 }
1089 }
1090 }
1091
1092 static void radv_get_physical_device_queue_family_properties(
1093 struct radv_physical_device* pdevice,
1094 uint32_t* pCount,
1095 VkQueueFamilyProperties** pQueueFamilyProperties)
1096 {
1097 int num_queue_families = 1;
1098 int idx;
1099 if (pdevice->rad_info.num_compute_rings > 0 &&
1100 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1101 num_queue_families++;
1102
1103 if (pQueueFamilyProperties == NULL) {
1104 *pCount = num_queue_families;
1105 return;
1106 }
1107
1108 if (!*pCount)
1109 return;
1110
1111 idx = 0;
1112 if (*pCount >= 1) {
1113 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1114 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1115 VK_QUEUE_COMPUTE_BIT |
1116 VK_QUEUE_TRANSFER_BIT |
1117 VK_QUEUE_SPARSE_BINDING_BIT,
1118 .queueCount = 1,
1119 .timestampValidBits = 64,
1120 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1121 };
1122 idx++;
1123 }
1124
1125 if (pdevice->rad_info.num_compute_rings > 0 &&
1126 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1127 if (*pCount > idx) {
1128 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1129 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1130 VK_QUEUE_TRANSFER_BIT |
1131 VK_QUEUE_SPARSE_BINDING_BIT,
1132 .queueCount = pdevice->rad_info.num_compute_rings,
1133 .timestampValidBits = 64,
1134 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1135 };
1136 idx++;
1137 }
1138 }
1139 *pCount = idx;
1140 }
1141
1142 void radv_GetPhysicalDeviceQueueFamilyProperties(
1143 VkPhysicalDevice physicalDevice,
1144 uint32_t* pCount,
1145 VkQueueFamilyProperties* pQueueFamilyProperties)
1146 {
1147 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1148 if (!pQueueFamilyProperties) {
1149 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1150 return;
1151 }
1152 VkQueueFamilyProperties *properties[] = {
1153 pQueueFamilyProperties + 0,
1154 pQueueFamilyProperties + 1,
1155 pQueueFamilyProperties + 2,
1156 };
1157 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1158 assert(*pCount <= 3);
1159 }
1160
1161 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1162 VkPhysicalDevice physicalDevice,
1163 uint32_t* pCount,
1164 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1165 {
1166 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1167 if (!pQueueFamilyProperties) {
1168 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1169 return;
1170 }
1171 VkQueueFamilyProperties *properties[] = {
1172 &pQueueFamilyProperties[0].queueFamilyProperties,
1173 &pQueueFamilyProperties[1].queueFamilyProperties,
1174 &pQueueFamilyProperties[2].queueFamilyProperties,
1175 };
1176 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1177 assert(*pCount <= 3);
1178 }
1179
1180 void radv_GetPhysicalDeviceMemoryProperties(
1181 VkPhysicalDevice physicalDevice,
1182 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1183 {
1184 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1185
1186 *pMemoryProperties = physical_device->memory_properties;
1187 }
1188
1189 void radv_GetPhysicalDeviceMemoryProperties2(
1190 VkPhysicalDevice physicalDevice,
1191 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1192 {
1193 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1194 &pMemoryProperties->memoryProperties);
1195 }
1196
1197 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1198 VkDevice _device,
1199 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1200 const void *pHostPointer,
1201 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1202 {
1203 RADV_FROM_HANDLE(radv_device, device, _device);
1204
1205 switch (handleType)
1206 {
1207 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1208 const struct radv_physical_device *physical_device = device->physical_device;
1209 uint32_t memoryTypeBits = 0;
1210 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1211 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1212 memoryTypeBits = (1 << i);
1213 break;
1214 }
1215 }
1216 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1217 return VK_SUCCESS;
1218 }
1219 default:
1220 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1221 }
1222 }
1223
1224 static enum radeon_ctx_priority
1225 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1226 {
1227 /* Default to MEDIUM when a specific global priority isn't requested */
1228 if (!pObj)
1229 return RADEON_CTX_PRIORITY_MEDIUM;
1230
1231 switch(pObj->globalPriority) {
1232 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1233 return RADEON_CTX_PRIORITY_REALTIME;
1234 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1235 return RADEON_CTX_PRIORITY_HIGH;
1236 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1237 return RADEON_CTX_PRIORITY_MEDIUM;
1238 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1239 return RADEON_CTX_PRIORITY_LOW;
1240 default:
1241 unreachable("Illegal global priority value");
1242 return RADEON_CTX_PRIORITY_INVALID;
1243 }
1244 }
1245
1246 static int
1247 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1248 uint32_t queue_family_index, int idx,
1249 VkDeviceQueueCreateFlags flags,
1250 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1251 {
1252 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1253 queue->device = device;
1254 queue->queue_family_index = queue_family_index;
1255 queue->queue_idx = idx;
1256 queue->priority = radv_get_queue_global_priority(global_priority);
1257 queue->flags = flags;
1258
1259 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1260 if (!queue->hw_ctx)
1261 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1262
1263 return VK_SUCCESS;
1264 }
1265
1266 static void
1267 radv_queue_finish(struct radv_queue *queue)
1268 {
1269 if (queue->hw_ctx)
1270 queue->device->ws->ctx_destroy(queue->hw_ctx);
1271
1272 if (queue->initial_full_flush_preamble_cs)
1273 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1274 if (queue->initial_preamble_cs)
1275 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1276 if (queue->continue_preamble_cs)
1277 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1278 if (queue->descriptor_bo)
1279 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1280 if (queue->scratch_bo)
1281 queue->device->ws->buffer_destroy(queue->scratch_bo);
1282 if (queue->esgs_ring_bo)
1283 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1284 if (queue->gsvs_ring_bo)
1285 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1286 if (queue->tess_rings_bo)
1287 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1288 if (queue->compute_scratch_bo)
1289 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1290 }
1291
1292 static void
1293 radv_bo_list_init(struct radv_bo_list *bo_list)
1294 {
1295 pthread_mutex_init(&bo_list->mutex, NULL);
1296 bo_list->list.count = bo_list->capacity = 0;
1297 bo_list->list.bos = NULL;
1298 }
1299
1300 static void
1301 radv_bo_list_finish(struct radv_bo_list *bo_list)
1302 {
1303 free(bo_list->list.bos);
1304 pthread_mutex_destroy(&bo_list->mutex);
1305 }
1306
1307 static VkResult radv_bo_list_add(struct radv_device *device,
1308 struct radeon_winsys_bo *bo)
1309 {
1310 struct radv_bo_list *bo_list = &device->bo_list;
1311
1312 if (unlikely(!device->use_global_bo_list))
1313 return VK_SUCCESS;
1314
1315 pthread_mutex_lock(&bo_list->mutex);
1316 if (bo_list->list.count == bo_list->capacity) {
1317 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1318 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1319
1320 if (!data) {
1321 pthread_mutex_unlock(&bo_list->mutex);
1322 return VK_ERROR_OUT_OF_HOST_MEMORY;
1323 }
1324
1325 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1326 bo_list->capacity = capacity;
1327 }
1328
1329 bo_list->list.bos[bo_list->list.count++] = bo;
1330 pthread_mutex_unlock(&bo_list->mutex);
1331 return VK_SUCCESS;
1332 }
1333
1334 static void radv_bo_list_remove(struct radv_device *device,
1335 struct radeon_winsys_bo *bo)
1336 {
1337 struct radv_bo_list *bo_list = &device->bo_list;
1338
1339 if (unlikely(!device->use_global_bo_list))
1340 return;
1341
1342 pthread_mutex_lock(&bo_list->mutex);
1343 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1344 if (bo_list->list.bos[i] == bo) {
1345 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1346 --bo_list->list.count;
1347 break;
1348 }
1349 }
1350 pthread_mutex_unlock(&bo_list->mutex);
1351 }
1352
1353 static void
1354 radv_device_init_gs_info(struct radv_device *device)
1355 {
1356 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1357 device->physical_device->rad_info.family);
1358 }
1359
1360 static int radv_get_device_extension_index(const char *name)
1361 {
1362 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1363 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1364 return i;
1365 }
1366 return -1;
1367 }
1368
1369 VkResult radv_CreateDevice(
1370 VkPhysicalDevice physicalDevice,
1371 const VkDeviceCreateInfo* pCreateInfo,
1372 const VkAllocationCallbacks* pAllocator,
1373 VkDevice* pDevice)
1374 {
1375 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1376 VkResult result;
1377 struct radv_device *device;
1378
1379 bool keep_shader_info = false;
1380
1381 /* Check enabled features */
1382 if (pCreateInfo->pEnabledFeatures) {
1383 VkPhysicalDeviceFeatures supported_features;
1384 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1385 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1386 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1387 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1388 for (uint32_t i = 0; i < num_features; i++) {
1389 if (enabled_feature[i] && !supported_feature[i])
1390 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1391 }
1392 }
1393
1394 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1395 sizeof(*device), 8,
1396 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1397 if (!device)
1398 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1399
1400 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1401 device->instance = physical_device->instance;
1402 device->physical_device = physical_device;
1403
1404 device->ws = physical_device->ws;
1405 if (pAllocator)
1406 device->alloc = *pAllocator;
1407 else
1408 device->alloc = physical_device->instance->alloc;
1409
1410 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1411 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1412 int index = radv_get_device_extension_index(ext_name);
1413 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1414 vk_free(&device->alloc, device);
1415 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1416 }
1417
1418 device->enabled_extensions.extensions[index] = true;
1419 }
1420
1421 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1422
1423 /* With update after bind we can't attach bo's to the command buffer
1424 * from the descriptor set anymore, so we have to use a global BO list.
1425 */
1426 device->use_global_bo_list =
1427 device->enabled_extensions.EXT_descriptor_indexing;
1428
1429 mtx_init(&device->shader_slab_mutex, mtx_plain);
1430 list_inithead(&device->shader_slabs);
1431
1432 radv_bo_list_init(&device->bo_list);
1433
1434 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1435 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1436 uint32_t qfi = queue_create->queueFamilyIndex;
1437 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1438 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1439
1440 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1441
1442 device->queues[qfi] = vk_alloc(&device->alloc,
1443 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1444 if (!device->queues[qfi]) {
1445 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1446 goto fail;
1447 }
1448
1449 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1450
1451 device->queue_count[qfi] = queue_create->queueCount;
1452
1453 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1454 result = radv_queue_init(device, &device->queues[qfi][q],
1455 qfi, q, queue_create->flags,
1456 global_priority);
1457 if (result != VK_SUCCESS)
1458 goto fail;
1459 }
1460 }
1461
1462 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1463 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1464
1465 /* Disabled and not implemented for now. */
1466 device->dfsm_allowed = device->pbb_allowed && false;
1467
1468 #ifdef ANDROID
1469 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1470 #endif
1471
1472 device->llvm_supports_spill = true;
1473
1474 /* The maximum number of scratch waves. Scratch space isn't divided
1475 * evenly between CUs. The number is only a function of the number of CUs.
1476 * We can decrease the constant to decrease the scratch buffer size.
1477 *
1478 * sctx->scratch_waves must be >= the maximum posible size of
1479 * 1 threadgroup, so that the hw doesn't hang from being unable
1480 * to start any.
1481 *
1482 * The recommended value is 4 per CU at most. Higher numbers don't
1483 * bring much benefit, but they still occupy chip resources (think
1484 * async compute). I've seen ~2% performance difference between 4 and 32.
1485 */
1486 uint32_t max_threads_per_block = 2048;
1487 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1488 max_threads_per_block / 64);
1489
1490 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1491
1492 if (device->physical_device->rad_info.chip_class >= CIK) {
1493 /* If the KMD allows it (there is a KMD hw register for it),
1494 * allow launching waves out-of-order.
1495 */
1496 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1497 }
1498
1499 radv_device_init_gs_info(device);
1500
1501 device->tess_offchip_block_dw_size =
1502 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1503 device->has_distributed_tess =
1504 device->physical_device->rad_info.chip_class >= VI &&
1505 device->physical_device->rad_info.max_se >= 2;
1506
1507 if (getenv("RADV_TRACE_FILE")) {
1508 const char *filename = getenv("RADV_TRACE_FILE");
1509
1510 keep_shader_info = true;
1511
1512 if (!radv_init_trace(device))
1513 goto fail;
1514
1515 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1516 radv_dump_enabled_options(device, stderr);
1517 }
1518
1519 device->keep_shader_info = keep_shader_info;
1520
1521 result = radv_device_init_meta(device);
1522 if (result != VK_SUCCESS)
1523 goto fail;
1524
1525 radv_device_init_msaa(device);
1526
1527 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1528 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1529 switch (family) {
1530 case RADV_QUEUE_GENERAL:
1531 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1532 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1533 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1534 break;
1535 case RADV_QUEUE_COMPUTE:
1536 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1537 radeon_emit(device->empty_cs[family], 0);
1538 break;
1539 }
1540 device->ws->cs_finalize(device->empty_cs[family]);
1541 }
1542
1543 if (device->physical_device->rad_info.chip_class >= CIK)
1544 cik_create_gfx_config(device);
1545
1546 VkPipelineCacheCreateInfo ci;
1547 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1548 ci.pNext = NULL;
1549 ci.flags = 0;
1550 ci.pInitialData = NULL;
1551 ci.initialDataSize = 0;
1552 VkPipelineCache pc;
1553 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1554 &ci, NULL, &pc);
1555 if (result != VK_SUCCESS)
1556 goto fail_meta;
1557
1558 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1559
1560 *pDevice = radv_device_to_handle(device);
1561 return VK_SUCCESS;
1562
1563 fail_meta:
1564 radv_device_finish_meta(device);
1565 fail:
1566 radv_bo_list_finish(&device->bo_list);
1567
1568 if (device->trace_bo)
1569 device->ws->buffer_destroy(device->trace_bo);
1570
1571 if (device->gfx_init)
1572 device->ws->buffer_destroy(device->gfx_init);
1573
1574 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1575 for (unsigned q = 0; q < device->queue_count[i]; q++)
1576 radv_queue_finish(&device->queues[i][q]);
1577 if (device->queue_count[i])
1578 vk_free(&device->alloc, device->queues[i]);
1579 }
1580
1581 vk_free(&device->alloc, device);
1582 return result;
1583 }
1584
1585 void radv_DestroyDevice(
1586 VkDevice _device,
1587 const VkAllocationCallbacks* pAllocator)
1588 {
1589 RADV_FROM_HANDLE(radv_device, device, _device);
1590
1591 if (!device)
1592 return;
1593
1594 if (device->trace_bo)
1595 device->ws->buffer_destroy(device->trace_bo);
1596
1597 if (device->gfx_init)
1598 device->ws->buffer_destroy(device->gfx_init);
1599
1600 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1601 for (unsigned q = 0; q < device->queue_count[i]; q++)
1602 radv_queue_finish(&device->queues[i][q]);
1603 if (device->queue_count[i])
1604 vk_free(&device->alloc, device->queues[i]);
1605 if (device->empty_cs[i])
1606 device->ws->cs_destroy(device->empty_cs[i]);
1607 }
1608 radv_device_finish_meta(device);
1609
1610 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1611 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1612
1613 radv_destroy_shader_slabs(device);
1614
1615 radv_bo_list_finish(&device->bo_list);
1616 vk_free(&device->alloc, device);
1617 }
1618
1619 VkResult radv_EnumerateInstanceLayerProperties(
1620 uint32_t* pPropertyCount,
1621 VkLayerProperties* pProperties)
1622 {
1623 if (pProperties == NULL) {
1624 *pPropertyCount = 0;
1625 return VK_SUCCESS;
1626 }
1627
1628 /* None supported at this time */
1629 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1630 }
1631
1632 VkResult radv_EnumerateDeviceLayerProperties(
1633 VkPhysicalDevice physicalDevice,
1634 uint32_t* pPropertyCount,
1635 VkLayerProperties* pProperties)
1636 {
1637 if (pProperties == NULL) {
1638 *pPropertyCount = 0;
1639 return VK_SUCCESS;
1640 }
1641
1642 /* None supported at this time */
1643 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1644 }
1645
1646 void radv_GetDeviceQueue2(
1647 VkDevice _device,
1648 const VkDeviceQueueInfo2* pQueueInfo,
1649 VkQueue* pQueue)
1650 {
1651 RADV_FROM_HANDLE(radv_device, device, _device);
1652 struct radv_queue *queue;
1653
1654 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1655 if (pQueueInfo->flags != queue->flags) {
1656 /* From the Vulkan 1.1.70 spec:
1657 *
1658 * "The queue returned by vkGetDeviceQueue2 must have the same
1659 * flags value from this structure as that used at device
1660 * creation time in a VkDeviceQueueCreateInfo instance. If no
1661 * matching flags were specified at device creation time then
1662 * pQueue will return VK_NULL_HANDLE."
1663 */
1664 *pQueue = VK_NULL_HANDLE;
1665 return;
1666 }
1667
1668 *pQueue = radv_queue_to_handle(queue);
1669 }
1670
1671 void radv_GetDeviceQueue(
1672 VkDevice _device,
1673 uint32_t queueFamilyIndex,
1674 uint32_t queueIndex,
1675 VkQueue* pQueue)
1676 {
1677 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1678 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1679 .queueFamilyIndex = queueFamilyIndex,
1680 .queueIndex = queueIndex
1681 };
1682
1683 radv_GetDeviceQueue2(_device, &info, pQueue);
1684 }
1685
1686 static void
1687 fill_geom_tess_rings(struct radv_queue *queue,
1688 uint32_t *map,
1689 bool add_sample_positions,
1690 uint32_t esgs_ring_size,
1691 struct radeon_winsys_bo *esgs_ring_bo,
1692 uint32_t gsvs_ring_size,
1693 struct radeon_winsys_bo *gsvs_ring_bo,
1694 uint32_t tess_factor_ring_size,
1695 uint32_t tess_offchip_ring_offset,
1696 uint32_t tess_offchip_ring_size,
1697 struct radeon_winsys_bo *tess_rings_bo)
1698 {
1699 uint64_t esgs_va = 0, gsvs_va = 0;
1700 uint64_t tess_va = 0, tess_offchip_va = 0;
1701 uint32_t *desc = &map[4];
1702
1703 if (esgs_ring_bo)
1704 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1705 if (gsvs_ring_bo)
1706 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1707 if (tess_rings_bo) {
1708 tess_va = radv_buffer_get_va(tess_rings_bo);
1709 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1710 }
1711
1712 /* stride 0, num records - size, add tid, swizzle, elsize4,
1713 index stride 64 */
1714 desc[0] = esgs_va;
1715 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1716 S_008F04_STRIDE(0) |
1717 S_008F04_SWIZZLE_ENABLE(true);
1718 desc[2] = esgs_ring_size;
1719 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1720 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1721 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1722 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1723 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1724 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1725 S_008F0C_ELEMENT_SIZE(1) |
1726 S_008F0C_INDEX_STRIDE(3) |
1727 S_008F0C_ADD_TID_ENABLE(true);
1728
1729 desc += 4;
1730 /* GS entry for ES->GS ring */
1731 /* stride 0, num records - size, elsize0,
1732 index stride 0 */
1733 desc[0] = esgs_va;
1734 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1735 S_008F04_STRIDE(0) |
1736 S_008F04_SWIZZLE_ENABLE(false);
1737 desc[2] = esgs_ring_size;
1738 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1739 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1740 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1741 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1742 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1743 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1744 S_008F0C_ELEMENT_SIZE(0) |
1745 S_008F0C_INDEX_STRIDE(0) |
1746 S_008F0C_ADD_TID_ENABLE(false);
1747
1748 desc += 4;
1749 /* VS entry for GS->VS ring */
1750 /* stride 0, num records - size, elsize0,
1751 index stride 0 */
1752 desc[0] = gsvs_va;
1753 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1754 S_008F04_STRIDE(0) |
1755 S_008F04_SWIZZLE_ENABLE(false);
1756 desc[2] = gsvs_ring_size;
1757 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1758 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1759 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1760 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1761 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1762 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1763 S_008F0C_ELEMENT_SIZE(0) |
1764 S_008F0C_INDEX_STRIDE(0) |
1765 S_008F0C_ADD_TID_ENABLE(false);
1766 desc += 4;
1767
1768 /* stride gsvs_itemsize, num records 64
1769 elsize 4, index stride 16 */
1770 /* shader will patch stride and desc[2] */
1771 desc[0] = gsvs_va;
1772 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1773 S_008F04_STRIDE(0) |
1774 S_008F04_SWIZZLE_ENABLE(true);
1775 desc[2] = 0;
1776 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1777 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1778 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1779 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1780 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1781 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1782 S_008F0C_ELEMENT_SIZE(1) |
1783 S_008F0C_INDEX_STRIDE(1) |
1784 S_008F0C_ADD_TID_ENABLE(true);
1785 desc += 4;
1786
1787 desc[0] = tess_va;
1788 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1789 S_008F04_STRIDE(0) |
1790 S_008F04_SWIZZLE_ENABLE(false);
1791 desc[2] = tess_factor_ring_size;
1792 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1793 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1794 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1795 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1796 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1797 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1798 S_008F0C_ELEMENT_SIZE(0) |
1799 S_008F0C_INDEX_STRIDE(0) |
1800 S_008F0C_ADD_TID_ENABLE(false);
1801 desc += 4;
1802
1803 desc[0] = tess_offchip_va;
1804 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1805 S_008F04_STRIDE(0) |
1806 S_008F04_SWIZZLE_ENABLE(false);
1807 desc[2] = tess_offchip_ring_size;
1808 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1809 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1810 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1811 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1812 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1813 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1814 S_008F0C_ELEMENT_SIZE(0) |
1815 S_008F0C_INDEX_STRIDE(0) |
1816 S_008F0C_ADD_TID_ENABLE(false);
1817 desc += 4;
1818
1819 /* add sample positions after all rings */
1820 memcpy(desc, queue->device->sample_locations_1x, 8);
1821 desc += 2;
1822 memcpy(desc, queue->device->sample_locations_2x, 16);
1823 desc += 4;
1824 memcpy(desc, queue->device->sample_locations_4x, 32);
1825 desc += 8;
1826 memcpy(desc, queue->device->sample_locations_8x, 64);
1827 desc += 16;
1828 memcpy(desc, queue->device->sample_locations_16x, 128);
1829 }
1830
1831 static unsigned
1832 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1833 {
1834 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1835 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1836 device->physical_device->rad_info.family != CHIP_STONEY;
1837 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1838 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1839 device->physical_device->rad_info.max_se;
1840 unsigned offchip_granularity;
1841 unsigned hs_offchip_param;
1842 switch (device->tess_offchip_block_dw_size) {
1843 default:
1844 assert(0);
1845 /* fall through */
1846 case 8192:
1847 offchip_granularity = V_03093C_X_8K_DWORDS;
1848 break;
1849 case 4096:
1850 offchip_granularity = V_03093C_X_4K_DWORDS;
1851 break;
1852 }
1853
1854 switch (device->physical_device->rad_info.chip_class) {
1855 case SI:
1856 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1857 break;
1858 case CIK:
1859 case VI:
1860 case GFX9:
1861 default:
1862 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1863 break;
1864 }
1865
1866 *max_offchip_buffers_p = max_offchip_buffers;
1867 if (device->physical_device->rad_info.chip_class >= CIK) {
1868 if (device->physical_device->rad_info.chip_class >= VI)
1869 --max_offchip_buffers;
1870 hs_offchip_param =
1871 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1872 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1873 } else {
1874 hs_offchip_param =
1875 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1876 }
1877 return hs_offchip_param;
1878 }
1879
1880 static VkResult
1881 radv_get_preamble_cs(struct radv_queue *queue,
1882 uint32_t scratch_size,
1883 uint32_t compute_scratch_size,
1884 uint32_t esgs_ring_size,
1885 uint32_t gsvs_ring_size,
1886 bool needs_tess_rings,
1887 bool needs_sample_positions,
1888 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1889 struct radeon_winsys_cs **initial_preamble_cs,
1890 struct radeon_winsys_cs **continue_preamble_cs)
1891 {
1892 struct radeon_winsys_bo *scratch_bo = NULL;
1893 struct radeon_winsys_bo *descriptor_bo = NULL;
1894 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1895 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1896 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1897 struct radeon_winsys_bo *tess_rings_bo = NULL;
1898 struct radeon_winsys_cs *dest_cs[3] = {0};
1899 bool add_tess_rings = false, add_sample_positions = false;
1900 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1901 unsigned max_offchip_buffers;
1902 unsigned hs_offchip_param = 0;
1903 unsigned tess_offchip_ring_offset;
1904 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1905 if (!queue->has_tess_rings) {
1906 if (needs_tess_rings)
1907 add_tess_rings = true;
1908 }
1909 if (!queue->has_sample_positions) {
1910 if (needs_sample_positions)
1911 add_sample_positions = true;
1912 }
1913 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1914 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1915 &max_offchip_buffers);
1916 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1917 tess_offchip_ring_size = max_offchip_buffers *
1918 queue->device->tess_offchip_block_dw_size * 4;
1919
1920 if (scratch_size <= queue->scratch_size &&
1921 compute_scratch_size <= queue->compute_scratch_size &&
1922 esgs_ring_size <= queue->esgs_ring_size &&
1923 gsvs_ring_size <= queue->gsvs_ring_size &&
1924 !add_tess_rings && !add_sample_positions &&
1925 queue->initial_preamble_cs) {
1926 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1927 *initial_preamble_cs = queue->initial_preamble_cs;
1928 *continue_preamble_cs = queue->continue_preamble_cs;
1929 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1930 *continue_preamble_cs = NULL;
1931 return VK_SUCCESS;
1932 }
1933
1934 if (scratch_size > queue->scratch_size) {
1935 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1936 scratch_size,
1937 4096,
1938 RADEON_DOMAIN_VRAM,
1939 ring_bo_flags);
1940 if (!scratch_bo)
1941 goto fail;
1942 } else
1943 scratch_bo = queue->scratch_bo;
1944
1945 if (compute_scratch_size > queue->compute_scratch_size) {
1946 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1947 compute_scratch_size,
1948 4096,
1949 RADEON_DOMAIN_VRAM,
1950 ring_bo_flags);
1951 if (!compute_scratch_bo)
1952 goto fail;
1953
1954 } else
1955 compute_scratch_bo = queue->compute_scratch_bo;
1956
1957 if (esgs_ring_size > queue->esgs_ring_size) {
1958 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1959 esgs_ring_size,
1960 4096,
1961 RADEON_DOMAIN_VRAM,
1962 ring_bo_flags);
1963 if (!esgs_ring_bo)
1964 goto fail;
1965 } else {
1966 esgs_ring_bo = queue->esgs_ring_bo;
1967 esgs_ring_size = queue->esgs_ring_size;
1968 }
1969
1970 if (gsvs_ring_size > queue->gsvs_ring_size) {
1971 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1972 gsvs_ring_size,
1973 4096,
1974 RADEON_DOMAIN_VRAM,
1975 ring_bo_flags);
1976 if (!gsvs_ring_bo)
1977 goto fail;
1978 } else {
1979 gsvs_ring_bo = queue->gsvs_ring_bo;
1980 gsvs_ring_size = queue->gsvs_ring_size;
1981 }
1982
1983 if (add_tess_rings) {
1984 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1985 tess_offchip_ring_offset + tess_offchip_ring_size,
1986 256,
1987 RADEON_DOMAIN_VRAM,
1988 ring_bo_flags);
1989 if (!tess_rings_bo)
1990 goto fail;
1991 } else {
1992 tess_rings_bo = queue->tess_rings_bo;
1993 }
1994
1995 if (scratch_bo != queue->scratch_bo ||
1996 esgs_ring_bo != queue->esgs_ring_bo ||
1997 gsvs_ring_bo != queue->gsvs_ring_bo ||
1998 tess_rings_bo != queue->tess_rings_bo ||
1999 add_sample_positions) {
2000 uint32_t size = 0;
2001 if (gsvs_ring_bo || esgs_ring_bo ||
2002 tess_rings_bo || add_sample_positions) {
2003 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2004 if (add_sample_positions)
2005 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2006 }
2007 else if (scratch_bo)
2008 size = 8; /* 2 dword */
2009
2010 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2011 size,
2012 4096,
2013 RADEON_DOMAIN_VRAM,
2014 RADEON_FLAG_CPU_ACCESS |
2015 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2016 RADEON_FLAG_READ_ONLY);
2017 if (!descriptor_bo)
2018 goto fail;
2019 } else
2020 descriptor_bo = queue->descriptor_bo;
2021
2022 for(int i = 0; i < 3; ++i) {
2023 struct radeon_winsys_cs *cs = NULL;
2024 cs = queue->device->ws->cs_create(queue->device->ws,
2025 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2026 if (!cs)
2027 goto fail;
2028
2029 dest_cs[i] = cs;
2030
2031 if (scratch_bo)
2032 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
2033
2034 if (esgs_ring_bo)
2035 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
2036
2037 if (gsvs_ring_bo)
2038 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
2039
2040 if (tess_rings_bo)
2041 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
2042
2043 if (descriptor_bo)
2044 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
2045
2046 if (descriptor_bo != queue->descriptor_bo) {
2047 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2048
2049 if (scratch_bo) {
2050 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2051 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2052 S_008F04_SWIZZLE_ENABLE(1);
2053 map[0] = scratch_va;
2054 map[1] = rsrc1;
2055 }
2056
2057 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2058 add_sample_positions)
2059 fill_geom_tess_rings(queue, map, add_sample_positions,
2060 esgs_ring_size, esgs_ring_bo,
2061 gsvs_ring_size, gsvs_ring_bo,
2062 tess_factor_ring_size,
2063 tess_offchip_ring_offset,
2064 tess_offchip_ring_size,
2065 tess_rings_bo);
2066
2067 queue->device->ws->buffer_unmap(descriptor_bo);
2068 }
2069
2070 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2071 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2072 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2073 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2074 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2075 }
2076
2077 if (esgs_ring_bo || gsvs_ring_bo) {
2078 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2079 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2080 radeon_emit(cs, esgs_ring_size >> 8);
2081 radeon_emit(cs, gsvs_ring_size >> 8);
2082 } else {
2083 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2084 radeon_emit(cs, esgs_ring_size >> 8);
2085 radeon_emit(cs, gsvs_ring_size >> 8);
2086 }
2087 }
2088
2089 if (tess_rings_bo) {
2090 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
2091 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2092 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2093 S_030938_SIZE(tess_factor_ring_size / 4));
2094 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2095 tf_va >> 8);
2096 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2097 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2098 S_030944_BASE_HI(tf_va >> 40));
2099 }
2100 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
2101 } else {
2102 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2103 S_008988_SIZE(tess_factor_ring_size / 4));
2104 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2105 tf_va >> 8);
2106 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2107 hs_offchip_param);
2108 }
2109 }
2110
2111 if (descriptor_bo) {
2112 uint64_t va = radv_buffer_get_va(descriptor_bo);
2113 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2114 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2115 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2116 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2117 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2118
2119 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2120 radeon_set_sh_reg_seq(cs, regs[i], 2);
2121 radeon_emit(cs, va);
2122 radeon_emit(cs, va >> 32);
2123 }
2124 } else {
2125 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2126 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2127 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2128 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2129 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2130 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2131
2132 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2133 radeon_set_sh_reg_seq(cs, regs[i], 2);
2134 radeon_emit(cs, va);
2135 radeon_emit(cs, va >> 32);
2136 }
2137 }
2138 }
2139
2140 if (compute_scratch_bo) {
2141 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
2142 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2143 S_008F04_SWIZZLE_ENABLE(1);
2144
2145 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
2146
2147 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2148 radeon_emit(cs, scratch_va);
2149 radeon_emit(cs, rsrc1);
2150 }
2151
2152 if (i == 0) {
2153 si_cs_emit_cache_flush(cs,
2154 queue->device->physical_device->rad_info.chip_class,
2155 NULL, 0,
2156 queue->queue_family_index == RING_COMPUTE &&
2157 queue->device->physical_device->rad_info.chip_class >= CIK,
2158 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2159 RADV_CMD_FLAG_INV_ICACHE |
2160 RADV_CMD_FLAG_INV_SMEM_L1 |
2161 RADV_CMD_FLAG_INV_VMEM_L1 |
2162 RADV_CMD_FLAG_INV_GLOBAL_L2);
2163 } else if (i == 1) {
2164 si_cs_emit_cache_flush(cs,
2165 queue->device->physical_device->rad_info.chip_class,
2166 NULL, 0,
2167 queue->queue_family_index == RING_COMPUTE &&
2168 queue->device->physical_device->rad_info.chip_class >= CIK,
2169 RADV_CMD_FLAG_INV_ICACHE |
2170 RADV_CMD_FLAG_INV_SMEM_L1 |
2171 RADV_CMD_FLAG_INV_VMEM_L1 |
2172 RADV_CMD_FLAG_INV_GLOBAL_L2);
2173 }
2174
2175 if (!queue->device->ws->cs_finalize(cs))
2176 goto fail;
2177 }
2178
2179 if (queue->initial_full_flush_preamble_cs)
2180 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2181
2182 if (queue->initial_preamble_cs)
2183 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2184
2185 if (queue->continue_preamble_cs)
2186 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2187
2188 queue->initial_full_flush_preamble_cs = dest_cs[0];
2189 queue->initial_preamble_cs = dest_cs[1];
2190 queue->continue_preamble_cs = dest_cs[2];
2191
2192 if (scratch_bo != queue->scratch_bo) {
2193 if (queue->scratch_bo)
2194 queue->device->ws->buffer_destroy(queue->scratch_bo);
2195 queue->scratch_bo = scratch_bo;
2196 queue->scratch_size = scratch_size;
2197 }
2198
2199 if (compute_scratch_bo != queue->compute_scratch_bo) {
2200 if (queue->compute_scratch_bo)
2201 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2202 queue->compute_scratch_bo = compute_scratch_bo;
2203 queue->compute_scratch_size = compute_scratch_size;
2204 }
2205
2206 if (esgs_ring_bo != queue->esgs_ring_bo) {
2207 if (queue->esgs_ring_bo)
2208 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2209 queue->esgs_ring_bo = esgs_ring_bo;
2210 queue->esgs_ring_size = esgs_ring_size;
2211 }
2212
2213 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2214 if (queue->gsvs_ring_bo)
2215 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2216 queue->gsvs_ring_bo = gsvs_ring_bo;
2217 queue->gsvs_ring_size = gsvs_ring_size;
2218 }
2219
2220 if (tess_rings_bo != queue->tess_rings_bo) {
2221 queue->tess_rings_bo = tess_rings_bo;
2222 queue->has_tess_rings = true;
2223 }
2224
2225 if (descriptor_bo != queue->descriptor_bo) {
2226 if (queue->descriptor_bo)
2227 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2228
2229 queue->descriptor_bo = descriptor_bo;
2230 }
2231
2232 if (add_sample_positions)
2233 queue->has_sample_positions = true;
2234
2235 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2236 *initial_preamble_cs = queue->initial_preamble_cs;
2237 *continue_preamble_cs = queue->continue_preamble_cs;
2238 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2239 *continue_preamble_cs = NULL;
2240 return VK_SUCCESS;
2241 fail:
2242 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2243 if (dest_cs[i])
2244 queue->device->ws->cs_destroy(dest_cs[i]);
2245 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2246 queue->device->ws->buffer_destroy(descriptor_bo);
2247 if (scratch_bo && scratch_bo != queue->scratch_bo)
2248 queue->device->ws->buffer_destroy(scratch_bo);
2249 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2250 queue->device->ws->buffer_destroy(compute_scratch_bo);
2251 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2252 queue->device->ws->buffer_destroy(esgs_ring_bo);
2253 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2254 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2255 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2256 queue->device->ws->buffer_destroy(tess_rings_bo);
2257 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2258 }
2259
2260 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2261 int num_sems,
2262 const VkSemaphore *sems,
2263 VkFence _fence,
2264 bool reset_temp)
2265 {
2266 int syncobj_idx = 0, sem_idx = 0;
2267
2268 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2269 return VK_SUCCESS;
2270
2271 for (uint32_t i = 0; i < num_sems; i++) {
2272 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2273
2274 if (sem->temp_syncobj || sem->syncobj)
2275 counts->syncobj_count++;
2276 else
2277 counts->sem_count++;
2278 }
2279
2280 if (_fence != VK_NULL_HANDLE) {
2281 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2282 if (fence->temp_syncobj || fence->syncobj)
2283 counts->syncobj_count++;
2284 }
2285
2286 if (counts->syncobj_count) {
2287 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2288 if (!counts->syncobj)
2289 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2290 }
2291
2292 if (counts->sem_count) {
2293 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2294 if (!counts->sem) {
2295 free(counts->syncobj);
2296 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2297 }
2298 }
2299
2300 for (uint32_t i = 0; i < num_sems; i++) {
2301 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2302
2303 if (sem->temp_syncobj) {
2304 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2305 }
2306 else if (sem->syncobj)
2307 counts->syncobj[syncobj_idx++] = sem->syncobj;
2308 else {
2309 assert(sem->sem);
2310 counts->sem[sem_idx++] = sem->sem;
2311 }
2312 }
2313
2314 if (_fence != VK_NULL_HANDLE) {
2315 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2316 if (fence->temp_syncobj)
2317 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2318 else if (fence->syncobj)
2319 counts->syncobj[syncobj_idx++] = fence->syncobj;
2320 }
2321
2322 return VK_SUCCESS;
2323 }
2324
2325 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2326 {
2327 free(sem_info->wait.syncobj);
2328 free(sem_info->wait.sem);
2329 free(sem_info->signal.syncobj);
2330 free(sem_info->signal.sem);
2331 }
2332
2333
2334 static void radv_free_temp_syncobjs(struct radv_device *device,
2335 int num_sems,
2336 const VkSemaphore *sems)
2337 {
2338 for (uint32_t i = 0; i < num_sems; i++) {
2339 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2340
2341 if (sem->temp_syncobj) {
2342 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2343 sem->temp_syncobj = 0;
2344 }
2345 }
2346 }
2347
2348 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2349 int num_wait_sems,
2350 const VkSemaphore *wait_sems,
2351 int num_signal_sems,
2352 const VkSemaphore *signal_sems,
2353 VkFence fence)
2354 {
2355 VkResult ret;
2356 memset(sem_info, 0, sizeof(*sem_info));
2357
2358 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2359 if (ret)
2360 return ret;
2361 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2362 if (ret)
2363 radv_free_sem_info(sem_info);
2364
2365 /* caller can override these */
2366 sem_info->cs_emit_wait = true;
2367 sem_info->cs_emit_signal = true;
2368 return ret;
2369 }
2370
2371 /* Signals fence as soon as all the work currently put on queue is done. */
2372 static VkResult radv_signal_fence(struct radv_queue *queue,
2373 struct radv_fence *fence)
2374 {
2375 int ret;
2376 VkResult result;
2377 struct radv_winsys_sem_info sem_info;
2378
2379 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2380 radv_fence_to_handle(fence));
2381 if (result != VK_SUCCESS)
2382 return result;
2383
2384 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2385 &queue->device->empty_cs[queue->queue_family_index],
2386 1, NULL, NULL, &sem_info, NULL,
2387 false, fence->fence);
2388 radv_free_sem_info(&sem_info);
2389
2390 /* TODO: find a better error */
2391 if (ret)
2392 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2393
2394 return VK_SUCCESS;
2395 }
2396
2397 VkResult radv_QueueSubmit(
2398 VkQueue _queue,
2399 uint32_t submitCount,
2400 const VkSubmitInfo* pSubmits,
2401 VkFence _fence)
2402 {
2403 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2404 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2405 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2406 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2407 int ret;
2408 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2409 uint32_t scratch_size = 0;
2410 uint32_t compute_scratch_size = 0;
2411 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2412 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2413 VkResult result;
2414 bool fence_emitted = false;
2415 bool tess_rings_needed = false;
2416 bool sample_positions_needed = false;
2417
2418 /* Do this first so failing to allocate scratch buffers can't result in
2419 * partially executed submissions. */
2420 for (uint32_t i = 0; i < submitCount; i++) {
2421 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2422 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2423 pSubmits[i].pCommandBuffers[j]);
2424
2425 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2426 compute_scratch_size = MAX2(compute_scratch_size,
2427 cmd_buffer->compute_scratch_size_needed);
2428 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2429 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2430 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2431 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2432 }
2433 }
2434
2435 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2436 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2437 sample_positions_needed, &initial_flush_preamble_cs,
2438 &initial_preamble_cs, &continue_preamble_cs);
2439 if (result != VK_SUCCESS)
2440 return result;
2441
2442 for (uint32_t i = 0; i < submitCount; i++) {
2443 struct radeon_winsys_cs **cs_array;
2444 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2445 bool can_patch = true;
2446 uint32_t advance;
2447 struct radv_winsys_sem_info sem_info;
2448
2449 result = radv_alloc_sem_info(&sem_info,
2450 pSubmits[i].waitSemaphoreCount,
2451 pSubmits[i].pWaitSemaphores,
2452 pSubmits[i].signalSemaphoreCount,
2453 pSubmits[i].pSignalSemaphores,
2454 _fence);
2455 if (result != VK_SUCCESS)
2456 return result;
2457
2458 if (!pSubmits[i].commandBufferCount) {
2459 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2460 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2461 &queue->device->empty_cs[queue->queue_family_index],
2462 1, NULL, NULL,
2463 &sem_info, NULL,
2464 false, base_fence);
2465 if (ret) {
2466 radv_loge("failed to submit CS %d\n", i);
2467 abort();
2468 }
2469 fence_emitted = true;
2470 }
2471 radv_free_sem_info(&sem_info);
2472 continue;
2473 }
2474
2475 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2476 (pSubmits[i].commandBufferCount));
2477
2478 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2479 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2480 pSubmits[i].pCommandBuffers[j]);
2481 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2482
2483 cs_array[j] = cmd_buffer->cs;
2484 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2485 can_patch = false;
2486
2487 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2488 }
2489
2490 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2491 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2492 advance = MIN2(max_cs_submission,
2493 pSubmits[i].commandBufferCount - j);
2494
2495 if (queue->device->trace_bo)
2496 *queue->device->trace_id_ptr = 0;
2497
2498 sem_info.cs_emit_wait = j == 0;
2499 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2500
2501 if (unlikely(queue->device->use_global_bo_list))
2502 pthread_mutex_lock(&queue->device->bo_list.mutex);
2503
2504 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2505 advance, initial_preamble, continue_preamble_cs,
2506 &sem_info, &queue->device->bo_list.list,
2507 can_patch, base_fence);
2508
2509 if (unlikely(queue->device->use_global_bo_list))
2510 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2511
2512 if (ret) {
2513 radv_loge("failed to submit CS %d\n", i);
2514 abort();
2515 }
2516 fence_emitted = true;
2517 if (queue->device->trace_bo) {
2518 radv_check_gpu_hangs(queue, cs_array[j]);
2519 }
2520 }
2521
2522 radv_free_temp_syncobjs(queue->device,
2523 pSubmits[i].waitSemaphoreCount,
2524 pSubmits[i].pWaitSemaphores);
2525 radv_free_sem_info(&sem_info);
2526 free(cs_array);
2527 }
2528
2529 if (fence) {
2530 if (!fence_emitted) {
2531 radv_signal_fence(queue, fence);
2532 }
2533 fence->submitted = true;
2534 }
2535
2536 return VK_SUCCESS;
2537 }
2538
2539 VkResult radv_QueueWaitIdle(
2540 VkQueue _queue)
2541 {
2542 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2543
2544 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2545 radv_queue_family_to_ring(queue->queue_family_index),
2546 queue->queue_idx);
2547 return VK_SUCCESS;
2548 }
2549
2550 VkResult radv_DeviceWaitIdle(
2551 VkDevice _device)
2552 {
2553 RADV_FROM_HANDLE(radv_device, device, _device);
2554
2555 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2556 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2557 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2558 }
2559 }
2560 return VK_SUCCESS;
2561 }
2562
2563 VkResult radv_EnumerateInstanceExtensionProperties(
2564 const char* pLayerName,
2565 uint32_t* pPropertyCount,
2566 VkExtensionProperties* pProperties)
2567 {
2568 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2569
2570 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2571 if (radv_supported_instance_extensions.extensions[i]) {
2572 vk_outarray_append(&out, prop) {
2573 *prop = radv_instance_extensions[i];
2574 }
2575 }
2576 }
2577
2578 return vk_outarray_status(&out);
2579 }
2580
2581 VkResult radv_EnumerateDeviceExtensionProperties(
2582 VkPhysicalDevice physicalDevice,
2583 const char* pLayerName,
2584 uint32_t* pPropertyCount,
2585 VkExtensionProperties* pProperties)
2586 {
2587 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2588 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2589
2590 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2591 if (device->supported_extensions.extensions[i]) {
2592 vk_outarray_append(&out, prop) {
2593 *prop = radv_device_extensions[i];
2594 }
2595 }
2596 }
2597
2598 return vk_outarray_status(&out);
2599 }
2600
2601 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2602 VkInstance _instance,
2603 const char* pName)
2604 {
2605 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2606
2607 return radv_lookup_entrypoint_checked(pName,
2608 instance ? instance->apiVersion : 0,
2609 instance ? &instance->enabled_extensions : NULL,
2610 NULL);
2611 }
2612
2613 /* The loader wants us to expose a second GetInstanceProcAddr function
2614 * to work around certain LD_PRELOAD issues seen in apps.
2615 */
2616 PUBLIC
2617 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2618 VkInstance instance,
2619 const char* pName);
2620
2621 PUBLIC
2622 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2623 VkInstance instance,
2624 const char* pName)
2625 {
2626 return radv_GetInstanceProcAddr(instance, pName);
2627 }
2628
2629 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2630 VkDevice _device,
2631 const char* pName)
2632 {
2633 RADV_FROM_HANDLE(radv_device, device, _device);
2634
2635 return radv_lookup_entrypoint_checked(pName,
2636 device->instance->apiVersion,
2637 &device->instance->enabled_extensions,
2638 &device->enabled_extensions);
2639 }
2640
2641 bool radv_get_memory_fd(struct radv_device *device,
2642 struct radv_device_memory *memory,
2643 int *pFD)
2644 {
2645 struct radeon_bo_metadata metadata;
2646
2647 if (memory->image) {
2648 radv_init_metadata(device, memory->image, &metadata);
2649 device->ws->buffer_set_metadata(memory->bo, &metadata);
2650 }
2651
2652 return device->ws->buffer_get_fd(device->ws, memory->bo,
2653 pFD);
2654 }
2655
2656 static VkResult radv_alloc_memory(struct radv_device *device,
2657 const VkMemoryAllocateInfo* pAllocateInfo,
2658 const VkAllocationCallbacks* pAllocator,
2659 VkDeviceMemory* pMem)
2660 {
2661 struct radv_device_memory *mem;
2662 VkResult result;
2663 enum radeon_bo_domain domain;
2664 uint32_t flags = 0;
2665 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2666
2667 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2668
2669 if (pAllocateInfo->allocationSize == 0) {
2670 /* Apparently, this is allowed */
2671 *pMem = VK_NULL_HANDLE;
2672 return VK_SUCCESS;
2673 }
2674
2675 const VkImportMemoryFdInfoKHR *import_info =
2676 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2677 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2678 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2679 const VkExportMemoryAllocateInfoKHR *export_info =
2680 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2681 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2682 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2683
2684 const struct wsi_memory_allocate_info *wsi_info =
2685 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2686
2687 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2688 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2689 if (mem == NULL)
2690 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2691
2692 if (wsi_info && wsi_info->implicit_sync)
2693 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2694
2695 if (dedicate_info) {
2696 mem->image = radv_image_from_handle(dedicate_info->image);
2697 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2698 } else {
2699 mem->image = NULL;
2700 mem->buffer = NULL;
2701 }
2702
2703 mem->user_ptr = NULL;
2704
2705 if (import_info) {
2706 assert(import_info->handleType ==
2707 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2708 import_info->handleType ==
2709 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2710 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2711 NULL, NULL);
2712 if (!mem->bo) {
2713 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2714 goto fail;
2715 } else {
2716 close(import_info->fd);
2717 }
2718 } else if (host_ptr_info) {
2719 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2720 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2721 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2722 pAllocateInfo->allocationSize);
2723 if (!mem->bo) {
2724 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2725 goto fail;
2726 } else {
2727 mem->user_ptr = host_ptr_info->pHostPointer;
2728 }
2729 } else {
2730 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2731 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2732 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2733 domain = RADEON_DOMAIN_GTT;
2734 else
2735 domain = RADEON_DOMAIN_VRAM;
2736
2737 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2738 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2739 else
2740 flags |= RADEON_FLAG_CPU_ACCESS;
2741
2742 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2743 flags |= RADEON_FLAG_GTT_WC;
2744
2745 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2746 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2747
2748 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2749 domain, flags);
2750
2751 if (!mem->bo) {
2752 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2753 goto fail;
2754 }
2755 mem->type_index = mem_type_index;
2756 }
2757
2758 result = radv_bo_list_add(device, mem->bo);
2759 if (result != VK_SUCCESS)
2760 goto fail_bo;
2761
2762 *pMem = radv_device_memory_to_handle(mem);
2763
2764 return VK_SUCCESS;
2765
2766 fail_bo:
2767 device->ws->buffer_destroy(mem->bo);
2768 fail:
2769 vk_free2(&device->alloc, pAllocator, mem);
2770
2771 return result;
2772 }
2773
2774 VkResult radv_AllocateMemory(
2775 VkDevice _device,
2776 const VkMemoryAllocateInfo* pAllocateInfo,
2777 const VkAllocationCallbacks* pAllocator,
2778 VkDeviceMemory* pMem)
2779 {
2780 RADV_FROM_HANDLE(radv_device, device, _device);
2781 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2782 }
2783
2784 void radv_FreeMemory(
2785 VkDevice _device,
2786 VkDeviceMemory _mem,
2787 const VkAllocationCallbacks* pAllocator)
2788 {
2789 RADV_FROM_HANDLE(radv_device, device, _device);
2790 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2791
2792 if (mem == NULL)
2793 return;
2794
2795 radv_bo_list_remove(device, mem->bo);
2796 device->ws->buffer_destroy(mem->bo);
2797 mem->bo = NULL;
2798
2799 vk_free2(&device->alloc, pAllocator, mem);
2800 }
2801
2802 VkResult radv_MapMemory(
2803 VkDevice _device,
2804 VkDeviceMemory _memory,
2805 VkDeviceSize offset,
2806 VkDeviceSize size,
2807 VkMemoryMapFlags flags,
2808 void** ppData)
2809 {
2810 RADV_FROM_HANDLE(radv_device, device, _device);
2811 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2812
2813 if (mem == NULL) {
2814 *ppData = NULL;
2815 return VK_SUCCESS;
2816 }
2817
2818 if (mem->user_ptr)
2819 *ppData = mem->user_ptr;
2820 else
2821 *ppData = device->ws->buffer_map(mem->bo);
2822
2823 if (*ppData) {
2824 *ppData += offset;
2825 return VK_SUCCESS;
2826 }
2827
2828 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2829 }
2830
2831 void radv_UnmapMemory(
2832 VkDevice _device,
2833 VkDeviceMemory _memory)
2834 {
2835 RADV_FROM_HANDLE(radv_device, device, _device);
2836 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2837
2838 if (mem == NULL)
2839 return;
2840
2841 if (mem->user_ptr == NULL)
2842 device->ws->buffer_unmap(mem->bo);
2843 }
2844
2845 VkResult radv_FlushMappedMemoryRanges(
2846 VkDevice _device,
2847 uint32_t memoryRangeCount,
2848 const VkMappedMemoryRange* pMemoryRanges)
2849 {
2850 return VK_SUCCESS;
2851 }
2852
2853 VkResult radv_InvalidateMappedMemoryRanges(
2854 VkDevice _device,
2855 uint32_t memoryRangeCount,
2856 const VkMappedMemoryRange* pMemoryRanges)
2857 {
2858 return VK_SUCCESS;
2859 }
2860
2861 void radv_GetBufferMemoryRequirements(
2862 VkDevice _device,
2863 VkBuffer _buffer,
2864 VkMemoryRequirements* pMemoryRequirements)
2865 {
2866 RADV_FROM_HANDLE(radv_device, device, _device);
2867 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2868
2869 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2870
2871 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2872 pMemoryRequirements->alignment = 4096;
2873 else
2874 pMemoryRequirements->alignment = 16;
2875
2876 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2877 }
2878
2879 void radv_GetBufferMemoryRequirements2(
2880 VkDevice device,
2881 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2882 VkMemoryRequirements2KHR* pMemoryRequirements)
2883 {
2884 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2885 &pMemoryRequirements->memoryRequirements);
2886 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2887 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2888 switch (ext->sType) {
2889 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2890 VkMemoryDedicatedRequirementsKHR *req =
2891 (VkMemoryDedicatedRequirementsKHR *) ext;
2892 req->requiresDedicatedAllocation = buffer->shareable;
2893 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2894 break;
2895 }
2896 default:
2897 break;
2898 }
2899 }
2900 }
2901
2902 void radv_GetImageMemoryRequirements(
2903 VkDevice _device,
2904 VkImage _image,
2905 VkMemoryRequirements* pMemoryRequirements)
2906 {
2907 RADV_FROM_HANDLE(radv_device, device, _device);
2908 RADV_FROM_HANDLE(radv_image, image, _image);
2909
2910 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2911
2912 pMemoryRequirements->size = image->size;
2913 pMemoryRequirements->alignment = image->alignment;
2914 }
2915
2916 void radv_GetImageMemoryRequirements2(
2917 VkDevice device,
2918 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2919 VkMemoryRequirements2KHR* pMemoryRequirements)
2920 {
2921 radv_GetImageMemoryRequirements(device, pInfo->image,
2922 &pMemoryRequirements->memoryRequirements);
2923
2924 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2925
2926 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2927 switch (ext->sType) {
2928 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2929 VkMemoryDedicatedRequirementsKHR *req =
2930 (VkMemoryDedicatedRequirementsKHR *) ext;
2931 req->requiresDedicatedAllocation = image->shareable;
2932 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2933 break;
2934 }
2935 default:
2936 break;
2937 }
2938 }
2939 }
2940
2941 void radv_GetImageSparseMemoryRequirements(
2942 VkDevice device,
2943 VkImage image,
2944 uint32_t* pSparseMemoryRequirementCount,
2945 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2946 {
2947 stub();
2948 }
2949
2950 void radv_GetImageSparseMemoryRequirements2(
2951 VkDevice device,
2952 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2953 uint32_t* pSparseMemoryRequirementCount,
2954 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2955 {
2956 stub();
2957 }
2958
2959 void radv_GetDeviceMemoryCommitment(
2960 VkDevice device,
2961 VkDeviceMemory memory,
2962 VkDeviceSize* pCommittedMemoryInBytes)
2963 {
2964 *pCommittedMemoryInBytes = 0;
2965 }
2966
2967 VkResult radv_BindBufferMemory2(VkDevice device,
2968 uint32_t bindInfoCount,
2969 const VkBindBufferMemoryInfoKHR *pBindInfos)
2970 {
2971 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2972 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2973 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2974
2975 if (mem) {
2976 buffer->bo = mem->bo;
2977 buffer->offset = pBindInfos[i].memoryOffset;
2978 } else {
2979 buffer->bo = NULL;
2980 }
2981 }
2982 return VK_SUCCESS;
2983 }
2984
2985 VkResult radv_BindBufferMemory(
2986 VkDevice device,
2987 VkBuffer buffer,
2988 VkDeviceMemory memory,
2989 VkDeviceSize memoryOffset)
2990 {
2991 const VkBindBufferMemoryInfoKHR info = {
2992 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2993 .buffer = buffer,
2994 .memory = memory,
2995 .memoryOffset = memoryOffset
2996 };
2997
2998 return radv_BindBufferMemory2(device, 1, &info);
2999 }
3000
3001 VkResult radv_BindImageMemory2(VkDevice device,
3002 uint32_t bindInfoCount,
3003 const VkBindImageMemoryInfoKHR *pBindInfos)
3004 {
3005 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3006 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3007 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3008
3009 if (mem) {
3010 image->bo = mem->bo;
3011 image->offset = pBindInfos[i].memoryOffset;
3012 } else {
3013 image->bo = NULL;
3014 image->offset = 0;
3015 }
3016 }
3017 return VK_SUCCESS;
3018 }
3019
3020
3021 VkResult radv_BindImageMemory(
3022 VkDevice device,
3023 VkImage image,
3024 VkDeviceMemory memory,
3025 VkDeviceSize memoryOffset)
3026 {
3027 const VkBindImageMemoryInfoKHR info = {
3028 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3029 .image = image,
3030 .memory = memory,
3031 .memoryOffset = memoryOffset
3032 };
3033
3034 return radv_BindImageMemory2(device, 1, &info);
3035 }
3036
3037
3038 static void
3039 radv_sparse_buffer_bind_memory(struct radv_device *device,
3040 const VkSparseBufferMemoryBindInfo *bind)
3041 {
3042 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3043
3044 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3045 struct radv_device_memory *mem = NULL;
3046
3047 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3048 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3049
3050 device->ws->buffer_virtual_bind(buffer->bo,
3051 bind->pBinds[i].resourceOffset,
3052 bind->pBinds[i].size,
3053 mem ? mem->bo : NULL,
3054 bind->pBinds[i].memoryOffset);
3055 }
3056 }
3057
3058 static void
3059 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3060 const VkSparseImageOpaqueMemoryBindInfo *bind)
3061 {
3062 RADV_FROM_HANDLE(radv_image, image, bind->image);
3063
3064 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3065 struct radv_device_memory *mem = NULL;
3066
3067 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3068 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3069
3070 device->ws->buffer_virtual_bind(image->bo,
3071 bind->pBinds[i].resourceOffset,
3072 bind->pBinds[i].size,
3073 mem ? mem->bo : NULL,
3074 bind->pBinds[i].memoryOffset);
3075 }
3076 }
3077
3078 VkResult radv_QueueBindSparse(
3079 VkQueue _queue,
3080 uint32_t bindInfoCount,
3081 const VkBindSparseInfo* pBindInfo,
3082 VkFence _fence)
3083 {
3084 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3085 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3086 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3087 bool fence_emitted = false;
3088
3089 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3090 struct radv_winsys_sem_info sem_info;
3091 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3092 radv_sparse_buffer_bind_memory(queue->device,
3093 pBindInfo[i].pBufferBinds + j);
3094 }
3095
3096 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3097 radv_sparse_image_opaque_bind_memory(queue->device,
3098 pBindInfo[i].pImageOpaqueBinds + j);
3099 }
3100
3101 VkResult result;
3102 result = radv_alloc_sem_info(&sem_info,
3103 pBindInfo[i].waitSemaphoreCount,
3104 pBindInfo[i].pWaitSemaphores,
3105 pBindInfo[i].signalSemaphoreCount,
3106 pBindInfo[i].pSignalSemaphores,
3107 _fence);
3108 if (result != VK_SUCCESS)
3109 return result;
3110
3111 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3112 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3113 &queue->device->empty_cs[queue->queue_family_index],
3114 1, NULL, NULL,
3115 &sem_info, NULL,
3116 false, base_fence);
3117 fence_emitted = true;
3118 if (fence)
3119 fence->submitted = true;
3120 }
3121
3122 radv_free_sem_info(&sem_info);
3123
3124 }
3125
3126 if (fence) {
3127 if (!fence_emitted) {
3128 radv_signal_fence(queue, fence);
3129 }
3130 fence->submitted = true;
3131 }
3132
3133 return VK_SUCCESS;
3134 }
3135
3136 VkResult radv_CreateFence(
3137 VkDevice _device,
3138 const VkFenceCreateInfo* pCreateInfo,
3139 const VkAllocationCallbacks* pAllocator,
3140 VkFence* pFence)
3141 {
3142 RADV_FROM_HANDLE(radv_device, device, _device);
3143 const VkExportFenceCreateInfoKHR *export =
3144 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3145 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3146 export ? export->handleTypes : 0;
3147
3148 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3149 sizeof(*fence), 8,
3150 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3151
3152 if (!fence)
3153 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3154
3155 fence->submitted = false;
3156 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3157 fence->temp_syncobj = 0;
3158 if (device->always_use_syncobj || handleTypes) {
3159 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3160 if (ret) {
3161 vk_free2(&device->alloc, pAllocator, fence);
3162 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3163 }
3164 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3165 device->ws->signal_syncobj(device->ws, fence->syncobj);
3166 }
3167 fence->fence = NULL;
3168 } else {
3169 fence->fence = device->ws->create_fence();
3170 if (!fence->fence) {
3171 vk_free2(&device->alloc, pAllocator, fence);
3172 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3173 }
3174 fence->syncobj = 0;
3175 }
3176
3177 *pFence = radv_fence_to_handle(fence);
3178
3179 return VK_SUCCESS;
3180 }
3181
3182 void radv_DestroyFence(
3183 VkDevice _device,
3184 VkFence _fence,
3185 const VkAllocationCallbacks* pAllocator)
3186 {
3187 RADV_FROM_HANDLE(radv_device, device, _device);
3188 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3189
3190 if (!fence)
3191 return;
3192
3193 if (fence->temp_syncobj)
3194 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3195 if (fence->syncobj)
3196 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3197 if (fence->fence)
3198 device->ws->destroy_fence(fence->fence);
3199 vk_free2(&device->alloc, pAllocator, fence);
3200 }
3201
3202
3203 static uint64_t radv_get_current_time()
3204 {
3205 struct timespec tv;
3206 clock_gettime(CLOCK_MONOTONIC, &tv);
3207 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3208 }
3209
3210 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3211 {
3212 uint64_t current_time = radv_get_current_time();
3213
3214 timeout = MIN2(UINT64_MAX - current_time, timeout);
3215
3216 return current_time + timeout;
3217 }
3218
3219
3220 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3221 {
3222 for (uint32_t i = 0; i < fenceCount; ++i) {
3223 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3224 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3225 return false;
3226 }
3227 return true;
3228 }
3229
3230 VkResult radv_WaitForFences(
3231 VkDevice _device,
3232 uint32_t fenceCount,
3233 const VkFence* pFences,
3234 VkBool32 waitAll,
3235 uint64_t timeout)
3236 {
3237 RADV_FROM_HANDLE(radv_device, device, _device);
3238 timeout = radv_get_absolute_timeout(timeout);
3239
3240 if (device->always_use_syncobj) {
3241 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3242 if (!handles)
3243 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3244
3245 for (uint32_t i = 0; i < fenceCount; ++i) {
3246 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3247 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3248 }
3249
3250 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3251
3252 free(handles);
3253 return success ? VK_SUCCESS : VK_TIMEOUT;
3254 }
3255
3256 if (!waitAll && fenceCount > 1) {
3257 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3258 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3259 uint32_t wait_count = 0;
3260 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3261 if (!fences)
3262 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3263
3264 for (uint32_t i = 0; i < fenceCount; ++i) {
3265 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3266
3267 if (fence->signalled) {
3268 free(fences);
3269 return VK_SUCCESS;
3270 }
3271
3272 fences[wait_count++] = fence->fence;
3273 }
3274
3275 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3276 waitAll, timeout - radv_get_current_time());
3277
3278 free(fences);
3279 return success ? VK_SUCCESS : VK_TIMEOUT;
3280 }
3281
3282 while(radv_get_current_time() <= timeout) {
3283 for (uint32_t i = 0; i < fenceCount; ++i) {
3284 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3285 return VK_SUCCESS;
3286 }
3287 }
3288 return VK_TIMEOUT;
3289 }
3290
3291 for (uint32_t i = 0; i < fenceCount; ++i) {
3292 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3293 bool expired = false;
3294
3295 if (fence->temp_syncobj) {
3296 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3297 return VK_TIMEOUT;
3298 continue;
3299 }
3300
3301 if (fence->syncobj) {
3302 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3303 return VK_TIMEOUT;
3304 continue;
3305 }
3306
3307 if (fence->signalled)
3308 continue;
3309
3310 if (!fence->submitted) {
3311 while(radv_get_current_time() <= timeout && !fence->submitted)
3312 /* Do nothing */;
3313
3314 if (!fence->submitted)
3315 return VK_TIMEOUT;
3316
3317 /* Recheck as it may have been set by submitting operations. */
3318 if (fence->signalled)
3319 continue;
3320 }
3321
3322 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3323 if (!expired)
3324 return VK_TIMEOUT;
3325
3326 fence->signalled = true;
3327 }
3328
3329 return VK_SUCCESS;
3330 }
3331
3332 VkResult radv_ResetFences(VkDevice _device,
3333 uint32_t fenceCount,
3334 const VkFence *pFences)
3335 {
3336 RADV_FROM_HANDLE(radv_device, device, _device);
3337
3338 for (unsigned i = 0; i < fenceCount; ++i) {
3339 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3340 fence->submitted = fence->signalled = false;
3341
3342 /* Per spec, we first restore the permanent payload, and then reset, so
3343 * having a temp syncobj should not skip resetting the permanent syncobj. */
3344 if (fence->temp_syncobj) {
3345 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3346 fence->temp_syncobj = 0;
3347 }
3348
3349 if (fence->syncobj) {
3350 device->ws->reset_syncobj(device->ws, fence->syncobj);
3351 }
3352 }
3353
3354 return VK_SUCCESS;
3355 }
3356
3357 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3358 {
3359 RADV_FROM_HANDLE(radv_device, device, _device);
3360 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3361
3362 if (fence->temp_syncobj) {
3363 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3364 return success ? VK_SUCCESS : VK_NOT_READY;
3365 }
3366
3367 if (fence->syncobj) {
3368 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3369 return success ? VK_SUCCESS : VK_NOT_READY;
3370 }
3371
3372 if (fence->signalled)
3373 return VK_SUCCESS;
3374 if (!fence->submitted)
3375 return VK_NOT_READY;
3376 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3377 return VK_NOT_READY;
3378
3379 return VK_SUCCESS;
3380 }
3381
3382
3383 // Queue semaphore functions
3384
3385 VkResult radv_CreateSemaphore(
3386 VkDevice _device,
3387 const VkSemaphoreCreateInfo* pCreateInfo,
3388 const VkAllocationCallbacks* pAllocator,
3389 VkSemaphore* pSemaphore)
3390 {
3391 RADV_FROM_HANDLE(radv_device, device, _device);
3392 const VkExportSemaphoreCreateInfoKHR *export =
3393 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3394 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3395 export ? export->handleTypes : 0;
3396
3397 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3398 sizeof(*sem), 8,
3399 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3400 if (!sem)
3401 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3402
3403 sem->temp_syncobj = 0;
3404 /* create a syncobject if we are going to export this semaphore */
3405 if (device->always_use_syncobj || handleTypes) {
3406 assert (device->physical_device->rad_info.has_syncobj);
3407 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3408 if (ret) {
3409 vk_free2(&device->alloc, pAllocator, sem);
3410 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3411 }
3412 sem->sem = NULL;
3413 } else {
3414 sem->sem = device->ws->create_sem(device->ws);
3415 if (!sem->sem) {
3416 vk_free2(&device->alloc, pAllocator, sem);
3417 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3418 }
3419 sem->syncobj = 0;
3420 }
3421
3422 *pSemaphore = radv_semaphore_to_handle(sem);
3423 return VK_SUCCESS;
3424 }
3425
3426 void radv_DestroySemaphore(
3427 VkDevice _device,
3428 VkSemaphore _semaphore,
3429 const VkAllocationCallbacks* pAllocator)
3430 {
3431 RADV_FROM_HANDLE(radv_device, device, _device);
3432 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3433 if (!_semaphore)
3434 return;
3435
3436 if (sem->syncobj)
3437 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3438 else
3439 device->ws->destroy_sem(sem->sem);
3440 vk_free2(&device->alloc, pAllocator, sem);
3441 }
3442
3443 VkResult radv_CreateEvent(
3444 VkDevice _device,
3445 const VkEventCreateInfo* pCreateInfo,
3446 const VkAllocationCallbacks* pAllocator,
3447 VkEvent* pEvent)
3448 {
3449 RADV_FROM_HANDLE(radv_device, device, _device);
3450 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3451 sizeof(*event), 8,
3452 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3453
3454 if (!event)
3455 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3456
3457 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3458 RADEON_DOMAIN_GTT,
3459 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3460 if (!event->bo) {
3461 vk_free2(&device->alloc, pAllocator, event);
3462 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3463 }
3464
3465 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3466
3467 *pEvent = radv_event_to_handle(event);
3468
3469 return VK_SUCCESS;
3470 }
3471
3472 void radv_DestroyEvent(
3473 VkDevice _device,
3474 VkEvent _event,
3475 const VkAllocationCallbacks* pAllocator)
3476 {
3477 RADV_FROM_HANDLE(radv_device, device, _device);
3478 RADV_FROM_HANDLE(radv_event, event, _event);
3479
3480 if (!event)
3481 return;
3482 device->ws->buffer_destroy(event->bo);
3483 vk_free2(&device->alloc, pAllocator, event);
3484 }
3485
3486 VkResult radv_GetEventStatus(
3487 VkDevice _device,
3488 VkEvent _event)
3489 {
3490 RADV_FROM_HANDLE(radv_event, event, _event);
3491
3492 if (*event->map == 1)
3493 return VK_EVENT_SET;
3494 return VK_EVENT_RESET;
3495 }
3496
3497 VkResult radv_SetEvent(
3498 VkDevice _device,
3499 VkEvent _event)
3500 {
3501 RADV_FROM_HANDLE(radv_event, event, _event);
3502 *event->map = 1;
3503
3504 return VK_SUCCESS;
3505 }
3506
3507 VkResult radv_ResetEvent(
3508 VkDevice _device,
3509 VkEvent _event)
3510 {
3511 RADV_FROM_HANDLE(radv_event, event, _event);
3512 *event->map = 0;
3513
3514 return VK_SUCCESS;
3515 }
3516
3517 VkResult radv_CreateBuffer(
3518 VkDevice _device,
3519 const VkBufferCreateInfo* pCreateInfo,
3520 const VkAllocationCallbacks* pAllocator,
3521 VkBuffer* pBuffer)
3522 {
3523 RADV_FROM_HANDLE(radv_device, device, _device);
3524 struct radv_buffer *buffer;
3525
3526 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3527
3528 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3529 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3530 if (buffer == NULL)
3531 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3532
3533 buffer->size = pCreateInfo->size;
3534 buffer->usage = pCreateInfo->usage;
3535 buffer->bo = NULL;
3536 buffer->offset = 0;
3537 buffer->flags = pCreateInfo->flags;
3538
3539 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3540 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3541
3542 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3543 buffer->bo = device->ws->buffer_create(device->ws,
3544 align64(buffer->size, 4096),
3545 4096, 0, RADEON_FLAG_VIRTUAL);
3546 if (!buffer->bo) {
3547 vk_free2(&device->alloc, pAllocator, buffer);
3548 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3549 }
3550 }
3551
3552 *pBuffer = radv_buffer_to_handle(buffer);
3553
3554 return VK_SUCCESS;
3555 }
3556
3557 void radv_DestroyBuffer(
3558 VkDevice _device,
3559 VkBuffer _buffer,
3560 const VkAllocationCallbacks* pAllocator)
3561 {
3562 RADV_FROM_HANDLE(radv_device, device, _device);
3563 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3564
3565 if (!buffer)
3566 return;
3567
3568 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3569 device->ws->buffer_destroy(buffer->bo);
3570
3571 vk_free2(&device->alloc, pAllocator, buffer);
3572 }
3573
3574 static inline unsigned
3575 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3576 {
3577 if (stencil)
3578 return image->surface.u.legacy.stencil_tiling_index[level];
3579 else
3580 return image->surface.u.legacy.tiling_index[level];
3581 }
3582
3583 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3584 {
3585 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3586 }
3587
3588 static uint32_t
3589 radv_init_dcc_control_reg(struct radv_device *device,
3590 struct radv_image_view *iview)
3591 {
3592 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3593 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3594 unsigned max_compressed_block_size;
3595 unsigned independent_64b_blocks;
3596
3597 if (device->physical_device->rad_info.chip_class < VI)
3598 return 0;
3599
3600 if (iview->image->info.samples > 1) {
3601 if (iview->image->surface.bpe == 1)
3602 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3603 else if (iview->image->surface.bpe == 2)
3604 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3605 }
3606
3607 if (!device->physical_device->rad_info.has_dedicated_vram) {
3608 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3609 * dGPU and 64 for APU because all of our APUs to date use
3610 * DIMMs which have a request granularity size of 64B while all
3611 * other chips have a 32B request size.
3612 */
3613 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3614 }
3615
3616 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3617 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3618 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3619 /* If this DCC image is potentially going to be used in texture
3620 * fetches, we need some special settings.
3621 */
3622 independent_64b_blocks = 1;
3623 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3624 } else {
3625 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3626 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3627 * big as possible for better compression state.
3628 */
3629 independent_64b_blocks = 0;
3630 max_compressed_block_size = max_uncompressed_block_size;
3631 }
3632
3633 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3634 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3635 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3636 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3637 }
3638
3639 static void
3640 radv_initialise_color_surface(struct radv_device *device,
3641 struct radv_color_buffer_info *cb,
3642 struct radv_image_view *iview)
3643 {
3644 const struct vk_format_description *desc;
3645 unsigned ntype, format, swap, endian;
3646 unsigned blend_clamp = 0, blend_bypass = 0;
3647 uint64_t va;
3648 const struct radeon_surf *surf = &iview->image->surface;
3649
3650 desc = vk_format_description(iview->vk_format);
3651
3652 memset(cb, 0, sizeof(*cb));
3653
3654 /* Intensity is implemented as Red, so treat it that way. */
3655 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3656
3657 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3658
3659 cb->cb_color_base = va >> 8;
3660
3661 if (device->physical_device->rad_info.chip_class >= GFX9) {
3662 struct gfx9_surf_meta_flags meta;
3663 if (iview->image->dcc_offset)
3664 meta = iview->image->surface.u.gfx9.dcc;
3665 else
3666 meta = iview->image->surface.u.gfx9.cmask;
3667
3668 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3669 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3670 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3671 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3672
3673 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3674 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3675 } else {
3676 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3677 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3678
3679 cb->cb_color_base += level_info->offset >> 8;
3680 if (level_info->mode == RADEON_SURF_MODE_2D)
3681 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3682
3683 pitch_tile_max = level_info->nblk_x / 8 - 1;
3684 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3685 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3686
3687 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3688 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3689 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3690
3691 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3692
3693 if (radv_image_has_fmask(iview->image)) {
3694 if (device->physical_device->rad_info.chip_class >= CIK)
3695 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3696 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3697 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3698 } else {
3699 /* This must be set for fast clear to work without FMASK. */
3700 if (device->physical_device->rad_info.chip_class >= CIK)
3701 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3702 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3703 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3704 }
3705 }
3706
3707 /* CMASK variables */
3708 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3709 va += iview->image->cmask.offset;
3710 cb->cb_color_cmask = va >> 8;
3711
3712 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3713 va += iview->image->dcc_offset;
3714 cb->cb_dcc_base = va >> 8;
3715 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3716
3717 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3718 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3719 S_028C6C_SLICE_MAX(max_slice);
3720
3721 if (iview->image->info.samples > 1) {
3722 unsigned log_samples = util_logbase2(iview->image->info.samples);
3723
3724 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3725 S_028C74_NUM_FRAGMENTS(log_samples);
3726 }
3727
3728 if (radv_image_has_fmask(iview->image)) {
3729 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3730 cb->cb_color_fmask = va >> 8;
3731 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3732 } else {
3733 cb->cb_color_fmask = cb->cb_color_base;
3734 }
3735
3736 ntype = radv_translate_color_numformat(iview->vk_format,
3737 desc,
3738 vk_format_get_first_non_void_channel(iview->vk_format));
3739 format = radv_translate_colorformat(iview->vk_format);
3740 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3741 radv_finishme("Illegal color\n");
3742 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3743 endian = radv_colorformat_endian_swap(format);
3744
3745 /* blend clamp should be set for all NORM/SRGB types */
3746 if (ntype == V_028C70_NUMBER_UNORM ||
3747 ntype == V_028C70_NUMBER_SNORM ||
3748 ntype == V_028C70_NUMBER_SRGB)
3749 blend_clamp = 1;
3750
3751 /* set blend bypass according to docs if SINT/UINT or
3752 8/24 COLOR variants */
3753 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3754 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3755 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3756 blend_clamp = 0;
3757 blend_bypass = 1;
3758 }
3759 #if 0
3760 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3761 (format == V_028C70_COLOR_8 ||
3762 format == V_028C70_COLOR_8_8 ||
3763 format == V_028C70_COLOR_8_8_8_8))
3764 ->color_is_int8 = true;
3765 #endif
3766 cb->cb_color_info = S_028C70_FORMAT(format) |
3767 S_028C70_COMP_SWAP(swap) |
3768 S_028C70_BLEND_CLAMP(blend_clamp) |
3769 S_028C70_BLEND_BYPASS(blend_bypass) |
3770 S_028C70_SIMPLE_FLOAT(1) |
3771 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3772 ntype != V_028C70_NUMBER_SNORM &&
3773 ntype != V_028C70_NUMBER_SRGB &&
3774 format != V_028C70_COLOR_8_24 &&
3775 format != V_028C70_COLOR_24_8) |
3776 S_028C70_NUMBER_TYPE(ntype) |
3777 S_028C70_ENDIAN(endian);
3778 if (radv_image_has_fmask(iview->image)) {
3779 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3780 if (device->physical_device->rad_info.chip_class == SI) {
3781 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3782 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3783 }
3784 }
3785
3786 if (radv_image_has_cmask(iview->image) &&
3787 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3788 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3789
3790 if (radv_dcc_enabled(iview->image, iview->base_mip))
3791 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3792
3793 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3794
3795 /* This must be set for fast clear to work without FMASK. */
3796 if (!radv_image_has_fmask(iview->image) &&
3797 device->physical_device->rad_info.chip_class == SI) {
3798 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3799 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3800 }
3801
3802 if (device->physical_device->rad_info.chip_class >= GFX9) {
3803 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3804 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3805
3806 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3807 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3808 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3809 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3810 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3811 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3812 }
3813 }
3814
3815 static unsigned
3816 radv_calc_decompress_on_z_planes(struct radv_device *device,
3817 struct radv_image_view *iview)
3818 {
3819 unsigned max_zplanes = 0;
3820
3821 assert(radv_image_is_tc_compat_htile(iview->image));
3822
3823 if (device->physical_device->rad_info.chip_class >= GFX9) {
3824 /* Default value for 32-bit depth surfaces. */
3825 max_zplanes = 4;
3826
3827 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3828 iview->image->info.samples > 1)
3829 max_zplanes = 2;
3830
3831 max_zplanes = max_zplanes + 1;
3832 } else {
3833 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3834 /* Do not enable Z plane compression for 16-bit depth
3835 * surfaces because isn't supported on GFX8. Only
3836 * 32-bit depth surfaces are supported by the hardware.
3837 * This allows to maintain shader compatibility and to
3838 * reduce the number of depth decompressions.
3839 */
3840 max_zplanes = 1;
3841 } else {
3842 if (iview->image->info.samples <= 1)
3843 max_zplanes = 5;
3844 else if (iview->image->info.samples <= 4)
3845 max_zplanes = 3;
3846 else
3847 max_zplanes = 2;
3848 }
3849 }
3850
3851 return max_zplanes;
3852 }
3853
3854 static void
3855 radv_initialise_ds_surface(struct radv_device *device,
3856 struct radv_ds_buffer_info *ds,
3857 struct radv_image_view *iview)
3858 {
3859 unsigned level = iview->base_mip;
3860 unsigned format, stencil_format;
3861 uint64_t va, s_offs, z_offs;
3862 bool stencil_only = false;
3863 memset(ds, 0, sizeof(*ds));
3864 switch (iview->image->vk_format) {
3865 case VK_FORMAT_D24_UNORM_S8_UINT:
3866 case VK_FORMAT_X8_D24_UNORM_PACK32:
3867 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3868 ds->offset_scale = 2.0f;
3869 break;
3870 case VK_FORMAT_D16_UNORM:
3871 case VK_FORMAT_D16_UNORM_S8_UINT:
3872 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3873 ds->offset_scale = 4.0f;
3874 break;
3875 case VK_FORMAT_D32_SFLOAT:
3876 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3877 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3878 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3879 ds->offset_scale = 1.0f;
3880 break;
3881 case VK_FORMAT_S8_UINT:
3882 stencil_only = true;
3883 break;
3884 default:
3885 break;
3886 }
3887
3888 format = radv_translate_dbformat(iview->image->vk_format);
3889 stencil_format = iview->image->surface.has_stencil ?
3890 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3891
3892 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3893 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3894 S_028008_SLICE_MAX(max_slice);
3895
3896 ds->db_htile_data_base = 0;
3897 ds->db_htile_surface = 0;
3898
3899 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3900 s_offs = z_offs = va;
3901
3902 if (device->physical_device->rad_info.chip_class >= GFX9) {
3903 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3904 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3905
3906 ds->db_z_info = S_028038_FORMAT(format) |
3907 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3908 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3909 S_028038_MAXMIP(iview->image->info.levels - 1);
3910 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3911 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3912
3913 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3914 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3915 ds->db_depth_view |= S_028008_MIPID(level);
3916
3917 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3918 S_02801C_Y_MAX(iview->image->info.height - 1);
3919
3920 if (radv_htile_enabled(iview->image, level)) {
3921 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3922
3923 if (radv_image_is_tc_compat_htile(iview->image)) {
3924 unsigned max_zplanes =
3925 radv_calc_decompress_on_z_planes(device, iview);
3926
3927 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3928 S_028038_ITERATE_FLUSH(1);
3929 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3930 }
3931
3932 if (!iview->image->surface.has_stencil)
3933 /* Use all of the htile_buffer for depth if there's no stencil. */
3934 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3935 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3936 iview->image->htile_offset;
3937 ds->db_htile_data_base = va >> 8;
3938 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3939 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3940 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3941 }
3942 } else {
3943 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3944
3945 if (stencil_only)
3946 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3947
3948 z_offs += iview->image->surface.u.legacy.level[level].offset;
3949 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3950
3951 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3952 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3953 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3954
3955 if (iview->image->info.samples > 1)
3956 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3957
3958 if (device->physical_device->rad_info.chip_class >= CIK) {
3959 struct radeon_info *info = &device->physical_device->rad_info;
3960 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3961 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3962 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3963 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3964 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3965 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3966
3967 if (stencil_only)
3968 tile_mode = stencil_tile_mode;
3969
3970 ds->db_depth_info |=
3971 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3972 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3973 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3974 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3975 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3976 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3977 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3978 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3979 } else {
3980 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3981 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3982 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3983 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3984 if (stencil_only)
3985 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3986 }
3987
3988 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3989 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3990 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3991
3992 if (radv_htile_enabled(iview->image, level)) {
3993 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3994
3995 if (!iview->image->surface.has_stencil &&
3996 !radv_image_is_tc_compat_htile(iview->image))
3997 /* Use all of the htile_buffer for depth if there's no stencil. */
3998 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3999
4000 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4001 iview->image->htile_offset;
4002 ds->db_htile_data_base = va >> 8;
4003 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4004
4005 if (radv_image_is_tc_compat_htile(iview->image)) {
4006 unsigned max_zplanes =
4007 radv_calc_decompress_on_z_planes(device, iview);
4008
4009 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4010 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4011 }
4012 }
4013 }
4014
4015 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4016 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4017 }
4018
4019 VkResult radv_CreateFramebuffer(
4020 VkDevice _device,
4021 const VkFramebufferCreateInfo* pCreateInfo,
4022 const VkAllocationCallbacks* pAllocator,
4023 VkFramebuffer* pFramebuffer)
4024 {
4025 RADV_FROM_HANDLE(radv_device, device, _device);
4026 struct radv_framebuffer *framebuffer;
4027
4028 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4029
4030 size_t size = sizeof(*framebuffer) +
4031 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4032 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4033 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4034 if (framebuffer == NULL)
4035 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4036
4037 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4038 framebuffer->width = pCreateInfo->width;
4039 framebuffer->height = pCreateInfo->height;
4040 framebuffer->layers = pCreateInfo->layers;
4041 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4042 VkImageView _iview = pCreateInfo->pAttachments[i];
4043 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4044 framebuffer->attachments[i].attachment = iview;
4045 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4046 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4047 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4048 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4049 }
4050 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4051 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4052 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4053 }
4054
4055 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4056 return VK_SUCCESS;
4057 }
4058
4059 void radv_DestroyFramebuffer(
4060 VkDevice _device,
4061 VkFramebuffer _fb,
4062 const VkAllocationCallbacks* pAllocator)
4063 {
4064 RADV_FROM_HANDLE(radv_device, device, _device);
4065 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4066
4067 if (!fb)
4068 return;
4069 vk_free2(&device->alloc, pAllocator, fb);
4070 }
4071
4072 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4073 {
4074 switch (address_mode) {
4075 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4076 return V_008F30_SQ_TEX_WRAP;
4077 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4078 return V_008F30_SQ_TEX_MIRROR;
4079 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4080 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4081 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4082 return V_008F30_SQ_TEX_CLAMP_BORDER;
4083 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4084 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4085 default:
4086 unreachable("illegal tex wrap mode");
4087 break;
4088 }
4089 }
4090
4091 static unsigned
4092 radv_tex_compare(VkCompareOp op)
4093 {
4094 switch (op) {
4095 case VK_COMPARE_OP_NEVER:
4096 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4097 case VK_COMPARE_OP_LESS:
4098 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4099 case VK_COMPARE_OP_EQUAL:
4100 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4101 case VK_COMPARE_OP_LESS_OR_EQUAL:
4102 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4103 case VK_COMPARE_OP_GREATER:
4104 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4105 case VK_COMPARE_OP_NOT_EQUAL:
4106 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4107 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4108 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4109 case VK_COMPARE_OP_ALWAYS:
4110 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4111 default:
4112 unreachable("illegal compare mode");
4113 break;
4114 }
4115 }
4116
4117 static unsigned
4118 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4119 {
4120 switch (filter) {
4121 case VK_FILTER_NEAREST:
4122 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4123 V_008F38_SQ_TEX_XY_FILTER_POINT);
4124 case VK_FILTER_LINEAR:
4125 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4126 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4127 case VK_FILTER_CUBIC_IMG:
4128 default:
4129 fprintf(stderr, "illegal texture filter");
4130 return 0;
4131 }
4132 }
4133
4134 static unsigned
4135 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4136 {
4137 switch (mode) {
4138 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4139 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4140 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4141 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4142 default:
4143 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4144 }
4145 }
4146
4147 static unsigned
4148 radv_tex_bordercolor(VkBorderColor bcolor)
4149 {
4150 switch (bcolor) {
4151 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4152 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4153 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4154 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4155 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4156 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4157 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4158 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4159 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4160 default:
4161 break;
4162 }
4163 return 0;
4164 }
4165
4166 static unsigned
4167 radv_tex_aniso_filter(unsigned filter)
4168 {
4169 if (filter < 2)
4170 return 0;
4171 if (filter < 4)
4172 return 1;
4173 if (filter < 8)
4174 return 2;
4175 if (filter < 16)
4176 return 3;
4177 return 4;
4178 }
4179
4180 static unsigned
4181 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4182 {
4183 switch (mode) {
4184 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4185 return SQ_IMG_FILTER_MODE_BLEND;
4186 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4187 return SQ_IMG_FILTER_MODE_MIN;
4188 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4189 return SQ_IMG_FILTER_MODE_MAX;
4190 default:
4191 break;
4192 }
4193 return 0;
4194 }
4195
4196 static void
4197 radv_init_sampler(struct radv_device *device,
4198 struct radv_sampler *sampler,
4199 const VkSamplerCreateInfo *pCreateInfo)
4200 {
4201 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4202 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4203 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4204 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4205 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4206
4207 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4208 vk_find_struct_const(pCreateInfo->pNext,
4209 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4210 if (sampler_reduction)
4211 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4212
4213 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4214 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4215 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4216 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4217 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4218 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4219 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4220 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4221 S_008F30_DISABLE_CUBE_WRAP(0) |
4222 S_008F30_COMPAT_MODE(is_vi) |
4223 S_008F30_FILTER_MODE(filter_mode));
4224 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4225 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4226 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4227 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4228 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4229 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4230 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4231 S_008F38_MIP_POINT_PRECLAMP(0) |
4232 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4233 S_008F38_FILTER_PREC_FIX(1) |
4234 S_008F38_ANISO_OVERRIDE(is_vi));
4235 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4236 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4237 }
4238
4239 VkResult radv_CreateSampler(
4240 VkDevice _device,
4241 const VkSamplerCreateInfo* pCreateInfo,
4242 const VkAllocationCallbacks* pAllocator,
4243 VkSampler* pSampler)
4244 {
4245 RADV_FROM_HANDLE(radv_device, device, _device);
4246 struct radv_sampler *sampler;
4247
4248 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4249
4250 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4251 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4252 if (!sampler)
4253 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4254
4255 radv_init_sampler(device, sampler, pCreateInfo);
4256 *pSampler = radv_sampler_to_handle(sampler);
4257
4258 return VK_SUCCESS;
4259 }
4260
4261 void radv_DestroySampler(
4262 VkDevice _device,
4263 VkSampler _sampler,
4264 const VkAllocationCallbacks* pAllocator)
4265 {
4266 RADV_FROM_HANDLE(radv_device, device, _device);
4267 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4268
4269 if (!sampler)
4270 return;
4271 vk_free2(&device->alloc, pAllocator, sampler);
4272 }
4273
4274 /* vk_icd.h does not declare this function, so we declare it here to
4275 * suppress Wmissing-prototypes.
4276 */
4277 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4278 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4279
4280 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4281 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4282 {
4283 /* For the full details on loader interface versioning, see
4284 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4285 * What follows is a condensed summary, to help you navigate the large and
4286 * confusing official doc.
4287 *
4288 * - Loader interface v0 is incompatible with later versions. We don't
4289 * support it.
4290 *
4291 * - In loader interface v1:
4292 * - The first ICD entrypoint called by the loader is
4293 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4294 * entrypoint.
4295 * - The ICD must statically expose no other Vulkan symbol unless it is
4296 * linked with -Bsymbolic.
4297 * - Each dispatchable Vulkan handle created by the ICD must be
4298 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4299 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4300 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4301 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4302 * such loader-managed surfaces.
4303 *
4304 * - Loader interface v2 differs from v1 in:
4305 * - The first ICD entrypoint called by the loader is
4306 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4307 * statically expose this entrypoint.
4308 *
4309 * - Loader interface v3 differs from v2 in:
4310 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4311 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4312 * because the loader no longer does so.
4313 */
4314 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4315 return VK_SUCCESS;
4316 }
4317
4318 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4319 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4320 int *pFD)
4321 {
4322 RADV_FROM_HANDLE(radv_device, device, _device);
4323 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4324
4325 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4326
4327 /* At the moment, we support only the below handle types. */
4328 assert(pGetFdInfo->handleType ==
4329 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4330 pGetFdInfo->handleType ==
4331 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4332
4333 bool ret = radv_get_memory_fd(device, memory, pFD);
4334 if (ret == false)
4335 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4336 return VK_SUCCESS;
4337 }
4338
4339 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4340 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4341 int fd,
4342 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4343 {
4344 switch (handleType) {
4345 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4346 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4347 return VK_SUCCESS;
4348
4349 default:
4350 /* The valid usage section for this function says:
4351 *
4352 * "handleType must not be one of the handle types defined as
4353 * opaque."
4354 *
4355 * So opaque handle types fall into the default "unsupported" case.
4356 */
4357 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4358 }
4359 }
4360
4361 static VkResult radv_import_opaque_fd(struct radv_device *device,
4362 int fd,
4363 uint32_t *syncobj)
4364 {
4365 uint32_t syncobj_handle = 0;
4366 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4367 if (ret != 0)
4368 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4369
4370 if (*syncobj)
4371 device->ws->destroy_syncobj(device->ws, *syncobj);
4372
4373 *syncobj = syncobj_handle;
4374 close(fd);
4375
4376 return VK_SUCCESS;
4377 }
4378
4379 static VkResult radv_import_sync_fd(struct radv_device *device,
4380 int fd,
4381 uint32_t *syncobj)
4382 {
4383 /* If we create a syncobj we do it locally so that if we have an error, we don't
4384 * leave a syncobj in an undetermined state in the fence. */
4385 uint32_t syncobj_handle = *syncobj;
4386 if (!syncobj_handle) {
4387 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4388 if (ret) {
4389 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4390 }
4391 }
4392
4393 if (fd == -1) {
4394 device->ws->signal_syncobj(device->ws, syncobj_handle);
4395 } else {
4396 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4397 if (ret != 0)
4398 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4399 }
4400
4401 *syncobj = syncobj_handle;
4402 if (fd != -1)
4403 close(fd);
4404
4405 return VK_SUCCESS;
4406 }
4407
4408 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4409 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4410 {
4411 RADV_FROM_HANDLE(radv_device, device, _device);
4412 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4413 uint32_t *syncobj_dst = NULL;
4414
4415 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4416 syncobj_dst = &sem->temp_syncobj;
4417 } else {
4418 syncobj_dst = &sem->syncobj;
4419 }
4420
4421 switch(pImportSemaphoreFdInfo->handleType) {
4422 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4423 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4424 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4425 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4426 default:
4427 unreachable("Unhandled semaphore handle type");
4428 }
4429 }
4430
4431 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4432 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4433 int *pFd)
4434 {
4435 RADV_FROM_HANDLE(radv_device, device, _device);
4436 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4437 int ret;
4438 uint32_t syncobj_handle;
4439
4440 if (sem->temp_syncobj)
4441 syncobj_handle = sem->temp_syncobj;
4442 else
4443 syncobj_handle = sem->syncobj;
4444
4445 switch(pGetFdInfo->handleType) {
4446 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4447 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4448 break;
4449 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4450 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4451 if (!ret) {
4452 if (sem->temp_syncobj) {
4453 close (sem->temp_syncobj);
4454 sem->temp_syncobj = 0;
4455 } else {
4456 device->ws->reset_syncobj(device->ws, syncobj_handle);
4457 }
4458 }
4459 break;
4460 default:
4461 unreachable("Unhandled semaphore handle type");
4462 }
4463
4464 if (ret)
4465 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4466 return VK_SUCCESS;
4467 }
4468
4469 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4470 VkPhysicalDevice physicalDevice,
4471 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4472 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4473 {
4474 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4475
4476 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4477 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4478 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4479 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4480 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4481 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4482 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4483 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4484 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4485 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4486 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4487 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4488 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4489 } else {
4490 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4491 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4492 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4493 }
4494 }
4495
4496 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4497 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4498 {
4499 RADV_FROM_HANDLE(radv_device, device, _device);
4500 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4501 uint32_t *syncobj_dst = NULL;
4502
4503
4504 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4505 syncobj_dst = &fence->temp_syncobj;
4506 } else {
4507 syncobj_dst = &fence->syncobj;
4508 }
4509
4510 switch(pImportFenceFdInfo->handleType) {
4511 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4512 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4513 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4514 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4515 default:
4516 unreachable("Unhandled fence handle type");
4517 }
4518 }
4519
4520 VkResult radv_GetFenceFdKHR(VkDevice _device,
4521 const VkFenceGetFdInfoKHR *pGetFdInfo,
4522 int *pFd)
4523 {
4524 RADV_FROM_HANDLE(radv_device, device, _device);
4525 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4526 int ret;
4527 uint32_t syncobj_handle;
4528
4529 if (fence->temp_syncobj)
4530 syncobj_handle = fence->temp_syncobj;
4531 else
4532 syncobj_handle = fence->syncobj;
4533
4534 switch(pGetFdInfo->handleType) {
4535 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4536 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4537 break;
4538 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4539 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4540 if (!ret) {
4541 if (fence->temp_syncobj) {
4542 close (fence->temp_syncobj);
4543 fence->temp_syncobj = 0;
4544 } else {
4545 device->ws->reset_syncobj(device->ws, syncobj_handle);
4546 }
4547 }
4548 break;
4549 default:
4550 unreachable("Unhandled fence handle type");
4551 }
4552
4553 if (ret)
4554 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4555 return VK_SUCCESS;
4556 }
4557
4558 void radv_GetPhysicalDeviceExternalFenceProperties(
4559 VkPhysicalDevice physicalDevice,
4560 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4561 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4562 {
4563 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4564
4565 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4566 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4567 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4568 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4569 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4570 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4571 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4572 } else {
4573 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4574 pExternalFenceProperties->compatibleHandleTypes = 0;
4575 pExternalFenceProperties->externalFenceFeatures = 0;
4576 }
4577 }
4578
4579 VkResult
4580 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4581 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4582 const VkAllocationCallbacks* pAllocator,
4583 VkDebugReportCallbackEXT* pCallback)
4584 {
4585 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4586 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4587 pCreateInfo, pAllocator, &instance->alloc,
4588 pCallback);
4589 }
4590
4591 void
4592 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4593 VkDebugReportCallbackEXT _callback,
4594 const VkAllocationCallbacks* pAllocator)
4595 {
4596 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4597 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4598 _callback, pAllocator, &instance->alloc);
4599 }
4600
4601 void
4602 radv_DebugReportMessageEXT(VkInstance _instance,
4603 VkDebugReportFlagsEXT flags,
4604 VkDebugReportObjectTypeEXT objectType,
4605 uint64_t object,
4606 size_t location,
4607 int32_t messageCode,
4608 const char* pLayerPrefix,
4609 const char* pMessage)
4610 {
4611 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4612 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4613 object, location, messageCode, pLayerPrefix, pMessage);
4614 }
4615
4616 void
4617 radv_GetDeviceGroupPeerMemoryFeatures(
4618 VkDevice device,
4619 uint32_t heapIndex,
4620 uint32_t localDeviceIndex,
4621 uint32_t remoteDeviceIndex,
4622 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4623 {
4624 assert(localDeviceIndex == remoteDeviceIndex);
4625
4626 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4627 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4628 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4629 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4630 }