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radv: enable VK_KHR_16bit_storage extension / 16bit storage features
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 }
484 }
485
486 static int radv_get_instance_extension_index(const char *name)
487 {
488 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
489 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
490 return i;
491 }
492 return -1;
493 }
494
495
496 VkResult radv_CreateInstance(
497 const VkInstanceCreateInfo* pCreateInfo,
498 const VkAllocationCallbacks* pAllocator,
499 VkInstance* pInstance)
500 {
501 struct radv_instance *instance;
502 VkResult result;
503
504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
505
506 uint32_t client_version;
507 if (pCreateInfo->pApplicationInfo &&
508 pCreateInfo->pApplicationInfo->apiVersion != 0) {
509 client_version = pCreateInfo->pApplicationInfo->apiVersion;
510 } else {
511 radv_EnumerateInstanceVersion(&client_version);
512 }
513
514 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
515 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
516 if (!instance)
517 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
518
519 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
520
521 if (pAllocator)
522 instance->alloc = *pAllocator;
523 else
524 instance->alloc = default_alloc;
525
526 instance->apiVersion = client_version;
527 instance->physicalDeviceCount = -1;
528
529 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
530 radv_debug_options);
531
532 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
533 radv_perftest_options);
534
535
536 if (instance->debug_flags & RADV_DEBUG_STARTUP)
537 radv_logi("Created an instance");
538
539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
541 int index = radv_get_instance_extension_index(ext_name);
542
543 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
544 vk_free2(&default_alloc, pAllocator, instance);
545 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
546 }
547
548 instance->enabled_extensions.extensions[index] = true;
549 }
550
551 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
552 if (result != VK_SUCCESS) {
553 vk_free2(&default_alloc, pAllocator, instance);
554 return vk_error(instance, result);
555 }
556
557 _mesa_locale_init();
558
559 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
560
561 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
562
563 *pInstance = radv_instance_to_handle(instance);
564
565 return VK_SUCCESS;
566 }
567
568 void radv_DestroyInstance(
569 VkInstance _instance,
570 const VkAllocationCallbacks* pAllocator)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573
574 if (!instance)
575 return;
576
577 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
578 radv_physical_device_finish(instance->physicalDevices + i);
579 }
580
581 VG(VALGRIND_DESTROY_MEMPOOL(instance));
582
583 _mesa_locale_fini();
584
585 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
586
587 vk_free(&instance->alloc, instance);
588 }
589
590 static VkResult
591 radv_enumerate_devices(struct radv_instance *instance)
592 {
593 /* TODO: Check for more devices ? */
594 drmDevicePtr devices[8];
595 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
596 int max_devices;
597
598 instance->physicalDeviceCount = 0;
599
600 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Found %d drm nodes", max_devices);
604
605 if (max_devices < 1)
606 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
607
608 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
609 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
610 devices[i]->bustype == DRM_BUS_PCI &&
611 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
612
613 result = radv_physical_device_init(instance->physicalDevices +
614 instance->physicalDeviceCount,
615 instance,
616 devices[i]);
617 if (result == VK_SUCCESS)
618 ++instance->physicalDeviceCount;
619 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 break;
621 }
622 }
623 drmFreeDevices(devices, max_devices);
624
625 return result;
626 }
627
628 VkResult radv_EnumeratePhysicalDevices(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceCount,
631 VkPhysicalDevice* pPhysicalDevices)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDevices) {
644 *pPhysicalDeviceCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
648 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
649 }
650
651 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
652 : VK_SUCCESS;
653 }
654
655 VkResult radv_EnumeratePhysicalDeviceGroups(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceGroupCount,
658 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDeviceGroupProperties) {
671 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
675 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
676 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
678 }
679 }
680 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
681 : VK_SUCCESS;
682 }
683
684 void radv_GetPhysicalDeviceFeatures(
685 VkPhysicalDevice physicalDevice,
686 VkPhysicalDeviceFeatures* pFeatures)
687 {
688 memset(pFeatures, 0, sizeof(*pFeatures));
689
690 *pFeatures = (VkPhysicalDeviceFeatures) {
691 .robustBufferAccess = true,
692 .fullDrawIndexUint32 = true,
693 .imageCubeArray = true,
694 .independentBlend = true,
695 .geometryShader = true,
696 .tessellationShader = true,
697 .sampleRateShading = true,
698 .dualSrcBlend = true,
699 .logicOp = true,
700 .multiDrawIndirect = true,
701 .drawIndirectFirstInstance = true,
702 .depthClamp = true,
703 .depthBiasClamp = true,
704 .fillModeNonSolid = true,
705 .depthBounds = true,
706 .wideLines = true,
707 .largePoints = true,
708 .alphaToOne = true,
709 .multiViewport = true,
710 .samplerAnisotropy = true,
711 .textureCompressionETC2 = false,
712 .textureCompressionASTC_LDR = false,
713 .textureCompressionBC = true,
714 .occlusionQueryPrecise = true,
715 .pipelineStatisticsQuery = true,
716 .vertexPipelineStoresAndAtomics = true,
717 .fragmentStoresAndAtomics = true,
718 .shaderTessellationAndGeometryPointSize = true,
719 .shaderImageGatherExtended = true,
720 .shaderStorageImageExtendedFormats = true,
721 .shaderStorageImageMultisample = false,
722 .shaderUniformBufferArrayDynamicIndexing = true,
723 .shaderSampledImageArrayDynamicIndexing = true,
724 .shaderStorageBufferArrayDynamicIndexing = true,
725 .shaderStorageImageArrayDynamicIndexing = true,
726 .shaderStorageImageReadWithoutFormat = true,
727 .shaderStorageImageWriteWithoutFormat = true,
728 .shaderClipDistance = true,
729 .shaderCullDistance = true,
730 .shaderFloat64 = true,
731 .shaderInt64 = true,
732 .shaderInt16 = false,
733 .sparseBinding = true,
734 .variableMultisampleRate = true,
735 .inheritedQueries = true,
736 };
737 }
738
739 void radv_GetPhysicalDeviceFeatures2(
740 VkPhysicalDevice physicalDevice,
741 VkPhysicalDeviceFeatures2KHR *pFeatures)
742 {
743 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
744 vk_foreach_struct(ext, pFeatures->pNext) {
745 switch (ext->sType) {
746 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
747 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
748 features->variablePointersStorageBuffer = true;
749 features->variablePointers = false;
750 break;
751 }
752 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
753 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
754 features->multiview = true;
755 features->multiviewGeometryShader = true;
756 features->multiviewTessellationShader = true;
757 break;
758 }
759 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
760 VkPhysicalDeviceShaderDrawParameterFeatures *features =
761 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
762 features->shaderDrawParameters = true;
763 break;
764 }
765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
766 VkPhysicalDeviceProtectedMemoryFeatures *features =
767 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
768 features->protectedMemory = false;
769 break;
770 }
771 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
772 VkPhysicalDevice16BitStorageFeatures *features =
773 (VkPhysicalDevice16BitStorageFeatures*)ext;
774 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
775 features->storageBuffer16BitAccess = enabled;
776 features->uniformAndStorageBuffer16BitAccess = enabled;
777 features->storagePushConstant16 = enabled;
778 features->storageInputOutput16 = enabled;
779 break;
780 }
781 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
782 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
783 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
784 features->samplerYcbcrConversion = false;
785 break;
786 }
787 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
788 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
789 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
790 features->shaderInputAttachmentArrayDynamicIndexing = true;
791 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
792 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
793 features->shaderUniformBufferArrayNonUniformIndexing = false;
794 features->shaderSampledImageArrayNonUniformIndexing = false;
795 features->shaderStorageBufferArrayNonUniformIndexing = false;
796 features->shaderStorageImageArrayNonUniformIndexing = false;
797 features->shaderInputAttachmentArrayNonUniformIndexing = false;
798 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
799 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
800 features->descriptorBindingUniformBufferUpdateAfterBind = true;
801 features->descriptorBindingSampledImageUpdateAfterBind = true;
802 features->descriptorBindingStorageImageUpdateAfterBind = true;
803 features->descriptorBindingStorageBufferUpdateAfterBind = true;
804 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
805 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
806 features->descriptorBindingUpdateUnusedWhilePending = true;
807 features->descriptorBindingPartiallyBound = true;
808 features->descriptorBindingVariableDescriptorCount = true;
809 features->runtimeDescriptorArray = true;
810 break;
811 }
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
813 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
814 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
815 features->conditionalRendering = true;
816 features->inheritedConditionalRendering = false;
817 break;
818 }
819 default:
820 break;
821 }
822 }
823 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
824 }
825
826 void radv_GetPhysicalDeviceProperties(
827 VkPhysicalDevice physicalDevice,
828 VkPhysicalDeviceProperties* pProperties)
829 {
830 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
831 VkSampleCountFlags sample_counts = 0xf;
832
833 /* make sure that the entire descriptor set is addressable with a signed
834 * 32-bit int. So the sum of all limits scaled by descriptor size has to
835 * be at most 2 GiB. the combined image & samples object count as one of
836 * both. This limit is for the pipeline layout, not for the set layout, but
837 * there is no set limit, so we just set a pipeline limit. I don't think
838 * any app is going to hit this soon. */
839 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
840 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
841 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
842 32 /* sampler, largest when combined with image */ +
843 64 /* sampled image */ +
844 64 /* storage image */);
845
846 VkPhysicalDeviceLimits limits = {
847 .maxImageDimension1D = (1 << 14),
848 .maxImageDimension2D = (1 << 14),
849 .maxImageDimension3D = (1 << 11),
850 .maxImageDimensionCube = (1 << 14),
851 .maxImageArrayLayers = (1 << 11),
852 .maxTexelBufferElements = 128 * 1024 * 1024,
853 .maxUniformBufferRange = UINT32_MAX,
854 .maxStorageBufferRange = UINT32_MAX,
855 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
856 .maxMemoryAllocationCount = UINT32_MAX,
857 .maxSamplerAllocationCount = 64 * 1024,
858 .bufferImageGranularity = 64, /* A cache line */
859 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
860 .maxBoundDescriptorSets = MAX_SETS,
861 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
862 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
863 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
864 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
865 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
866 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
867 .maxPerStageResources = max_descriptor_set_size,
868 .maxDescriptorSetSamplers = max_descriptor_set_size,
869 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
870 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
871 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
872 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
873 .maxDescriptorSetSampledImages = max_descriptor_set_size,
874 .maxDescriptorSetStorageImages = max_descriptor_set_size,
875 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
876 .maxVertexInputAttributes = 32,
877 .maxVertexInputBindings = 32,
878 .maxVertexInputAttributeOffset = 2047,
879 .maxVertexInputBindingStride = 2048,
880 .maxVertexOutputComponents = 128,
881 .maxTessellationGenerationLevel = 64,
882 .maxTessellationPatchSize = 32,
883 .maxTessellationControlPerVertexInputComponents = 128,
884 .maxTessellationControlPerVertexOutputComponents = 128,
885 .maxTessellationControlPerPatchOutputComponents = 120,
886 .maxTessellationControlTotalOutputComponents = 4096,
887 .maxTessellationEvaluationInputComponents = 128,
888 .maxTessellationEvaluationOutputComponents = 128,
889 .maxGeometryShaderInvocations = 127,
890 .maxGeometryInputComponents = 64,
891 .maxGeometryOutputComponents = 128,
892 .maxGeometryOutputVertices = 256,
893 .maxGeometryTotalOutputComponents = 1024,
894 .maxFragmentInputComponents = 128,
895 .maxFragmentOutputAttachments = 8,
896 .maxFragmentDualSrcAttachments = 1,
897 .maxFragmentCombinedOutputResources = 8,
898 .maxComputeSharedMemorySize = 32768,
899 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
900 .maxComputeWorkGroupInvocations = 2048,
901 .maxComputeWorkGroupSize = {
902 2048,
903 2048,
904 2048
905 },
906 .subPixelPrecisionBits = 4 /* FIXME */,
907 .subTexelPrecisionBits = 4 /* FIXME */,
908 .mipmapPrecisionBits = 4 /* FIXME */,
909 .maxDrawIndexedIndexValue = UINT32_MAX,
910 .maxDrawIndirectCount = UINT32_MAX,
911 .maxSamplerLodBias = 16,
912 .maxSamplerAnisotropy = 16,
913 .maxViewports = MAX_VIEWPORTS,
914 .maxViewportDimensions = { (1 << 14), (1 << 14) },
915 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
916 .viewportSubPixelBits = 8,
917 .minMemoryMapAlignment = 4096, /* A page */
918 .minTexelBufferOffsetAlignment = 1,
919 .minUniformBufferOffsetAlignment = 4,
920 .minStorageBufferOffsetAlignment = 4,
921 .minTexelOffset = -32,
922 .maxTexelOffset = 31,
923 .minTexelGatherOffset = -32,
924 .maxTexelGatherOffset = 31,
925 .minInterpolationOffset = -2,
926 .maxInterpolationOffset = 2,
927 .subPixelInterpolationOffsetBits = 8,
928 .maxFramebufferWidth = (1 << 14),
929 .maxFramebufferHeight = (1 << 14),
930 .maxFramebufferLayers = (1 << 10),
931 .framebufferColorSampleCounts = sample_counts,
932 .framebufferDepthSampleCounts = sample_counts,
933 .framebufferStencilSampleCounts = sample_counts,
934 .framebufferNoAttachmentsSampleCounts = sample_counts,
935 .maxColorAttachments = MAX_RTS,
936 .sampledImageColorSampleCounts = sample_counts,
937 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
938 .sampledImageDepthSampleCounts = sample_counts,
939 .sampledImageStencilSampleCounts = sample_counts,
940 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
941 .maxSampleMaskWords = 1,
942 .timestampComputeAndGraphics = true,
943 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
944 .maxClipDistances = 8,
945 .maxCullDistances = 8,
946 .maxCombinedClipAndCullDistances = 8,
947 .discreteQueuePriorities = 1,
948 .pointSizeRange = { 0.125, 255.875 },
949 .lineWidthRange = { 0.0, 7.9921875 },
950 .pointSizeGranularity = (1.0 / 8.0),
951 .lineWidthGranularity = (1.0 / 128.0),
952 .strictLines = false, /* FINISHME */
953 .standardSampleLocations = true,
954 .optimalBufferCopyOffsetAlignment = 128,
955 .optimalBufferCopyRowPitchAlignment = 128,
956 .nonCoherentAtomSize = 64,
957 };
958
959 *pProperties = (VkPhysicalDeviceProperties) {
960 .apiVersion = radv_physical_device_api_version(pdevice),
961 .driverVersion = vk_get_driver_version(),
962 .vendorID = ATI_VENDOR_ID,
963 .deviceID = pdevice->rad_info.pci_id,
964 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
965 .limits = limits,
966 .sparseProperties = {0},
967 };
968
969 strcpy(pProperties->deviceName, pdevice->name);
970 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
971 }
972
973 void radv_GetPhysicalDeviceProperties2(
974 VkPhysicalDevice physicalDevice,
975 VkPhysicalDeviceProperties2KHR *pProperties)
976 {
977 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
978 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
979
980 vk_foreach_struct(ext, pProperties->pNext) {
981 switch (ext->sType) {
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
983 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
984 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
985 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
986 break;
987 }
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
989 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
990 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
991 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
992 properties->deviceLUIDValid = false;
993 break;
994 }
995 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
996 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
997 properties->maxMultiviewViewCount = MAX_VIEWS;
998 properties->maxMultiviewInstanceIndex = INT_MAX;
999 break;
1000 }
1001 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1002 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1003 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1004 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1005 break;
1006 }
1007 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1008 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1009 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1010 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1011 break;
1012 }
1013 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1014 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1015 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1016 properties->minImportedHostPointerAlignment = 4096;
1017 break;
1018 }
1019 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1020 VkPhysicalDeviceSubgroupProperties *properties =
1021 (VkPhysicalDeviceSubgroupProperties*)ext;
1022 properties->subgroupSize = 64;
1023 properties->supportedStages = VK_SHADER_STAGE_ALL;
1024 properties->supportedOperations =
1025 VK_SUBGROUP_FEATURE_BASIC_BIT |
1026 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1027 VK_SUBGROUP_FEATURE_QUAD_BIT |
1028 VK_SUBGROUP_FEATURE_VOTE_BIT;
1029 if (pdevice->rad_info.chip_class >= VI) {
1030 properties->supportedOperations |=
1031 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1032 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1033 }
1034 properties->quadOperationsInAllStages = true;
1035 break;
1036 }
1037 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1038 VkPhysicalDeviceMaintenance3Properties *properties =
1039 (VkPhysicalDeviceMaintenance3Properties*)ext;
1040 /* Make sure everything is addressable by a signed 32-bit int, and
1041 * our largest descriptors are 96 bytes. */
1042 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1043 /* Our buffer size fields allow only this much */
1044 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1045 break;
1046 }
1047 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1048 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1049 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1050 /* GFX6-8 only support single channel min/max filter. */
1051 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1052 properties->filterMinmaxSingleComponentFormats = true;
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1056 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1057 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1058
1059 /* Shader engines. */
1060 properties->shaderEngineCount =
1061 pdevice->rad_info.max_se;
1062 properties->shaderArraysPerEngineCount =
1063 pdevice->rad_info.max_sh_per_se;
1064 properties->computeUnitsPerShaderArray =
1065 pdevice->rad_info.num_good_compute_units /
1066 (pdevice->rad_info.max_se *
1067 pdevice->rad_info.max_sh_per_se);
1068 properties->simdPerComputeUnit = 4;
1069 properties->wavefrontsPerSimd =
1070 pdevice->rad_info.family == CHIP_TONGA ||
1071 pdevice->rad_info.family == CHIP_ICELAND ||
1072 pdevice->rad_info.family == CHIP_POLARIS10 ||
1073 pdevice->rad_info.family == CHIP_POLARIS11 ||
1074 pdevice->rad_info.family == CHIP_POLARIS12 ||
1075 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1076 properties->wavefrontSize = 64;
1077
1078 /* SGPR. */
1079 properties->sgprsPerSimd =
1080 radv_get_num_physical_sgprs(pdevice);
1081 properties->minSgprAllocation =
1082 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1083 properties->maxSgprAllocation =
1084 pdevice->rad_info.family == CHIP_TONGA ||
1085 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1086 properties->sgprAllocationGranularity =
1087 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1088
1089 /* VGPR. */
1090 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1091 properties->minVgprAllocation = 4;
1092 properties->maxVgprAllocation = 256;
1093 properties->vgprAllocationGranularity = 4;
1094 break;
1095 }
1096 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1097 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1098 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1099 properties->maxVertexAttribDivisor = UINT32_MAX;
1100 break;
1101 }
1102 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1103 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1104 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1105 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1106 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1107 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1108 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1109 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1110 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1111 properties->robustBufferAccessUpdateAfterBind = false;
1112 properties->quadDivergentImplicitLod = false;
1113
1114 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1115 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1116 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1117 32 /* sampler, largest when combined with image */ +
1118 64 /* sampled image */ +
1119 64 /* storage image */);
1120 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1121 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1122 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1123 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1124 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1125 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1126 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1127 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1128 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1129 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1130 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1131 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1132 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1133 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1134 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1135 break;
1136 }
1137 default:
1138 break;
1139 }
1140 }
1141 }
1142
1143 static void radv_get_physical_device_queue_family_properties(
1144 struct radv_physical_device* pdevice,
1145 uint32_t* pCount,
1146 VkQueueFamilyProperties** pQueueFamilyProperties)
1147 {
1148 int num_queue_families = 1;
1149 int idx;
1150 if (pdevice->rad_info.num_compute_rings > 0 &&
1151 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1152 num_queue_families++;
1153
1154 if (pQueueFamilyProperties == NULL) {
1155 *pCount = num_queue_families;
1156 return;
1157 }
1158
1159 if (!*pCount)
1160 return;
1161
1162 idx = 0;
1163 if (*pCount >= 1) {
1164 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1165 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1166 VK_QUEUE_COMPUTE_BIT |
1167 VK_QUEUE_TRANSFER_BIT |
1168 VK_QUEUE_SPARSE_BINDING_BIT,
1169 .queueCount = 1,
1170 .timestampValidBits = 64,
1171 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1172 };
1173 idx++;
1174 }
1175
1176 if (pdevice->rad_info.num_compute_rings > 0 &&
1177 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1178 if (*pCount > idx) {
1179 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1180 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1181 VK_QUEUE_TRANSFER_BIT |
1182 VK_QUEUE_SPARSE_BINDING_BIT,
1183 .queueCount = pdevice->rad_info.num_compute_rings,
1184 .timestampValidBits = 64,
1185 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1186 };
1187 idx++;
1188 }
1189 }
1190 *pCount = idx;
1191 }
1192
1193 void radv_GetPhysicalDeviceQueueFamilyProperties(
1194 VkPhysicalDevice physicalDevice,
1195 uint32_t* pCount,
1196 VkQueueFamilyProperties* pQueueFamilyProperties)
1197 {
1198 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1199 if (!pQueueFamilyProperties) {
1200 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1201 return;
1202 }
1203 VkQueueFamilyProperties *properties[] = {
1204 pQueueFamilyProperties + 0,
1205 pQueueFamilyProperties + 1,
1206 pQueueFamilyProperties + 2,
1207 };
1208 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1209 assert(*pCount <= 3);
1210 }
1211
1212 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1213 VkPhysicalDevice physicalDevice,
1214 uint32_t* pCount,
1215 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1216 {
1217 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1218 if (!pQueueFamilyProperties) {
1219 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1220 return;
1221 }
1222 VkQueueFamilyProperties *properties[] = {
1223 &pQueueFamilyProperties[0].queueFamilyProperties,
1224 &pQueueFamilyProperties[1].queueFamilyProperties,
1225 &pQueueFamilyProperties[2].queueFamilyProperties,
1226 };
1227 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1228 assert(*pCount <= 3);
1229 }
1230
1231 void radv_GetPhysicalDeviceMemoryProperties(
1232 VkPhysicalDevice physicalDevice,
1233 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1234 {
1235 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1236
1237 *pMemoryProperties = physical_device->memory_properties;
1238 }
1239
1240 void radv_GetPhysicalDeviceMemoryProperties2(
1241 VkPhysicalDevice physicalDevice,
1242 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1243 {
1244 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1245 &pMemoryProperties->memoryProperties);
1246 }
1247
1248 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1249 VkDevice _device,
1250 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1251 const void *pHostPointer,
1252 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1253 {
1254 RADV_FROM_HANDLE(radv_device, device, _device);
1255
1256 switch (handleType)
1257 {
1258 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1259 const struct radv_physical_device *physical_device = device->physical_device;
1260 uint32_t memoryTypeBits = 0;
1261 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1262 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1263 memoryTypeBits = (1 << i);
1264 break;
1265 }
1266 }
1267 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1268 return VK_SUCCESS;
1269 }
1270 default:
1271 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1272 }
1273 }
1274
1275 static enum radeon_ctx_priority
1276 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1277 {
1278 /* Default to MEDIUM when a specific global priority isn't requested */
1279 if (!pObj)
1280 return RADEON_CTX_PRIORITY_MEDIUM;
1281
1282 switch(pObj->globalPriority) {
1283 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1284 return RADEON_CTX_PRIORITY_REALTIME;
1285 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1286 return RADEON_CTX_PRIORITY_HIGH;
1287 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1288 return RADEON_CTX_PRIORITY_MEDIUM;
1289 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1290 return RADEON_CTX_PRIORITY_LOW;
1291 default:
1292 unreachable("Illegal global priority value");
1293 return RADEON_CTX_PRIORITY_INVALID;
1294 }
1295 }
1296
1297 static int
1298 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1299 uint32_t queue_family_index, int idx,
1300 VkDeviceQueueCreateFlags flags,
1301 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1302 {
1303 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1304 queue->device = device;
1305 queue->queue_family_index = queue_family_index;
1306 queue->queue_idx = idx;
1307 queue->priority = radv_get_queue_global_priority(global_priority);
1308 queue->flags = flags;
1309
1310 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1311 if (!queue->hw_ctx)
1312 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1313
1314 return VK_SUCCESS;
1315 }
1316
1317 static void
1318 radv_queue_finish(struct radv_queue *queue)
1319 {
1320 if (queue->hw_ctx)
1321 queue->device->ws->ctx_destroy(queue->hw_ctx);
1322
1323 if (queue->initial_full_flush_preamble_cs)
1324 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1325 if (queue->initial_preamble_cs)
1326 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1327 if (queue->continue_preamble_cs)
1328 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1329 if (queue->descriptor_bo)
1330 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1331 if (queue->scratch_bo)
1332 queue->device->ws->buffer_destroy(queue->scratch_bo);
1333 if (queue->esgs_ring_bo)
1334 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1335 if (queue->gsvs_ring_bo)
1336 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1337 if (queue->tess_rings_bo)
1338 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1339 if (queue->compute_scratch_bo)
1340 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1341 }
1342
1343 static void
1344 radv_bo_list_init(struct radv_bo_list *bo_list)
1345 {
1346 pthread_mutex_init(&bo_list->mutex, NULL);
1347 bo_list->list.count = bo_list->capacity = 0;
1348 bo_list->list.bos = NULL;
1349 }
1350
1351 static void
1352 radv_bo_list_finish(struct radv_bo_list *bo_list)
1353 {
1354 free(bo_list->list.bos);
1355 pthread_mutex_destroy(&bo_list->mutex);
1356 }
1357
1358 static VkResult radv_bo_list_add(struct radv_device *device,
1359 struct radeon_winsys_bo *bo)
1360 {
1361 struct radv_bo_list *bo_list = &device->bo_list;
1362
1363 if (unlikely(!device->use_global_bo_list))
1364 return VK_SUCCESS;
1365
1366 pthread_mutex_lock(&bo_list->mutex);
1367 if (bo_list->list.count == bo_list->capacity) {
1368 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1369 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1370
1371 if (!data) {
1372 pthread_mutex_unlock(&bo_list->mutex);
1373 return VK_ERROR_OUT_OF_HOST_MEMORY;
1374 }
1375
1376 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1377 bo_list->capacity = capacity;
1378 }
1379
1380 bo_list->list.bos[bo_list->list.count++] = bo;
1381 pthread_mutex_unlock(&bo_list->mutex);
1382 return VK_SUCCESS;
1383 }
1384
1385 static void radv_bo_list_remove(struct radv_device *device,
1386 struct radeon_winsys_bo *bo)
1387 {
1388 struct radv_bo_list *bo_list = &device->bo_list;
1389
1390 if (unlikely(!device->use_global_bo_list))
1391 return;
1392
1393 pthread_mutex_lock(&bo_list->mutex);
1394 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1395 if (bo_list->list.bos[i] == bo) {
1396 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1397 --bo_list->list.count;
1398 break;
1399 }
1400 }
1401 pthread_mutex_unlock(&bo_list->mutex);
1402 }
1403
1404 static void
1405 radv_device_init_gs_info(struct radv_device *device)
1406 {
1407 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1408 device->physical_device->rad_info.family);
1409 }
1410
1411 static int radv_get_device_extension_index(const char *name)
1412 {
1413 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1414 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1415 return i;
1416 }
1417 return -1;
1418 }
1419
1420 VkResult radv_CreateDevice(
1421 VkPhysicalDevice physicalDevice,
1422 const VkDeviceCreateInfo* pCreateInfo,
1423 const VkAllocationCallbacks* pAllocator,
1424 VkDevice* pDevice)
1425 {
1426 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1427 VkResult result;
1428 struct radv_device *device;
1429
1430 bool keep_shader_info = false;
1431
1432 /* Check enabled features */
1433 if (pCreateInfo->pEnabledFeatures) {
1434 VkPhysicalDeviceFeatures supported_features;
1435 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1436 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1437 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1438 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1439 for (uint32_t i = 0; i < num_features; i++) {
1440 if (enabled_feature[i] && !supported_feature[i])
1441 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1442 }
1443 }
1444
1445 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1446 sizeof(*device), 8,
1447 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1448 if (!device)
1449 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1450
1451 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1452 device->instance = physical_device->instance;
1453 device->physical_device = physical_device;
1454
1455 device->ws = physical_device->ws;
1456 if (pAllocator)
1457 device->alloc = *pAllocator;
1458 else
1459 device->alloc = physical_device->instance->alloc;
1460
1461 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1462 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1463 int index = radv_get_device_extension_index(ext_name);
1464 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1465 vk_free(&device->alloc, device);
1466 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1467 }
1468
1469 device->enabled_extensions.extensions[index] = true;
1470 }
1471
1472 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1473
1474 /* With update after bind we can't attach bo's to the command buffer
1475 * from the descriptor set anymore, so we have to use a global BO list.
1476 */
1477 device->use_global_bo_list =
1478 device->enabled_extensions.EXT_descriptor_indexing;
1479
1480 mtx_init(&device->shader_slab_mutex, mtx_plain);
1481 list_inithead(&device->shader_slabs);
1482
1483 radv_bo_list_init(&device->bo_list);
1484
1485 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1486 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1487 uint32_t qfi = queue_create->queueFamilyIndex;
1488 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1489 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1490
1491 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1492
1493 device->queues[qfi] = vk_alloc(&device->alloc,
1494 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1495 if (!device->queues[qfi]) {
1496 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1497 goto fail;
1498 }
1499
1500 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1501
1502 device->queue_count[qfi] = queue_create->queueCount;
1503
1504 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1505 result = radv_queue_init(device, &device->queues[qfi][q],
1506 qfi, q, queue_create->flags,
1507 global_priority);
1508 if (result != VK_SUCCESS)
1509 goto fail;
1510 }
1511 }
1512
1513 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1514 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1515 device->physical_device->rad_info.family == CHIP_RAVEN);
1516
1517 /* Disabled and not implemented for now. */
1518 device->dfsm_allowed = device->pbb_allowed &&
1519 device->physical_device->rad_info.family == CHIP_RAVEN;
1520
1521 #ifdef ANDROID
1522 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1523 #endif
1524
1525 /* The maximum number of scratch waves. Scratch space isn't divided
1526 * evenly between CUs. The number is only a function of the number of CUs.
1527 * We can decrease the constant to decrease the scratch buffer size.
1528 *
1529 * sctx->scratch_waves must be >= the maximum possible size of
1530 * 1 threadgroup, so that the hw doesn't hang from being unable
1531 * to start any.
1532 *
1533 * The recommended value is 4 per CU at most. Higher numbers don't
1534 * bring much benefit, but they still occupy chip resources (think
1535 * async compute). I've seen ~2% performance difference between 4 and 32.
1536 */
1537 uint32_t max_threads_per_block = 2048;
1538 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1539 max_threads_per_block / 64);
1540
1541 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1542
1543 if (device->physical_device->rad_info.chip_class >= CIK) {
1544 /* If the KMD allows it (there is a KMD hw register for it),
1545 * allow launching waves out-of-order.
1546 */
1547 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1548 }
1549
1550 radv_device_init_gs_info(device);
1551
1552 device->tess_offchip_block_dw_size =
1553 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1554 device->has_distributed_tess =
1555 device->physical_device->rad_info.chip_class >= VI &&
1556 device->physical_device->rad_info.max_se >= 2;
1557
1558 if (getenv("RADV_TRACE_FILE")) {
1559 const char *filename = getenv("RADV_TRACE_FILE");
1560
1561 keep_shader_info = true;
1562
1563 if (!radv_init_trace(device))
1564 goto fail;
1565
1566 fprintf(stderr, "*****************************************************************************\n");
1567 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1568 fprintf(stderr, "*****************************************************************************\n");
1569
1570 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1571 radv_dump_enabled_options(device, stderr);
1572 }
1573
1574 device->keep_shader_info = keep_shader_info;
1575
1576 result = radv_device_init_meta(device);
1577 if (result != VK_SUCCESS)
1578 goto fail;
1579
1580 radv_device_init_msaa(device);
1581
1582 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1583 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1584 switch (family) {
1585 case RADV_QUEUE_GENERAL:
1586 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1587 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1588 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1589 break;
1590 case RADV_QUEUE_COMPUTE:
1591 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1592 radeon_emit(device->empty_cs[family], 0);
1593 break;
1594 }
1595 device->ws->cs_finalize(device->empty_cs[family]);
1596 }
1597
1598 if (device->physical_device->rad_info.chip_class >= CIK)
1599 cik_create_gfx_config(device);
1600
1601 VkPipelineCacheCreateInfo ci;
1602 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1603 ci.pNext = NULL;
1604 ci.flags = 0;
1605 ci.pInitialData = NULL;
1606 ci.initialDataSize = 0;
1607 VkPipelineCache pc;
1608 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1609 &ci, NULL, &pc);
1610 if (result != VK_SUCCESS)
1611 goto fail_meta;
1612
1613 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1614
1615 *pDevice = radv_device_to_handle(device);
1616 return VK_SUCCESS;
1617
1618 fail_meta:
1619 radv_device_finish_meta(device);
1620 fail:
1621 radv_bo_list_finish(&device->bo_list);
1622
1623 if (device->trace_bo)
1624 device->ws->buffer_destroy(device->trace_bo);
1625
1626 if (device->gfx_init)
1627 device->ws->buffer_destroy(device->gfx_init);
1628
1629 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1630 for (unsigned q = 0; q < device->queue_count[i]; q++)
1631 radv_queue_finish(&device->queues[i][q]);
1632 if (device->queue_count[i])
1633 vk_free(&device->alloc, device->queues[i]);
1634 }
1635
1636 vk_free(&device->alloc, device);
1637 return result;
1638 }
1639
1640 void radv_DestroyDevice(
1641 VkDevice _device,
1642 const VkAllocationCallbacks* pAllocator)
1643 {
1644 RADV_FROM_HANDLE(radv_device, device, _device);
1645
1646 if (!device)
1647 return;
1648
1649 if (device->trace_bo)
1650 device->ws->buffer_destroy(device->trace_bo);
1651
1652 if (device->gfx_init)
1653 device->ws->buffer_destroy(device->gfx_init);
1654
1655 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1656 for (unsigned q = 0; q < device->queue_count[i]; q++)
1657 radv_queue_finish(&device->queues[i][q]);
1658 if (device->queue_count[i])
1659 vk_free(&device->alloc, device->queues[i]);
1660 if (device->empty_cs[i])
1661 device->ws->cs_destroy(device->empty_cs[i]);
1662 }
1663 radv_device_finish_meta(device);
1664
1665 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1666 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1667
1668 radv_destroy_shader_slabs(device);
1669
1670 radv_bo_list_finish(&device->bo_list);
1671 vk_free(&device->alloc, device);
1672 }
1673
1674 VkResult radv_EnumerateInstanceLayerProperties(
1675 uint32_t* pPropertyCount,
1676 VkLayerProperties* pProperties)
1677 {
1678 if (pProperties == NULL) {
1679 *pPropertyCount = 0;
1680 return VK_SUCCESS;
1681 }
1682
1683 /* None supported at this time */
1684 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1685 }
1686
1687 VkResult radv_EnumerateDeviceLayerProperties(
1688 VkPhysicalDevice physicalDevice,
1689 uint32_t* pPropertyCount,
1690 VkLayerProperties* pProperties)
1691 {
1692 if (pProperties == NULL) {
1693 *pPropertyCount = 0;
1694 return VK_SUCCESS;
1695 }
1696
1697 /* None supported at this time */
1698 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1699 }
1700
1701 void radv_GetDeviceQueue2(
1702 VkDevice _device,
1703 const VkDeviceQueueInfo2* pQueueInfo,
1704 VkQueue* pQueue)
1705 {
1706 RADV_FROM_HANDLE(radv_device, device, _device);
1707 struct radv_queue *queue;
1708
1709 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1710 if (pQueueInfo->flags != queue->flags) {
1711 /* From the Vulkan 1.1.70 spec:
1712 *
1713 * "The queue returned by vkGetDeviceQueue2 must have the same
1714 * flags value from this structure as that used at device
1715 * creation time in a VkDeviceQueueCreateInfo instance. If no
1716 * matching flags were specified at device creation time then
1717 * pQueue will return VK_NULL_HANDLE."
1718 */
1719 *pQueue = VK_NULL_HANDLE;
1720 return;
1721 }
1722
1723 *pQueue = radv_queue_to_handle(queue);
1724 }
1725
1726 void radv_GetDeviceQueue(
1727 VkDevice _device,
1728 uint32_t queueFamilyIndex,
1729 uint32_t queueIndex,
1730 VkQueue* pQueue)
1731 {
1732 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1733 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1734 .queueFamilyIndex = queueFamilyIndex,
1735 .queueIndex = queueIndex
1736 };
1737
1738 radv_GetDeviceQueue2(_device, &info, pQueue);
1739 }
1740
1741 static void
1742 fill_geom_tess_rings(struct radv_queue *queue,
1743 uint32_t *map,
1744 bool add_sample_positions,
1745 uint32_t esgs_ring_size,
1746 struct radeon_winsys_bo *esgs_ring_bo,
1747 uint32_t gsvs_ring_size,
1748 struct radeon_winsys_bo *gsvs_ring_bo,
1749 uint32_t tess_factor_ring_size,
1750 uint32_t tess_offchip_ring_offset,
1751 uint32_t tess_offchip_ring_size,
1752 struct radeon_winsys_bo *tess_rings_bo)
1753 {
1754 uint64_t esgs_va = 0, gsvs_va = 0;
1755 uint64_t tess_va = 0, tess_offchip_va = 0;
1756 uint32_t *desc = &map[4];
1757
1758 if (esgs_ring_bo)
1759 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1760 if (gsvs_ring_bo)
1761 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1762 if (tess_rings_bo) {
1763 tess_va = radv_buffer_get_va(tess_rings_bo);
1764 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1765 }
1766
1767 /* stride 0, num records - size, add tid, swizzle, elsize4,
1768 index stride 64 */
1769 desc[0] = esgs_va;
1770 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1771 S_008F04_STRIDE(0) |
1772 S_008F04_SWIZZLE_ENABLE(true);
1773 desc[2] = esgs_ring_size;
1774 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1775 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1776 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1777 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1778 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1779 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1780 S_008F0C_ELEMENT_SIZE(1) |
1781 S_008F0C_INDEX_STRIDE(3) |
1782 S_008F0C_ADD_TID_ENABLE(true);
1783
1784 desc += 4;
1785 /* GS entry for ES->GS ring */
1786 /* stride 0, num records - size, elsize0,
1787 index stride 0 */
1788 desc[0] = esgs_va;
1789 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1790 S_008F04_STRIDE(0) |
1791 S_008F04_SWIZZLE_ENABLE(false);
1792 desc[2] = esgs_ring_size;
1793 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1794 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1795 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1796 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1797 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1798 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1799 S_008F0C_ELEMENT_SIZE(0) |
1800 S_008F0C_INDEX_STRIDE(0) |
1801 S_008F0C_ADD_TID_ENABLE(false);
1802
1803 desc += 4;
1804 /* VS entry for GS->VS ring */
1805 /* stride 0, num records - size, elsize0,
1806 index stride 0 */
1807 desc[0] = gsvs_va;
1808 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1809 S_008F04_STRIDE(0) |
1810 S_008F04_SWIZZLE_ENABLE(false);
1811 desc[2] = gsvs_ring_size;
1812 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1813 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1814 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1815 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1816 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1817 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1818 S_008F0C_ELEMENT_SIZE(0) |
1819 S_008F0C_INDEX_STRIDE(0) |
1820 S_008F0C_ADD_TID_ENABLE(false);
1821 desc += 4;
1822
1823 /* stride gsvs_itemsize, num records 64
1824 elsize 4, index stride 16 */
1825 /* shader will patch stride and desc[2] */
1826 desc[0] = gsvs_va;
1827 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1828 S_008F04_STRIDE(0) |
1829 S_008F04_SWIZZLE_ENABLE(true);
1830 desc[2] = 0;
1831 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1832 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1833 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1834 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1835 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1836 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1837 S_008F0C_ELEMENT_SIZE(1) |
1838 S_008F0C_INDEX_STRIDE(1) |
1839 S_008F0C_ADD_TID_ENABLE(true);
1840 desc += 4;
1841
1842 desc[0] = tess_va;
1843 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1844 S_008F04_STRIDE(0) |
1845 S_008F04_SWIZZLE_ENABLE(false);
1846 desc[2] = tess_factor_ring_size;
1847 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1848 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1849 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1850 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1851 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1852 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1853 S_008F0C_ELEMENT_SIZE(0) |
1854 S_008F0C_INDEX_STRIDE(0) |
1855 S_008F0C_ADD_TID_ENABLE(false);
1856 desc += 4;
1857
1858 desc[0] = tess_offchip_va;
1859 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1860 S_008F04_STRIDE(0) |
1861 S_008F04_SWIZZLE_ENABLE(false);
1862 desc[2] = tess_offchip_ring_size;
1863 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1864 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1865 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1866 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1867 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1868 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1869 S_008F0C_ELEMENT_SIZE(0) |
1870 S_008F0C_INDEX_STRIDE(0) |
1871 S_008F0C_ADD_TID_ENABLE(false);
1872 desc += 4;
1873
1874 /* add sample positions after all rings */
1875 memcpy(desc, queue->device->sample_locations_1x, 8);
1876 desc += 2;
1877 memcpy(desc, queue->device->sample_locations_2x, 16);
1878 desc += 4;
1879 memcpy(desc, queue->device->sample_locations_4x, 32);
1880 desc += 8;
1881 memcpy(desc, queue->device->sample_locations_8x, 64);
1882 desc += 16;
1883 memcpy(desc, queue->device->sample_locations_16x, 128);
1884 }
1885
1886 static unsigned
1887 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1888 {
1889 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1890 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1891 device->physical_device->rad_info.family != CHIP_STONEY;
1892 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1893 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1894 device->physical_device->rad_info.max_se;
1895 unsigned offchip_granularity;
1896 unsigned hs_offchip_param;
1897 switch (device->tess_offchip_block_dw_size) {
1898 default:
1899 assert(0);
1900 /* fall through */
1901 case 8192:
1902 offchip_granularity = V_03093C_X_8K_DWORDS;
1903 break;
1904 case 4096:
1905 offchip_granularity = V_03093C_X_4K_DWORDS;
1906 break;
1907 }
1908
1909 switch (device->physical_device->rad_info.chip_class) {
1910 case SI:
1911 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1912 break;
1913 case CIK:
1914 case VI:
1915 case GFX9:
1916 default:
1917 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1918 break;
1919 }
1920
1921 *max_offchip_buffers_p = max_offchip_buffers;
1922 if (device->physical_device->rad_info.chip_class >= CIK) {
1923 if (device->physical_device->rad_info.chip_class >= VI)
1924 --max_offchip_buffers;
1925 hs_offchip_param =
1926 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1927 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1928 } else {
1929 hs_offchip_param =
1930 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1931 }
1932 return hs_offchip_param;
1933 }
1934
1935 static void
1936 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1937 struct radeon_winsys_bo *esgs_ring_bo,
1938 uint32_t esgs_ring_size,
1939 struct radeon_winsys_bo *gsvs_ring_bo,
1940 uint32_t gsvs_ring_size)
1941 {
1942 if (!esgs_ring_bo && !gsvs_ring_bo)
1943 return;
1944
1945 if (esgs_ring_bo)
1946 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1947
1948 if (gsvs_ring_bo)
1949 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1950
1951 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1952 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1953 radeon_emit(cs, esgs_ring_size >> 8);
1954 radeon_emit(cs, gsvs_ring_size >> 8);
1955 } else {
1956 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1957 radeon_emit(cs, esgs_ring_size >> 8);
1958 radeon_emit(cs, gsvs_ring_size >> 8);
1959 }
1960 }
1961
1962 static void
1963 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1964 unsigned hs_offchip_param, unsigned tf_ring_size,
1965 struct radeon_winsys_bo *tess_rings_bo)
1966 {
1967 uint64_t tf_va;
1968
1969 if (!tess_rings_bo)
1970 return;
1971
1972 tf_va = radv_buffer_get_va(tess_rings_bo);
1973
1974 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
1975
1976 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1977 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1978 S_030938_SIZE(tf_ring_size / 4));
1979 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1980 tf_va >> 8);
1981 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1982 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1983 S_030944_BASE_HI(tf_va >> 40));
1984 }
1985 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1986 hs_offchip_param);
1987 } else {
1988 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1989 S_008988_SIZE(tf_ring_size / 4));
1990 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1991 tf_va >> 8);
1992 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1993 hs_offchip_param);
1994 }
1995 }
1996
1997 static void
1998 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1999 struct radeon_winsys_bo *compute_scratch_bo)
2000 {
2001 uint64_t scratch_va;
2002
2003 if (!compute_scratch_bo)
2004 return;
2005
2006 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2007
2008 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2009
2010 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2011 radeon_emit(cs, scratch_va);
2012 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2013 S_008F04_SWIZZLE_ENABLE(1));
2014 }
2015
2016 static void
2017 radv_emit_global_shader_pointers(struct radv_queue *queue,
2018 struct radeon_cmdbuf *cs,
2019 struct radeon_winsys_bo *descriptor_bo)
2020 {
2021 uint64_t va;
2022
2023 if (!descriptor_bo)
2024 return;
2025
2026 va = radv_buffer_get_va(descriptor_bo);
2027
2028 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2029
2030 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2031 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2032 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2033 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2034 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2035
2036 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2037 radv_emit_shader_pointer(queue->device, cs, regs[i],
2038 va, true);
2039 }
2040 } else {
2041 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2042 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2043 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2044 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2045 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2046 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2047
2048 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2049 radv_emit_shader_pointer(queue->device, cs, regs[i],
2050 va, true);
2051 }
2052 }
2053 }
2054
2055 static VkResult
2056 radv_get_preamble_cs(struct radv_queue *queue,
2057 uint32_t scratch_size,
2058 uint32_t compute_scratch_size,
2059 uint32_t esgs_ring_size,
2060 uint32_t gsvs_ring_size,
2061 bool needs_tess_rings,
2062 bool needs_sample_positions,
2063 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2064 struct radeon_cmdbuf **initial_preamble_cs,
2065 struct radeon_cmdbuf **continue_preamble_cs)
2066 {
2067 struct radeon_winsys_bo *scratch_bo = NULL;
2068 struct radeon_winsys_bo *descriptor_bo = NULL;
2069 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2070 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2071 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2072 struct radeon_winsys_bo *tess_rings_bo = NULL;
2073 struct radeon_cmdbuf *dest_cs[3] = {0};
2074 bool add_tess_rings = false, add_sample_positions = false;
2075 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2076 unsigned max_offchip_buffers;
2077 unsigned hs_offchip_param = 0;
2078 unsigned tess_offchip_ring_offset;
2079 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2080 if (!queue->has_tess_rings) {
2081 if (needs_tess_rings)
2082 add_tess_rings = true;
2083 }
2084 if (!queue->has_sample_positions) {
2085 if (needs_sample_positions)
2086 add_sample_positions = true;
2087 }
2088 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2089 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2090 &max_offchip_buffers);
2091 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2092 tess_offchip_ring_size = max_offchip_buffers *
2093 queue->device->tess_offchip_block_dw_size * 4;
2094
2095 if (scratch_size <= queue->scratch_size &&
2096 compute_scratch_size <= queue->compute_scratch_size &&
2097 esgs_ring_size <= queue->esgs_ring_size &&
2098 gsvs_ring_size <= queue->gsvs_ring_size &&
2099 !add_tess_rings && !add_sample_positions &&
2100 queue->initial_preamble_cs) {
2101 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2102 *initial_preamble_cs = queue->initial_preamble_cs;
2103 *continue_preamble_cs = queue->continue_preamble_cs;
2104 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2105 *continue_preamble_cs = NULL;
2106 return VK_SUCCESS;
2107 }
2108
2109 if (scratch_size > queue->scratch_size) {
2110 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2111 scratch_size,
2112 4096,
2113 RADEON_DOMAIN_VRAM,
2114 ring_bo_flags);
2115 if (!scratch_bo)
2116 goto fail;
2117 } else
2118 scratch_bo = queue->scratch_bo;
2119
2120 if (compute_scratch_size > queue->compute_scratch_size) {
2121 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2122 compute_scratch_size,
2123 4096,
2124 RADEON_DOMAIN_VRAM,
2125 ring_bo_flags);
2126 if (!compute_scratch_bo)
2127 goto fail;
2128
2129 } else
2130 compute_scratch_bo = queue->compute_scratch_bo;
2131
2132 if (esgs_ring_size > queue->esgs_ring_size) {
2133 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2134 esgs_ring_size,
2135 4096,
2136 RADEON_DOMAIN_VRAM,
2137 ring_bo_flags);
2138 if (!esgs_ring_bo)
2139 goto fail;
2140 } else {
2141 esgs_ring_bo = queue->esgs_ring_bo;
2142 esgs_ring_size = queue->esgs_ring_size;
2143 }
2144
2145 if (gsvs_ring_size > queue->gsvs_ring_size) {
2146 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2147 gsvs_ring_size,
2148 4096,
2149 RADEON_DOMAIN_VRAM,
2150 ring_bo_flags);
2151 if (!gsvs_ring_bo)
2152 goto fail;
2153 } else {
2154 gsvs_ring_bo = queue->gsvs_ring_bo;
2155 gsvs_ring_size = queue->gsvs_ring_size;
2156 }
2157
2158 if (add_tess_rings) {
2159 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2160 tess_offchip_ring_offset + tess_offchip_ring_size,
2161 256,
2162 RADEON_DOMAIN_VRAM,
2163 ring_bo_flags);
2164 if (!tess_rings_bo)
2165 goto fail;
2166 } else {
2167 tess_rings_bo = queue->tess_rings_bo;
2168 }
2169
2170 if (scratch_bo != queue->scratch_bo ||
2171 esgs_ring_bo != queue->esgs_ring_bo ||
2172 gsvs_ring_bo != queue->gsvs_ring_bo ||
2173 tess_rings_bo != queue->tess_rings_bo ||
2174 add_sample_positions) {
2175 uint32_t size = 0;
2176 if (gsvs_ring_bo || esgs_ring_bo ||
2177 tess_rings_bo || add_sample_positions) {
2178 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2179 if (add_sample_positions)
2180 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2181 }
2182 else if (scratch_bo)
2183 size = 8; /* 2 dword */
2184
2185 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2186 size,
2187 4096,
2188 RADEON_DOMAIN_VRAM,
2189 RADEON_FLAG_CPU_ACCESS |
2190 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2191 RADEON_FLAG_READ_ONLY);
2192 if (!descriptor_bo)
2193 goto fail;
2194 } else
2195 descriptor_bo = queue->descriptor_bo;
2196
2197 for(int i = 0; i < 3; ++i) {
2198 struct radeon_cmdbuf *cs = NULL;
2199 cs = queue->device->ws->cs_create(queue->device->ws,
2200 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2201 if (!cs)
2202 goto fail;
2203
2204 dest_cs[i] = cs;
2205
2206 if (scratch_bo)
2207 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2208
2209 if (descriptor_bo != queue->descriptor_bo) {
2210 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2211
2212 if (scratch_bo) {
2213 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2214 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2215 S_008F04_SWIZZLE_ENABLE(1);
2216 map[0] = scratch_va;
2217 map[1] = rsrc1;
2218 }
2219
2220 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2221 add_sample_positions)
2222 fill_geom_tess_rings(queue, map, add_sample_positions,
2223 esgs_ring_size, esgs_ring_bo,
2224 gsvs_ring_size, gsvs_ring_bo,
2225 tess_factor_ring_size,
2226 tess_offchip_ring_offset,
2227 tess_offchip_ring_size,
2228 tess_rings_bo);
2229
2230 queue->device->ws->buffer_unmap(descriptor_bo);
2231 }
2232
2233 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2234 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2235 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2236 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2237 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2238 }
2239
2240 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2241 gsvs_ring_bo, gsvs_ring_size);
2242 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2243 tess_factor_ring_size, tess_rings_bo);
2244 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2245 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2246
2247 if (i == 0) {
2248 si_cs_emit_cache_flush(cs,
2249 queue->device->physical_device->rad_info.chip_class,
2250 NULL, 0,
2251 queue->queue_family_index == RING_COMPUTE &&
2252 queue->device->physical_device->rad_info.chip_class >= CIK,
2253 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2254 RADV_CMD_FLAG_INV_ICACHE |
2255 RADV_CMD_FLAG_INV_SMEM_L1 |
2256 RADV_CMD_FLAG_INV_VMEM_L1 |
2257 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2258 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2259 } else if (i == 1) {
2260 si_cs_emit_cache_flush(cs,
2261 queue->device->physical_device->rad_info.chip_class,
2262 NULL, 0,
2263 queue->queue_family_index == RING_COMPUTE &&
2264 queue->device->physical_device->rad_info.chip_class >= CIK,
2265 RADV_CMD_FLAG_INV_ICACHE |
2266 RADV_CMD_FLAG_INV_SMEM_L1 |
2267 RADV_CMD_FLAG_INV_VMEM_L1 |
2268 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2269 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2270 }
2271
2272 if (!queue->device->ws->cs_finalize(cs))
2273 goto fail;
2274 }
2275
2276 if (queue->initial_full_flush_preamble_cs)
2277 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2278
2279 if (queue->initial_preamble_cs)
2280 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2281
2282 if (queue->continue_preamble_cs)
2283 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2284
2285 queue->initial_full_flush_preamble_cs = dest_cs[0];
2286 queue->initial_preamble_cs = dest_cs[1];
2287 queue->continue_preamble_cs = dest_cs[2];
2288
2289 if (scratch_bo != queue->scratch_bo) {
2290 if (queue->scratch_bo)
2291 queue->device->ws->buffer_destroy(queue->scratch_bo);
2292 queue->scratch_bo = scratch_bo;
2293 queue->scratch_size = scratch_size;
2294 }
2295
2296 if (compute_scratch_bo != queue->compute_scratch_bo) {
2297 if (queue->compute_scratch_bo)
2298 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2299 queue->compute_scratch_bo = compute_scratch_bo;
2300 queue->compute_scratch_size = compute_scratch_size;
2301 }
2302
2303 if (esgs_ring_bo != queue->esgs_ring_bo) {
2304 if (queue->esgs_ring_bo)
2305 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2306 queue->esgs_ring_bo = esgs_ring_bo;
2307 queue->esgs_ring_size = esgs_ring_size;
2308 }
2309
2310 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2311 if (queue->gsvs_ring_bo)
2312 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2313 queue->gsvs_ring_bo = gsvs_ring_bo;
2314 queue->gsvs_ring_size = gsvs_ring_size;
2315 }
2316
2317 if (tess_rings_bo != queue->tess_rings_bo) {
2318 queue->tess_rings_bo = tess_rings_bo;
2319 queue->has_tess_rings = true;
2320 }
2321
2322 if (descriptor_bo != queue->descriptor_bo) {
2323 if (queue->descriptor_bo)
2324 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2325
2326 queue->descriptor_bo = descriptor_bo;
2327 }
2328
2329 if (add_sample_positions)
2330 queue->has_sample_positions = true;
2331
2332 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2333 *initial_preamble_cs = queue->initial_preamble_cs;
2334 *continue_preamble_cs = queue->continue_preamble_cs;
2335 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2336 *continue_preamble_cs = NULL;
2337 return VK_SUCCESS;
2338 fail:
2339 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2340 if (dest_cs[i])
2341 queue->device->ws->cs_destroy(dest_cs[i]);
2342 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2343 queue->device->ws->buffer_destroy(descriptor_bo);
2344 if (scratch_bo && scratch_bo != queue->scratch_bo)
2345 queue->device->ws->buffer_destroy(scratch_bo);
2346 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2347 queue->device->ws->buffer_destroy(compute_scratch_bo);
2348 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2349 queue->device->ws->buffer_destroy(esgs_ring_bo);
2350 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2351 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2352 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2353 queue->device->ws->buffer_destroy(tess_rings_bo);
2354 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2355 }
2356
2357 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2358 struct radv_winsys_sem_counts *counts,
2359 int num_sems,
2360 const VkSemaphore *sems,
2361 VkFence _fence,
2362 bool reset_temp)
2363 {
2364 int syncobj_idx = 0, sem_idx = 0;
2365
2366 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2367 return VK_SUCCESS;
2368
2369 for (uint32_t i = 0; i < num_sems; i++) {
2370 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2371
2372 if (sem->temp_syncobj || sem->syncobj)
2373 counts->syncobj_count++;
2374 else
2375 counts->sem_count++;
2376 }
2377
2378 if (_fence != VK_NULL_HANDLE) {
2379 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2380 if (fence->temp_syncobj || fence->syncobj)
2381 counts->syncobj_count++;
2382 }
2383
2384 if (counts->syncobj_count) {
2385 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2386 if (!counts->syncobj)
2387 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2388 }
2389
2390 if (counts->sem_count) {
2391 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2392 if (!counts->sem) {
2393 free(counts->syncobj);
2394 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2395 }
2396 }
2397
2398 for (uint32_t i = 0; i < num_sems; i++) {
2399 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2400
2401 if (sem->temp_syncobj) {
2402 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2403 }
2404 else if (sem->syncobj)
2405 counts->syncobj[syncobj_idx++] = sem->syncobj;
2406 else {
2407 assert(sem->sem);
2408 counts->sem[sem_idx++] = sem->sem;
2409 }
2410 }
2411
2412 if (_fence != VK_NULL_HANDLE) {
2413 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2414 if (fence->temp_syncobj)
2415 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2416 else if (fence->syncobj)
2417 counts->syncobj[syncobj_idx++] = fence->syncobj;
2418 }
2419
2420 return VK_SUCCESS;
2421 }
2422
2423 static void
2424 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2425 {
2426 free(sem_info->wait.syncobj);
2427 free(sem_info->wait.sem);
2428 free(sem_info->signal.syncobj);
2429 free(sem_info->signal.sem);
2430 }
2431
2432
2433 static void radv_free_temp_syncobjs(struct radv_device *device,
2434 int num_sems,
2435 const VkSemaphore *sems)
2436 {
2437 for (uint32_t i = 0; i < num_sems; i++) {
2438 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2439
2440 if (sem->temp_syncobj) {
2441 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2442 sem->temp_syncobj = 0;
2443 }
2444 }
2445 }
2446
2447 static VkResult
2448 radv_alloc_sem_info(struct radv_instance *instance,
2449 struct radv_winsys_sem_info *sem_info,
2450 int num_wait_sems,
2451 const VkSemaphore *wait_sems,
2452 int num_signal_sems,
2453 const VkSemaphore *signal_sems,
2454 VkFence fence)
2455 {
2456 VkResult ret;
2457 memset(sem_info, 0, sizeof(*sem_info));
2458
2459 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2460 if (ret)
2461 return ret;
2462 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2463 if (ret)
2464 radv_free_sem_info(sem_info);
2465
2466 /* caller can override these */
2467 sem_info->cs_emit_wait = true;
2468 sem_info->cs_emit_signal = true;
2469 return ret;
2470 }
2471
2472 /* Signals fence as soon as all the work currently put on queue is done. */
2473 static VkResult radv_signal_fence(struct radv_queue *queue,
2474 struct radv_fence *fence)
2475 {
2476 int ret;
2477 VkResult result;
2478 struct radv_winsys_sem_info sem_info;
2479
2480 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2481 radv_fence_to_handle(fence));
2482 if (result != VK_SUCCESS)
2483 return result;
2484
2485 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2486 &queue->device->empty_cs[queue->queue_family_index],
2487 1, NULL, NULL, &sem_info, NULL,
2488 false, fence->fence);
2489 radv_free_sem_info(&sem_info);
2490
2491 if (ret)
2492 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2493
2494 return VK_SUCCESS;
2495 }
2496
2497 VkResult radv_QueueSubmit(
2498 VkQueue _queue,
2499 uint32_t submitCount,
2500 const VkSubmitInfo* pSubmits,
2501 VkFence _fence)
2502 {
2503 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2504 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2505 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2506 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2507 int ret;
2508 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2509 uint32_t scratch_size = 0;
2510 uint32_t compute_scratch_size = 0;
2511 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2512 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2513 VkResult result;
2514 bool fence_emitted = false;
2515 bool tess_rings_needed = false;
2516 bool sample_positions_needed = false;
2517
2518 /* Do this first so failing to allocate scratch buffers can't result in
2519 * partially executed submissions. */
2520 for (uint32_t i = 0; i < submitCount; i++) {
2521 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2522 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2523 pSubmits[i].pCommandBuffers[j]);
2524
2525 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2526 compute_scratch_size = MAX2(compute_scratch_size,
2527 cmd_buffer->compute_scratch_size_needed);
2528 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2529 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2530 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2531 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2532 }
2533 }
2534
2535 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2536 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2537 sample_positions_needed, &initial_flush_preamble_cs,
2538 &initial_preamble_cs, &continue_preamble_cs);
2539 if (result != VK_SUCCESS)
2540 return result;
2541
2542 for (uint32_t i = 0; i < submitCount; i++) {
2543 struct radeon_cmdbuf **cs_array;
2544 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2545 bool can_patch = true;
2546 uint32_t advance;
2547 struct radv_winsys_sem_info sem_info;
2548
2549 result = radv_alloc_sem_info(queue->device->instance,
2550 &sem_info,
2551 pSubmits[i].waitSemaphoreCount,
2552 pSubmits[i].pWaitSemaphores,
2553 pSubmits[i].signalSemaphoreCount,
2554 pSubmits[i].pSignalSemaphores,
2555 _fence);
2556 if (result != VK_SUCCESS)
2557 return result;
2558
2559 if (!pSubmits[i].commandBufferCount) {
2560 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2561 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2562 &queue->device->empty_cs[queue->queue_family_index],
2563 1, NULL, NULL,
2564 &sem_info, NULL,
2565 false, base_fence);
2566 if (ret) {
2567 radv_loge("failed to submit CS %d\n", i);
2568 abort();
2569 }
2570 fence_emitted = true;
2571 }
2572 radv_free_sem_info(&sem_info);
2573 continue;
2574 }
2575
2576 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2577 (pSubmits[i].commandBufferCount));
2578
2579 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2580 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2581 pSubmits[i].pCommandBuffers[j]);
2582 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2583
2584 cs_array[j] = cmd_buffer->cs;
2585 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2586 can_patch = false;
2587
2588 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2589 }
2590
2591 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2592 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2593 const struct radv_winsys_bo_list *bo_list = NULL;
2594
2595 advance = MIN2(max_cs_submission,
2596 pSubmits[i].commandBufferCount - j);
2597
2598 if (queue->device->trace_bo)
2599 *queue->device->trace_id_ptr = 0;
2600
2601 sem_info.cs_emit_wait = j == 0;
2602 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2603
2604 if (unlikely(queue->device->use_global_bo_list)) {
2605 pthread_mutex_lock(&queue->device->bo_list.mutex);
2606 bo_list = &queue->device->bo_list.list;
2607 }
2608
2609 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2610 advance, initial_preamble, continue_preamble_cs,
2611 &sem_info, bo_list,
2612 can_patch, base_fence);
2613
2614 if (unlikely(queue->device->use_global_bo_list))
2615 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2616
2617 if (ret) {
2618 radv_loge("failed to submit CS %d\n", i);
2619 abort();
2620 }
2621 fence_emitted = true;
2622 if (queue->device->trace_bo) {
2623 radv_check_gpu_hangs(queue, cs_array[j]);
2624 }
2625 }
2626
2627 radv_free_temp_syncobjs(queue->device,
2628 pSubmits[i].waitSemaphoreCount,
2629 pSubmits[i].pWaitSemaphores);
2630 radv_free_sem_info(&sem_info);
2631 free(cs_array);
2632 }
2633
2634 if (fence) {
2635 if (!fence_emitted) {
2636 result = radv_signal_fence(queue, fence);
2637 if (result != VK_SUCCESS)
2638 return result;
2639 }
2640 fence->submitted = true;
2641 }
2642
2643 return VK_SUCCESS;
2644 }
2645
2646 VkResult radv_QueueWaitIdle(
2647 VkQueue _queue)
2648 {
2649 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2650
2651 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2652 radv_queue_family_to_ring(queue->queue_family_index),
2653 queue->queue_idx);
2654 return VK_SUCCESS;
2655 }
2656
2657 VkResult radv_DeviceWaitIdle(
2658 VkDevice _device)
2659 {
2660 RADV_FROM_HANDLE(radv_device, device, _device);
2661
2662 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2663 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2664 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2665 }
2666 }
2667 return VK_SUCCESS;
2668 }
2669
2670 VkResult radv_EnumerateInstanceExtensionProperties(
2671 const char* pLayerName,
2672 uint32_t* pPropertyCount,
2673 VkExtensionProperties* pProperties)
2674 {
2675 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2676
2677 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2678 if (radv_supported_instance_extensions.extensions[i]) {
2679 vk_outarray_append(&out, prop) {
2680 *prop = radv_instance_extensions[i];
2681 }
2682 }
2683 }
2684
2685 return vk_outarray_status(&out);
2686 }
2687
2688 VkResult radv_EnumerateDeviceExtensionProperties(
2689 VkPhysicalDevice physicalDevice,
2690 const char* pLayerName,
2691 uint32_t* pPropertyCount,
2692 VkExtensionProperties* pProperties)
2693 {
2694 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2695 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2696
2697 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2698 if (device->supported_extensions.extensions[i]) {
2699 vk_outarray_append(&out, prop) {
2700 *prop = radv_device_extensions[i];
2701 }
2702 }
2703 }
2704
2705 return vk_outarray_status(&out);
2706 }
2707
2708 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2709 VkInstance _instance,
2710 const char* pName)
2711 {
2712 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2713
2714 return radv_lookup_entrypoint_checked(pName,
2715 instance ? instance->apiVersion : 0,
2716 instance ? &instance->enabled_extensions : NULL,
2717 NULL);
2718 }
2719
2720 /* The loader wants us to expose a second GetInstanceProcAddr function
2721 * to work around certain LD_PRELOAD issues seen in apps.
2722 */
2723 PUBLIC
2724 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2725 VkInstance instance,
2726 const char* pName);
2727
2728 PUBLIC
2729 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2730 VkInstance instance,
2731 const char* pName)
2732 {
2733 return radv_GetInstanceProcAddr(instance, pName);
2734 }
2735
2736 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2737 VkDevice _device,
2738 const char* pName)
2739 {
2740 RADV_FROM_HANDLE(radv_device, device, _device);
2741
2742 return radv_lookup_entrypoint_checked(pName,
2743 device->instance->apiVersion,
2744 &device->instance->enabled_extensions,
2745 &device->enabled_extensions);
2746 }
2747
2748 bool radv_get_memory_fd(struct radv_device *device,
2749 struct radv_device_memory *memory,
2750 int *pFD)
2751 {
2752 struct radeon_bo_metadata metadata;
2753
2754 if (memory->image) {
2755 radv_init_metadata(device, memory->image, &metadata);
2756 device->ws->buffer_set_metadata(memory->bo, &metadata);
2757 }
2758
2759 return device->ws->buffer_get_fd(device->ws, memory->bo,
2760 pFD);
2761 }
2762
2763 static VkResult radv_alloc_memory(struct radv_device *device,
2764 const VkMemoryAllocateInfo* pAllocateInfo,
2765 const VkAllocationCallbacks* pAllocator,
2766 VkDeviceMemory* pMem)
2767 {
2768 struct radv_device_memory *mem;
2769 VkResult result;
2770 enum radeon_bo_domain domain;
2771 uint32_t flags = 0;
2772 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2773
2774 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2775
2776 if (pAllocateInfo->allocationSize == 0) {
2777 /* Apparently, this is allowed */
2778 *pMem = VK_NULL_HANDLE;
2779 return VK_SUCCESS;
2780 }
2781
2782 const VkImportMemoryFdInfoKHR *import_info =
2783 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2784 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2785 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2786 const VkExportMemoryAllocateInfoKHR *export_info =
2787 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2788 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2789 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2790
2791 const struct wsi_memory_allocate_info *wsi_info =
2792 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2793
2794 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2795 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2796 if (mem == NULL)
2797 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2798
2799 if (wsi_info && wsi_info->implicit_sync)
2800 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2801
2802 if (dedicate_info) {
2803 mem->image = radv_image_from_handle(dedicate_info->image);
2804 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2805 } else {
2806 mem->image = NULL;
2807 mem->buffer = NULL;
2808 }
2809
2810 mem->user_ptr = NULL;
2811
2812 if (import_info) {
2813 assert(import_info->handleType ==
2814 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2815 import_info->handleType ==
2816 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2817 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2818 NULL, NULL);
2819 if (!mem->bo) {
2820 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2821 goto fail;
2822 } else {
2823 close(import_info->fd);
2824 }
2825 } else if (host_ptr_info) {
2826 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2827 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2828 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2829 pAllocateInfo->allocationSize);
2830 if (!mem->bo) {
2831 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2832 goto fail;
2833 } else {
2834 mem->user_ptr = host_ptr_info->pHostPointer;
2835 }
2836 } else {
2837 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2838 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2839 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2840 domain = RADEON_DOMAIN_GTT;
2841 else
2842 domain = RADEON_DOMAIN_VRAM;
2843
2844 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2845 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2846 else
2847 flags |= RADEON_FLAG_CPU_ACCESS;
2848
2849 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2850 flags |= RADEON_FLAG_GTT_WC;
2851
2852 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2853 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2854
2855 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2856 domain, flags);
2857
2858 if (!mem->bo) {
2859 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2860 goto fail;
2861 }
2862 mem->type_index = mem_type_index;
2863 }
2864
2865 result = radv_bo_list_add(device, mem->bo);
2866 if (result != VK_SUCCESS)
2867 goto fail_bo;
2868
2869 *pMem = radv_device_memory_to_handle(mem);
2870
2871 return VK_SUCCESS;
2872
2873 fail_bo:
2874 device->ws->buffer_destroy(mem->bo);
2875 fail:
2876 vk_free2(&device->alloc, pAllocator, mem);
2877
2878 return result;
2879 }
2880
2881 VkResult radv_AllocateMemory(
2882 VkDevice _device,
2883 const VkMemoryAllocateInfo* pAllocateInfo,
2884 const VkAllocationCallbacks* pAllocator,
2885 VkDeviceMemory* pMem)
2886 {
2887 RADV_FROM_HANDLE(radv_device, device, _device);
2888 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2889 }
2890
2891 void radv_FreeMemory(
2892 VkDevice _device,
2893 VkDeviceMemory _mem,
2894 const VkAllocationCallbacks* pAllocator)
2895 {
2896 RADV_FROM_HANDLE(radv_device, device, _device);
2897 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2898
2899 if (mem == NULL)
2900 return;
2901
2902 radv_bo_list_remove(device, mem->bo);
2903 device->ws->buffer_destroy(mem->bo);
2904 mem->bo = NULL;
2905
2906 vk_free2(&device->alloc, pAllocator, mem);
2907 }
2908
2909 VkResult radv_MapMemory(
2910 VkDevice _device,
2911 VkDeviceMemory _memory,
2912 VkDeviceSize offset,
2913 VkDeviceSize size,
2914 VkMemoryMapFlags flags,
2915 void** ppData)
2916 {
2917 RADV_FROM_HANDLE(radv_device, device, _device);
2918 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2919
2920 if (mem == NULL) {
2921 *ppData = NULL;
2922 return VK_SUCCESS;
2923 }
2924
2925 if (mem->user_ptr)
2926 *ppData = mem->user_ptr;
2927 else
2928 *ppData = device->ws->buffer_map(mem->bo);
2929
2930 if (*ppData) {
2931 *ppData += offset;
2932 return VK_SUCCESS;
2933 }
2934
2935 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2936 }
2937
2938 void radv_UnmapMemory(
2939 VkDevice _device,
2940 VkDeviceMemory _memory)
2941 {
2942 RADV_FROM_HANDLE(radv_device, device, _device);
2943 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2944
2945 if (mem == NULL)
2946 return;
2947
2948 if (mem->user_ptr == NULL)
2949 device->ws->buffer_unmap(mem->bo);
2950 }
2951
2952 VkResult radv_FlushMappedMemoryRanges(
2953 VkDevice _device,
2954 uint32_t memoryRangeCount,
2955 const VkMappedMemoryRange* pMemoryRanges)
2956 {
2957 return VK_SUCCESS;
2958 }
2959
2960 VkResult radv_InvalidateMappedMemoryRanges(
2961 VkDevice _device,
2962 uint32_t memoryRangeCount,
2963 const VkMappedMemoryRange* pMemoryRanges)
2964 {
2965 return VK_SUCCESS;
2966 }
2967
2968 void radv_GetBufferMemoryRequirements(
2969 VkDevice _device,
2970 VkBuffer _buffer,
2971 VkMemoryRequirements* pMemoryRequirements)
2972 {
2973 RADV_FROM_HANDLE(radv_device, device, _device);
2974 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2975
2976 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2977
2978 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2979 pMemoryRequirements->alignment = 4096;
2980 else
2981 pMemoryRequirements->alignment = 16;
2982
2983 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2984 }
2985
2986 void radv_GetBufferMemoryRequirements2(
2987 VkDevice device,
2988 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2989 VkMemoryRequirements2KHR* pMemoryRequirements)
2990 {
2991 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2992 &pMemoryRequirements->memoryRequirements);
2993 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2994 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2995 switch (ext->sType) {
2996 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2997 VkMemoryDedicatedRequirementsKHR *req =
2998 (VkMemoryDedicatedRequirementsKHR *) ext;
2999 req->requiresDedicatedAllocation = buffer->shareable;
3000 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3001 break;
3002 }
3003 default:
3004 break;
3005 }
3006 }
3007 }
3008
3009 void radv_GetImageMemoryRequirements(
3010 VkDevice _device,
3011 VkImage _image,
3012 VkMemoryRequirements* pMemoryRequirements)
3013 {
3014 RADV_FROM_HANDLE(radv_device, device, _device);
3015 RADV_FROM_HANDLE(radv_image, image, _image);
3016
3017 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3018
3019 pMemoryRequirements->size = image->size;
3020 pMemoryRequirements->alignment = image->alignment;
3021 }
3022
3023 void radv_GetImageMemoryRequirements2(
3024 VkDevice device,
3025 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3026 VkMemoryRequirements2KHR* pMemoryRequirements)
3027 {
3028 radv_GetImageMemoryRequirements(device, pInfo->image,
3029 &pMemoryRequirements->memoryRequirements);
3030
3031 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3032
3033 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3034 switch (ext->sType) {
3035 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3036 VkMemoryDedicatedRequirementsKHR *req =
3037 (VkMemoryDedicatedRequirementsKHR *) ext;
3038 req->requiresDedicatedAllocation = image->shareable;
3039 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3040 break;
3041 }
3042 default:
3043 break;
3044 }
3045 }
3046 }
3047
3048 void radv_GetImageSparseMemoryRequirements(
3049 VkDevice device,
3050 VkImage image,
3051 uint32_t* pSparseMemoryRequirementCount,
3052 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3053 {
3054 stub();
3055 }
3056
3057 void radv_GetImageSparseMemoryRequirements2(
3058 VkDevice device,
3059 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3060 uint32_t* pSparseMemoryRequirementCount,
3061 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3062 {
3063 stub();
3064 }
3065
3066 void radv_GetDeviceMemoryCommitment(
3067 VkDevice device,
3068 VkDeviceMemory memory,
3069 VkDeviceSize* pCommittedMemoryInBytes)
3070 {
3071 *pCommittedMemoryInBytes = 0;
3072 }
3073
3074 VkResult radv_BindBufferMemory2(VkDevice device,
3075 uint32_t bindInfoCount,
3076 const VkBindBufferMemoryInfoKHR *pBindInfos)
3077 {
3078 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3079 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3080 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3081
3082 if (mem) {
3083 buffer->bo = mem->bo;
3084 buffer->offset = pBindInfos[i].memoryOffset;
3085 } else {
3086 buffer->bo = NULL;
3087 }
3088 }
3089 return VK_SUCCESS;
3090 }
3091
3092 VkResult radv_BindBufferMemory(
3093 VkDevice device,
3094 VkBuffer buffer,
3095 VkDeviceMemory memory,
3096 VkDeviceSize memoryOffset)
3097 {
3098 const VkBindBufferMemoryInfoKHR info = {
3099 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3100 .buffer = buffer,
3101 .memory = memory,
3102 .memoryOffset = memoryOffset
3103 };
3104
3105 return radv_BindBufferMemory2(device, 1, &info);
3106 }
3107
3108 VkResult radv_BindImageMemory2(VkDevice device,
3109 uint32_t bindInfoCount,
3110 const VkBindImageMemoryInfoKHR *pBindInfos)
3111 {
3112 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3113 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3114 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3115
3116 if (mem) {
3117 image->bo = mem->bo;
3118 image->offset = pBindInfos[i].memoryOffset;
3119 } else {
3120 image->bo = NULL;
3121 image->offset = 0;
3122 }
3123 }
3124 return VK_SUCCESS;
3125 }
3126
3127
3128 VkResult radv_BindImageMemory(
3129 VkDevice device,
3130 VkImage image,
3131 VkDeviceMemory memory,
3132 VkDeviceSize memoryOffset)
3133 {
3134 const VkBindImageMemoryInfoKHR info = {
3135 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3136 .image = image,
3137 .memory = memory,
3138 .memoryOffset = memoryOffset
3139 };
3140
3141 return radv_BindImageMemory2(device, 1, &info);
3142 }
3143
3144
3145 static void
3146 radv_sparse_buffer_bind_memory(struct radv_device *device,
3147 const VkSparseBufferMemoryBindInfo *bind)
3148 {
3149 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3150
3151 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3152 struct radv_device_memory *mem = NULL;
3153
3154 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3155 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3156
3157 device->ws->buffer_virtual_bind(buffer->bo,
3158 bind->pBinds[i].resourceOffset,
3159 bind->pBinds[i].size,
3160 mem ? mem->bo : NULL,
3161 bind->pBinds[i].memoryOffset);
3162 }
3163 }
3164
3165 static void
3166 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3167 const VkSparseImageOpaqueMemoryBindInfo *bind)
3168 {
3169 RADV_FROM_HANDLE(radv_image, image, bind->image);
3170
3171 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3172 struct radv_device_memory *mem = NULL;
3173
3174 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3175 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3176
3177 device->ws->buffer_virtual_bind(image->bo,
3178 bind->pBinds[i].resourceOffset,
3179 bind->pBinds[i].size,
3180 mem ? mem->bo : NULL,
3181 bind->pBinds[i].memoryOffset);
3182 }
3183 }
3184
3185 VkResult radv_QueueBindSparse(
3186 VkQueue _queue,
3187 uint32_t bindInfoCount,
3188 const VkBindSparseInfo* pBindInfo,
3189 VkFence _fence)
3190 {
3191 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3192 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3193 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3194 bool fence_emitted = false;
3195 VkResult result;
3196 int ret;
3197
3198 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3199 struct radv_winsys_sem_info sem_info;
3200 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3201 radv_sparse_buffer_bind_memory(queue->device,
3202 pBindInfo[i].pBufferBinds + j);
3203 }
3204
3205 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3206 radv_sparse_image_opaque_bind_memory(queue->device,
3207 pBindInfo[i].pImageOpaqueBinds + j);
3208 }
3209
3210 VkResult result;
3211 result = radv_alloc_sem_info(queue->device->instance,
3212 &sem_info,
3213 pBindInfo[i].waitSemaphoreCount,
3214 pBindInfo[i].pWaitSemaphores,
3215 pBindInfo[i].signalSemaphoreCount,
3216 pBindInfo[i].pSignalSemaphores,
3217 _fence);
3218 if (result != VK_SUCCESS)
3219 return result;
3220
3221 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3222 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3223 &queue->device->empty_cs[queue->queue_family_index],
3224 1, NULL, NULL,
3225 &sem_info, NULL,
3226 false, base_fence);
3227 if (ret) {
3228 radv_loge("failed to submit CS %d\n", i);
3229 abort();
3230 }
3231
3232 fence_emitted = true;
3233 if (fence)
3234 fence->submitted = true;
3235 }
3236
3237 radv_free_sem_info(&sem_info);
3238
3239 }
3240
3241 if (fence) {
3242 if (!fence_emitted) {
3243 result = radv_signal_fence(queue, fence);
3244 if (result != VK_SUCCESS)
3245 return result;
3246 }
3247 fence->submitted = true;
3248 }
3249
3250 return VK_SUCCESS;
3251 }
3252
3253 VkResult radv_CreateFence(
3254 VkDevice _device,
3255 const VkFenceCreateInfo* pCreateInfo,
3256 const VkAllocationCallbacks* pAllocator,
3257 VkFence* pFence)
3258 {
3259 RADV_FROM_HANDLE(radv_device, device, _device);
3260 const VkExportFenceCreateInfoKHR *export =
3261 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3262 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3263 export ? export->handleTypes : 0;
3264
3265 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3266 sizeof(*fence), 8,
3267 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3268
3269 if (!fence)
3270 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3271
3272 fence->fence_wsi = NULL;
3273 fence->submitted = false;
3274 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3275 fence->temp_syncobj = 0;
3276 if (device->always_use_syncobj || handleTypes) {
3277 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3278 if (ret) {
3279 vk_free2(&device->alloc, pAllocator, fence);
3280 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3281 }
3282 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3283 device->ws->signal_syncobj(device->ws, fence->syncobj);
3284 }
3285 fence->fence = NULL;
3286 } else {
3287 fence->fence = device->ws->create_fence();
3288 if (!fence->fence) {
3289 vk_free2(&device->alloc, pAllocator, fence);
3290 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3291 }
3292 fence->syncobj = 0;
3293 }
3294
3295 *pFence = radv_fence_to_handle(fence);
3296
3297 return VK_SUCCESS;
3298 }
3299
3300 void radv_DestroyFence(
3301 VkDevice _device,
3302 VkFence _fence,
3303 const VkAllocationCallbacks* pAllocator)
3304 {
3305 RADV_FROM_HANDLE(radv_device, device, _device);
3306 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3307
3308 if (!fence)
3309 return;
3310
3311 if (fence->temp_syncobj)
3312 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3313 if (fence->syncobj)
3314 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3315 if (fence->fence)
3316 device->ws->destroy_fence(fence->fence);
3317 if (fence->fence_wsi)
3318 fence->fence_wsi->destroy(fence->fence_wsi);
3319 vk_free2(&device->alloc, pAllocator, fence);
3320 }
3321
3322
3323 static uint64_t radv_get_current_time()
3324 {
3325 struct timespec tv;
3326 clock_gettime(CLOCK_MONOTONIC, &tv);
3327 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3328 }
3329
3330 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3331 {
3332 uint64_t current_time = radv_get_current_time();
3333
3334 timeout = MIN2(UINT64_MAX - current_time, timeout);
3335
3336 return current_time + timeout;
3337 }
3338
3339
3340 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3341 {
3342 for (uint32_t i = 0; i < fenceCount; ++i) {
3343 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3344 if (fence->fence == NULL || fence->syncobj ||
3345 fence->temp_syncobj ||
3346 (!fence->signalled && !fence->submitted))
3347 return false;
3348 }
3349 return true;
3350 }
3351
3352 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3353 {
3354 for (uint32_t i = 0; i < fenceCount; ++i) {
3355 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3356 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3357 return false;
3358 }
3359 return true;
3360 }
3361
3362 VkResult radv_WaitForFences(
3363 VkDevice _device,
3364 uint32_t fenceCount,
3365 const VkFence* pFences,
3366 VkBool32 waitAll,
3367 uint64_t timeout)
3368 {
3369 RADV_FROM_HANDLE(radv_device, device, _device);
3370 timeout = radv_get_absolute_timeout(timeout);
3371
3372 if (device->always_use_syncobj &&
3373 radv_all_fences_syncobj(fenceCount, pFences))
3374 {
3375 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3376 if (!handles)
3377 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3378
3379 for (uint32_t i = 0; i < fenceCount; ++i) {
3380 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3381 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3382 }
3383
3384 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3385
3386 free(handles);
3387 return success ? VK_SUCCESS : VK_TIMEOUT;
3388 }
3389
3390 if (!waitAll && fenceCount > 1) {
3391 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3392 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3393 uint32_t wait_count = 0;
3394 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3395 if (!fences)
3396 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3397
3398 for (uint32_t i = 0; i < fenceCount; ++i) {
3399 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3400
3401 if (fence->signalled) {
3402 free(fences);
3403 return VK_SUCCESS;
3404 }
3405
3406 fences[wait_count++] = fence->fence;
3407 }
3408
3409 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3410 waitAll, timeout - radv_get_current_time());
3411
3412 free(fences);
3413 return success ? VK_SUCCESS : VK_TIMEOUT;
3414 }
3415
3416 while(radv_get_current_time() <= timeout) {
3417 for (uint32_t i = 0; i < fenceCount; ++i) {
3418 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3419 return VK_SUCCESS;
3420 }
3421 }
3422 return VK_TIMEOUT;
3423 }
3424
3425 for (uint32_t i = 0; i < fenceCount; ++i) {
3426 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3427 bool expired = false;
3428
3429 if (fence->temp_syncobj) {
3430 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3431 return VK_TIMEOUT;
3432 continue;
3433 }
3434
3435 if (fence->syncobj) {
3436 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3437 return VK_TIMEOUT;
3438 continue;
3439 }
3440
3441 if (fence->signalled)
3442 continue;
3443
3444 if (fence->fence) {
3445 if (!fence->submitted) {
3446 while(radv_get_current_time() <= timeout &&
3447 !fence->submitted)
3448 /* Do nothing */;
3449
3450 if (!fence->submitted)
3451 return VK_TIMEOUT;
3452
3453 /* Recheck as it may have been set by
3454 * submitting operations. */
3455
3456 if (fence->signalled)
3457 continue;
3458 }
3459
3460 expired = device->ws->fence_wait(device->ws,
3461 fence->fence,
3462 true, timeout);
3463 if (!expired)
3464 return VK_TIMEOUT;
3465 }
3466
3467 if (fence->fence_wsi) {
3468 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3469 if (result != VK_SUCCESS)
3470 return result;
3471 }
3472
3473 fence->signalled = true;
3474 }
3475
3476 return VK_SUCCESS;
3477 }
3478
3479 VkResult radv_ResetFences(VkDevice _device,
3480 uint32_t fenceCount,
3481 const VkFence *pFences)
3482 {
3483 RADV_FROM_HANDLE(radv_device, device, _device);
3484
3485 for (unsigned i = 0; i < fenceCount; ++i) {
3486 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3487 fence->submitted = fence->signalled = false;
3488
3489 /* Per spec, we first restore the permanent payload, and then reset, so
3490 * having a temp syncobj should not skip resetting the permanent syncobj. */
3491 if (fence->temp_syncobj) {
3492 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3493 fence->temp_syncobj = 0;
3494 }
3495
3496 if (fence->syncobj) {
3497 device->ws->reset_syncobj(device->ws, fence->syncobj);
3498 }
3499 }
3500
3501 return VK_SUCCESS;
3502 }
3503
3504 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3505 {
3506 RADV_FROM_HANDLE(radv_device, device, _device);
3507 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3508
3509 if (fence->temp_syncobj) {
3510 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3511 return success ? VK_SUCCESS : VK_NOT_READY;
3512 }
3513
3514 if (fence->syncobj) {
3515 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3516 return success ? VK_SUCCESS : VK_NOT_READY;
3517 }
3518
3519 if (fence->signalled)
3520 return VK_SUCCESS;
3521 if (!fence->submitted)
3522 return VK_NOT_READY;
3523 if (fence->fence) {
3524 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3525 return VK_NOT_READY;
3526 }
3527 if (fence->fence_wsi) {
3528 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3529
3530 if (result != VK_SUCCESS) {
3531 if (result == VK_TIMEOUT)
3532 return VK_NOT_READY;
3533 return result;
3534 }
3535 }
3536 return VK_SUCCESS;
3537 }
3538
3539
3540 // Queue semaphore functions
3541
3542 VkResult radv_CreateSemaphore(
3543 VkDevice _device,
3544 const VkSemaphoreCreateInfo* pCreateInfo,
3545 const VkAllocationCallbacks* pAllocator,
3546 VkSemaphore* pSemaphore)
3547 {
3548 RADV_FROM_HANDLE(radv_device, device, _device);
3549 const VkExportSemaphoreCreateInfoKHR *export =
3550 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3551 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3552 export ? export->handleTypes : 0;
3553
3554 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3555 sizeof(*sem), 8,
3556 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3557 if (!sem)
3558 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3559
3560 sem->temp_syncobj = 0;
3561 /* create a syncobject if we are going to export this semaphore */
3562 if (device->always_use_syncobj || handleTypes) {
3563 assert (device->physical_device->rad_info.has_syncobj);
3564 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3565 if (ret) {
3566 vk_free2(&device->alloc, pAllocator, sem);
3567 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3568 }
3569 sem->sem = NULL;
3570 } else {
3571 sem->sem = device->ws->create_sem(device->ws);
3572 if (!sem->sem) {
3573 vk_free2(&device->alloc, pAllocator, sem);
3574 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3575 }
3576 sem->syncobj = 0;
3577 }
3578
3579 *pSemaphore = radv_semaphore_to_handle(sem);
3580 return VK_SUCCESS;
3581 }
3582
3583 void radv_DestroySemaphore(
3584 VkDevice _device,
3585 VkSemaphore _semaphore,
3586 const VkAllocationCallbacks* pAllocator)
3587 {
3588 RADV_FROM_HANDLE(radv_device, device, _device);
3589 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3590 if (!_semaphore)
3591 return;
3592
3593 if (sem->syncobj)
3594 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3595 else
3596 device->ws->destroy_sem(sem->sem);
3597 vk_free2(&device->alloc, pAllocator, sem);
3598 }
3599
3600 VkResult radv_CreateEvent(
3601 VkDevice _device,
3602 const VkEventCreateInfo* pCreateInfo,
3603 const VkAllocationCallbacks* pAllocator,
3604 VkEvent* pEvent)
3605 {
3606 RADV_FROM_HANDLE(radv_device, device, _device);
3607 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3608 sizeof(*event), 8,
3609 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3610
3611 if (!event)
3612 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3613
3614 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3615 RADEON_DOMAIN_GTT,
3616 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3617 if (!event->bo) {
3618 vk_free2(&device->alloc, pAllocator, event);
3619 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3620 }
3621
3622 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3623
3624 *pEvent = radv_event_to_handle(event);
3625
3626 return VK_SUCCESS;
3627 }
3628
3629 void radv_DestroyEvent(
3630 VkDevice _device,
3631 VkEvent _event,
3632 const VkAllocationCallbacks* pAllocator)
3633 {
3634 RADV_FROM_HANDLE(radv_device, device, _device);
3635 RADV_FROM_HANDLE(radv_event, event, _event);
3636
3637 if (!event)
3638 return;
3639 device->ws->buffer_destroy(event->bo);
3640 vk_free2(&device->alloc, pAllocator, event);
3641 }
3642
3643 VkResult radv_GetEventStatus(
3644 VkDevice _device,
3645 VkEvent _event)
3646 {
3647 RADV_FROM_HANDLE(radv_event, event, _event);
3648
3649 if (*event->map == 1)
3650 return VK_EVENT_SET;
3651 return VK_EVENT_RESET;
3652 }
3653
3654 VkResult radv_SetEvent(
3655 VkDevice _device,
3656 VkEvent _event)
3657 {
3658 RADV_FROM_HANDLE(radv_event, event, _event);
3659 *event->map = 1;
3660
3661 return VK_SUCCESS;
3662 }
3663
3664 VkResult radv_ResetEvent(
3665 VkDevice _device,
3666 VkEvent _event)
3667 {
3668 RADV_FROM_HANDLE(radv_event, event, _event);
3669 *event->map = 0;
3670
3671 return VK_SUCCESS;
3672 }
3673
3674 VkResult radv_CreateBuffer(
3675 VkDevice _device,
3676 const VkBufferCreateInfo* pCreateInfo,
3677 const VkAllocationCallbacks* pAllocator,
3678 VkBuffer* pBuffer)
3679 {
3680 RADV_FROM_HANDLE(radv_device, device, _device);
3681 struct radv_buffer *buffer;
3682
3683 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3684
3685 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3686 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3687 if (buffer == NULL)
3688 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3689
3690 buffer->size = pCreateInfo->size;
3691 buffer->usage = pCreateInfo->usage;
3692 buffer->bo = NULL;
3693 buffer->offset = 0;
3694 buffer->flags = pCreateInfo->flags;
3695
3696 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3697 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3698
3699 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3700 buffer->bo = device->ws->buffer_create(device->ws,
3701 align64(buffer->size, 4096),
3702 4096, 0, RADEON_FLAG_VIRTUAL);
3703 if (!buffer->bo) {
3704 vk_free2(&device->alloc, pAllocator, buffer);
3705 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3706 }
3707 }
3708
3709 *pBuffer = radv_buffer_to_handle(buffer);
3710
3711 return VK_SUCCESS;
3712 }
3713
3714 void radv_DestroyBuffer(
3715 VkDevice _device,
3716 VkBuffer _buffer,
3717 const VkAllocationCallbacks* pAllocator)
3718 {
3719 RADV_FROM_HANDLE(radv_device, device, _device);
3720 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3721
3722 if (!buffer)
3723 return;
3724
3725 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3726 device->ws->buffer_destroy(buffer->bo);
3727
3728 vk_free2(&device->alloc, pAllocator, buffer);
3729 }
3730
3731 static inline unsigned
3732 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3733 {
3734 if (stencil)
3735 return image->surface.u.legacy.stencil_tiling_index[level];
3736 else
3737 return image->surface.u.legacy.tiling_index[level];
3738 }
3739
3740 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3741 {
3742 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3743 }
3744
3745 static uint32_t
3746 radv_init_dcc_control_reg(struct radv_device *device,
3747 struct radv_image_view *iview)
3748 {
3749 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3750 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3751 unsigned max_compressed_block_size;
3752 unsigned independent_64b_blocks;
3753
3754 if (device->physical_device->rad_info.chip_class < VI)
3755 return 0;
3756
3757 if (iview->image->info.samples > 1) {
3758 if (iview->image->surface.bpe == 1)
3759 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3760 else if (iview->image->surface.bpe == 2)
3761 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3762 }
3763
3764 if (!device->physical_device->rad_info.has_dedicated_vram) {
3765 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3766 * dGPU and 64 for APU because all of our APUs to date use
3767 * DIMMs which have a request granularity size of 64B while all
3768 * other chips have a 32B request size.
3769 */
3770 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3771 }
3772
3773 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3774 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3775 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3776 /* If this DCC image is potentially going to be used in texture
3777 * fetches, we need some special settings.
3778 */
3779 independent_64b_blocks = 1;
3780 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3781 } else {
3782 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3783 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3784 * big as possible for better compression state.
3785 */
3786 independent_64b_blocks = 0;
3787 max_compressed_block_size = max_uncompressed_block_size;
3788 }
3789
3790 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3791 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3792 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3793 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3794 }
3795
3796 static void
3797 radv_initialise_color_surface(struct radv_device *device,
3798 struct radv_color_buffer_info *cb,
3799 struct radv_image_view *iview)
3800 {
3801 const struct vk_format_description *desc;
3802 unsigned ntype, format, swap, endian;
3803 unsigned blend_clamp = 0, blend_bypass = 0;
3804 uint64_t va;
3805 const struct radeon_surf *surf = &iview->image->surface;
3806
3807 desc = vk_format_description(iview->vk_format);
3808
3809 memset(cb, 0, sizeof(*cb));
3810
3811 /* Intensity is implemented as Red, so treat it that way. */
3812 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3813
3814 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3815
3816 cb->cb_color_base = va >> 8;
3817
3818 if (device->physical_device->rad_info.chip_class >= GFX9) {
3819 struct gfx9_surf_meta_flags meta;
3820 if (iview->image->dcc_offset)
3821 meta = iview->image->surface.u.gfx9.dcc;
3822 else
3823 meta = iview->image->surface.u.gfx9.cmask;
3824
3825 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3826 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3827 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3828 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3829
3830 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3831 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3832 } else {
3833 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3834 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3835
3836 cb->cb_color_base += level_info->offset >> 8;
3837 if (level_info->mode == RADEON_SURF_MODE_2D)
3838 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3839
3840 pitch_tile_max = level_info->nblk_x / 8 - 1;
3841 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3842 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3843
3844 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3845 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3846 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3847
3848 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3849
3850 if (radv_image_has_fmask(iview->image)) {
3851 if (device->physical_device->rad_info.chip_class >= CIK)
3852 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3853 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3854 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3855 } else {
3856 /* This must be set for fast clear to work without FMASK. */
3857 if (device->physical_device->rad_info.chip_class >= CIK)
3858 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3859 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3860 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3861 }
3862 }
3863
3864 /* CMASK variables */
3865 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3866 va += iview->image->cmask.offset;
3867 cb->cb_color_cmask = va >> 8;
3868
3869 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3870 va += iview->image->dcc_offset;
3871 cb->cb_dcc_base = va >> 8;
3872 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3873
3874 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3875 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3876 S_028C6C_SLICE_MAX(max_slice);
3877
3878 if (iview->image->info.samples > 1) {
3879 unsigned log_samples = util_logbase2(iview->image->info.samples);
3880
3881 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3882 S_028C74_NUM_FRAGMENTS(log_samples);
3883 }
3884
3885 if (radv_image_has_fmask(iview->image)) {
3886 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3887 cb->cb_color_fmask = va >> 8;
3888 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3889 } else {
3890 cb->cb_color_fmask = cb->cb_color_base;
3891 }
3892
3893 ntype = radv_translate_color_numformat(iview->vk_format,
3894 desc,
3895 vk_format_get_first_non_void_channel(iview->vk_format));
3896 format = radv_translate_colorformat(iview->vk_format);
3897 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3898 radv_finishme("Illegal color\n");
3899 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3900 endian = radv_colorformat_endian_swap(format);
3901
3902 /* blend clamp should be set for all NORM/SRGB types */
3903 if (ntype == V_028C70_NUMBER_UNORM ||
3904 ntype == V_028C70_NUMBER_SNORM ||
3905 ntype == V_028C70_NUMBER_SRGB)
3906 blend_clamp = 1;
3907
3908 /* set blend bypass according to docs if SINT/UINT or
3909 8/24 COLOR variants */
3910 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3911 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3912 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3913 blend_clamp = 0;
3914 blend_bypass = 1;
3915 }
3916 #if 0
3917 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3918 (format == V_028C70_COLOR_8 ||
3919 format == V_028C70_COLOR_8_8 ||
3920 format == V_028C70_COLOR_8_8_8_8))
3921 ->color_is_int8 = true;
3922 #endif
3923 cb->cb_color_info = S_028C70_FORMAT(format) |
3924 S_028C70_COMP_SWAP(swap) |
3925 S_028C70_BLEND_CLAMP(blend_clamp) |
3926 S_028C70_BLEND_BYPASS(blend_bypass) |
3927 S_028C70_SIMPLE_FLOAT(1) |
3928 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3929 ntype != V_028C70_NUMBER_SNORM &&
3930 ntype != V_028C70_NUMBER_SRGB &&
3931 format != V_028C70_COLOR_8_24 &&
3932 format != V_028C70_COLOR_24_8) |
3933 S_028C70_NUMBER_TYPE(ntype) |
3934 S_028C70_ENDIAN(endian);
3935 if (radv_image_has_fmask(iview->image)) {
3936 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3937 if (device->physical_device->rad_info.chip_class == SI) {
3938 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3939 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3940 }
3941 }
3942
3943 if (radv_image_has_cmask(iview->image) &&
3944 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3945 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3946
3947 if (radv_dcc_enabled(iview->image, iview->base_mip))
3948 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3949
3950 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3951
3952 /* This must be set for fast clear to work without FMASK. */
3953 if (!radv_image_has_fmask(iview->image) &&
3954 device->physical_device->rad_info.chip_class == SI) {
3955 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3956 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3957 }
3958
3959 if (device->physical_device->rad_info.chip_class >= GFX9) {
3960 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3961 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3962
3963 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3964 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3965 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3966 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3967 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3968 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3969 }
3970 }
3971
3972 static unsigned
3973 radv_calc_decompress_on_z_planes(struct radv_device *device,
3974 struct radv_image_view *iview)
3975 {
3976 unsigned max_zplanes = 0;
3977
3978 assert(radv_image_is_tc_compat_htile(iview->image));
3979
3980 if (device->physical_device->rad_info.chip_class >= GFX9) {
3981 /* Default value for 32-bit depth surfaces. */
3982 max_zplanes = 4;
3983
3984 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3985 iview->image->info.samples > 1)
3986 max_zplanes = 2;
3987
3988 max_zplanes = max_zplanes + 1;
3989 } else {
3990 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3991 /* Do not enable Z plane compression for 16-bit depth
3992 * surfaces because isn't supported on GFX8. Only
3993 * 32-bit depth surfaces are supported by the hardware.
3994 * This allows to maintain shader compatibility and to
3995 * reduce the number of depth decompressions.
3996 */
3997 max_zplanes = 1;
3998 } else {
3999 if (iview->image->info.samples <= 1)
4000 max_zplanes = 5;
4001 else if (iview->image->info.samples <= 4)
4002 max_zplanes = 3;
4003 else
4004 max_zplanes = 2;
4005 }
4006 }
4007
4008 return max_zplanes;
4009 }
4010
4011 static void
4012 radv_initialise_ds_surface(struct radv_device *device,
4013 struct radv_ds_buffer_info *ds,
4014 struct radv_image_view *iview)
4015 {
4016 unsigned level = iview->base_mip;
4017 unsigned format, stencil_format;
4018 uint64_t va, s_offs, z_offs;
4019 bool stencil_only = false;
4020 memset(ds, 0, sizeof(*ds));
4021 switch (iview->image->vk_format) {
4022 case VK_FORMAT_D24_UNORM_S8_UINT:
4023 case VK_FORMAT_X8_D24_UNORM_PACK32:
4024 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4025 ds->offset_scale = 2.0f;
4026 break;
4027 case VK_FORMAT_D16_UNORM:
4028 case VK_FORMAT_D16_UNORM_S8_UINT:
4029 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4030 ds->offset_scale = 4.0f;
4031 break;
4032 case VK_FORMAT_D32_SFLOAT:
4033 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4034 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4035 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4036 ds->offset_scale = 1.0f;
4037 break;
4038 case VK_FORMAT_S8_UINT:
4039 stencil_only = true;
4040 break;
4041 default:
4042 break;
4043 }
4044
4045 format = radv_translate_dbformat(iview->image->vk_format);
4046 stencil_format = iview->image->surface.has_stencil ?
4047 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4048
4049 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4050 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4051 S_028008_SLICE_MAX(max_slice);
4052
4053 ds->db_htile_data_base = 0;
4054 ds->db_htile_surface = 0;
4055
4056 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4057 s_offs = z_offs = va;
4058
4059 if (device->physical_device->rad_info.chip_class >= GFX9) {
4060 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4061 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4062
4063 ds->db_z_info = S_028038_FORMAT(format) |
4064 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4065 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4066 S_028038_MAXMIP(iview->image->info.levels - 1) |
4067 S_028038_ZRANGE_PRECISION(1);
4068 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4069 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4070
4071 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4072 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4073 ds->db_depth_view |= S_028008_MIPID(level);
4074
4075 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4076 S_02801C_Y_MAX(iview->image->info.height - 1);
4077
4078 if (radv_htile_enabled(iview->image, level)) {
4079 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4080
4081 if (radv_image_is_tc_compat_htile(iview->image)) {
4082 unsigned max_zplanes =
4083 radv_calc_decompress_on_z_planes(device, iview);
4084
4085 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4086 S_028038_ITERATE_FLUSH(1);
4087 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4088 }
4089
4090 if (!iview->image->surface.has_stencil)
4091 /* Use all of the htile_buffer for depth if there's no stencil. */
4092 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4093 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4094 iview->image->htile_offset;
4095 ds->db_htile_data_base = va >> 8;
4096 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4097 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4098 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4099 }
4100 } else {
4101 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4102
4103 if (stencil_only)
4104 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4105
4106 z_offs += iview->image->surface.u.legacy.level[level].offset;
4107 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4108
4109 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4110 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4111 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4112
4113 if (iview->image->info.samples > 1)
4114 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4115
4116 if (device->physical_device->rad_info.chip_class >= CIK) {
4117 struct radeon_info *info = &device->physical_device->rad_info;
4118 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4119 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4120 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4121 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4122 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4123 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4124
4125 if (stencil_only)
4126 tile_mode = stencil_tile_mode;
4127
4128 ds->db_depth_info |=
4129 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4130 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4131 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4132 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4133 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4134 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4135 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4136 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4137 } else {
4138 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4139 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4140 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4141 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4142 if (stencil_only)
4143 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4144 }
4145
4146 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4147 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4148 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4149
4150 if (radv_htile_enabled(iview->image, level)) {
4151 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4152
4153 if (!iview->image->surface.has_stencil &&
4154 !radv_image_is_tc_compat_htile(iview->image))
4155 /* Use all of the htile_buffer for depth if there's no stencil. */
4156 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4157
4158 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4159 iview->image->htile_offset;
4160 ds->db_htile_data_base = va >> 8;
4161 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4162
4163 if (radv_image_is_tc_compat_htile(iview->image)) {
4164 unsigned max_zplanes =
4165 radv_calc_decompress_on_z_planes(device, iview);
4166
4167 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4168 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4169 }
4170 }
4171 }
4172
4173 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4174 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4175 }
4176
4177 VkResult radv_CreateFramebuffer(
4178 VkDevice _device,
4179 const VkFramebufferCreateInfo* pCreateInfo,
4180 const VkAllocationCallbacks* pAllocator,
4181 VkFramebuffer* pFramebuffer)
4182 {
4183 RADV_FROM_HANDLE(radv_device, device, _device);
4184 struct radv_framebuffer *framebuffer;
4185
4186 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4187
4188 size_t size = sizeof(*framebuffer) +
4189 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4190 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4191 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4192 if (framebuffer == NULL)
4193 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4194
4195 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4196 framebuffer->width = pCreateInfo->width;
4197 framebuffer->height = pCreateInfo->height;
4198 framebuffer->layers = pCreateInfo->layers;
4199 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4200 VkImageView _iview = pCreateInfo->pAttachments[i];
4201 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4202 framebuffer->attachments[i].attachment = iview;
4203 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4204 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4205 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4206 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4207 }
4208 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4209 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4210 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4211 }
4212
4213 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4214 return VK_SUCCESS;
4215 }
4216
4217 void radv_DestroyFramebuffer(
4218 VkDevice _device,
4219 VkFramebuffer _fb,
4220 const VkAllocationCallbacks* pAllocator)
4221 {
4222 RADV_FROM_HANDLE(radv_device, device, _device);
4223 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4224
4225 if (!fb)
4226 return;
4227 vk_free2(&device->alloc, pAllocator, fb);
4228 }
4229
4230 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4231 {
4232 switch (address_mode) {
4233 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4234 return V_008F30_SQ_TEX_WRAP;
4235 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4236 return V_008F30_SQ_TEX_MIRROR;
4237 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4238 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4239 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4240 return V_008F30_SQ_TEX_CLAMP_BORDER;
4241 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4242 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4243 default:
4244 unreachable("illegal tex wrap mode");
4245 break;
4246 }
4247 }
4248
4249 static unsigned
4250 radv_tex_compare(VkCompareOp op)
4251 {
4252 switch (op) {
4253 case VK_COMPARE_OP_NEVER:
4254 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4255 case VK_COMPARE_OP_LESS:
4256 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4257 case VK_COMPARE_OP_EQUAL:
4258 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4259 case VK_COMPARE_OP_LESS_OR_EQUAL:
4260 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4261 case VK_COMPARE_OP_GREATER:
4262 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4263 case VK_COMPARE_OP_NOT_EQUAL:
4264 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4265 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4266 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4267 case VK_COMPARE_OP_ALWAYS:
4268 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4269 default:
4270 unreachable("illegal compare mode");
4271 break;
4272 }
4273 }
4274
4275 static unsigned
4276 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4277 {
4278 switch (filter) {
4279 case VK_FILTER_NEAREST:
4280 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4281 V_008F38_SQ_TEX_XY_FILTER_POINT);
4282 case VK_FILTER_LINEAR:
4283 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4284 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4285 case VK_FILTER_CUBIC_IMG:
4286 default:
4287 fprintf(stderr, "illegal texture filter");
4288 return 0;
4289 }
4290 }
4291
4292 static unsigned
4293 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4294 {
4295 switch (mode) {
4296 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4297 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4298 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4299 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4300 default:
4301 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4302 }
4303 }
4304
4305 static unsigned
4306 radv_tex_bordercolor(VkBorderColor bcolor)
4307 {
4308 switch (bcolor) {
4309 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4310 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4311 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4312 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4313 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4314 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4315 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4316 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4317 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4318 default:
4319 break;
4320 }
4321 return 0;
4322 }
4323
4324 static unsigned
4325 radv_tex_aniso_filter(unsigned filter)
4326 {
4327 if (filter < 2)
4328 return 0;
4329 if (filter < 4)
4330 return 1;
4331 if (filter < 8)
4332 return 2;
4333 if (filter < 16)
4334 return 3;
4335 return 4;
4336 }
4337
4338 static unsigned
4339 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4340 {
4341 switch (mode) {
4342 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4343 return SQ_IMG_FILTER_MODE_BLEND;
4344 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4345 return SQ_IMG_FILTER_MODE_MIN;
4346 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4347 return SQ_IMG_FILTER_MODE_MAX;
4348 default:
4349 break;
4350 }
4351 return 0;
4352 }
4353
4354 static void
4355 radv_init_sampler(struct radv_device *device,
4356 struct radv_sampler *sampler,
4357 const VkSamplerCreateInfo *pCreateInfo)
4358 {
4359 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4360 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4361 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4362 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4363 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4364
4365 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4366 vk_find_struct_const(pCreateInfo->pNext,
4367 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4368 if (sampler_reduction)
4369 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4370
4371 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4372 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4373 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4374 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4375 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4376 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4377 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4378 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4379 S_008F30_DISABLE_CUBE_WRAP(0) |
4380 S_008F30_COMPAT_MODE(is_vi) |
4381 S_008F30_FILTER_MODE(filter_mode));
4382 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4383 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4384 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4385 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4386 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4387 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4388 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4389 S_008F38_MIP_POINT_PRECLAMP(0) |
4390 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4391 S_008F38_FILTER_PREC_FIX(1) |
4392 S_008F38_ANISO_OVERRIDE(is_vi));
4393 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4394 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4395 }
4396
4397 VkResult radv_CreateSampler(
4398 VkDevice _device,
4399 const VkSamplerCreateInfo* pCreateInfo,
4400 const VkAllocationCallbacks* pAllocator,
4401 VkSampler* pSampler)
4402 {
4403 RADV_FROM_HANDLE(radv_device, device, _device);
4404 struct radv_sampler *sampler;
4405
4406 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4407
4408 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4409 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4410 if (!sampler)
4411 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4412
4413 radv_init_sampler(device, sampler, pCreateInfo);
4414 *pSampler = radv_sampler_to_handle(sampler);
4415
4416 return VK_SUCCESS;
4417 }
4418
4419 void radv_DestroySampler(
4420 VkDevice _device,
4421 VkSampler _sampler,
4422 const VkAllocationCallbacks* pAllocator)
4423 {
4424 RADV_FROM_HANDLE(radv_device, device, _device);
4425 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4426
4427 if (!sampler)
4428 return;
4429 vk_free2(&device->alloc, pAllocator, sampler);
4430 }
4431
4432 /* vk_icd.h does not declare this function, so we declare it here to
4433 * suppress Wmissing-prototypes.
4434 */
4435 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4436 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4437
4438 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4439 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4440 {
4441 /* For the full details on loader interface versioning, see
4442 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4443 * What follows is a condensed summary, to help you navigate the large and
4444 * confusing official doc.
4445 *
4446 * - Loader interface v0 is incompatible with later versions. We don't
4447 * support it.
4448 *
4449 * - In loader interface v1:
4450 * - The first ICD entrypoint called by the loader is
4451 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4452 * entrypoint.
4453 * - The ICD must statically expose no other Vulkan symbol unless it is
4454 * linked with -Bsymbolic.
4455 * - Each dispatchable Vulkan handle created by the ICD must be
4456 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4457 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4458 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4459 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4460 * such loader-managed surfaces.
4461 *
4462 * - Loader interface v2 differs from v1 in:
4463 * - The first ICD entrypoint called by the loader is
4464 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4465 * statically expose this entrypoint.
4466 *
4467 * - Loader interface v3 differs from v2 in:
4468 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4469 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4470 * because the loader no longer does so.
4471 */
4472 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4473 return VK_SUCCESS;
4474 }
4475
4476 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4477 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4478 int *pFD)
4479 {
4480 RADV_FROM_HANDLE(radv_device, device, _device);
4481 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4482
4483 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4484
4485 /* At the moment, we support only the below handle types. */
4486 assert(pGetFdInfo->handleType ==
4487 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4488 pGetFdInfo->handleType ==
4489 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4490
4491 bool ret = radv_get_memory_fd(device, memory, pFD);
4492 if (ret == false)
4493 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4494 return VK_SUCCESS;
4495 }
4496
4497 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4498 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4499 int fd,
4500 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4501 {
4502 RADV_FROM_HANDLE(radv_device, device, _device);
4503
4504 switch (handleType) {
4505 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4506 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4507 return VK_SUCCESS;
4508
4509 default:
4510 /* The valid usage section for this function says:
4511 *
4512 * "handleType must not be one of the handle types defined as
4513 * opaque."
4514 *
4515 * So opaque handle types fall into the default "unsupported" case.
4516 */
4517 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4518 }
4519 }
4520
4521 static VkResult radv_import_opaque_fd(struct radv_device *device,
4522 int fd,
4523 uint32_t *syncobj)
4524 {
4525 uint32_t syncobj_handle = 0;
4526 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4527 if (ret != 0)
4528 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4529
4530 if (*syncobj)
4531 device->ws->destroy_syncobj(device->ws, *syncobj);
4532
4533 *syncobj = syncobj_handle;
4534 close(fd);
4535
4536 return VK_SUCCESS;
4537 }
4538
4539 static VkResult radv_import_sync_fd(struct radv_device *device,
4540 int fd,
4541 uint32_t *syncobj)
4542 {
4543 /* If we create a syncobj we do it locally so that if we have an error, we don't
4544 * leave a syncobj in an undetermined state in the fence. */
4545 uint32_t syncobj_handle = *syncobj;
4546 if (!syncobj_handle) {
4547 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4548 if (ret) {
4549 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4550 }
4551 }
4552
4553 if (fd == -1) {
4554 device->ws->signal_syncobj(device->ws, syncobj_handle);
4555 } else {
4556 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4557 if (ret != 0)
4558 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4559 }
4560
4561 *syncobj = syncobj_handle;
4562 if (fd != -1)
4563 close(fd);
4564
4565 return VK_SUCCESS;
4566 }
4567
4568 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4569 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4570 {
4571 RADV_FROM_HANDLE(radv_device, device, _device);
4572 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4573 uint32_t *syncobj_dst = NULL;
4574
4575 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4576 syncobj_dst = &sem->temp_syncobj;
4577 } else {
4578 syncobj_dst = &sem->syncobj;
4579 }
4580
4581 switch(pImportSemaphoreFdInfo->handleType) {
4582 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4583 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4584 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4585 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4586 default:
4587 unreachable("Unhandled semaphore handle type");
4588 }
4589 }
4590
4591 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4592 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4593 int *pFd)
4594 {
4595 RADV_FROM_HANDLE(radv_device, device, _device);
4596 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4597 int ret;
4598 uint32_t syncobj_handle;
4599
4600 if (sem->temp_syncobj)
4601 syncobj_handle = sem->temp_syncobj;
4602 else
4603 syncobj_handle = sem->syncobj;
4604
4605 switch(pGetFdInfo->handleType) {
4606 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4607 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4608 break;
4609 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4610 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4611 if (!ret) {
4612 if (sem->temp_syncobj) {
4613 close (sem->temp_syncobj);
4614 sem->temp_syncobj = 0;
4615 } else {
4616 device->ws->reset_syncobj(device->ws, syncobj_handle);
4617 }
4618 }
4619 break;
4620 default:
4621 unreachable("Unhandled semaphore handle type");
4622 }
4623
4624 if (ret)
4625 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4626 return VK_SUCCESS;
4627 }
4628
4629 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4630 VkPhysicalDevice physicalDevice,
4631 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4632 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4633 {
4634 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4635
4636 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4637 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4638 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4639 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4640 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4641 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4642 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4643 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4644 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4645 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4646 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4647 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4648 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4649 } else {
4650 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4651 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4652 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4653 }
4654 }
4655
4656 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4657 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4658 {
4659 RADV_FROM_HANDLE(radv_device, device, _device);
4660 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4661 uint32_t *syncobj_dst = NULL;
4662
4663
4664 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4665 syncobj_dst = &fence->temp_syncobj;
4666 } else {
4667 syncobj_dst = &fence->syncobj;
4668 }
4669
4670 switch(pImportFenceFdInfo->handleType) {
4671 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4672 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4673 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4674 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4675 default:
4676 unreachable("Unhandled fence handle type");
4677 }
4678 }
4679
4680 VkResult radv_GetFenceFdKHR(VkDevice _device,
4681 const VkFenceGetFdInfoKHR *pGetFdInfo,
4682 int *pFd)
4683 {
4684 RADV_FROM_HANDLE(radv_device, device, _device);
4685 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4686 int ret;
4687 uint32_t syncobj_handle;
4688
4689 if (fence->temp_syncobj)
4690 syncobj_handle = fence->temp_syncobj;
4691 else
4692 syncobj_handle = fence->syncobj;
4693
4694 switch(pGetFdInfo->handleType) {
4695 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4696 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4697 break;
4698 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4699 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4700 if (!ret) {
4701 if (fence->temp_syncobj) {
4702 close (fence->temp_syncobj);
4703 fence->temp_syncobj = 0;
4704 } else {
4705 device->ws->reset_syncobj(device->ws, syncobj_handle);
4706 }
4707 }
4708 break;
4709 default:
4710 unreachable("Unhandled fence handle type");
4711 }
4712
4713 if (ret)
4714 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4715 return VK_SUCCESS;
4716 }
4717
4718 void radv_GetPhysicalDeviceExternalFenceProperties(
4719 VkPhysicalDevice physicalDevice,
4720 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4721 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4722 {
4723 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4724
4725 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4726 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4727 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4728 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4729 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4730 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4731 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4732 } else {
4733 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4734 pExternalFenceProperties->compatibleHandleTypes = 0;
4735 pExternalFenceProperties->externalFenceFeatures = 0;
4736 }
4737 }
4738
4739 VkResult
4740 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4741 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4742 const VkAllocationCallbacks* pAllocator,
4743 VkDebugReportCallbackEXT* pCallback)
4744 {
4745 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4746 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4747 pCreateInfo, pAllocator, &instance->alloc,
4748 pCallback);
4749 }
4750
4751 void
4752 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4753 VkDebugReportCallbackEXT _callback,
4754 const VkAllocationCallbacks* pAllocator)
4755 {
4756 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4757 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4758 _callback, pAllocator, &instance->alloc);
4759 }
4760
4761 void
4762 radv_DebugReportMessageEXT(VkInstance _instance,
4763 VkDebugReportFlagsEXT flags,
4764 VkDebugReportObjectTypeEXT objectType,
4765 uint64_t object,
4766 size_t location,
4767 int32_t messageCode,
4768 const char* pLayerPrefix,
4769 const char* pMessage)
4770 {
4771 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4772 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4773 object, location, messageCode, pLayerPrefix, pMessage);
4774 }
4775
4776 void
4777 radv_GetDeviceGroupPeerMemoryFeatures(
4778 VkDevice device,
4779 uint32_t heapIndex,
4780 uint32_t localDeviceIndex,
4781 uint32_t remoteDeviceIndex,
4782 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4783 {
4784 assert(localDeviceIndex == remoteDeviceIndex);
4785
4786 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4787 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4788 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4789 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4790 }