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[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
105 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
106 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
107 default: chip_string = "AMD RADV unknown"; break;
108 }
109
110 if (HAVE_LLVM > 0) {
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 }
115
116 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
117 }
118
119 static void
120 radv_physical_device_init_mem_types(struct radv_physical_device *device)
121 {
122 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
123 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
124 device->rad_info.vram_vis_size);
125
126 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
127 device->memory_properties.memoryHeapCount = 0;
128 if (device->rad_info.vram_size - visible_vram_size > 0) {
129 vram_index = device->memory_properties.memoryHeapCount++;
130 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
131 .size = device->rad_info.vram_size - visible_vram_size,
132 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
133 };
134 }
135 if (visible_vram_size) {
136 visible_vram_index = device->memory_properties.memoryHeapCount++;
137 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
138 .size = visible_vram_size,
139 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
140 };
141 }
142 if (device->rad_info.gart_size > 0) {
143 gart_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
145 .size = device->rad_info.gart_size,
146 .flags = 0,
147 };
148 }
149
150 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
151 unsigned type_count = 0;
152 if (vram_index >= 0) {
153 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
154 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
155 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
156 .heapIndex = vram_index,
157 };
158 }
159 if (gart_index >= 0) {
160 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
161 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
162 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
163 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
164 .heapIndex = gart_index,
165 };
166 }
167 if (visible_vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
171 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
172 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
173 .heapIndex = visible_vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228
229 fd = open(path, O_RDWR | O_CLOEXEC);
230 if (fd < 0)
231 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
232
233 version = drmGetVersion(fd);
234 if (!version) {
235 close(fd);
236 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
237 "failed to get version %s: %m", path);
238 }
239
240 if (strcmp(version->name, "amdgpu")) {
241 drmFreeVersion(version);
242 close(fd);
243 return VK_ERROR_INCOMPATIBLE_DRIVER;
244 }
245 drmFreeVersion(version);
246
247 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 device->instance = instance;
249 assert(strlen(path) < ARRAY_SIZE(device->path));
250 strncpy(device->path, path, ARRAY_SIZE(device->path));
251
252 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
253 instance->perftest_flags);
254 if (!device->ws) {
255 result = VK_ERROR_INCOMPATIBLE_DRIVER;
256 goto fail;
257 }
258
259 device->local_fd = fd;
260 device->ws->query_info(device->ws, &device->rad_info);
261
262 radv_handle_env_var_force_family(device);
263
264 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
265
266 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
267 device->ws->destroy(device->ws);
268 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
269 "cannot generate UUID");
270 goto fail;
271 }
272
273 /* These flags affect shader compilation. */
274 uint64_t shader_env_flags =
275 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
276 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
277
278 /* The gpu id is already embeded in the uuid so we just pass "radv"
279 * when creating the cache.
280 */
281 char buf[VK_UUID_SIZE * 2 + 1];
282 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
283 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
284
285 if (device->rad_info.chip_class < VI ||
286 device->rad_info.chip_class > GFX9)
287 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
288
289 radv_get_driver_uuid(&device->device_uuid);
290 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
291
292 if (device->rad_info.family == CHIP_STONEY ||
293 device->rad_info.chip_class >= GFX9) {
294 device->has_rbplus = true;
295 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
296 device->rad_info.family == CHIP_VEGA12 ||
297 device->rad_info.family == CHIP_RAVEN;
298 }
299
300 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
301 * on SI.
302 */
303 device->has_clear_state = device->rad_info.chip_class >= CIK;
304
305 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
306
307 /* Vega10/Raven need a special workaround for a hardware bug. */
308 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
309 device->rad_info.family == CHIP_RAVEN;
310
311 /* Out-of-order primitive rasterization. */
312 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
313 device->rad_info.max_se >= 2;
314 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
315 (device->instance->perftest_flags & RADV_PERFTEST_OUT_OF_ORDER);
316
317 radv_physical_device_init_mem_types(device);
318 radv_fill_device_extension_table(device, &device->supported_extensions);
319
320 result = radv_init_wsi(device);
321 if (result != VK_SUCCESS) {
322 device->ws->destroy(device->ws);
323 goto fail;
324 }
325
326 return VK_SUCCESS;
327
328 fail:
329 close(fd);
330 return result;
331 }
332
333 static void
334 radv_physical_device_finish(struct radv_physical_device *device)
335 {
336 radv_finish_wsi(device);
337 device->ws->destroy(device->ws);
338 disk_cache_destroy(device->disk_cache);
339 close(device->local_fd);
340 }
341
342 static void *
343 default_alloc_func(void *pUserData, size_t size, size_t align,
344 VkSystemAllocationScope allocationScope)
345 {
346 return malloc(size);
347 }
348
349 static void *
350 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
351 size_t align, VkSystemAllocationScope allocationScope)
352 {
353 return realloc(pOriginal, size);
354 }
355
356 static void
357 default_free_func(void *pUserData, void *pMemory)
358 {
359 free(pMemory);
360 }
361
362 static const VkAllocationCallbacks default_alloc = {
363 .pUserData = NULL,
364 .pfnAllocation = default_alloc_func,
365 .pfnReallocation = default_realloc_func,
366 .pfnFree = default_free_func,
367 };
368
369 static const struct debug_control radv_debug_options[] = {
370 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
371 {"nodcc", RADV_DEBUG_NO_DCC},
372 {"shaders", RADV_DEBUG_DUMP_SHADERS},
373 {"nocache", RADV_DEBUG_NO_CACHE},
374 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
375 {"nohiz", RADV_DEBUG_NO_HIZ},
376 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
377 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
378 {"allbos", RADV_DEBUG_ALL_BOS},
379 {"noibs", RADV_DEBUG_NO_IBS},
380 {"spirv", RADV_DEBUG_DUMP_SPIRV},
381 {"vmfaults", RADV_DEBUG_VM_FAULTS},
382 {"zerovram", RADV_DEBUG_ZERO_VRAM},
383 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
384 {"nosisched", RADV_DEBUG_NO_SISCHED},
385 {"preoptir", RADV_DEBUG_PREOPTIR},
386 {NULL, 0}
387 };
388
389 const char *
390 radv_get_debug_option_name(int id)
391 {
392 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
393 return radv_debug_options[id].string;
394 }
395
396 static const struct debug_control radv_perftest_options[] = {
397 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
398 {"sisched", RADV_PERFTEST_SISCHED},
399 {"localbos", RADV_PERFTEST_LOCAL_BOS},
400 {"binning", RADV_PERFTEST_BINNING},
401 {"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
402 {NULL, 0}
403 };
404
405 const char *
406 radv_get_perftest_option_name(int id)
407 {
408 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
409 return radv_perftest_options[id].string;
410 }
411
412 static void
413 radv_handle_per_app_options(struct radv_instance *instance,
414 const VkApplicationInfo *info)
415 {
416 const char *name = info ? info->pApplicationName : NULL;
417
418 if (!name)
419 return;
420
421 if (!strcmp(name, "Talos - Linux - 32bit") ||
422 !strcmp(name, "Talos - Linux - 64bit")) {
423 /* Force enable LLVM sisched for Talos because it looks safe
424 * and it gives few more FPS.
425 */
426 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
427 }
428 }
429
430 static int radv_get_instance_extension_index(const char *name)
431 {
432 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
433 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
434 return i;
435 }
436 return -1;
437 }
438
439
440 VkResult radv_CreateInstance(
441 const VkInstanceCreateInfo* pCreateInfo,
442 const VkAllocationCallbacks* pAllocator,
443 VkInstance* pInstance)
444 {
445 struct radv_instance *instance;
446 VkResult result;
447
448 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
449
450 uint32_t client_version;
451 if (pCreateInfo->pApplicationInfo &&
452 pCreateInfo->pApplicationInfo->apiVersion != 0) {
453 client_version = pCreateInfo->pApplicationInfo->apiVersion;
454 } else {
455 client_version = VK_MAKE_VERSION(1, 0, 0);
456 }
457
458 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
459 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
460 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
461 "Client requested version %d.%d.%d",
462 VK_VERSION_MAJOR(client_version),
463 VK_VERSION_MINOR(client_version),
464 VK_VERSION_PATCH(client_version));
465 }
466
467 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
468 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
469 if (!instance)
470 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
471
472 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
473
474 if (pAllocator)
475 instance->alloc = *pAllocator;
476 else
477 instance->alloc = default_alloc;
478
479 instance->apiVersion = client_version;
480 instance->physicalDeviceCount = -1;
481
482 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
483 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
484 int index = radv_get_instance_extension_index(ext_name);
485
486 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
487 vk_free2(&default_alloc, pAllocator, instance);
488 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
489 }
490
491 instance->enabled_extensions.extensions[index] = true;
492 }
493
494 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
495 if (result != VK_SUCCESS) {
496 vk_free2(&default_alloc, pAllocator, instance);
497 return vk_error(result);
498 }
499
500 _mesa_locale_init();
501
502 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
503
504 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
505 radv_debug_options);
506
507 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
508 radv_perftest_options);
509
510 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
511
512 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
513 /* Disable sisched when the user requests it, this is mostly
514 * useful when the driver force-enable sisched for the given
515 * application.
516 */
517 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
518 }
519
520 *pInstance = radv_instance_to_handle(instance);
521
522 return VK_SUCCESS;
523 }
524
525 void radv_DestroyInstance(
526 VkInstance _instance,
527 const VkAllocationCallbacks* pAllocator)
528 {
529 RADV_FROM_HANDLE(radv_instance, instance, _instance);
530
531 if (!instance)
532 return;
533
534 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
535 radv_physical_device_finish(instance->physicalDevices + i);
536 }
537
538 VG(VALGRIND_DESTROY_MEMPOOL(instance));
539
540 _mesa_locale_fini();
541
542 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
543
544 vk_free(&instance->alloc, instance);
545 }
546
547 static VkResult
548 radv_enumerate_devices(struct radv_instance *instance)
549 {
550 /* TODO: Check for more devices ? */
551 drmDevicePtr devices[8];
552 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
553 int max_devices;
554
555 instance->physicalDeviceCount = 0;
556
557 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
558 if (max_devices < 1)
559 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
560
561 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
562 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
563 devices[i]->bustype == DRM_BUS_PCI &&
564 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
565
566 result = radv_physical_device_init(instance->physicalDevices +
567 instance->physicalDeviceCount,
568 instance,
569 devices[i]);
570 if (result == VK_SUCCESS)
571 ++instance->physicalDeviceCount;
572 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
573 break;
574 }
575 }
576 drmFreeDevices(devices, max_devices);
577
578 return result;
579 }
580
581 VkResult radv_EnumeratePhysicalDevices(
582 VkInstance _instance,
583 uint32_t* pPhysicalDeviceCount,
584 VkPhysicalDevice* pPhysicalDevices)
585 {
586 RADV_FROM_HANDLE(radv_instance, instance, _instance);
587 VkResult result;
588
589 if (instance->physicalDeviceCount < 0) {
590 result = radv_enumerate_devices(instance);
591 if (result != VK_SUCCESS &&
592 result != VK_ERROR_INCOMPATIBLE_DRIVER)
593 return result;
594 }
595
596 if (!pPhysicalDevices) {
597 *pPhysicalDeviceCount = instance->physicalDeviceCount;
598 } else {
599 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
600 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
601 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
602 }
603
604 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
605 : VK_SUCCESS;
606 }
607
608 VkResult radv_EnumeratePhysicalDeviceGroups(
609 VkInstance _instance,
610 uint32_t* pPhysicalDeviceGroupCount,
611 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
612 {
613 RADV_FROM_HANDLE(radv_instance, instance, _instance);
614 VkResult result;
615
616 if (instance->physicalDeviceCount < 0) {
617 result = radv_enumerate_devices(instance);
618 if (result != VK_SUCCESS &&
619 result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 return result;
621 }
622
623 if (!pPhysicalDeviceGroupProperties) {
624 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
625 } else {
626 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
627 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
628 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
629 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
630 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
631 }
632 }
633 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
634 : VK_SUCCESS;
635 }
636
637 void radv_GetPhysicalDeviceFeatures(
638 VkPhysicalDevice physicalDevice,
639 VkPhysicalDeviceFeatures* pFeatures)
640 {
641 memset(pFeatures, 0, sizeof(*pFeatures));
642
643 *pFeatures = (VkPhysicalDeviceFeatures) {
644 .robustBufferAccess = true,
645 .fullDrawIndexUint32 = true,
646 .imageCubeArray = true,
647 .independentBlend = true,
648 .geometryShader = true,
649 .tessellationShader = true,
650 .sampleRateShading = true,
651 .dualSrcBlend = true,
652 .logicOp = true,
653 .multiDrawIndirect = true,
654 .drawIndirectFirstInstance = true,
655 .depthClamp = true,
656 .depthBiasClamp = true,
657 .fillModeNonSolid = true,
658 .depthBounds = true,
659 .wideLines = true,
660 .largePoints = true,
661 .alphaToOne = true,
662 .multiViewport = true,
663 .samplerAnisotropy = true,
664 .textureCompressionETC2 = false,
665 .textureCompressionASTC_LDR = false,
666 .textureCompressionBC = true,
667 .occlusionQueryPrecise = true,
668 .pipelineStatisticsQuery = true,
669 .vertexPipelineStoresAndAtomics = true,
670 .fragmentStoresAndAtomics = true,
671 .shaderTessellationAndGeometryPointSize = true,
672 .shaderImageGatherExtended = true,
673 .shaderStorageImageExtendedFormats = true,
674 .shaderStorageImageMultisample = false,
675 .shaderUniformBufferArrayDynamicIndexing = true,
676 .shaderSampledImageArrayDynamicIndexing = true,
677 .shaderStorageBufferArrayDynamicIndexing = true,
678 .shaderStorageImageArrayDynamicIndexing = true,
679 .shaderStorageImageReadWithoutFormat = true,
680 .shaderStorageImageWriteWithoutFormat = true,
681 .shaderClipDistance = true,
682 .shaderCullDistance = true,
683 .shaderFloat64 = true,
684 .shaderInt64 = true,
685 .shaderInt16 = false,
686 .sparseBinding = true,
687 .variableMultisampleRate = true,
688 .inheritedQueries = true,
689 };
690 }
691
692 void radv_GetPhysicalDeviceFeatures2(
693 VkPhysicalDevice physicalDevice,
694 VkPhysicalDeviceFeatures2KHR *pFeatures)
695 {
696 vk_foreach_struct(ext, pFeatures->pNext) {
697 switch (ext->sType) {
698 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
699 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
700 features->variablePointersStorageBuffer = true;
701 features->variablePointers = false;
702 break;
703 }
704 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
705 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
706 features->multiview = true;
707 features->multiviewGeometryShader = true;
708 features->multiviewTessellationShader = true;
709 break;
710 }
711 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
712 VkPhysicalDeviceShaderDrawParameterFeatures *features =
713 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
714 features->shaderDrawParameters = true;
715 break;
716 }
717 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
718 VkPhysicalDeviceProtectedMemoryFeatures *features =
719 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
720 features->protectedMemory = false;
721 break;
722 }
723 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
724 VkPhysicalDevice16BitStorageFeatures *features =
725 (VkPhysicalDevice16BitStorageFeatures*)ext;
726 features->storageBuffer16BitAccess = false;
727 features->uniformAndStorageBuffer16BitAccess = false;
728 features->storagePushConstant16 = false;
729 features->storageInputOutput16 = false;
730 break;
731 }
732 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
733 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
734 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
735 features->samplerYcbcrConversion = false;
736 break;
737 }
738 default:
739 break;
740 }
741 }
742 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
743 }
744
745 void radv_GetPhysicalDeviceProperties(
746 VkPhysicalDevice physicalDevice,
747 VkPhysicalDeviceProperties* pProperties)
748 {
749 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
750 VkSampleCountFlags sample_counts = 0xf;
751
752 /* make sure that the entire descriptor set is addressable with a signed
753 * 32-bit int. So the sum of all limits scaled by descriptor size has to
754 * be at most 2 GiB. the combined image & samples object count as one of
755 * both. This limit is for the pipeline layout, not for the set layout, but
756 * there is no set limit, so we just set a pipeline limit. I don't think
757 * any app is going to hit this soon. */
758 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
759 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
760 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
761 32 /* sampler, largest when combined with image */ +
762 64 /* sampled image */ +
763 64 /* storage image */);
764
765 VkPhysicalDeviceLimits limits = {
766 .maxImageDimension1D = (1 << 14),
767 .maxImageDimension2D = (1 << 14),
768 .maxImageDimension3D = (1 << 11),
769 .maxImageDimensionCube = (1 << 14),
770 .maxImageArrayLayers = (1 << 11),
771 .maxTexelBufferElements = 128 * 1024 * 1024,
772 .maxUniformBufferRange = UINT32_MAX,
773 .maxStorageBufferRange = UINT32_MAX,
774 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
775 .maxMemoryAllocationCount = UINT32_MAX,
776 .maxSamplerAllocationCount = 64 * 1024,
777 .bufferImageGranularity = 64, /* A cache line */
778 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
779 .maxBoundDescriptorSets = MAX_SETS,
780 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
781 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
782 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
783 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
784 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
785 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
786 .maxPerStageResources = max_descriptor_set_size,
787 .maxDescriptorSetSamplers = max_descriptor_set_size,
788 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
789 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
790 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
791 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
792 .maxDescriptorSetSampledImages = max_descriptor_set_size,
793 .maxDescriptorSetStorageImages = max_descriptor_set_size,
794 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
795 .maxVertexInputAttributes = 32,
796 .maxVertexInputBindings = 32,
797 .maxVertexInputAttributeOffset = 2047,
798 .maxVertexInputBindingStride = 2048,
799 .maxVertexOutputComponents = 128,
800 .maxTessellationGenerationLevel = 64,
801 .maxTessellationPatchSize = 32,
802 .maxTessellationControlPerVertexInputComponents = 128,
803 .maxTessellationControlPerVertexOutputComponents = 128,
804 .maxTessellationControlPerPatchOutputComponents = 120,
805 .maxTessellationControlTotalOutputComponents = 4096,
806 .maxTessellationEvaluationInputComponents = 128,
807 .maxTessellationEvaluationOutputComponents = 128,
808 .maxGeometryShaderInvocations = 127,
809 .maxGeometryInputComponents = 64,
810 .maxGeometryOutputComponents = 128,
811 .maxGeometryOutputVertices = 256,
812 .maxGeometryTotalOutputComponents = 1024,
813 .maxFragmentInputComponents = 128,
814 .maxFragmentOutputAttachments = 8,
815 .maxFragmentDualSrcAttachments = 1,
816 .maxFragmentCombinedOutputResources = 8,
817 .maxComputeSharedMemorySize = 32768,
818 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
819 .maxComputeWorkGroupInvocations = 2048,
820 .maxComputeWorkGroupSize = {
821 2048,
822 2048,
823 2048
824 },
825 .subPixelPrecisionBits = 4 /* FIXME */,
826 .subTexelPrecisionBits = 4 /* FIXME */,
827 .mipmapPrecisionBits = 4 /* FIXME */,
828 .maxDrawIndexedIndexValue = UINT32_MAX,
829 .maxDrawIndirectCount = UINT32_MAX,
830 .maxSamplerLodBias = 16,
831 .maxSamplerAnisotropy = 16,
832 .maxViewports = MAX_VIEWPORTS,
833 .maxViewportDimensions = { (1 << 14), (1 << 14) },
834 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
835 .viewportSubPixelBits = 13, /* We take a float? */
836 .minMemoryMapAlignment = 4096, /* A page */
837 .minTexelBufferOffsetAlignment = 1,
838 .minUniformBufferOffsetAlignment = 4,
839 .minStorageBufferOffsetAlignment = 4,
840 .minTexelOffset = -32,
841 .maxTexelOffset = 31,
842 .minTexelGatherOffset = -32,
843 .maxTexelGatherOffset = 31,
844 .minInterpolationOffset = -2,
845 .maxInterpolationOffset = 2,
846 .subPixelInterpolationOffsetBits = 8,
847 .maxFramebufferWidth = (1 << 14),
848 .maxFramebufferHeight = (1 << 14),
849 .maxFramebufferLayers = (1 << 10),
850 .framebufferColorSampleCounts = sample_counts,
851 .framebufferDepthSampleCounts = sample_counts,
852 .framebufferStencilSampleCounts = sample_counts,
853 .framebufferNoAttachmentsSampleCounts = sample_counts,
854 .maxColorAttachments = MAX_RTS,
855 .sampledImageColorSampleCounts = sample_counts,
856 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
857 .sampledImageDepthSampleCounts = sample_counts,
858 .sampledImageStencilSampleCounts = sample_counts,
859 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
860 .maxSampleMaskWords = 1,
861 .timestampComputeAndGraphics = true,
862 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
863 .maxClipDistances = 8,
864 .maxCullDistances = 8,
865 .maxCombinedClipAndCullDistances = 8,
866 .discreteQueuePriorities = 1,
867 .pointSizeRange = { 0.125, 255.875 },
868 .lineWidthRange = { 0.0, 7.9921875 },
869 .pointSizeGranularity = (1.0 / 8.0),
870 .lineWidthGranularity = (1.0 / 128.0),
871 .strictLines = false, /* FINISHME */
872 .standardSampleLocations = true,
873 .optimalBufferCopyOffsetAlignment = 128,
874 .optimalBufferCopyRowPitchAlignment = 128,
875 .nonCoherentAtomSize = 64,
876 };
877
878 *pProperties = (VkPhysicalDeviceProperties) {
879 .apiVersion = radv_physical_device_api_version(pdevice),
880 .driverVersion = vk_get_driver_version(),
881 .vendorID = ATI_VENDOR_ID,
882 .deviceID = pdevice->rad_info.pci_id,
883 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
884 .limits = limits,
885 .sparseProperties = {0},
886 };
887
888 strcpy(pProperties->deviceName, pdevice->name);
889 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
890 }
891
892 void radv_GetPhysicalDeviceProperties2(
893 VkPhysicalDevice physicalDevice,
894 VkPhysicalDeviceProperties2KHR *pProperties)
895 {
896 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
897 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
898
899 vk_foreach_struct(ext, pProperties->pNext) {
900 switch (ext->sType) {
901 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
902 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
903 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
904 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
905 break;
906 }
907 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
908 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
909 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
910 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
911 properties->deviceLUIDValid = false;
912 break;
913 }
914 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
915 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
916 properties->maxMultiviewViewCount = MAX_VIEWS;
917 properties->maxMultiviewInstanceIndex = INT_MAX;
918 break;
919 }
920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
921 VkPhysicalDevicePointClippingPropertiesKHR *properties =
922 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
923 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
924 break;
925 }
926 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
927 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
928 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
929 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
930 break;
931 }
932 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
933 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
934 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
935 properties->minImportedHostPointerAlignment = 4096;
936 break;
937 }
938 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
939 VkPhysicalDeviceSubgroupProperties *properties =
940 (VkPhysicalDeviceSubgroupProperties*)ext;
941 properties->subgroupSize = 64;
942 properties->supportedStages = VK_SHADER_STAGE_ALL;
943 properties->supportedOperations =
944 VK_SUBGROUP_FEATURE_BASIC_BIT |
945 VK_SUBGROUP_FEATURE_BALLOT_BIT |
946 VK_SUBGROUP_FEATURE_QUAD_BIT |
947 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
948 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT |
949 VK_SUBGROUP_FEATURE_VOTE_BIT;
950 properties->quadOperationsInAllStages = true;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
954 VkPhysicalDeviceMaintenance3Properties *properties =
955 (VkPhysicalDeviceMaintenance3Properties*)ext;
956 /* Make sure everything is addressable by a signed 32-bit int, and
957 * our largest descriptors are 96 bytes. */
958 properties->maxPerSetDescriptors = (1ull << 31) / 96;
959 /* Our buffer size fields allow only this much */
960 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
961 break;
962 }
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
964 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
965 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
966 /* GFX6-8 only support single channel min/max filter. */
967 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
968 properties->filterMinmaxSingleComponentFormats = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
972 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
973 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
974
975 /* Shader engines. */
976 properties->shaderEngineCount =
977 pdevice->rad_info.max_se;
978 properties->shaderArraysPerEngineCount =
979 pdevice->rad_info.max_sh_per_se;
980 properties->computeUnitsPerShaderArray =
981 pdevice->rad_info.num_good_compute_units /
982 (pdevice->rad_info.max_se *
983 pdevice->rad_info.max_sh_per_se);
984 properties->simdPerComputeUnit = 4;
985 properties->wavefrontsPerSimd =
986 pdevice->rad_info.family == CHIP_TONGA ||
987 pdevice->rad_info.family == CHIP_ICELAND ||
988 pdevice->rad_info.family == CHIP_POLARIS10 ||
989 pdevice->rad_info.family == CHIP_POLARIS11 ||
990 pdevice->rad_info.family == CHIP_POLARIS12 ? 8 : 10;
991 properties->wavefrontSize = 64;
992
993 /* SGPR. */
994 properties->sgprsPerSimd =
995 radv_get_num_physical_sgprs(pdevice);
996 properties->minSgprAllocation =
997 pdevice->rad_info.chip_class >= VI ? 16 : 8;
998 properties->maxSgprAllocation =
999 pdevice->rad_info.family == CHIP_TONGA ||
1000 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1001 properties->sgprAllocationGranularity =
1002 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1003
1004 /* VGPR. */
1005 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1006 properties->minVgprAllocation = 4;
1007 properties->maxVgprAllocation = 256;
1008 properties->vgprAllocationGranularity = 4;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1012 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1013 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1014 properties->maxVertexAttribDivisor = UINT32_MAX;
1015 break;
1016 }
1017 default:
1018 break;
1019 }
1020 }
1021 }
1022
1023 static void radv_get_physical_device_queue_family_properties(
1024 struct radv_physical_device* pdevice,
1025 uint32_t* pCount,
1026 VkQueueFamilyProperties** pQueueFamilyProperties)
1027 {
1028 int num_queue_families = 1;
1029 int idx;
1030 if (pdevice->rad_info.num_compute_rings > 0 &&
1031 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1032 num_queue_families++;
1033
1034 if (pQueueFamilyProperties == NULL) {
1035 *pCount = num_queue_families;
1036 return;
1037 }
1038
1039 if (!*pCount)
1040 return;
1041
1042 idx = 0;
1043 if (*pCount >= 1) {
1044 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1045 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1046 VK_QUEUE_COMPUTE_BIT |
1047 VK_QUEUE_TRANSFER_BIT |
1048 VK_QUEUE_SPARSE_BINDING_BIT,
1049 .queueCount = 1,
1050 .timestampValidBits = 64,
1051 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1052 };
1053 idx++;
1054 }
1055
1056 if (pdevice->rad_info.num_compute_rings > 0 &&
1057 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1058 if (*pCount > idx) {
1059 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1060 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1061 VK_QUEUE_TRANSFER_BIT |
1062 VK_QUEUE_SPARSE_BINDING_BIT,
1063 .queueCount = pdevice->rad_info.num_compute_rings,
1064 .timestampValidBits = 64,
1065 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1066 };
1067 idx++;
1068 }
1069 }
1070 *pCount = idx;
1071 }
1072
1073 void radv_GetPhysicalDeviceQueueFamilyProperties(
1074 VkPhysicalDevice physicalDevice,
1075 uint32_t* pCount,
1076 VkQueueFamilyProperties* pQueueFamilyProperties)
1077 {
1078 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1079 if (!pQueueFamilyProperties) {
1080 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1081 return;
1082 }
1083 VkQueueFamilyProperties *properties[] = {
1084 pQueueFamilyProperties + 0,
1085 pQueueFamilyProperties + 1,
1086 pQueueFamilyProperties + 2,
1087 };
1088 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1089 assert(*pCount <= 3);
1090 }
1091
1092 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1093 VkPhysicalDevice physicalDevice,
1094 uint32_t* pCount,
1095 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1096 {
1097 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1098 if (!pQueueFamilyProperties) {
1099 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1100 return;
1101 }
1102 VkQueueFamilyProperties *properties[] = {
1103 &pQueueFamilyProperties[0].queueFamilyProperties,
1104 &pQueueFamilyProperties[1].queueFamilyProperties,
1105 &pQueueFamilyProperties[2].queueFamilyProperties,
1106 };
1107 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1108 assert(*pCount <= 3);
1109 }
1110
1111 void radv_GetPhysicalDeviceMemoryProperties(
1112 VkPhysicalDevice physicalDevice,
1113 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1114 {
1115 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1116
1117 *pMemoryProperties = physical_device->memory_properties;
1118 }
1119
1120 void radv_GetPhysicalDeviceMemoryProperties2(
1121 VkPhysicalDevice physicalDevice,
1122 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1123 {
1124 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1125 &pMemoryProperties->memoryProperties);
1126 }
1127
1128 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1129 VkDevice _device,
1130 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1131 const void *pHostPointer,
1132 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1133 {
1134 RADV_FROM_HANDLE(radv_device, device, _device);
1135
1136 switch (handleType)
1137 {
1138 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1139 const struct radv_physical_device *physical_device = device->physical_device;
1140 uint32_t memoryTypeBits = 0;
1141 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1142 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1143 memoryTypeBits = (1 << i);
1144 break;
1145 }
1146 }
1147 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1148 return VK_SUCCESS;
1149 }
1150 default:
1151 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1152 }
1153 }
1154
1155 static enum radeon_ctx_priority
1156 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1157 {
1158 /* Default to MEDIUM when a specific global priority isn't requested */
1159 if (!pObj)
1160 return RADEON_CTX_PRIORITY_MEDIUM;
1161
1162 switch(pObj->globalPriority) {
1163 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1164 return RADEON_CTX_PRIORITY_REALTIME;
1165 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1166 return RADEON_CTX_PRIORITY_HIGH;
1167 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1168 return RADEON_CTX_PRIORITY_MEDIUM;
1169 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1170 return RADEON_CTX_PRIORITY_LOW;
1171 default:
1172 unreachable("Illegal global priority value");
1173 return RADEON_CTX_PRIORITY_INVALID;
1174 }
1175 }
1176
1177 static int
1178 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1179 uint32_t queue_family_index, int idx,
1180 VkDeviceQueueCreateFlags flags,
1181 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1182 {
1183 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1184 queue->device = device;
1185 queue->queue_family_index = queue_family_index;
1186 queue->queue_idx = idx;
1187 queue->priority = radv_get_queue_global_priority(global_priority);
1188 queue->flags = flags;
1189
1190 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1191 if (!queue->hw_ctx)
1192 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1193
1194 return VK_SUCCESS;
1195 }
1196
1197 static void
1198 radv_queue_finish(struct radv_queue *queue)
1199 {
1200 if (queue->hw_ctx)
1201 queue->device->ws->ctx_destroy(queue->hw_ctx);
1202
1203 if (queue->initial_full_flush_preamble_cs)
1204 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1205 if (queue->initial_preamble_cs)
1206 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1207 if (queue->continue_preamble_cs)
1208 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1209 if (queue->descriptor_bo)
1210 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1211 if (queue->scratch_bo)
1212 queue->device->ws->buffer_destroy(queue->scratch_bo);
1213 if (queue->esgs_ring_bo)
1214 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1215 if (queue->gsvs_ring_bo)
1216 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1217 if (queue->tess_rings_bo)
1218 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1219 if (queue->compute_scratch_bo)
1220 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1221 }
1222
1223 static void
1224 radv_bo_list_init(struct radv_bo_list *bo_list)
1225 {
1226 pthread_mutex_init(&bo_list->mutex, NULL);
1227 bo_list->list.count = bo_list->capacity = 0;
1228 bo_list->list.bos = NULL;
1229 }
1230
1231 static void
1232 radv_bo_list_finish(struct radv_bo_list *bo_list)
1233 {
1234 free(bo_list->list.bos);
1235 pthread_mutex_destroy(&bo_list->mutex);
1236 }
1237
1238 static VkResult radv_bo_list_add(struct radv_bo_list *bo_list, struct radeon_winsys_bo *bo)
1239 {
1240 pthread_mutex_lock(&bo_list->mutex);
1241 if (bo_list->list.count == bo_list->capacity) {
1242 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1243 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1244
1245 if (!data) {
1246 pthread_mutex_unlock(&bo_list->mutex);
1247 return VK_ERROR_OUT_OF_HOST_MEMORY;
1248 }
1249
1250 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1251 bo_list->capacity = capacity;
1252 }
1253
1254 bo_list->list.bos[bo_list->list.count++] = bo;
1255 pthread_mutex_unlock(&bo_list->mutex);
1256 return VK_SUCCESS;
1257 }
1258
1259 static void radv_bo_list_remove(struct radv_bo_list *bo_list, struct radeon_winsys_bo *bo)
1260 {
1261 pthread_mutex_lock(&bo_list->mutex);
1262 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1263 if (bo_list->list.bos[i] == bo) {
1264 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1265 --bo_list->list.count;
1266 break;
1267 }
1268 }
1269 pthread_mutex_unlock(&bo_list->mutex);
1270 }
1271
1272 static void
1273 radv_device_init_gs_info(struct radv_device *device)
1274 {
1275 switch (device->physical_device->rad_info.family) {
1276 case CHIP_OLAND:
1277 case CHIP_HAINAN:
1278 case CHIP_KAVERI:
1279 case CHIP_KABINI:
1280 case CHIP_MULLINS:
1281 case CHIP_ICELAND:
1282 case CHIP_CARRIZO:
1283 case CHIP_STONEY:
1284 device->gs_table_depth = 16;
1285 return;
1286 case CHIP_TAHITI:
1287 case CHIP_PITCAIRN:
1288 case CHIP_VERDE:
1289 case CHIP_BONAIRE:
1290 case CHIP_HAWAII:
1291 case CHIP_TONGA:
1292 case CHIP_FIJI:
1293 case CHIP_POLARIS10:
1294 case CHIP_POLARIS11:
1295 case CHIP_POLARIS12:
1296 case CHIP_VEGA10:
1297 case CHIP_VEGA12:
1298 case CHIP_RAVEN:
1299 device->gs_table_depth = 32;
1300 return;
1301 default:
1302 unreachable("unknown GPU");
1303 }
1304 }
1305
1306 static int radv_get_device_extension_index(const char *name)
1307 {
1308 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1309 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1310 return i;
1311 }
1312 return -1;
1313 }
1314
1315 VkResult radv_CreateDevice(
1316 VkPhysicalDevice physicalDevice,
1317 const VkDeviceCreateInfo* pCreateInfo,
1318 const VkAllocationCallbacks* pAllocator,
1319 VkDevice* pDevice)
1320 {
1321 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1322 VkResult result;
1323 struct radv_device *device;
1324
1325 bool keep_shader_info = false;
1326
1327 /* Check enabled features */
1328 if (pCreateInfo->pEnabledFeatures) {
1329 VkPhysicalDeviceFeatures supported_features;
1330 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1331 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1332 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1333 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1334 for (uint32_t i = 0; i < num_features; i++) {
1335 if (enabled_feature[i] && !supported_feature[i])
1336 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1337 }
1338 }
1339
1340 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1341 sizeof(*device), 8,
1342 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1343 if (!device)
1344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1345
1346 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1347 device->instance = physical_device->instance;
1348 device->physical_device = physical_device;
1349
1350 device->ws = physical_device->ws;
1351 if (pAllocator)
1352 device->alloc = *pAllocator;
1353 else
1354 device->alloc = physical_device->instance->alloc;
1355
1356 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1357 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1358 int index = radv_get_device_extension_index(ext_name);
1359 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1360 vk_free(&device->alloc, device);
1361 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1362 }
1363
1364 device->enabled_extensions.extensions[index] = true;
1365 }
1366
1367 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1368
1369 mtx_init(&device->shader_slab_mutex, mtx_plain);
1370 list_inithead(&device->shader_slabs);
1371
1372 radv_bo_list_init(&device->bo_list);
1373
1374 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1375 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1376 uint32_t qfi = queue_create->queueFamilyIndex;
1377 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1378 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1379
1380 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1381
1382 device->queues[qfi] = vk_alloc(&device->alloc,
1383 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1384 if (!device->queues[qfi]) {
1385 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1386 goto fail;
1387 }
1388
1389 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1390
1391 device->queue_count[qfi] = queue_create->queueCount;
1392
1393 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1394 result = radv_queue_init(device, &device->queues[qfi][q],
1395 qfi, q, queue_create->flags,
1396 global_priority);
1397 if (result != VK_SUCCESS)
1398 goto fail;
1399 }
1400 }
1401
1402 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1403 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1404
1405 /* Disabled and not implemented for now. */
1406 device->dfsm_allowed = device->pbb_allowed && false;
1407
1408 #ifdef ANDROID
1409 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1410 #endif
1411
1412 device->llvm_supports_spill = true;
1413
1414 /* The maximum number of scratch waves. Scratch space isn't divided
1415 * evenly between CUs. The number is only a function of the number of CUs.
1416 * We can decrease the constant to decrease the scratch buffer size.
1417 *
1418 * sctx->scratch_waves must be >= the maximum posible size of
1419 * 1 threadgroup, so that the hw doesn't hang from being unable
1420 * to start any.
1421 *
1422 * The recommended value is 4 per CU at most. Higher numbers don't
1423 * bring much benefit, but they still occupy chip resources (think
1424 * async compute). I've seen ~2% performance difference between 4 and 32.
1425 */
1426 uint32_t max_threads_per_block = 2048;
1427 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1428 max_threads_per_block / 64);
1429
1430 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1431
1432 if (device->physical_device->rad_info.chip_class >= CIK) {
1433 /* If the KMD allows it (there is a KMD hw register for it),
1434 * allow launching waves out-of-order.
1435 */
1436 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1437 }
1438
1439 radv_device_init_gs_info(device);
1440
1441 device->tess_offchip_block_dw_size =
1442 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1443 device->has_distributed_tess =
1444 device->physical_device->rad_info.chip_class >= VI &&
1445 device->physical_device->rad_info.max_se >= 2;
1446
1447 if (getenv("RADV_TRACE_FILE")) {
1448 const char *filename = getenv("RADV_TRACE_FILE");
1449
1450 keep_shader_info = true;
1451
1452 if (!radv_init_trace(device))
1453 goto fail;
1454
1455 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1456 radv_dump_enabled_options(device, stderr);
1457 }
1458
1459 device->keep_shader_info = keep_shader_info;
1460
1461 result = radv_device_init_meta(device);
1462 if (result != VK_SUCCESS)
1463 goto fail;
1464
1465 radv_device_init_msaa(device);
1466
1467 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1468 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1469 switch (family) {
1470 case RADV_QUEUE_GENERAL:
1471 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1472 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1473 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1474 break;
1475 case RADV_QUEUE_COMPUTE:
1476 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1477 radeon_emit(device->empty_cs[family], 0);
1478 break;
1479 }
1480 device->ws->cs_finalize(device->empty_cs[family]);
1481 }
1482
1483 if (device->physical_device->rad_info.chip_class >= CIK)
1484 cik_create_gfx_config(device);
1485
1486 VkPipelineCacheCreateInfo ci;
1487 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1488 ci.pNext = NULL;
1489 ci.flags = 0;
1490 ci.pInitialData = NULL;
1491 ci.initialDataSize = 0;
1492 VkPipelineCache pc;
1493 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1494 &ci, NULL, &pc);
1495 if (result != VK_SUCCESS)
1496 goto fail_meta;
1497
1498 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1499
1500 *pDevice = radv_device_to_handle(device);
1501 return VK_SUCCESS;
1502
1503 fail_meta:
1504 radv_device_finish_meta(device);
1505 fail:
1506 radv_bo_list_finish(&device->bo_list);
1507
1508 if (device->trace_bo)
1509 device->ws->buffer_destroy(device->trace_bo);
1510
1511 if (device->gfx_init)
1512 device->ws->buffer_destroy(device->gfx_init);
1513
1514 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1515 for (unsigned q = 0; q < device->queue_count[i]; q++)
1516 radv_queue_finish(&device->queues[i][q]);
1517 if (device->queue_count[i])
1518 vk_free(&device->alloc, device->queues[i]);
1519 }
1520
1521 vk_free(&device->alloc, device);
1522 return result;
1523 }
1524
1525 void radv_DestroyDevice(
1526 VkDevice _device,
1527 const VkAllocationCallbacks* pAllocator)
1528 {
1529 RADV_FROM_HANDLE(radv_device, device, _device);
1530
1531 if (!device)
1532 return;
1533
1534 if (device->trace_bo)
1535 device->ws->buffer_destroy(device->trace_bo);
1536
1537 if (device->gfx_init)
1538 device->ws->buffer_destroy(device->gfx_init);
1539
1540 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1541 for (unsigned q = 0; q < device->queue_count[i]; q++)
1542 radv_queue_finish(&device->queues[i][q]);
1543 if (device->queue_count[i])
1544 vk_free(&device->alloc, device->queues[i]);
1545 if (device->empty_cs[i])
1546 device->ws->cs_destroy(device->empty_cs[i]);
1547 }
1548 radv_device_finish_meta(device);
1549
1550 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1551 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1552
1553 radv_destroy_shader_slabs(device);
1554
1555 radv_bo_list_finish(&device->bo_list);
1556 vk_free(&device->alloc, device);
1557 }
1558
1559 VkResult radv_EnumerateInstanceLayerProperties(
1560 uint32_t* pPropertyCount,
1561 VkLayerProperties* pProperties)
1562 {
1563 if (pProperties == NULL) {
1564 *pPropertyCount = 0;
1565 return VK_SUCCESS;
1566 }
1567
1568 /* None supported at this time */
1569 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1570 }
1571
1572 VkResult radv_EnumerateDeviceLayerProperties(
1573 VkPhysicalDevice physicalDevice,
1574 uint32_t* pPropertyCount,
1575 VkLayerProperties* pProperties)
1576 {
1577 if (pProperties == NULL) {
1578 *pPropertyCount = 0;
1579 return VK_SUCCESS;
1580 }
1581
1582 /* None supported at this time */
1583 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1584 }
1585
1586 void radv_GetDeviceQueue2(
1587 VkDevice _device,
1588 const VkDeviceQueueInfo2* pQueueInfo,
1589 VkQueue* pQueue)
1590 {
1591 RADV_FROM_HANDLE(radv_device, device, _device);
1592 struct radv_queue *queue;
1593
1594 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1595 if (pQueueInfo->flags != queue->flags) {
1596 /* From the Vulkan 1.1.70 spec:
1597 *
1598 * "The queue returned by vkGetDeviceQueue2 must have the same
1599 * flags value from this structure as that used at device
1600 * creation time in a VkDeviceQueueCreateInfo instance. If no
1601 * matching flags were specified at device creation time then
1602 * pQueue will return VK_NULL_HANDLE."
1603 */
1604 *pQueue = VK_NULL_HANDLE;
1605 return;
1606 }
1607
1608 *pQueue = radv_queue_to_handle(queue);
1609 }
1610
1611 void radv_GetDeviceQueue(
1612 VkDevice _device,
1613 uint32_t queueFamilyIndex,
1614 uint32_t queueIndex,
1615 VkQueue* pQueue)
1616 {
1617 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1618 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1619 .queueFamilyIndex = queueFamilyIndex,
1620 .queueIndex = queueIndex
1621 };
1622
1623 radv_GetDeviceQueue2(_device, &info, pQueue);
1624 }
1625
1626 static void
1627 fill_geom_tess_rings(struct radv_queue *queue,
1628 uint32_t *map,
1629 bool add_sample_positions,
1630 uint32_t esgs_ring_size,
1631 struct radeon_winsys_bo *esgs_ring_bo,
1632 uint32_t gsvs_ring_size,
1633 struct radeon_winsys_bo *gsvs_ring_bo,
1634 uint32_t tess_factor_ring_size,
1635 uint32_t tess_offchip_ring_offset,
1636 uint32_t tess_offchip_ring_size,
1637 struct radeon_winsys_bo *tess_rings_bo)
1638 {
1639 uint64_t esgs_va = 0, gsvs_va = 0;
1640 uint64_t tess_va = 0, tess_offchip_va = 0;
1641 uint32_t *desc = &map[4];
1642
1643 if (esgs_ring_bo)
1644 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1645 if (gsvs_ring_bo)
1646 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1647 if (tess_rings_bo) {
1648 tess_va = radv_buffer_get_va(tess_rings_bo);
1649 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1650 }
1651
1652 /* stride 0, num records - size, add tid, swizzle, elsize4,
1653 index stride 64 */
1654 desc[0] = esgs_va;
1655 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1656 S_008F04_STRIDE(0) |
1657 S_008F04_SWIZZLE_ENABLE(true);
1658 desc[2] = esgs_ring_size;
1659 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1660 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1661 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1662 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1663 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1664 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1665 S_008F0C_ELEMENT_SIZE(1) |
1666 S_008F0C_INDEX_STRIDE(3) |
1667 S_008F0C_ADD_TID_ENABLE(true);
1668
1669 desc += 4;
1670 /* GS entry for ES->GS ring */
1671 /* stride 0, num records - size, elsize0,
1672 index stride 0 */
1673 desc[0] = esgs_va;
1674 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1675 S_008F04_STRIDE(0) |
1676 S_008F04_SWIZZLE_ENABLE(false);
1677 desc[2] = esgs_ring_size;
1678 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1679 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1680 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1681 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1682 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1683 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1684 S_008F0C_ELEMENT_SIZE(0) |
1685 S_008F0C_INDEX_STRIDE(0) |
1686 S_008F0C_ADD_TID_ENABLE(false);
1687
1688 desc += 4;
1689 /* VS entry for GS->VS ring */
1690 /* stride 0, num records - size, elsize0,
1691 index stride 0 */
1692 desc[0] = gsvs_va;
1693 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1694 S_008F04_STRIDE(0) |
1695 S_008F04_SWIZZLE_ENABLE(false);
1696 desc[2] = gsvs_ring_size;
1697 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1698 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1699 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1700 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1701 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1702 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1703 S_008F0C_ELEMENT_SIZE(0) |
1704 S_008F0C_INDEX_STRIDE(0) |
1705 S_008F0C_ADD_TID_ENABLE(false);
1706 desc += 4;
1707
1708 /* stride gsvs_itemsize, num records 64
1709 elsize 4, index stride 16 */
1710 /* shader will patch stride and desc[2] */
1711 desc[0] = gsvs_va;
1712 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1713 S_008F04_STRIDE(0) |
1714 S_008F04_SWIZZLE_ENABLE(true);
1715 desc[2] = 0;
1716 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1717 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1718 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1719 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1720 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1721 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1722 S_008F0C_ELEMENT_SIZE(1) |
1723 S_008F0C_INDEX_STRIDE(1) |
1724 S_008F0C_ADD_TID_ENABLE(true);
1725 desc += 4;
1726
1727 desc[0] = tess_va;
1728 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1729 S_008F04_STRIDE(0) |
1730 S_008F04_SWIZZLE_ENABLE(false);
1731 desc[2] = tess_factor_ring_size;
1732 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1733 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1734 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1735 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1736 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1737 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1738 S_008F0C_ELEMENT_SIZE(0) |
1739 S_008F0C_INDEX_STRIDE(0) |
1740 S_008F0C_ADD_TID_ENABLE(false);
1741 desc += 4;
1742
1743 desc[0] = tess_offchip_va;
1744 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1745 S_008F04_STRIDE(0) |
1746 S_008F04_SWIZZLE_ENABLE(false);
1747 desc[2] = tess_offchip_ring_size;
1748 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1749 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1750 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1751 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1752 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1753 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1754 S_008F0C_ELEMENT_SIZE(0) |
1755 S_008F0C_INDEX_STRIDE(0) |
1756 S_008F0C_ADD_TID_ENABLE(false);
1757 desc += 4;
1758
1759 /* add sample positions after all rings */
1760 memcpy(desc, queue->device->sample_locations_1x, 8);
1761 desc += 2;
1762 memcpy(desc, queue->device->sample_locations_2x, 16);
1763 desc += 4;
1764 memcpy(desc, queue->device->sample_locations_4x, 32);
1765 desc += 8;
1766 memcpy(desc, queue->device->sample_locations_8x, 64);
1767 desc += 16;
1768 memcpy(desc, queue->device->sample_locations_16x, 128);
1769 }
1770
1771 static unsigned
1772 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1773 {
1774 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1775 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1776 device->physical_device->rad_info.family != CHIP_STONEY;
1777 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1778 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1779 device->physical_device->rad_info.max_se;
1780 unsigned offchip_granularity;
1781 unsigned hs_offchip_param;
1782 switch (device->tess_offchip_block_dw_size) {
1783 default:
1784 assert(0);
1785 /* fall through */
1786 case 8192:
1787 offchip_granularity = V_03093C_X_8K_DWORDS;
1788 break;
1789 case 4096:
1790 offchip_granularity = V_03093C_X_4K_DWORDS;
1791 break;
1792 }
1793
1794 switch (device->physical_device->rad_info.chip_class) {
1795 case SI:
1796 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1797 break;
1798 case CIK:
1799 case VI:
1800 case GFX9:
1801 default:
1802 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1803 break;
1804 }
1805
1806 *max_offchip_buffers_p = max_offchip_buffers;
1807 if (device->physical_device->rad_info.chip_class >= CIK) {
1808 if (device->physical_device->rad_info.chip_class >= VI)
1809 --max_offchip_buffers;
1810 hs_offchip_param =
1811 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1812 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1813 } else {
1814 hs_offchip_param =
1815 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1816 }
1817 return hs_offchip_param;
1818 }
1819
1820 static VkResult
1821 radv_get_preamble_cs(struct radv_queue *queue,
1822 uint32_t scratch_size,
1823 uint32_t compute_scratch_size,
1824 uint32_t esgs_ring_size,
1825 uint32_t gsvs_ring_size,
1826 bool needs_tess_rings,
1827 bool needs_sample_positions,
1828 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1829 struct radeon_winsys_cs **initial_preamble_cs,
1830 struct radeon_winsys_cs **continue_preamble_cs)
1831 {
1832 struct radeon_winsys_bo *scratch_bo = NULL;
1833 struct radeon_winsys_bo *descriptor_bo = NULL;
1834 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1835 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1836 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1837 struct radeon_winsys_bo *tess_rings_bo = NULL;
1838 struct radeon_winsys_cs *dest_cs[3] = {0};
1839 bool add_tess_rings = false, add_sample_positions = false;
1840 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1841 unsigned max_offchip_buffers;
1842 unsigned hs_offchip_param = 0;
1843 unsigned tess_offchip_ring_offset;
1844 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1845 if (!queue->has_tess_rings) {
1846 if (needs_tess_rings)
1847 add_tess_rings = true;
1848 }
1849 if (!queue->has_sample_positions) {
1850 if (needs_sample_positions)
1851 add_sample_positions = true;
1852 }
1853 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1854 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1855 &max_offchip_buffers);
1856 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1857 tess_offchip_ring_size = max_offchip_buffers *
1858 queue->device->tess_offchip_block_dw_size * 4;
1859
1860 if (scratch_size <= queue->scratch_size &&
1861 compute_scratch_size <= queue->compute_scratch_size &&
1862 esgs_ring_size <= queue->esgs_ring_size &&
1863 gsvs_ring_size <= queue->gsvs_ring_size &&
1864 !add_tess_rings && !add_sample_positions &&
1865 queue->initial_preamble_cs) {
1866 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1867 *initial_preamble_cs = queue->initial_preamble_cs;
1868 *continue_preamble_cs = queue->continue_preamble_cs;
1869 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1870 *continue_preamble_cs = NULL;
1871 return VK_SUCCESS;
1872 }
1873
1874 if (scratch_size > queue->scratch_size) {
1875 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1876 scratch_size,
1877 4096,
1878 RADEON_DOMAIN_VRAM,
1879 ring_bo_flags);
1880 if (!scratch_bo)
1881 goto fail;
1882 } else
1883 scratch_bo = queue->scratch_bo;
1884
1885 if (compute_scratch_size > queue->compute_scratch_size) {
1886 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1887 compute_scratch_size,
1888 4096,
1889 RADEON_DOMAIN_VRAM,
1890 ring_bo_flags);
1891 if (!compute_scratch_bo)
1892 goto fail;
1893
1894 } else
1895 compute_scratch_bo = queue->compute_scratch_bo;
1896
1897 if (esgs_ring_size > queue->esgs_ring_size) {
1898 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1899 esgs_ring_size,
1900 4096,
1901 RADEON_DOMAIN_VRAM,
1902 ring_bo_flags);
1903 if (!esgs_ring_bo)
1904 goto fail;
1905 } else {
1906 esgs_ring_bo = queue->esgs_ring_bo;
1907 esgs_ring_size = queue->esgs_ring_size;
1908 }
1909
1910 if (gsvs_ring_size > queue->gsvs_ring_size) {
1911 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1912 gsvs_ring_size,
1913 4096,
1914 RADEON_DOMAIN_VRAM,
1915 ring_bo_flags);
1916 if (!gsvs_ring_bo)
1917 goto fail;
1918 } else {
1919 gsvs_ring_bo = queue->gsvs_ring_bo;
1920 gsvs_ring_size = queue->gsvs_ring_size;
1921 }
1922
1923 if (add_tess_rings) {
1924 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1925 tess_offchip_ring_offset + tess_offchip_ring_size,
1926 256,
1927 RADEON_DOMAIN_VRAM,
1928 ring_bo_flags);
1929 if (!tess_rings_bo)
1930 goto fail;
1931 } else {
1932 tess_rings_bo = queue->tess_rings_bo;
1933 }
1934
1935 if (scratch_bo != queue->scratch_bo ||
1936 esgs_ring_bo != queue->esgs_ring_bo ||
1937 gsvs_ring_bo != queue->gsvs_ring_bo ||
1938 tess_rings_bo != queue->tess_rings_bo ||
1939 add_sample_positions) {
1940 uint32_t size = 0;
1941 if (gsvs_ring_bo || esgs_ring_bo ||
1942 tess_rings_bo || add_sample_positions) {
1943 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1944 if (add_sample_positions)
1945 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1946 }
1947 else if (scratch_bo)
1948 size = 8; /* 2 dword */
1949
1950 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1951 size,
1952 4096,
1953 RADEON_DOMAIN_VRAM,
1954 RADEON_FLAG_CPU_ACCESS |
1955 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1956 RADEON_FLAG_READ_ONLY);
1957 if (!descriptor_bo)
1958 goto fail;
1959 } else
1960 descriptor_bo = queue->descriptor_bo;
1961
1962 for(int i = 0; i < 3; ++i) {
1963 struct radeon_winsys_cs *cs = NULL;
1964 cs = queue->device->ws->cs_create(queue->device->ws,
1965 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1966 if (!cs)
1967 goto fail;
1968
1969 dest_cs[i] = cs;
1970
1971 if (scratch_bo)
1972 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1973
1974 if (esgs_ring_bo)
1975 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1976
1977 if (gsvs_ring_bo)
1978 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1979
1980 if (tess_rings_bo)
1981 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1982
1983 if (descriptor_bo)
1984 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1985
1986 if (descriptor_bo != queue->descriptor_bo) {
1987 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1988
1989 if (scratch_bo) {
1990 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1991 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1992 S_008F04_SWIZZLE_ENABLE(1);
1993 map[0] = scratch_va;
1994 map[1] = rsrc1;
1995 }
1996
1997 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
1998 add_sample_positions)
1999 fill_geom_tess_rings(queue, map, add_sample_positions,
2000 esgs_ring_size, esgs_ring_bo,
2001 gsvs_ring_size, gsvs_ring_bo,
2002 tess_factor_ring_size,
2003 tess_offchip_ring_offset,
2004 tess_offchip_ring_size,
2005 tess_rings_bo);
2006
2007 queue->device->ws->buffer_unmap(descriptor_bo);
2008 }
2009
2010 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2011 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2012 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2013 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2014 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2015 }
2016
2017 if (esgs_ring_bo || gsvs_ring_bo) {
2018 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2019 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2020 radeon_emit(cs, esgs_ring_size >> 8);
2021 radeon_emit(cs, gsvs_ring_size >> 8);
2022 } else {
2023 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2024 radeon_emit(cs, esgs_ring_size >> 8);
2025 radeon_emit(cs, gsvs_ring_size >> 8);
2026 }
2027 }
2028
2029 if (tess_rings_bo) {
2030 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
2031 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2032 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2033 S_030938_SIZE(tess_factor_ring_size / 4));
2034 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2035 tf_va >> 8);
2036 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2037 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2038 S_030944_BASE_HI(tf_va >> 40));
2039 }
2040 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
2041 } else {
2042 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2043 S_008988_SIZE(tess_factor_ring_size / 4));
2044 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2045 tf_va >> 8);
2046 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2047 hs_offchip_param);
2048 }
2049 }
2050
2051 if (descriptor_bo) {
2052 uint64_t va = radv_buffer_get_va(descriptor_bo);
2053 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2054 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2055 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2056 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2057 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2058
2059 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2060 radeon_set_sh_reg_seq(cs, regs[i], 2);
2061 radeon_emit(cs, va);
2062 radeon_emit(cs, va >> 32);
2063 }
2064 } else {
2065 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2066 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2067 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2068 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2069 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2070 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2071
2072 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2073 radeon_set_sh_reg_seq(cs, regs[i], 2);
2074 radeon_emit(cs, va);
2075 radeon_emit(cs, va >> 32);
2076 }
2077 }
2078 }
2079
2080 if (compute_scratch_bo) {
2081 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
2082 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2083 S_008F04_SWIZZLE_ENABLE(1);
2084
2085 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
2086
2087 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2088 radeon_emit(cs, scratch_va);
2089 radeon_emit(cs, rsrc1);
2090 }
2091
2092 if (i == 0) {
2093 si_cs_emit_cache_flush(cs,
2094 queue->device->physical_device->rad_info.chip_class,
2095 NULL, 0,
2096 queue->queue_family_index == RING_COMPUTE &&
2097 queue->device->physical_device->rad_info.chip_class >= CIK,
2098 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2099 RADV_CMD_FLAG_INV_ICACHE |
2100 RADV_CMD_FLAG_INV_SMEM_L1 |
2101 RADV_CMD_FLAG_INV_VMEM_L1 |
2102 RADV_CMD_FLAG_INV_GLOBAL_L2);
2103 } else if (i == 1) {
2104 si_cs_emit_cache_flush(cs,
2105 queue->device->physical_device->rad_info.chip_class,
2106 NULL, 0,
2107 queue->queue_family_index == RING_COMPUTE &&
2108 queue->device->physical_device->rad_info.chip_class >= CIK,
2109 RADV_CMD_FLAG_INV_ICACHE |
2110 RADV_CMD_FLAG_INV_SMEM_L1 |
2111 RADV_CMD_FLAG_INV_VMEM_L1 |
2112 RADV_CMD_FLAG_INV_GLOBAL_L2);
2113 }
2114
2115 if (!queue->device->ws->cs_finalize(cs))
2116 goto fail;
2117 }
2118
2119 if (queue->initial_full_flush_preamble_cs)
2120 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2121
2122 if (queue->initial_preamble_cs)
2123 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2124
2125 if (queue->continue_preamble_cs)
2126 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2127
2128 queue->initial_full_flush_preamble_cs = dest_cs[0];
2129 queue->initial_preamble_cs = dest_cs[1];
2130 queue->continue_preamble_cs = dest_cs[2];
2131
2132 if (scratch_bo != queue->scratch_bo) {
2133 if (queue->scratch_bo)
2134 queue->device->ws->buffer_destroy(queue->scratch_bo);
2135 queue->scratch_bo = scratch_bo;
2136 queue->scratch_size = scratch_size;
2137 }
2138
2139 if (compute_scratch_bo != queue->compute_scratch_bo) {
2140 if (queue->compute_scratch_bo)
2141 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2142 queue->compute_scratch_bo = compute_scratch_bo;
2143 queue->compute_scratch_size = compute_scratch_size;
2144 }
2145
2146 if (esgs_ring_bo != queue->esgs_ring_bo) {
2147 if (queue->esgs_ring_bo)
2148 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2149 queue->esgs_ring_bo = esgs_ring_bo;
2150 queue->esgs_ring_size = esgs_ring_size;
2151 }
2152
2153 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2154 if (queue->gsvs_ring_bo)
2155 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2156 queue->gsvs_ring_bo = gsvs_ring_bo;
2157 queue->gsvs_ring_size = gsvs_ring_size;
2158 }
2159
2160 if (tess_rings_bo != queue->tess_rings_bo) {
2161 queue->tess_rings_bo = tess_rings_bo;
2162 queue->has_tess_rings = true;
2163 }
2164
2165 if (descriptor_bo != queue->descriptor_bo) {
2166 if (queue->descriptor_bo)
2167 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2168
2169 queue->descriptor_bo = descriptor_bo;
2170 }
2171
2172 if (add_sample_positions)
2173 queue->has_sample_positions = true;
2174
2175 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2176 *initial_preamble_cs = queue->initial_preamble_cs;
2177 *continue_preamble_cs = queue->continue_preamble_cs;
2178 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2179 *continue_preamble_cs = NULL;
2180 return VK_SUCCESS;
2181 fail:
2182 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2183 if (dest_cs[i])
2184 queue->device->ws->cs_destroy(dest_cs[i]);
2185 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2186 queue->device->ws->buffer_destroy(descriptor_bo);
2187 if (scratch_bo && scratch_bo != queue->scratch_bo)
2188 queue->device->ws->buffer_destroy(scratch_bo);
2189 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2190 queue->device->ws->buffer_destroy(compute_scratch_bo);
2191 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2192 queue->device->ws->buffer_destroy(esgs_ring_bo);
2193 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2194 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2195 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2196 queue->device->ws->buffer_destroy(tess_rings_bo);
2197 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2198 }
2199
2200 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2201 int num_sems,
2202 const VkSemaphore *sems,
2203 VkFence _fence,
2204 bool reset_temp)
2205 {
2206 int syncobj_idx = 0, sem_idx = 0;
2207
2208 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2209 return VK_SUCCESS;
2210
2211 for (uint32_t i = 0; i < num_sems; i++) {
2212 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2213
2214 if (sem->temp_syncobj || sem->syncobj)
2215 counts->syncobj_count++;
2216 else
2217 counts->sem_count++;
2218 }
2219
2220 if (_fence != VK_NULL_HANDLE) {
2221 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2222 if (fence->temp_syncobj || fence->syncobj)
2223 counts->syncobj_count++;
2224 }
2225
2226 if (counts->syncobj_count) {
2227 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2228 if (!counts->syncobj)
2229 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2230 }
2231
2232 if (counts->sem_count) {
2233 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2234 if (!counts->sem) {
2235 free(counts->syncobj);
2236 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2237 }
2238 }
2239
2240 for (uint32_t i = 0; i < num_sems; i++) {
2241 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2242
2243 if (sem->temp_syncobj) {
2244 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2245 }
2246 else if (sem->syncobj)
2247 counts->syncobj[syncobj_idx++] = sem->syncobj;
2248 else {
2249 assert(sem->sem);
2250 counts->sem[sem_idx++] = sem->sem;
2251 }
2252 }
2253
2254 if (_fence != VK_NULL_HANDLE) {
2255 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2256 if (fence->temp_syncobj)
2257 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2258 else if (fence->syncobj)
2259 counts->syncobj[syncobj_idx++] = fence->syncobj;
2260 }
2261
2262 return VK_SUCCESS;
2263 }
2264
2265 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2266 {
2267 free(sem_info->wait.syncobj);
2268 free(sem_info->wait.sem);
2269 free(sem_info->signal.syncobj);
2270 free(sem_info->signal.sem);
2271 }
2272
2273
2274 static void radv_free_temp_syncobjs(struct radv_device *device,
2275 int num_sems,
2276 const VkSemaphore *sems)
2277 {
2278 for (uint32_t i = 0; i < num_sems; i++) {
2279 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2280
2281 if (sem->temp_syncobj) {
2282 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2283 sem->temp_syncobj = 0;
2284 }
2285 }
2286 }
2287
2288 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2289 int num_wait_sems,
2290 const VkSemaphore *wait_sems,
2291 int num_signal_sems,
2292 const VkSemaphore *signal_sems,
2293 VkFence fence)
2294 {
2295 VkResult ret;
2296 memset(sem_info, 0, sizeof(*sem_info));
2297
2298 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2299 if (ret)
2300 return ret;
2301 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2302 if (ret)
2303 radv_free_sem_info(sem_info);
2304
2305 /* caller can override these */
2306 sem_info->cs_emit_wait = true;
2307 sem_info->cs_emit_signal = true;
2308 return ret;
2309 }
2310
2311 /* Signals fence as soon as all the work currently put on queue is done. */
2312 static VkResult radv_signal_fence(struct radv_queue *queue,
2313 struct radv_fence *fence)
2314 {
2315 int ret;
2316 VkResult result;
2317 struct radv_winsys_sem_info sem_info;
2318
2319 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2320 radv_fence_to_handle(fence));
2321 if (result != VK_SUCCESS)
2322 return result;
2323
2324 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2325 &queue->device->empty_cs[queue->queue_family_index],
2326 1, NULL, NULL, &sem_info, NULL,
2327 false, fence->fence);
2328 radv_free_sem_info(&sem_info);
2329
2330 /* TODO: find a better error */
2331 if (ret)
2332 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2333
2334 return VK_SUCCESS;
2335 }
2336
2337 VkResult radv_QueueSubmit(
2338 VkQueue _queue,
2339 uint32_t submitCount,
2340 const VkSubmitInfo* pSubmits,
2341 VkFence _fence)
2342 {
2343 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2344 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2345 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2346 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2347 int ret;
2348 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2349 uint32_t scratch_size = 0;
2350 uint32_t compute_scratch_size = 0;
2351 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2352 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2353 VkResult result;
2354 bool fence_emitted = false;
2355 bool tess_rings_needed = false;
2356 bool sample_positions_needed = false;
2357
2358 /* Do this first so failing to allocate scratch buffers can't result in
2359 * partially executed submissions. */
2360 for (uint32_t i = 0; i < submitCount; i++) {
2361 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2362 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2363 pSubmits[i].pCommandBuffers[j]);
2364
2365 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2366 compute_scratch_size = MAX2(compute_scratch_size,
2367 cmd_buffer->compute_scratch_size_needed);
2368 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2369 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2370 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2371 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2372 }
2373 }
2374
2375 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2376 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2377 sample_positions_needed, &initial_flush_preamble_cs,
2378 &initial_preamble_cs, &continue_preamble_cs);
2379 if (result != VK_SUCCESS)
2380 return result;
2381
2382 for (uint32_t i = 0; i < submitCount; i++) {
2383 struct radeon_winsys_cs **cs_array;
2384 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2385 bool can_patch = true;
2386 uint32_t advance;
2387 struct radv_winsys_sem_info sem_info;
2388
2389 result = radv_alloc_sem_info(&sem_info,
2390 pSubmits[i].waitSemaphoreCount,
2391 pSubmits[i].pWaitSemaphores,
2392 pSubmits[i].signalSemaphoreCount,
2393 pSubmits[i].pSignalSemaphores,
2394 _fence);
2395 if (result != VK_SUCCESS)
2396 return result;
2397
2398 if (!pSubmits[i].commandBufferCount) {
2399 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2400 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2401 &queue->device->empty_cs[queue->queue_family_index],
2402 1, NULL, NULL,
2403 &sem_info, NULL,
2404 false, base_fence);
2405 if (ret) {
2406 radv_loge("failed to submit CS %d\n", i);
2407 abort();
2408 }
2409 fence_emitted = true;
2410 }
2411 radv_free_sem_info(&sem_info);
2412 continue;
2413 }
2414
2415 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2416 (pSubmits[i].commandBufferCount));
2417
2418 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2419 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2420 pSubmits[i].pCommandBuffers[j]);
2421 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2422
2423 cs_array[j] = cmd_buffer->cs;
2424 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2425 can_patch = false;
2426
2427 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2428 }
2429
2430 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2431 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2432 advance = MIN2(max_cs_submission,
2433 pSubmits[i].commandBufferCount - j);
2434
2435 if (queue->device->trace_bo)
2436 *queue->device->trace_id_ptr = 0;
2437
2438 sem_info.cs_emit_wait = j == 0;
2439 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2440
2441 pthread_mutex_lock(&queue->device->bo_list.mutex);
2442
2443 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2444 advance, initial_preamble, continue_preamble_cs,
2445 &sem_info, &queue->device->bo_list.list,
2446 can_patch, base_fence);
2447
2448 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2449
2450 if (ret) {
2451 radv_loge("failed to submit CS %d\n", i);
2452 abort();
2453 }
2454 fence_emitted = true;
2455 if (queue->device->trace_bo) {
2456 radv_check_gpu_hangs(queue, cs_array[j]);
2457 }
2458 }
2459
2460 radv_free_temp_syncobjs(queue->device,
2461 pSubmits[i].waitSemaphoreCount,
2462 pSubmits[i].pWaitSemaphores);
2463 radv_free_sem_info(&sem_info);
2464 free(cs_array);
2465 }
2466
2467 if (fence) {
2468 if (!fence_emitted) {
2469 radv_signal_fence(queue, fence);
2470 }
2471 fence->submitted = true;
2472 }
2473
2474 return VK_SUCCESS;
2475 }
2476
2477 VkResult radv_QueueWaitIdle(
2478 VkQueue _queue)
2479 {
2480 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2481
2482 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2483 radv_queue_family_to_ring(queue->queue_family_index),
2484 queue->queue_idx);
2485 return VK_SUCCESS;
2486 }
2487
2488 VkResult radv_DeviceWaitIdle(
2489 VkDevice _device)
2490 {
2491 RADV_FROM_HANDLE(radv_device, device, _device);
2492
2493 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2494 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2495 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2496 }
2497 }
2498 return VK_SUCCESS;
2499 }
2500
2501 VkResult radv_EnumerateInstanceExtensionProperties(
2502 const char* pLayerName,
2503 uint32_t* pPropertyCount,
2504 VkExtensionProperties* pProperties)
2505 {
2506 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2507
2508 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2509 if (radv_supported_instance_extensions.extensions[i]) {
2510 vk_outarray_append(&out, prop) {
2511 *prop = radv_instance_extensions[i];
2512 }
2513 }
2514 }
2515
2516 return vk_outarray_status(&out);
2517 }
2518
2519 VkResult radv_EnumerateDeviceExtensionProperties(
2520 VkPhysicalDevice physicalDevice,
2521 const char* pLayerName,
2522 uint32_t* pPropertyCount,
2523 VkExtensionProperties* pProperties)
2524 {
2525 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2526 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2527
2528 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2529 if (device->supported_extensions.extensions[i]) {
2530 vk_outarray_append(&out, prop) {
2531 *prop = radv_device_extensions[i];
2532 }
2533 }
2534 }
2535
2536 return vk_outarray_status(&out);
2537 }
2538
2539 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2540 VkInstance _instance,
2541 const char* pName)
2542 {
2543 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2544
2545 return radv_lookup_entrypoint_checked(pName,
2546 instance ? instance->apiVersion : 0,
2547 instance ? &instance->enabled_extensions : NULL,
2548 NULL);
2549 }
2550
2551 /* The loader wants us to expose a second GetInstanceProcAddr function
2552 * to work around certain LD_PRELOAD issues seen in apps.
2553 */
2554 PUBLIC
2555 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2556 VkInstance instance,
2557 const char* pName);
2558
2559 PUBLIC
2560 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2561 VkInstance instance,
2562 const char* pName)
2563 {
2564 return radv_GetInstanceProcAddr(instance, pName);
2565 }
2566
2567 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2568 VkDevice _device,
2569 const char* pName)
2570 {
2571 RADV_FROM_HANDLE(radv_device, device, _device);
2572
2573 return radv_lookup_entrypoint_checked(pName,
2574 device->instance->apiVersion,
2575 &device->instance->enabled_extensions,
2576 &device->enabled_extensions);
2577 }
2578
2579 bool radv_get_memory_fd(struct radv_device *device,
2580 struct radv_device_memory *memory,
2581 int *pFD)
2582 {
2583 struct radeon_bo_metadata metadata;
2584
2585 if (memory->image) {
2586 radv_init_metadata(device, memory->image, &metadata);
2587 device->ws->buffer_set_metadata(memory->bo, &metadata);
2588 }
2589
2590 return device->ws->buffer_get_fd(device->ws, memory->bo,
2591 pFD);
2592 }
2593
2594 static VkResult radv_alloc_memory(struct radv_device *device,
2595 const VkMemoryAllocateInfo* pAllocateInfo,
2596 const VkAllocationCallbacks* pAllocator,
2597 VkDeviceMemory* pMem)
2598 {
2599 struct radv_device_memory *mem;
2600 VkResult result;
2601 enum radeon_bo_domain domain;
2602 uint32_t flags = 0;
2603 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2604
2605 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2606
2607 if (pAllocateInfo->allocationSize == 0) {
2608 /* Apparently, this is allowed */
2609 *pMem = VK_NULL_HANDLE;
2610 return VK_SUCCESS;
2611 }
2612
2613 const VkImportMemoryFdInfoKHR *import_info =
2614 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2615 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2616 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2617 const VkExportMemoryAllocateInfoKHR *export_info =
2618 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2619 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2620 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2621
2622 const struct wsi_memory_allocate_info *wsi_info =
2623 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2624
2625 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2626 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2627 if (mem == NULL)
2628 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2629
2630 if (wsi_info && wsi_info->implicit_sync)
2631 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2632
2633 if (dedicate_info) {
2634 mem->image = radv_image_from_handle(dedicate_info->image);
2635 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2636 } else {
2637 mem->image = NULL;
2638 mem->buffer = NULL;
2639 }
2640
2641 mem->user_ptr = NULL;
2642
2643 if (import_info) {
2644 assert(import_info->handleType ==
2645 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2646 import_info->handleType ==
2647 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2648 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2649 NULL, NULL);
2650 if (!mem->bo) {
2651 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2652 goto fail;
2653 } else {
2654 close(import_info->fd);
2655 }
2656 } else if (host_ptr_info) {
2657 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2658 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2659 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2660 pAllocateInfo->allocationSize);
2661 if (!mem->bo) {
2662 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2663 goto fail;
2664 } else {
2665 mem->user_ptr = host_ptr_info->pHostPointer;
2666 }
2667 } else {
2668 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2669 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2670 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2671 domain = RADEON_DOMAIN_GTT;
2672 else
2673 domain = RADEON_DOMAIN_VRAM;
2674
2675 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2676 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2677 else
2678 flags |= RADEON_FLAG_CPU_ACCESS;
2679
2680 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2681 flags |= RADEON_FLAG_GTT_WC;
2682
2683 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2684 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2685
2686 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2687 domain, flags);
2688
2689 if (!mem->bo) {
2690 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2691 goto fail;
2692 }
2693 mem->type_index = mem_type_index;
2694 }
2695
2696 result = radv_bo_list_add(&device->bo_list, mem->bo);
2697 if (result != VK_SUCCESS)
2698 goto fail_bo;
2699
2700 *pMem = radv_device_memory_to_handle(mem);
2701
2702 return VK_SUCCESS;
2703
2704 fail_bo:
2705 device->ws->buffer_destroy(mem->bo);
2706 fail:
2707 vk_free2(&device->alloc, pAllocator, mem);
2708
2709 return result;
2710 }
2711
2712 VkResult radv_AllocateMemory(
2713 VkDevice _device,
2714 const VkMemoryAllocateInfo* pAllocateInfo,
2715 const VkAllocationCallbacks* pAllocator,
2716 VkDeviceMemory* pMem)
2717 {
2718 RADV_FROM_HANDLE(radv_device, device, _device);
2719 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2720 }
2721
2722 void radv_FreeMemory(
2723 VkDevice _device,
2724 VkDeviceMemory _mem,
2725 const VkAllocationCallbacks* pAllocator)
2726 {
2727 RADV_FROM_HANDLE(radv_device, device, _device);
2728 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2729
2730 if (mem == NULL)
2731 return;
2732
2733 radv_bo_list_remove(&device->bo_list, mem->bo);
2734 device->ws->buffer_destroy(mem->bo);
2735 mem->bo = NULL;
2736
2737 vk_free2(&device->alloc, pAllocator, mem);
2738 }
2739
2740 VkResult radv_MapMemory(
2741 VkDevice _device,
2742 VkDeviceMemory _memory,
2743 VkDeviceSize offset,
2744 VkDeviceSize size,
2745 VkMemoryMapFlags flags,
2746 void** ppData)
2747 {
2748 RADV_FROM_HANDLE(radv_device, device, _device);
2749 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2750
2751 if (mem == NULL) {
2752 *ppData = NULL;
2753 return VK_SUCCESS;
2754 }
2755
2756 if (mem->user_ptr)
2757 *ppData = mem->user_ptr;
2758 else
2759 *ppData = device->ws->buffer_map(mem->bo);
2760
2761 if (*ppData) {
2762 *ppData += offset;
2763 return VK_SUCCESS;
2764 }
2765
2766 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2767 }
2768
2769 void radv_UnmapMemory(
2770 VkDevice _device,
2771 VkDeviceMemory _memory)
2772 {
2773 RADV_FROM_HANDLE(radv_device, device, _device);
2774 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2775
2776 if (mem == NULL)
2777 return;
2778
2779 if (mem->user_ptr == NULL)
2780 device->ws->buffer_unmap(mem->bo);
2781 }
2782
2783 VkResult radv_FlushMappedMemoryRanges(
2784 VkDevice _device,
2785 uint32_t memoryRangeCount,
2786 const VkMappedMemoryRange* pMemoryRanges)
2787 {
2788 return VK_SUCCESS;
2789 }
2790
2791 VkResult radv_InvalidateMappedMemoryRanges(
2792 VkDevice _device,
2793 uint32_t memoryRangeCount,
2794 const VkMappedMemoryRange* pMemoryRanges)
2795 {
2796 return VK_SUCCESS;
2797 }
2798
2799 void radv_GetBufferMemoryRequirements(
2800 VkDevice _device,
2801 VkBuffer _buffer,
2802 VkMemoryRequirements* pMemoryRequirements)
2803 {
2804 RADV_FROM_HANDLE(radv_device, device, _device);
2805 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2806
2807 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2808
2809 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2810 pMemoryRequirements->alignment = 4096;
2811 else
2812 pMemoryRequirements->alignment = 16;
2813
2814 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2815 }
2816
2817 void radv_GetBufferMemoryRequirements2(
2818 VkDevice device,
2819 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2820 VkMemoryRequirements2KHR* pMemoryRequirements)
2821 {
2822 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2823 &pMemoryRequirements->memoryRequirements);
2824 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2825 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2826 switch (ext->sType) {
2827 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2828 VkMemoryDedicatedRequirementsKHR *req =
2829 (VkMemoryDedicatedRequirementsKHR *) ext;
2830 req->requiresDedicatedAllocation = buffer->shareable;
2831 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2832 break;
2833 }
2834 default:
2835 break;
2836 }
2837 }
2838 }
2839
2840 void radv_GetImageMemoryRequirements(
2841 VkDevice _device,
2842 VkImage _image,
2843 VkMemoryRequirements* pMemoryRequirements)
2844 {
2845 RADV_FROM_HANDLE(radv_device, device, _device);
2846 RADV_FROM_HANDLE(radv_image, image, _image);
2847
2848 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2849
2850 pMemoryRequirements->size = image->size;
2851 pMemoryRequirements->alignment = image->alignment;
2852 }
2853
2854 void radv_GetImageMemoryRequirements2(
2855 VkDevice device,
2856 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2857 VkMemoryRequirements2KHR* pMemoryRequirements)
2858 {
2859 radv_GetImageMemoryRequirements(device, pInfo->image,
2860 &pMemoryRequirements->memoryRequirements);
2861
2862 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2863
2864 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2865 switch (ext->sType) {
2866 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2867 VkMemoryDedicatedRequirementsKHR *req =
2868 (VkMemoryDedicatedRequirementsKHR *) ext;
2869 req->requiresDedicatedAllocation = image->shareable;
2870 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2871 break;
2872 }
2873 default:
2874 break;
2875 }
2876 }
2877 }
2878
2879 void radv_GetImageSparseMemoryRequirements(
2880 VkDevice device,
2881 VkImage image,
2882 uint32_t* pSparseMemoryRequirementCount,
2883 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2884 {
2885 stub();
2886 }
2887
2888 void radv_GetImageSparseMemoryRequirements2(
2889 VkDevice device,
2890 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2891 uint32_t* pSparseMemoryRequirementCount,
2892 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2893 {
2894 stub();
2895 }
2896
2897 void radv_GetDeviceMemoryCommitment(
2898 VkDevice device,
2899 VkDeviceMemory memory,
2900 VkDeviceSize* pCommittedMemoryInBytes)
2901 {
2902 *pCommittedMemoryInBytes = 0;
2903 }
2904
2905 VkResult radv_BindBufferMemory2(VkDevice device,
2906 uint32_t bindInfoCount,
2907 const VkBindBufferMemoryInfoKHR *pBindInfos)
2908 {
2909 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2910 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2911 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2912
2913 if (mem) {
2914 buffer->bo = mem->bo;
2915 buffer->offset = pBindInfos[i].memoryOffset;
2916 } else {
2917 buffer->bo = NULL;
2918 }
2919 }
2920 return VK_SUCCESS;
2921 }
2922
2923 VkResult radv_BindBufferMemory(
2924 VkDevice device,
2925 VkBuffer buffer,
2926 VkDeviceMemory memory,
2927 VkDeviceSize memoryOffset)
2928 {
2929 const VkBindBufferMemoryInfoKHR info = {
2930 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2931 .buffer = buffer,
2932 .memory = memory,
2933 .memoryOffset = memoryOffset
2934 };
2935
2936 return radv_BindBufferMemory2(device, 1, &info);
2937 }
2938
2939 VkResult radv_BindImageMemory2(VkDevice device,
2940 uint32_t bindInfoCount,
2941 const VkBindImageMemoryInfoKHR *pBindInfos)
2942 {
2943 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2944 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2945 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2946
2947 if (mem) {
2948 image->bo = mem->bo;
2949 image->offset = pBindInfos[i].memoryOffset;
2950 } else {
2951 image->bo = NULL;
2952 image->offset = 0;
2953 }
2954 }
2955 return VK_SUCCESS;
2956 }
2957
2958
2959 VkResult radv_BindImageMemory(
2960 VkDevice device,
2961 VkImage image,
2962 VkDeviceMemory memory,
2963 VkDeviceSize memoryOffset)
2964 {
2965 const VkBindImageMemoryInfoKHR info = {
2966 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2967 .image = image,
2968 .memory = memory,
2969 .memoryOffset = memoryOffset
2970 };
2971
2972 return radv_BindImageMemory2(device, 1, &info);
2973 }
2974
2975
2976 static void
2977 radv_sparse_buffer_bind_memory(struct radv_device *device,
2978 const VkSparseBufferMemoryBindInfo *bind)
2979 {
2980 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2981
2982 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2983 struct radv_device_memory *mem = NULL;
2984
2985 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2986 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2987
2988 device->ws->buffer_virtual_bind(buffer->bo,
2989 bind->pBinds[i].resourceOffset,
2990 bind->pBinds[i].size,
2991 mem ? mem->bo : NULL,
2992 bind->pBinds[i].memoryOffset);
2993 }
2994 }
2995
2996 static void
2997 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2998 const VkSparseImageOpaqueMemoryBindInfo *bind)
2999 {
3000 RADV_FROM_HANDLE(radv_image, image, bind->image);
3001
3002 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3003 struct radv_device_memory *mem = NULL;
3004
3005 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3006 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3007
3008 device->ws->buffer_virtual_bind(image->bo,
3009 bind->pBinds[i].resourceOffset,
3010 bind->pBinds[i].size,
3011 mem ? mem->bo : NULL,
3012 bind->pBinds[i].memoryOffset);
3013 }
3014 }
3015
3016 VkResult radv_QueueBindSparse(
3017 VkQueue _queue,
3018 uint32_t bindInfoCount,
3019 const VkBindSparseInfo* pBindInfo,
3020 VkFence _fence)
3021 {
3022 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3023 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3024 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3025 bool fence_emitted = false;
3026
3027 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3028 struct radv_winsys_sem_info sem_info;
3029 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3030 radv_sparse_buffer_bind_memory(queue->device,
3031 pBindInfo[i].pBufferBinds + j);
3032 }
3033
3034 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3035 radv_sparse_image_opaque_bind_memory(queue->device,
3036 pBindInfo[i].pImageOpaqueBinds + j);
3037 }
3038
3039 VkResult result;
3040 result = radv_alloc_sem_info(&sem_info,
3041 pBindInfo[i].waitSemaphoreCount,
3042 pBindInfo[i].pWaitSemaphores,
3043 pBindInfo[i].signalSemaphoreCount,
3044 pBindInfo[i].pSignalSemaphores,
3045 _fence);
3046 if (result != VK_SUCCESS)
3047 return result;
3048
3049 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3050 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3051 &queue->device->empty_cs[queue->queue_family_index],
3052 1, NULL, NULL,
3053 &sem_info, NULL,
3054 false, base_fence);
3055 fence_emitted = true;
3056 if (fence)
3057 fence->submitted = true;
3058 }
3059
3060 radv_free_sem_info(&sem_info);
3061
3062 }
3063
3064 if (fence) {
3065 if (!fence_emitted) {
3066 radv_signal_fence(queue, fence);
3067 }
3068 fence->submitted = true;
3069 }
3070
3071 return VK_SUCCESS;
3072 }
3073
3074 VkResult radv_CreateFence(
3075 VkDevice _device,
3076 const VkFenceCreateInfo* pCreateInfo,
3077 const VkAllocationCallbacks* pAllocator,
3078 VkFence* pFence)
3079 {
3080 RADV_FROM_HANDLE(radv_device, device, _device);
3081 const VkExportFenceCreateInfoKHR *export =
3082 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3083 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3084 export ? export->handleTypes : 0;
3085
3086 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3087 sizeof(*fence), 8,
3088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3089
3090 if (!fence)
3091 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3092
3093 fence->submitted = false;
3094 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3095 fence->temp_syncobj = 0;
3096 if (device->always_use_syncobj || handleTypes) {
3097 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3098 if (ret) {
3099 vk_free2(&device->alloc, pAllocator, fence);
3100 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3101 }
3102 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3103 device->ws->signal_syncobj(device->ws, fence->syncobj);
3104 }
3105 fence->fence = NULL;
3106 } else {
3107 fence->fence = device->ws->create_fence();
3108 if (!fence->fence) {
3109 vk_free2(&device->alloc, pAllocator, fence);
3110 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3111 }
3112 fence->syncobj = 0;
3113 }
3114
3115 *pFence = radv_fence_to_handle(fence);
3116
3117 return VK_SUCCESS;
3118 }
3119
3120 void radv_DestroyFence(
3121 VkDevice _device,
3122 VkFence _fence,
3123 const VkAllocationCallbacks* pAllocator)
3124 {
3125 RADV_FROM_HANDLE(radv_device, device, _device);
3126 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3127
3128 if (!fence)
3129 return;
3130
3131 if (fence->temp_syncobj)
3132 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3133 if (fence->syncobj)
3134 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3135 if (fence->fence)
3136 device->ws->destroy_fence(fence->fence);
3137 vk_free2(&device->alloc, pAllocator, fence);
3138 }
3139
3140
3141 static uint64_t radv_get_current_time()
3142 {
3143 struct timespec tv;
3144 clock_gettime(CLOCK_MONOTONIC, &tv);
3145 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3146 }
3147
3148 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3149 {
3150 uint64_t current_time = radv_get_current_time();
3151
3152 timeout = MIN2(UINT64_MAX - current_time, timeout);
3153
3154 return current_time + timeout;
3155 }
3156
3157
3158 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3159 {
3160 for (uint32_t i = 0; i < fenceCount; ++i) {
3161 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3162 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3163 return false;
3164 }
3165 return true;
3166 }
3167
3168 VkResult radv_WaitForFences(
3169 VkDevice _device,
3170 uint32_t fenceCount,
3171 const VkFence* pFences,
3172 VkBool32 waitAll,
3173 uint64_t timeout)
3174 {
3175 RADV_FROM_HANDLE(radv_device, device, _device);
3176 timeout = radv_get_absolute_timeout(timeout);
3177
3178 if (device->always_use_syncobj) {
3179 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3180 if (!handles)
3181 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3182
3183 for (uint32_t i = 0; i < fenceCount; ++i) {
3184 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3185 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3186 }
3187
3188 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3189
3190 free(handles);
3191 return success ? VK_SUCCESS : VK_TIMEOUT;
3192 }
3193
3194 if (!waitAll && fenceCount > 1) {
3195 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3196 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3197 uint32_t wait_count = 0;
3198 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3199 if (!fences)
3200 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3201
3202 for (uint32_t i = 0; i < fenceCount; ++i) {
3203 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3204
3205 if (fence->signalled) {
3206 free(fences);
3207 return VK_SUCCESS;
3208 }
3209
3210 fences[wait_count++] = fence->fence;
3211 }
3212
3213 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3214 waitAll, timeout - radv_get_current_time());
3215
3216 free(fences);
3217 return success ? VK_SUCCESS : VK_TIMEOUT;
3218 }
3219
3220 while(radv_get_current_time() <= timeout) {
3221 for (uint32_t i = 0; i < fenceCount; ++i) {
3222 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3223 return VK_SUCCESS;
3224 }
3225 }
3226 return VK_TIMEOUT;
3227 }
3228
3229 for (uint32_t i = 0; i < fenceCount; ++i) {
3230 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3231 bool expired = false;
3232
3233 if (fence->temp_syncobj) {
3234 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3235 return VK_TIMEOUT;
3236 continue;
3237 }
3238
3239 if (fence->syncobj) {
3240 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3241 return VK_TIMEOUT;
3242 continue;
3243 }
3244
3245 if (fence->signalled)
3246 continue;
3247
3248 if (!fence->submitted) {
3249 while(radv_get_current_time() <= timeout && !fence->submitted)
3250 /* Do nothing */;
3251
3252 if (!fence->submitted)
3253 return VK_TIMEOUT;
3254
3255 /* Recheck as it may have been set by submitting operations. */
3256 if (fence->signalled)
3257 continue;
3258 }
3259
3260 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3261 if (!expired)
3262 return VK_TIMEOUT;
3263
3264 fence->signalled = true;
3265 }
3266
3267 return VK_SUCCESS;
3268 }
3269
3270 VkResult radv_ResetFences(VkDevice _device,
3271 uint32_t fenceCount,
3272 const VkFence *pFences)
3273 {
3274 RADV_FROM_HANDLE(radv_device, device, _device);
3275
3276 for (unsigned i = 0; i < fenceCount; ++i) {
3277 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3278 fence->submitted = fence->signalled = false;
3279
3280 /* Per spec, we first restore the permanent payload, and then reset, so
3281 * having a temp syncobj should not skip resetting the permanent syncobj. */
3282 if (fence->temp_syncobj) {
3283 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3284 fence->temp_syncobj = 0;
3285 }
3286
3287 if (fence->syncobj) {
3288 device->ws->reset_syncobj(device->ws, fence->syncobj);
3289 }
3290 }
3291
3292 return VK_SUCCESS;
3293 }
3294
3295 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3296 {
3297 RADV_FROM_HANDLE(radv_device, device, _device);
3298 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3299
3300 if (fence->temp_syncobj) {
3301 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3302 return success ? VK_SUCCESS : VK_NOT_READY;
3303 }
3304
3305 if (fence->syncobj) {
3306 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3307 return success ? VK_SUCCESS : VK_NOT_READY;
3308 }
3309
3310 if (fence->signalled)
3311 return VK_SUCCESS;
3312 if (!fence->submitted)
3313 return VK_NOT_READY;
3314 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3315 return VK_NOT_READY;
3316
3317 return VK_SUCCESS;
3318 }
3319
3320
3321 // Queue semaphore functions
3322
3323 VkResult radv_CreateSemaphore(
3324 VkDevice _device,
3325 const VkSemaphoreCreateInfo* pCreateInfo,
3326 const VkAllocationCallbacks* pAllocator,
3327 VkSemaphore* pSemaphore)
3328 {
3329 RADV_FROM_HANDLE(radv_device, device, _device);
3330 const VkExportSemaphoreCreateInfoKHR *export =
3331 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3332 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3333 export ? export->handleTypes : 0;
3334
3335 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3336 sizeof(*sem), 8,
3337 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3338 if (!sem)
3339 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3340
3341 sem->temp_syncobj = 0;
3342 /* create a syncobject if we are going to export this semaphore */
3343 if (device->always_use_syncobj || handleTypes) {
3344 assert (device->physical_device->rad_info.has_syncobj);
3345 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3346 if (ret) {
3347 vk_free2(&device->alloc, pAllocator, sem);
3348 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3349 }
3350 sem->sem = NULL;
3351 } else {
3352 sem->sem = device->ws->create_sem(device->ws);
3353 if (!sem->sem) {
3354 vk_free2(&device->alloc, pAllocator, sem);
3355 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3356 }
3357 sem->syncobj = 0;
3358 }
3359
3360 *pSemaphore = radv_semaphore_to_handle(sem);
3361 return VK_SUCCESS;
3362 }
3363
3364 void radv_DestroySemaphore(
3365 VkDevice _device,
3366 VkSemaphore _semaphore,
3367 const VkAllocationCallbacks* pAllocator)
3368 {
3369 RADV_FROM_HANDLE(radv_device, device, _device);
3370 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3371 if (!_semaphore)
3372 return;
3373
3374 if (sem->syncobj)
3375 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3376 else
3377 device->ws->destroy_sem(sem->sem);
3378 vk_free2(&device->alloc, pAllocator, sem);
3379 }
3380
3381 VkResult radv_CreateEvent(
3382 VkDevice _device,
3383 const VkEventCreateInfo* pCreateInfo,
3384 const VkAllocationCallbacks* pAllocator,
3385 VkEvent* pEvent)
3386 {
3387 RADV_FROM_HANDLE(radv_device, device, _device);
3388 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3389 sizeof(*event), 8,
3390 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3391
3392 if (!event)
3393 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3394
3395 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3396 RADEON_DOMAIN_GTT,
3397 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3398 if (!event->bo) {
3399 vk_free2(&device->alloc, pAllocator, event);
3400 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3401 }
3402
3403 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3404
3405 *pEvent = radv_event_to_handle(event);
3406
3407 return VK_SUCCESS;
3408 }
3409
3410 void radv_DestroyEvent(
3411 VkDevice _device,
3412 VkEvent _event,
3413 const VkAllocationCallbacks* pAllocator)
3414 {
3415 RADV_FROM_HANDLE(radv_device, device, _device);
3416 RADV_FROM_HANDLE(radv_event, event, _event);
3417
3418 if (!event)
3419 return;
3420 device->ws->buffer_destroy(event->bo);
3421 vk_free2(&device->alloc, pAllocator, event);
3422 }
3423
3424 VkResult radv_GetEventStatus(
3425 VkDevice _device,
3426 VkEvent _event)
3427 {
3428 RADV_FROM_HANDLE(radv_event, event, _event);
3429
3430 if (*event->map == 1)
3431 return VK_EVENT_SET;
3432 return VK_EVENT_RESET;
3433 }
3434
3435 VkResult radv_SetEvent(
3436 VkDevice _device,
3437 VkEvent _event)
3438 {
3439 RADV_FROM_HANDLE(radv_event, event, _event);
3440 *event->map = 1;
3441
3442 return VK_SUCCESS;
3443 }
3444
3445 VkResult radv_ResetEvent(
3446 VkDevice _device,
3447 VkEvent _event)
3448 {
3449 RADV_FROM_HANDLE(radv_event, event, _event);
3450 *event->map = 0;
3451
3452 return VK_SUCCESS;
3453 }
3454
3455 VkResult radv_CreateBuffer(
3456 VkDevice _device,
3457 const VkBufferCreateInfo* pCreateInfo,
3458 const VkAllocationCallbacks* pAllocator,
3459 VkBuffer* pBuffer)
3460 {
3461 RADV_FROM_HANDLE(radv_device, device, _device);
3462 struct radv_buffer *buffer;
3463
3464 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3465
3466 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3467 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3468 if (buffer == NULL)
3469 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3470
3471 buffer->size = pCreateInfo->size;
3472 buffer->usage = pCreateInfo->usage;
3473 buffer->bo = NULL;
3474 buffer->offset = 0;
3475 buffer->flags = pCreateInfo->flags;
3476
3477 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3478 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3479
3480 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3481 buffer->bo = device->ws->buffer_create(device->ws,
3482 align64(buffer->size, 4096),
3483 4096, 0, RADEON_FLAG_VIRTUAL);
3484 if (!buffer->bo) {
3485 vk_free2(&device->alloc, pAllocator, buffer);
3486 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3487 }
3488 }
3489
3490 *pBuffer = radv_buffer_to_handle(buffer);
3491
3492 return VK_SUCCESS;
3493 }
3494
3495 void radv_DestroyBuffer(
3496 VkDevice _device,
3497 VkBuffer _buffer,
3498 const VkAllocationCallbacks* pAllocator)
3499 {
3500 RADV_FROM_HANDLE(radv_device, device, _device);
3501 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3502
3503 if (!buffer)
3504 return;
3505
3506 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3507 device->ws->buffer_destroy(buffer->bo);
3508
3509 vk_free2(&device->alloc, pAllocator, buffer);
3510 }
3511
3512 static inline unsigned
3513 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3514 {
3515 if (stencil)
3516 return image->surface.u.legacy.stencil_tiling_index[level];
3517 else
3518 return image->surface.u.legacy.tiling_index[level];
3519 }
3520
3521 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3522 {
3523 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3524 }
3525
3526 static uint32_t
3527 radv_init_dcc_control_reg(struct radv_device *device,
3528 struct radv_image_view *iview)
3529 {
3530 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3531 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3532 unsigned max_compressed_block_size;
3533 unsigned independent_64b_blocks;
3534
3535 if (device->physical_device->rad_info.chip_class < VI)
3536 return 0;
3537
3538 if (iview->image->info.samples > 1) {
3539 if (iview->image->surface.bpe == 1)
3540 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3541 else if (iview->image->surface.bpe == 2)
3542 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3543 }
3544
3545 if (!device->physical_device->rad_info.has_dedicated_vram) {
3546 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3547 * dGPU and 64 for APU because all of our APUs to date use
3548 * DIMMs which have a request granularity size of 64B while all
3549 * other chips have a 32B request size.
3550 */
3551 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3552 }
3553
3554 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3555 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3556 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3557 /* If this DCC image is potentially going to be used in texture
3558 * fetches, we need some special settings.
3559 */
3560 independent_64b_blocks = 1;
3561 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3562 } else {
3563 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3564 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3565 * big as possible for better compression state.
3566 */
3567 independent_64b_blocks = 0;
3568 max_compressed_block_size = max_uncompressed_block_size;
3569 }
3570
3571 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3572 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3573 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3574 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3575 }
3576
3577 static void
3578 radv_initialise_color_surface(struct radv_device *device,
3579 struct radv_color_buffer_info *cb,
3580 struct radv_image_view *iview)
3581 {
3582 const struct vk_format_description *desc;
3583 unsigned ntype, format, swap, endian;
3584 unsigned blend_clamp = 0, blend_bypass = 0;
3585 uint64_t va;
3586 const struct radeon_surf *surf = &iview->image->surface;
3587
3588 desc = vk_format_description(iview->vk_format);
3589
3590 memset(cb, 0, sizeof(*cb));
3591
3592 /* Intensity is implemented as Red, so treat it that way. */
3593 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3594
3595 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3596
3597 cb->cb_color_base = va >> 8;
3598
3599 if (device->physical_device->rad_info.chip_class >= GFX9) {
3600 struct gfx9_surf_meta_flags meta;
3601 if (iview->image->dcc_offset)
3602 meta = iview->image->surface.u.gfx9.dcc;
3603 else
3604 meta = iview->image->surface.u.gfx9.cmask;
3605
3606 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3607 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3608 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3609 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3610
3611 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3612 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3613 } else {
3614 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3615 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3616
3617 cb->cb_color_base += level_info->offset >> 8;
3618 if (level_info->mode == RADEON_SURF_MODE_2D)
3619 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3620
3621 pitch_tile_max = level_info->nblk_x / 8 - 1;
3622 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3623 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3624
3625 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3626 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3627 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3628
3629 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3630
3631 if (radv_image_has_fmask(iview->image)) {
3632 if (device->physical_device->rad_info.chip_class >= CIK)
3633 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3634 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3635 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3636 } else {
3637 /* This must be set for fast clear to work without FMASK. */
3638 if (device->physical_device->rad_info.chip_class >= CIK)
3639 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3640 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3641 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3642 }
3643 }
3644
3645 /* CMASK variables */
3646 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3647 va += iview->image->cmask.offset;
3648 cb->cb_color_cmask = va >> 8;
3649
3650 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3651 va += iview->image->dcc_offset;
3652 cb->cb_dcc_base = va >> 8;
3653 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3654
3655 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3656 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3657 S_028C6C_SLICE_MAX(max_slice);
3658
3659 if (iview->image->info.samples > 1) {
3660 unsigned log_samples = util_logbase2(iview->image->info.samples);
3661
3662 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3663 S_028C74_NUM_FRAGMENTS(log_samples);
3664 }
3665
3666 if (radv_image_has_fmask(iview->image)) {
3667 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3668 cb->cb_color_fmask = va >> 8;
3669 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3670 } else {
3671 cb->cb_color_fmask = cb->cb_color_base;
3672 }
3673
3674 ntype = radv_translate_color_numformat(iview->vk_format,
3675 desc,
3676 vk_format_get_first_non_void_channel(iview->vk_format));
3677 format = radv_translate_colorformat(iview->vk_format);
3678 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3679 radv_finishme("Illegal color\n");
3680 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3681 endian = radv_colorformat_endian_swap(format);
3682
3683 /* blend clamp should be set for all NORM/SRGB types */
3684 if (ntype == V_028C70_NUMBER_UNORM ||
3685 ntype == V_028C70_NUMBER_SNORM ||
3686 ntype == V_028C70_NUMBER_SRGB)
3687 blend_clamp = 1;
3688
3689 /* set blend bypass according to docs if SINT/UINT or
3690 8/24 COLOR variants */
3691 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3692 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3693 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3694 blend_clamp = 0;
3695 blend_bypass = 1;
3696 }
3697 #if 0
3698 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3699 (format == V_028C70_COLOR_8 ||
3700 format == V_028C70_COLOR_8_8 ||
3701 format == V_028C70_COLOR_8_8_8_8))
3702 ->color_is_int8 = true;
3703 #endif
3704 cb->cb_color_info = S_028C70_FORMAT(format) |
3705 S_028C70_COMP_SWAP(swap) |
3706 S_028C70_BLEND_CLAMP(blend_clamp) |
3707 S_028C70_BLEND_BYPASS(blend_bypass) |
3708 S_028C70_SIMPLE_FLOAT(1) |
3709 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3710 ntype != V_028C70_NUMBER_SNORM &&
3711 ntype != V_028C70_NUMBER_SRGB &&
3712 format != V_028C70_COLOR_8_24 &&
3713 format != V_028C70_COLOR_24_8) |
3714 S_028C70_NUMBER_TYPE(ntype) |
3715 S_028C70_ENDIAN(endian);
3716 if (radv_image_has_fmask(iview->image)) {
3717 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3718 if (device->physical_device->rad_info.chip_class == SI) {
3719 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3720 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3721 }
3722 }
3723
3724 if (radv_image_has_cmask(iview->image) &&
3725 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3726 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3727
3728 if (radv_dcc_enabled(iview->image, iview->base_mip))
3729 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3730
3731 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3732
3733 /* This must be set for fast clear to work without FMASK. */
3734 if (!radv_image_has_fmask(iview->image) &&
3735 device->physical_device->rad_info.chip_class == SI) {
3736 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3737 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3738 }
3739
3740 if (device->physical_device->rad_info.chip_class >= GFX9) {
3741 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3742 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3743
3744 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3745 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3746 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3747 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3748 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3749 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3750 }
3751 }
3752
3753 static unsigned
3754 radv_calc_decompress_on_z_planes(struct radv_device *device,
3755 struct radv_image_view *iview)
3756 {
3757 unsigned max_zplanes = 0;
3758
3759 assert(radv_image_is_tc_compat_htile(iview->image));
3760
3761 if (device->physical_device->rad_info.chip_class >= GFX9) {
3762 /* Default value for 32-bit depth surfaces. */
3763 max_zplanes = 4;
3764
3765 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3766 iview->image->info.samples > 1)
3767 max_zplanes = 2;
3768
3769 max_zplanes = max_zplanes + 1;
3770 } else {
3771 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3772 /* Do not enable Z plane compression for 16-bit depth
3773 * surfaces because isn't supported on GFX8. Only
3774 * 32-bit depth surfaces are supported by the hardware.
3775 * This allows to maintain shader compatibility and to
3776 * reduce the number of depth decompressions.
3777 */
3778 max_zplanes = 1;
3779 } else {
3780 if (iview->image->info.samples <= 1)
3781 max_zplanes = 5;
3782 else if (iview->image->info.samples <= 4)
3783 max_zplanes = 3;
3784 else
3785 max_zplanes = 2;
3786 }
3787 }
3788
3789 return max_zplanes;
3790 }
3791
3792 static void
3793 radv_initialise_ds_surface(struct radv_device *device,
3794 struct radv_ds_buffer_info *ds,
3795 struct radv_image_view *iview)
3796 {
3797 unsigned level = iview->base_mip;
3798 unsigned format, stencil_format;
3799 uint64_t va, s_offs, z_offs;
3800 bool stencil_only = false;
3801 memset(ds, 0, sizeof(*ds));
3802 switch (iview->image->vk_format) {
3803 case VK_FORMAT_D24_UNORM_S8_UINT:
3804 case VK_FORMAT_X8_D24_UNORM_PACK32:
3805 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3806 ds->offset_scale = 2.0f;
3807 break;
3808 case VK_FORMAT_D16_UNORM:
3809 case VK_FORMAT_D16_UNORM_S8_UINT:
3810 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3811 ds->offset_scale = 4.0f;
3812 break;
3813 case VK_FORMAT_D32_SFLOAT:
3814 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3815 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3816 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3817 ds->offset_scale = 1.0f;
3818 break;
3819 case VK_FORMAT_S8_UINT:
3820 stencil_only = true;
3821 break;
3822 default:
3823 break;
3824 }
3825
3826 format = radv_translate_dbformat(iview->image->vk_format);
3827 stencil_format = iview->image->surface.has_stencil ?
3828 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3829
3830 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3831 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3832 S_028008_SLICE_MAX(max_slice);
3833
3834 ds->db_htile_data_base = 0;
3835 ds->db_htile_surface = 0;
3836
3837 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3838 s_offs = z_offs = va;
3839
3840 if (device->physical_device->rad_info.chip_class >= GFX9) {
3841 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3842 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3843
3844 ds->db_z_info = S_028038_FORMAT(format) |
3845 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3846 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3847 S_028038_MAXMIP(iview->image->info.levels - 1);
3848 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3849 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3850
3851 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3852 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3853 ds->db_depth_view |= S_028008_MIPID(level);
3854
3855 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3856 S_02801C_Y_MAX(iview->image->info.height - 1);
3857
3858 if (radv_htile_enabled(iview->image, level)) {
3859 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3860
3861 if (radv_image_is_tc_compat_htile(iview->image)) {
3862 unsigned max_zplanes =
3863 radv_calc_decompress_on_z_planes(device, iview);
3864
3865 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3866 S_028038_ITERATE_FLUSH(1);
3867 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3868 }
3869
3870 if (!iview->image->surface.has_stencil)
3871 /* Use all of the htile_buffer for depth if there's no stencil. */
3872 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3873 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3874 iview->image->htile_offset;
3875 ds->db_htile_data_base = va >> 8;
3876 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3877 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3878 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3879 }
3880 } else {
3881 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3882
3883 if (stencil_only)
3884 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3885
3886 z_offs += iview->image->surface.u.legacy.level[level].offset;
3887 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3888
3889 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3890 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3891 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3892
3893 if (iview->image->info.samples > 1)
3894 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3895
3896 if (device->physical_device->rad_info.chip_class >= CIK) {
3897 struct radeon_info *info = &device->physical_device->rad_info;
3898 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3899 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3900 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3901 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3902 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3903 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3904
3905 if (stencil_only)
3906 tile_mode = stencil_tile_mode;
3907
3908 ds->db_depth_info |=
3909 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3910 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3911 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3912 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3913 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3914 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3915 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3916 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3917 } else {
3918 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3919 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3920 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3921 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3922 if (stencil_only)
3923 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3924 }
3925
3926 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3927 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3928 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3929
3930 if (radv_htile_enabled(iview->image, level)) {
3931 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3932
3933 if (!iview->image->surface.has_stencil &&
3934 !radv_image_is_tc_compat_htile(iview->image))
3935 /* Use all of the htile_buffer for depth if there's no stencil. */
3936 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3937
3938 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3939 iview->image->htile_offset;
3940 ds->db_htile_data_base = va >> 8;
3941 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3942
3943 if (radv_image_is_tc_compat_htile(iview->image)) {
3944 unsigned max_zplanes =
3945 radv_calc_decompress_on_z_planes(device, iview);
3946
3947 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3948 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
3949 }
3950 }
3951 }
3952
3953 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3954 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3955 }
3956
3957 VkResult radv_CreateFramebuffer(
3958 VkDevice _device,
3959 const VkFramebufferCreateInfo* pCreateInfo,
3960 const VkAllocationCallbacks* pAllocator,
3961 VkFramebuffer* pFramebuffer)
3962 {
3963 RADV_FROM_HANDLE(radv_device, device, _device);
3964 struct radv_framebuffer *framebuffer;
3965
3966 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3967
3968 size_t size = sizeof(*framebuffer) +
3969 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3970 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3971 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3972 if (framebuffer == NULL)
3973 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3974
3975 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3976 framebuffer->width = pCreateInfo->width;
3977 framebuffer->height = pCreateInfo->height;
3978 framebuffer->layers = pCreateInfo->layers;
3979 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3980 VkImageView _iview = pCreateInfo->pAttachments[i];
3981 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3982 framebuffer->attachments[i].attachment = iview;
3983 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3984 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3985 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3986 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3987 }
3988 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3989 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3990 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3991 }
3992
3993 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3994 return VK_SUCCESS;
3995 }
3996
3997 void radv_DestroyFramebuffer(
3998 VkDevice _device,
3999 VkFramebuffer _fb,
4000 const VkAllocationCallbacks* pAllocator)
4001 {
4002 RADV_FROM_HANDLE(radv_device, device, _device);
4003 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4004
4005 if (!fb)
4006 return;
4007 vk_free2(&device->alloc, pAllocator, fb);
4008 }
4009
4010 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4011 {
4012 switch (address_mode) {
4013 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4014 return V_008F30_SQ_TEX_WRAP;
4015 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4016 return V_008F30_SQ_TEX_MIRROR;
4017 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4018 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4019 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4020 return V_008F30_SQ_TEX_CLAMP_BORDER;
4021 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4022 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4023 default:
4024 unreachable("illegal tex wrap mode");
4025 break;
4026 }
4027 }
4028
4029 static unsigned
4030 radv_tex_compare(VkCompareOp op)
4031 {
4032 switch (op) {
4033 case VK_COMPARE_OP_NEVER:
4034 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4035 case VK_COMPARE_OP_LESS:
4036 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4037 case VK_COMPARE_OP_EQUAL:
4038 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4039 case VK_COMPARE_OP_LESS_OR_EQUAL:
4040 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4041 case VK_COMPARE_OP_GREATER:
4042 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4043 case VK_COMPARE_OP_NOT_EQUAL:
4044 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4045 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4046 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4047 case VK_COMPARE_OP_ALWAYS:
4048 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4049 default:
4050 unreachable("illegal compare mode");
4051 break;
4052 }
4053 }
4054
4055 static unsigned
4056 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4057 {
4058 switch (filter) {
4059 case VK_FILTER_NEAREST:
4060 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4061 V_008F38_SQ_TEX_XY_FILTER_POINT);
4062 case VK_FILTER_LINEAR:
4063 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4064 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4065 case VK_FILTER_CUBIC_IMG:
4066 default:
4067 fprintf(stderr, "illegal texture filter");
4068 return 0;
4069 }
4070 }
4071
4072 static unsigned
4073 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4074 {
4075 switch (mode) {
4076 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4077 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4078 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4079 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4080 default:
4081 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4082 }
4083 }
4084
4085 static unsigned
4086 radv_tex_bordercolor(VkBorderColor bcolor)
4087 {
4088 switch (bcolor) {
4089 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4090 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4091 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4092 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4093 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4094 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4095 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4096 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4097 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4098 default:
4099 break;
4100 }
4101 return 0;
4102 }
4103
4104 static unsigned
4105 radv_tex_aniso_filter(unsigned filter)
4106 {
4107 if (filter < 2)
4108 return 0;
4109 if (filter < 4)
4110 return 1;
4111 if (filter < 8)
4112 return 2;
4113 if (filter < 16)
4114 return 3;
4115 return 4;
4116 }
4117
4118 static unsigned
4119 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4120 {
4121 switch (mode) {
4122 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4123 return SQ_IMG_FILTER_MODE_BLEND;
4124 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4125 return SQ_IMG_FILTER_MODE_MIN;
4126 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4127 return SQ_IMG_FILTER_MODE_MAX;
4128 default:
4129 break;
4130 }
4131 return 0;
4132 }
4133
4134 static void
4135 radv_init_sampler(struct radv_device *device,
4136 struct radv_sampler *sampler,
4137 const VkSamplerCreateInfo *pCreateInfo)
4138 {
4139 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4140 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4141 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4142 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4143 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4144
4145 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4146 vk_find_struct_const(pCreateInfo->pNext,
4147 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4148 if (sampler_reduction)
4149 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4150
4151 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4152 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4153 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4154 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4155 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4156 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4157 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4158 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4159 S_008F30_DISABLE_CUBE_WRAP(0) |
4160 S_008F30_COMPAT_MODE(is_vi) |
4161 S_008F30_FILTER_MODE(filter_mode));
4162 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4163 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4164 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4165 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4166 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4167 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4168 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4169 S_008F38_MIP_POINT_PRECLAMP(0) |
4170 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4171 S_008F38_FILTER_PREC_FIX(1) |
4172 S_008F38_ANISO_OVERRIDE(is_vi));
4173 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4174 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4175 }
4176
4177 VkResult radv_CreateSampler(
4178 VkDevice _device,
4179 const VkSamplerCreateInfo* pCreateInfo,
4180 const VkAllocationCallbacks* pAllocator,
4181 VkSampler* pSampler)
4182 {
4183 RADV_FROM_HANDLE(radv_device, device, _device);
4184 struct radv_sampler *sampler;
4185
4186 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4187
4188 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4189 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4190 if (!sampler)
4191 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4192
4193 radv_init_sampler(device, sampler, pCreateInfo);
4194 *pSampler = radv_sampler_to_handle(sampler);
4195
4196 return VK_SUCCESS;
4197 }
4198
4199 void radv_DestroySampler(
4200 VkDevice _device,
4201 VkSampler _sampler,
4202 const VkAllocationCallbacks* pAllocator)
4203 {
4204 RADV_FROM_HANDLE(radv_device, device, _device);
4205 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4206
4207 if (!sampler)
4208 return;
4209 vk_free2(&device->alloc, pAllocator, sampler);
4210 }
4211
4212 /* vk_icd.h does not declare this function, so we declare it here to
4213 * suppress Wmissing-prototypes.
4214 */
4215 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4216 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4217
4218 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4219 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4220 {
4221 /* For the full details on loader interface versioning, see
4222 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4223 * What follows is a condensed summary, to help you navigate the large and
4224 * confusing official doc.
4225 *
4226 * - Loader interface v0 is incompatible with later versions. We don't
4227 * support it.
4228 *
4229 * - In loader interface v1:
4230 * - The first ICD entrypoint called by the loader is
4231 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4232 * entrypoint.
4233 * - The ICD must statically expose no other Vulkan symbol unless it is
4234 * linked with -Bsymbolic.
4235 * - Each dispatchable Vulkan handle created by the ICD must be
4236 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4237 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4238 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4239 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4240 * such loader-managed surfaces.
4241 *
4242 * - Loader interface v2 differs from v1 in:
4243 * - The first ICD entrypoint called by the loader is
4244 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4245 * statically expose this entrypoint.
4246 *
4247 * - Loader interface v3 differs from v2 in:
4248 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4249 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4250 * because the loader no longer does so.
4251 */
4252 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4253 return VK_SUCCESS;
4254 }
4255
4256 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4257 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4258 int *pFD)
4259 {
4260 RADV_FROM_HANDLE(radv_device, device, _device);
4261 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4262
4263 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4264
4265 /* At the moment, we support only the below handle types. */
4266 assert(pGetFdInfo->handleType ==
4267 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4268 pGetFdInfo->handleType ==
4269 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4270
4271 bool ret = radv_get_memory_fd(device, memory, pFD);
4272 if (ret == false)
4273 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4274 return VK_SUCCESS;
4275 }
4276
4277 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4278 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4279 int fd,
4280 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4281 {
4282 switch (handleType) {
4283 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4284 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4285 return VK_SUCCESS;
4286
4287 default:
4288 /* The valid usage section for this function says:
4289 *
4290 * "handleType must not be one of the handle types defined as
4291 * opaque."
4292 *
4293 * So opaque handle types fall into the default "unsupported" case.
4294 */
4295 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4296 }
4297 }
4298
4299 static VkResult radv_import_opaque_fd(struct radv_device *device,
4300 int fd,
4301 uint32_t *syncobj)
4302 {
4303 uint32_t syncobj_handle = 0;
4304 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4305 if (ret != 0)
4306 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4307
4308 if (*syncobj)
4309 device->ws->destroy_syncobj(device->ws, *syncobj);
4310
4311 *syncobj = syncobj_handle;
4312 close(fd);
4313
4314 return VK_SUCCESS;
4315 }
4316
4317 static VkResult radv_import_sync_fd(struct radv_device *device,
4318 int fd,
4319 uint32_t *syncobj)
4320 {
4321 /* If we create a syncobj we do it locally so that if we have an error, we don't
4322 * leave a syncobj in an undetermined state in the fence. */
4323 uint32_t syncobj_handle = *syncobj;
4324 if (!syncobj_handle) {
4325 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4326 if (ret) {
4327 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4328 }
4329 }
4330
4331 if (fd == -1) {
4332 device->ws->signal_syncobj(device->ws, syncobj_handle);
4333 } else {
4334 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4335 if (ret != 0)
4336 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4337 }
4338
4339 *syncobj = syncobj_handle;
4340 if (fd != -1)
4341 close(fd);
4342
4343 return VK_SUCCESS;
4344 }
4345
4346 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4347 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4348 {
4349 RADV_FROM_HANDLE(radv_device, device, _device);
4350 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4351 uint32_t *syncobj_dst = NULL;
4352
4353 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4354 syncobj_dst = &sem->temp_syncobj;
4355 } else {
4356 syncobj_dst = &sem->syncobj;
4357 }
4358
4359 switch(pImportSemaphoreFdInfo->handleType) {
4360 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4361 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4362 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4363 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4364 default:
4365 unreachable("Unhandled semaphore handle type");
4366 }
4367 }
4368
4369 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4370 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4371 int *pFd)
4372 {
4373 RADV_FROM_HANDLE(radv_device, device, _device);
4374 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4375 int ret;
4376 uint32_t syncobj_handle;
4377
4378 if (sem->temp_syncobj)
4379 syncobj_handle = sem->temp_syncobj;
4380 else
4381 syncobj_handle = sem->syncobj;
4382
4383 switch(pGetFdInfo->handleType) {
4384 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4385 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4386 break;
4387 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4388 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4389 if (!ret) {
4390 if (sem->temp_syncobj) {
4391 close (sem->temp_syncobj);
4392 sem->temp_syncobj = 0;
4393 } else {
4394 device->ws->reset_syncobj(device->ws, syncobj_handle);
4395 }
4396 }
4397 break;
4398 default:
4399 unreachable("Unhandled semaphore handle type");
4400 }
4401
4402 if (ret)
4403 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4404 return VK_SUCCESS;
4405 }
4406
4407 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4408 VkPhysicalDevice physicalDevice,
4409 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4410 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4411 {
4412 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4413
4414 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4415 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4416 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4417 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4418 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4419 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4420 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4421 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4422 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4423 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4424 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4425 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4426 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4427 } else {
4428 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4429 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4430 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4431 }
4432 }
4433
4434 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4435 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4436 {
4437 RADV_FROM_HANDLE(radv_device, device, _device);
4438 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4439 uint32_t *syncobj_dst = NULL;
4440
4441
4442 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4443 syncobj_dst = &fence->temp_syncobj;
4444 } else {
4445 syncobj_dst = &fence->syncobj;
4446 }
4447
4448 switch(pImportFenceFdInfo->handleType) {
4449 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4450 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4451 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4452 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4453 default:
4454 unreachable("Unhandled fence handle type");
4455 }
4456 }
4457
4458 VkResult radv_GetFenceFdKHR(VkDevice _device,
4459 const VkFenceGetFdInfoKHR *pGetFdInfo,
4460 int *pFd)
4461 {
4462 RADV_FROM_HANDLE(radv_device, device, _device);
4463 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4464 int ret;
4465 uint32_t syncobj_handle;
4466
4467 if (fence->temp_syncobj)
4468 syncobj_handle = fence->temp_syncobj;
4469 else
4470 syncobj_handle = fence->syncobj;
4471
4472 switch(pGetFdInfo->handleType) {
4473 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4474 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4475 break;
4476 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4477 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4478 if (!ret) {
4479 if (fence->temp_syncobj) {
4480 close (fence->temp_syncobj);
4481 fence->temp_syncobj = 0;
4482 } else {
4483 device->ws->reset_syncobj(device->ws, syncobj_handle);
4484 }
4485 }
4486 break;
4487 default:
4488 unreachable("Unhandled fence handle type");
4489 }
4490
4491 if (ret)
4492 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4493 return VK_SUCCESS;
4494 }
4495
4496 void radv_GetPhysicalDeviceExternalFenceProperties(
4497 VkPhysicalDevice physicalDevice,
4498 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4499 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4500 {
4501 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4502
4503 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4504 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4505 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4506 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4507 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4508 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4509 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4510 } else {
4511 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4512 pExternalFenceProperties->compatibleHandleTypes = 0;
4513 pExternalFenceProperties->externalFenceFeatures = 0;
4514 }
4515 }
4516
4517 VkResult
4518 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4519 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4520 const VkAllocationCallbacks* pAllocator,
4521 VkDebugReportCallbackEXT* pCallback)
4522 {
4523 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4524 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4525 pCreateInfo, pAllocator, &instance->alloc,
4526 pCallback);
4527 }
4528
4529 void
4530 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4531 VkDebugReportCallbackEXT _callback,
4532 const VkAllocationCallbacks* pAllocator)
4533 {
4534 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4535 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4536 _callback, pAllocator, &instance->alloc);
4537 }
4538
4539 void
4540 radv_DebugReportMessageEXT(VkInstance _instance,
4541 VkDebugReportFlagsEXT flags,
4542 VkDebugReportObjectTypeEXT objectType,
4543 uint64_t object,
4544 size_t location,
4545 int32_t messageCode,
4546 const char* pLayerPrefix,
4547 const char* pMessage)
4548 {
4549 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4550 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4551 object, location, messageCode, pLayerPrefix, pMessage);
4552 }
4553
4554 void
4555 radv_GetDeviceGroupPeerMemoryFeatures(
4556 VkDevice device,
4557 uint32_t heapIndex,
4558 uint32_t localDeviceIndex,
4559 uint32_t remoteDeviceIndex,
4560 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4561 {
4562 assert(localDeviceIndex == remoteDeviceIndex);
4563
4564 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4565 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4566 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4567 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4568 }