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radv: Add non-uniform indexing lowering.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90
91 switch (family) {
92 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
93 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
94 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
95 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
96 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
97 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
98 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
99 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
100 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
101 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
114 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
115 default: chip_string = "AMD RADV unknown"; break;
116 }
117
118 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
119 }
120
121 static uint64_t
122 radv_get_visible_vram_size(struct radv_physical_device *device)
123 {
124 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
125 }
126
127 static uint64_t
128 radv_get_vram_size(struct radv_physical_device *device)
129 {
130 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
131 }
132
133 static void
134 radv_physical_device_init_mem_types(struct radv_physical_device *device)
135 {
136 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
137 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
138 uint64_t vram_size = radv_get_vram_size(device);
139 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
140 device->memory_properties.memoryHeapCount = 0;
141 if (vram_size > 0) {
142 vram_index = device->memory_properties.memoryHeapCount++;
143 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
144 .size = vram_size,
145 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
146 };
147 }
148 if (visible_vram_size) {
149 visible_vram_index = device->memory_properties.memoryHeapCount++;
150 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
151 .size = visible_vram_size,
152 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
153 };
154 }
155 if (device->rad_info.gart_size > 0) {
156 gart_index = device->memory_properties.memoryHeapCount++;
157 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
158 .size = device->rad_info.gart_size,
159 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
160 };
161 }
162
163 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
164 unsigned type_count = 0;
165 if (vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
169 .heapIndex = vram_index,
170 };
171 }
172 if (gart_index >= 0) {
173 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
174 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
175 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
176 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
177 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
178 .heapIndex = gart_index,
179 };
180 }
181 if (visible_vram_index >= 0) {
182 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
183 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
184 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
185 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
186 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
187 .heapIndex = visible_vram_index,
188 };
189 }
190 if (gart_index >= 0) {
191 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
192 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
193 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
194 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
195 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
196 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
197 .heapIndex = gart_index,
198 };
199 }
200 device->memory_properties.memoryTypeCount = type_count;
201 }
202
203 static void
204 radv_handle_env_var_force_family(struct radv_physical_device *device)
205 {
206 const char *family = getenv("RADV_FORCE_FAMILY");
207 unsigned i;
208
209 if (!family)
210 return;
211
212 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
213 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
214 /* Override family and chip_class. */
215 device->rad_info.family = i;
216
217 if (i >= CHIP_VEGA10)
218 device->rad_info.chip_class = GFX9;
219 else if (i >= CHIP_TONGA)
220 device->rad_info.chip_class = VI;
221 else if (i >= CHIP_BONAIRE)
222 device->rad_info.chip_class = CIK;
223 else
224 device->rad_info.chip_class = SI;
225
226 return;
227 }
228 }
229
230 fprintf(stderr, "radv: Unknown family: %s\n", family);
231 exit(1);
232 }
233
234 static VkResult
235 radv_physical_device_init(struct radv_physical_device *device,
236 struct radv_instance *instance,
237 drmDevicePtr drm_device)
238 {
239 const char *path = drm_device->nodes[DRM_NODE_RENDER];
240 VkResult result;
241 drmVersionPtr version;
242 int fd;
243 int master_fd = -1;
244
245 fd = open(path, O_RDWR | O_CLOEXEC);
246 if (fd < 0) {
247 if (instance->debug_flags & RADV_DEBUG_STARTUP)
248 radv_logi("Could not open device '%s'", path);
249
250 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
251 }
252
253 version = drmGetVersion(fd);
254 if (!version) {
255 close(fd);
256
257 if (instance->debug_flags & RADV_DEBUG_STARTUP)
258 radv_logi("Could not get the kernel driver version for device '%s'", path);
259
260 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
261 "failed to get version %s: %m", path);
262 }
263
264 if (strcmp(version->name, "amdgpu")) {
265 drmFreeVersion(version);
266 close(fd);
267
268 if (instance->debug_flags & RADV_DEBUG_STARTUP)
269 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
270
271 return VK_ERROR_INCOMPATIBLE_DRIVER;
272 }
273 drmFreeVersion(version);
274
275 if (instance->debug_flags & RADV_DEBUG_STARTUP)
276 radv_logi("Found compatible device '%s'.", path);
277
278 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
279 device->instance = instance;
280
281 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
282 instance->perftest_flags);
283 if (!device->ws) {
284 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
285 goto fail;
286 }
287
288 if (instance->enabled_extensions.KHR_display) {
289 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
290 if (master_fd >= 0) {
291 uint32_t accel_working = 0;
292 struct drm_amdgpu_info request = {
293 .return_pointer = (uintptr_t)&accel_working,
294 .return_size = sizeof(accel_working),
295 .query = AMDGPU_INFO_ACCEL_WORKING
296 };
297
298 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
299 close(master_fd);
300 master_fd = -1;
301 }
302 }
303 }
304
305 device->master_fd = master_fd;
306 device->local_fd = fd;
307 device->ws->query_info(device->ws, &device->rad_info);
308
309 radv_handle_env_var_force_family(device);
310
311 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
312
313 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
314 device->ws->destroy(device->ws);
315 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
316 "cannot generate UUID");
317 goto fail;
318 }
319
320 /* These flags affect shader compilation. */
321 uint64_t shader_env_flags =
322 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
323 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
324
325 /* The gpu id is already embedded in the uuid so we just pass "radv"
326 * when creating the cache.
327 */
328 char buf[VK_UUID_SIZE * 2 + 1];
329 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
330 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
331
332 if (device->rad_info.chip_class < VI ||
333 device->rad_info.chip_class > GFX9)
334 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
335
336 radv_get_driver_uuid(&device->driver_uuid);
337 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
338
339 if (device->rad_info.family == CHIP_STONEY ||
340 device->rad_info.chip_class >= GFX9) {
341 device->has_rbplus = true;
342 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
343 device->rad_info.family == CHIP_VEGA12 ||
344 device->rad_info.family == CHIP_RAVEN ||
345 device->rad_info.family == CHIP_RAVEN2;
346 }
347
348 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
349 * on SI.
350 */
351 device->has_clear_state = device->rad_info.chip_class >= CIK;
352
353 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
354
355 /* Vega10/Raven need a special workaround for a hardware bug. */
356 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
357 device->rad_info.family == CHIP_RAVEN;
358
359 /* Out-of-order primitive rasterization. */
360 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
361 device->rad_info.max_se >= 2;
362 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
363 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
364
365 device->dcc_msaa_allowed =
366 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
367
368 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
369 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
370 (device->rad_info.chip_class >= VI &&
371 device->rad_info.me_fw_feature >= 41);
372
373 radv_physical_device_init_mem_types(device);
374 radv_fill_device_extension_table(device, &device->supported_extensions);
375
376 device->bus_info = *drm_device->businfo.pci;
377
378 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
379 ac_print_gpu_info(&device->rad_info);
380
381 /* The WSI is structured as a layer on top of the driver, so this has
382 * to be the last part of initialization (at least until we get other
383 * semi-layers).
384 */
385 result = radv_init_wsi(device);
386 if (result != VK_SUCCESS) {
387 device->ws->destroy(device->ws);
388 vk_error(instance, result);
389 goto fail;
390 }
391
392 return VK_SUCCESS;
393
394 fail:
395 close(fd);
396 if (master_fd != -1)
397 close(master_fd);
398 return result;
399 }
400
401 static void
402 radv_physical_device_finish(struct radv_physical_device *device)
403 {
404 radv_finish_wsi(device);
405 device->ws->destroy(device->ws);
406 disk_cache_destroy(device->disk_cache);
407 close(device->local_fd);
408 if (device->master_fd != -1)
409 close(device->master_fd);
410 }
411
412 static void *
413 default_alloc_func(void *pUserData, size_t size, size_t align,
414 VkSystemAllocationScope allocationScope)
415 {
416 return malloc(size);
417 }
418
419 static void *
420 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
421 size_t align, VkSystemAllocationScope allocationScope)
422 {
423 return realloc(pOriginal, size);
424 }
425
426 static void
427 default_free_func(void *pUserData, void *pMemory)
428 {
429 free(pMemory);
430 }
431
432 static const VkAllocationCallbacks default_alloc = {
433 .pUserData = NULL,
434 .pfnAllocation = default_alloc_func,
435 .pfnReallocation = default_realloc_func,
436 .pfnFree = default_free_func,
437 };
438
439 static const struct debug_control radv_debug_options[] = {
440 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
441 {"nodcc", RADV_DEBUG_NO_DCC},
442 {"shaders", RADV_DEBUG_DUMP_SHADERS},
443 {"nocache", RADV_DEBUG_NO_CACHE},
444 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
445 {"nohiz", RADV_DEBUG_NO_HIZ},
446 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
447 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
448 {"allbos", RADV_DEBUG_ALL_BOS},
449 {"noibs", RADV_DEBUG_NO_IBS},
450 {"spirv", RADV_DEBUG_DUMP_SPIRV},
451 {"vmfaults", RADV_DEBUG_VM_FAULTS},
452 {"zerovram", RADV_DEBUG_ZERO_VRAM},
453 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
454 {"nosisched", RADV_DEBUG_NO_SISCHED},
455 {"preoptir", RADV_DEBUG_PREOPTIR},
456 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
457 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
458 {"info", RADV_DEBUG_INFO},
459 {"errors", RADV_DEBUG_ERRORS},
460 {"startup", RADV_DEBUG_STARTUP},
461 {"checkir", RADV_DEBUG_CHECKIR},
462 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
463 {"nobinning", RADV_DEBUG_NOBINNING},
464 {NULL, 0}
465 };
466
467 const char *
468 radv_get_debug_option_name(int id)
469 {
470 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
471 return radv_debug_options[id].string;
472 }
473
474 static const struct debug_control radv_perftest_options[] = {
475 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
476 {"sisched", RADV_PERFTEST_SISCHED},
477 {"localbos", RADV_PERFTEST_LOCAL_BOS},
478 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
479 {NULL, 0}
480 };
481
482 const char *
483 radv_get_perftest_option_name(int id)
484 {
485 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
486 return radv_perftest_options[id].string;
487 }
488
489 static void
490 radv_handle_per_app_options(struct radv_instance *instance,
491 const VkApplicationInfo *info)
492 {
493 const char *name = info ? info->pApplicationName : NULL;
494
495 if (!name)
496 return;
497
498 if (!strcmp(name, "Talos - Linux - 32bit") ||
499 !strcmp(name, "Talos - Linux - 64bit")) {
500 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
501 /* Force enable LLVM sisched for Talos because it looks
502 * safe and it gives few more FPS.
503 */
504 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
505 }
506 } else if (!strcmp(name, "DOOM_VFR")) {
507 /* Work around a Doom VFR game bug */
508 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
509 }
510 }
511
512 static int radv_get_instance_extension_index(const char *name)
513 {
514 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
515 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
516 return i;
517 }
518 return -1;
519 }
520
521
522 VkResult radv_CreateInstance(
523 const VkInstanceCreateInfo* pCreateInfo,
524 const VkAllocationCallbacks* pAllocator,
525 VkInstance* pInstance)
526 {
527 struct radv_instance *instance;
528 VkResult result;
529
530 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
531
532 uint32_t client_version;
533 if (pCreateInfo->pApplicationInfo &&
534 pCreateInfo->pApplicationInfo->apiVersion != 0) {
535 client_version = pCreateInfo->pApplicationInfo->apiVersion;
536 } else {
537 client_version = VK_API_VERSION_1_0;
538 }
539
540 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
541 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
542 if (!instance)
543 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
544
545 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
546
547 if (pAllocator)
548 instance->alloc = *pAllocator;
549 else
550 instance->alloc = default_alloc;
551
552 instance->apiVersion = client_version;
553 instance->physicalDeviceCount = -1;
554
555 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
556 radv_debug_options);
557
558 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
559 radv_perftest_options);
560
561
562 if (instance->debug_flags & RADV_DEBUG_STARTUP)
563 radv_logi("Created an instance");
564
565 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
566 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
567 int index = radv_get_instance_extension_index(ext_name);
568
569 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
570 vk_free2(&default_alloc, pAllocator, instance);
571 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
572 }
573
574 instance->enabled_extensions.extensions[index] = true;
575 }
576
577 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
578 if (result != VK_SUCCESS) {
579 vk_free2(&default_alloc, pAllocator, instance);
580 return vk_error(instance, result);
581 }
582
583 _mesa_locale_init();
584
585 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
586
587 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
588
589 *pInstance = radv_instance_to_handle(instance);
590
591 return VK_SUCCESS;
592 }
593
594 void radv_DestroyInstance(
595 VkInstance _instance,
596 const VkAllocationCallbacks* pAllocator)
597 {
598 RADV_FROM_HANDLE(radv_instance, instance, _instance);
599
600 if (!instance)
601 return;
602
603 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
604 radv_physical_device_finish(instance->physicalDevices + i);
605 }
606
607 VG(VALGRIND_DESTROY_MEMPOOL(instance));
608
609 _mesa_locale_fini();
610
611 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
612
613 vk_free(&instance->alloc, instance);
614 }
615
616 static VkResult
617 radv_enumerate_devices(struct radv_instance *instance)
618 {
619 /* TODO: Check for more devices ? */
620 drmDevicePtr devices[8];
621 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
622 int max_devices;
623
624 instance->physicalDeviceCount = 0;
625
626 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
627
628 if (instance->debug_flags & RADV_DEBUG_STARTUP)
629 radv_logi("Found %d drm nodes", max_devices);
630
631 if (max_devices < 1)
632 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
633
634 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
635 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
636 devices[i]->bustype == DRM_BUS_PCI &&
637 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
638
639 result = radv_physical_device_init(instance->physicalDevices +
640 instance->physicalDeviceCount,
641 instance,
642 devices[i]);
643 if (result == VK_SUCCESS)
644 ++instance->physicalDeviceCount;
645 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
646 break;
647 }
648 }
649 drmFreeDevices(devices, max_devices);
650
651 return result;
652 }
653
654 VkResult radv_EnumeratePhysicalDevices(
655 VkInstance _instance,
656 uint32_t* pPhysicalDeviceCount,
657 VkPhysicalDevice* pPhysicalDevices)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660 VkResult result;
661
662 if (instance->physicalDeviceCount < 0) {
663 result = radv_enumerate_devices(instance);
664 if (result != VK_SUCCESS &&
665 result != VK_ERROR_INCOMPATIBLE_DRIVER)
666 return result;
667 }
668
669 if (!pPhysicalDevices) {
670 *pPhysicalDeviceCount = instance->physicalDeviceCount;
671 } else {
672 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
673 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
674 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
675 }
676
677 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
678 : VK_SUCCESS;
679 }
680
681 VkResult radv_EnumeratePhysicalDeviceGroups(
682 VkInstance _instance,
683 uint32_t* pPhysicalDeviceGroupCount,
684 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
685 {
686 RADV_FROM_HANDLE(radv_instance, instance, _instance);
687 VkResult result;
688
689 if (instance->physicalDeviceCount < 0) {
690 result = radv_enumerate_devices(instance);
691 if (result != VK_SUCCESS &&
692 result != VK_ERROR_INCOMPATIBLE_DRIVER)
693 return result;
694 }
695
696 if (!pPhysicalDeviceGroupProperties) {
697 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
698 } else {
699 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
700 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
701 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
702 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
703 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
704 }
705 }
706 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
707 : VK_SUCCESS;
708 }
709
710 void radv_GetPhysicalDeviceFeatures(
711 VkPhysicalDevice physicalDevice,
712 VkPhysicalDeviceFeatures* pFeatures)
713 {
714 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
715 memset(pFeatures, 0, sizeof(*pFeatures));
716
717 *pFeatures = (VkPhysicalDeviceFeatures) {
718 .robustBufferAccess = true,
719 .fullDrawIndexUint32 = true,
720 .imageCubeArray = true,
721 .independentBlend = true,
722 .geometryShader = true,
723 .tessellationShader = true,
724 .sampleRateShading = true,
725 .dualSrcBlend = true,
726 .logicOp = true,
727 .multiDrawIndirect = true,
728 .drawIndirectFirstInstance = true,
729 .depthClamp = true,
730 .depthBiasClamp = true,
731 .fillModeNonSolid = true,
732 .depthBounds = true,
733 .wideLines = true,
734 .largePoints = true,
735 .alphaToOne = true,
736 .multiViewport = true,
737 .samplerAnisotropy = true,
738 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
739 .textureCompressionASTC_LDR = false,
740 .textureCompressionBC = true,
741 .occlusionQueryPrecise = true,
742 .pipelineStatisticsQuery = true,
743 .vertexPipelineStoresAndAtomics = true,
744 .fragmentStoresAndAtomics = true,
745 .shaderTessellationAndGeometryPointSize = true,
746 .shaderImageGatherExtended = true,
747 .shaderStorageImageExtendedFormats = true,
748 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
749 .shaderUniformBufferArrayDynamicIndexing = true,
750 .shaderSampledImageArrayDynamicIndexing = true,
751 .shaderStorageBufferArrayDynamicIndexing = true,
752 .shaderStorageImageArrayDynamicIndexing = true,
753 .shaderStorageImageReadWithoutFormat = true,
754 .shaderStorageImageWriteWithoutFormat = true,
755 .shaderClipDistance = true,
756 .shaderCullDistance = true,
757 .shaderFloat64 = true,
758 .shaderInt64 = true,
759 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
760 .sparseBinding = true,
761 .variableMultisampleRate = true,
762 .inheritedQueries = true,
763 };
764 }
765
766 void radv_GetPhysicalDeviceFeatures2(
767 VkPhysicalDevice physicalDevice,
768 VkPhysicalDeviceFeatures2 *pFeatures)
769 {
770 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
771 vk_foreach_struct(ext, pFeatures->pNext) {
772 switch (ext->sType) {
773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
774 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
775 features->variablePointersStorageBuffer = true;
776 features->variablePointers = true;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
780 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
781 features->multiview = true;
782 features->multiviewGeometryShader = true;
783 features->multiviewTessellationShader = true;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
787 VkPhysicalDeviceShaderDrawParameterFeatures *features =
788 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
789 features->shaderDrawParameters = true;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
793 VkPhysicalDeviceProtectedMemoryFeatures *features =
794 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
795 features->protectedMemory = false;
796 break;
797 }
798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
799 VkPhysicalDevice16BitStorageFeatures *features =
800 (VkPhysicalDevice16BitStorageFeatures*)ext;
801 bool enabled = pdevice->rad_info.chip_class >= VI;
802 features->storageBuffer16BitAccess = enabled;
803 features->uniformAndStorageBuffer16BitAccess = enabled;
804 features->storagePushConstant16 = enabled;
805 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
806 break;
807 }
808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
809 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
810 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
811 features->samplerYcbcrConversion = false;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
815 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
816 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
817 features->shaderInputAttachmentArrayDynamicIndexing = true;
818 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
819 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
820 features->shaderUniformBufferArrayNonUniformIndexing = true;
821 features->shaderSampledImageArrayNonUniformIndexing = true;
822 features->shaderStorageBufferArrayNonUniformIndexing = true;
823 features->shaderStorageImageArrayNonUniformIndexing = true;
824 features->shaderInputAttachmentArrayNonUniformIndexing = true;
825 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
826 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
827 features->descriptorBindingUniformBufferUpdateAfterBind = true;
828 features->descriptorBindingSampledImageUpdateAfterBind = true;
829 features->descriptorBindingStorageImageUpdateAfterBind = true;
830 features->descriptorBindingStorageBufferUpdateAfterBind = true;
831 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
832 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
833 features->descriptorBindingUpdateUnusedWhilePending = true;
834 features->descriptorBindingPartiallyBound = true;
835 features->descriptorBindingVariableDescriptorCount = true;
836 features->runtimeDescriptorArray = true;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
840 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
841 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
842 features->conditionalRendering = true;
843 features->inheritedConditionalRendering = false;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
847 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
848 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
849 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
850 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
854 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
855 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
856 features->transformFeedback = true;
857 features->geometryStreams = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
861 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
862 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
863 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
864 break;
865 }
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
867 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
868 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
869 features->memoryPriority = VK_TRUE;
870 break;
871 }
872 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
873 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
874 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
875 features->bufferDeviceAddress = true;
876 features->bufferDeviceAddressCaptureReplay = false;
877 features->bufferDeviceAddressMultiDevice = false;
878 break;
879 }
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
881 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
882 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
883 features->depthClipEnable = true;
884 break;
885 }
886 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
887 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
888 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
889 features->hostQueryReset = true;
890 break;
891 }
892 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
893 VkPhysicalDevice8BitStorageFeaturesKHR *features =
894 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
895 bool enabled = pdevice->rad_info.chip_class >= VI;
896 features->storageBuffer8BitAccess = enabled;
897 features->uniformAndStorageBuffer8BitAccess = enabled;
898 features->storagePushConstant8 = enabled;
899 break;
900 }
901 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
902 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
903 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
904 bool enabled = pdevice->rad_info.chip_class >= VI;
905 features->shaderFloat16 = VK_FALSE;
906 features->shaderInt8 = enabled;
907 break;
908 }
909 default:
910 break;
911 }
912 }
913 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
914 }
915
916 void radv_GetPhysicalDeviceProperties(
917 VkPhysicalDevice physicalDevice,
918 VkPhysicalDeviceProperties* pProperties)
919 {
920 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
921 VkSampleCountFlags sample_counts = 0xf;
922
923 /* make sure that the entire descriptor set is addressable with a signed
924 * 32-bit int. So the sum of all limits scaled by descriptor size has to
925 * be at most 2 GiB. the combined image & samples object count as one of
926 * both. This limit is for the pipeline layout, not for the set layout, but
927 * there is no set limit, so we just set a pipeline limit. I don't think
928 * any app is going to hit this soon. */
929 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
930 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
931 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
932 32 /* sampler, largest when combined with image */ +
933 64 /* sampled image */ +
934 64 /* storage image */);
935
936 VkPhysicalDeviceLimits limits = {
937 .maxImageDimension1D = (1 << 14),
938 .maxImageDimension2D = (1 << 14),
939 .maxImageDimension3D = (1 << 11),
940 .maxImageDimensionCube = (1 << 14),
941 .maxImageArrayLayers = (1 << 11),
942 .maxTexelBufferElements = 128 * 1024 * 1024,
943 .maxUniformBufferRange = UINT32_MAX,
944 .maxStorageBufferRange = UINT32_MAX,
945 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
946 .maxMemoryAllocationCount = UINT32_MAX,
947 .maxSamplerAllocationCount = 64 * 1024,
948 .bufferImageGranularity = 64, /* A cache line */
949 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
950 .maxBoundDescriptorSets = MAX_SETS,
951 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
952 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
953 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
954 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
955 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
956 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
957 .maxPerStageResources = max_descriptor_set_size,
958 .maxDescriptorSetSamplers = max_descriptor_set_size,
959 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
960 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
961 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
962 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
963 .maxDescriptorSetSampledImages = max_descriptor_set_size,
964 .maxDescriptorSetStorageImages = max_descriptor_set_size,
965 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
966 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
967 .maxVertexInputBindings = MAX_VBS,
968 .maxVertexInputAttributeOffset = 2047,
969 .maxVertexInputBindingStride = 2048,
970 .maxVertexOutputComponents = 128,
971 .maxTessellationGenerationLevel = 64,
972 .maxTessellationPatchSize = 32,
973 .maxTessellationControlPerVertexInputComponents = 128,
974 .maxTessellationControlPerVertexOutputComponents = 128,
975 .maxTessellationControlPerPatchOutputComponents = 120,
976 .maxTessellationControlTotalOutputComponents = 4096,
977 .maxTessellationEvaluationInputComponents = 128,
978 .maxTessellationEvaluationOutputComponents = 128,
979 .maxGeometryShaderInvocations = 127,
980 .maxGeometryInputComponents = 64,
981 .maxGeometryOutputComponents = 128,
982 .maxGeometryOutputVertices = 256,
983 .maxGeometryTotalOutputComponents = 1024,
984 .maxFragmentInputComponents = 128,
985 .maxFragmentOutputAttachments = 8,
986 .maxFragmentDualSrcAttachments = 1,
987 .maxFragmentCombinedOutputResources = 8,
988 .maxComputeSharedMemorySize = 32768,
989 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
990 .maxComputeWorkGroupInvocations = 2048,
991 .maxComputeWorkGroupSize = {
992 2048,
993 2048,
994 2048
995 },
996 .subPixelPrecisionBits = 8,
997 .subTexelPrecisionBits = 8,
998 .mipmapPrecisionBits = 8,
999 .maxDrawIndexedIndexValue = UINT32_MAX,
1000 .maxDrawIndirectCount = UINT32_MAX,
1001 .maxSamplerLodBias = 16,
1002 .maxSamplerAnisotropy = 16,
1003 .maxViewports = MAX_VIEWPORTS,
1004 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1005 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1006 .viewportSubPixelBits = 8,
1007 .minMemoryMapAlignment = 4096, /* A page */
1008 .minTexelBufferOffsetAlignment = 1,
1009 .minUniformBufferOffsetAlignment = 4,
1010 .minStorageBufferOffsetAlignment = 4,
1011 .minTexelOffset = -32,
1012 .maxTexelOffset = 31,
1013 .minTexelGatherOffset = -32,
1014 .maxTexelGatherOffset = 31,
1015 .minInterpolationOffset = -2,
1016 .maxInterpolationOffset = 2,
1017 .subPixelInterpolationOffsetBits = 8,
1018 .maxFramebufferWidth = (1 << 14),
1019 .maxFramebufferHeight = (1 << 14),
1020 .maxFramebufferLayers = (1 << 10),
1021 .framebufferColorSampleCounts = sample_counts,
1022 .framebufferDepthSampleCounts = sample_counts,
1023 .framebufferStencilSampleCounts = sample_counts,
1024 .framebufferNoAttachmentsSampleCounts = sample_counts,
1025 .maxColorAttachments = MAX_RTS,
1026 .sampledImageColorSampleCounts = sample_counts,
1027 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1028 .sampledImageDepthSampleCounts = sample_counts,
1029 .sampledImageStencilSampleCounts = sample_counts,
1030 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1031 .maxSampleMaskWords = 1,
1032 .timestampComputeAndGraphics = true,
1033 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1034 .maxClipDistances = 8,
1035 .maxCullDistances = 8,
1036 .maxCombinedClipAndCullDistances = 8,
1037 .discreteQueuePriorities = 2,
1038 .pointSizeRange = { 0.0, 8192.0 },
1039 .lineWidthRange = { 0.0, 7.9921875 },
1040 .pointSizeGranularity = (1.0 / 8.0),
1041 .lineWidthGranularity = (1.0 / 128.0),
1042 .strictLines = false, /* FINISHME */
1043 .standardSampleLocations = true,
1044 .optimalBufferCopyOffsetAlignment = 128,
1045 .optimalBufferCopyRowPitchAlignment = 128,
1046 .nonCoherentAtomSize = 64,
1047 };
1048
1049 *pProperties = (VkPhysicalDeviceProperties) {
1050 .apiVersion = radv_physical_device_api_version(pdevice),
1051 .driverVersion = vk_get_driver_version(),
1052 .vendorID = ATI_VENDOR_ID,
1053 .deviceID = pdevice->rad_info.pci_id,
1054 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1055 .limits = limits,
1056 .sparseProperties = {0},
1057 };
1058
1059 strcpy(pProperties->deviceName, pdevice->name);
1060 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1061 }
1062
1063 void radv_GetPhysicalDeviceProperties2(
1064 VkPhysicalDevice physicalDevice,
1065 VkPhysicalDeviceProperties2 *pProperties)
1066 {
1067 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1068 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1069
1070 vk_foreach_struct(ext, pProperties->pNext) {
1071 switch (ext->sType) {
1072 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1073 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1074 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1075 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1076 break;
1077 }
1078 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1079 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1080 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1081 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1082 properties->deviceLUIDValid = false;
1083 break;
1084 }
1085 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1086 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1087 properties->maxMultiviewViewCount = MAX_VIEWS;
1088 properties->maxMultiviewInstanceIndex = INT_MAX;
1089 break;
1090 }
1091 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1092 VkPhysicalDevicePointClippingProperties *properties =
1093 (VkPhysicalDevicePointClippingProperties*)ext;
1094 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1095 break;
1096 }
1097 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1098 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1099 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1100 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1104 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1105 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1106 properties->minImportedHostPointerAlignment = 4096;
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1110 VkPhysicalDeviceSubgroupProperties *properties =
1111 (VkPhysicalDeviceSubgroupProperties*)ext;
1112 properties->subgroupSize = 64;
1113 properties->supportedStages = VK_SHADER_STAGE_ALL;
1114 properties->supportedOperations =
1115 VK_SUBGROUP_FEATURE_BASIC_BIT |
1116 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1117 VK_SUBGROUP_FEATURE_QUAD_BIT |
1118 VK_SUBGROUP_FEATURE_VOTE_BIT;
1119 if (pdevice->rad_info.chip_class >= VI) {
1120 properties->supportedOperations |=
1121 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1122 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1123 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1124 }
1125 properties->quadOperationsInAllStages = true;
1126 break;
1127 }
1128 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1129 VkPhysicalDeviceMaintenance3Properties *properties =
1130 (VkPhysicalDeviceMaintenance3Properties*)ext;
1131 /* Make sure everything is addressable by a signed 32-bit int, and
1132 * our largest descriptors are 96 bytes. */
1133 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1134 /* Our buffer size fields allow only this much */
1135 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1139 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1140 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1141 /* GFX6-8 only support single channel min/max filter. */
1142 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1143 properties->filterMinmaxSingleComponentFormats = true;
1144 break;
1145 }
1146 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1147 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1148 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1149
1150 /* Shader engines. */
1151 properties->shaderEngineCount =
1152 pdevice->rad_info.max_se;
1153 properties->shaderArraysPerEngineCount =
1154 pdevice->rad_info.max_sh_per_se;
1155 properties->computeUnitsPerShaderArray =
1156 pdevice->rad_info.num_good_cu_per_sh;
1157 properties->simdPerComputeUnit = 4;
1158 properties->wavefrontsPerSimd =
1159 pdevice->rad_info.family == CHIP_TONGA ||
1160 pdevice->rad_info.family == CHIP_ICELAND ||
1161 pdevice->rad_info.family == CHIP_POLARIS10 ||
1162 pdevice->rad_info.family == CHIP_POLARIS11 ||
1163 pdevice->rad_info.family == CHIP_POLARIS12 ||
1164 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1165 properties->wavefrontSize = 64;
1166
1167 /* SGPR. */
1168 properties->sgprsPerSimd =
1169 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1170 properties->minSgprAllocation =
1171 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1172 properties->maxSgprAllocation =
1173 pdevice->rad_info.family == CHIP_TONGA ||
1174 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1175 properties->sgprAllocationGranularity =
1176 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1177
1178 /* VGPR. */
1179 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1180 properties->minVgprAllocation = 4;
1181 properties->maxVgprAllocation = 256;
1182 properties->vgprAllocationGranularity = 4;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1186 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1187 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1188 properties->maxVertexAttribDivisor = UINT32_MAX;
1189 break;
1190 }
1191 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1192 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1193 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1194 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1195 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1196 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1197 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1198 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1199 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1200 properties->robustBufferAccessUpdateAfterBind = false;
1201 properties->quadDivergentImplicitLod = false;
1202
1203 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1204 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1205 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1206 32 /* sampler, largest when combined with image */ +
1207 64 /* sampled image */ +
1208 64 /* storage image */);
1209 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1210 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1211 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1212 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1213 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1214 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1215 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1216 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1217 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1218 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1219 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1220 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1221 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1222 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1223 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1224 break;
1225 }
1226 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1227 VkPhysicalDeviceProtectedMemoryProperties *properties =
1228 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1229 properties->protectedNoFault = false;
1230 break;
1231 }
1232 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1233 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1234 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1235 properties->primitiveOverestimationSize = 0;
1236 properties->maxExtraPrimitiveOverestimationSize = 0;
1237 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1238 properties->primitiveUnderestimation = VK_FALSE;
1239 properties->conservativePointAndLineRasterization = VK_FALSE;
1240 properties->degenerateTrianglesRasterized = VK_FALSE;
1241 properties->degenerateLinesRasterized = VK_FALSE;
1242 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1243 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1244 break;
1245 }
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1247 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1248 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1249 properties->pciDomain = pdevice->bus_info.domain;
1250 properties->pciBus = pdevice->bus_info.bus;
1251 properties->pciDevice = pdevice->bus_info.dev;
1252 properties->pciFunction = pdevice->bus_info.func;
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1256 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1257 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1258
1259 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1260 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1261 strcpy(driver_props->driverName, "radv");
1262
1263 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1264 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1265 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1266 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1267
1268 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1269 .major = 1,
1270 .minor = 1,
1271 .subminor = 2,
1272 .patch = 0,
1273 };
1274 break;
1275 }
1276 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1277 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1278 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1279 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1280 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1281 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1282 properties->maxTransformFeedbackStreamDataSize = 512;
1283 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1284 properties->maxTransformFeedbackBufferDataStride = 512;
1285 properties->transformFeedbackQueries = true;
1286 properties->transformFeedbackStreamsLinesTriangles = false;
1287 properties->transformFeedbackRasterizationStreamSelect = false;
1288 properties->transformFeedbackDraw = true;
1289 break;
1290 }
1291 default:
1292 break;
1293 }
1294 }
1295 }
1296
1297 static void radv_get_physical_device_queue_family_properties(
1298 struct radv_physical_device* pdevice,
1299 uint32_t* pCount,
1300 VkQueueFamilyProperties** pQueueFamilyProperties)
1301 {
1302 int num_queue_families = 1;
1303 int idx;
1304 if (pdevice->rad_info.num_compute_rings > 0 &&
1305 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1306 num_queue_families++;
1307
1308 if (pQueueFamilyProperties == NULL) {
1309 *pCount = num_queue_families;
1310 return;
1311 }
1312
1313 if (!*pCount)
1314 return;
1315
1316 idx = 0;
1317 if (*pCount >= 1) {
1318 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1319 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1320 VK_QUEUE_COMPUTE_BIT |
1321 VK_QUEUE_TRANSFER_BIT |
1322 VK_QUEUE_SPARSE_BINDING_BIT,
1323 .queueCount = 1,
1324 .timestampValidBits = 64,
1325 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1326 };
1327 idx++;
1328 }
1329
1330 if (pdevice->rad_info.num_compute_rings > 0 &&
1331 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1332 if (*pCount > idx) {
1333 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1334 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1335 VK_QUEUE_TRANSFER_BIT |
1336 VK_QUEUE_SPARSE_BINDING_BIT,
1337 .queueCount = pdevice->rad_info.num_compute_rings,
1338 .timestampValidBits = 64,
1339 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1340 };
1341 idx++;
1342 }
1343 }
1344 *pCount = idx;
1345 }
1346
1347 void radv_GetPhysicalDeviceQueueFamilyProperties(
1348 VkPhysicalDevice physicalDevice,
1349 uint32_t* pCount,
1350 VkQueueFamilyProperties* pQueueFamilyProperties)
1351 {
1352 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1353 if (!pQueueFamilyProperties) {
1354 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1355 return;
1356 }
1357 VkQueueFamilyProperties *properties[] = {
1358 pQueueFamilyProperties + 0,
1359 pQueueFamilyProperties + 1,
1360 pQueueFamilyProperties + 2,
1361 };
1362 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1363 assert(*pCount <= 3);
1364 }
1365
1366 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1367 VkPhysicalDevice physicalDevice,
1368 uint32_t* pCount,
1369 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1370 {
1371 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1372 if (!pQueueFamilyProperties) {
1373 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1374 return;
1375 }
1376 VkQueueFamilyProperties *properties[] = {
1377 &pQueueFamilyProperties[0].queueFamilyProperties,
1378 &pQueueFamilyProperties[1].queueFamilyProperties,
1379 &pQueueFamilyProperties[2].queueFamilyProperties,
1380 };
1381 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1382 assert(*pCount <= 3);
1383 }
1384
1385 void radv_GetPhysicalDeviceMemoryProperties(
1386 VkPhysicalDevice physicalDevice,
1387 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1388 {
1389 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1390
1391 *pMemoryProperties = physical_device->memory_properties;
1392 }
1393
1394 static void
1395 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1396 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1397 {
1398 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1399 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1400 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1401 uint64_t vram_size = radv_get_vram_size(device);
1402 uint64_t gtt_size = device->rad_info.gart_size;
1403 uint64_t heap_budget, heap_usage;
1404
1405 /* For all memory heaps, the computation of budget is as follow:
1406 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1407 *
1408 * The Vulkan spec 1.1.97 says that the budget should include any
1409 * currently allocated device memory.
1410 *
1411 * Note that the application heap usages are not really accurate (eg.
1412 * in presence of shared buffers).
1413 */
1414 if (vram_size) {
1415 heap_usage = device->ws->query_value(device->ws,
1416 RADEON_ALLOCATED_VRAM);
1417
1418 heap_budget = vram_size -
1419 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1420 heap_usage;
1421
1422 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1423 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1424 }
1425
1426 if (visible_vram_size) {
1427 heap_usage = device->ws->query_value(device->ws,
1428 RADEON_ALLOCATED_VRAM_VIS);
1429
1430 heap_budget = visible_vram_size -
1431 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1432 heap_usage;
1433
1434 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1435 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1436 }
1437
1438 if (gtt_size) {
1439 heap_usage = device->ws->query_value(device->ws,
1440 RADEON_ALLOCATED_GTT);
1441
1442 heap_budget = gtt_size -
1443 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1444 heap_usage;
1445
1446 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1447 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1448 }
1449
1450 /* The heapBudget and heapUsage values must be zero for array elements
1451 * greater than or equal to
1452 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1453 */
1454 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1455 memoryBudget->heapBudget[i] = 0;
1456 memoryBudget->heapUsage[i] = 0;
1457 }
1458 }
1459
1460 void radv_GetPhysicalDeviceMemoryProperties2(
1461 VkPhysicalDevice physicalDevice,
1462 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1463 {
1464 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1465 &pMemoryProperties->memoryProperties);
1466
1467 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1468 vk_find_struct(pMemoryProperties->pNext,
1469 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1470 if (memory_budget)
1471 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1472 }
1473
1474 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1475 VkDevice _device,
1476 VkExternalMemoryHandleTypeFlagBits handleType,
1477 const void *pHostPointer,
1478 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1479 {
1480 RADV_FROM_HANDLE(radv_device, device, _device);
1481
1482 switch (handleType)
1483 {
1484 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1485 const struct radv_physical_device *physical_device = device->physical_device;
1486 uint32_t memoryTypeBits = 0;
1487 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1488 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1489 memoryTypeBits = (1 << i);
1490 break;
1491 }
1492 }
1493 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1494 return VK_SUCCESS;
1495 }
1496 default:
1497 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1498 }
1499 }
1500
1501 static enum radeon_ctx_priority
1502 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1503 {
1504 /* Default to MEDIUM when a specific global priority isn't requested */
1505 if (!pObj)
1506 return RADEON_CTX_PRIORITY_MEDIUM;
1507
1508 switch(pObj->globalPriority) {
1509 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1510 return RADEON_CTX_PRIORITY_REALTIME;
1511 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1512 return RADEON_CTX_PRIORITY_HIGH;
1513 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1514 return RADEON_CTX_PRIORITY_MEDIUM;
1515 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1516 return RADEON_CTX_PRIORITY_LOW;
1517 default:
1518 unreachable("Illegal global priority value");
1519 return RADEON_CTX_PRIORITY_INVALID;
1520 }
1521 }
1522
1523 static int
1524 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1525 uint32_t queue_family_index, int idx,
1526 VkDeviceQueueCreateFlags flags,
1527 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1528 {
1529 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1530 queue->device = device;
1531 queue->queue_family_index = queue_family_index;
1532 queue->queue_idx = idx;
1533 queue->priority = radv_get_queue_global_priority(global_priority);
1534 queue->flags = flags;
1535
1536 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1537 if (!queue->hw_ctx)
1538 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1539
1540 return VK_SUCCESS;
1541 }
1542
1543 static void
1544 radv_queue_finish(struct radv_queue *queue)
1545 {
1546 if (queue->hw_ctx)
1547 queue->device->ws->ctx_destroy(queue->hw_ctx);
1548
1549 if (queue->initial_full_flush_preamble_cs)
1550 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1551 if (queue->initial_preamble_cs)
1552 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1553 if (queue->continue_preamble_cs)
1554 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1555 if (queue->descriptor_bo)
1556 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1557 if (queue->scratch_bo)
1558 queue->device->ws->buffer_destroy(queue->scratch_bo);
1559 if (queue->esgs_ring_bo)
1560 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1561 if (queue->gsvs_ring_bo)
1562 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1563 if (queue->tess_rings_bo)
1564 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1565 if (queue->compute_scratch_bo)
1566 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1567 }
1568
1569 static void
1570 radv_bo_list_init(struct radv_bo_list *bo_list)
1571 {
1572 pthread_mutex_init(&bo_list->mutex, NULL);
1573 bo_list->list.count = bo_list->capacity = 0;
1574 bo_list->list.bos = NULL;
1575 }
1576
1577 static void
1578 radv_bo_list_finish(struct radv_bo_list *bo_list)
1579 {
1580 free(bo_list->list.bos);
1581 pthread_mutex_destroy(&bo_list->mutex);
1582 }
1583
1584 static VkResult radv_bo_list_add(struct radv_device *device,
1585 struct radeon_winsys_bo *bo)
1586 {
1587 struct radv_bo_list *bo_list = &device->bo_list;
1588
1589 if (bo->is_local)
1590 return VK_SUCCESS;
1591
1592 if (unlikely(!device->use_global_bo_list))
1593 return VK_SUCCESS;
1594
1595 pthread_mutex_lock(&bo_list->mutex);
1596 if (bo_list->list.count == bo_list->capacity) {
1597 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1598 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1599
1600 if (!data) {
1601 pthread_mutex_unlock(&bo_list->mutex);
1602 return VK_ERROR_OUT_OF_HOST_MEMORY;
1603 }
1604
1605 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1606 bo_list->capacity = capacity;
1607 }
1608
1609 bo_list->list.bos[bo_list->list.count++] = bo;
1610 pthread_mutex_unlock(&bo_list->mutex);
1611 return VK_SUCCESS;
1612 }
1613
1614 static void radv_bo_list_remove(struct radv_device *device,
1615 struct radeon_winsys_bo *bo)
1616 {
1617 struct radv_bo_list *bo_list = &device->bo_list;
1618
1619 if (bo->is_local)
1620 return;
1621
1622 if (unlikely(!device->use_global_bo_list))
1623 return;
1624
1625 pthread_mutex_lock(&bo_list->mutex);
1626 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1627 if (bo_list->list.bos[i] == bo) {
1628 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1629 --bo_list->list.count;
1630 break;
1631 }
1632 }
1633 pthread_mutex_unlock(&bo_list->mutex);
1634 }
1635
1636 static void
1637 radv_device_init_gs_info(struct radv_device *device)
1638 {
1639 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1640 device->physical_device->rad_info.family);
1641 }
1642
1643 static int radv_get_device_extension_index(const char *name)
1644 {
1645 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1646 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1647 return i;
1648 }
1649 return -1;
1650 }
1651
1652 static int
1653 radv_get_int_debug_option(const char *name, int default_value)
1654 {
1655 const char *str;
1656 int result;
1657
1658 str = getenv(name);
1659 if (!str) {
1660 result = default_value;
1661 } else {
1662 char *endptr;
1663
1664 result = strtol(str, &endptr, 0);
1665 if (str == endptr) {
1666 /* No digits founs. */
1667 result = default_value;
1668 }
1669 }
1670
1671 return result;
1672 }
1673
1674 VkResult radv_CreateDevice(
1675 VkPhysicalDevice physicalDevice,
1676 const VkDeviceCreateInfo* pCreateInfo,
1677 const VkAllocationCallbacks* pAllocator,
1678 VkDevice* pDevice)
1679 {
1680 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1681 VkResult result;
1682 struct radv_device *device;
1683
1684 bool keep_shader_info = false;
1685
1686 /* Check enabled features */
1687 if (pCreateInfo->pEnabledFeatures) {
1688 VkPhysicalDeviceFeatures supported_features;
1689 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1690 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1691 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1692 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1693 for (uint32_t i = 0; i < num_features; i++) {
1694 if (enabled_feature[i] && !supported_feature[i])
1695 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1696 }
1697 }
1698
1699 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1700 sizeof(*device), 8,
1701 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1702 if (!device)
1703 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1704
1705 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1706 device->instance = physical_device->instance;
1707 device->physical_device = physical_device;
1708
1709 device->ws = physical_device->ws;
1710 if (pAllocator)
1711 device->alloc = *pAllocator;
1712 else
1713 device->alloc = physical_device->instance->alloc;
1714
1715 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1716 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1717 int index = radv_get_device_extension_index(ext_name);
1718 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1719 vk_free(&device->alloc, device);
1720 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1721 }
1722
1723 device->enabled_extensions.extensions[index] = true;
1724 }
1725
1726 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1727
1728 /* With update after bind we can't attach bo's to the command buffer
1729 * from the descriptor set anymore, so we have to use a global BO list.
1730 */
1731 device->use_global_bo_list =
1732 device->enabled_extensions.EXT_descriptor_indexing ||
1733 device->enabled_extensions.EXT_buffer_device_address;
1734
1735 mtx_init(&device->shader_slab_mutex, mtx_plain);
1736 list_inithead(&device->shader_slabs);
1737
1738 radv_bo_list_init(&device->bo_list);
1739
1740 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1741 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1742 uint32_t qfi = queue_create->queueFamilyIndex;
1743 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1744 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1745
1746 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1747
1748 device->queues[qfi] = vk_alloc(&device->alloc,
1749 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1750 if (!device->queues[qfi]) {
1751 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1752 goto fail;
1753 }
1754
1755 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1756
1757 device->queue_count[qfi] = queue_create->queueCount;
1758
1759 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1760 result = radv_queue_init(device, &device->queues[qfi][q],
1761 qfi, q, queue_create->flags,
1762 global_priority);
1763 if (result != VK_SUCCESS)
1764 goto fail;
1765 }
1766 }
1767
1768 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1769 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1770
1771 /* Disabled and not implemented for now. */
1772 device->dfsm_allowed = device->pbb_allowed &&
1773 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1774 device->physical_device->rad_info.family == CHIP_RAVEN2);
1775
1776 #ifdef ANDROID
1777 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1778 #endif
1779
1780 /* The maximum number of scratch waves. Scratch space isn't divided
1781 * evenly between CUs. The number is only a function of the number of CUs.
1782 * We can decrease the constant to decrease the scratch buffer size.
1783 *
1784 * sctx->scratch_waves must be >= the maximum possible size of
1785 * 1 threadgroup, so that the hw doesn't hang from being unable
1786 * to start any.
1787 *
1788 * The recommended value is 4 per CU at most. Higher numbers don't
1789 * bring much benefit, but they still occupy chip resources (think
1790 * async compute). I've seen ~2% performance difference between 4 and 32.
1791 */
1792 uint32_t max_threads_per_block = 2048;
1793 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1794 max_threads_per_block / 64);
1795
1796 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1797
1798 if (device->physical_device->rad_info.chip_class >= CIK) {
1799 /* If the KMD allows it (there is a KMD hw register for it),
1800 * allow launching waves out-of-order.
1801 */
1802 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1803 }
1804
1805 radv_device_init_gs_info(device);
1806
1807 device->tess_offchip_block_dw_size =
1808 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1809 device->has_distributed_tess =
1810 device->physical_device->rad_info.chip_class >= VI &&
1811 device->physical_device->rad_info.max_se >= 2;
1812
1813 if (getenv("RADV_TRACE_FILE")) {
1814 const char *filename = getenv("RADV_TRACE_FILE");
1815
1816 keep_shader_info = true;
1817
1818 if (!radv_init_trace(device))
1819 goto fail;
1820
1821 fprintf(stderr, "*****************************************************************************\n");
1822 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1823 fprintf(stderr, "*****************************************************************************\n");
1824
1825 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1826 radv_dump_enabled_options(device, stderr);
1827 }
1828
1829 device->keep_shader_info = keep_shader_info;
1830
1831 result = radv_device_init_meta(device);
1832 if (result != VK_SUCCESS)
1833 goto fail;
1834
1835 radv_device_init_msaa(device);
1836
1837 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1838 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1839 switch (family) {
1840 case RADV_QUEUE_GENERAL:
1841 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1842 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1843 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1844 break;
1845 case RADV_QUEUE_COMPUTE:
1846 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1847 radeon_emit(device->empty_cs[family], 0);
1848 break;
1849 }
1850 device->ws->cs_finalize(device->empty_cs[family]);
1851 }
1852
1853 if (device->physical_device->rad_info.chip_class >= CIK)
1854 cik_create_gfx_config(device);
1855
1856 VkPipelineCacheCreateInfo ci;
1857 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1858 ci.pNext = NULL;
1859 ci.flags = 0;
1860 ci.pInitialData = NULL;
1861 ci.initialDataSize = 0;
1862 VkPipelineCache pc;
1863 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1864 &ci, NULL, &pc);
1865 if (result != VK_SUCCESS)
1866 goto fail_meta;
1867
1868 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1869
1870 device->force_aniso =
1871 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1872 if (device->force_aniso >= 0) {
1873 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1874 1 << util_logbase2(device->force_aniso));
1875 }
1876
1877 *pDevice = radv_device_to_handle(device);
1878 return VK_SUCCESS;
1879
1880 fail_meta:
1881 radv_device_finish_meta(device);
1882 fail:
1883 radv_bo_list_finish(&device->bo_list);
1884
1885 if (device->trace_bo)
1886 device->ws->buffer_destroy(device->trace_bo);
1887
1888 if (device->gfx_init)
1889 device->ws->buffer_destroy(device->gfx_init);
1890
1891 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1892 for (unsigned q = 0; q < device->queue_count[i]; q++)
1893 radv_queue_finish(&device->queues[i][q]);
1894 if (device->queue_count[i])
1895 vk_free(&device->alloc, device->queues[i]);
1896 }
1897
1898 vk_free(&device->alloc, device);
1899 return result;
1900 }
1901
1902 void radv_DestroyDevice(
1903 VkDevice _device,
1904 const VkAllocationCallbacks* pAllocator)
1905 {
1906 RADV_FROM_HANDLE(radv_device, device, _device);
1907
1908 if (!device)
1909 return;
1910
1911 if (device->trace_bo)
1912 device->ws->buffer_destroy(device->trace_bo);
1913
1914 if (device->gfx_init)
1915 device->ws->buffer_destroy(device->gfx_init);
1916
1917 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1918 for (unsigned q = 0; q < device->queue_count[i]; q++)
1919 radv_queue_finish(&device->queues[i][q]);
1920 if (device->queue_count[i])
1921 vk_free(&device->alloc, device->queues[i]);
1922 if (device->empty_cs[i])
1923 device->ws->cs_destroy(device->empty_cs[i]);
1924 }
1925 radv_device_finish_meta(device);
1926
1927 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1928 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1929
1930 radv_destroy_shader_slabs(device);
1931
1932 radv_bo_list_finish(&device->bo_list);
1933 vk_free(&device->alloc, device);
1934 }
1935
1936 VkResult radv_EnumerateInstanceLayerProperties(
1937 uint32_t* pPropertyCount,
1938 VkLayerProperties* pProperties)
1939 {
1940 if (pProperties == NULL) {
1941 *pPropertyCount = 0;
1942 return VK_SUCCESS;
1943 }
1944
1945 /* None supported at this time */
1946 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1947 }
1948
1949 VkResult radv_EnumerateDeviceLayerProperties(
1950 VkPhysicalDevice physicalDevice,
1951 uint32_t* pPropertyCount,
1952 VkLayerProperties* pProperties)
1953 {
1954 if (pProperties == NULL) {
1955 *pPropertyCount = 0;
1956 return VK_SUCCESS;
1957 }
1958
1959 /* None supported at this time */
1960 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1961 }
1962
1963 void radv_GetDeviceQueue2(
1964 VkDevice _device,
1965 const VkDeviceQueueInfo2* pQueueInfo,
1966 VkQueue* pQueue)
1967 {
1968 RADV_FROM_HANDLE(radv_device, device, _device);
1969 struct radv_queue *queue;
1970
1971 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1972 if (pQueueInfo->flags != queue->flags) {
1973 /* From the Vulkan 1.1.70 spec:
1974 *
1975 * "The queue returned by vkGetDeviceQueue2 must have the same
1976 * flags value from this structure as that used at device
1977 * creation time in a VkDeviceQueueCreateInfo instance. If no
1978 * matching flags were specified at device creation time then
1979 * pQueue will return VK_NULL_HANDLE."
1980 */
1981 *pQueue = VK_NULL_HANDLE;
1982 return;
1983 }
1984
1985 *pQueue = radv_queue_to_handle(queue);
1986 }
1987
1988 void radv_GetDeviceQueue(
1989 VkDevice _device,
1990 uint32_t queueFamilyIndex,
1991 uint32_t queueIndex,
1992 VkQueue* pQueue)
1993 {
1994 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1995 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1996 .queueFamilyIndex = queueFamilyIndex,
1997 .queueIndex = queueIndex
1998 };
1999
2000 radv_GetDeviceQueue2(_device, &info, pQueue);
2001 }
2002
2003 static void
2004 fill_geom_tess_rings(struct radv_queue *queue,
2005 uint32_t *map,
2006 bool add_sample_positions,
2007 uint32_t esgs_ring_size,
2008 struct radeon_winsys_bo *esgs_ring_bo,
2009 uint32_t gsvs_ring_size,
2010 struct radeon_winsys_bo *gsvs_ring_bo,
2011 uint32_t tess_factor_ring_size,
2012 uint32_t tess_offchip_ring_offset,
2013 uint32_t tess_offchip_ring_size,
2014 struct radeon_winsys_bo *tess_rings_bo)
2015 {
2016 uint32_t *desc = &map[4];
2017
2018 if (esgs_ring_bo) {
2019 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2020
2021 /* stride 0, num records - size, add tid, swizzle, elsize4,
2022 index stride 64 */
2023 desc[0] = esgs_va;
2024 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2025 S_008F04_STRIDE(0) |
2026 S_008F04_SWIZZLE_ENABLE(true);
2027 desc[2] = esgs_ring_size;
2028 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2029 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2030 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2031 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2032 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2033 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2034 S_008F0C_ELEMENT_SIZE(1) |
2035 S_008F0C_INDEX_STRIDE(3) |
2036 S_008F0C_ADD_TID_ENABLE(true);
2037
2038 /* GS entry for ES->GS ring */
2039 /* stride 0, num records - size, elsize0,
2040 index stride 0 */
2041 desc[4] = esgs_va;
2042 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2043 S_008F04_STRIDE(0) |
2044 S_008F04_SWIZZLE_ENABLE(false);
2045 desc[6] = esgs_ring_size;
2046 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2047 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2048 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2049 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2050 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2051 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2052 S_008F0C_ELEMENT_SIZE(0) |
2053 S_008F0C_INDEX_STRIDE(0) |
2054 S_008F0C_ADD_TID_ENABLE(false);
2055 }
2056
2057 desc += 8;
2058
2059 if (gsvs_ring_bo) {
2060 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2061
2062 /* VS entry for GS->VS ring */
2063 /* stride 0, num records - size, elsize0,
2064 index stride 0 */
2065 desc[0] = gsvs_va;
2066 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2067 S_008F04_STRIDE(0) |
2068 S_008F04_SWIZZLE_ENABLE(false);
2069 desc[2] = gsvs_ring_size;
2070 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2071 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2072 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2073 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2074 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2075 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2076 S_008F0C_ELEMENT_SIZE(0) |
2077 S_008F0C_INDEX_STRIDE(0) |
2078 S_008F0C_ADD_TID_ENABLE(false);
2079
2080 /* stride gsvs_itemsize, num records 64
2081 elsize 4, index stride 16 */
2082 /* shader will patch stride and desc[2] */
2083 desc[4] = gsvs_va;
2084 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2085 S_008F04_STRIDE(0) |
2086 S_008F04_SWIZZLE_ENABLE(true);
2087 desc[6] = 0;
2088 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2089 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2090 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2091 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2092 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2093 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2094 S_008F0C_ELEMENT_SIZE(1) |
2095 S_008F0C_INDEX_STRIDE(1) |
2096 S_008F0C_ADD_TID_ENABLE(true);
2097 }
2098
2099 desc += 8;
2100
2101 if (tess_rings_bo) {
2102 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2103 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2104
2105 desc[0] = tess_va;
2106 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2107 S_008F04_STRIDE(0) |
2108 S_008F04_SWIZZLE_ENABLE(false);
2109 desc[2] = tess_factor_ring_size;
2110 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2111 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2112 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2113 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2114 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2115 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2116 S_008F0C_ELEMENT_SIZE(0) |
2117 S_008F0C_INDEX_STRIDE(0) |
2118 S_008F0C_ADD_TID_ENABLE(false);
2119
2120 desc[4] = tess_offchip_va;
2121 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2122 S_008F04_STRIDE(0) |
2123 S_008F04_SWIZZLE_ENABLE(false);
2124 desc[6] = tess_offchip_ring_size;
2125 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2126 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2127 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2128 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2129 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2130 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2131 S_008F0C_ELEMENT_SIZE(0) |
2132 S_008F0C_INDEX_STRIDE(0) |
2133 S_008F0C_ADD_TID_ENABLE(false);
2134 }
2135
2136 desc += 8;
2137
2138 if (add_sample_positions) {
2139 /* add sample positions after all rings */
2140 memcpy(desc, queue->device->sample_locations_1x, 8);
2141 desc += 2;
2142 memcpy(desc, queue->device->sample_locations_2x, 16);
2143 desc += 4;
2144 memcpy(desc, queue->device->sample_locations_4x, 32);
2145 desc += 8;
2146 memcpy(desc, queue->device->sample_locations_8x, 64);
2147 }
2148 }
2149
2150 static unsigned
2151 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2152 {
2153 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2154 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2155 device->physical_device->rad_info.family != CHIP_STONEY;
2156 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2157 unsigned max_offchip_buffers;
2158 unsigned offchip_granularity;
2159 unsigned hs_offchip_param;
2160
2161 /*
2162 * Per RadeonSI:
2163 * This must be one less than the maximum number due to a hw limitation.
2164 * Various hardware bugs in SI, CIK, and GFX9 need this.
2165 *
2166 * Per AMDVLK:
2167 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2168 * Gfx7 should limit max_offchip_buffers to 508
2169 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2170 *
2171 * Follow AMDVLK here.
2172 */
2173 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2174 device->physical_device->rad_info.chip_class == CIK ||
2175 device->physical_device->rad_info.chip_class == SI)
2176 --max_offchip_buffers_per_se;
2177
2178 max_offchip_buffers = max_offchip_buffers_per_se *
2179 device->physical_device->rad_info.max_se;
2180
2181 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2182 * around by setting 4K granularity.
2183 */
2184 if (device->tess_offchip_block_dw_size == 4096) {
2185 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2186 offchip_granularity = V_03093C_X_4K_DWORDS;
2187 } else {
2188 assert(device->tess_offchip_block_dw_size == 8192);
2189 offchip_granularity = V_03093C_X_8K_DWORDS;
2190 }
2191
2192 switch (device->physical_device->rad_info.chip_class) {
2193 case SI:
2194 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2195 break;
2196 case CIK:
2197 case VI:
2198 case GFX9:
2199 default:
2200 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2201 break;
2202 }
2203
2204 *max_offchip_buffers_p = max_offchip_buffers;
2205 if (device->physical_device->rad_info.chip_class >= CIK) {
2206 if (device->physical_device->rad_info.chip_class >= VI)
2207 --max_offchip_buffers;
2208 hs_offchip_param =
2209 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2210 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2211 } else {
2212 hs_offchip_param =
2213 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2214 }
2215 return hs_offchip_param;
2216 }
2217
2218 static void
2219 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2220 struct radeon_winsys_bo *esgs_ring_bo,
2221 uint32_t esgs_ring_size,
2222 struct radeon_winsys_bo *gsvs_ring_bo,
2223 uint32_t gsvs_ring_size)
2224 {
2225 if (!esgs_ring_bo && !gsvs_ring_bo)
2226 return;
2227
2228 if (esgs_ring_bo)
2229 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2230
2231 if (gsvs_ring_bo)
2232 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2233
2234 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2235 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2236 radeon_emit(cs, esgs_ring_size >> 8);
2237 radeon_emit(cs, gsvs_ring_size >> 8);
2238 } else {
2239 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2240 radeon_emit(cs, esgs_ring_size >> 8);
2241 radeon_emit(cs, gsvs_ring_size >> 8);
2242 }
2243 }
2244
2245 static void
2246 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2247 unsigned hs_offchip_param, unsigned tf_ring_size,
2248 struct radeon_winsys_bo *tess_rings_bo)
2249 {
2250 uint64_t tf_va;
2251
2252 if (!tess_rings_bo)
2253 return;
2254
2255 tf_va = radv_buffer_get_va(tess_rings_bo);
2256
2257 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2258
2259 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2260 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2261 S_030938_SIZE(tf_ring_size / 4));
2262 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2263 tf_va >> 8);
2264 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2265 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2266 S_030944_BASE_HI(tf_va >> 40));
2267 }
2268 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2269 hs_offchip_param);
2270 } else {
2271 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2272 S_008988_SIZE(tf_ring_size / 4));
2273 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2274 tf_va >> 8);
2275 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2276 hs_offchip_param);
2277 }
2278 }
2279
2280 static void
2281 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2282 struct radeon_winsys_bo *compute_scratch_bo)
2283 {
2284 uint64_t scratch_va;
2285
2286 if (!compute_scratch_bo)
2287 return;
2288
2289 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2290
2291 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2292
2293 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2294 radeon_emit(cs, scratch_va);
2295 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2296 S_008F04_SWIZZLE_ENABLE(1));
2297 }
2298
2299 static void
2300 radv_emit_global_shader_pointers(struct radv_queue *queue,
2301 struct radeon_cmdbuf *cs,
2302 struct radeon_winsys_bo *descriptor_bo)
2303 {
2304 uint64_t va;
2305
2306 if (!descriptor_bo)
2307 return;
2308
2309 va = radv_buffer_get_va(descriptor_bo);
2310
2311 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2312
2313 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2314 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2315 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2316 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2317 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2318
2319 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2320 radv_emit_shader_pointer(queue->device, cs, regs[i],
2321 va, true);
2322 }
2323 } else {
2324 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2325 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2326 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2327 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2328 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2329 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2330
2331 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2332 radv_emit_shader_pointer(queue->device, cs, regs[i],
2333 va, true);
2334 }
2335 }
2336 }
2337
2338 static void
2339 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2340 {
2341 struct radv_device *device = queue->device;
2342
2343 if (device->gfx_init) {
2344 uint64_t va = radv_buffer_get_va(device->gfx_init);
2345
2346 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2347 radeon_emit(cs, va);
2348 radeon_emit(cs, va >> 32);
2349 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2350
2351 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2352 } else {
2353 struct radv_physical_device *physical_device = device->physical_device;
2354 si_emit_graphics(physical_device, cs);
2355 }
2356 }
2357
2358 static void
2359 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2360 {
2361 struct radv_physical_device *physical_device = queue->device->physical_device;
2362 si_emit_compute(physical_device, cs);
2363 }
2364
2365 static VkResult
2366 radv_get_preamble_cs(struct radv_queue *queue,
2367 uint32_t scratch_size,
2368 uint32_t compute_scratch_size,
2369 uint32_t esgs_ring_size,
2370 uint32_t gsvs_ring_size,
2371 bool needs_tess_rings,
2372 bool needs_sample_positions,
2373 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2374 struct radeon_cmdbuf **initial_preamble_cs,
2375 struct radeon_cmdbuf **continue_preamble_cs)
2376 {
2377 struct radeon_winsys_bo *scratch_bo = NULL;
2378 struct radeon_winsys_bo *descriptor_bo = NULL;
2379 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2380 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2381 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2382 struct radeon_winsys_bo *tess_rings_bo = NULL;
2383 struct radeon_cmdbuf *dest_cs[3] = {0};
2384 bool add_tess_rings = false, add_sample_positions = false;
2385 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2386 unsigned max_offchip_buffers;
2387 unsigned hs_offchip_param = 0;
2388 unsigned tess_offchip_ring_offset;
2389 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2390 if (!queue->has_tess_rings) {
2391 if (needs_tess_rings)
2392 add_tess_rings = true;
2393 }
2394 if (!queue->has_sample_positions) {
2395 if (needs_sample_positions)
2396 add_sample_positions = true;
2397 }
2398 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2399 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2400 &max_offchip_buffers);
2401 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2402 tess_offchip_ring_size = max_offchip_buffers *
2403 queue->device->tess_offchip_block_dw_size * 4;
2404
2405 if (scratch_size <= queue->scratch_size &&
2406 compute_scratch_size <= queue->compute_scratch_size &&
2407 esgs_ring_size <= queue->esgs_ring_size &&
2408 gsvs_ring_size <= queue->gsvs_ring_size &&
2409 !add_tess_rings && !add_sample_positions &&
2410 queue->initial_preamble_cs) {
2411 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2412 *initial_preamble_cs = queue->initial_preamble_cs;
2413 *continue_preamble_cs = queue->continue_preamble_cs;
2414 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2415 *continue_preamble_cs = NULL;
2416 return VK_SUCCESS;
2417 }
2418
2419 if (scratch_size > queue->scratch_size) {
2420 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2421 scratch_size,
2422 4096,
2423 RADEON_DOMAIN_VRAM,
2424 ring_bo_flags,
2425 RADV_BO_PRIORITY_SCRATCH);
2426 if (!scratch_bo)
2427 goto fail;
2428 } else
2429 scratch_bo = queue->scratch_bo;
2430
2431 if (compute_scratch_size > queue->compute_scratch_size) {
2432 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2433 compute_scratch_size,
2434 4096,
2435 RADEON_DOMAIN_VRAM,
2436 ring_bo_flags,
2437 RADV_BO_PRIORITY_SCRATCH);
2438 if (!compute_scratch_bo)
2439 goto fail;
2440
2441 } else
2442 compute_scratch_bo = queue->compute_scratch_bo;
2443
2444 if (esgs_ring_size > queue->esgs_ring_size) {
2445 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2446 esgs_ring_size,
2447 4096,
2448 RADEON_DOMAIN_VRAM,
2449 ring_bo_flags,
2450 RADV_BO_PRIORITY_SCRATCH);
2451 if (!esgs_ring_bo)
2452 goto fail;
2453 } else {
2454 esgs_ring_bo = queue->esgs_ring_bo;
2455 esgs_ring_size = queue->esgs_ring_size;
2456 }
2457
2458 if (gsvs_ring_size > queue->gsvs_ring_size) {
2459 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2460 gsvs_ring_size,
2461 4096,
2462 RADEON_DOMAIN_VRAM,
2463 ring_bo_flags,
2464 RADV_BO_PRIORITY_SCRATCH);
2465 if (!gsvs_ring_bo)
2466 goto fail;
2467 } else {
2468 gsvs_ring_bo = queue->gsvs_ring_bo;
2469 gsvs_ring_size = queue->gsvs_ring_size;
2470 }
2471
2472 if (add_tess_rings) {
2473 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2474 tess_offchip_ring_offset + tess_offchip_ring_size,
2475 256,
2476 RADEON_DOMAIN_VRAM,
2477 ring_bo_flags,
2478 RADV_BO_PRIORITY_SCRATCH);
2479 if (!tess_rings_bo)
2480 goto fail;
2481 } else {
2482 tess_rings_bo = queue->tess_rings_bo;
2483 }
2484
2485 if (scratch_bo != queue->scratch_bo ||
2486 esgs_ring_bo != queue->esgs_ring_bo ||
2487 gsvs_ring_bo != queue->gsvs_ring_bo ||
2488 tess_rings_bo != queue->tess_rings_bo ||
2489 add_sample_positions) {
2490 uint32_t size = 0;
2491 if (gsvs_ring_bo || esgs_ring_bo ||
2492 tess_rings_bo || add_sample_positions) {
2493 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2494 if (add_sample_positions)
2495 size += 128; /* 64+32+16+8 = 120 bytes */
2496 }
2497 else if (scratch_bo)
2498 size = 8; /* 2 dword */
2499
2500 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2501 size,
2502 4096,
2503 RADEON_DOMAIN_VRAM,
2504 RADEON_FLAG_CPU_ACCESS |
2505 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2506 RADEON_FLAG_READ_ONLY,
2507 RADV_BO_PRIORITY_DESCRIPTOR);
2508 if (!descriptor_bo)
2509 goto fail;
2510 } else
2511 descriptor_bo = queue->descriptor_bo;
2512
2513 if (descriptor_bo != queue->descriptor_bo) {
2514 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2515
2516 if (scratch_bo) {
2517 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2518 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2519 S_008F04_SWIZZLE_ENABLE(1);
2520 map[0] = scratch_va;
2521 map[1] = rsrc1;
2522 }
2523
2524 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2525 fill_geom_tess_rings(queue, map, add_sample_positions,
2526 esgs_ring_size, esgs_ring_bo,
2527 gsvs_ring_size, gsvs_ring_bo,
2528 tess_factor_ring_size,
2529 tess_offchip_ring_offset,
2530 tess_offchip_ring_size,
2531 tess_rings_bo);
2532
2533 queue->device->ws->buffer_unmap(descriptor_bo);
2534 }
2535
2536 for(int i = 0; i < 3; ++i) {
2537 struct radeon_cmdbuf *cs = NULL;
2538 cs = queue->device->ws->cs_create(queue->device->ws,
2539 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2540 if (!cs)
2541 goto fail;
2542
2543 dest_cs[i] = cs;
2544
2545 if (scratch_bo)
2546 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2547
2548 /* Emit initial configuration. */
2549 switch (queue->queue_family_index) {
2550 case RADV_QUEUE_GENERAL:
2551 radv_init_graphics_state(cs, queue);
2552 break;
2553 case RADV_QUEUE_COMPUTE:
2554 radv_init_compute_state(cs, queue);
2555 break;
2556 case RADV_QUEUE_TRANSFER:
2557 break;
2558 }
2559
2560 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2561 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2562 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2563 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2564 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2565 }
2566
2567 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2568 gsvs_ring_bo, gsvs_ring_size);
2569 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2570 tess_factor_ring_size, tess_rings_bo);
2571 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2572 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2573
2574 if (i == 0) {
2575 si_cs_emit_cache_flush(cs,
2576 queue->device->physical_device->rad_info.chip_class,
2577 NULL, 0,
2578 queue->queue_family_index == RING_COMPUTE &&
2579 queue->device->physical_device->rad_info.chip_class >= CIK,
2580 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2581 RADV_CMD_FLAG_INV_ICACHE |
2582 RADV_CMD_FLAG_INV_SMEM_L1 |
2583 RADV_CMD_FLAG_INV_VMEM_L1 |
2584 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2585 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2586 } else if (i == 1) {
2587 si_cs_emit_cache_flush(cs,
2588 queue->device->physical_device->rad_info.chip_class,
2589 NULL, 0,
2590 queue->queue_family_index == RING_COMPUTE &&
2591 queue->device->physical_device->rad_info.chip_class >= CIK,
2592 RADV_CMD_FLAG_INV_ICACHE |
2593 RADV_CMD_FLAG_INV_SMEM_L1 |
2594 RADV_CMD_FLAG_INV_VMEM_L1 |
2595 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2596 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2597 }
2598
2599 if (!queue->device->ws->cs_finalize(cs))
2600 goto fail;
2601 }
2602
2603 if (queue->initial_full_flush_preamble_cs)
2604 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2605
2606 if (queue->initial_preamble_cs)
2607 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2608
2609 if (queue->continue_preamble_cs)
2610 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2611
2612 queue->initial_full_flush_preamble_cs = dest_cs[0];
2613 queue->initial_preamble_cs = dest_cs[1];
2614 queue->continue_preamble_cs = dest_cs[2];
2615
2616 if (scratch_bo != queue->scratch_bo) {
2617 if (queue->scratch_bo)
2618 queue->device->ws->buffer_destroy(queue->scratch_bo);
2619 queue->scratch_bo = scratch_bo;
2620 queue->scratch_size = scratch_size;
2621 }
2622
2623 if (compute_scratch_bo != queue->compute_scratch_bo) {
2624 if (queue->compute_scratch_bo)
2625 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2626 queue->compute_scratch_bo = compute_scratch_bo;
2627 queue->compute_scratch_size = compute_scratch_size;
2628 }
2629
2630 if (esgs_ring_bo != queue->esgs_ring_bo) {
2631 if (queue->esgs_ring_bo)
2632 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2633 queue->esgs_ring_bo = esgs_ring_bo;
2634 queue->esgs_ring_size = esgs_ring_size;
2635 }
2636
2637 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2638 if (queue->gsvs_ring_bo)
2639 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2640 queue->gsvs_ring_bo = gsvs_ring_bo;
2641 queue->gsvs_ring_size = gsvs_ring_size;
2642 }
2643
2644 if (tess_rings_bo != queue->tess_rings_bo) {
2645 queue->tess_rings_bo = tess_rings_bo;
2646 queue->has_tess_rings = true;
2647 }
2648
2649 if (descriptor_bo != queue->descriptor_bo) {
2650 if (queue->descriptor_bo)
2651 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2652
2653 queue->descriptor_bo = descriptor_bo;
2654 }
2655
2656 if (add_sample_positions)
2657 queue->has_sample_positions = true;
2658
2659 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2660 *initial_preamble_cs = queue->initial_preamble_cs;
2661 *continue_preamble_cs = queue->continue_preamble_cs;
2662 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2663 *continue_preamble_cs = NULL;
2664 return VK_SUCCESS;
2665 fail:
2666 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2667 if (dest_cs[i])
2668 queue->device->ws->cs_destroy(dest_cs[i]);
2669 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2670 queue->device->ws->buffer_destroy(descriptor_bo);
2671 if (scratch_bo && scratch_bo != queue->scratch_bo)
2672 queue->device->ws->buffer_destroy(scratch_bo);
2673 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2674 queue->device->ws->buffer_destroy(compute_scratch_bo);
2675 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2676 queue->device->ws->buffer_destroy(esgs_ring_bo);
2677 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2678 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2679 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2680 queue->device->ws->buffer_destroy(tess_rings_bo);
2681 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2682 }
2683
2684 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2685 struct radv_winsys_sem_counts *counts,
2686 int num_sems,
2687 const VkSemaphore *sems,
2688 VkFence _fence,
2689 bool reset_temp)
2690 {
2691 int syncobj_idx = 0, sem_idx = 0;
2692
2693 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2694 return VK_SUCCESS;
2695
2696 for (uint32_t i = 0; i < num_sems; i++) {
2697 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2698
2699 if (sem->temp_syncobj || sem->syncobj)
2700 counts->syncobj_count++;
2701 else
2702 counts->sem_count++;
2703 }
2704
2705 if (_fence != VK_NULL_HANDLE) {
2706 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2707 if (fence->temp_syncobj || fence->syncobj)
2708 counts->syncobj_count++;
2709 }
2710
2711 if (counts->syncobj_count) {
2712 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2713 if (!counts->syncobj)
2714 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2715 }
2716
2717 if (counts->sem_count) {
2718 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2719 if (!counts->sem) {
2720 free(counts->syncobj);
2721 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2722 }
2723 }
2724
2725 for (uint32_t i = 0; i < num_sems; i++) {
2726 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2727
2728 if (sem->temp_syncobj) {
2729 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2730 }
2731 else if (sem->syncobj)
2732 counts->syncobj[syncobj_idx++] = sem->syncobj;
2733 else {
2734 assert(sem->sem);
2735 counts->sem[sem_idx++] = sem->sem;
2736 }
2737 }
2738
2739 if (_fence != VK_NULL_HANDLE) {
2740 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2741 if (fence->temp_syncobj)
2742 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2743 else if (fence->syncobj)
2744 counts->syncobj[syncobj_idx++] = fence->syncobj;
2745 }
2746
2747 return VK_SUCCESS;
2748 }
2749
2750 static void
2751 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2752 {
2753 free(sem_info->wait.syncobj);
2754 free(sem_info->wait.sem);
2755 free(sem_info->signal.syncobj);
2756 free(sem_info->signal.sem);
2757 }
2758
2759
2760 static void radv_free_temp_syncobjs(struct radv_device *device,
2761 int num_sems,
2762 const VkSemaphore *sems)
2763 {
2764 for (uint32_t i = 0; i < num_sems; i++) {
2765 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2766
2767 if (sem->temp_syncobj) {
2768 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2769 sem->temp_syncobj = 0;
2770 }
2771 }
2772 }
2773
2774 static VkResult
2775 radv_alloc_sem_info(struct radv_instance *instance,
2776 struct radv_winsys_sem_info *sem_info,
2777 int num_wait_sems,
2778 const VkSemaphore *wait_sems,
2779 int num_signal_sems,
2780 const VkSemaphore *signal_sems,
2781 VkFence fence)
2782 {
2783 VkResult ret;
2784 memset(sem_info, 0, sizeof(*sem_info));
2785
2786 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2787 if (ret)
2788 return ret;
2789 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2790 if (ret)
2791 radv_free_sem_info(sem_info);
2792
2793 /* caller can override these */
2794 sem_info->cs_emit_wait = true;
2795 sem_info->cs_emit_signal = true;
2796 return ret;
2797 }
2798
2799 /* Signals fence as soon as all the work currently put on queue is done. */
2800 static VkResult radv_signal_fence(struct radv_queue *queue,
2801 struct radv_fence *fence)
2802 {
2803 int ret;
2804 VkResult result;
2805 struct radv_winsys_sem_info sem_info;
2806
2807 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2808 radv_fence_to_handle(fence));
2809 if (result != VK_SUCCESS)
2810 return result;
2811
2812 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2813 &queue->device->empty_cs[queue->queue_family_index],
2814 1, NULL, NULL, &sem_info, NULL,
2815 false, fence->fence);
2816 radv_free_sem_info(&sem_info);
2817
2818 if (ret)
2819 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2820
2821 return VK_SUCCESS;
2822 }
2823
2824 VkResult radv_QueueSubmit(
2825 VkQueue _queue,
2826 uint32_t submitCount,
2827 const VkSubmitInfo* pSubmits,
2828 VkFence _fence)
2829 {
2830 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2831 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2832 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2833 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2834 int ret;
2835 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2836 uint32_t scratch_size = 0;
2837 uint32_t compute_scratch_size = 0;
2838 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2839 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2840 VkResult result;
2841 bool fence_emitted = false;
2842 bool tess_rings_needed = false;
2843 bool sample_positions_needed = false;
2844
2845 /* Do this first so failing to allocate scratch buffers can't result in
2846 * partially executed submissions. */
2847 for (uint32_t i = 0; i < submitCount; i++) {
2848 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2849 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2850 pSubmits[i].pCommandBuffers[j]);
2851
2852 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2853 compute_scratch_size = MAX2(compute_scratch_size,
2854 cmd_buffer->compute_scratch_size_needed);
2855 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2856 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2857 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2858 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2859 }
2860 }
2861
2862 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2863 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2864 sample_positions_needed, &initial_flush_preamble_cs,
2865 &initial_preamble_cs, &continue_preamble_cs);
2866 if (result != VK_SUCCESS)
2867 return result;
2868
2869 for (uint32_t i = 0; i < submitCount; i++) {
2870 struct radeon_cmdbuf **cs_array;
2871 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2872 bool can_patch = true;
2873 uint32_t advance;
2874 struct radv_winsys_sem_info sem_info;
2875
2876 result = radv_alloc_sem_info(queue->device->instance,
2877 &sem_info,
2878 pSubmits[i].waitSemaphoreCount,
2879 pSubmits[i].pWaitSemaphores,
2880 pSubmits[i].signalSemaphoreCount,
2881 pSubmits[i].pSignalSemaphores,
2882 _fence);
2883 if (result != VK_SUCCESS)
2884 return result;
2885
2886 if (!pSubmits[i].commandBufferCount) {
2887 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2888 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2889 &queue->device->empty_cs[queue->queue_family_index],
2890 1, NULL, NULL,
2891 &sem_info, NULL,
2892 false, base_fence);
2893 if (ret) {
2894 radv_loge("failed to submit CS %d\n", i);
2895 abort();
2896 }
2897 fence_emitted = true;
2898 }
2899 radv_free_sem_info(&sem_info);
2900 continue;
2901 }
2902
2903 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2904 (pSubmits[i].commandBufferCount));
2905
2906 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2907 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2908 pSubmits[i].pCommandBuffers[j]);
2909 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2910
2911 cs_array[j] = cmd_buffer->cs;
2912 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2913 can_patch = false;
2914
2915 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2916 }
2917
2918 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2919 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2920 const struct radv_winsys_bo_list *bo_list = NULL;
2921
2922 advance = MIN2(max_cs_submission,
2923 pSubmits[i].commandBufferCount - j);
2924
2925 if (queue->device->trace_bo)
2926 *queue->device->trace_id_ptr = 0;
2927
2928 sem_info.cs_emit_wait = j == 0;
2929 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2930
2931 if (unlikely(queue->device->use_global_bo_list)) {
2932 pthread_mutex_lock(&queue->device->bo_list.mutex);
2933 bo_list = &queue->device->bo_list.list;
2934 }
2935
2936 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2937 advance, initial_preamble, continue_preamble_cs,
2938 &sem_info, bo_list,
2939 can_patch, base_fence);
2940
2941 if (unlikely(queue->device->use_global_bo_list))
2942 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2943
2944 if (ret) {
2945 radv_loge("failed to submit CS %d\n", i);
2946 abort();
2947 }
2948 fence_emitted = true;
2949 if (queue->device->trace_bo) {
2950 radv_check_gpu_hangs(queue, cs_array[j]);
2951 }
2952 }
2953
2954 radv_free_temp_syncobjs(queue->device,
2955 pSubmits[i].waitSemaphoreCount,
2956 pSubmits[i].pWaitSemaphores);
2957 radv_free_sem_info(&sem_info);
2958 free(cs_array);
2959 }
2960
2961 if (fence) {
2962 if (!fence_emitted) {
2963 result = radv_signal_fence(queue, fence);
2964 if (result != VK_SUCCESS)
2965 return result;
2966 }
2967 fence->submitted = true;
2968 }
2969
2970 return VK_SUCCESS;
2971 }
2972
2973 VkResult radv_QueueWaitIdle(
2974 VkQueue _queue)
2975 {
2976 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2977
2978 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2979 radv_queue_family_to_ring(queue->queue_family_index),
2980 queue->queue_idx);
2981 return VK_SUCCESS;
2982 }
2983
2984 VkResult radv_DeviceWaitIdle(
2985 VkDevice _device)
2986 {
2987 RADV_FROM_HANDLE(radv_device, device, _device);
2988
2989 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2990 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2991 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2992 }
2993 }
2994 return VK_SUCCESS;
2995 }
2996
2997 VkResult radv_EnumerateInstanceExtensionProperties(
2998 const char* pLayerName,
2999 uint32_t* pPropertyCount,
3000 VkExtensionProperties* pProperties)
3001 {
3002 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3003
3004 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3005 if (radv_supported_instance_extensions.extensions[i]) {
3006 vk_outarray_append(&out, prop) {
3007 *prop = radv_instance_extensions[i];
3008 }
3009 }
3010 }
3011
3012 return vk_outarray_status(&out);
3013 }
3014
3015 VkResult radv_EnumerateDeviceExtensionProperties(
3016 VkPhysicalDevice physicalDevice,
3017 const char* pLayerName,
3018 uint32_t* pPropertyCount,
3019 VkExtensionProperties* pProperties)
3020 {
3021 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3022 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3023
3024 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3025 if (device->supported_extensions.extensions[i]) {
3026 vk_outarray_append(&out, prop) {
3027 *prop = radv_device_extensions[i];
3028 }
3029 }
3030 }
3031
3032 return vk_outarray_status(&out);
3033 }
3034
3035 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3036 VkInstance _instance,
3037 const char* pName)
3038 {
3039 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3040
3041 return radv_lookup_entrypoint_checked(pName,
3042 instance ? instance->apiVersion : 0,
3043 instance ? &instance->enabled_extensions : NULL,
3044 NULL);
3045 }
3046
3047 /* The loader wants us to expose a second GetInstanceProcAddr function
3048 * to work around certain LD_PRELOAD issues seen in apps.
3049 */
3050 PUBLIC
3051 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3052 VkInstance instance,
3053 const char* pName);
3054
3055 PUBLIC
3056 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3057 VkInstance instance,
3058 const char* pName)
3059 {
3060 return radv_GetInstanceProcAddr(instance, pName);
3061 }
3062
3063 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3064 VkDevice _device,
3065 const char* pName)
3066 {
3067 RADV_FROM_HANDLE(radv_device, device, _device);
3068
3069 return radv_lookup_entrypoint_checked(pName,
3070 device->instance->apiVersion,
3071 &device->instance->enabled_extensions,
3072 &device->enabled_extensions);
3073 }
3074
3075 bool radv_get_memory_fd(struct radv_device *device,
3076 struct radv_device_memory *memory,
3077 int *pFD)
3078 {
3079 struct radeon_bo_metadata metadata;
3080
3081 if (memory->image) {
3082 radv_init_metadata(device, memory->image, &metadata);
3083 device->ws->buffer_set_metadata(memory->bo, &metadata);
3084 }
3085
3086 return device->ws->buffer_get_fd(device->ws, memory->bo,
3087 pFD);
3088 }
3089
3090 static VkResult radv_alloc_memory(struct radv_device *device,
3091 const VkMemoryAllocateInfo* pAllocateInfo,
3092 const VkAllocationCallbacks* pAllocator,
3093 VkDeviceMemory* pMem)
3094 {
3095 struct radv_device_memory *mem;
3096 VkResult result;
3097 enum radeon_bo_domain domain;
3098 uint32_t flags = 0;
3099 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3100
3101 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3102
3103 if (pAllocateInfo->allocationSize == 0) {
3104 /* Apparently, this is allowed */
3105 *pMem = VK_NULL_HANDLE;
3106 return VK_SUCCESS;
3107 }
3108
3109 const VkImportMemoryFdInfoKHR *import_info =
3110 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3111 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3112 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3113 const VkExportMemoryAllocateInfo *export_info =
3114 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3115 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3116 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3117
3118 const struct wsi_memory_allocate_info *wsi_info =
3119 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3120
3121 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3122 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3123 if (mem == NULL)
3124 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3125
3126 if (wsi_info && wsi_info->implicit_sync)
3127 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3128
3129 if (dedicate_info) {
3130 mem->image = radv_image_from_handle(dedicate_info->image);
3131 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3132 } else {
3133 mem->image = NULL;
3134 mem->buffer = NULL;
3135 }
3136
3137 float priority_float = 0.5;
3138 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3139 vk_find_struct_const(pAllocateInfo->pNext,
3140 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3141 if (priority_ext)
3142 priority_float = priority_ext->priority;
3143
3144 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3145 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3146
3147 mem->user_ptr = NULL;
3148
3149 if (import_info) {
3150 assert(import_info->handleType ==
3151 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3152 import_info->handleType ==
3153 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3154 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3155 priority, NULL, NULL);
3156 if (!mem->bo) {
3157 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3158 goto fail;
3159 } else {
3160 close(import_info->fd);
3161 }
3162 } else if (host_ptr_info) {
3163 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3164 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3165 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3166 pAllocateInfo->allocationSize,
3167 priority);
3168 if (!mem->bo) {
3169 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3170 goto fail;
3171 } else {
3172 mem->user_ptr = host_ptr_info->pHostPointer;
3173 }
3174 } else {
3175 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3176 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3177 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3178 domain = RADEON_DOMAIN_GTT;
3179 else
3180 domain = RADEON_DOMAIN_VRAM;
3181
3182 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3183 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3184 else
3185 flags |= RADEON_FLAG_CPU_ACCESS;
3186
3187 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3188 flags |= RADEON_FLAG_GTT_WC;
3189
3190 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3191 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3192
3193 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3194 domain, flags, priority);
3195
3196 if (!mem->bo) {
3197 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3198 goto fail;
3199 }
3200 mem->type_index = mem_type_index;
3201 }
3202
3203 result = radv_bo_list_add(device, mem->bo);
3204 if (result != VK_SUCCESS)
3205 goto fail_bo;
3206
3207 *pMem = radv_device_memory_to_handle(mem);
3208
3209 return VK_SUCCESS;
3210
3211 fail_bo:
3212 device->ws->buffer_destroy(mem->bo);
3213 fail:
3214 vk_free2(&device->alloc, pAllocator, mem);
3215
3216 return result;
3217 }
3218
3219 VkResult radv_AllocateMemory(
3220 VkDevice _device,
3221 const VkMemoryAllocateInfo* pAllocateInfo,
3222 const VkAllocationCallbacks* pAllocator,
3223 VkDeviceMemory* pMem)
3224 {
3225 RADV_FROM_HANDLE(radv_device, device, _device);
3226 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3227 }
3228
3229 void radv_FreeMemory(
3230 VkDevice _device,
3231 VkDeviceMemory _mem,
3232 const VkAllocationCallbacks* pAllocator)
3233 {
3234 RADV_FROM_HANDLE(radv_device, device, _device);
3235 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3236
3237 if (mem == NULL)
3238 return;
3239
3240 radv_bo_list_remove(device, mem->bo);
3241 device->ws->buffer_destroy(mem->bo);
3242 mem->bo = NULL;
3243
3244 vk_free2(&device->alloc, pAllocator, mem);
3245 }
3246
3247 VkResult radv_MapMemory(
3248 VkDevice _device,
3249 VkDeviceMemory _memory,
3250 VkDeviceSize offset,
3251 VkDeviceSize size,
3252 VkMemoryMapFlags flags,
3253 void** ppData)
3254 {
3255 RADV_FROM_HANDLE(radv_device, device, _device);
3256 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3257
3258 if (mem == NULL) {
3259 *ppData = NULL;
3260 return VK_SUCCESS;
3261 }
3262
3263 if (mem->user_ptr)
3264 *ppData = mem->user_ptr;
3265 else
3266 *ppData = device->ws->buffer_map(mem->bo);
3267
3268 if (*ppData) {
3269 *ppData += offset;
3270 return VK_SUCCESS;
3271 }
3272
3273 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3274 }
3275
3276 void radv_UnmapMemory(
3277 VkDevice _device,
3278 VkDeviceMemory _memory)
3279 {
3280 RADV_FROM_HANDLE(radv_device, device, _device);
3281 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3282
3283 if (mem == NULL)
3284 return;
3285
3286 if (mem->user_ptr == NULL)
3287 device->ws->buffer_unmap(mem->bo);
3288 }
3289
3290 VkResult radv_FlushMappedMemoryRanges(
3291 VkDevice _device,
3292 uint32_t memoryRangeCount,
3293 const VkMappedMemoryRange* pMemoryRanges)
3294 {
3295 return VK_SUCCESS;
3296 }
3297
3298 VkResult radv_InvalidateMappedMemoryRanges(
3299 VkDevice _device,
3300 uint32_t memoryRangeCount,
3301 const VkMappedMemoryRange* pMemoryRanges)
3302 {
3303 return VK_SUCCESS;
3304 }
3305
3306 void radv_GetBufferMemoryRequirements(
3307 VkDevice _device,
3308 VkBuffer _buffer,
3309 VkMemoryRequirements* pMemoryRequirements)
3310 {
3311 RADV_FROM_HANDLE(radv_device, device, _device);
3312 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3313
3314 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3315
3316 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3317 pMemoryRequirements->alignment = 4096;
3318 else
3319 pMemoryRequirements->alignment = 16;
3320
3321 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3322 }
3323
3324 void radv_GetBufferMemoryRequirements2(
3325 VkDevice device,
3326 const VkBufferMemoryRequirementsInfo2 *pInfo,
3327 VkMemoryRequirements2 *pMemoryRequirements)
3328 {
3329 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3330 &pMemoryRequirements->memoryRequirements);
3331 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3332 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3333 switch (ext->sType) {
3334 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3335 VkMemoryDedicatedRequirements *req =
3336 (VkMemoryDedicatedRequirements *) ext;
3337 req->requiresDedicatedAllocation = buffer->shareable;
3338 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3339 break;
3340 }
3341 default:
3342 break;
3343 }
3344 }
3345 }
3346
3347 void radv_GetImageMemoryRequirements(
3348 VkDevice _device,
3349 VkImage _image,
3350 VkMemoryRequirements* pMemoryRequirements)
3351 {
3352 RADV_FROM_HANDLE(radv_device, device, _device);
3353 RADV_FROM_HANDLE(radv_image, image, _image);
3354
3355 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3356
3357 pMemoryRequirements->size = image->size;
3358 pMemoryRequirements->alignment = image->alignment;
3359 }
3360
3361 void radv_GetImageMemoryRequirements2(
3362 VkDevice device,
3363 const VkImageMemoryRequirementsInfo2 *pInfo,
3364 VkMemoryRequirements2 *pMemoryRequirements)
3365 {
3366 radv_GetImageMemoryRequirements(device, pInfo->image,
3367 &pMemoryRequirements->memoryRequirements);
3368
3369 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3370
3371 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3372 switch (ext->sType) {
3373 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3374 VkMemoryDedicatedRequirements *req =
3375 (VkMemoryDedicatedRequirements *) ext;
3376 req->requiresDedicatedAllocation = image->shareable;
3377 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3378 break;
3379 }
3380 default:
3381 break;
3382 }
3383 }
3384 }
3385
3386 void radv_GetImageSparseMemoryRequirements(
3387 VkDevice device,
3388 VkImage image,
3389 uint32_t* pSparseMemoryRequirementCount,
3390 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3391 {
3392 stub();
3393 }
3394
3395 void radv_GetImageSparseMemoryRequirements2(
3396 VkDevice device,
3397 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3398 uint32_t* pSparseMemoryRequirementCount,
3399 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3400 {
3401 stub();
3402 }
3403
3404 void radv_GetDeviceMemoryCommitment(
3405 VkDevice device,
3406 VkDeviceMemory memory,
3407 VkDeviceSize* pCommittedMemoryInBytes)
3408 {
3409 *pCommittedMemoryInBytes = 0;
3410 }
3411
3412 VkResult radv_BindBufferMemory2(VkDevice device,
3413 uint32_t bindInfoCount,
3414 const VkBindBufferMemoryInfo *pBindInfos)
3415 {
3416 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3417 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3418 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3419
3420 if (mem) {
3421 buffer->bo = mem->bo;
3422 buffer->offset = pBindInfos[i].memoryOffset;
3423 } else {
3424 buffer->bo = NULL;
3425 }
3426 }
3427 return VK_SUCCESS;
3428 }
3429
3430 VkResult radv_BindBufferMemory(
3431 VkDevice device,
3432 VkBuffer buffer,
3433 VkDeviceMemory memory,
3434 VkDeviceSize memoryOffset)
3435 {
3436 const VkBindBufferMemoryInfo info = {
3437 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3438 .buffer = buffer,
3439 .memory = memory,
3440 .memoryOffset = memoryOffset
3441 };
3442
3443 return radv_BindBufferMemory2(device, 1, &info);
3444 }
3445
3446 VkResult radv_BindImageMemory2(VkDevice device,
3447 uint32_t bindInfoCount,
3448 const VkBindImageMemoryInfo *pBindInfos)
3449 {
3450 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3451 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3452 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3453
3454 if (mem) {
3455 image->bo = mem->bo;
3456 image->offset = pBindInfos[i].memoryOffset;
3457 } else {
3458 image->bo = NULL;
3459 image->offset = 0;
3460 }
3461 }
3462 return VK_SUCCESS;
3463 }
3464
3465
3466 VkResult radv_BindImageMemory(
3467 VkDevice device,
3468 VkImage image,
3469 VkDeviceMemory memory,
3470 VkDeviceSize memoryOffset)
3471 {
3472 const VkBindImageMemoryInfo info = {
3473 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3474 .image = image,
3475 .memory = memory,
3476 .memoryOffset = memoryOffset
3477 };
3478
3479 return radv_BindImageMemory2(device, 1, &info);
3480 }
3481
3482
3483 static void
3484 radv_sparse_buffer_bind_memory(struct radv_device *device,
3485 const VkSparseBufferMemoryBindInfo *bind)
3486 {
3487 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3488
3489 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3490 struct radv_device_memory *mem = NULL;
3491
3492 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3493 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3494
3495 device->ws->buffer_virtual_bind(buffer->bo,
3496 bind->pBinds[i].resourceOffset,
3497 bind->pBinds[i].size,
3498 mem ? mem->bo : NULL,
3499 bind->pBinds[i].memoryOffset);
3500 }
3501 }
3502
3503 static void
3504 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3505 const VkSparseImageOpaqueMemoryBindInfo *bind)
3506 {
3507 RADV_FROM_HANDLE(radv_image, image, bind->image);
3508
3509 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3510 struct radv_device_memory *mem = NULL;
3511
3512 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3513 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3514
3515 device->ws->buffer_virtual_bind(image->bo,
3516 bind->pBinds[i].resourceOffset,
3517 bind->pBinds[i].size,
3518 mem ? mem->bo : NULL,
3519 bind->pBinds[i].memoryOffset);
3520 }
3521 }
3522
3523 VkResult radv_QueueBindSparse(
3524 VkQueue _queue,
3525 uint32_t bindInfoCount,
3526 const VkBindSparseInfo* pBindInfo,
3527 VkFence _fence)
3528 {
3529 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3530 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3531 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3532 bool fence_emitted = false;
3533 VkResult result;
3534 int ret;
3535
3536 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3537 struct radv_winsys_sem_info sem_info;
3538 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3539 radv_sparse_buffer_bind_memory(queue->device,
3540 pBindInfo[i].pBufferBinds + j);
3541 }
3542
3543 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3544 radv_sparse_image_opaque_bind_memory(queue->device,
3545 pBindInfo[i].pImageOpaqueBinds + j);
3546 }
3547
3548 VkResult result;
3549 result = radv_alloc_sem_info(queue->device->instance,
3550 &sem_info,
3551 pBindInfo[i].waitSemaphoreCount,
3552 pBindInfo[i].pWaitSemaphores,
3553 pBindInfo[i].signalSemaphoreCount,
3554 pBindInfo[i].pSignalSemaphores,
3555 _fence);
3556 if (result != VK_SUCCESS)
3557 return result;
3558
3559 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3560 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3561 &queue->device->empty_cs[queue->queue_family_index],
3562 1, NULL, NULL,
3563 &sem_info, NULL,
3564 false, base_fence);
3565 if (ret) {
3566 radv_loge("failed to submit CS %d\n", i);
3567 abort();
3568 }
3569
3570 fence_emitted = true;
3571 if (fence)
3572 fence->submitted = true;
3573 }
3574
3575 radv_free_sem_info(&sem_info);
3576
3577 }
3578
3579 if (fence) {
3580 if (!fence_emitted) {
3581 result = radv_signal_fence(queue, fence);
3582 if (result != VK_SUCCESS)
3583 return result;
3584 }
3585 fence->submitted = true;
3586 }
3587
3588 return VK_SUCCESS;
3589 }
3590
3591 VkResult radv_CreateFence(
3592 VkDevice _device,
3593 const VkFenceCreateInfo* pCreateInfo,
3594 const VkAllocationCallbacks* pAllocator,
3595 VkFence* pFence)
3596 {
3597 RADV_FROM_HANDLE(radv_device, device, _device);
3598 const VkExportFenceCreateInfo *export =
3599 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3600 VkExternalFenceHandleTypeFlags handleTypes =
3601 export ? export->handleTypes : 0;
3602
3603 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3604 sizeof(*fence), 8,
3605 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3606
3607 if (!fence)
3608 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3609
3610 fence->fence_wsi = NULL;
3611 fence->submitted = false;
3612 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3613 fence->temp_syncobj = 0;
3614 if (device->always_use_syncobj || handleTypes) {
3615 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3616 if (ret) {
3617 vk_free2(&device->alloc, pAllocator, fence);
3618 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3619 }
3620 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3621 device->ws->signal_syncobj(device->ws, fence->syncobj);
3622 }
3623 fence->fence = NULL;
3624 } else {
3625 fence->fence = device->ws->create_fence();
3626 if (!fence->fence) {
3627 vk_free2(&device->alloc, pAllocator, fence);
3628 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3629 }
3630 fence->syncobj = 0;
3631 }
3632
3633 *pFence = radv_fence_to_handle(fence);
3634
3635 return VK_SUCCESS;
3636 }
3637
3638 void radv_DestroyFence(
3639 VkDevice _device,
3640 VkFence _fence,
3641 const VkAllocationCallbacks* pAllocator)
3642 {
3643 RADV_FROM_HANDLE(radv_device, device, _device);
3644 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3645
3646 if (!fence)
3647 return;
3648
3649 if (fence->temp_syncobj)
3650 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3651 if (fence->syncobj)
3652 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3653 if (fence->fence)
3654 device->ws->destroy_fence(fence->fence);
3655 if (fence->fence_wsi)
3656 fence->fence_wsi->destroy(fence->fence_wsi);
3657 vk_free2(&device->alloc, pAllocator, fence);
3658 }
3659
3660
3661 uint64_t radv_get_current_time(void)
3662 {
3663 struct timespec tv;
3664 clock_gettime(CLOCK_MONOTONIC, &tv);
3665 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3666 }
3667
3668 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3669 {
3670 uint64_t current_time = radv_get_current_time();
3671
3672 timeout = MIN2(UINT64_MAX - current_time, timeout);
3673
3674 return current_time + timeout;
3675 }
3676
3677
3678 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3679 {
3680 for (uint32_t i = 0; i < fenceCount; ++i) {
3681 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3682 if (fence->fence == NULL || fence->syncobj ||
3683 fence->temp_syncobj ||
3684 (!fence->signalled && !fence->submitted))
3685 return false;
3686 }
3687 return true;
3688 }
3689
3690 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3691 {
3692 for (uint32_t i = 0; i < fenceCount; ++i) {
3693 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3694 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3695 return false;
3696 }
3697 return true;
3698 }
3699
3700 VkResult radv_WaitForFences(
3701 VkDevice _device,
3702 uint32_t fenceCount,
3703 const VkFence* pFences,
3704 VkBool32 waitAll,
3705 uint64_t timeout)
3706 {
3707 RADV_FROM_HANDLE(radv_device, device, _device);
3708 timeout = radv_get_absolute_timeout(timeout);
3709
3710 if (device->always_use_syncobj &&
3711 radv_all_fences_syncobj(fenceCount, pFences))
3712 {
3713 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3714 if (!handles)
3715 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3716
3717 for (uint32_t i = 0; i < fenceCount; ++i) {
3718 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3719 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3720 }
3721
3722 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3723
3724 free(handles);
3725 return success ? VK_SUCCESS : VK_TIMEOUT;
3726 }
3727
3728 if (!waitAll && fenceCount > 1) {
3729 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3730 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3731 uint32_t wait_count = 0;
3732 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3733 if (!fences)
3734 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3735
3736 for (uint32_t i = 0; i < fenceCount; ++i) {
3737 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3738
3739 if (fence->signalled) {
3740 free(fences);
3741 return VK_SUCCESS;
3742 }
3743
3744 fences[wait_count++] = fence->fence;
3745 }
3746
3747 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3748 waitAll, timeout - radv_get_current_time());
3749
3750 free(fences);
3751 return success ? VK_SUCCESS : VK_TIMEOUT;
3752 }
3753
3754 while(radv_get_current_time() <= timeout) {
3755 for (uint32_t i = 0; i < fenceCount; ++i) {
3756 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3757 return VK_SUCCESS;
3758 }
3759 }
3760 return VK_TIMEOUT;
3761 }
3762
3763 for (uint32_t i = 0; i < fenceCount; ++i) {
3764 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3765 bool expired = false;
3766
3767 if (fence->temp_syncobj) {
3768 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3769 return VK_TIMEOUT;
3770 continue;
3771 }
3772
3773 if (fence->syncobj) {
3774 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3775 return VK_TIMEOUT;
3776 continue;
3777 }
3778
3779 if (fence->signalled)
3780 continue;
3781
3782 if (fence->fence) {
3783 if (!fence->submitted) {
3784 while(radv_get_current_time() <= timeout &&
3785 !fence->submitted)
3786 /* Do nothing */;
3787
3788 if (!fence->submitted)
3789 return VK_TIMEOUT;
3790
3791 /* Recheck as it may have been set by
3792 * submitting operations. */
3793
3794 if (fence->signalled)
3795 continue;
3796 }
3797
3798 expired = device->ws->fence_wait(device->ws,
3799 fence->fence,
3800 true, timeout);
3801 if (!expired)
3802 return VK_TIMEOUT;
3803 }
3804
3805 if (fence->fence_wsi) {
3806 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3807 if (result != VK_SUCCESS)
3808 return result;
3809 }
3810
3811 fence->signalled = true;
3812 }
3813
3814 return VK_SUCCESS;
3815 }
3816
3817 VkResult radv_ResetFences(VkDevice _device,
3818 uint32_t fenceCount,
3819 const VkFence *pFences)
3820 {
3821 RADV_FROM_HANDLE(radv_device, device, _device);
3822
3823 for (unsigned i = 0; i < fenceCount; ++i) {
3824 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3825 fence->submitted = fence->signalled = false;
3826
3827 /* Per spec, we first restore the permanent payload, and then reset, so
3828 * having a temp syncobj should not skip resetting the permanent syncobj. */
3829 if (fence->temp_syncobj) {
3830 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3831 fence->temp_syncobj = 0;
3832 }
3833
3834 if (fence->syncobj) {
3835 device->ws->reset_syncobj(device->ws, fence->syncobj);
3836 }
3837 }
3838
3839 return VK_SUCCESS;
3840 }
3841
3842 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3843 {
3844 RADV_FROM_HANDLE(radv_device, device, _device);
3845 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3846
3847 if (fence->temp_syncobj) {
3848 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3849 return success ? VK_SUCCESS : VK_NOT_READY;
3850 }
3851
3852 if (fence->syncobj) {
3853 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3854 return success ? VK_SUCCESS : VK_NOT_READY;
3855 }
3856
3857 if (fence->signalled)
3858 return VK_SUCCESS;
3859 if (!fence->submitted)
3860 return VK_NOT_READY;
3861 if (fence->fence) {
3862 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3863 return VK_NOT_READY;
3864 }
3865 if (fence->fence_wsi) {
3866 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3867
3868 if (result != VK_SUCCESS) {
3869 if (result == VK_TIMEOUT)
3870 return VK_NOT_READY;
3871 return result;
3872 }
3873 }
3874 return VK_SUCCESS;
3875 }
3876
3877
3878 // Queue semaphore functions
3879
3880 VkResult radv_CreateSemaphore(
3881 VkDevice _device,
3882 const VkSemaphoreCreateInfo* pCreateInfo,
3883 const VkAllocationCallbacks* pAllocator,
3884 VkSemaphore* pSemaphore)
3885 {
3886 RADV_FROM_HANDLE(radv_device, device, _device);
3887 const VkExportSemaphoreCreateInfo *export =
3888 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3889 VkExternalSemaphoreHandleTypeFlags handleTypes =
3890 export ? export->handleTypes : 0;
3891
3892 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3893 sizeof(*sem), 8,
3894 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3895 if (!sem)
3896 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3897
3898 sem->temp_syncobj = 0;
3899 /* create a syncobject if we are going to export this semaphore */
3900 if (device->always_use_syncobj || handleTypes) {
3901 assert (device->physical_device->rad_info.has_syncobj);
3902 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3903 if (ret) {
3904 vk_free2(&device->alloc, pAllocator, sem);
3905 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3906 }
3907 sem->sem = NULL;
3908 } else {
3909 sem->sem = device->ws->create_sem(device->ws);
3910 if (!sem->sem) {
3911 vk_free2(&device->alloc, pAllocator, sem);
3912 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3913 }
3914 sem->syncobj = 0;
3915 }
3916
3917 *pSemaphore = radv_semaphore_to_handle(sem);
3918 return VK_SUCCESS;
3919 }
3920
3921 void radv_DestroySemaphore(
3922 VkDevice _device,
3923 VkSemaphore _semaphore,
3924 const VkAllocationCallbacks* pAllocator)
3925 {
3926 RADV_FROM_HANDLE(radv_device, device, _device);
3927 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3928 if (!_semaphore)
3929 return;
3930
3931 if (sem->syncobj)
3932 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3933 else
3934 device->ws->destroy_sem(sem->sem);
3935 vk_free2(&device->alloc, pAllocator, sem);
3936 }
3937
3938 VkResult radv_CreateEvent(
3939 VkDevice _device,
3940 const VkEventCreateInfo* pCreateInfo,
3941 const VkAllocationCallbacks* pAllocator,
3942 VkEvent* pEvent)
3943 {
3944 RADV_FROM_HANDLE(radv_device, device, _device);
3945 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3946 sizeof(*event), 8,
3947 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3948
3949 if (!event)
3950 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3951
3952 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3953 RADEON_DOMAIN_GTT,
3954 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3955 RADV_BO_PRIORITY_FENCE);
3956 if (!event->bo) {
3957 vk_free2(&device->alloc, pAllocator, event);
3958 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3959 }
3960
3961 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3962
3963 *pEvent = radv_event_to_handle(event);
3964
3965 return VK_SUCCESS;
3966 }
3967
3968 void radv_DestroyEvent(
3969 VkDevice _device,
3970 VkEvent _event,
3971 const VkAllocationCallbacks* pAllocator)
3972 {
3973 RADV_FROM_HANDLE(radv_device, device, _device);
3974 RADV_FROM_HANDLE(radv_event, event, _event);
3975
3976 if (!event)
3977 return;
3978 device->ws->buffer_destroy(event->bo);
3979 vk_free2(&device->alloc, pAllocator, event);
3980 }
3981
3982 VkResult radv_GetEventStatus(
3983 VkDevice _device,
3984 VkEvent _event)
3985 {
3986 RADV_FROM_HANDLE(radv_event, event, _event);
3987
3988 if (*event->map == 1)
3989 return VK_EVENT_SET;
3990 return VK_EVENT_RESET;
3991 }
3992
3993 VkResult radv_SetEvent(
3994 VkDevice _device,
3995 VkEvent _event)
3996 {
3997 RADV_FROM_HANDLE(radv_event, event, _event);
3998 *event->map = 1;
3999
4000 return VK_SUCCESS;
4001 }
4002
4003 VkResult radv_ResetEvent(
4004 VkDevice _device,
4005 VkEvent _event)
4006 {
4007 RADV_FROM_HANDLE(radv_event, event, _event);
4008 *event->map = 0;
4009
4010 return VK_SUCCESS;
4011 }
4012
4013 VkResult radv_CreateBuffer(
4014 VkDevice _device,
4015 const VkBufferCreateInfo* pCreateInfo,
4016 const VkAllocationCallbacks* pAllocator,
4017 VkBuffer* pBuffer)
4018 {
4019 RADV_FROM_HANDLE(radv_device, device, _device);
4020 struct radv_buffer *buffer;
4021
4022 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4023
4024 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4025 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4026 if (buffer == NULL)
4027 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4028
4029 buffer->size = pCreateInfo->size;
4030 buffer->usage = pCreateInfo->usage;
4031 buffer->bo = NULL;
4032 buffer->offset = 0;
4033 buffer->flags = pCreateInfo->flags;
4034
4035 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4036 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4037
4038 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4039 buffer->bo = device->ws->buffer_create(device->ws,
4040 align64(buffer->size, 4096),
4041 4096, 0, RADEON_FLAG_VIRTUAL,
4042 RADV_BO_PRIORITY_VIRTUAL);
4043 if (!buffer->bo) {
4044 vk_free2(&device->alloc, pAllocator, buffer);
4045 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4046 }
4047 }
4048
4049 *pBuffer = radv_buffer_to_handle(buffer);
4050
4051 return VK_SUCCESS;
4052 }
4053
4054 void radv_DestroyBuffer(
4055 VkDevice _device,
4056 VkBuffer _buffer,
4057 const VkAllocationCallbacks* pAllocator)
4058 {
4059 RADV_FROM_HANDLE(radv_device, device, _device);
4060 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4061
4062 if (!buffer)
4063 return;
4064
4065 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4066 device->ws->buffer_destroy(buffer->bo);
4067
4068 vk_free2(&device->alloc, pAllocator, buffer);
4069 }
4070
4071 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4072 VkDevice device,
4073 const VkBufferDeviceAddressInfoEXT* pInfo)
4074 {
4075 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4076 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4077 }
4078
4079
4080 static inline unsigned
4081 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4082 {
4083 if (stencil)
4084 return image->surface.u.legacy.stencil_tiling_index[level];
4085 else
4086 return image->surface.u.legacy.tiling_index[level];
4087 }
4088
4089 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4090 {
4091 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4092 }
4093
4094 static uint32_t
4095 radv_init_dcc_control_reg(struct radv_device *device,
4096 struct radv_image_view *iview)
4097 {
4098 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4099 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4100 unsigned max_compressed_block_size;
4101 unsigned independent_64b_blocks;
4102
4103 if (!radv_image_has_dcc(iview->image))
4104 return 0;
4105
4106 if (iview->image->info.samples > 1) {
4107 if (iview->image->surface.bpe == 1)
4108 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4109 else if (iview->image->surface.bpe == 2)
4110 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4111 }
4112
4113 if (!device->physical_device->rad_info.has_dedicated_vram) {
4114 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4115 * dGPU and 64 for APU because all of our APUs to date use
4116 * DIMMs which have a request granularity size of 64B while all
4117 * other chips have a 32B request size.
4118 */
4119 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4120 }
4121
4122 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4123 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4124 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4125 /* If this DCC image is potentially going to be used in texture
4126 * fetches, we need some special settings.
4127 */
4128 independent_64b_blocks = 1;
4129 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4130 } else {
4131 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4132 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4133 * big as possible for better compression state.
4134 */
4135 independent_64b_blocks = 0;
4136 max_compressed_block_size = max_uncompressed_block_size;
4137 }
4138
4139 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4140 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4141 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4142 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4143 }
4144
4145 static void
4146 radv_initialise_color_surface(struct radv_device *device,
4147 struct radv_color_buffer_info *cb,
4148 struct radv_image_view *iview)
4149 {
4150 const struct vk_format_description *desc;
4151 unsigned ntype, format, swap, endian;
4152 unsigned blend_clamp = 0, blend_bypass = 0;
4153 uint64_t va;
4154 const struct radeon_surf *surf = &iview->image->surface;
4155
4156 desc = vk_format_description(iview->vk_format);
4157
4158 memset(cb, 0, sizeof(*cb));
4159
4160 /* Intensity is implemented as Red, so treat it that way. */
4161 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4162
4163 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4164
4165 cb->cb_color_base = va >> 8;
4166
4167 if (device->physical_device->rad_info.chip_class >= GFX9) {
4168 struct gfx9_surf_meta_flags meta;
4169 if (iview->image->dcc_offset)
4170 meta = iview->image->surface.u.gfx9.dcc;
4171 else
4172 meta = iview->image->surface.u.gfx9.cmask;
4173
4174 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4175 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4176 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4177 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4178
4179 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4180 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4181 } else {
4182 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4183 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4184
4185 cb->cb_color_base += level_info->offset >> 8;
4186 if (level_info->mode == RADEON_SURF_MODE_2D)
4187 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4188
4189 pitch_tile_max = level_info->nblk_x / 8 - 1;
4190 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4191 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4192
4193 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4194 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4195 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4196
4197 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4198
4199 if (radv_image_has_fmask(iview->image)) {
4200 if (device->physical_device->rad_info.chip_class >= CIK)
4201 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4202 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4203 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4204 } else {
4205 /* This must be set for fast clear to work without FMASK. */
4206 if (device->physical_device->rad_info.chip_class >= CIK)
4207 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4208 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4209 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4210 }
4211 }
4212
4213 /* CMASK variables */
4214 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4215 va += iview->image->cmask.offset;
4216 cb->cb_color_cmask = va >> 8;
4217
4218 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4219 va += iview->image->dcc_offset;
4220 cb->cb_dcc_base = va >> 8;
4221 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4222
4223 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4224 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4225 S_028C6C_SLICE_MAX(max_slice);
4226
4227 if (iview->image->info.samples > 1) {
4228 unsigned log_samples = util_logbase2(iview->image->info.samples);
4229
4230 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4231 S_028C74_NUM_FRAGMENTS(log_samples);
4232 }
4233
4234 if (radv_image_has_fmask(iview->image)) {
4235 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4236 cb->cb_color_fmask = va >> 8;
4237 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4238 } else {
4239 cb->cb_color_fmask = cb->cb_color_base;
4240 }
4241
4242 ntype = radv_translate_color_numformat(iview->vk_format,
4243 desc,
4244 vk_format_get_first_non_void_channel(iview->vk_format));
4245 format = radv_translate_colorformat(iview->vk_format);
4246 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4247 radv_finishme("Illegal color\n");
4248 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4249 endian = radv_colorformat_endian_swap(format);
4250
4251 /* blend clamp should be set for all NORM/SRGB types */
4252 if (ntype == V_028C70_NUMBER_UNORM ||
4253 ntype == V_028C70_NUMBER_SNORM ||
4254 ntype == V_028C70_NUMBER_SRGB)
4255 blend_clamp = 1;
4256
4257 /* set blend bypass according to docs if SINT/UINT or
4258 8/24 COLOR variants */
4259 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4260 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4261 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4262 blend_clamp = 0;
4263 blend_bypass = 1;
4264 }
4265 #if 0
4266 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4267 (format == V_028C70_COLOR_8 ||
4268 format == V_028C70_COLOR_8_8 ||
4269 format == V_028C70_COLOR_8_8_8_8))
4270 ->color_is_int8 = true;
4271 #endif
4272 cb->cb_color_info = S_028C70_FORMAT(format) |
4273 S_028C70_COMP_SWAP(swap) |
4274 S_028C70_BLEND_CLAMP(blend_clamp) |
4275 S_028C70_BLEND_BYPASS(blend_bypass) |
4276 S_028C70_SIMPLE_FLOAT(1) |
4277 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4278 ntype != V_028C70_NUMBER_SNORM &&
4279 ntype != V_028C70_NUMBER_SRGB &&
4280 format != V_028C70_COLOR_8_24 &&
4281 format != V_028C70_COLOR_24_8) |
4282 S_028C70_NUMBER_TYPE(ntype) |
4283 S_028C70_ENDIAN(endian);
4284 if (radv_image_has_fmask(iview->image)) {
4285 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4286 if (device->physical_device->rad_info.chip_class == SI) {
4287 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4288 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4289 }
4290 }
4291
4292 if (radv_image_has_cmask(iview->image) &&
4293 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4294 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4295
4296 if (radv_dcc_enabled(iview->image, iview->base_mip))
4297 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4298
4299 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4300
4301 /* This must be set for fast clear to work without FMASK. */
4302 if (!radv_image_has_fmask(iview->image) &&
4303 device->physical_device->rad_info.chip_class == SI) {
4304 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4305 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4306 }
4307
4308 if (device->physical_device->rad_info.chip_class >= GFX9) {
4309 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4310 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4311
4312 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4313 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4314 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4315 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4316 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4317 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4318 }
4319 }
4320
4321 static unsigned
4322 radv_calc_decompress_on_z_planes(struct radv_device *device,
4323 struct radv_image_view *iview)
4324 {
4325 unsigned max_zplanes = 0;
4326
4327 assert(radv_image_is_tc_compat_htile(iview->image));
4328
4329 if (device->physical_device->rad_info.chip_class >= GFX9) {
4330 /* Default value for 32-bit depth surfaces. */
4331 max_zplanes = 4;
4332
4333 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4334 iview->image->info.samples > 1)
4335 max_zplanes = 2;
4336
4337 max_zplanes = max_zplanes + 1;
4338 } else {
4339 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4340 /* Do not enable Z plane compression for 16-bit depth
4341 * surfaces because isn't supported on GFX8. Only
4342 * 32-bit depth surfaces are supported by the hardware.
4343 * This allows to maintain shader compatibility and to
4344 * reduce the number of depth decompressions.
4345 */
4346 max_zplanes = 1;
4347 } else {
4348 if (iview->image->info.samples <= 1)
4349 max_zplanes = 5;
4350 else if (iview->image->info.samples <= 4)
4351 max_zplanes = 3;
4352 else
4353 max_zplanes = 2;
4354 }
4355 }
4356
4357 return max_zplanes;
4358 }
4359
4360 static void
4361 radv_initialise_ds_surface(struct radv_device *device,
4362 struct radv_ds_buffer_info *ds,
4363 struct radv_image_view *iview)
4364 {
4365 unsigned level = iview->base_mip;
4366 unsigned format, stencil_format;
4367 uint64_t va, s_offs, z_offs;
4368 bool stencil_only = false;
4369 memset(ds, 0, sizeof(*ds));
4370 switch (iview->image->vk_format) {
4371 case VK_FORMAT_D24_UNORM_S8_UINT:
4372 case VK_FORMAT_X8_D24_UNORM_PACK32:
4373 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4374 ds->offset_scale = 2.0f;
4375 break;
4376 case VK_FORMAT_D16_UNORM:
4377 case VK_FORMAT_D16_UNORM_S8_UINT:
4378 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4379 ds->offset_scale = 4.0f;
4380 break;
4381 case VK_FORMAT_D32_SFLOAT:
4382 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4383 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4384 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4385 ds->offset_scale = 1.0f;
4386 break;
4387 case VK_FORMAT_S8_UINT:
4388 stencil_only = true;
4389 break;
4390 default:
4391 break;
4392 }
4393
4394 format = radv_translate_dbformat(iview->image->vk_format);
4395 stencil_format = iview->image->surface.has_stencil ?
4396 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4397
4398 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4399 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4400 S_028008_SLICE_MAX(max_slice);
4401
4402 ds->db_htile_data_base = 0;
4403 ds->db_htile_surface = 0;
4404
4405 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4406 s_offs = z_offs = va;
4407
4408 if (device->physical_device->rad_info.chip_class >= GFX9) {
4409 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4410 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4411
4412 ds->db_z_info = S_028038_FORMAT(format) |
4413 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4414 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4415 S_028038_MAXMIP(iview->image->info.levels - 1) |
4416 S_028038_ZRANGE_PRECISION(1);
4417 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4418 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4419
4420 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4421 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4422 ds->db_depth_view |= S_028008_MIPID(level);
4423
4424 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4425 S_02801C_Y_MAX(iview->image->info.height - 1);
4426
4427 if (radv_htile_enabled(iview->image, level)) {
4428 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4429
4430 if (radv_image_is_tc_compat_htile(iview->image)) {
4431 unsigned max_zplanes =
4432 radv_calc_decompress_on_z_planes(device, iview);
4433
4434 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4435 S_028038_ITERATE_FLUSH(1);
4436 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4437 }
4438
4439 if (!iview->image->surface.has_stencil)
4440 /* Use all of the htile_buffer for depth if there's no stencil. */
4441 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4442 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4443 iview->image->htile_offset;
4444 ds->db_htile_data_base = va >> 8;
4445 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4446 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4447 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4448 }
4449 } else {
4450 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4451
4452 if (stencil_only)
4453 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4454
4455 z_offs += iview->image->surface.u.legacy.level[level].offset;
4456 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4457
4458 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4459 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4460 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4461
4462 if (iview->image->info.samples > 1)
4463 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4464
4465 if (device->physical_device->rad_info.chip_class >= CIK) {
4466 struct radeon_info *info = &device->physical_device->rad_info;
4467 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4468 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4469 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4470 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4471 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4472 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4473
4474 if (stencil_only)
4475 tile_mode = stencil_tile_mode;
4476
4477 ds->db_depth_info |=
4478 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4479 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4480 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4481 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4482 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4483 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4484 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4485 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4486 } else {
4487 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4488 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4489 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4490 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4491 if (stencil_only)
4492 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4493 }
4494
4495 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4496 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4497 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4498
4499 if (radv_htile_enabled(iview->image, level)) {
4500 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4501
4502 if (!iview->image->surface.has_stencil &&
4503 !radv_image_is_tc_compat_htile(iview->image))
4504 /* Use all of the htile_buffer for depth if there's no stencil. */
4505 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4506
4507 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4508 iview->image->htile_offset;
4509 ds->db_htile_data_base = va >> 8;
4510 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4511
4512 if (radv_image_is_tc_compat_htile(iview->image)) {
4513 unsigned max_zplanes =
4514 radv_calc_decompress_on_z_planes(device, iview);
4515
4516 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4517 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4518 }
4519 }
4520 }
4521
4522 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4523 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4524 }
4525
4526 VkResult radv_CreateFramebuffer(
4527 VkDevice _device,
4528 const VkFramebufferCreateInfo* pCreateInfo,
4529 const VkAllocationCallbacks* pAllocator,
4530 VkFramebuffer* pFramebuffer)
4531 {
4532 RADV_FROM_HANDLE(radv_device, device, _device);
4533 struct radv_framebuffer *framebuffer;
4534
4535 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4536
4537 size_t size = sizeof(*framebuffer) +
4538 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4539 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4540 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4541 if (framebuffer == NULL)
4542 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4543
4544 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4545 framebuffer->width = pCreateInfo->width;
4546 framebuffer->height = pCreateInfo->height;
4547 framebuffer->layers = pCreateInfo->layers;
4548 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4549 VkImageView _iview = pCreateInfo->pAttachments[i];
4550 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4551 framebuffer->attachments[i].attachment = iview;
4552 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4553 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4554 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4555 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4556 }
4557 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4558 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4559 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4560 }
4561
4562 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4563 return VK_SUCCESS;
4564 }
4565
4566 void radv_DestroyFramebuffer(
4567 VkDevice _device,
4568 VkFramebuffer _fb,
4569 const VkAllocationCallbacks* pAllocator)
4570 {
4571 RADV_FROM_HANDLE(radv_device, device, _device);
4572 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4573
4574 if (!fb)
4575 return;
4576 vk_free2(&device->alloc, pAllocator, fb);
4577 }
4578
4579 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4580 {
4581 switch (address_mode) {
4582 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4583 return V_008F30_SQ_TEX_WRAP;
4584 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4585 return V_008F30_SQ_TEX_MIRROR;
4586 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4587 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4588 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4589 return V_008F30_SQ_TEX_CLAMP_BORDER;
4590 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4591 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4592 default:
4593 unreachable("illegal tex wrap mode");
4594 break;
4595 }
4596 }
4597
4598 static unsigned
4599 radv_tex_compare(VkCompareOp op)
4600 {
4601 switch (op) {
4602 case VK_COMPARE_OP_NEVER:
4603 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4604 case VK_COMPARE_OP_LESS:
4605 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4606 case VK_COMPARE_OP_EQUAL:
4607 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4608 case VK_COMPARE_OP_LESS_OR_EQUAL:
4609 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4610 case VK_COMPARE_OP_GREATER:
4611 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4612 case VK_COMPARE_OP_NOT_EQUAL:
4613 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4614 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4615 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4616 case VK_COMPARE_OP_ALWAYS:
4617 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4618 default:
4619 unreachable("illegal compare mode");
4620 break;
4621 }
4622 }
4623
4624 static unsigned
4625 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4626 {
4627 switch (filter) {
4628 case VK_FILTER_NEAREST:
4629 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4630 V_008F38_SQ_TEX_XY_FILTER_POINT);
4631 case VK_FILTER_LINEAR:
4632 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4633 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4634 case VK_FILTER_CUBIC_IMG:
4635 default:
4636 fprintf(stderr, "illegal texture filter");
4637 return 0;
4638 }
4639 }
4640
4641 static unsigned
4642 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4643 {
4644 switch (mode) {
4645 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4646 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4647 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4648 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4649 default:
4650 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4651 }
4652 }
4653
4654 static unsigned
4655 radv_tex_bordercolor(VkBorderColor bcolor)
4656 {
4657 switch (bcolor) {
4658 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4659 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4660 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4661 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4662 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4663 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4664 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4665 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4666 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4667 default:
4668 break;
4669 }
4670 return 0;
4671 }
4672
4673 static unsigned
4674 radv_tex_aniso_filter(unsigned filter)
4675 {
4676 if (filter < 2)
4677 return 0;
4678 if (filter < 4)
4679 return 1;
4680 if (filter < 8)
4681 return 2;
4682 if (filter < 16)
4683 return 3;
4684 return 4;
4685 }
4686
4687 static unsigned
4688 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4689 {
4690 switch (mode) {
4691 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4692 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4693 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4694 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4695 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4696 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4697 default:
4698 break;
4699 }
4700 return 0;
4701 }
4702
4703 static uint32_t
4704 radv_get_max_anisotropy(struct radv_device *device,
4705 const VkSamplerCreateInfo *pCreateInfo)
4706 {
4707 if (device->force_aniso >= 0)
4708 return device->force_aniso;
4709
4710 if (pCreateInfo->anisotropyEnable &&
4711 pCreateInfo->maxAnisotropy > 1.0f)
4712 return (uint32_t)pCreateInfo->maxAnisotropy;
4713
4714 return 0;
4715 }
4716
4717 static void
4718 radv_init_sampler(struct radv_device *device,
4719 struct radv_sampler *sampler,
4720 const VkSamplerCreateInfo *pCreateInfo)
4721 {
4722 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4723 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4724 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4725 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4726
4727 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4728 vk_find_struct_const(pCreateInfo->pNext,
4729 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4730 if (sampler_reduction)
4731 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4732
4733 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4734 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4735 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4736 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4737 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4738 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4739 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4740 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4741 S_008F30_DISABLE_CUBE_WRAP(0) |
4742 S_008F30_COMPAT_MODE(is_vi) |
4743 S_008F30_FILTER_MODE(filter_mode));
4744 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4745 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4746 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4747 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4748 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4749 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4750 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4751 S_008F38_MIP_POINT_PRECLAMP(0) |
4752 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4753 S_008F38_FILTER_PREC_FIX(1) |
4754 S_008F38_ANISO_OVERRIDE(is_vi));
4755 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4756 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4757 }
4758
4759 VkResult radv_CreateSampler(
4760 VkDevice _device,
4761 const VkSamplerCreateInfo* pCreateInfo,
4762 const VkAllocationCallbacks* pAllocator,
4763 VkSampler* pSampler)
4764 {
4765 RADV_FROM_HANDLE(radv_device, device, _device);
4766 struct radv_sampler *sampler;
4767
4768 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4769
4770 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4771 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4772 if (!sampler)
4773 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4774
4775 radv_init_sampler(device, sampler, pCreateInfo);
4776 *pSampler = radv_sampler_to_handle(sampler);
4777
4778 return VK_SUCCESS;
4779 }
4780
4781 void radv_DestroySampler(
4782 VkDevice _device,
4783 VkSampler _sampler,
4784 const VkAllocationCallbacks* pAllocator)
4785 {
4786 RADV_FROM_HANDLE(radv_device, device, _device);
4787 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4788
4789 if (!sampler)
4790 return;
4791 vk_free2(&device->alloc, pAllocator, sampler);
4792 }
4793
4794 /* vk_icd.h does not declare this function, so we declare it here to
4795 * suppress Wmissing-prototypes.
4796 */
4797 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4798 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4799
4800 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4801 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4802 {
4803 /* For the full details on loader interface versioning, see
4804 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4805 * What follows is a condensed summary, to help you navigate the large and
4806 * confusing official doc.
4807 *
4808 * - Loader interface v0 is incompatible with later versions. We don't
4809 * support it.
4810 *
4811 * - In loader interface v1:
4812 * - The first ICD entrypoint called by the loader is
4813 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4814 * entrypoint.
4815 * - The ICD must statically expose no other Vulkan symbol unless it is
4816 * linked with -Bsymbolic.
4817 * - Each dispatchable Vulkan handle created by the ICD must be
4818 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4819 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4820 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4821 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4822 * such loader-managed surfaces.
4823 *
4824 * - Loader interface v2 differs from v1 in:
4825 * - The first ICD entrypoint called by the loader is
4826 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4827 * statically expose this entrypoint.
4828 *
4829 * - Loader interface v3 differs from v2 in:
4830 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4831 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4832 * because the loader no longer does so.
4833 */
4834 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4835 return VK_SUCCESS;
4836 }
4837
4838 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4839 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4840 int *pFD)
4841 {
4842 RADV_FROM_HANDLE(radv_device, device, _device);
4843 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4844
4845 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4846
4847 /* At the moment, we support only the below handle types. */
4848 assert(pGetFdInfo->handleType ==
4849 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4850 pGetFdInfo->handleType ==
4851 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4852
4853 bool ret = radv_get_memory_fd(device, memory, pFD);
4854 if (ret == false)
4855 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4856 return VK_SUCCESS;
4857 }
4858
4859 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4860 VkExternalMemoryHandleTypeFlagBits handleType,
4861 int fd,
4862 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4863 {
4864 RADV_FROM_HANDLE(radv_device, device, _device);
4865
4866 switch (handleType) {
4867 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4868 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4869 return VK_SUCCESS;
4870
4871 default:
4872 /* The valid usage section for this function says:
4873 *
4874 * "handleType must not be one of the handle types defined as
4875 * opaque."
4876 *
4877 * So opaque handle types fall into the default "unsupported" case.
4878 */
4879 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4880 }
4881 }
4882
4883 static VkResult radv_import_opaque_fd(struct radv_device *device,
4884 int fd,
4885 uint32_t *syncobj)
4886 {
4887 uint32_t syncobj_handle = 0;
4888 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4889 if (ret != 0)
4890 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4891
4892 if (*syncobj)
4893 device->ws->destroy_syncobj(device->ws, *syncobj);
4894
4895 *syncobj = syncobj_handle;
4896 close(fd);
4897
4898 return VK_SUCCESS;
4899 }
4900
4901 static VkResult radv_import_sync_fd(struct radv_device *device,
4902 int fd,
4903 uint32_t *syncobj)
4904 {
4905 /* If we create a syncobj we do it locally so that if we have an error, we don't
4906 * leave a syncobj in an undetermined state in the fence. */
4907 uint32_t syncobj_handle = *syncobj;
4908 if (!syncobj_handle) {
4909 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4910 if (ret) {
4911 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4912 }
4913 }
4914
4915 if (fd == -1) {
4916 device->ws->signal_syncobj(device->ws, syncobj_handle);
4917 } else {
4918 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4919 if (ret != 0)
4920 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4921 }
4922
4923 *syncobj = syncobj_handle;
4924 if (fd != -1)
4925 close(fd);
4926
4927 return VK_SUCCESS;
4928 }
4929
4930 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4931 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4932 {
4933 RADV_FROM_HANDLE(radv_device, device, _device);
4934 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4935 uint32_t *syncobj_dst = NULL;
4936
4937 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4938 syncobj_dst = &sem->temp_syncobj;
4939 } else {
4940 syncobj_dst = &sem->syncobj;
4941 }
4942
4943 switch(pImportSemaphoreFdInfo->handleType) {
4944 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4945 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4946 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4947 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4948 default:
4949 unreachable("Unhandled semaphore handle type");
4950 }
4951 }
4952
4953 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4954 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4955 int *pFd)
4956 {
4957 RADV_FROM_HANDLE(radv_device, device, _device);
4958 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4959 int ret;
4960 uint32_t syncobj_handle;
4961
4962 if (sem->temp_syncobj)
4963 syncobj_handle = sem->temp_syncobj;
4964 else
4965 syncobj_handle = sem->syncobj;
4966
4967 switch(pGetFdInfo->handleType) {
4968 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4969 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4970 break;
4971 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4972 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4973 if (!ret) {
4974 if (sem->temp_syncobj) {
4975 close (sem->temp_syncobj);
4976 sem->temp_syncobj = 0;
4977 } else {
4978 device->ws->reset_syncobj(device->ws, syncobj_handle);
4979 }
4980 }
4981 break;
4982 default:
4983 unreachable("Unhandled semaphore handle type");
4984 }
4985
4986 if (ret)
4987 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4988 return VK_SUCCESS;
4989 }
4990
4991 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4992 VkPhysicalDevice physicalDevice,
4993 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4994 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4995 {
4996 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4997
4998 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4999 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5000 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5001 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5002 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5003 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5004 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5005 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5006 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5007 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5008 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5009 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5010 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5011 } else {
5012 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5013 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5014 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5015 }
5016 }
5017
5018 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5019 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5020 {
5021 RADV_FROM_HANDLE(radv_device, device, _device);
5022 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5023 uint32_t *syncobj_dst = NULL;
5024
5025
5026 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5027 syncobj_dst = &fence->temp_syncobj;
5028 } else {
5029 syncobj_dst = &fence->syncobj;
5030 }
5031
5032 switch(pImportFenceFdInfo->handleType) {
5033 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5034 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5035 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5036 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5037 default:
5038 unreachable("Unhandled fence handle type");
5039 }
5040 }
5041
5042 VkResult radv_GetFenceFdKHR(VkDevice _device,
5043 const VkFenceGetFdInfoKHR *pGetFdInfo,
5044 int *pFd)
5045 {
5046 RADV_FROM_HANDLE(radv_device, device, _device);
5047 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5048 int ret;
5049 uint32_t syncobj_handle;
5050
5051 if (fence->temp_syncobj)
5052 syncobj_handle = fence->temp_syncobj;
5053 else
5054 syncobj_handle = fence->syncobj;
5055
5056 switch(pGetFdInfo->handleType) {
5057 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5058 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5059 break;
5060 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5061 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5062 if (!ret) {
5063 if (fence->temp_syncobj) {
5064 close (fence->temp_syncobj);
5065 fence->temp_syncobj = 0;
5066 } else {
5067 device->ws->reset_syncobj(device->ws, syncobj_handle);
5068 }
5069 }
5070 break;
5071 default:
5072 unreachable("Unhandled fence handle type");
5073 }
5074
5075 if (ret)
5076 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5077 return VK_SUCCESS;
5078 }
5079
5080 void radv_GetPhysicalDeviceExternalFenceProperties(
5081 VkPhysicalDevice physicalDevice,
5082 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5083 VkExternalFenceProperties *pExternalFenceProperties)
5084 {
5085 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5086
5087 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5088 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5089 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5090 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5091 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5092 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5093 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5094 } else {
5095 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5096 pExternalFenceProperties->compatibleHandleTypes = 0;
5097 pExternalFenceProperties->externalFenceFeatures = 0;
5098 }
5099 }
5100
5101 VkResult
5102 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5103 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5104 const VkAllocationCallbacks* pAllocator,
5105 VkDebugReportCallbackEXT* pCallback)
5106 {
5107 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5108 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5109 pCreateInfo, pAllocator, &instance->alloc,
5110 pCallback);
5111 }
5112
5113 void
5114 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5115 VkDebugReportCallbackEXT _callback,
5116 const VkAllocationCallbacks* pAllocator)
5117 {
5118 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5119 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5120 _callback, pAllocator, &instance->alloc);
5121 }
5122
5123 void
5124 radv_DebugReportMessageEXT(VkInstance _instance,
5125 VkDebugReportFlagsEXT flags,
5126 VkDebugReportObjectTypeEXT objectType,
5127 uint64_t object,
5128 size_t location,
5129 int32_t messageCode,
5130 const char* pLayerPrefix,
5131 const char* pMessage)
5132 {
5133 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5134 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5135 object, location, messageCode, pLayerPrefix, pMessage);
5136 }
5137
5138 void
5139 radv_GetDeviceGroupPeerMemoryFeatures(
5140 VkDevice device,
5141 uint32_t heapIndex,
5142 uint32_t localDeviceIndex,
5143 uint32_t remoteDeviceIndex,
5144 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5145 {
5146 assert(localDeviceIndex == remoteDeviceIndex);
5147
5148 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5149 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5150 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5151 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5152 }
5153
5154 static const VkTimeDomainEXT radv_time_domains[] = {
5155 VK_TIME_DOMAIN_DEVICE_EXT,
5156 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5157 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5158 };
5159
5160 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5161 VkPhysicalDevice physicalDevice,
5162 uint32_t *pTimeDomainCount,
5163 VkTimeDomainEXT *pTimeDomains)
5164 {
5165 int d;
5166 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5167
5168 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5169 vk_outarray_append(&out, i) {
5170 *i = radv_time_domains[d];
5171 }
5172 }
5173
5174 return vk_outarray_status(&out);
5175 }
5176
5177 static uint64_t
5178 radv_clock_gettime(clockid_t clock_id)
5179 {
5180 struct timespec current;
5181 int ret;
5182
5183 ret = clock_gettime(clock_id, &current);
5184 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5185 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5186 if (ret < 0)
5187 return 0;
5188
5189 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5190 }
5191
5192 VkResult radv_GetCalibratedTimestampsEXT(
5193 VkDevice _device,
5194 uint32_t timestampCount,
5195 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5196 uint64_t *pTimestamps,
5197 uint64_t *pMaxDeviation)
5198 {
5199 RADV_FROM_HANDLE(radv_device, device, _device);
5200 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5201 int d;
5202 uint64_t begin, end;
5203 uint64_t max_clock_period = 0;
5204
5205 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5206
5207 for (d = 0; d < timestampCount; d++) {
5208 switch (pTimestampInfos[d].timeDomain) {
5209 case VK_TIME_DOMAIN_DEVICE_EXT:
5210 pTimestamps[d] = device->ws->query_value(device->ws,
5211 RADEON_TIMESTAMP);
5212 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5213 max_clock_period = MAX2(max_clock_period, device_period);
5214 break;
5215 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5216 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5217 max_clock_period = MAX2(max_clock_period, 1);
5218 break;
5219
5220 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5221 pTimestamps[d] = begin;
5222 break;
5223 default:
5224 pTimestamps[d] = 0;
5225 break;
5226 }
5227 }
5228
5229 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5230
5231 /*
5232 * The maximum deviation is the sum of the interval over which we
5233 * perform the sampling and the maximum period of any sampled
5234 * clock. That's because the maximum skew between any two sampled
5235 * clock edges is when the sampled clock with the largest period is
5236 * sampled at the end of that period but right at the beginning of the
5237 * sampling interval and some other clock is sampled right at the
5238 * begining of its sampling period and right at the end of the
5239 * sampling interval. Let's assume the GPU has the longest clock
5240 * period and that the application is sampling GPU and monotonic:
5241 *
5242 * s e
5243 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5244 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5245 *
5246 * g
5247 * 0 1 2 3
5248 * GPU -----_____-----_____-----_____-----_____
5249 *
5250 * m
5251 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5252 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5253 *
5254 * Interval <----------------->
5255 * Deviation <-------------------------->
5256 *
5257 * s = read(raw) 2
5258 * g = read(GPU) 1
5259 * m = read(monotonic) 2
5260 * e = read(raw) b
5261 *
5262 * We round the sample interval up by one tick to cover sampling error
5263 * in the interval clock
5264 */
5265
5266 uint64_t sample_interval = end - begin + 1;
5267
5268 *pMaxDeviation = sample_interval + max_clock_period;
5269
5270 return VK_SUCCESS;
5271 }