2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
54 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
57 unsigned char sha1
[20];
58 unsigned ptr_size
= sizeof(void*);
60 memset(uuid
, 0, VK_UUID_SIZE
);
61 _mesa_sha1_init(&ctx
);
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
67 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
68 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
69 _mesa_sha1_final(&ctx
, sha1
);
71 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
76 radv_get_driver_uuid(void *uuid
)
78 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
82 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
84 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
88 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
90 const char *chip_string
;
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
103 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
110 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20
: chip_string
= "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10
: chip_string
= "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12
: chip_string
= "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14
: chip_string
= "AMD RADV NAVI14"; break;
119 default: chip_string
= "AMD RADV unknown"; break;
122 snprintf(name
, name_len
, "%s (LLVM " MESA_LLVM_VERSION_STRING
")", chip_string
);
126 radv_get_visible_vram_size(struct radv_physical_device
*device
)
128 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
132 radv_get_vram_size(struct radv_physical_device
*device
)
134 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
138 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
141 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
142 uint64_t vram_size
= radv_get_vram_size(device
);
143 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
144 device
->memory_properties
.memoryHeapCount
= 0;
146 vram_index
= device
->memory_properties
.memoryHeapCount
++;
147 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
149 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
152 if (visible_vram_size
) {
153 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
154 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
155 .size
= visible_vram_size
,
156 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
159 if (device
->rad_info
.gart_size
> 0) {
160 gart_index
= device
->memory_properties
.memoryHeapCount
++;
161 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
162 .size
= device
->rad_info
.gart_size
,
163 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
168 unsigned type_count
= 0;
169 if (vram_index
>= 0) {
170 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
171 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
172 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
173 .heapIndex
= vram_index
,
176 if (gart_index
>= 0) {
177 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
178 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
179 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
181 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
182 .heapIndex
= gart_index
,
185 if (visible_vram_index
>= 0) {
186 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
187 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
188 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
191 .heapIndex
= visible_vram_index
,
194 if (gart_index
>= 0) {
195 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
196 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
197 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
200 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
201 .heapIndex
= gart_index
,
204 device
->memory_properties
.memoryTypeCount
= type_count
;
208 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
210 const char *family
= getenv("RADV_FORCE_FAMILY");
216 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
217 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
218 /* Override family and chip_class. */
219 device
->rad_info
.family
= i
;
221 if (i
>= CHIP_NAVI10
)
222 device
->rad_info
.chip_class
= GFX10
;
223 else if (i
>= CHIP_VEGA10
)
224 device
->rad_info
.chip_class
= GFX9
;
225 else if (i
>= CHIP_TONGA
)
226 device
->rad_info
.chip_class
= GFX8
;
227 else if (i
>= CHIP_BONAIRE
)
228 device
->rad_info
.chip_class
= GFX7
;
230 device
->rad_info
.chip_class
= GFX6
;
236 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
241 radv_physical_device_init(struct radv_physical_device
*device
,
242 struct radv_instance
*instance
,
243 drmDevicePtr drm_device
)
245 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
247 drmVersionPtr version
;
251 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
253 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
254 radv_logi("Could not open device '%s'", path
);
256 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
259 version
= drmGetVersion(fd
);
263 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
264 radv_logi("Could not get the kernel driver version for device '%s'", path
);
266 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
267 "failed to get version %s: %m", path
);
270 if (strcmp(version
->name
, "amdgpu")) {
271 drmFreeVersion(version
);
274 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
277 return VK_ERROR_INCOMPATIBLE_DRIVER
;
279 drmFreeVersion(version
);
281 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
282 radv_logi("Found compatible device '%s'.", path
);
284 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
285 device
->instance
= instance
;
287 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
288 instance
->perftest_flags
);
290 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
294 if (instance
->enabled_extensions
.KHR_display
) {
295 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
296 if (master_fd
>= 0) {
297 uint32_t accel_working
= 0;
298 struct drm_amdgpu_info request
= {
299 .return_pointer
= (uintptr_t)&accel_working
,
300 .return_size
= sizeof(accel_working
),
301 .query
= AMDGPU_INFO_ACCEL_WORKING
304 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
311 device
->master_fd
= master_fd
;
312 device
->local_fd
= fd
;
313 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
315 radv_handle_env_var_force_family(device
);
317 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
319 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
320 device
->ws
->destroy(device
->ws
);
321 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
322 "cannot generate UUID");
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags
=
328 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
329 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
334 char buf
[VK_UUID_SIZE
* 2 + 1];
335 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
336 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
338 if (device
->rad_info
.chip_class
< GFX8
||
339 device
->rad_info
.chip_class
> GFX9
)
340 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
342 radv_get_driver_uuid(&device
->driver_uuid
);
343 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
345 if (device
->rad_info
.family
== CHIP_STONEY
||
346 device
->rad_info
.chip_class
>= GFX9
) {
347 device
->has_rbplus
= true;
348 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
349 device
->rad_info
.family
== CHIP_VEGA12
||
350 device
->rad_info
.family
== CHIP_RAVEN
||
351 device
->rad_info
.family
== CHIP_RAVEN2
;
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
357 device
->has_clear_state
= device
->rad_info
.chip_class
>= GFX7
;
359 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= GFX8
;
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
363 device
->rad_info
.family
== CHIP_RAVEN
;
365 /* Out-of-order primitive rasterization. */
366 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= GFX8
&&
367 device
->rad_info
.max_se
>= 2;
368 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
369 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
371 device
->dcc_msaa_allowed
=
372 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
374 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
375 device
->has_load_ctx_reg_pkt
= device
->rad_info
.chip_class
>= GFX9
||
376 (device
->rad_info
.chip_class
>= GFX8
&&
377 device
->rad_info
.me_fw_feature
>= 41);
379 device
->has_dcc_constant_encode
= device
->rad_info
.family
== CHIP_RAVEN2
;
381 device
->use_shader_ballot
= device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
;
383 radv_physical_device_init_mem_types(device
);
384 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
386 device
->bus_info
= *drm_device
->businfo
.pci
;
388 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
389 ac_print_gpu_info(&device
->rad_info
);
391 /* The WSI is structured as a layer on top of the driver, so this has
392 * to be the last part of initialization (at least until we get other
395 result
= radv_init_wsi(device
);
396 if (result
!= VK_SUCCESS
) {
397 device
->ws
->destroy(device
->ws
);
398 vk_error(instance
, result
);
412 radv_physical_device_finish(struct radv_physical_device
*device
)
414 radv_finish_wsi(device
);
415 device
->ws
->destroy(device
->ws
);
416 disk_cache_destroy(device
->disk_cache
);
417 close(device
->local_fd
);
418 if (device
->master_fd
!= -1)
419 close(device
->master_fd
);
423 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
424 VkSystemAllocationScope allocationScope
)
430 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
431 size_t align
, VkSystemAllocationScope allocationScope
)
433 return realloc(pOriginal
, size
);
437 default_free_func(void *pUserData
, void *pMemory
)
442 static const VkAllocationCallbacks default_alloc
= {
444 .pfnAllocation
= default_alloc_func
,
445 .pfnReallocation
= default_realloc_func
,
446 .pfnFree
= default_free_func
,
449 static const struct debug_control radv_debug_options
[] = {
450 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
451 {"nodcc", RADV_DEBUG_NO_DCC
},
452 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
453 {"nocache", RADV_DEBUG_NO_CACHE
},
454 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
455 {"nohiz", RADV_DEBUG_NO_HIZ
},
456 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
457 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
458 {"allbos", RADV_DEBUG_ALL_BOS
},
459 {"noibs", RADV_DEBUG_NO_IBS
},
460 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
461 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
462 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
463 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
464 {"nosisched", RADV_DEBUG_NO_SISCHED
},
465 {"preoptir", RADV_DEBUG_PREOPTIR
},
466 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
467 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
468 {"info", RADV_DEBUG_INFO
},
469 {"errors", RADV_DEBUG_ERRORS
},
470 {"startup", RADV_DEBUG_STARTUP
},
471 {"checkir", RADV_DEBUG_CHECKIR
},
472 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
473 {"nobinning", RADV_DEBUG_NOBINNING
},
474 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
479 radv_get_debug_option_name(int id
)
481 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
482 return radv_debug_options
[id
].string
;
485 static const struct debug_control radv_perftest_options
[] = {
486 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
487 {"sisched", RADV_PERFTEST_SISCHED
},
488 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
489 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
490 {"bolist", RADV_PERFTEST_BO_LIST
},
491 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
492 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
497 radv_get_perftest_option_name(int id
)
499 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
500 return radv_perftest_options
[id
].string
;
504 radv_handle_per_app_options(struct radv_instance
*instance
,
505 const VkApplicationInfo
*info
)
507 const char *name
= info
? info
->pApplicationName
: NULL
;
512 if (!strcmp(name
, "Talos - Linux - 32bit") ||
513 !strcmp(name
, "Talos - Linux - 64bit")) {
514 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
515 /* Force enable LLVM sisched for Talos because it looks
516 * safe and it gives few more FPS.
518 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
520 } else if (!strcmp(name
, "DOOM_VFR")) {
521 /* Work around a Doom VFR game bug */
522 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
523 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
524 /* Workaround for a WaW hazard when LLVM moves/merges
525 * load/store memory operations.
526 * See https://reviews.llvm.org/D61313
528 if (HAVE_LLVM
< 0x900)
529 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
533 static int radv_get_instance_extension_index(const char *name
)
535 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
536 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
542 static const char radv_dri_options_xml
[] =
544 DRI_CONF_SECTION_QUALITY
545 DRI_CONF_ADAPTIVE_SYNC("true")
549 static void radv_init_dri_options(struct radv_instance
*instance
)
551 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
552 driParseConfigFiles(&instance
->dri_options
,
553 &instance
->available_dri_options
,
557 VkResult
radv_CreateInstance(
558 const VkInstanceCreateInfo
* pCreateInfo
,
559 const VkAllocationCallbacks
* pAllocator
,
560 VkInstance
* pInstance
)
562 struct radv_instance
*instance
;
565 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
567 uint32_t client_version
;
568 if (pCreateInfo
->pApplicationInfo
&&
569 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
570 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
572 client_version
= VK_API_VERSION_1_0
;
575 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
576 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
578 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
580 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
583 instance
->alloc
= *pAllocator
;
585 instance
->alloc
= default_alloc
;
587 instance
->apiVersion
= client_version
;
588 instance
->physicalDeviceCount
= -1;
590 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
593 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
594 radv_perftest_options
);
597 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
598 radv_logi("Created an instance");
600 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
601 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
602 int index
= radv_get_instance_extension_index(ext_name
);
604 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
605 vk_free2(&default_alloc
, pAllocator
, instance
);
606 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
609 instance
->enabled_extensions
.extensions
[index
] = true;
612 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
613 if (result
!= VK_SUCCESS
) {
614 vk_free2(&default_alloc
, pAllocator
, instance
);
615 return vk_error(instance
, result
);
619 glsl_type_singleton_init_or_ref();
621 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
623 radv_init_dri_options(instance
);
624 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
626 *pInstance
= radv_instance_to_handle(instance
);
631 void radv_DestroyInstance(
632 VkInstance _instance
,
633 const VkAllocationCallbacks
* pAllocator
)
635 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
640 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
641 radv_physical_device_finish(instance
->physicalDevices
+ i
);
644 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
646 glsl_type_singleton_decref();
649 driDestroyOptionCache(&instance
->dri_options
);
650 driDestroyOptionInfo(&instance
->available_dri_options
);
652 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
654 vk_free(&instance
->alloc
, instance
);
658 radv_enumerate_devices(struct radv_instance
*instance
)
660 /* TODO: Check for more devices ? */
661 drmDevicePtr devices
[8];
662 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
665 instance
->physicalDeviceCount
= 0;
667 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
669 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
670 radv_logi("Found %d drm nodes", max_devices
);
673 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
675 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
676 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
677 devices
[i
]->bustype
== DRM_BUS_PCI
&&
678 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
680 result
= radv_physical_device_init(instance
->physicalDevices
+
681 instance
->physicalDeviceCount
,
684 if (result
== VK_SUCCESS
)
685 ++instance
->physicalDeviceCount
;
686 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
690 drmFreeDevices(devices
, max_devices
);
695 VkResult
radv_EnumeratePhysicalDevices(
696 VkInstance _instance
,
697 uint32_t* pPhysicalDeviceCount
,
698 VkPhysicalDevice
* pPhysicalDevices
)
700 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
703 if (instance
->physicalDeviceCount
< 0) {
704 result
= radv_enumerate_devices(instance
);
705 if (result
!= VK_SUCCESS
&&
706 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
710 if (!pPhysicalDevices
) {
711 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
713 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
714 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
715 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
718 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
722 VkResult
radv_EnumeratePhysicalDeviceGroups(
723 VkInstance _instance
,
724 uint32_t* pPhysicalDeviceGroupCount
,
725 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
727 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
730 if (instance
->physicalDeviceCount
< 0) {
731 result
= radv_enumerate_devices(instance
);
732 if (result
!= VK_SUCCESS
&&
733 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
737 if (!pPhysicalDeviceGroupProperties
) {
738 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
740 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
741 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
742 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
743 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
744 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
747 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
751 void radv_GetPhysicalDeviceFeatures(
752 VkPhysicalDevice physicalDevice
,
753 VkPhysicalDeviceFeatures
* pFeatures
)
755 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
756 memset(pFeatures
, 0, sizeof(*pFeatures
));
758 *pFeatures
= (VkPhysicalDeviceFeatures
) {
759 .robustBufferAccess
= true,
760 .fullDrawIndexUint32
= true,
761 .imageCubeArray
= true,
762 .independentBlend
= true,
763 .geometryShader
= true,
764 .tessellationShader
= true,
765 .sampleRateShading
= true,
766 .dualSrcBlend
= true,
768 .multiDrawIndirect
= true,
769 .drawIndirectFirstInstance
= true,
771 .depthBiasClamp
= true,
772 .fillModeNonSolid
= true,
777 .multiViewport
= true,
778 .samplerAnisotropy
= true,
779 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
780 .textureCompressionASTC_LDR
= false,
781 .textureCompressionBC
= true,
782 .occlusionQueryPrecise
= true,
783 .pipelineStatisticsQuery
= true,
784 .vertexPipelineStoresAndAtomics
= true,
785 .fragmentStoresAndAtomics
= true,
786 .shaderTessellationAndGeometryPointSize
= true,
787 .shaderImageGatherExtended
= true,
788 .shaderStorageImageExtendedFormats
= true,
789 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
790 .shaderUniformBufferArrayDynamicIndexing
= true,
791 .shaderSampledImageArrayDynamicIndexing
= true,
792 .shaderStorageBufferArrayDynamicIndexing
= true,
793 .shaderStorageImageArrayDynamicIndexing
= true,
794 .shaderStorageImageReadWithoutFormat
= true,
795 .shaderStorageImageWriteWithoutFormat
= true,
796 .shaderClipDistance
= true,
797 .shaderCullDistance
= true,
798 .shaderFloat64
= true,
800 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
,
801 .sparseBinding
= true,
802 .variableMultisampleRate
= true,
803 .inheritedQueries
= true,
807 void radv_GetPhysicalDeviceFeatures2(
808 VkPhysicalDevice physicalDevice
,
809 VkPhysicalDeviceFeatures2
*pFeatures
)
811 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
812 vk_foreach_struct(ext
, pFeatures
->pNext
) {
813 switch (ext
->sType
) {
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
815 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
816 features
->variablePointersStorageBuffer
= true;
817 features
->variablePointers
= true;
820 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
821 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
822 features
->multiview
= true;
823 features
->multiviewGeometryShader
= true;
824 features
->multiviewTessellationShader
= true;
827 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
828 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
829 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
830 features
->shaderDrawParameters
= true;
833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
834 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
835 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
836 features
->protectedMemory
= false;
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
840 VkPhysicalDevice16BitStorageFeatures
*features
=
841 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
842 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
843 features
->storageBuffer16BitAccess
= enabled
;
844 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
845 features
->storagePushConstant16
= enabled
;
846 features
->storageInputOutput16
= enabled
&& HAVE_LLVM
>= 0x900;
849 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
850 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
851 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
852 features
->samplerYcbcrConversion
= true;
855 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
856 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
857 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
858 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
859 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
860 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
861 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
862 features
->shaderSampledImageArrayNonUniformIndexing
= true;
863 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
864 features
->shaderStorageImageArrayNonUniformIndexing
= true;
865 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
866 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
867 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
868 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
869 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
870 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
871 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
872 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
873 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
874 features
->descriptorBindingUpdateUnusedWhilePending
= true;
875 features
->descriptorBindingPartiallyBound
= true;
876 features
->descriptorBindingVariableDescriptorCount
= true;
877 features
->runtimeDescriptorArray
= true;
880 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
881 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
882 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
883 features
->conditionalRendering
= true;
884 features
->inheritedConditionalRendering
= false;
887 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
888 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
889 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
890 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
891 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
895 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
896 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
897 features
->transformFeedback
= true;
898 features
->geometryStreams
= true;
901 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
902 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
903 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
904 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
907 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
908 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
909 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
910 features
->memoryPriority
= VK_TRUE
;
913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
914 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
915 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
916 features
->bufferDeviceAddress
= true;
917 features
->bufferDeviceAddressCaptureReplay
= false;
918 features
->bufferDeviceAddressMultiDevice
= false;
921 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
922 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
923 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
924 features
->depthClipEnable
= true;
927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
928 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
929 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
930 features
->hostQueryReset
= true;
933 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
934 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
935 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
936 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
;
937 features
->storageBuffer8BitAccess
= enabled
;
938 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
939 features
->storagePushConstant8
= enabled
;
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR
: {
943 VkPhysicalDeviceFloat16Int8FeaturesKHR
*features
=
944 (VkPhysicalDeviceFloat16Int8FeaturesKHR
*)ext
;
945 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& HAVE_LLVM
>= 0x0800;
946 features
->shaderInt8
= true;
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
950 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
951 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
952 /* TODO: Enable this once the driver supports 64-bit
953 * compare&swap atomic operations.
955 features
->shaderBufferInt64Atomics
= false;
956 features
->shaderSharedInt64Atomics
= false;
959 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
960 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
961 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
963 features
->inlineUniformBlock
= true;
964 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
968 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
969 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
970 features
->computeDerivativeGroupQuads
= false;
971 features
->computeDerivativeGroupLinear
= true;
974 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
975 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
976 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
977 features
->ycbcrImageArrays
= true;
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
981 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
982 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
983 features
->uniformBufferStandardLayout
= true;
990 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
993 void radv_GetPhysicalDeviceProperties(
994 VkPhysicalDevice physicalDevice
,
995 VkPhysicalDeviceProperties
* pProperties
)
997 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
998 VkSampleCountFlags sample_counts
= 0xf;
1000 /* make sure that the entire descriptor set is addressable with a signed
1001 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1002 * be at most 2 GiB. the combined image & samples object count as one of
1003 * both. This limit is for the pipeline layout, not for the set layout, but
1004 * there is no set limit, so we just set a pipeline limit. I don't think
1005 * any app is going to hit this soon. */
1006 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1007 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1008 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1009 32 /* sampler, largest when combined with image */ +
1010 64 /* sampled image */ +
1011 64 /* storage image */);
1013 VkPhysicalDeviceLimits limits
= {
1014 .maxImageDimension1D
= (1 << 14),
1015 .maxImageDimension2D
= (1 << 14),
1016 .maxImageDimension3D
= (1 << 11),
1017 .maxImageDimensionCube
= (1 << 14),
1018 .maxImageArrayLayers
= (1 << 11),
1019 .maxTexelBufferElements
= 128 * 1024 * 1024,
1020 .maxUniformBufferRange
= UINT32_MAX
,
1021 .maxStorageBufferRange
= UINT32_MAX
,
1022 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1023 .maxMemoryAllocationCount
= UINT32_MAX
,
1024 .maxSamplerAllocationCount
= 64 * 1024,
1025 .bufferImageGranularity
= 64, /* A cache line */
1026 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1027 .maxBoundDescriptorSets
= MAX_SETS
,
1028 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1029 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1030 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1031 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1032 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1033 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1034 .maxPerStageResources
= max_descriptor_set_size
,
1035 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1036 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1037 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1038 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1039 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1040 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1041 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1042 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1043 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1044 .maxVertexInputBindings
= MAX_VBS
,
1045 .maxVertexInputAttributeOffset
= 2047,
1046 .maxVertexInputBindingStride
= 2048,
1047 .maxVertexOutputComponents
= 128,
1048 .maxTessellationGenerationLevel
= 64,
1049 .maxTessellationPatchSize
= 32,
1050 .maxTessellationControlPerVertexInputComponents
= 128,
1051 .maxTessellationControlPerVertexOutputComponents
= 128,
1052 .maxTessellationControlPerPatchOutputComponents
= 120,
1053 .maxTessellationControlTotalOutputComponents
= 4096,
1054 .maxTessellationEvaluationInputComponents
= 128,
1055 .maxTessellationEvaluationOutputComponents
= 128,
1056 .maxGeometryShaderInvocations
= 127,
1057 .maxGeometryInputComponents
= 64,
1058 .maxGeometryOutputComponents
= 128,
1059 .maxGeometryOutputVertices
= 256,
1060 .maxGeometryTotalOutputComponents
= 1024,
1061 .maxFragmentInputComponents
= 128,
1062 .maxFragmentOutputAttachments
= 8,
1063 .maxFragmentDualSrcAttachments
= 1,
1064 .maxFragmentCombinedOutputResources
= 8,
1065 .maxComputeSharedMemorySize
= 32768,
1066 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1067 .maxComputeWorkGroupInvocations
= 2048,
1068 .maxComputeWorkGroupSize
= {
1073 .subPixelPrecisionBits
= 8,
1074 .subTexelPrecisionBits
= 8,
1075 .mipmapPrecisionBits
= 8,
1076 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1077 .maxDrawIndirectCount
= UINT32_MAX
,
1078 .maxSamplerLodBias
= 16,
1079 .maxSamplerAnisotropy
= 16,
1080 .maxViewports
= MAX_VIEWPORTS
,
1081 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1082 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1083 .viewportSubPixelBits
= 8,
1084 .minMemoryMapAlignment
= 4096, /* A page */
1085 .minTexelBufferOffsetAlignment
= 1,
1086 .minUniformBufferOffsetAlignment
= 4,
1087 .minStorageBufferOffsetAlignment
= 4,
1088 .minTexelOffset
= -32,
1089 .maxTexelOffset
= 31,
1090 .minTexelGatherOffset
= -32,
1091 .maxTexelGatherOffset
= 31,
1092 .minInterpolationOffset
= -2,
1093 .maxInterpolationOffset
= 2,
1094 .subPixelInterpolationOffsetBits
= 8,
1095 .maxFramebufferWidth
= (1 << 14),
1096 .maxFramebufferHeight
= (1 << 14),
1097 .maxFramebufferLayers
= (1 << 10),
1098 .framebufferColorSampleCounts
= sample_counts
,
1099 .framebufferDepthSampleCounts
= sample_counts
,
1100 .framebufferStencilSampleCounts
= sample_counts
,
1101 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1102 .maxColorAttachments
= MAX_RTS
,
1103 .sampledImageColorSampleCounts
= sample_counts
,
1104 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1105 .sampledImageDepthSampleCounts
= sample_counts
,
1106 .sampledImageStencilSampleCounts
= sample_counts
,
1107 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1108 .maxSampleMaskWords
= 1,
1109 .timestampComputeAndGraphics
= true,
1110 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1111 .maxClipDistances
= 8,
1112 .maxCullDistances
= 8,
1113 .maxCombinedClipAndCullDistances
= 8,
1114 .discreteQueuePriorities
= 2,
1115 .pointSizeRange
= { 0.0, 8192.0 },
1116 .lineWidthRange
= { 0.0, 7.9921875 },
1117 .pointSizeGranularity
= (1.0 / 8.0),
1118 .lineWidthGranularity
= (1.0 / 128.0),
1119 .strictLines
= false, /* FINISHME */
1120 .standardSampleLocations
= true,
1121 .optimalBufferCopyOffsetAlignment
= 128,
1122 .optimalBufferCopyRowPitchAlignment
= 128,
1123 .nonCoherentAtomSize
= 64,
1126 *pProperties
= (VkPhysicalDeviceProperties
) {
1127 .apiVersion
= radv_physical_device_api_version(pdevice
),
1128 .driverVersion
= vk_get_driver_version(),
1129 .vendorID
= ATI_VENDOR_ID
,
1130 .deviceID
= pdevice
->rad_info
.pci_id
,
1131 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1133 .sparseProperties
= {0},
1136 strcpy(pProperties
->deviceName
, pdevice
->name
);
1137 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1140 void radv_GetPhysicalDeviceProperties2(
1141 VkPhysicalDevice physicalDevice
,
1142 VkPhysicalDeviceProperties2
*pProperties
)
1144 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1145 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1147 vk_foreach_struct(ext
, pProperties
->pNext
) {
1148 switch (ext
->sType
) {
1149 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1150 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1151 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1152 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1155 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1156 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1157 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1158 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1159 properties
->deviceLUIDValid
= false;
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1163 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1164 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1165 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1168 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1169 VkPhysicalDevicePointClippingProperties
*properties
=
1170 (VkPhysicalDevicePointClippingProperties
*)ext
;
1171 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1175 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1176 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1177 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1180 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1181 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1182 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1183 properties
->minImportedHostPointerAlignment
= 4096;
1186 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1187 VkPhysicalDeviceSubgroupProperties
*properties
=
1188 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1189 properties
->subgroupSize
= 64;
1190 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1191 properties
->supportedOperations
=
1192 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1193 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1194 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1195 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1196 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1197 properties
->supportedOperations
|=
1198 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1199 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1200 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1202 properties
->quadOperationsInAllStages
= true;
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1206 VkPhysicalDeviceMaintenance3Properties
*properties
=
1207 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1208 /* Make sure everything is addressable by a signed 32-bit int, and
1209 * our largest descriptors are 96 bytes. */
1210 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1211 /* Our buffer size fields allow only this much */
1212 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1215 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1216 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1217 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1218 /* GFX6-8 only support single channel min/max filter. */
1219 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1220 properties
->filterMinmaxSingleComponentFormats
= true;
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1224 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1225 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1227 /* Shader engines. */
1228 properties
->shaderEngineCount
=
1229 pdevice
->rad_info
.max_se
;
1230 properties
->shaderArraysPerEngineCount
=
1231 pdevice
->rad_info
.max_sh_per_se
;
1232 properties
->computeUnitsPerShaderArray
=
1233 pdevice
->rad_info
.num_good_cu_per_sh
;
1234 properties
->simdPerComputeUnit
= 4;
1235 properties
->wavefrontsPerSimd
=
1236 pdevice
->rad_info
.family
== CHIP_TONGA
||
1237 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1238 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1239 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1240 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1241 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1242 properties
->wavefrontSize
= 64;
1245 properties
->sgprsPerSimd
=
1246 ac_get_num_physical_sgprs(pdevice
->rad_info
.chip_class
);
1247 properties
->minSgprAllocation
=
1248 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1249 properties
->maxSgprAllocation
=
1250 pdevice
->rad_info
.family
== CHIP_TONGA
||
1251 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1252 properties
->sgprAllocationGranularity
=
1253 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1256 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1257 properties
->minVgprAllocation
= 4;
1258 properties
->maxVgprAllocation
= 256;
1259 properties
->vgprAllocationGranularity
= 4;
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1263 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1264 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1265 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1268 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1269 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1270 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1271 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1272 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1273 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1274 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1275 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1276 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1277 properties
->robustBufferAccessUpdateAfterBind
= false;
1278 properties
->quadDivergentImplicitLod
= false;
1280 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1281 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1282 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1283 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1284 32 /* sampler, largest when combined with image */ +
1285 64 /* sampled image */ +
1286 64 /* storage image */);
1287 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1288 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1289 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1290 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1291 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1292 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1293 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1294 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1295 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1296 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1297 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1298 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1299 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1300 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1301 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1304 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1305 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1306 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1307 properties
->protectedNoFault
= false;
1310 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1311 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1312 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1313 properties
->primitiveOverestimationSize
= 0;
1314 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1315 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1316 properties
->primitiveUnderestimation
= VK_FALSE
;
1317 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1318 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1319 properties
->degenerateLinesRasterized
= VK_FALSE
;
1320 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1321 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1324 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1325 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1326 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1327 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1328 properties
->pciBus
= pdevice
->bus_info
.bus
;
1329 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1330 properties
->pciFunction
= pdevice
->bus_info
.func
;
1333 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1334 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1335 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1337 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1338 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1339 strcpy(driver_props
->driverName
, "radv");
1341 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1342 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1343 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1344 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1346 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1354 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1355 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1356 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1357 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1358 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1359 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1360 properties
->maxTransformFeedbackStreamDataSize
= 512;
1361 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1362 properties
->maxTransformFeedbackBufferDataStride
= 512;
1363 properties
->transformFeedbackQueries
= true;
1364 properties
->transformFeedbackStreamsLinesTriangles
= true;
1365 properties
->transformFeedbackRasterizationStreamSelect
= false;
1366 properties
->transformFeedbackDraw
= true;
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1370 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1371 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1373 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1374 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1375 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1376 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1377 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1380 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1381 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1382 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1383 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1384 VK_SAMPLE_COUNT_4_BIT
|
1385 VK_SAMPLE_COUNT_8_BIT
;
1386 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1387 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1388 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1389 properties
->sampleLocationSubPixelBits
= 4;
1390 properties
->variableSampleLocations
= VK_FALSE
;
1393 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1394 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1395 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1397 /* We support all of the depth resolve modes */
1398 properties
->supportedDepthResolveModes
=
1399 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1400 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1401 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1402 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1404 /* Average doesn't make sense for stencil so we don't support that */
1405 properties
->supportedStencilResolveModes
=
1406 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1407 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1408 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1410 properties
->independentResolveNone
= VK_TRUE
;
1411 properties
->independentResolve
= VK_TRUE
;
1420 static void radv_get_physical_device_queue_family_properties(
1421 struct radv_physical_device
* pdevice
,
1423 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1425 int num_queue_families
= 1;
1427 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1428 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1429 num_queue_families
++;
1431 if (pQueueFamilyProperties
== NULL
) {
1432 *pCount
= num_queue_families
;
1441 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1442 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1443 VK_QUEUE_COMPUTE_BIT
|
1444 VK_QUEUE_TRANSFER_BIT
|
1445 VK_QUEUE_SPARSE_BINDING_BIT
,
1447 .timestampValidBits
= 64,
1448 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1453 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1454 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1455 if (*pCount
> idx
) {
1456 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1457 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1458 VK_QUEUE_TRANSFER_BIT
|
1459 VK_QUEUE_SPARSE_BINDING_BIT
,
1460 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1461 .timestampValidBits
= 64,
1462 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1470 void radv_GetPhysicalDeviceQueueFamilyProperties(
1471 VkPhysicalDevice physicalDevice
,
1473 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1475 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1476 if (!pQueueFamilyProperties
) {
1477 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1480 VkQueueFamilyProperties
*properties
[] = {
1481 pQueueFamilyProperties
+ 0,
1482 pQueueFamilyProperties
+ 1,
1483 pQueueFamilyProperties
+ 2,
1485 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1486 assert(*pCount
<= 3);
1489 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1490 VkPhysicalDevice physicalDevice
,
1492 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1494 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1495 if (!pQueueFamilyProperties
) {
1496 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1499 VkQueueFamilyProperties
*properties
[] = {
1500 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1501 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1502 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1504 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1505 assert(*pCount
<= 3);
1508 void radv_GetPhysicalDeviceMemoryProperties(
1509 VkPhysicalDevice physicalDevice
,
1510 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1512 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1514 *pMemoryProperties
= physical_device
->memory_properties
;
1518 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1519 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1521 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1522 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1523 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1524 uint64_t vram_size
= radv_get_vram_size(device
);
1525 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1526 uint64_t heap_budget
, heap_usage
;
1528 /* For all memory heaps, the computation of budget is as follow:
1529 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1531 * The Vulkan spec 1.1.97 says that the budget should include any
1532 * currently allocated device memory.
1534 * Note that the application heap usages are not really accurate (eg.
1535 * in presence of shared buffers).
1537 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1538 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1540 switch (device
->mem_type_indices
[i
]) {
1541 case RADV_MEM_TYPE_VRAM
:
1542 heap_usage
= device
->ws
->query_value(device
->ws
,
1543 RADEON_ALLOCATED_VRAM
);
1545 heap_budget
= vram_size
-
1546 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1549 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1550 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1552 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1553 heap_usage
= device
->ws
->query_value(device
->ws
,
1554 RADEON_ALLOCATED_VRAM_VIS
);
1556 heap_budget
= visible_vram_size
-
1557 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1560 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1561 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1563 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1564 heap_usage
= device
->ws
->query_value(device
->ws
,
1565 RADEON_ALLOCATED_GTT
);
1567 heap_budget
= gtt_size
-
1568 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1571 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1572 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1579 /* The heapBudget and heapUsage values must be zero for array elements
1580 * greater than or equal to
1581 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1583 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1584 memoryBudget
->heapBudget
[i
] = 0;
1585 memoryBudget
->heapUsage
[i
] = 0;
1589 void radv_GetPhysicalDeviceMemoryProperties2(
1590 VkPhysicalDevice physicalDevice
,
1591 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1593 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1594 &pMemoryProperties
->memoryProperties
);
1596 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1597 vk_find_struct(pMemoryProperties
->pNext
,
1598 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1600 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1603 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1605 VkExternalMemoryHandleTypeFlagBits handleType
,
1606 const void *pHostPointer
,
1607 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1609 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1613 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1614 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1615 uint32_t memoryTypeBits
= 0;
1616 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1617 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1618 memoryTypeBits
= (1 << i
);
1622 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1626 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1630 static enum radeon_ctx_priority
1631 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1633 /* Default to MEDIUM when a specific global priority isn't requested */
1635 return RADEON_CTX_PRIORITY_MEDIUM
;
1637 switch(pObj
->globalPriority
) {
1638 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1639 return RADEON_CTX_PRIORITY_REALTIME
;
1640 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1641 return RADEON_CTX_PRIORITY_HIGH
;
1642 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1643 return RADEON_CTX_PRIORITY_MEDIUM
;
1644 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1645 return RADEON_CTX_PRIORITY_LOW
;
1647 unreachable("Illegal global priority value");
1648 return RADEON_CTX_PRIORITY_INVALID
;
1653 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1654 uint32_t queue_family_index
, int idx
,
1655 VkDeviceQueueCreateFlags flags
,
1656 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1658 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1659 queue
->device
= device
;
1660 queue
->queue_family_index
= queue_family_index
;
1661 queue
->queue_idx
= idx
;
1662 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1663 queue
->flags
= flags
;
1665 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1667 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1673 radv_queue_finish(struct radv_queue
*queue
)
1676 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1678 if (queue
->initial_full_flush_preamble_cs
)
1679 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1680 if (queue
->initial_preamble_cs
)
1681 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1682 if (queue
->continue_preamble_cs
)
1683 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1684 if (queue
->descriptor_bo
)
1685 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1686 if (queue
->scratch_bo
)
1687 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1688 if (queue
->esgs_ring_bo
)
1689 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1690 if (queue
->gsvs_ring_bo
)
1691 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1692 if (queue
->tess_rings_bo
)
1693 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1694 if (queue
->compute_scratch_bo
)
1695 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1699 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1701 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1702 bo_list
->list
.count
= bo_list
->capacity
= 0;
1703 bo_list
->list
.bos
= NULL
;
1707 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1709 free(bo_list
->list
.bos
);
1710 pthread_mutex_destroy(&bo_list
->mutex
);
1713 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1714 struct radeon_winsys_bo
*bo
)
1716 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1721 if (unlikely(!device
->use_global_bo_list
))
1724 pthread_mutex_lock(&bo_list
->mutex
);
1725 if (bo_list
->list
.count
== bo_list
->capacity
) {
1726 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1727 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1730 pthread_mutex_unlock(&bo_list
->mutex
);
1731 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1734 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1735 bo_list
->capacity
= capacity
;
1738 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1739 pthread_mutex_unlock(&bo_list
->mutex
);
1743 static void radv_bo_list_remove(struct radv_device
*device
,
1744 struct radeon_winsys_bo
*bo
)
1746 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1751 if (unlikely(!device
->use_global_bo_list
))
1754 pthread_mutex_lock(&bo_list
->mutex
);
1755 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1756 if (bo_list
->list
.bos
[i
] == bo
) {
1757 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1758 --bo_list
->list
.count
;
1762 pthread_mutex_unlock(&bo_list
->mutex
);
1766 radv_device_init_gs_info(struct radv_device
*device
)
1768 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1769 device
->physical_device
->rad_info
.family
);
1772 static int radv_get_device_extension_index(const char *name
)
1774 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1775 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1782 radv_get_int_debug_option(const char *name
, int default_value
)
1789 result
= default_value
;
1793 result
= strtol(str
, &endptr
, 0);
1794 if (str
== endptr
) {
1795 /* No digits founs. */
1796 result
= default_value
;
1803 VkResult
radv_CreateDevice(
1804 VkPhysicalDevice physicalDevice
,
1805 const VkDeviceCreateInfo
* pCreateInfo
,
1806 const VkAllocationCallbacks
* pAllocator
,
1809 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1811 struct radv_device
*device
;
1813 bool keep_shader_info
= false;
1815 /* Check enabled features */
1816 if (pCreateInfo
->pEnabledFeatures
) {
1817 VkPhysicalDeviceFeatures supported_features
;
1818 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1819 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1820 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1821 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1822 for (uint32_t i
= 0; i
< num_features
; i
++) {
1823 if (enabled_feature
[i
] && !supported_feature
[i
])
1824 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1828 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1830 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1832 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1834 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1835 device
->instance
= physical_device
->instance
;
1836 device
->physical_device
= physical_device
;
1838 device
->ws
= physical_device
->ws
;
1840 device
->alloc
= *pAllocator
;
1842 device
->alloc
= physical_device
->instance
->alloc
;
1844 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1845 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1846 int index
= radv_get_device_extension_index(ext_name
);
1847 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1848 vk_free(&device
->alloc
, device
);
1849 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1852 device
->enabled_extensions
.extensions
[index
] = true;
1855 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1857 /* With update after bind we can't attach bo's to the command buffer
1858 * from the descriptor set anymore, so we have to use a global BO list.
1860 device
->use_global_bo_list
=
1861 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
1862 device
->enabled_extensions
.EXT_descriptor_indexing
||
1863 device
->enabled_extensions
.EXT_buffer_device_address
;
1865 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1866 list_inithead(&device
->shader_slabs
);
1868 radv_bo_list_init(&device
->bo_list
);
1870 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1871 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1872 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1873 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1874 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1876 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1878 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1879 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1880 if (!device
->queues
[qfi
]) {
1881 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1885 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1887 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1889 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1890 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1891 qfi
, q
, queue_create
->flags
,
1893 if (result
!= VK_SUCCESS
)
1898 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1899 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1901 /* Disabled and not implemented for now. */
1902 device
->dfsm_allowed
= device
->pbb_allowed
&&
1903 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1904 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1907 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1910 /* The maximum number of scratch waves. Scratch space isn't divided
1911 * evenly between CUs. The number is only a function of the number of CUs.
1912 * We can decrease the constant to decrease the scratch buffer size.
1914 * sctx->scratch_waves must be >= the maximum possible size of
1915 * 1 threadgroup, so that the hw doesn't hang from being unable
1918 * The recommended value is 4 per CU at most. Higher numbers don't
1919 * bring much benefit, but they still occupy chip resources (think
1920 * async compute). I've seen ~2% performance difference between 4 and 32.
1922 uint32_t max_threads_per_block
= 2048;
1923 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1924 max_threads_per_block
/ 64);
1926 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1928 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1929 /* If the KMD allows it (there is a KMD hw register for it),
1930 * allow launching waves out-of-order.
1932 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1935 radv_device_init_gs_info(device
);
1937 device
->tess_offchip_block_dw_size
=
1938 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1939 device
->has_distributed_tess
=
1940 device
->physical_device
->rad_info
.chip_class
>= GFX8
&&
1941 device
->physical_device
->rad_info
.max_se
>= 2;
1943 if (getenv("RADV_TRACE_FILE")) {
1944 const char *filename
= getenv("RADV_TRACE_FILE");
1946 keep_shader_info
= true;
1948 if (!radv_init_trace(device
))
1951 fprintf(stderr
, "*****************************************************************************\n");
1952 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1953 fprintf(stderr
, "*****************************************************************************\n");
1955 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1956 radv_dump_enabled_options(device
, stderr
);
1959 device
->keep_shader_info
= keep_shader_info
;
1961 result
= radv_device_init_meta(device
);
1962 if (result
!= VK_SUCCESS
)
1965 radv_device_init_msaa(device
);
1967 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1968 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1970 case RADV_QUEUE_GENERAL
:
1971 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1972 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1973 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1975 case RADV_QUEUE_COMPUTE
:
1976 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1977 radeon_emit(device
->empty_cs
[family
], 0);
1980 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1983 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
1984 cik_create_gfx_config(device
);
1986 VkPipelineCacheCreateInfo ci
;
1987 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1990 ci
.pInitialData
= NULL
;
1991 ci
.initialDataSize
= 0;
1993 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1995 if (result
!= VK_SUCCESS
)
1998 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2000 device
->force_aniso
=
2001 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2002 if (device
->force_aniso
>= 0) {
2003 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2004 1 << util_logbase2(device
->force_aniso
));
2007 *pDevice
= radv_device_to_handle(device
);
2011 radv_device_finish_meta(device
);
2013 radv_bo_list_finish(&device
->bo_list
);
2015 if (device
->trace_bo
)
2016 device
->ws
->buffer_destroy(device
->trace_bo
);
2018 if (device
->gfx_init
)
2019 device
->ws
->buffer_destroy(device
->gfx_init
);
2021 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2022 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2023 radv_queue_finish(&device
->queues
[i
][q
]);
2024 if (device
->queue_count
[i
])
2025 vk_free(&device
->alloc
, device
->queues
[i
]);
2028 vk_free(&device
->alloc
, device
);
2032 void radv_DestroyDevice(
2034 const VkAllocationCallbacks
* pAllocator
)
2036 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2041 if (device
->trace_bo
)
2042 device
->ws
->buffer_destroy(device
->trace_bo
);
2044 if (device
->gfx_init
)
2045 device
->ws
->buffer_destroy(device
->gfx_init
);
2047 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2048 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2049 radv_queue_finish(&device
->queues
[i
][q
]);
2050 if (device
->queue_count
[i
])
2051 vk_free(&device
->alloc
, device
->queues
[i
]);
2052 if (device
->empty_cs
[i
])
2053 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2055 radv_device_finish_meta(device
);
2057 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2058 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2060 radv_destroy_shader_slabs(device
);
2062 radv_bo_list_finish(&device
->bo_list
);
2063 vk_free(&device
->alloc
, device
);
2066 VkResult
radv_EnumerateInstanceLayerProperties(
2067 uint32_t* pPropertyCount
,
2068 VkLayerProperties
* pProperties
)
2070 if (pProperties
== NULL
) {
2071 *pPropertyCount
= 0;
2075 /* None supported at this time */
2076 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2079 VkResult
radv_EnumerateDeviceLayerProperties(
2080 VkPhysicalDevice physicalDevice
,
2081 uint32_t* pPropertyCount
,
2082 VkLayerProperties
* pProperties
)
2084 if (pProperties
== NULL
) {
2085 *pPropertyCount
= 0;
2089 /* None supported at this time */
2090 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2093 void radv_GetDeviceQueue2(
2095 const VkDeviceQueueInfo2
* pQueueInfo
,
2098 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2099 struct radv_queue
*queue
;
2101 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2102 if (pQueueInfo
->flags
!= queue
->flags
) {
2103 /* From the Vulkan 1.1.70 spec:
2105 * "The queue returned by vkGetDeviceQueue2 must have the same
2106 * flags value from this structure as that used at device
2107 * creation time in a VkDeviceQueueCreateInfo instance. If no
2108 * matching flags were specified at device creation time then
2109 * pQueue will return VK_NULL_HANDLE."
2111 *pQueue
= VK_NULL_HANDLE
;
2115 *pQueue
= radv_queue_to_handle(queue
);
2118 void radv_GetDeviceQueue(
2120 uint32_t queueFamilyIndex
,
2121 uint32_t queueIndex
,
2124 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2125 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2126 .queueFamilyIndex
= queueFamilyIndex
,
2127 .queueIndex
= queueIndex
2130 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2134 fill_geom_tess_rings(struct radv_queue
*queue
,
2136 bool add_sample_positions
,
2137 uint32_t esgs_ring_size
,
2138 struct radeon_winsys_bo
*esgs_ring_bo
,
2139 uint32_t gsvs_ring_size
,
2140 struct radeon_winsys_bo
*gsvs_ring_bo
,
2141 uint32_t tess_factor_ring_size
,
2142 uint32_t tess_offchip_ring_offset
,
2143 uint32_t tess_offchip_ring_size
,
2144 struct radeon_winsys_bo
*tess_rings_bo
)
2146 uint32_t *desc
= &map
[4];
2149 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2151 /* stride 0, num records - size, add tid, swizzle, elsize4,
2154 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2155 S_008F04_STRIDE(0) |
2156 S_008F04_SWIZZLE_ENABLE(true);
2157 desc
[2] = esgs_ring_size
;
2158 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2159 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2160 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2161 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2162 S_008F0C_ELEMENT_SIZE(1) |
2163 S_008F0C_INDEX_STRIDE(3) |
2164 S_008F0C_ADD_TID_ENABLE(true);
2166 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2167 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2168 S_008F0C_OOB_SELECT(2) |
2169 S_008F0C_RESOURCE_LEVEL(1);
2171 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2172 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2175 /* GS entry for ES->GS ring */
2176 /* stride 0, num records - size, elsize0,
2179 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
2180 S_008F04_STRIDE(0) |
2181 S_008F04_SWIZZLE_ENABLE(false);
2182 desc
[6] = esgs_ring_size
;
2183 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2184 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2185 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2186 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2187 S_008F0C_ELEMENT_SIZE(0) |
2188 S_008F0C_INDEX_STRIDE(0) |
2189 S_008F0C_ADD_TID_ENABLE(false);
2191 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2192 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2193 S_008F0C_OOB_SELECT(2) |
2194 S_008F0C_RESOURCE_LEVEL(1);
2196 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2197 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2204 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2206 /* VS entry for GS->VS ring */
2207 /* stride 0, num records - size, elsize0,
2210 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2211 S_008F04_STRIDE(0) |
2212 S_008F04_SWIZZLE_ENABLE(false);
2213 desc
[2] = gsvs_ring_size
;
2214 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2215 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2216 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2217 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2218 S_008F0C_ELEMENT_SIZE(0) |
2219 S_008F0C_INDEX_STRIDE(0) |
2220 S_008F0C_ADD_TID_ENABLE(false);
2222 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2223 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2224 S_008F0C_OOB_SELECT(2) |
2225 S_008F0C_RESOURCE_LEVEL(1);
2227 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2228 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2231 /* stride gsvs_itemsize, num records 64
2232 elsize 4, index stride 16 */
2233 /* shader will patch stride and desc[2] */
2235 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
2236 S_008F04_STRIDE(0) |
2237 S_008F04_SWIZZLE_ENABLE(true);
2239 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2240 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2241 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2242 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2243 S_008F0C_ELEMENT_SIZE(1) |
2244 S_008F0C_INDEX_STRIDE(1) |
2245 S_008F0C_ADD_TID_ENABLE(true);
2247 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2248 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2249 S_008F0C_OOB_SELECT(2) |
2250 S_008F0C_RESOURCE_LEVEL(1);
2252 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2253 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2260 if (tess_rings_bo
) {
2261 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2262 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2265 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
2266 S_008F04_STRIDE(0) |
2267 S_008F04_SWIZZLE_ENABLE(false);
2268 desc
[2] = tess_factor_ring_size
;
2269 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2270 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2271 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2272 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2274 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2275 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2276 S_008F0C_OOB_SELECT(3) |
2277 S_008F0C_RESOURCE_LEVEL(1);
2279 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2283 desc
[4] = tess_offchip_va
;
2284 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
2285 S_008F04_STRIDE(0) |
2286 S_008F04_SWIZZLE_ENABLE(false);
2287 desc
[6] = tess_offchip_ring_size
;
2288 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2289 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2290 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2291 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2293 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2294 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2295 S_008F0C_OOB_SELECT(3) |
2296 S_008F0C_RESOURCE_LEVEL(1);
2298 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2299 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2305 if (add_sample_positions
) {
2306 /* add sample positions after all rings */
2307 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2309 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2311 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2313 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2318 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2320 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2321 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2322 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2323 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2324 unsigned max_offchip_buffers
;
2325 unsigned offchip_granularity
;
2326 unsigned hs_offchip_param
;
2330 * This must be one less than the maximum number due to a hw limitation.
2331 * Various hardware bugs need thGFX7
2334 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2335 * Gfx7 should limit max_offchip_buffers to 508
2336 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2338 * Follow AMDVLK here.
2340 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2341 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2342 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2343 --max_offchip_buffers_per_se
;
2345 max_offchip_buffers
= max_offchip_buffers_per_se
*
2346 device
->physical_device
->rad_info
.max_se
;
2348 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2349 * around by setting 4K granularity.
2351 if (device
->tess_offchip_block_dw_size
== 4096) {
2352 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2353 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2355 assert(device
->tess_offchip_block_dw_size
== 8192);
2356 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2359 switch (device
->physical_device
->rad_info
.chip_class
) {
2361 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2367 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2371 *max_offchip_buffers_p
= max_offchip_buffers
;
2372 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2373 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2374 --max_offchip_buffers
;
2376 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2377 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2380 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2382 return hs_offchip_param
;
2386 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2387 struct radeon_winsys_bo
*esgs_ring_bo
,
2388 uint32_t esgs_ring_size
,
2389 struct radeon_winsys_bo
*gsvs_ring_bo
,
2390 uint32_t gsvs_ring_size
)
2392 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2396 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2399 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2401 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2402 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2403 radeon_emit(cs
, esgs_ring_size
>> 8);
2404 radeon_emit(cs
, gsvs_ring_size
>> 8);
2406 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2407 radeon_emit(cs
, esgs_ring_size
>> 8);
2408 radeon_emit(cs
, gsvs_ring_size
>> 8);
2413 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2414 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2415 struct radeon_winsys_bo
*tess_rings_bo
)
2422 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2424 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2426 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2427 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2428 S_030938_SIZE(tf_ring_size
/ 4));
2429 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2432 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2433 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
2434 S_030984_BASE_HI(tf_va
>> 40));
2435 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2436 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2437 S_030944_BASE_HI(tf_va
>> 40));
2439 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2442 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2443 S_008988_SIZE(tf_ring_size
/ 4));
2444 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2446 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2452 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2453 struct radeon_winsys_bo
*compute_scratch_bo
)
2455 uint64_t scratch_va
;
2457 if (!compute_scratch_bo
)
2460 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2462 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2464 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2465 radeon_emit(cs
, scratch_va
);
2466 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2467 S_008F04_SWIZZLE_ENABLE(1));
2471 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2472 struct radeon_cmdbuf
*cs
,
2473 struct radeon_winsys_bo
*descriptor_bo
)
2480 va
= radv_buffer_get_va(descriptor_bo
);
2482 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2484 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2485 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2486 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2487 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2488 R_00B430_SPI_SHADER_USER_DATA_HS_0
};
2490 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2491 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2494 } else if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2495 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2496 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2497 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2498 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2500 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2501 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2505 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2506 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2507 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2508 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2509 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2510 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2512 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2513 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2520 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2522 struct radv_device
*device
= queue
->device
;
2524 if (device
->gfx_init
) {
2525 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2527 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2528 radeon_emit(cs
, va
);
2529 radeon_emit(cs
, va
>> 32);
2530 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2532 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2534 struct radv_physical_device
*physical_device
= device
->physical_device
;
2535 si_emit_graphics(physical_device
, cs
);
2540 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2542 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2543 si_emit_compute(physical_device
, cs
);
2547 radv_get_preamble_cs(struct radv_queue
*queue
,
2548 uint32_t scratch_size
,
2549 uint32_t compute_scratch_size
,
2550 uint32_t esgs_ring_size
,
2551 uint32_t gsvs_ring_size
,
2552 bool needs_tess_rings
,
2553 bool needs_sample_positions
,
2554 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2555 struct radeon_cmdbuf
**initial_preamble_cs
,
2556 struct radeon_cmdbuf
**continue_preamble_cs
)
2558 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2559 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2560 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2561 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2562 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2563 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2564 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2565 bool add_tess_rings
= false, add_sample_positions
= false;
2566 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2567 unsigned max_offchip_buffers
;
2568 unsigned hs_offchip_param
= 0;
2569 unsigned tess_offchip_ring_offset
;
2570 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2571 if (!queue
->has_tess_rings
) {
2572 if (needs_tess_rings
)
2573 add_tess_rings
= true;
2575 if (!queue
->has_sample_positions
) {
2576 if (needs_sample_positions
)
2577 add_sample_positions
= true;
2579 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2580 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2581 &max_offchip_buffers
);
2582 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2583 tess_offchip_ring_size
= max_offchip_buffers
*
2584 queue
->device
->tess_offchip_block_dw_size
* 4;
2586 if (scratch_size
<= queue
->scratch_size
&&
2587 compute_scratch_size
<= queue
->compute_scratch_size
&&
2588 esgs_ring_size
<= queue
->esgs_ring_size
&&
2589 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2590 !add_tess_rings
&& !add_sample_positions
&&
2591 queue
->initial_preamble_cs
) {
2592 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2593 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2594 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2595 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2596 *continue_preamble_cs
= NULL
;
2600 if (scratch_size
> queue
->scratch_size
) {
2601 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2606 RADV_BO_PRIORITY_SCRATCH
);
2610 scratch_bo
= queue
->scratch_bo
;
2612 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2613 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2614 compute_scratch_size
,
2618 RADV_BO_PRIORITY_SCRATCH
);
2619 if (!compute_scratch_bo
)
2623 compute_scratch_bo
= queue
->compute_scratch_bo
;
2625 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2626 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2631 RADV_BO_PRIORITY_SCRATCH
);
2635 esgs_ring_bo
= queue
->esgs_ring_bo
;
2636 esgs_ring_size
= queue
->esgs_ring_size
;
2639 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2640 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2645 RADV_BO_PRIORITY_SCRATCH
);
2649 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2650 gsvs_ring_size
= queue
->gsvs_ring_size
;
2653 if (add_tess_rings
) {
2654 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2655 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2659 RADV_BO_PRIORITY_SCRATCH
);
2663 tess_rings_bo
= queue
->tess_rings_bo
;
2666 if (scratch_bo
!= queue
->scratch_bo
||
2667 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2668 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2669 tess_rings_bo
!= queue
->tess_rings_bo
||
2670 add_sample_positions
) {
2672 if (gsvs_ring_bo
|| esgs_ring_bo
||
2673 tess_rings_bo
|| add_sample_positions
) {
2674 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2675 if (add_sample_positions
)
2676 size
+= 128; /* 64+32+16+8 = 120 bytes */
2678 else if (scratch_bo
)
2679 size
= 8; /* 2 dword */
2681 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2685 RADEON_FLAG_CPU_ACCESS
|
2686 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2687 RADEON_FLAG_READ_ONLY
,
2688 RADV_BO_PRIORITY_DESCRIPTOR
);
2692 descriptor_bo
= queue
->descriptor_bo
;
2694 if (descriptor_bo
!= queue
->descriptor_bo
) {
2695 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2698 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2699 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2700 S_008F04_SWIZZLE_ENABLE(1);
2701 map
[0] = scratch_va
;
2705 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
2706 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2707 esgs_ring_size
, esgs_ring_bo
,
2708 gsvs_ring_size
, gsvs_ring_bo
,
2709 tess_factor_ring_size
,
2710 tess_offchip_ring_offset
,
2711 tess_offchip_ring_size
,
2714 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2717 for(int i
= 0; i
< 3; ++i
) {
2718 struct radeon_cmdbuf
*cs
= NULL
;
2719 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2720 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2727 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2729 /* Emit initial configuration. */
2730 switch (queue
->queue_family_index
) {
2731 case RADV_QUEUE_GENERAL
:
2732 radv_init_graphics_state(cs
, queue
);
2734 case RADV_QUEUE_COMPUTE
:
2735 radv_init_compute_state(cs
, queue
);
2737 case RADV_QUEUE_TRANSFER
:
2741 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2742 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2743 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2744 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2745 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2748 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2749 gsvs_ring_bo
, gsvs_ring_size
);
2750 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2751 tess_factor_ring_size
, tess_rings_bo
);
2752 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2753 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2756 si_cs_emit_cache_flush(cs
,
2757 queue
->device
->physical_device
->rad_info
.chip_class
,
2759 queue
->queue_family_index
== RING_COMPUTE
&&
2760 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2761 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2762 RADV_CMD_FLAG_INV_ICACHE
|
2763 RADV_CMD_FLAG_INV_SCACHE
|
2764 RADV_CMD_FLAG_INV_VCACHE
|
2765 RADV_CMD_FLAG_INV_L2
|
2766 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2767 } else if (i
== 1) {
2768 si_cs_emit_cache_flush(cs
,
2769 queue
->device
->physical_device
->rad_info
.chip_class
,
2771 queue
->queue_family_index
== RING_COMPUTE
&&
2772 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
2773 RADV_CMD_FLAG_INV_ICACHE
|
2774 RADV_CMD_FLAG_INV_SCACHE
|
2775 RADV_CMD_FLAG_INV_VCACHE
|
2776 RADV_CMD_FLAG_INV_L2
|
2777 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2780 if (!queue
->device
->ws
->cs_finalize(cs
))
2784 if (queue
->initial_full_flush_preamble_cs
)
2785 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2787 if (queue
->initial_preamble_cs
)
2788 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2790 if (queue
->continue_preamble_cs
)
2791 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2793 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2794 queue
->initial_preamble_cs
= dest_cs
[1];
2795 queue
->continue_preamble_cs
= dest_cs
[2];
2797 if (scratch_bo
!= queue
->scratch_bo
) {
2798 if (queue
->scratch_bo
)
2799 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2800 queue
->scratch_bo
= scratch_bo
;
2801 queue
->scratch_size
= scratch_size
;
2804 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2805 if (queue
->compute_scratch_bo
)
2806 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2807 queue
->compute_scratch_bo
= compute_scratch_bo
;
2808 queue
->compute_scratch_size
= compute_scratch_size
;
2811 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2812 if (queue
->esgs_ring_bo
)
2813 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2814 queue
->esgs_ring_bo
= esgs_ring_bo
;
2815 queue
->esgs_ring_size
= esgs_ring_size
;
2818 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2819 if (queue
->gsvs_ring_bo
)
2820 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2821 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2822 queue
->gsvs_ring_size
= gsvs_ring_size
;
2825 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2826 queue
->tess_rings_bo
= tess_rings_bo
;
2827 queue
->has_tess_rings
= true;
2830 if (descriptor_bo
!= queue
->descriptor_bo
) {
2831 if (queue
->descriptor_bo
)
2832 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2834 queue
->descriptor_bo
= descriptor_bo
;
2837 if (add_sample_positions
)
2838 queue
->has_sample_positions
= true;
2840 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2841 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2842 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2843 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2844 *continue_preamble_cs
= NULL
;
2847 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2849 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2850 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2851 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2852 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2853 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2854 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2855 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2856 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2857 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2858 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2859 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2860 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2861 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2862 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2865 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2866 struct radv_winsys_sem_counts
*counts
,
2868 const VkSemaphore
*sems
,
2872 int syncobj_idx
= 0, sem_idx
= 0;
2874 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2877 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2878 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2880 if (sem
->temp_syncobj
|| sem
->syncobj
)
2881 counts
->syncobj_count
++;
2883 counts
->sem_count
++;
2886 if (_fence
!= VK_NULL_HANDLE
) {
2887 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2888 if (fence
->temp_syncobj
|| fence
->syncobj
)
2889 counts
->syncobj_count
++;
2892 if (counts
->syncobj_count
) {
2893 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2894 if (!counts
->syncobj
)
2895 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2898 if (counts
->sem_count
) {
2899 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2901 free(counts
->syncobj
);
2902 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2906 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2907 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2909 if (sem
->temp_syncobj
) {
2910 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2912 else if (sem
->syncobj
)
2913 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2916 counts
->sem
[sem_idx
++] = sem
->sem
;
2920 if (_fence
!= VK_NULL_HANDLE
) {
2921 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2922 if (fence
->temp_syncobj
)
2923 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2924 else if (fence
->syncobj
)
2925 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2932 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2934 free(sem_info
->wait
.syncobj
);
2935 free(sem_info
->wait
.sem
);
2936 free(sem_info
->signal
.syncobj
);
2937 free(sem_info
->signal
.sem
);
2941 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2943 const VkSemaphore
*sems
)
2945 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2946 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2948 if (sem
->temp_syncobj
) {
2949 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2950 sem
->temp_syncobj
= 0;
2956 radv_alloc_sem_info(struct radv_instance
*instance
,
2957 struct radv_winsys_sem_info
*sem_info
,
2959 const VkSemaphore
*wait_sems
,
2960 int num_signal_sems
,
2961 const VkSemaphore
*signal_sems
,
2965 memset(sem_info
, 0, sizeof(*sem_info
));
2967 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2970 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2972 radv_free_sem_info(sem_info
);
2974 /* caller can override these */
2975 sem_info
->cs_emit_wait
= true;
2976 sem_info
->cs_emit_signal
= true;
2980 /* Signals fence as soon as all the work currently put on queue is done. */
2981 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2982 struct radv_fence
*fence
)
2986 struct radv_winsys_sem_info sem_info
;
2988 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2989 radv_fence_to_handle(fence
));
2990 if (result
!= VK_SUCCESS
)
2993 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2994 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2995 1, NULL
, NULL
, &sem_info
, NULL
,
2996 false, fence
->fence
);
2997 radv_free_sem_info(&sem_info
);
3000 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
3005 VkResult
radv_QueueSubmit(
3007 uint32_t submitCount
,
3008 const VkSubmitInfo
* pSubmits
,
3011 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3012 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3013 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3014 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
3016 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
3017 uint32_t scratch_size
= 0;
3018 uint32_t compute_scratch_size
= 0;
3019 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
3020 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
3022 bool fence_emitted
= false;
3023 bool tess_rings_needed
= false;
3024 bool sample_positions_needed
= false;
3026 /* Do this first so failing to allocate scratch buffers can't result in
3027 * partially executed submissions. */
3028 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3029 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3030 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3031 pSubmits
[i
].pCommandBuffers
[j
]);
3033 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
3034 compute_scratch_size
= MAX2(compute_scratch_size
,
3035 cmd_buffer
->compute_scratch_size_needed
);
3036 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
3037 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
3038 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
3039 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
3043 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
3044 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
3045 sample_positions_needed
, &initial_flush_preamble_cs
,
3046 &initial_preamble_cs
, &continue_preamble_cs
);
3047 if (result
!= VK_SUCCESS
)
3050 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3051 struct radeon_cmdbuf
**cs_array
;
3052 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
3053 bool can_patch
= true;
3055 struct radv_winsys_sem_info sem_info
;
3057 result
= radv_alloc_sem_info(queue
->device
->instance
,
3059 pSubmits
[i
].waitSemaphoreCount
,
3060 pSubmits
[i
].pWaitSemaphores
,
3061 pSubmits
[i
].signalSemaphoreCount
,
3062 pSubmits
[i
].pSignalSemaphores
,
3064 if (result
!= VK_SUCCESS
)
3067 if (!pSubmits
[i
].commandBufferCount
) {
3068 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
3069 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3070 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3075 radv_loge("failed to submit CS %d\n", i
);
3078 fence_emitted
= true;
3080 radv_free_sem_info(&sem_info
);
3084 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3085 (pSubmits
[i
].commandBufferCount
));
3087 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
3088 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3089 pSubmits
[i
].pCommandBuffers
[j
]);
3090 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3092 cs_array
[j
] = cmd_buffer
->cs
;
3093 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3096 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3099 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
3100 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3101 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3103 advance
= MIN2(max_cs_submission
,
3104 pSubmits
[i
].commandBufferCount
- j
);
3106 if (queue
->device
->trace_bo
)
3107 *queue
->device
->trace_id_ptr
= 0;
3109 sem_info
.cs_emit_wait
= j
== 0;
3110 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
3112 if (unlikely(queue
->device
->use_global_bo_list
)) {
3113 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3114 bo_list
= &queue
->device
->bo_list
.list
;
3117 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3118 advance
, initial_preamble
, continue_preamble_cs
,
3120 can_patch
, base_fence
);
3122 if (unlikely(queue
->device
->use_global_bo_list
))
3123 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3126 radv_loge("failed to submit CS %d\n", i
);
3129 fence_emitted
= true;
3130 if (queue
->device
->trace_bo
) {
3131 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3135 radv_free_temp_syncobjs(queue
->device
,
3136 pSubmits
[i
].waitSemaphoreCount
,
3137 pSubmits
[i
].pWaitSemaphores
);
3138 radv_free_sem_info(&sem_info
);
3143 if (!fence_emitted
) {
3144 result
= radv_signal_fence(queue
, fence
);
3145 if (result
!= VK_SUCCESS
)
3153 VkResult
radv_QueueWaitIdle(
3156 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3158 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3159 radv_queue_family_to_ring(queue
->queue_family_index
),
3164 VkResult
radv_DeviceWaitIdle(
3167 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3169 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3170 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3171 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3177 VkResult
radv_EnumerateInstanceExtensionProperties(
3178 const char* pLayerName
,
3179 uint32_t* pPropertyCount
,
3180 VkExtensionProperties
* pProperties
)
3182 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3184 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3185 if (radv_supported_instance_extensions
.extensions
[i
]) {
3186 vk_outarray_append(&out
, prop
) {
3187 *prop
= radv_instance_extensions
[i
];
3192 return vk_outarray_status(&out
);
3195 VkResult
radv_EnumerateDeviceExtensionProperties(
3196 VkPhysicalDevice physicalDevice
,
3197 const char* pLayerName
,
3198 uint32_t* pPropertyCount
,
3199 VkExtensionProperties
* pProperties
)
3201 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3202 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3204 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3205 if (device
->supported_extensions
.extensions
[i
]) {
3206 vk_outarray_append(&out
, prop
) {
3207 *prop
= radv_device_extensions
[i
];
3212 return vk_outarray_status(&out
);
3215 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3216 VkInstance _instance
,
3219 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3221 return radv_lookup_entrypoint_checked(pName
,
3222 instance
? instance
->apiVersion
: 0,
3223 instance
? &instance
->enabled_extensions
: NULL
,
3227 /* The loader wants us to expose a second GetInstanceProcAddr function
3228 * to work around certain LD_PRELOAD issues seen in apps.
3231 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3232 VkInstance instance
,
3236 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3237 VkInstance instance
,
3240 return radv_GetInstanceProcAddr(instance
, pName
);
3244 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3245 VkInstance _instance
,
3249 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3250 VkInstance _instance
,
3253 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3255 return radv_lookup_physical_device_entrypoint_checked(pName
,
3256 instance
? instance
->apiVersion
: 0,
3257 instance
? &instance
->enabled_extensions
: NULL
);
3260 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3264 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3266 return radv_lookup_entrypoint_checked(pName
,
3267 device
->instance
->apiVersion
,
3268 &device
->instance
->enabled_extensions
,
3269 &device
->enabled_extensions
);
3272 bool radv_get_memory_fd(struct radv_device
*device
,
3273 struct radv_device_memory
*memory
,
3276 struct radeon_bo_metadata metadata
;
3278 if (memory
->image
) {
3279 radv_init_metadata(device
, memory
->image
, &metadata
);
3280 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3283 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3287 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3288 const VkMemoryAllocateInfo
* pAllocateInfo
,
3289 const VkAllocationCallbacks
* pAllocator
,
3290 VkDeviceMemory
* pMem
)
3292 struct radv_device_memory
*mem
;
3294 enum radeon_bo_domain domain
;
3296 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3298 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3300 if (pAllocateInfo
->allocationSize
== 0) {
3301 /* Apparently, this is allowed */
3302 *pMem
= VK_NULL_HANDLE
;
3306 const VkImportMemoryFdInfoKHR
*import_info
=
3307 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3308 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3309 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3310 const VkExportMemoryAllocateInfo
*export_info
=
3311 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3312 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3313 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3315 const struct wsi_memory_allocate_info
*wsi_info
=
3316 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3318 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
3319 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3321 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3323 if (wsi_info
&& wsi_info
->implicit_sync
)
3324 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
3326 if (dedicate_info
) {
3327 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
3328 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
3334 float priority_float
= 0.5;
3335 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
3336 vk_find_struct_const(pAllocateInfo
->pNext
,
3337 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
3339 priority_float
= priority_ext
->priority
;
3341 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
3342 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
3344 mem
->user_ptr
= NULL
;
3347 assert(import_info
->handleType
==
3348 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
3349 import_info
->handleType
==
3350 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3351 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3352 priority
, NULL
, NULL
);
3354 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3357 close(import_info
->fd
);
3359 } else if (host_ptr_info
) {
3360 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3361 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3362 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3363 pAllocateInfo
->allocationSize
,
3366 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
3369 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3372 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3373 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3374 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3375 domain
= RADEON_DOMAIN_GTT
;
3377 domain
= RADEON_DOMAIN_VRAM
;
3379 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3380 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3382 flags
|= RADEON_FLAG_CPU_ACCESS
;
3384 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3385 flags
|= RADEON_FLAG_GTT_WC
;
3387 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
3388 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3389 if (device
->use_global_bo_list
) {
3390 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
3394 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3395 domain
, flags
, priority
);
3398 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3401 mem
->type_index
= mem_type_index
;
3404 result
= radv_bo_list_add(device
, mem
->bo
);
3405 if (result
!= VK_SUCCESS
)
3408 *pMem
= radv_device_memory_to_handle(mem
);
3413 device
->ws
->buffer_destroy(mem
->bo
);
3415 vk_free2(&device
->alloc
, pAllocator
, mem
);
3420 VkResult
radv_AllocateMemory(
3422 const VkMemoryAllocateInfo
* pAllocateInfo
,
3423 const VkAllocationCallbacks
* pAllocator
,
3424 VkDeviceMemory
* pMem
)
3426 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3427 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3430 void radv_FreeMemory(
3432 VkDeviceMemory _mem
,
3433 const VkAllocationCallbacks
* pAllocator
)
3435 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3436 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3441 radv_bo_list_remove(device
, mem
->bo
);
3442 device
->ws
->buffer_destroy(mem
->bo
);
3445 vk_free2(&device
->alloc
, pAllocator
, mem
);
3448 VkResult
radv_MapMemory(
3450 VkDeviceMemory _memory
,
3451 VkDeviceSize offset
,
3453 VkMemoryMapFlags flags
,
3456 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3457 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3465 *ppData
= mem
->user_ptr
;
3467 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3474 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3477 void radv_UnmapMemory(
3479 VkDeviceMemory _memory
)
3481 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3482 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3487 if (mem
->user_ptr
== NULL
)
3488 device
->ws
->buffer_unmap(mem
->bo
);
3491 VkResult
radv_FlushMappedMemoryRanges(
3493 uint32_t memoryRangeCount
,
3494 const VkMappedMemoryRange
* pMemoryRanges
)
3499 VkResult
radv_InvalidateMappedMemoryRanges(
3501 uint32_t memoryRangeCount
,
3502 const VkMappedMemoryRange
* pMemoryRanges
)
3507 void radv_GetBufferMemoryRequirements(
3510 VkMemoryRequirements
* pMemoryRequirements
)
3512 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3513 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3515 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3517 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3518 pMemoryRequirements
->alignment
= 4096;
3520 pMemoryRequirements
->alignment
= 16;
3522 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3525 void radv_GetBufferMemoryRequirements2(
3527 const VkBufferMemoryRequirementsInfo2
*pInfo
,
3528 VkMemoryRequirements2
*pMemoryRequirements
)
3530 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3531 &pMemoryRequirements
->memoryRequirements
);
3532 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3533 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3534 switch (ext
->sType
) {
3535 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3536 VkMemoryDedicatedRequirements
*req
=
3537 (VkMemoryDedicatedRequirements
*) ext
;
3538 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3539 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3548 void radv_GetImageMemoryRequirements(
3551 VkMemoryRequirements
* pMemoryRequirements
)
3553 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3554 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3556 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3558 pMemoryRequirements
->size
= image
->size
;
3559 pMemoryRequirements
->alignment
= image
->alignment
;
3562 void radv_GetImageMemoryRequirements2(
3564 const VkImageMemoryRequirementsInfo2
*pInfo
,
3565 VkMemoryRequirements2
*pMemoryRequirements
)
3567 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3568 &pMemoryRequirements
->memoryRequirements
);
3570 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3572 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3573 switch (ext
->sType
) {
3574 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
3575 VkMemoryDedicatedRequirements
*req
=
3576 (VkMemoryDedicatedRequirements
*) ext
;
3577 req
->requiresDedicatedAllocation
= image
->shareable
;
3578 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3587 void radv_GetImageSparseMemoryRequirements(
3590 uint32_t* pSparseMemoryRequirementCount
,
3591 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3596 void radv_GetImageSparseMemoryRequirements2(
3598 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
3599 uint32_t* pSparseMemoryRequirementCount
,
3600 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
3605 void radv_GetDeviceMemoryCommitment(
3607 VkDeviceMemory memory
,
3608 VkDeviceSize
* pCommittedMemoryInBytes
)
3610 *pCommittedMemoryInBytes
= 0;
3613 VkResult
radv_BindBufferMemory2(VkDevice device
,
3614 uint32_t bindInfoCount
,
3615 const VkBindBufferMemoryInfo
*pBindInfos
)
3617 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3618 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3619 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3622 buffer
->bo
= mem
->bo
;
3623 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3631 VkResult
radv_BindBufferMemory(
3634 VkDeviceMemory memory
,
3635 VkDeviceSize memoryOffset
)
3637 const VkBindBufferMemoryInfo info
= {
3638 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3641 .memoryOffset
= memoryOffset
3644 return radv_BindBufferMemory2(device
, 1, &info
);
3647 VkResult
radv_BindImageMemory2(VkDevice device
,
3648 uint32_t bindInfoCount
,
3649 const VkBindImageMemoryInfo
*pBindInfos
)
3651 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3652 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3653 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3656 image
->bo
= mem
->bo
;
3657 image
->offset
= pBindInfos
[i
].memoryOffset
;
3667 VkResult
radv_BindImageMemory(
3670 VkDeviceMemory memory
,
3671 VkDeviceSize memoryOffset
)
3673 const VkBindImageMemoryInfo info
= {
3674 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
3677 .memoryOffset
= memoryOffset
3680 return radv_BindImageMemory2(device
, 1, &info
);
3685 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3686 const VkSparseBufferMemoryBindInfo
*bind
)
3688 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3690 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3691 struct radv_device_memory
*mem
= NULL
;
3693 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3694 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3696 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3697 bind
->pBinds
[i
].resourceOffset
,
3698 bind
->pBinds
[i
].size
,
3699 mem
? mem
->bo
: NULL
,
3700 bind
->pBinds
[i
].memoryOffset
);
3705 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3706 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3708 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3710 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3711 struct radv_device_memory
*mem
= NULL
;
3713 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3714 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3716 device
->ws
->buffer_virtual_bind(image
->bo
,
3717 bind
->pBinds
[i
].resourceOffset
,
3718 bind
->pBinds
[i
].size
,
3719 mem
? mem
->bo
: NULL
,
3720 bind
->pBinds
[i
].memoryOffset
);
3724 VkResult
radv_QueueBindSparse(
3726 uint32_t bindInfoCount
,
3727 const VkBindSparseInfo
* pBindInfo
,
3730 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3731 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3732 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3733 bool fence_emitted
= false;
3737 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3738 struct radv_winsys_sem_info sem_info
;
3739 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3740 radv_sparse_buffer_bind_memory(queue
->device
,
3741 pBindInfo
[i
].pBufferBinds
+ j
);
3744 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3745 radv_sparse_image_opaque_bind_memory(queue
->device
,
3746 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3750 result
= radv_alloc_sem_info(queue
->device
->instance
,
3752 pBindInfo
[i
].waitSemaphoreCount
,
3753 pBindInfo
[i
].pWaitSemaphores
,
3754 pBindInfo
[i
].signalSemaphoreCount
,
3755 pBindInfo
[i
].pSignalSemaphores
,
3757 if (result
!= VK_SUCCESS
)
3760 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3761 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3762 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3767 radv_loge("failed to submit CS %d\n", i
);
3771 fence_emitted
= true;
3774 radv_free_sem_info(&sem_info
);
3779 if (!fence_emitted
) {
3780 result
= radv_signal_fence(queue
, fence
);
3781 if (result
!= VK_SUCCESS
)
3789 VkResult
radv_CreateFence(
3791 const VkFenceCreateInfo
* pCreateInfo
,
3792 const VkAllocationCallbacks
* pAllocator
,
3795 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3796 const VkExportFenceCreateInfo
*export
=
3797 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
3798 VkExternalFenceHandleTypeFlags handleTypes
=
3799 export
? export
->handleTypes
: 0;
3801 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3803 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3806 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3808 fence
->fence_wsi
= NULL
;
3809 fence
->temp_syncobj
= 0;
3810 if (device
->always_use_syncobj
|| handleTypes
) {
3811 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3813 vk_free2(&device
->alloc
, pAllocator
, fence
);
3814 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3816 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3817 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3819 fence
->fence
= NULL
;
3821 fence
->fence
= device
->ws
->create_fence();
3822 if (!fence
->fence
) {
3823 vk_free2(&device
->alloc
, pAllocator
, fence
);
3824 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3827 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
3828 device
->ws
->signal_fence(fence
->fence
);
3831 *pFence
= radv_fence_to_handle(fence
);
3836 void radv_DestroyFence(
3839 const VkAllocationCallbacks
* pAllocator
)
3841 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3842 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3847 if (fence
->temp_syncobj
)
3848 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3850 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3852 device
->ws
->destroy_fence(fence
->fence
);
3853 if (fence
->fence_wsi
)
3854 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3855 vk_free2(&device
->alloc
, pAllocator
, fence
);
3859 uint64_t radv_get_current_time(void)
3862 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3863 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3866 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3868 uint64_t current_time
= radv_get_current_time();
3870 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3872 return current_time
+ timeout
;
3876 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
3877 uint32_t fenceCount
, const VkFence
*pFences
)
3879 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3880 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3881 if (fence
->fence
== NULL
|| fence
->syncobj
||
3882 fence
->temp_syncobj
|| fence
->fence_wsi
||
3883 (!device
->ws
->is_fence_waitable(fence
->fence
)))
3889 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3891 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3892 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3893 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3899 VkResult
radv_WaitForFences(
3901 uint32_t fenceCount
,
3902 const VkFence
* pFences
,
3906 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3907 timeout
= radv_get_absolute_timeout(timeout
);
3909 if (device
->always_use_syncobj
&&
3910 radv_all_fences_syncobj(fenceCount
, pFences
))
3912 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3914 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3916 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3917 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3918 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3921 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3924 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3927 if (!waitAll
&& fenceCount
> 1) {
3928 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3929 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
3930 uint32_t wait_count
= 0;
3931 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3933 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3935 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3936 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3938 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
3943 fences
[wait_count
++] = fence
->fence
;
3946 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3947 waitAll
, timeout
- radv_get_current_time());
3950 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3953 while(radv_get_current_time() <= timeout
) {
3954 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3955 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3962 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3963 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3964 bool expired
= false;
3966 if (fence
->temp_syncobj
) {
3967 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3972 if (fence
->syncobj
) {
3973 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3979 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
3980 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
3981 radv_get_current_time() <= timeout
)
3985 expired
= device
->ws
->fence_wait(device
->ws
,
3992 if (fence
->fence_wsi
) {
3993 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3994 if (result
!= VK_SUCCESS
)
4002 VkResult
radv_ResetFences(VkDevice _device
,
4003 uint32_t fenceCount
,
4004 const VkFence
*pFences
)
4006 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4008 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
4009 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4011 device
->ws
->reset_fence(fence
->fence
);
4013 /* Per spec, we first restore the permanent payload, and then reset, so
4014 * having a temp syncobj should not skip resetting the permanent syncobj. */
4015 if (fence
->temp_syncobj
) {
4016 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4017 fence
->temp_syncobj
= 0;
4020 if (fence
->syncobj
) {
4021 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
4028 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
4030 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4031 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4033 if (fence
->temp_syncobj
) {
4034 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
4035 return success
? VK_SUCCESS
: VK_NOT_READY
;
4038 if (fence
->syncobj
) {
4039 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
4040 return success
? VK_SUCCESS
: VK_NOT_READY
;
4044 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
4045 return VK_NOT_READY
;
4047 if (fence
->fence_wsi
) {
4048 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
4050 if (result
!= VK_SUCCESS
) {
4051 if (result
== VK_TIMEOUT
)
4052 return VK_NOT_READY
;
4060 // Queue semaphore functions
4062 VkResult
radv_CreateSemaphore(
4064 const VkSemaphoreCreateInfo
* pCreateInfo
,
4065 const VkAllocationCallbacks
* pAllocator
,
4066 VkSemaphore
* pSemaphore
)
4068 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4069 const VkExportSemaphoreCreateInfo
*export
=
4070 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4071 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4072 export
? export
->handleTypes
: 0;
4074 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4076 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4078 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4080 sem
->temp_syncobj
= 0;
4081 /* create a syncobject if we are going to export this semaphore */
4082 if (device
->always_use_syncobj
|| handleTypes
) {
4083 assert (device
->physical_device
->rad_info
.has_syncobj
);
4084 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4086 vk_free2(&device
->alloc
, pAllocator
, sem
);
4087 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4091 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4093 vk_free2(&device
->alloc
, pAllocator
, sem
);
4094 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4099 *pSemaphore
= radv_semaphore_to_handle(sem
);
4103 void radv_DestroySemaphore(
4105 VkSemaphore _semaphore
,
4106 const VkAllocationCallbacks
* pAllocator
)
4108 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4109 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4114 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4116 device
->ws
->destroy_sem(sem
->sem
);
4117 vk_free2(&device
->alloc
, pAllocator
, sem
);
4120 VkResult
radv_CreateEvent(
4122 const VkEventCreateInfo
* pCreateInfo
,
4123 const VkAllocationCallbacks
* pAllocator
,
4126 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4127 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4129 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4132 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4134 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4136 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4137 RADV_BO_PRIORITY_FENCE
);
4139 vk_free2(&device
->alloc
, pAllocator
, event
);
4140 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4143 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4145 *pEvent
= radv_event_to_handle(event
);
4150 void radv_DestroyEvent(
4153 const VkAllocationCallbacks
* pAllocator
)
4155 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4156 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4160 device
->ws
->buffer_destroy(event
->bo
);
4161 vk_free2(&device
->alloc
, pAllocator
, event
);
4164 VkResult
radv_GetEventStatus(
4168 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4170 if (*event
->map
== 1)
4171 return VK_EVENT_SET
;
4172 return VK_EVENT_RESET
;
4175 VkResult
radv_SetEvent(
4179 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4185 VkResult
radv_ResetEvent(
4189 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4195 VkResult
radv_CreateBuffer(
4197 const VkBufferCreateInfo
* pCreateInfo
,
4198 const VkAllocationCallbacks
* pAllocator
,
4201 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4202 struct radv_buffer
*buffer
;
4204 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4206 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4207 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4209 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4211 buffer
->size
= pCreateInfo
->size
;
4212 buffer
->usage
= pCreateInfo
->usage
;
4215 buffer
->flags
= pCreateInfo
->flags
;
4217 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4218 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4220 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4221 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4222 align64(buffer
->size
, 4096),
4223 4096, 0, RADEON_FLAG_VIRTUAL
,
4224 RADV_BO_PRIORITY_VIRTUAL
);
4226 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4227 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4231 *pBuffer
= radv_buffer_to_handle(buffer
);
4236 void radv_DestroyBuffer(
4239 const VkAllocationCallbacks
* pAllocator
)
4241 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4242 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4247 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4248 device
->ws
->buffer_destroy(buffer
->bo
);
4250 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4253 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4255 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4257 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4258 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4262 static inline unsigned
4263 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4266 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4268 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4271 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4273 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4277 radv_init_dcc_control_reg(struct radv_device
*device
,
4278 struct radv_image_view
*iview
)
4280 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4281 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4282 unsigned max_compressed_block_size
;
4283 unsigned independent_128b_blocks
;
4284 unsigned independent_64b_blocks
;
4286 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4289 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4290 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4291 * dGPU and 64 for APU because all of our APUs to date use
4292 * DIMMs which have a request granularity size of 64B while all
4293 * other chips have a 32B request size.
4295 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4298 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4299 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4300 independent_64b_blocks
= 0;
4301 independent_128b_blocks
= 1;
4303 independent_128b_blocks
= 0;
4305 if (iview
->image
->info
.samples
> 1) {
4306 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4307 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4308 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4309 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4312 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4313 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4314 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4315 /* If this DCC image is potentially going to be used in texture
4316 * fetches, we need some special settings.
4318 independent_64b_blocks
= 1;
4319 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4321 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4322 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4323 * big as possible for better compression state.
4325 independent_64b_blocks
= 0;
4326 max_compressed_block_size
= max_uncompressed_block_size
;
4330 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4331 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4332 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4333 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
4334 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
4338 radv_initialise_color_surface(struct radv_device
*device
,
4339 struct radv_color_buffer_info
*cb
,
4340 struct radv_image_view
*iview
)
4342 const struct vk_format_description
*desc
;
4343 unsigned ntype
, format
, swap
, endian
;
4344 unsigned blend_clamp
= 0, blend_bypass
= 0;
4346 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4347 const struct radeon_surf
*surf
= &plane
->surface
;
4349 desc
= vk_format_description(iview
->vk_format
);
4351 memset(cb
, 0, sizeof(*cb
));
4353 /* Intensity is implemented as Red, so treat it that way. */
4354 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4356 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4358 cb
->cb_color_base
= va
>> 8;
4360 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4361 struct gfx9_surf_meta_flags meta
;
4362 if (iview
->image
->dcc_offset
)
4363 meta
= surf
->u
.gfx9
.dcc
;
4365 meta
= surf
->u
.gfx9
.cmask
;
4367 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4368 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4369 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4370 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
4371 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
4373 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4374 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
4375 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4376 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4377 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4380 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
4381 cb
->cb_color_base
|= surf
->tile_swizzle
;
4383 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4384 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4386 cb
->cb_color_base
+= level_info
->offset
>> 8;
4387 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4388 cb
->cb_color_base
|= surf
->tile_swizzle
;
4390 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4391 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4392 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
4394 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4395 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4396 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4398 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4400 if (radv_image_has_fmask(iview
->image
)) {
4401 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4402 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4403 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4404 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4406 /* This must be set for fast clear to work without FMASK. */
4407 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4408 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4409 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4410 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4414 /* CMASK variables */
4415 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4416 va
+= iview
->image
->cmask
.offset
;
4417 cb
->cb_color_cmask
= va
>> 8;
4419 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4420 va
+= iview
->image
->dcc_offset
;
4422 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
4423 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4424 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
4426 cb
->cb_dcc_base
= va
>> 8;
4427 cb
->cb_dcc_base
|= surf
->tile_swizzle
;
4429 /* GFX10 field has the same base shift as the GFX6 field. */
4430 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4431 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4432 S_028C6C_SLICE_MAX_GFX10(max_slice
);
4434 if (iview
->image
->info
.samples
> 1) {
4435 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4437 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4438 S_028C74_NUM_FRAGMENTS(log_samples
);
4441 if (radv_image_has_fmask(iview
->image
)) {
4442 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4443 cb
->cb_color_fmask
= va
>> 8;
4444 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4446 cb
->cb_color_fmask
= cb
->cb_color_base
;
4449 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4451 vk_format_get_first_non_void_channel(iview
->vk_format
));
4452 format
= radv_translate_colorformat(iview
->vk_format
);
4453 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4454 radv_finishme("Illegal color\n");
4455 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4456 endian
= radv_colorformat_endian_swap(format
);
4458 /* blend clamp should be set for all NORM/SRGB types */
4459 if (ntype
== V_028C70_NUMBER_UNORM
||
4460 ntype
== V_028C70_NUMBER_SNORM
||
4461 ntype
== V_028C70_NUMBER_SRGB
)
4464 /* set blend bypass according to docs if SINT/UINT or
4465 8/24 COLOR variants */
4466 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4467 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4468 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4473 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4474 (format
== V_028C70_COLOR_8
||
4475 format
== V_028C70_COLOR_8_8
||
4476 format
== V_028C70_COLOR_8_8_8_8
))
4477 ->color_is_int8
= true;
4479 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4480 S_028C70_COMP_SWAP(swap
) |
4481 S_028C70_BLEND_CLAMP(blend_clamp
) |
4482 S_028C70_BLEND_BYPASS(blend_bypass
) |
4483 S_028C70_SIMPLE_FLOAT(1) |
4484 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4485 ntype
!= V_028C70_NUMBER_SNORM
&&
4486 ntype
!= V_028C70_NUMBER_SRGB
&&
4487 format
!= V_028C70_COLOR_8_24
&&
4488 format
!= V_028C70_COLOR_24_8
) |
4489 S_028C70_NUMBER_TYPE(ntype
) |
4490 S_028C70_ENDIAN(endian
);
4491 if (radv_image_has_fmask(iview
->image
)) {
4492 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4493 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4494 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4495 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4498 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
4499 /* Allow the texture block to read FMASK directly
4500 * without decompressing it. This bit must be cleared
4501 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4502 * otherwise the operation doesn't happen.
4504 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4506 /* Set CMASK into a tiling format that allows the
4507 * texture block to read it.
4509 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
4513 if (radv_image_has_cmask(iview
->image
) &&
4514 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4515 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4517 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4518 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4520 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4522 /* This must be set for fast clear to work without FMASK. */
4523 if (!radv_image_has_fmask(iview
->image
) &&
4524 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
4525 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
4526 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4529 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4530 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
4532 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4533 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4534 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
4535 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
4537 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4538 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
4540 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
4541 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
4542 S_028EE0_RESOURCE_LEVEL(1);
4544 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
4545 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4546 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
4549 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
4550 S_028C68_MIP0_HEIGHT(height
- 1) |
4551 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4556 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4557 struct radv_image_view
*iview
)
4559 unsigned max_zplanes
= 0;
4561 assert(radv_image_is_tc_compat_htile(iview
->image
));
4563 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4564 /* Default value for 32-bit depth surfaces. */
4567 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4568 iview
->image
->info
.samples
> 1)
4571 max_zplanes
= max_zplanes
+ 1;
4573 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4574 /* Do not enable Z plane compression for 16-bit depth
4575 * surfaces because isn't supported on GFX8. Only
4576 * 32-bit depth surfaces are supported by the hardware.
4577 * This allows to maintain shader compatibility and to
4578 * reduce the number of depth decompressions.
4582 if (iview
->image
->info
.samples
<= 1)
4584 else if (iview
->image
->info
.samples
<= 4)
4595 radv_initialise_ds_surface(struct radv_device
*device
,
4596 struct radv_ds_buffer_info
*ds
,
4597 struct radv_image_view
*iview
)
4599 unsigned level
= iview
->base_mip
;
4600 unsigned format
, stencil_format
;
4601 uint64_t va
, s_offs
, z_offs
;
4602 bool stencil_only
= false;
4603 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
4604 const struct radeon_surf
*surf
= &plane
->surface
;
4606 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
4608 memset(ds
, 0, sizeof(*ds
));
4609 switch (iview
->image
->vk_format
) {
4610 case VK_FORMAT_D24_UNORM_S8_UINT
:
4611 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4612 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4613 ds
->offset_scale
= 2.0f
;
4615 case VK_FORMAT_D16_UNORM
:
4616 case VK_FORMAT_D16_UNORM_S8_UINT
:
4617 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4618 ds
->offset_scale
= 4.0f
;
4620 case VK_FORMAT_D32_SFLOAT
:
4621 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4622 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4623 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4624 ds
->offset_scale
= 1.0f
;
4626 case VK_FORMAT_S8_UINT
:
4627 stencil_only
= true;
4633 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4634 stencil_format
= surf
->has_stencil
?
4635 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4637 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4638 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4639 S_028008_SLICE_MAX(max_slice
);
4640 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4641 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
4642 S_028008_SLICE_MAX_HI(max_slice
>> 11);
4645 ds
->db_htile_data_base
= 0;
4646 ds
->db_htile_surface
= 0;
4648 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4649 s_offs
= z_offs
= va
;
4651 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4652 assert(surf
->u
.gfx9
.surf_offset
== 0);
4653 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
4655 ds
->db_z_info
= S_028038_FORMAT(format
) |
4656 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4657 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
4658 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4659 S_028038_ZRANGE_PRECISION(1);
4660 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4661 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
4663 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4664 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
4665 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
4668 ds
->db_depth_view
|= S_028008_MIPID(level
);
4669 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4670 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4672 if (radv_htile_enabled(iview
->image
, level
)) {
4673 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4675 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4676 unsigned max_zplanes
=
4677 radv_calc_decompress_on_z_planes(device
, iview
);
4679 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4681 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4682 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
4683 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
4685 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
4686 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4690 if (!surf
->has_stencil
)
4691 /* Use all of the htile_buffer for depth if there's no stencil. */
4692 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4693 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4694 iview
->image
->htile_offset
;
4695 ds
->db_htile_data_base
= va
>> 8;
4696 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4697 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
4699 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
4700 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
4704 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
4707 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
4709 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
4710 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
4712 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4713 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4714 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4716 if (iview
->image
->info
.samples
> 1)
4717 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4719 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4720 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4721 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
4722 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
4723 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
4724 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4725 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4726 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4729 tile_mode
= stencil_tile_mode
;
4731 ds
->db_depth_info
|=
4732 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4733 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4734 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4735 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4736 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4737 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4738 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4739 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4741 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
4742 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4743 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
4744 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4746 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4749 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4750 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4751 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4753 if (radv_htile_enabled(iview
->image
, level
)) {
4754 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4756 if (!surf
->has_stencil
&&
4757 !radv_image_is_tc_compat_htile(iview
->image
))
4758 /* Use all of the htile_buffer for depth if there's no stencil. */
4759 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4761 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4762 iview
->image
->htile_offset
;
4763 ds
->db_htile_data_base
= va
>> 8;
4764 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4766 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4767 unsigned max_zplanes
=
4768 radv_calc_decompress_on_z_planes(device
, iview
);
4770 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4771 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4776 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4777 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4780 VkResult
radv_CreateFramebuffer(
4782 const VkFramebufferCreateInfo
* pCreateInfo
,
4783 const VkAllocationCallbacks
* pAllocator
,
4784 VkFramebuffer
* pFramebuffer
)
4786 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4787 struct radv_framebuffer
*framebuffer
;
4789 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4791 size_t size
= sizeof(*framebuffer
) +
4792 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4793 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4794 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4795 if (framebuffer
== NULL
)
4796 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4798 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4799 framebuffer
->width
= pCreateInfo
->width
;
4800 framebuffer
->height
= pCreateInfo
->height
;
4801 framebuffer
->layers
= pCreateInfo
->layers
;
4802 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4803 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4804 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4805 framebuffer
->attachments
[i
].attachment
= iview
;
4806 if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4807 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4809 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4811 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4812 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4813 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4816 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4820 void radv_DestroyFramebuffer(
4823 const VkAllocationCallbacks
* pAllocator
)
4825 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4826 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4830 vk_free2(&device
->alloc
, pAllocator
, fb
);
4833 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4835 switch (address_mode
) {
4836 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4837 return V_008F30_SQ_TEX_WRAP
;
4838 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4839 return V_008F30_SQ_TEX_MIRROR
;
4840 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4841 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4842 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4843 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4844 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4845 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4847 unreachable("illegal tex wrap mode");
4853 radv_tex_compare(VkCompareOp op
)
4856 case VK_COMPARE_OP_NEVER
:
4857 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4858 case VK_COMPARE_OP_LESS
:
4859 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4860 case VK_COMPARE_OP_EQUAL
:
4861 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4862 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4863 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4864 case VK_COMPARE_OP_GREATER
:
4865 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4866 case VK_COMPARE_OP_NOT_EQUAL
:
4867 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4868 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4869 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4870 case VK_COMPARE_OP_ALWAYS
:
4871 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4873 unreachable("illegal compare mode");
4879 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4882 case VK_FILTER_NEAREST
:
4883 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4884 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4885 case VK_FILTER_LINEAR
:
4886 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4887 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4888 case VK_FILTER_CUBIC_IMG
:
4890 fprintf(stderr
, "illegal texture filter");
4896 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4899 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4900 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4901 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4902 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4904 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4909 radv_tex_bordercolor(VkBorderColor bcolor
)
4912 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4913 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4914 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4915 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4916 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4917 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4918 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4919 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4920 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4928 radv_tex_aniso_filter(unsigned filter
)
4942 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4945 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4946 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4947 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4948 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4949 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4950 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4958 radv_get_max_anisotropy(struct radv_device
*device
,
4959 const VkSamplerCreateInfo
*pCreateInfo
)
4961 if (device
->force_aniso
>= 0)
4962 return device
->force_aniso
;
4964 if (pCreateInfo
->anisotropyEnable
&&
4965 pCreateInfo
->maxAnisotropy
> 1.0f
)
4966 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4972 radv_init_sampler(struct radv_device
*device
,
4973 struct radv_sampler
*sampler
,
4974 const VkSamplerCreateInfo
*pCreateInfo
)
4976 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4977 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4978 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
4979 device
->physical_device
->rad_info
.chip_class
== GFX9
;
4980 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4982 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4983 vk_find_struct_const(pCreateInfo
->pNext
,
4984 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4985 if (sampler_reduction
)
4986 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4988 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4989 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4990 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4991 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4992 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4993 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4994 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4995 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4996 S_008F30_DISABLE_CUBE_WRAP(0) |
4997 S_008F30_COMPAT_MODE(compat_mode
) |
4998 S_008F30_FILTER_MODE(filter_mode
));
4999 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
5000 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
5001 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
5002 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
5003 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
5004 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
5005 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
5006 S_008F38_MIP_POINT_PRECLAMP(0));
5007 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5008 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
5010 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5011 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5013 sampler
->state
[2] |=
5014 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
5015 S_008F38_FILTER_PREC_FIX(1) |
5016 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
5020 VkResult
radv_CreateSampler(
5022 const VkSamplerCreateInfo
* pCreateInfo
,
5023 const VkAllocationCallbacks
* pAllocator
,
5024 VkSampler
* pSampler
)
5026 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5027 struct radv_sampler
*sampler
;
5029 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
5030 vk_find_struct_const(pCreateInfo
->pNext
,
5031 SAMPLER_YCBCR_CONVERSION_INFO
);
5033 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
5035 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
5036 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5038 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5040 radv_init_sampler(device
, sampler
, pCreateInfo
);
5042 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
5043 *pSampler
= radv_sampler_to_handle(sampler
);
5048 void radv_DestroySampler(
5051 const VkAllocationCallbacks
* pAllocator
)
5053 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5054 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
5058 vk_free2(&device
->alloc
, pAllocator
, sampler
);
5061 /* vk_icd.h does not declare this function, so we declare it here to
5062 * suppress Wmissing-prototypes.
5064 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5065 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
5067 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5068 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
5070 /* For the full details on loader interface versioning, see
5071 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5072 * What follows is a condensed summary, to help you navigate the large and
5073 * confusing official doc.
5075 * - Loader interface v0 is incompatible with later versions. We don't
5078 * - In loader interface v1:
5079 * - The first ICD entrypoint called by the loader is
5080 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5082 * - The ICD must statically expose no other Vulkan symbol unless it is
5083 * linked with -Bsymbolic.
5084 * - Each dispatchable Vulkan handle created by the ICD must be
5085 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5086 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5087 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5088 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5089 * such loader-managed surfaces.
5091 * - Loader interface v2 differs from v1 in:
5092 * - The first ICD entrypoint called by the loader is
5093 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5094 * statically expose this entrypoint.
5096 * - Loader interface v3 differs from v2 in:
5097 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5098 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5099 * because the loader no longer does so.
5101 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5105 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5106 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5109 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5110 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5112 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5114 /* At the moment, we support only the below handle types. */
5115 assert(pGetFdInfo
->handleType
==
5116 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5117 pGetFdInfo
->handleType
==
5118 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5120 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5122 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5126 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5127 VkExternalMemoryHandleTypeFlagBits handleType
,
5129 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5131 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5133 switch (handleType
) {
5134 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5135 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5139 /* The valid usage section for this function says:
5141 * "handleType must not be one of the handle types defined as
5144 * So opaque handle types fall into the default "unsupported" case.
5146 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5150 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5154 uint32_t syncobj_handle
= 0;
5155 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5157 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5160 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5162 *syncobj
= syncobj_handle
;
5168 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5172 /* If we create a syncobj we do it locally so that if we have an error, we don't
5173 * leave a syncobj in an undetermined state in the fence. */
5174 uint32_t syncobj_handle
= *syncobj
;
5175 if (!syncobj_handle
) {
5176 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5178 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5183 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5185 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5187 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5190 *syncobj
= syncobj_handle
;
5197 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5198 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5200 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5201 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5202 uint32_t *syncobj_dst
= NULL
;
5204 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5205 syncobj_dst
= &sem
->temp_syncobj
;
5207 syncobj_dst
= &sem
->syncobj
;
5210 switch(pImportSemaphoreFdInfo
->handleType
) {
5211 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5212 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5213 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5214 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5216 unreachable("Unhandled semaphore handle type");
5220 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5221 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5224 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5225 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5227 uint32_t syncobj_handle
;
5229 if (sem
->temp_syncobj
)
5230 syncobj_handle
= sem
->temp_syncobj
;
5232 syncobj_handle
= sem
->syncobj
;
5234 switch(pGetFdInfo
->handleType
) {
5235 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5236 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5238 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5239 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5241 if (sem
->temp_syncobj
) {
5242 close (sem
->temp_syncobj
);
5243 sem
->temp_syncobj
= 0;
5245 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5250 unreachable("Unhandled semaphore handle type");
5254 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5258 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5259 VkPhysicalDevice physicalDevice
,
5260 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5261 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5263 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5265 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5266 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5267 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5268 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5269 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5270 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5271 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5272 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5273 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5274 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5275 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5276 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5277 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5279 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5280 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5281 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5285 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5286 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5288 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5289 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5290 uint32_t *syncobj_dst
= NULL
;
5293 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5294 syncobj_dst
= &fence
->temp_syncobj
;
5296 syncobj_dst
= &fence
->syncobj
;
5299 switch(pImportFenceFdInfo
->handleType
) {
5300 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5301 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5302 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5303 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5305 unreachable("Unhandled fence handle type");
5309 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5310 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5313 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5314 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5316 uint32_t syncobj_handle
;
5318 if (fence
->temp_syncobj
)
5319 syncobj_handle
= fence
->temp_syncobj
;
5321 syncobj_handle
= fence
->syncobj
;
5323 switch(pGetFdInfo
->handleType
) {
5324 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5325 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5327 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5328 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5330 if (fence
->temp_syncobj
) {
5331 close (fence
->temp_syncobj
);
5332 fence
->temp_syncobj
= 0;
5334 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5339 unreachable("Unhandled fence handle type");
5343 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5347 void radv_GetPhysicalDeviceExternalFenceProperties(
5348 VkPhysicalDevice physicalDevice
,
5349 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5350 VkExternalFenceProperties
*pExternalFenceProperties
)
5352 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5354 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5355 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5356 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5357 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5358 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
5359 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
5360 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5362 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
5363 pExternalFenceProperties
->compatibleHandleTypes
= 0;
5364 pExternalFenceProperties
->externalFenceFeatures
= 0;
5369 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
5370 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
5371 const VkAllocationCallbacks
* pAllocator
,
5372 VkDebugReportCallbackEXT
* pCallback
)
5374 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5375 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
5376 pCreateInfo
, pAllocator
, &instance
->alloc
,
5381 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
5382 VkDebugReportCallbackEXT _callback
,
5383 const VkAllocationCallbacks
* pAllocator
)
5385 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5386 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
5387 _callback
, pAllocator
, &instance
->alloc
);
5391 radv_DebugReportMessageEXT(VkInstance _instance
,
5392 VkDebugReportFlagsEXT flags
,
5393 VkDebugReportObjectTypeEXT objectType
,
5396 int32_t messageCode
,
5397 const char* pLayerPrefix
,
5398 const char* pMessage
)
5400 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
5401 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
5402 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
5406 radv_GetDeviceGroupPeerMemoryFeatures(
5409 uint32_t localDeviceIndex
,
5410 uint32_t remoteDeviceIndex
,
5411 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
5413 assert(localDeviceIndex
== remoteDeviceIndex
);
5415 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
5416 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
5417 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
5418 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
5421 static const VkTimeDomainEXT radv_time_domains
[] = {
5422 VK_TIME_DOMAIN_DEVICE_EXT
,
5423 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
5424 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
5427 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5428 VkPhysicalDevice physicalDevice
,
5429 uint32_t *pTimeDomainCount
,
5430 VkTimeDomainEXT
*pTimeDomains
)
5433 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5435 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5436 vk_outarray_append(&out
, i
) {
5437 *i
= radv_time_domains
[d
];
5441 return vk_outarray_status(&out
);
5445 radv_clock_gettime(clockid_t clock_id
)
5447 struct timespec current
;
5450 ret
= clock_gettime(clock_id
, ¤t
);
5451 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5452 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5456 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5459 VkResult
radv_GetCalibratedTimestampsEXT(
5461 uint32_t timestampCount
,
5462 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5463 uint64_t *pTimestamps
,
5464 uint64_t *pMaxDeviation
)
5466 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5467 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5469 uint64_t begin
, end
;
5470 uint64_t max_clock_period
= 0;
5472 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5474 for (d
= 0; d
< timestampCount
; d
++) {
5475 switch (pTimestampInfos
[d
].timeDomain
) {
5476 case VK_TIME_DOMAIN_DEVICE_EXT
:
5477 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5479 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5480 max_clock_period
= MAX2(max_clock_period
, device_period
);
5482 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5483 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5484 max_clock_period
= MAX2(max_clock_period
, 1);
5487 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5488 pTimestamps
[d
] = begin
;
5496 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5499 * The maximum deviation is the sum of the interval over which we
5500 * perform the sampling and the maximum period of any sampled
5501 * clock. That's because the maximum skew between any two sampled
5502 * clock edges is when the sampled clock with the largest period is
5503 * sampled at the end of that period but right at the beginning of the
5504 * sampling interval and some other clock is sampled right at the
5505 * begining of its sampling period and right at the end of the
5506 * sampling interval. Let's assume the GPU has the longest clock
5507 * period and that the application is sampling GPU and monotonic:
5510 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5511 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5515 * GPU -----_____-----_____-----_____-----_____
5518 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5519 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5521 * Interval <----------------->
5522 * Deviation <-------------------------->
5526 * m = read(monotonic) 2
5529 * We round the sample interval up by one tick to cover sampling error
5530 * in the interval clock
5533 uint64_t sample_interval
= end
- begin
+ 1;
5535 *pMaxDeviation
= sample_interval
+ max_clock_period
;
5540 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5541 VkPhysicalDevice physicalDevice
,
5542 VkSampleCountFlagBits samples
,
5543 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
5545 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
5546 VK_SAMPLE_COUNT_4_BIT
|
5547 VK_SAMPLE_COUNT_8_BIT
)) {
5548 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
5550 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };