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radv: Disable dfsm by default even on Raven.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include <llvm/Config/llvm-config.h>
33 #include "radv_debug.h"
34 #include "radv_private.h"
35 #include "radv_shader.h"
36 #include "radv_cs.h"
37 #include "util/disk_cache.h"
38 #include "util/strtod.h"
39 #include "vk_util.h"
40 #include <xf86drm.h>
41 #include <amdgpu.h>
42 #include <amdgpu_drm.h>
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "git_sha1.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
118 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
119 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
120 default: chip_string = "AMD RADV unknown"; break;
121 }
122
123 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
124 }
125
126 static uint64_t
127 radv_get_visible_vram_size(struct radv_physical_device *device)
128 {
129 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
130 }
131
132 static uint64_t
133 radv_get_vram_size(struct radv_physical_device *device)
134 {
135 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
136 }
137
138 static void
139 radv_physical_device_init_mem_types(struct radv_physical_device *device)
140 {
141 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
142 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
143 uint64_t vram_size = radv_get_vram_size(device);
144 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
145 device->memory_properties.memoryHeapCount = 0;
146 if (vram_size > 0) {
147 vram_index = device->memory_properties.memoryHeapCount++;
148 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
149 .size = vram_size,
150 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
151 };
152 }
153 if (visible_vram_size) {
154 visible_vram_index = device->memory_properties.memoryHeapCount++;
155 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
156 .size = visible_vram_size,
157 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
158 };
159 }
160 if (device->rad_info.gart_size > 0) {
161 gart_index = device->memory_properties.memoryHeapCount++;
162 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
163 .size = device->rad_info.gart_size,
164 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
165 };
166 }
167
168 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
169 unsigned type_count = 0;
170 if (vram_index >= 0) {
171 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
172 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
173 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
174 .heapIndex = vram_index,
175 };
176 }
177 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
181 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
195 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
196 * as they have identical property flags, and according to the
197 * spec, for types with identical flags, the one with greater
198 * performance must be given a lower index. */
199 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
200 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
201 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
202 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
203 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
204 .heapIndex = gart_index,
205 };
206 }
207 if (gart_index >= 0) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
212 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
213 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
214 .heapIndex = gart_index,
215 };
216 }
217 device->memory_properties.memoryTypeCount = type_count;
218 }
219
220 static void
221 radv_handle_env_var_force_family(struct radv_physical_device *device)
222 {
223 const char *family = getenv("RADV_FORCE_FAMILY");
224 unsigned i;
225
226 if (!family)
227 return;
228
229 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
230 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
231 /* Override family and chip_class. */
232 device->rad_info.family = i;
233
234 if (i >= CHIP_NAVI10)
235 device->rad_info.chip_class = GFX10;
236 else if (i >= CHIP_VEGA10)
237 device->rad_info.chip_class = GFX9;
238 else if (i >= CHIP_TONGA)
239 device->rad_info.chip_class = GFX8;
240 else if (i >= CHIP_BONAIRE)
241 device->rad_info.chip_class = GFX7;
242 else
243 device->rad_info.chip_class = GFX6;
244
245 return;
246 }
247 }
248
249 fprintf(stderr, "radv: Unknown family: %s\n", family);
250 exit(1);
251 }
252
253 static VkResult
254 radv_physical_device_init(struct radv_physical_device *device,
255 struct radv_instance *instance,
256 drmDevicePtr drm_device)
257 {
258 const char *path = drm_device->nodes[DRM_NODE_RENDER];
259 VkResult result;
260 drmVersionPtr version;
261 int fd;
262 int master_fd = -1;
263
264 fd = open(path, O_RDWR | O_CLOEXEC);
265 if (fd < 0) {
266 if (instance->debug_flags & RADV_DEBUG_STARTUP)
267 radv_logi("Could not open device '%s'", path);
268
269 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
270 }
271
272 version = drmGetVersion(fd);
273 if (!version) {
274 close(fd);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Could not get the kernel driver version for device '%s'", path);
278
279 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
280 "failed to get version %s: %m", path);
281 }
282
283 if (strcmp(version->name, "amdgpu")) {
284 drmFreeVersion(version);
285 close(fd);
286
287 if (instance->debug_flags & RADV_DEBUG_STARTUP)
288 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
289
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Found compatible device '%s'.", path);
296
297 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
298 device->instance = instance;
299
300 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
301 instance->perftest_flags);
302 if (!device->ws) {
303 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
304 goto fail;
305 }
306
307 if (instance->enabled_extensions.KHR_display) {
308 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
309 if (master_fd >= 0) {
310 uint32_t accel_working = 0;
311 struct drm_amdgpu_info request = {
312 .return_pointer = (uintptr_t)&accel_working,
313 .return_size = sizeof(accel_working),
314 .query = AMDGPU_INFO_ACCEL_WORKING
315 };
316
317 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
318 close(master_fd);
319 master_fd = -1;
320 }
321 }
322 }
323
324 device->master_fd = master_fd;
325 device->local_fd = fd;
326 device->ws->query_info(device->ws, &device->rad_info);
327
328 radv_handle_env_var_force_family(device);
329
330 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
331
332 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
333 device->ws->destroy(device->ws);
334 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
335 "cannot generate UUID");
336 goto fail;
337 }
338
339 /* These flags affect shader compilation. */
340 uint64_t shader_env_flags =
341 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
342 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
343
344 /* The gpu id is already embedded in the uuid so we just pass "radv"
345 * when creating the cache.
346 */
347 char buf[VK_UUID_SIZE * 2 + 1];
348 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
349 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
350
351 if (device->rad_info.chip_class < GFX8 ||
352 device->rad_info.chip_class > GFX9)
353 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
354
355 radv_get_driver_uuid(&device->driver_uuid);
356 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
357
358 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
359 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
360
361 device->dcc_msaa_allowed =
362 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
363
364 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
365 device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
366
367 device->use_ngg_streamout = false;
368
369 /* Determine the number of threads per wave for all stages. */
370 device->cs_wave_size = 64;
371 device->ps_wave_size = 64;
372 device->ge_wave_size = 64;
373
374 if (device->rad_info.chip_class >= GFX10) {
375 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
376 device->cs_wave_size = 32;
377
378 /* For pixel shaders, wave64 is recommanded. */
379 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
380 device->ps_wave_size = 32;
381
382 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
383 device->ge_wave_size = 32;
384 }
385
386 radv_physical_device_init_mem_types(device);
387 radv_fill_device_extension_table(device, &device->supported_extensions);
388
389 device->bus_info = *drm_device->businfo.pci;
390
391 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
392 ac_print_gpu_info(&device->rad_info);
393
394 /* The WSI is structured as a layer on top of the driver, so this has
395 * to be the last part of initialization (at least until we get other
396 * semi-layers).
397 */
398 result = radv_init_wsi(device);
399 if (result != VK_SUCCESS) {
400 device->ws->destroy(device->ws);
401 vk_error(instance, result);
402 goto fail;
403 }
404
405 return VK_SUCCESS;
406
407 fail:
408 close(fd);
409 if (master_fd != -1)
410 close(master_fd);
411 return result;
412 }
413
414 static void
415 radv_physical_device_finish(struct radv_physical_device *device)
416 {
417 radv_finish_wsi(device);
418 device->ws->destroy(device->ws);
419 disk_cache_destroy(device->disk_cache);
420 close(device->local_fd);
421 if (device->master_fd != -1)
422 close(device->master_fd);
423 }
424
425 static void *
426 default_alloc_func(void *pUserData, size_t size, size_t align,
427 VkSystemAllocationScope allocationScope)
428 {
429 return malloc(size);
430 }
431
432 static void *
433 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
434 size_t align, VkSystemAllocationScope allocationScope)
435 {
436 return realloc(pOriginal, size);
437 }
438
439 static void
440 default_free_func(void *pUserData, void *pMemory)
441 {
442 free(pMemory);
443 }
444
445 static const VkAllocationCallbacks default_alloc = {
446 .pUserData = NULL,
447 .pfnAllocation = default_alloc_func,
448 .pfnReallocation = default_realloc_func,
449 .pfnFree = default_free_func,
450 };
451
452 static const struct debug_control radv_debug_options[] = {
453 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
454 {"nodcc", RADV_DEBUG_NO_DCC},
455 {"shaders", RADV_DEBUG_DUMP_SHADERS},
456 {"nocache", RADV_DEBUG_NO_CACHE},
457 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
458 {"nohiz", RADV_DEBUG_NO_HIZ},
459 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
460 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
461 {"allbos", RADV_DEBUG_ALL_BOS},
462 {"noibs", RADV_DEBUG_NO_IBS},
463 {"spirv", RADV_DEBUG_DUMP_SPIRV},
464 {"vmfaults", RADV_DEBUG_VM_FAULTS},
465 {"zerovram", RADV_DEBUG_ZERO_VRAM},
466 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
467 {"nosisched", RADV_DEBUG_NO_SISCHED},
468 {"preoptir", RADV_DEBUG_PREOPTIR},
469 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
470 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
471 {"info", RADV_DEBUG_INFO},
472 {"errors", RADV_DEBUG_ERRORS},
473 {"startup", RADV_DEBUG_STARTUP},
474 {"checkir", RADV_DEBUG_CHECKIR},
475 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
476 {"nobinning", RADV_DEBUG_NOBINNING},
477 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
478 {"nongg", RADV_DEBUG_NO_NGG},
479 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
480 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
481 {NULL, 0}
482 };
483
484 const char *
485 radv_get_debug_option_name(int id)
486 {
487 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
488 return radv_debug_options[id].string;
489 }
490
491 static const struct debug_control radv_perftest_options[] = {
492 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
493 {"sisched", RADV_PERFTEST_SISCHED},
494 {"localbos", RADV_PERFTEST_LOCAL_BOS},
495 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
496 {"bolist", RADV_PERFTEST_BO_LIST},
497 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
498 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
499 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
500 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
501 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
502 {"dfsm", RADV_PERFTEST_DFSM},
503 {NULL, 0}
504 };
505
506 const char *
507 radv_get_perftest_option_name(int id)
508 {
509 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
510 return radv_perftest_options[id].string;
511 }
512
513 static void
514 radv_handle_per_app_options(struct radv_instance *instance,
515 const VkApplicationInfo *info)
516 {
517 const char *name = info ? info->pApplicationName : NULL;
518
519 if (!name)
520 return;
521
522 if (!strcmp(name, "Talos - Linux - 32bit") ||
523 !strcmp(name, "Talos - Linux - 64bit")) {
524 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
525 /* Force enable LLVM sisched for Talos because it looks
526 * safe and it gives few more FPS.
527 */
528 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
529 }
530 } else if (!strcmp(name, "DOOM_VFR")) {
531 /* Work around a Doom VFR game bug */
532 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
533 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
534 /* Workaround for a WaW hazard when LLVM moves/merges
535 * load/store memory operations.
536 * See https://reviews.llvm.org/D61313
537 */
538 if (LLVM_VERSION_MAJOR < 9)
539 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
540 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
541 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
542 /* Force enable VK_AMD_shader_ballot because it looks
543 * safe and it gives a nice boost (+20% on Vega 56 at
544 * this time).
545 */
546 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
547 }
548 }
549 }
550
551 static int radv_get_instance_extension_index(const char *name)
552 {
553 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
554 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
555 return i;
556 }
557 return -1;
558 }
559
560 static const char radv_dri_options_xml[] =
561 DRI_CONF_BEGIN
562 DRI_CONF_SECTION_PERFORMANCE
563 DRI_CONF_ADAPTIVE_SYNC("true")
564 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
565 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
566 DRI_CONF_SECTION_END
567 DRI_CONF_END;
568
569 static void radv_init_dri_options(struct radv_instance *instance)
570 {
571 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
572 driParseConfigFiles(&instance->dri_options,
573 &instance->available_dri_options,
574 0, "radv", NULL,
575 instance->engineName,
576 instance->engineVersion);
577 }
578
579 VkResult radv_CreateInstance(
580 const VkInstanceCreateInfo* pCreateInfo,
581 const VkAllocationCallbacks* pAllocator,
582 VkInstance* pInstance)
583 {
584 struct radv_instance *instance;
585 VkResult result;
586
587 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
588
589 uint32_t client_version;
590 if (pCreateInfo->pApplicationInfo &&
591 pCreateInfo->pApplicationInfo->apiVersion != 0) {
592 client_version = pCreateInfo->pApplicationInfo->apiVersion;
593 } else {
594 client_version = VK_API_VERSION_1_0;
595 }
596
597 const char *engine_name = NULL;
598 uint32_t engine_version = 0;
599 if (pCreateInfo->pApplicationInfo) {
600 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
601 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
602 }
603
604 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
605 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
606 if (!instance)
607 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
608
609 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
610
611 if (pAllocator)
612 instance->alloc = *pAllocator;
613 else
614 instance->alloc = default_alloc;
615
616 instance->apiVersion = client_version;
617 instance->physicalDeviceCount = -1;
618
619 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
620 radv_debug_options);
621
622 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
623 radv_perftest_options);
624
625
626 if (instance->debug_flags & RADV_DEBUG_STARTUP)
627 radv_logi("Created an instance");
628
629 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
630 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
631 int index = radv_get_instance_extension_index(ext_name);
632
633 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
634 vk_free2(&default_alloc, pAllocator, instance);
635 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
636 }
637
638 instance->enabled_extensions.extensions[index] = true;
639 }
640
641 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
642 if (result != VK_SUCCESS) {
643 vk_free2(&default_alloc, pAllocator, instance);
644 return vk_error(instance, result);
645 }
646
647 instance->engineName = vk_strdup(&instance->alloc, engine_name,
648 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
649 instance->engineVersion = engine_version;
650
651 _mesa_locale_init();
652 glsl_type_singleton_init_or_ref();
653
654 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
655
656 radv_init_dri_options(instance);
657 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
658
659 *pInstance = radv_instance_to_handle(instance);
660
661 return VK_SUCCESS;
662 }
663
664 void radv_DestroyInstance(
665 VkInstance _instance,
666 const VkAllocationCallbacks* pAllocator)
667 {
668 RADV_FROM_HANDLE(radv_instance, instance, _instance);
669
670 if (!instance)
671 return;
672
673 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
674 radv_physical_device_finish(instance->physicalDevices + i);
675 }
676
677 vk_free(&instance->alloc, instance->engineName);
678
679 VG(VALGRIND_DESTROY_MEMPOOL(instance));
680
681 glsl_type_singleton_decref();
682 _mesa_locale_fini();
683
684 driDestroyOptionCache(&instance->dri_options);
685 driDestroyOptionInfo(&instance->available_dri_options);
686
687 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
688
689 vk_free(&instance->alloc, instance);
690 }
691
692 static VkResult
693 radv_enumerate_devices(struct radv_instance *instance)
694 {
695 /* TODO: Check for more devices ? */
696 drmDevicePtr devices[8];
697 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
698 int max_devices;
699
700 instance->physicalDeviceCount = 0;
701
702 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
703
704 if (instance->debug_flags & RADV_DEBUG_STARTUP)
705 radv_logi("Found %d drm nodes", max_devices);
706
707 if (max_devices < 1)
708 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
709
710 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
711 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
712 devices[i]->bustype == DRM_BUS_PCI &&
713 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
714
715 result = radv_physical_device_init(instance->physicalDevices +
716 instance->physicalDeviceCount,
717 instance,
718 devices[i]);
719 if (result == VK_SUCCESS)
720 ++instance->physicalDeviceCount;
721 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
722 break;
723 }
724 }
725 drmFreeDevices(devices, max_devices);
726
727 return result;
728 }
729
730 VkResult radv_EnumeratePhysicalDevices(
731 VkInstance _instance,
732 uint32_t* pPhysicalDeviceCount,
733 VkPhysicalDevice* pPhysicalDevices)
734 {
735 RADV_FROM_HANDLE(radv_instance, instance, _instance);
736 VkResult result;
737
738 if (instance->physicalDeviceCount < 0) {
739 result = radv_enumerate_devices(instance);
740 if (result != VK_SUCCESS &&
741 result != VK_ERROR_INCOMPATIBLE_DRIVER)
742 return result;
743 }
744
745 if (!pPhysicalDevices) {
746 *pPhysicalDeviceCount = instance->physicalDeviceCount;
747 } else {
748 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
749 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
750 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
751 }
752
753 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
754 : VK_SUCCESS;
755 }
756
757 VkResult radv_EnumeratePhysicalDeviceGroups(
758 VkInstance _instance,
759 uint32_t* pPhysicalDeviceGroupCount,
760 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
761 {
762 RADV_FROM_HANDLE(radv_instance, instance, _instance);
763 VkResult result;
764
765 if (instance->physicalDeviceCount < 0) {
766 result = radv_enumerate_devices(instance);
767 if (result != VK_SUCCESS &&
768 result != VK_ERROR_INCOMPATIBLE_DRIVER)
769 return result;
770 }
771
772 if (!pPhysicalDeviceGroupProperties) {
773 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
774 } else {
775 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
776 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
777 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
778 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
779 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
780 }
781 }
782 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
783 : VK_SUCCESS;
784 }
785
786 void radv_GetPhysicalDeviceFeatures(
787 VkPhysicalDevice physicalDevice,
788 VkPhysicalDeviceFeatures* pFeatures)
789 {
790 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
791 memset(pFeatures, 0, sizeof(*pFeatures));
792
793 *pFeatures = (VkPhysicalDeviceFeatures) {
794 .robustBufferAccess = true,
795 .fullDrawIndexUint32 = true,
796 .imageCubeArray = true,
797 .independentBlend = true,
798 .geometryShader = true,
799 .tessellationShader = true,
800 .sampleRateShading = true,
801 .dualSrcBlend = true,
802 .logicOp = true,
803 .multiDrawIndirect = true,
804 .drawIndirectFirstInstance = true,
805 .depthClamp = true,
806 .depthBiasClamp = true,
807 .fillModeNonSolid = true,
808 .depthBounds = true,
809 .wideLines = true,
810 .largePoints = true,
811 .alphaToOne = true,
812 .multiViewport = true,
813 .samplerAnisotropy = true,
814 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
815 .textureCompressionASTC_LDR = false,
816 .textureCompressionBC = true,
817 .occlusionQueryPrecise = true,
818 .pipelineStatisticsQuery = true,
819 .vertexPipelineStoresAndAtomics = true,
820 .fragmentStoresAndAtomics = true,
821 .shaderTessellationAndGeometryPointSize = true,
822 .shaderImageGatherExtended = true,
823 .shaderStorageImageExtendedFormats = true,
824 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
825 .shaderUniformBufferArrayDynamicIndexing = true,
826 .shaderSampledImageArrayDynamicIndexing = true,
827 .shaderStorageBufferArrayDynamicIndexing = true,
828 .shaderStorageImageArrayDynamicIndexing = true,
829 .shaderStorageImageReadWithoutFormat = true,
830 .shaderStorageImageWriteWithoutFormat = true,
831 .shaderClipDistance = true,
832 .shaderCullDistance = true,
833 .shaderFloat64 = true,
834 .shaderInt64 = true,
835 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
836 .sparseBinding = true,
837 .variableMultisampleRate = true,
838 .inheritedQueries = true,
839 };
840 }
841
842 void radv_GetPhysicalDeviceFeatures2(
843 VkPhysicalDevice physicalDevice,
844 VkPhysicalDeviceFeatures2 *pFeatures)
845 {
846 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
847 vk_foreach_struct(ext, pFeatures->pNext) {
848 switch (ext->sType) {
849 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
850 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
851 features->variablePointersStorageBuffer = true;
852 features->variablePointers = true;
853 break;
854 }
855 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
856 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
857 features->multiview = true;
858 features->multiviewGeometryShader = true;
859 features->multiviewTessellationShader = true;
860 break;
861 }
862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
863 VkPhysicalDeviceShaderDrawParametersFeatures *features =
864 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
865 features->shaderDrawParameters = true;
866 break;
867 }
868 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
869 VkPhysicalDeviceProtectedMemoryFeatures *features =
870 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
871 features->protectedMemory = false;
872 break;
873 }
874 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
875 VkPhysicalDevice16BitStorageFeatures *features =
876 (VkPhysicalDevice16BitStorageFeatures*)ext;
877 bool enabled = pdevice->rad_info.chip_class >= GFX8;
878 features->storageBuffer16BitAccess = enabled;
879 features->uniformAndStorageBuffer16BitAccess = enabled;
880 features->storagePushConstant16 = enabled;
881 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
885 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
886 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
887 features->samplerYcbcrConversion = true;
888 break;
889 }
890 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
891 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
892 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
893 features->shaderInputAttachmentArrayDynamicIndexing = true;
894 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
895 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
896 features->shaderUniformBufferArrayNonUniformIndexing = true;
897 features->shaderSampledImageArrayNonUniformIndexing = true;
898 features->shaderStorageBufferArrayNonUniformIndexing = true;
899 features->shaderStorageImageArrayNonUniformIndexing = true;
900 features->shaderInputAttachmentArrayNonUniformIndexing = true;
901 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
902 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
903 features->descriptorBindingUniformBufferUpdateAfterBind = true;
904 features->descriptorBindingSampledImageUpdateAfterBind = true;
905 features->descriptorBindingStorageImageUpdateAfterBind = true;
906 features->descriptorBindingStorageBufferUpdateAfterBind = true;
907 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
908 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
909 features->descriptorBindingUpdateUnusedWhilePending = true;
910 features->descriptorBindingPartiallyBound = true;
911 features->descriptorBindingVariableDescriptorCount = true;
912 features->runtimeDescriptorArray = true;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
916 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
917 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
918 features->conditionalRendering = true;
919 features->inheritedConditionalRendering = false;
920 break;
921 }
922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
923 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
924 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
925 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
926 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
927 break;
928 }
929 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
930 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
931 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
932 features->transformFeedback = true;
933 features->geometryStreams = !pdevice->use_ngg_streamout;
934 break;
935 }
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
937 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
938 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
939 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
943 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
944 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
945 features->memoryPriority = VK_TRUE;
946 break;
947 }
948 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
949 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
950 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
951 features->bufferDeviceAddress = true;
952 features->bufferDeviceAddressCaptureReplay = false;
953 features->bufferDeviceAddressMultiDevice = false;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
957 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
958 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
959 features->depthClipEnable = true;
960 break;
961 }
962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
963 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
964 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
965 features->hostQueryReset = true;
966 break;
967 }
968 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
969 VkPhysicalDevice8BitStorageFeaturesKHR *features =
970 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
971 bool enabled = pdevice->rad_info.chip_class >= GFX8;
972 features->storageBuffer8BitAccess = enabled;
973 features->uniformAndStorageBuffer8BitAccess = enabled;
974 features->storagePushConstant8 = enabled;
975 break;
976 }
977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
978 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
979 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
980 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8;
981 features->shaderInt8 = true;
982 break;
983 }
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
985 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
986 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
987 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
988 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
989 break;
990 }
991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
992 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
993 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
994
995 features->inlineUniformBlock = true;
996 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1000 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1001 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1002 features->computeDerivativeGroupQuads = false;
1003 features->computeDerivativeGroupLinear = true;
1004 break;
1005 }
1006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1007 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1008 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1009 features->ycbcrImageArrays = true;
1010 break;
1011 }
1012 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1013 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1014 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1015 features->uniformBufferStandardLayout = true;
1016 break;
1017 }
1018 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1019 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1020 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1021 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1022 break;
1023 }
1024 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1025 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1026 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1027 features->imagelessFramebuffer = true;
1028 break;
1029 }
1030 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1031 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1032 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1033 features->pipelineExecutableInfo = true;
1034 break;
1035 }
1036 default:
1037 break;
1038 }
1039 }
1040 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1041 }
1042
1043 void radv_GetPhysicalDeviceProperties(
1044 VkPhysicalDevice physicalDevice,
1045 VkPhysicalDeviceProperties* pProperties)
1046 {
1047 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1048 VkSampleCountFlags sample_counts = 0xf;
1049
1050 /* make sure that the entire descriptor set is addressable with a signed
1051 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1052 * be at most 2 GiB. the combined image & samples object count as one of
1053 * both. This limit is for the pipeline layout, not for the set layout, but
1054 * there is no set limit, so we just set a pipeline limit. I don't think
1055 * any app is going to hit this soon. */
1056 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1057 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1058 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1059 32 /* sampler, largest when combined with image */ +
1060 64 /* sampled image */ +
1061 64 /* storage image */);
1062
1063 VkPhysicalDeviceLimits limits = {
1064 .maxImageDimension1D = (1 << 14),
1065 .maxImageDimension2D = (1 << 14),
1066 .maxImageDimension3D = (1 << 11),
1067 .maxImageDimensionCube = (1 << 14),
1068 .maxImageArrayLayers = (1 << 11),
1069 .maxTexelBufferElements = 128 * 1024 * 1024,
1070 .maxUniformBufferRange = UINT32_MAX,
1071 .maxStorageBufferRange = UINT32_MAX,
1072 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1073 .maxMemoryAllocationCount = UINT32_MAX,
1074 .maxSamplerAllocationCount = 64 * 1024,
1075 .bufferImageGranularity = 64, /* A cache line */
1076 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1077 .maxBoundDescriptorSets = MAX_SETS,
1078 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1079 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1080 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1081 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1082 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1083 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1084 .maxPerStageResources = max_descriptor_set_size,
1085 .maxDescriptorSetSamplers = max_descriptor_set_size,
1086 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1087 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1088 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1089 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1090 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1091 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1092 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1093 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1094 .maxVertexInputBindings = MAX_VBS,
1095 .maxVertexInputAttributeOffset = 2047,
1096 .maxVertexInputBindingStride = 2048,
1097 .maxVertexOutputComponents = 128,
1098 .maxTessellationGenerationLevel = 64,
1099 .maxTessellationPatchSize = 32,
1100 .maxTessellationControlPerVertexInputComponents = 128,
1101 .maxTessellationControlPerVertexOutputComponents = 128,
1102 .maxTessellationControlPerPatchOutputComponents = 120,
1103 .maxTessellationControlTotalOutputComponents = 4096,
1104 .maxTessellationEvaluationInputComponents = 128,
1105 .maxTessellationEvaluationOutputComponents = 128,
1106 .maxGeometryShaderInvocations = 127,
1107 .maxGeometryInputComponents = 64,
1108 .maxGeometryOutputComponents = 128,
1109 .maxGeometryOutputVertices = 256,
1110 .maxGeometryTotalOutputComponents = 1024,
1111 .maxFragmentInputComponents = 128,
1112 .maxFragmentOutputAttachments = 8,
1113 .maxFragmentDualSrcAttachments = 1,
1114 .maxFragmentCombinedOutputResources = 8,
1115 .maxComputeSharedMemorySize = 32768,
1116 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1117 .maxComputeWorkGroupInvocations = 2048,
1118 .maxComputeWorkGroupSize = {
1119 2048,
1120 2048,
1121 2048
1122 },
1123 .subPixelPrecisionBits = 8,
1124 .subTexelPrecisionBits = 8,
1125 .mipmapPrecisionBits = 8,
1126 .maxDrawIndexedIndexValue = UINT32_MAX,
1127 .maxDrawIndirectCount = UINT32_MAX,
1128 .maxSamplerLodBias = 16,
1129 .maxSamplerAnisotropy = 16,
1130 .maxViewports = MAX_VIEWPORTS,
1131 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1132 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1133 .viewportSubPixelBits = 8,
1134 .minMemoryMapAlignment = 4096, /* A page */
1135 .minTexelBufferOffsetAlignment = 1,
1136 .minUniformBufferOffsetAlignment = 4,
1137 .minStorageBufferOffsetAlignment = 4,
1138 .minTexelOffset = -32,
1139 .maxTexelOffset = 31,
1140 .minTexelGatherOffset = -32,
1141 .maxTexelGatherOffset = 31,
1142 .minInterpolationOffset = -2,
1143 .maxInterpolationOffset = 2,
1144 .subPixelInterpolationOffsetBits = 8,
1145 .maxFramebufferWidth = (1 << 14),
1146 .maxFramebufferHeight = (1 << 14),
1147 .maxFramebufferLayers = (1 << 10),
1148 .framebufferColorSampleCounts = sample_counts,
1149 .framebufferDepthSampleCounts = sample_counts,
1150 .framebufferStencilSampleCounts = sample_counts,
1151 .framebufferNoAttachmentsSampleCounts = sample_counts,
1152 .maxColorAttachments = MAX_RTS,
1153 .sampledImageColorSampleCounts = sample_counts,
1154 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1155 .sampledImageDepthSampleCounts = sample_counts,
1156 .sampledImageStencilSampleCounts = sample_counts,
1157 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1158 .maxSampleMaskWords = 1,
1159 .timestampComputeAndGraphics = true,
1160 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1161 .maxClipDistances = 8,
1162 .maxCullDistances = 8,
1163 .maxCombinedClipAndCullDistances = 8,
1164 .discreteQueuePriorities = 2,
1165 .pointSizeRange = { 0.0, 8192.0 },
1166 .lineWidthRange = { 0.0, 7.9921875 },
1167 .pointSizeGranularity = (1.0 / 8.0),
1168 .lineWidthGranularity = (1.0 / 128.0),
1169 .strictLines = false, /* FINISHME */
1170 .standardSampleLocations = true,
1171 .optimalBufferCopyOffsetAlignment = 128,
1172 .optimalBufferCopyRowPitchAlignment = 128,
1173 .nonCoherentAtomSize = 64,
1174 };
1175
1176 *pProperties = (VkPhysicalDeviceProperties) {
1177 .apiVersion = radv_physical_device_api_version(pdevice),
1178 .driverVersion = vk_get_driver_version(),
1179 .vendorID = ATI_VENDOR_ID,
1180 .deviceID = pdevice->rad_info.pci_id,
1181 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1182 .limits = limits,
1183 .sparseProperties = {0},
1184 };
1185
1186 strcpy(pProperties->deviceName, pdevice->name);
1187 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1188 }
1189
1190 void radv_GetPhysicalDeviceProperties2(
1191 VkPhysicalDevice physicalDevice,
1192 VkPhysicalDeviceProperties2 *pProperties)
1193 {
1194 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1195 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1196
1197 vk_foreach_struct(ext, pProperties->pNext) {
1198 switch (ext->sType) {
1199 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1200 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1201 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1202 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1203 break;
1204 }
1205 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1206 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1207 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1208 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1209 properties->deviceLUIDValid = false;
1210 break;
1211 }
1212 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1213 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1214 properties->maxMultiviewViewCount = MAX_VIEWS;
1215 properties->maxMultiviewInstanceIndex = INT_MAX;
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1219 VkPhysicalDevicePointClippingProperties *properties =
1220 (VkPhysicalDevicePointClippingProperties*)ext;
1221 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1222 break;
1223 }
1224 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1225 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1226 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1227 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1228 break;
1229 }
1230 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1231 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1232 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1233 properties->minImportedHostPointerAlignment = 4096;
1234 break;
1235 }
1236 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1237 VkPhysicalDeviceSubgroupProperties *properties =
1238 (VkPhysicalDeviceSubgroupProperties*)ext;
1239 properties->subgroupSize = 64;
1240 properties->supportedStages = VK_SHADER_STAGE_ALL;
1241 properties->supportedOperations =
1242 VK_SUBGROUP_FEATURE_BASIC_BIT |
1243 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1244 VK_SUBGROUP_FEATURE_QUAD_BIT |
1245 VK_SUBGROUP_FEATURE_VOTE_BIT;
1246 if (pdevice->rad_info.chip_class >= GFX8) {
1247 properties->supportedOperations |=
1248 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1249 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1250 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1251 }
1252 properties->quadOperationsInAllStages = true;
1253 break;
1254 }
1255 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1256 VkPhysicalDeviceMaintenance3Properties *properties =
1257 (VkPhysicalDeviceMaintenance3Properties*)ext;
1258 /* Make sure everything is addressable by a signed 32-bit int, and
1259 * our largest descriptors are 96 bytes. */
1260 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1261 /* Our buffer size fields allow only this much */
1262 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1266 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1267 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1268 /* GFX6-8 only support single channel min/max filter. */
1269 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1270 properties->filterMinmaxSingleComponentFormats = true;
1271 break;
1272 }
1273 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1274 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1275 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1276
1277 /* Shader engines. */
1278 properties->shaderEngineCount =
1279 pdevice->rad_info.max_se;
1280 properties->shaderArraysPerEngineCount =
1281 pdevice->rad_info.max_sh_per_se;
1282 properties->computeUnitsPerShaderArray =
1283 pdevice->rad_info.num_good_cu_per_sh;
1284 properties->simdPerComputeUnit = 4;
1285 properties->wavefrontsPerSimd =
1286 pdevice->rad_info.family == CHIP_TONGA ||
1287 pdevice->rad_info.family == CHIP_ICELAND ||
1288 pdevice->rad_info.family == CHIP_POLARIS10 ||
1289 pdevice->rad_info.family == CHIP_POLARIS11 ||
1290 pdevice->rad_info.family == CHIP_POLARIS12 ||
1291 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1292 properties->wavefrontSize = 64;
1293
1294 /* SGPR. */
1295 properties->sgprsPerSimd =
1296 pdevice->rad_info.num_physical_sgprs_per_simd;
1297 properties->minSgprAllocation =
1298 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1299 properties->maxSgprAllocation =
1300 pdevice->rad_info.family == CHIP_TONGA ||
1301 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1302 properties->sgprAllocationGranularity =
1303 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1304
1305 /* VGPR. */
1306 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1307 properties->minVgprAllocation = 4;
1308 properties->maxVgprAllocation = 256;
1309 properties->vgprAllocationGranularity = 4;
1310 break;
1311 }
1312 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1313 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1314 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1315
1316 properties->shaderCoreFeatures = 0;
1317 properties->activeComputeUnitCount =
1318 pdevice->rad_info.num_good_compute_units;
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1322 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1323 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1324 properties->maxVertexAttribDivisor = UINT32_MAX;
1325 break;
1326 }
1327 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1328 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1329 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1330 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1331 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1332 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1333 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1334 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1335 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1336 properties->robustBufferAccessUpdateAfterBind = false;
1337 properties->quadDivergentImplicitLod = false;
1338
1339 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1340 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1341 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1342 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1343 32 /* sampler, largest when combined with image */ +
1344 64 /* sampled image */ +
1345 64 /* storage image */);
1346 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1347 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1348 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1349 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1350 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1351 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1352 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1353 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1354 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1355 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1356 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1357 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1358 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1359 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1360 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1364 VkPhysicalDeviceProtectedMemoryProperties *properties =
1365 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1366 properties->protectedNoFault = false;
1367 break;
1368 }
1369 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1370 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1371 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1372 properties->primitiveOverestimationSize = 0;
1373 properties->maxExtraPrimitiveOverestimationSize = 0;
1374 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1375 properties->primitiveUnderestimation = VK_FALSE;
1376 properties->conservativePointAndLineRasterization = VK_FALSE;
1377 properties->degenerateTrianglesRasterized = VK_FALSE;
1378 properties->degenerateLinesRasterized = VK_FALSE;
1379 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1380 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1381 break;
1382 }
1383 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1384 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1385 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1386 properties->pciDomain = pdevice->bus_info.domain;
1387 properties->pciBus = pdevice->bus_info.bus;
1388 properties->pciDevice = pdevice->bus_info.dev;
1389 properties->pciFunction = pdevice->bus_info.func;
1390 break;
1391 }
1392 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1393 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1394 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1395
1396 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1397 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1398 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1399 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1400 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1401
1402 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1403 .major = 1,
1404 .minor = 1,
1405 .subminor = 2,
1406 .patch = 0,
1407 };
1408 break;
1409 }
1410 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1411 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1412 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1413 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1414 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1415 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1416 properties->maxTransformFeedbackStreamDataSize = 512;
1417 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1418 properties->maxTransformFeedbackBufferDataStride = 512;
1419 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1420 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1421 properties->transformFeedbackRasterizationStreamSelect = false;
1422 properties->transformFeedbackDraw = true;
1423 break;
1424 }
1425 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1426 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1427 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1428
1429 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1430 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1431 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1432 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1433 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1434 break;
1435 }
1436 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1437 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1438 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1439 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1440 VK_SAMPLE_COUNT_4_BIT |
1441 VK_SAMPLE_COUNT_8_BIT;
1442 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1443 properties->sampleLocationCoordinateRange[0] = 0.0f;
1444 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1445 properties->sampleLocationSubPixelBits = 4;
1446 properties->variableSampleLocations = VK_FALSE;
1447 break;
1448 }
1449 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1450 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1451 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1452
1453 /* We support all of the depth resolve modes */
1454 properties->supportedDepthResolveModes =
1455 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1456 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1457 VK_RESOLVE_MODE_MIN_BIT_KHR |
1458 VK_RESOLVE_MODE_MAX_BIT_KHR;
1459
1460 /* Average doesn't make sense for stencil so we don't support that */
1461 properties->supportedStencilResolveModes =
1462 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1463 VK_RESOLVE_MODE_MIN_BIT_KHR |
1464 VK_RESOLVE_MODE_MAX_BIT_KHR;
1465
1466 properties->independentResolveNone = VK_TRUE;
1467 properties->independentResolve = VK_TRUE;
1468 break;
1469 }
1470 default:
1471 break;
1472 }
1473 }
1474 }
1475
1476 static void radv_get_physical_device_queue_family_properties(
1477 struct radv_physical_device* pdevice,
1478 uint32_t* pCount,
1479 VkQueueFamilyProperties** pQueueFamilyProperties)
1480 {
1481 int num_queue_families = 1;
1482 int idx;
1483 if (pdevice->rad_info.num_compute_rings > 0 &&
1484 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1485 num_queue_families++;
1486
1487 if (pQueueFamilyProperties == NULL) {
1488 *pCount = num_queue_families;
1489 return;
1490 }
1491
1492 if (!*pCount)
1493 return;
1494
1495 idx = 0;
1496 if (*pCount >= 1) {
1497 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1498 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1499 VK_QUEUE_COMPUTE_BIT |
1500 VK_QUEUE_TRANSFER_BIT |
1501 VK_QUEUE_SPARSE_BINDING_BIT,
1502 .queueCount = 1,
1503 .timestampValidBits = 64,
1504 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1505 };
1506 idx++;
1507 }
1508
1509 if (pdevice->rad_info.num_compute_rings > 0 &&
1510 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1511 if (*pCount > idx) {
1512 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1513 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1514 VK_QUEUE_TRANSFER_BIT |
1515 VK_QUEUE_SPARSE_BINDING_BIT,
1516 .queueCount = pdevice->rad_info.num_compute_rings,
1517 .timestampValidBits = 64,
1518 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1519 };
1520 idx++;
1521 }
1522 }
1523 *pCount = idx;
1524 }
1525
1526 void radv_GetPhysicalDeviceQueueFamilyProperties(
1527 VkPhysicalDevice physicalDevice,
1528 uint32_t* pCount,
1529 VkQueueFamilyProperties* pQueueFamilyProperties)
1530 {
1531 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1532 if (!pQueueFamilyProperties) {
1533 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1534 return;
1535 }
1536 VkQueueFamilyProperties *properties[] = {
1537 pQueueFamilyProperties + 0,
1538 pQueueFamilyProperties + 1,
1539 pQueueFamilyProperties + 2,
1540 };
1541 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1542 assert(*pCount <= 3);
1543 }
1544
1545 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1546 VkPhysicalDevice physicalDevice,
1547 uint32_t* pCount,
1548 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1549 {
1550 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1551 if (!pQueueFamilyProperties) {
1552 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1553 return;
1554 }
1555 VkQueueFamilyProperties *properties[] = {
1556 &pQueueFamilyProperties[0].queueFamilyProperties,
1557 &pQueueFamilyProperties[1].queueFamilyProperties,
1558 &pQueueFamilyProperties[2].queueFamilyProperties,
1559 };
1560 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1561 assert(*pCount <= 3);
1562 }
1563
1564 void radv_GetPhysicalDeviceMemoryProperties(
1565 VkPhysicalDevice physicalDevice,
1566 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1567 {
1568 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1569
1570 *pMemoryProperties = physical_device->memory_properties;
1571 }
1572
1573 static void
1574 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1575 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1576 {
1577 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1578 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1579 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1580 uint64_t vram_size = radv_get_vram_size(device);
1581 uint64_t gtt_size = device->rad_info.gart_size;
1582 uint64_t heap_budget, heap_usage;
1583
1584 /* For all memory heaps, the computation of budget is as follow:
1585 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1586 *
1587 * The Vulkan spec 1.1.97 says that the budget should include any
1588 * currently allocated device memory.
1589 *
1590 * Note that the application heap usages are not really accurate (eg.
1591 * in presence of shared buffers).
1592 */
1593 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1594 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1595
1596 switch (device->mem_type_indices[i]) {
1597 case RADV_MEM_TYPE_VRAM:
1598 heap_usage = device->ws->query_value(device->ws,
1599 RADEON_ALLOCATED_VRAM);
1600
1601 heap_budget = vram_size -
1602 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1603 heap_usage;
1604
1605 memoryBudget->heapBudget[heap_index] = heap_budget;
1606 memoryBudget->heapUsage[heap_index] = heap_usage;
1607 break;
1608 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1609 heap_usage = device->ws->query_value(device->ws,
1610 RADEON_ALLOCATED_VRAM_VIS);
1611
1612 heap_budget = visible_vram_size -
1613 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1614 heap_usage;
1615
1616 memoryBudget->heapBudget[heap_index] = heap_budget;
1617 memoryBudget->heapUsage[heap_index] = heap_usage;
1618 break;
1619 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1620 heap_usage = device->ws->query_value(device->ws,
1621 RADEON_ALLOCATED_GTT);
1622
1623 heap_budget = gtt_size -
1624 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1625 heap_usage;
1626
1627 memoryBudget->heapBudget[heap_index] = heap_budget;
1628 memoryBudget->heapUsage[heap_index] = heap_usage;
1629 break;
1630 default:
1631 break;
1632 }
1633 }
1634
1635 /* The heapBudget and heapUsage values must be zero for array elements
1636 * greater than or equal to
1637 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1638 */
1639 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1640 memoryBudget->heapBudget[i] = 0;
1641 memoryBudget->heapUsage[i] = 0;
1642 }
1643 }
1644
1645 void radv_GetPhysicalDeviceMemoryProperties2(
1646 VkPhysicalDevice physicalDevice,
1647 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1648 {
1649 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1650 &pMemoryProperties->memoryProperties);
1651
1652 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1653 vk_find_struct(pMemoryProperties->pNext,
1654 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1655 if (memory_budget)
1656 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1657 }
1658
1659 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1660 VkDevice _device,
1661 VkExternalMemoryHandleTypeFlagBits handleType,
1662 const void *pHostPointer,
1663 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1664 {
1665 RADV_FROM_HANDLE(radv_device, device, _device);
1666
1667 switch (handleType)
1668 {
1669 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1670 const struct radv_physical_device *physical_device = device->physical_device;
1671 uint32_t memoryTypeBits = 0;
1672 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1673 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1674 memoryTypeBits = (1 << i);
1675 break;
1676 }
1677 }
1678 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1679 return VK_SUCCESS;
1680 }
1681 default:
1682 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1683 }
1684 }
1685
1686 static enum radeon_ctx_priority
1687 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1688 {
1689 /* Default to MEDIUM when a specific global priority isn't requested */
1690 if (!pObj)
1691 return RADEON_CTX_PRIORITY_MEDIUM;
1692
1693 switch(pObj->globalPriority) {
1694 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1695 return RADEON_CTX_PRIORITY_REALTIME;
1696 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1697 return RADEON_CTX_PRIORITY_HIGH;
1698 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1699 return RADEON_CTX_PRIORITY_MEDIUM;
1700 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1701 return RADEON_CTX_PRIORITY_LOW;
1702 default:
1703 unreachable("Illegal global priority value");
1704 return RADEON_CTX_PRIORITY_INVALID;
1705 }
1706 }
1707
1708 static int
1709 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1710 uint32_t queue_family_index, int idx,
1711 VkDeviceQueueCreateFlags flags,
1712 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1713 {
1714 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1715 queue->device = device;
1716 queue->queue_family_index = queue_family_index;
1717 queue->queue_idx = idx;
1718 queue->priority = radv_get_queue_global_priority(global_priority);
1719 queue->flags = flags;
1720
1721 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1722 if (!queue->hw_ctx)
1723 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1724
1725 return VK_SUCCESS;
1726 }
1727
1728 static void
1729 radv_queue_finish(struct radv_queue *queue)
1730 {
1731 if (queue->hw_ctx)
1732 queue->device->ws->ctx_destroy(queue->hw_ctx);
1733
1734 if (queue->initial_full_flush_preamble_cs)
1735 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1736 if (queue->initial_preamble_cs)
1737 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1738 if (queue->continue_preamble_cs)
1739 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1740 if (queue->descriptor_bo)
1741 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1742 if (queue->scratch_bo)
1743 queue->device->ws->buffer_destroy(queue->scratch_bo);
1744 if (queue->esgs_ring_bo)
1745 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1746 if (queue->gsvs_ring_bo)
1747 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1748 if (queue->tess_rings_bo)
1749 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1750 if (queue->gds_bo)
1751 queue->device->ws->buffer_destroy(queue->gds_bo);
1752 if (queue->gds_oa_bo)
1753 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
1754 if (queue->compute_scratch_bo)
1755 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1756 }
1757
1758 static void
1759 radv_bo_list_init(struct radv_bo_list *bo_list)
1760 {
1761 pthread_mutex_init(&bo_list->mutex, NULL);
1762 bo_list->list.count = bo_list->capacity = 0;
1763 bo_list->list.bos = NULL;
1764 }
1765
1766 static void
1767 radv_bo_list_finish(struct radv_bo_list *bo_list)
1768 {
1769 free(bo_list->list.bos);
1770 pthread_mutex_destroy(&bo_list->mutex);
1771 }
1772
1773 static VkResult radv_bo_list_add(struct radv_device *device,
1774 struct radeon_winsys_bo *bo)
1775 {
1776 struct radv_bo_list *bo_list = &device->bo_list;
1777
1778 if (bo->is_local)
1779 return VK_SUCCESS;
1780
1781 if (unlikely(!device->use_global_bo_list))
1782 return VK_SUCCESS;
1783
1784 pthread_mutex_lock(&bo_list->mutex);
1785 if (bo_list->list.count == bo_list->capacity) {
1786 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1787 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1788
1789 if (!data) {
1790 pthread_mutex_unlock(&bo_list->mutex);
1791 return VK_ERROR_OUT_OF_HOST_MEMORY;
1792 }
1793
1794 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1795 bo_list->capacity = capacity;
1796 }
1797
1798 bo_list->list.bos[bo_list->list.count++] = bo;
1799 pthread_mutex_unlock(&bo_list->mutex);
1800 return VK_SUCCESS;
1801 }
1802
1803 static void radv_bo_list_remove(struct radv_device *device,
1804 struct radeon_winsys_bo *bo)
1805 {
1806 struct radv_bo_list *bo_list = &device->bo_list;
1807
1808 if (bo->is_local)
1809 return;
1810
1811 if (unlikely(!device->use_global_bo_list))
1812 return;
1813
1814 pthread_mutex_lock(&bo_list->mutex);
1815 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1816 if (bo_list->list.bos[i] == bo) {
1817 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1818 --bo_list->list.count;
1819 break;
1820 }
1821 }
1822 pthread_mutex_unlock(&bo_list->mutex);
1823 }
1824
1825 static void
1826 radv_device_init_gs_info(struct radv_device *device)
1827 {
1828 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1829 device->physical_device->rad_info.family);
1830 }
1831
1832 static int radv_get_device_extension_index(const char *name)
1833 {
1834 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1835 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1836 return i;
1837 }
1838 return -1;
1839 }
1840
1841 static int
1842 radv_get_int_debug_option(const char *name, int default_value)
1843 {
1844 const char *str;
1845 int result;
1846
1847 str = getenv(name);
1848 if (!str) {
1849 result = default_value;
1850 } else {
1851 char *endptr;
1852
1853 result = strtol(str, &endptr, 0);
1854 if (str == endptr) {
1855 /* No digits founs. */
1856 result = default_value;
1857 }
1858 }
1859
1860 return result;
1861 }
1862
1863 VkResult radv_CreateDevice(
1864 VkPhysicalDevice physicalDevice,
1865 const VkDeviceCreateInfo* pCreateInfo,
1866 const VkAllocationCallbacks* pAllocator,
1867 VkDevice* pDevice)
1868 {
1869 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1870 VkResult result;
1871 struct radv_device *device;
1872
1873 bool keep_shader_info = false;
1874
1875 /* Check enabled features */
1876 if (pCreateInfo->pEnabledFeatures) {
1877 VkPhysicalDeviceFeatures supported_features;
1878 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1879 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1880 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1881 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1882 for (uint32_t i = 0; i < num_features; i++) {
1883 if (enabled_feature[i] && !supported_feature[i])
1884 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1885 }
1886 }
1887
1888 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1889 sizeof(*device), 8,
1890 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1891 if (!device)
1892 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1893
1894 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1895 device->instance = physical_device->instance;
1896 device->physical_device = physical_device;
1897
1898 device->ws = physical_device->ws;
1899 if (pAllocator)
1900 device->alloc = *pAllocator;
1901 else
1902 device->alloc = physical_device->instance->alloc;
1903
1904 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1905 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1906 int index = radv_get_device_extension_index(ext_name);
1907 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1908 vk_free(&device->alloc, device);
1909 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1910 }
1911
1912 device->enabled_extensions.extensions[index] = true;
1913 }
1914
1915 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1916
1917 /* With update after bind we can't attach bo's to the command buffer
1918 * from the descriptor set anymore, so we have to use a global BO list.
1919 */
1920 device->use_global_bo_list =
1921 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1922 device->enabled_extensions.EXT_descriptor_indexing ||
1923 device->enabled_extensions.EXT_buffer_device_address;
1924
1925 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1926 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1927
1928 mtx_init(&device->shader_slab_mutex, mtx_plain);
1929 list_inithead(&device->shader_slabs);
1930
1931 radv_bo_list_init(&device->bo_list);
1932
1933 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1934 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1935 uint32_t qfi = queue_create->queueFamilyIndex;
1936 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1937 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1938
1939 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1940
1941 device->queues[qfi] = vk_alloc(&device->alloc,
1942 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1943 if (!device->queues[qfi]) {
1944 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1945 goto fail;
1946 }
1947
1948 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1949
1950 device->queue_count[qfi] = queue_create->queueCount;
1951
1952 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1953 result = radv_queue_init(device, &device->queues[qfi][q],
1954 qfi, q, queue_create->flags,
1955 global_priority);
1956 if (result != VK_SUCCESS)
1957 goto fail;
1958 }
1959 }
1960
1961 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1962 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1963
1964 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
1965 device->dfsm_allowed = device->pbb_allowed &&
1966 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
1967
1968 #ifdef ANDROID
1969 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1970 #endif
1971
1972 /* The maximum number of scratch waves. Scratch space isn't divided
1973 * evenly between CUs. The number is only a function of the number of CUs.
1974 * We can decrease the constant to decrease the scratch buffer size.
1975 *
1976 * sctx->scratch_waves must be >= the maximum possible size of
1977 * 1 threadgroup, so that the hw doesn't hang from being unable
1978 * to start any.
1979 *
1980 * The recommended value is 4 per CU at most. Higher numbers don't
1981 * bring much benefit, but they still occupy chip resources (think
1982 * async compute). I've seen ~2% performance difference between 4 and 32.
1983 */
1984 uint32_t max_threads_per_block = 2048;
1985 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1986 max_threads_per_block / 64);
1987
1988 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1989 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1990
1991 if (device->physical_device->rad_info.chip_class >= GFX7) {
1992 /* If the KMD allows it (there is a KMD hw register for it),
1993 * allow launching waves out-of-order.
1994 */
1995 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1996 }
1997
1998 radv_device_init_gs_info(device);
1999
2000 device->tess_offchip_block_dw_size =
2001 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2002
2003 if (getenv("RADV_TRACE_FILE")) {
2004 const char *filename = getenv("RADV_TRACE_FILE");
2005
2006 keep_shader_info = true;
2007
2008 if (!radv_init_trace(device))
2009 goto fail;
2010
2011 fprintf(stderr, "*****************************************************************************\n");
2012 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2013 fprintf(stderr, "*****************************************************************************\n");
2014
2015 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2016 radv_dump_enabled_options(device, stderr);
2017 }
2018
2019 device->keep_shader_info = keep_shader_info;
2020
2021 result = radv_device_init_meta(device);
2022 if (result != VK_SUCCESS)
2023 goto fail;
2024
2025 radv_device_init_msaa(device);
2026
2027 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2028 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2029 switch (family) {
2030 case RADV_QUEUE_GENERAL:
2031 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2032 if (device->physical_device->rad_info.drm_minor < 6) {
2033 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2034 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2035 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2036 }
2037 break;
2038 case RADV_QUEUE_COMPUTE:
2039 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2040 radeon_emit(device->empty_cs[family], 0);
2041 break;
2042 }
2043 device->ws->cs_finalize(device->empty_cs[family]);
2044 }
2045
2046 if (device->physical_device->rad_info.chip_class >= GFX7)
2047 cik_create_gfx_config(device);
2048
2049 VkPipelineCacheCreateInfo ci;
2050 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2051 ci.pNext = NULL;
2052 ci.flags = 0;
2053 ci.pInitialData = NULL;
2054 ci.initialDataSize = 0;
2055 VkPipelineCache pc;
2056 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2057 &ci, NULL, &pc);
2058 if (result != VK_SUCCESS)
2059 goto fail_meta;
2060
2061 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2062
2063 device->force_aniso =
2064 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2065 if (device->force_aniso >= 0) {
2066 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2067 1 << util_logbase2(device->force_aniso));
2068 }
2069
2070 *pDevice = radv_device_to_handle(device);
2071 return VK_SUCCESS;
2072
2073 fail_meta:
2074 radv_device_finish_meta(device);
2075 fail:
2076 radv_bo_list_finish(&device->bo_list);
2077
2078 if (device->trace_bo)
2079 device->ws->buffer_destroy(device->trace_bo);
2080
2081 if (device->gfx_init)
2082 device->ws->buffer_destroy(device->gfx_init);
2083
2084 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2085 for (unsigned q = 0; q < device->queue_count[i]; q++)
2086 radv_queue_finish(&device->queues[i][q]);
2087 if (device->queue_count[i])
2088 vk_free(&device->alloc, device->queues[i]);
2089 }
2090
2091 vk_free(&device->alloc, device);
2092 return result;
2093 }
2094
2095 void radv_DestroyDevice(
2096 VkDevice _device,
2097 const VkAllocationCallbacks* pAllocator)
2098 {
2099 RADV_FROM_HANDLE(radv_device, device, _device);
2100
2101 if (!device)
2102 return;
2103
2104 if (device->trace_bo)
2105 device->ws->buffer_destroy(device->trace_bo);
2106
2107 if (device->gfx_init)
2108 device->ws->buffer_destroy(device->gfx_init);
2109
2110 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2111 for (unsigned q = 0; q < device->queue_count[i]; q++)
2112 radv_queue_finish(&device->queues[i][q]);
2113 if (device->queue_count[i])
2114 vk_free(&device->alloc, device->queues[i]);
2115 if (device->empty_cs[i])
2116 device->ws->cs_destroy(device->empty_cs[i]);
2117 }
2118 radv_device_finish_meta(device);
2119
2120 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2121 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2122
2123 radv_destroy_shader_slabs(device);
2124
2125 radv_bo_list_finish(&device->bo_list);
2126 vk_free(&device->alloc, device);
2127 }
2128
2129 VkResult radv_EnumerateInstanceLayerProperties(
2130 uint32_t* pPropertyCount,
2131 VkLayerProperties* pProperties)
2132 {
2133 if (pProperties == NULL) {
2134 *pPropertyCount = 0;
2135 return VK_SUCCESS;
2136 }
2137
2138 /* None supported at this time */
2139 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2140 }
2141
2142 VkResult radv_EnumerateDeviceLayerProperties(
2143 VkPhysicalDevice physicalDevice,
2144 uint32_t* pPropertyCount,
2145 VkLayerProperties* pProperties)
2146 {
2147 if (pProperties == NULL) {
2148 *pPropertyCount = 0;
2149 return VK_SUCCESS;
2150 }
2151
2152 /* None supported at this time */
2153 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2154 }
2155
2156 void radv_GetDeviceQueue2(
2157 VkDevice _device,
2158 const VkDeviceQueueInfo2* pQueueInfo,
2159 VkQueue* pQueue)
2160 {
2161 RADV_FROM_HANDLE(radv_device, device, _device);
2162 struct radv_queue *queue;
2163
2164 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2165 if (pQueueInfo->flags != queue->flags) {
2166 /* From the Vulkan 1.1.70 spec:
2167 *
2168 * "The queue returned by vkGetDeviceQueue2 must have the same
2169 * flags value from this structure as that used at device
2170 * creation time in a VkDeviceQueueCreateInfo instance. If no
2171 * matching flags were specified at device creation time then
2172 * pQueue will return VK_NULL_HANDLE."
2173 */
2174 *pQueue = VK_NULL_HANDLE;
2175 return;
2176 }
2177
2178 *pQueue = radv_queue_to_handle(queue);
2179 }
2180
2181 void radv_GetDeviceQueue(
2182 VkDevice _device,
2183 uint32_t queueFamilyIndex,
2184 uint32_t queueIndex,
2185 VkQueue* pQueue)
2186 {
2187 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2188 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2189 .queueFamilyIndex = queueFamilyIndex,
2190 .queueIndex = queueIndex
2191 };
2192
2193 radv_GetDeviceQueue2(_device, &info, pQueue);
2194 }
2195
2196 static void
2197 fill_geom_tess_rings(struct radv_queue *queue,
2198 uint32_t *map,
2199 bool add_sample_positions,
2200 uint32_t esgs_ring_size,
2201 struct radeon_winsys_bo *esgs_ring_bo,
2202 uint32_t gsvs_ring_size,
2203 struct radeon_winsys_bo *gsvs_ring_bo,
2204 uint32_t tess_factor_ring_size,
2205 uint32_t tess_offchip_ring_offset,
2206 uint32_t tess_offchip_ring_size,
2207 struct radeon_winsys_bo *tess_rings_bo)
2208 {
2209 uint32_t *desc = &map[4];
2210
2211 if (esgs_ring_bo) {
2212 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2213
2214 /* stride 0, num records - size, add tid, swizzle, elsize4,
2215 index stride 64 */
2216 desc[0] = esgs_va;
2217 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2218 S_008F04_SWIZZLE_ENABLE(true);
2219 desc[2] = esgs_ring_size;
2220 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2221 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2222 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2223 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2224 S_008F0C_INDEX_STRIDE(3) |
2225 S_008F0C_ADD_TID_ENABLE(1);
2226
2227 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2228 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2229 S_008F0C_OOB_SELECT(2) |
2230 S_008F0C_RESOURCE_LEVEL(1);
2231 } else {
2232 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2233 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2234 S_008F0C_ELEMENT_SIZE(1);
2235 }
2236
2237 /* GS entry for ES->GS ring */
2238 /* stride 0, num records - size, elsize0,
2239 index stride 0 */
2240 desc[4] = esgs_va;
2241 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2242 desc[6] = esgs_ring_size;
2243 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2244 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2245 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2246 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2247
2248 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2249 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2250 S_008F0C_OOB_SELECT(2) |
2251 S_008F0C_RESOURCE_LEVEL(1);
2252 } else {
2253 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2254 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2255 }
2256 }
2257
2258 desc += 8;
2259
2260 if (gsvs_ring_bo) {
2261 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2262
2263 /* VS entry for GS->VS ring */
2264 /* stride 0, num records - size, elsize0,
2265 index stride 0 */
2266 desc[0] = gsvs_va;
2267 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2268 desc[2] = gsvs_ring_size;
2269 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2270 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2271 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2272 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2273
2274 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2275 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2276 S_008F0C_OOB_SELECT(2) |
2277 S_008F0C_RESOURCE_LEVEL(1);
2278 } else {
2279 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2281 }
2282
2283 /* stride gsvs_itemsize, num records 64
2284 elsize 4, index stride 16 */
2285 /* shader will patch stride and desc[2] */
2286 desc[4] = gsvs_va;
2287 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2288 S_008F04_SWIZZLE_ENABLE(1);
2289 desc[6] = 0;
2290 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2291 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2292 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2293 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2294 S_008F0C_INDEX_STRIDE(1) |
2295 S_008F0C_ADD_TID_ENABLE(true);
2296
2297 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2298 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2299 S_008F0C_OOB_SELECT(2) |
2300 S_008F0C_RESOURCE_LEVEL(1);
2301 } else {
2302 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2303 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2304 S_008F0C_ELEMENT_SIZE(1);
2305 }
2306
2307 }
2308
2309 desc += 8;
2310
2311 if (tess_rings_bo) {
2312 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2313 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2314
2315 desc[0] = tess_va;
2316 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2317 desc[2] = tess_factor_ring_size;
2318 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2319 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2320 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2321 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2322
2323 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2324 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2325 S_008F0C_OOB_SELECT(3) |
2326 S_008F0C_RESOURCE_LEVEL(1);
2327 } else {
2328 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2329 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2330 }
2331
2332 desc[4] = tess_offchip_va;
2333 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2334 desc[6] = tess_offchip_ring_size;
2335 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2336 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2337 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2338 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2339
2340 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2341 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2342 S_008F0C_OOB_SELECT(3) |
2343 S_008F0C_RESOURCE_LEVEL(1);
2344 } else {
2345 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2346 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2347 }
2348 }
2349
2350 desc += 8;
2351
2352 if (add_sample_positions) {
2353 /* add sample positions after all rings */
2354 memcpy(desc, queue->device->sample_locations_1x, 8);
2355 desc += 2;
2356 memcpy(desc, queue->device->sample_locations_2x, 16);
2357 desc += 4;
2358 memcpy(desc, queue->device->sample_locations_4x, 32);
2359 desc += 8;
2360 memcpy(desc, queue->device->sample_locations_8x, 64);
2361 }
2362 }
2363
2364 static unsigned
2365 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2366 {
2367 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2368 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2369 device->physical_device->rad_info.family != CHIP_STONEY;
2370 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2371 unsigned max_offchip_buffers;
2372 unsigned offchip_granularity;
2373 unsigned hs_offchip_param;
2374
2375 /*
2376 * Per RadeonSI:
2377 * This must be one less than the maximum number due to a hw limitation.
2378 * Various hardware bugs need thGFX7
2379 *
2380 * Per AMDVLK:
2381 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2382 * Gfx7 should limit max_offchip_buffers to 508
2383 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2384 *
2385 * Follow AMDVLK here.
2386 */
2387 if (device->physical_device->rad_info.chip_class >= GFX10) {
2388 max_offchip_buffers_per_se = 256;
2389 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2390 device->physical_device->rad_info.chip_class == GFX7 ||
2391 device->physical_device->rad_info.chip_class == GFX6)
2392 --max_offchip_buffers_per_se;
2393
2394 max_offchip_buffers = max_offchip_buffers_per_se *
2395 device->physical_device->rad_info.max_se;
2396
2397 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2398 * around by setting 4K granularity.
2399 */
2400 if (device->tess_offchip_block_dw_size == 4096) {
2401 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2402 offchip_granularity = V_03093C_X_4K_DWORDS;
2403 } else {
2404 assert(device->tess_offchip_block_dw_size == 8192);
2405 offchip_granularity = V_03093C_X_8K_DWORDS;
2406 }
2407
2408 switch (device->physical_device->rad_info.chip_class) {
2409 case GFX6:
2410 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2411 break;
2412 case GFX7:
2413 case GFX8:
2414 case GFX9:
2415 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2416 break;
2417 case GFX10:
2418 break;
2419 default:
2420 break;
2421 }
2422
2423 *max_offchip_buffers_p = max_offchip_buffers;
2424 if (device->physical_device->rad_info.chip_class >= GFX7) {
2425 if (device->physical_device->rad_info.chip_class >= GFX8)
2426 --max_offchip_buffers;
2427 hs_offchip_param =
2428 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2429 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2430 } else {
2431 hs_offchip_param =
2432 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2433 }
2434 return hs_offchip_param;
2435 }
2436
2437 static void
2438 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2439 struct radeon_winsys_bo *esgs_ring_bo,
2440 uint32_t esgs_ring_size,
2441 struct radeon_winsys_bo *gsvs_ring_bo,
2442 uint32_t gsvs_ring_size)
2443 {
2444 if (!esgs_ring_bo && !gsvs_ring_bo)
2445 return;
2446
2447 if (esgs_ring_bo)
2448 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2449
2450 if (gsvs_ring_bo)
2451 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2452
2453 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2454 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2455 radeon_emit(cs, esgs_ring_size >> 8);
2456 radeon_emit(cs, gsvs_ring_size >> 8);
2457 } else {
2458 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2459 radeon_emit(cs, esgs_ring_size >> 8);
2460 radeon_emit(cs, gsvs_ring_size >> 8);
2461 }
2462 }
2463
2464 static void
2465 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2466 unsigned hs_offchip_param, unsigned tf_ring_size,
2467 struct radeon_winsys_bo *tess_rings_bo)
2468 {
2469 uint64_t tf_va;
2470
2471 if (!tess_rings_bo)
2472 return;
2473
2474 tf_va = radv_buffer_get_va(tess_rings_bo);
2475
2476 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2477
2478 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2479 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2480 S_030938_SIZE(tf_ring_size / 4));
2481 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2482 tf_va >> 8);
2483
2484 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2485 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2486 S_030984_BASE_HI(tf_va >> 40));
2487 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2488 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2489 S_030944_BASE_HI(tf_va >> 40));
2490 }
2491 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2492 hs_offchip_param);
2493 } else {
2494 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2495 S_008988_SIZE(tf_ring_size / 4));
2496 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2497 tf_va >> 8);
2498 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2499 hs_offchip_param);
2500 }
2501 }
2502
2503 static void
2504 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2505 struct radeon_winsys_bo *compute_scratch_bo)
2506 {
2507 uint64_t scratch_va;
2508
2509 if (!compute_scratch_bo)
2510 return;
2511
2512 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2513
2514 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2515
2516 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2517 radeon_emit(cs, scratch_va);
2518 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2519 S_008F04_SWIZZLE_ENABLE(1));
2520 }
2521
2522 static void
2523 radv_emit_global_shader_pointers(struct radv_queue *queue,
2524 struct radeon_cmdbuf *cs,
2525 struct radeon_winsys_bo *descriptor_bo)
2526 {
2527 uint64_t va;
2528
2529 if (!descriptor_bo)
2530 return;
2531
2532 va = radv_buffer_get_va(descriptor_bo);
2533
2534 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2535
2536 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2537 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2538 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2539 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2540 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2541
2542 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2543 radv_emit_shader_pointer(queue->device, cs, regs[i],
2544 va, true);
2545 }
2546 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2547 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2548 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2549 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2550 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2551
2552 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2553 radv_emit_shader_pointer(queue->device, cs, regs[i],
2554 va, true);
2555 }
2556 } else {
2557 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2558 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2559 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2560 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2561 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2562 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2563
2564 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2565 radv_emit_shader_pointer(queue->device, cs, regs[i],
2566 va, true);
2567 }
2568 }
2569 }
2570
2571 static void
2572 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2573 {
2574 struct radv_device *device = queue->device;
2575
2576 if (device->gfx_init) {
2577 uint64_t va = radv_buffer_get_va(device->gfx_init);
2578
2579 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2580 radeon_emit(cs, va);
2581 radeon_emit(cs, va >> 32);
2582 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2583
2584 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2585 } else {
2586 struct radv_physical_device *physical_device = device->physical_device;
2587 si_emit_graphics(physical_device, cs);
2588 }
2589 }
2590
2591 static void
2592 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2593 {
2594 struct radv_physical_device *physical_device = queue->device->physical_device;
2595 si_emit_compute(physical_device, cs);
2596 }
2597
2598 static VkResult
2599 radv_get_preamble_cs(struct radv_queue *queue,
2600 uint32_t scratch_size,
2601 uint32_t compute_scratch_size,
2602 uint32_t esgs_ring_size,
2603 uint32_t gsvs_ring_size,
2604 bool needs_tess_rings,
2605 bool needs_gds,
2606 bool needs_sample_positions,
2607 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2608 struct radeon_cmdbuf **initial_preamble_cs,
2609 struct radeon_cmdbuf **continue_preamble_cs)
2610 {
2611 struct radeon_winsys_bo *scratch_bo = NULL;
2612 struct radeon_winsys_bo *descriptor_bo = NULL;
2613 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2614 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2615 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2616 struct radeon_winsys_bo *tess_rings_bo = NULL;
2617 struct radeon_winsys_bo *gds_bo = NULL;
2618 struct radeon_winsys_bo *gds_oa_bo = NULL;
2619 struct radeon_cmdbuf *dest_cs[3] = {0};
2620 bool add_tess_rings = false, add_gds = false, add_sample_positions = false;
2621 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2622 unsigned max_offchip_buffers;
2623 unsigned hs_offchip_param = 0;
2624 unsigned tess_offchip_ring_offset;
2625 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2626 if (!queue->has_tess_rings) {
2627 if (needs_tess_rings)
2628 add_tess_rings = true;
2629 }
2630 if (!queue->has_gds) {
2631 if (needs_gds)
2632 add_gds = true;
2633 }
2634 if (!queue->has_sample_positions) {
2635 if (needs_sample_positions)
2636 add_sample_positions = true;
2637 }
2638 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2639 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2640 &max_offchip_buffers);
2641 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2642 tess_offchip_ring_size = max_offchip_buffers *
2643 queue->device->tess_offchip_block_dw_size * 4;
2644
2645 if (scratch_size <= queue->scratch_size &&
2646 compute_scratch_size <= queue->compute_scratch_size &&
2647 esgs_ring_size <= queue->esgs_ring_size &&
2648 gsvs_ring_size <= queue->gsvs_ring_size &&
2649 !add_tess_rings && !add_gds && !add_sample_positions &&
2650 queue->initial_preamble_cs) {
2651 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2652 *initial_preamble_cs = queue->initial_preamble_cs;
2653 *continue_preamble_cs = queue->continue_preamble_cs;
2654 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2655 *continue_preamble_cs = NULL;
2656 return VK_SUCCESS;
2657 }
2658
2659 if (scratch_size > queue->scratch_size) {
2660 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2661 scratch_size,
2662 4096,
2663 RADEON_DOMAIN_VRAM,
2664 ring_bo_flags,
2665 RADV_BO_PRIORITY_SCRATCH);
2666 if (!scratch_bo)
2667 goto fail;
2668 } else
2669 scratch_bo = queue->scratch_bo;
2670
2671 if (compute_scratch_size > queue->compute_scratch_size) {
2672 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2673 compute_scratch_size,
2674 4096,
2675 RADEON_DOMAIN_VRAM,
2676 ring_bo_flags,
2677 RADV_BO_PRIORITY_SCRATCH);
2678 if (!compute_scratch_bo)
2679 goto fail;
2680
2681 } else
2682 compute_scratch_bo = queue->compute_scratch_bo;
2683
2684 if (esgs_ring_size > queue->esgs_ring_size) {
2685 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2686 esgs_ring_size,
2687 4096,
2688 RADEON_DOMAIN_VRAM,
2689 ring_bo_flags,
2690 RADV_BO_PRIORITY_SCRATCH);
2691 if (!esgs_ring_bo)
2692 goto fail;
2693 } else {
2694 esgs_ring_bo = queue->esgs_ring_bo;
2695 esgs_ring_size = queue->esgs_ring_size;
2696 }
2697
2698 if (gsvs_ring_size > queue->gsvs_ring_size) {
2699 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2700 gsvs_ring_size,
2701 4096,
2702 RADEON_DOMAIN_VRAM,
2703 ring_bo_flags,
2704 RADV_BO_PRIORITY_SCRATCH);
2705 if (!gsvs_ring_bo)
2706 goto fail;
2707 } else {
2708 gsvs_ring_bo = queue->gsvs_ring_bo;
2709 gsvs_ring_size = queue->gsvs_ring_size;
2710 }
2711
2712 if (add_tess_rings) {
2713 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2714 tess_offchip_ring_offset + tess_offchip_ring_size,
2715 256,
2716 RADEON_DOMAIN_VRAM,
2717 ring_bo_flags,
2718 RADV_BO_PRIORITY_SCRATCH);
2719 if (!tess_rings_bo)
2720 goto fail;
2721 } else {
2722 tess_rings_bo = queue->tess_rings_bo;
2723 }
2724
2725 if (add_gds) {
2726 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
2727
2728 /* 4 streamout GDS counters.
2729 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
2730 */
2731 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
2732 256, 4,
2733 RADEON_DOMAIN_GDS,
2734 ring_bo_flags,
2735 RADV_BO_PRIORITY_SCRATCH);
2736 if (!gds_bo)
2737 goto fail;
2738
2739 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
2740 4, 1,
2741 RADEON_DOMAIN_OA,
2742 ring_bo_flags,
2743 RADV_BO_PRIORITY_SCRATCH);
2744 if (!gds_oa_bo)
2745 goto fail;
2746 } else {
2747 gds_bo = queue->gds_bo;
2748 gds_oa_bo = queue->gds_oa_bo;
2749 }
2750
2751 if (scratch_bo != queue->scratch_bo ||
2752 esgs_ring_bo != queue->esgs_ring_bo ||
2753 gsvs_ring_bo != queue->gsvs_ring_bo ||
2754 tess_rings_bo != queue->tess_rings_bo ||
2755 add_sample_positions) {
2756 uint32_t size = 0;
2757 if (gsvs_ring_bo || esgs_ring_bo ||
2758 tess_rings_bo || add_sample_positions) {
2759 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2760 if (add_sample_positions)
2761 size += 128; /* 64+32+16+8 = 120 bytes */
2762 }
2763 else if (scratch_bo)
2764 size = 8; /* 2 dword */
2765
2766 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2767 size,
2768 4096,
2769 RADEON_DOMAIN_VRAM,
2770 RADEON_FLAG_CPU_ACCESS |
2771 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2772 RADEON_FLAG_READ_ONLY,
2773 RADV_BO_PRIORITY_DESCRIPTOR);
2774 if (!descriptor_bo)
2775 goto fail;
2776 } else
2777 descriptor_bo = queue->descriptor_bo;
2778
2779 if (descriptor_bo != queue->descriptor_bo) {
2780 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2781
2782 if (scratch_bo) {
2783 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2784 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2785 S_008F04_SWIZZLE_ENABLE(1);
2786 map[0] = scratch_va;
2787 map[1] = rsrc1;
2788 }
2789
2790 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2791 fill_geom_tess_rings(queue, map, add_sample_positions,
2792 esgs_ring_size, esgs_ring_bo,
2793 gsvs_ring_size, gsvs_ring_bo,
2794 tess_factor_ring_size,
2795 tess_offchip_ring_offset,
2796 tess_offchip_ring_size,
2797 tess_rings_bo);
2798
2799 queue->device->ws->buffer_unmap(descriptor_bo);
2800 }
2801
2802 for(int i = 0; i < 3; ++i) {
2803 struct radeon_cmdbuf *cs = NULL;
2804 cs = queue->device->ws->cs_create(queue->device->ws,
2805 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2806 if (!cs)
2807 goto fail;
2808
2809 dest_cs[i] = cs;
2810
2811 if (scratch_bo)
2812 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2813
2814 /* Emit initial configuration. */
2815 switch (queue->queue_family_index) {
2816 case RADV_QUEUE_GENERAL:
2817 radv_init_graphics_state(cs, queue);
2818 break;
2819 case RADV_QUEUE_COMPUTE:
2820 radv_init_compute_state(cs, queue);
2821 break;
2822 case RADV_QUEUE_TRANSFER:
2823 break;
2824 }
2825
2826 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2827 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2828 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2829
2830 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2831 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2832 }
2833
2834 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2835 gsvs_ring_bo, gsvs_ring_size);
2836 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2837 tess_factor_ring_size, tess_rings_bo);
2838 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2839 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2840
2841 if (gds_bo)
2842 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
2843 if (gds_oa_bo)
2844 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
2845
2846 if (i == 0) {
2847 si_cs_emit_cache_flush(cs,
2848 queue->device->physical_device->rad_info.chip_class,
2849 NULL, 0,
2850 queue->queue_family_index == RING_COMPUTE &&
2851 queue->device->physical_device->rad_info.chip_class >= GFX7,
2852 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2853 RADV_CMD_FLAG_INV_ICACHE |
2854 RADV_CMD_FLAG_INV_SCACHE |
2855 RADV_CMD_FLAG_INV_VCACHE |
2856 RADV_CMD_FLAG_INV_L2 |
2857 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2858 } else if (i == 1) {
2859 si_cs_emit_cache_flush(cs,
2860 queue->device->physical_device->rad_info.chip_class,
2861 NULL, 0,
2862 queue->queue_family_index == RING_COMPUTE &&
2863 queue->device->physical_device->rad_info.chip_class >= GFX7,
2864 RADV_CMD_FLAG_INV_ICACHE |
2865 RADV_CMD_FLAG_INV_SCACHE |
2866 RADV_CMD_FLAG_INV_VCACHE |
2867 RADV_CMD_FLAG_INV_L2 |
2868 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2869 }
2870
2871 if (!queue->device->ws->cs_finalize(cs))
2872 goto fail;
2873 }
2874
2875 if (queue->initial_full_flush_preamble_cs)
2876 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2877
2878 if (queue->initial_preamble_cs)
2879 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2880
2881 if (queue->continue_preamble_cs)
2882 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2883
2884 queue->initial_full_flush_preamble_cs = dest_cs[0];
2885 queue->initial_preamble_cs = dest_cs[1];
2886 queue->continue_preamble_cs = dest_cs[2];
2887
2888 if (scratch_bo != queue->scratch_bo) {
2889 if (queue->scratch_bo)
2890 queue->device->ws->buffer_destroy(queue->scratch_bo);
2891 queue->scratch_bo = scratch_bo;
2892 queue->scratch_size = scratch_size;
2893 }
2894
2895 if (compute_scratch_bo != queue->compute_scratch_bo) {
2896 if (queue->compute_scratch_bo)
2897 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2898 queue->compute_scratch_bo = compute_scratch_bo;
2899 queue->compute_scratch_size = compute_scratch_size;
2900 }
2901
2902 if (esgs_ring_bo != queue->esgs_ring_bo) {
2903 if (queue->esgs_ring_bo)
2904 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2905 queue->esgs_ring_bo = esgs_ring_bo;
2906 queue->esgs_ring_size = esgs_ring_size;
2907 }
2908
2909 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2910 if (queue->gsvs_ring_bo)
2911 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2912 queue->gsvs_ring_bo = gsvs_ring_bo;
2913 queue->gsvs_ring_size = gsvs_ring_size;
2914 }
2915
2916 if (tess_rings_bo != queue->tess_rings_bo) {
2917 queue->tess_rings_bo = tess_rings_bo;
2918 queue->has_tess_rings = true;
2919 }
2920
2921 if (gds_bo != queue->gds_bo) {
2922 queue->gds_bo = gds_bo;
2923 queue->has_gds = true;
2924 }
2925
2926 if (gds_oa_bo != queue->gds_oa_bo)
2927 queue->gds_oa_bo = gds_oa_bo;
2928
2929 if (descriptor_bo != queue->descriptor_bo) {
2930 if (queue->descriptor_bo)
2931 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2932
2933 queue->descriptor_bo = descriptor_bo;
2934 }
2935
2936 if (add_sample_positions)
2937 queue->has_sample_positions = true;
2938
2939 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2940 *initial_preamble_cs = queue->initial_preamble_cs;
2941 *continue_preamble_cs = queue->continue_preamble_cs;
2942 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2943 *continue_preamble_cs = NULL;
2944 return VK_SUCCESS;
2945 fail:
2946 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2947 if (dest_cs[i])
2948 queue->device->ws->cs_destroy(dest_cs[i]);
2949 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2950 queue->device->ws->buffer_destroy(descriptor_bo);
2951 if (scratch_bo && scratch_bo != queue->scratch_bo)
2952 queue->device->ws->buffer_destroy(scratch_bo);
2953 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2954 queue->device->ws->buffer_destroy(compute_scratch_bo);
2955 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2956 queue->device->ws->buffer_destroy(esgs_ring_bo);
2957 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2958 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2959 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2960 queue->device->ws->buffer_destroy(tess_rings_bo);
2961 if (gds_bo && gds_bo != queue->gds_bo)
2962 queue->device->ws->buffer_destroy(gds_bo);
2963 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
2964 queue->device->ws->buffer_destroy(gds_oa_bo);
2965
2966 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2967 }
2968
2969 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2970 struct radv_winsys_sem_counts *counts,
2971 int num_sems,
2972 const VkSemaphore *sems,
2973 VkFence _fence,
2974 bool reset_temp)
2975 {
2976 int syncobj_idx = 0, sem_idx = 0;
2977
2978 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2979 return VK_SUCCESS;
2980
2981 for (uint32_t i = 0; i < num_sems; i++) {
2982 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2983
2984 if (sem->temp_syncobj || sem->syncobj)
2985 counts->syncobj_count++;
2986 else
2987 counts->sem_count++;
2988 }
2989
2990 if (_fence != VK_NULL_HANDLE) {
2991 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2992 if (fence->temp_syncobj || fence->syncobj)
2993 counts->syncobj_count++;
2994 }
2995
2996 if (counts->syncobj_count) {
2997 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2998 if (!counts->syncobj)
2999 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3000 }
3001
3002 if (counts->sem_count) {
3003 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3004 if (!counts->sem) {
3005 free(counts->syncobj);
3006 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3007 }
3008 }
3009
3010 for (uint32_t i = 0; i < num_sems; i++) {
3011 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3012
3013 if (sem->temp_syncobj) {
3014 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
3015 }
3016 else if (sem->syncobj)
3017 counts->syncobj[syncobj_idx++] = sem->syncobj;
3018 else {
3019 assert(sem->sem);
3020 counts->sem[sem_idx++] = sem->sem;
3021 }
3022 }
3023
3024 if (_fence != VK_NULL_HANDLE) {
3025 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3026 if (fence->temp_syncobj)
3027 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
3028 else if (fence->syncobj)
3029 counts->syncobj[syncobj_idx++] = fence->syncobj;
3030 }
3031
3032 return VK_SUCCESS;
3033 }
3034
3035 static void
3036 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3037 {
3038 free(sem_info->wait.syncobj);
3039 free(sem_info->wait.sem);
3040 free(sem_info->signal.syncobj);
3041 free(sem_info->signal.sem);
3042 }
3043
3044
3045 static void radv_free_temp_syncobjs(struct radv_device *device,
3046 int num_sems,
3047 const VkSemaphore *sems)
3048 {
3049 for (uint32_t i = 0; i < num_sems; i++) {
3050 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3051
3052 if (sem->temp_syncobj) {
3053 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
3054 sem->temp_syncobj = 0;
3055 }
3056 }
3057 }
3058
3059 static VkResult
3060 radv_alloc_sem_info(struct radv_instance *instance,
3061 struct radv_winsys_sem_info *sem_info,
3062 int num_wait_sems,
3063 const VkSemaphore *wait_sems,
3064 int num_signal_sems,
3065 const VkSemaphore *signal_sems,
3066 VkFence fence)
3067 {
3068 VkResult ret;
3069 memset(sem_info, 0, sizeof(*sem_info));
3070
3071 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3072 if (ret)
3073 return ret;
3074 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3075 if (ret)
3076 radv_free_sem_info(sem_info);
3077
3078 /* caller can override these */
3079 sem_info->cs_emit_wait = true;
3080 sem_info->cs_emit_signal = true;
3081 return ret;
3082 }
3083
3084 /* Signals fence as soon as all the work currently put on queue is done. */
3085 static VkResult radv_signal_fence(struct radv_queue *queue,
3086 struct radv_fence *fence)
3087 {
3088 int ret;
3089 VkResult result;
3090 struct radv_winsys_sem_info sem_info;
3091
3092 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3093 radv_fence_to_handle(fence));
3094 if (result != VK_SUCCESS)
3095 return result;
3096
3097 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3098 &queue->device->empty_cs[queue->queue_family_index],
3099 1, NULL, NULL, &sem_info, NULL,
3100 false, fence->fence);
3101 radv_free_sem_info(&sem_info);
3102
3103 if (ret)
3104 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3105
3106 return VK_SUCCESS;
3107 }
3108
3109 VkResult radv_QueueSubmit(
3110 VkQueue _queue,
3111 uint32_t submitCount,
3112 const VkSubmitInfo* pSubmits,
3113 VkFence _fence)
3114 {
3115 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3116 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3117 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3118 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3119 int ret;
3120 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3121 uint32_t scratch_size = 0;
3122 uint32_t compute_scratch_size = 0;
3123 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3124 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3125 VkResult result;
3126 bool fence_emitted = false;
3127 bool tess_rings_needed = false;
3128 bool gds_needed = false;
3129 bool sample_positions_needed = false;
3130
3131 /* Do this first so failing to allocate scratch buffers can't result in
3132 * partially executed submissions. */
3133 for (uint32_t i = 0; i < submitCount; i++) {
3134 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3135 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3136 pSubmits[i].pCommandBuffers[j]);
3137
3138 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3139 compute_scratch_size = MAX2(compute_scratch_size,
3140 cmd_buffer->compute_scratch_size_needed);
3141 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3142 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3143 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3144 gds_needed |= cmd_buffer->gds_needed;
3145 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3146 }
3147 }
3148
3149 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3150 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3151 gds_needed, sample_positions_needed,
3152 &initial_flush_preamble_cs,
3153 &initial_preamble_cs, &continue_preamble_cs);
3154 if (result != VK_SUCCESS)
3155 return result;
3156
3157 for (uint32_t i = 0; i < submitCount; i++) {
3158 struct radeon_cmdbuf **cs_array;
3159 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3160 bool can_patch = true;
3161 uint32_t advance;
3162 struct radv_winsys_sem_info sem_info;
3163
3164 result = radv_alloc_sem_info(queue->device->instance,
3165 &sem_info,
3166 pSubmits[i].waitSemaphoreCount,
3167 pSubmits[i].pWaitSemaphores,
3168 pSubmits[i].signalSemaphoreCount,
3169 pSubmits[i].pSignalSemaphores,
3170 _fence);
3171 if (result != VK_SUCCESS)
3172 return result;
3173
3174 if (!pSubmits[i].commandBufferCount) {
3175 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3176 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3177 &queue->device->empty_cs[queue->queue_family_index],
3178 1, NULL, NULL,
3179 &sem_info, NULL,
3180 false, base_fence);
3181 if (ret) {
3182 radv_loge("failed to submit CS %d\n", i);
3183 abort();
3184 }
3185 fence_emitted = true;
3186 }
3187 radv_free_sem_info(&sem_info);
3188 continue;
3189 }
3190
3191 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3192 (pSubmits[i].commandBufferCount));
3193
3194 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3195 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3196 pSubmits[i].pCommandBuffers[j]);
3197 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3198
3199 cs_array[j] = cmd_buffer->cs;
3200 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3201 can_patch = false;
3202
3203 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3204 }
3205
3206 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3207 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3208 const struct radv_winsys_bo_list *bo_list = NULL;
3209
3210 advance = MIN2(max_cs_submission,
3211 pSubmits[i].commandBufferCount - j);
3212
3213 if (queue->device->trace_bo)
3214 *queue->device->trace_id_ptr = 0;
3215
3216 sem_info.cs_emit_wait = j == 0;
3217 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3218
3219 if (unlikely(queue->device->use_global_bo_list)) {
3220 pthread_mutex_lock(&queue->device->bo_list.mutex);
3221 bo_list = &queue->device->bo_list.list;
3222 }
3223
3224 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3225 advance, initial_preamble, continue_preamble_cs,
3226 &sem_info, bo_list,
3227 can_patch, base_fence);
3228
3229 if (unlikely(queue->device->use_global_bo_list))
3230 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3231
3232 if (ret) {
3233 radv_loge("failed to submit CS %d\n", i);
3234 abort();
3235 }
3236 fence_emitted = true;
3237 if (queue->device->trace_bo) {
3238 radv_check_gpu_hangs(queue, cs_array[j]);
3239 }
3240 }
3241
3242 radv_free_temp_syncobjs(queue->device,
3243 pSubmits[i].waitSemaphoreCount,
3244 pSubmits[i].pWaitSemaphores);
3245 radv_free_sem_info(&sem_info);
3246 free(cs_array);
3247 }
3248
3249 if (fence) {
3250 if (!fence_emitted) {
3251 result = radv_signal_fence(queue, fence);
3252 if (result != VK_SUCCESS)
3253 return result;
3254 }
3255 }
3256
3257 return VK_SUCCESS;
3258 }
3259
3260 VkResult radv_QueueWaitIdle(
3261 VkQueue _queue)
3262 {
3263 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3264
3265 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3266 radv_queue_family_to_ring(queue->queue_family_index),
3267 queue->queue_idx);
3268 return VK_SUCCESS;
3269 }
3270
3271 VkResult radv_DeviceWaitIdle(
3272 VkDevice _device)
3273 {
3274 RADV_FROM_HANDLE(radv_device, device, _device);
3275
3276 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3277 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3278 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3279 }
3280 }
3281 return VK_SUCCESS;
3282 }
3283
3284 VkResult radv_EnumerateInstanceExtensionProperties(
3285 const char* pLayerName,
3286 uint32_t* pPropertyCount,
3287 VkExtensionProperties* pProperties)
3288 {
3289 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3290
3291 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3292 if (radv_supported_instance_extensions.extensions[i]) {
3293 vk_outarray_append(&out, prop) {
3294 *prop = radv_instance_extensions[i];
3295 }
3296 }
3297 }
3298
3299 return vk_outarray_status(&out);
3300 }
3301
3302 VkResult radv_EnumerateDeviceExtensionProperties(
3303 VkPhysicalDevice physicalDevice,
3304 const char* pLayerName,
3305 uint32_t* pPropertyCount,
3306 VkExtensionProperties* pProperties)
3307 {
3308 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3309 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3310
3311 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3312 if (device->supported_extensions.extensions[i]) {
3313 vk_outarray_append(&out, prop) {
3314 *prop = radv_device_extensions[i];
3315 }
3316 }
3317 }
3318
3319 return vk_outarray_status(&out);
3320 }
3321
3322 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3323 VkInstance _instance,
3324 const char* pName)
3325 {
3326 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3327 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3328
3329 if (unchecked) {
3330 return radv_lookup_entrypoint_unchecked(pName);
3331 } else {
3332 return radv_lookup_entrypoint_checked(pName,
3333 instance ? instance->apiVersion : 0,
3334 instance ? &instance->enabled_extensions : NULL,
3335 NULL);
3336 }
3337 }
3338
3339 /* The loader wants us to expose a second GetInstanceProcAddr function
3340 * to work around certain LD_PRELOAD issues seen in apps.
3341 */
3342 PUBLIC
3343 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3344 VkInstance instance,
3345 const char* pName);
3346
3347 PUBLIC
3348 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3349 VkInstance instance,
3350 const char* pName)
3351 {
3352 return radv_GetInstanceProcAddr(instance, pName);
3353 }
3354
3355 PUBLIC
3356 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3357 VkInstance _instance,
3358 const char* pName);
3359
3360 PUBLIC
3361 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3362 VkInstance _instance,
3363 const char* pName)
3364 {
3365 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3366
3367 return radv_lookup_physical_device_entrypoint_checked(pName,
3368 instance ? instance->apiVersion : 0,
3369 instance ? &instance->enabled_extensions : NULL);
3370 }
3371
3372 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3373 VkDevice _device,
3374 const char* pName)
3375 {
3376 RADV_FROM_HANDLE(radv_device, device, _device);
3377 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3378
3379 if (unchecked) {
3380 return radv_lookup_entrypoint_unchecked(pName);
3381 } else {
3382 return radv_lookup_entrypoint_checked(pName,
3383 device->instance->apiVersion,
3384 &device->instance->enabled_extensions,
3385 &device->enabled_extensions);
3386 }
3387 }
3388
3389 bool radv_get_memory_fd(struct radv_device *device,
3390 struct radv_device_memory *memory,
3391 int *pFD)
3392 {
3393 struct radeon_bo_metadata metadata;
3394
3395 if (memory->image) {
3396 radv_init_metadata(device, memory->image, &metadata);
3397 device->ws->buffer_set_metadata(memory->bo, &metadata);
3398 }
3399
3400 return device->ws->buffer_get_fd(device->ws, memory->bo,
3401 pFD);
3402 }
3403
3404 static VkResult radv_alloc_memory(struct radv_device *device,
3405 const VkMemoryAllocateInfo* pAllocateInfo,
3406 const VkAllocationCallbacks* pAllocator,
3407 VkDeviceMemory* pMem)
3408 {
3409 struct radv_device_memory *mem;
3410 VkResult result;
3411 enum radeon_bo_domain domain;
3412 uint32_t flags = 0;
3413 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3414
3415 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3416
3417 if (pAllocateInfo->allocationSize == 0) {
3418 /* Apparently, this is allowed */
3419 *pMem = VK_NULL_HANDLE;
3420 return VK_SUCCESS;
3421 }
3422
3423 const VkImportMemoryFdInfoKHR *import_info =
3424 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3425 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3426 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3427 const VkExportMemoryAllocateInfo *export_info =
3428 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3429 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3430 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3431
3432 const struct wsi_memory_allocate_info *wsi_info =
3433 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3434
3435 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3436 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3437 if (mem == NULL)
3438 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3439
3440 if (wsi_info && wsi_info->implicit_sync)
3441 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3442
3443 if (dedicate_info) {
3444 mem->image = radv_image_from_handle(dedicate_info->image);
3445 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3446 } else {
3447 mem->image = NULL;
3448 mem->buffer = NULL;
3449 }
3450
3451 float priority_float = 0.5;
3452 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3453 vk_find_struct_const(pAllocateInfo->pNext,
3454 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3455 if (priority_ext)
3456 priority_float = priority_ext->priority;
3457
3458 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3459 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3460
3461 mem->user_ptr = NULL;
3462
3463 if (import_info) {
3464 assert(import_info->handleType ==
3465 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3466 import_info->handleType ==
3467 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3468 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3469 priority, NULL, NULL);
3470 if (!mem->bo) {
3471 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3472 goto fail;
3473 } else {
3474 close(import_info->fd);
3475 }
3476 } else if (host_ptr_info) {
3477 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3478 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3479 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3480 pAllocateInfo->allocationSize,
3481 priority);
3482 if (!mem->bo) {
3483 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3484 goto fail;
3485 } else {
3486 mem->user_ptr = host_ptr_info->pHostPointer;
3487 }
3488 } else {
3489 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3490 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3491 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3492 domain = RADEON_DOMAIN_GTT;
3493 else
3494 domain = RADEON_DOMAIN_VRAM;
3495
3496 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3497 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3498 else
3499 flags |= RADEON_FLAG_CPU_ACCESS;
3500
3501 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3502 flags |= RADEON_FLAG_GTT_WC;
3503
3504 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3505 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3506 if (device->use_global_bo_list) {
3507 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3508 }
3509 }
3510
3511 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3512 domain, flags, priority);
3513
3514 if (!mem->bo) {
3515 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3516 goto fail;
3517 }
3518 mem->type_index = mem_type_index;
3519 }
3520
3521 result = radv_bo_list_add(device, mem->bo);
3522 if (result != VK_SUCCESS)
3523 goto fail_bo;
3524
3525 *pMem = radv_device_memory_to_handle(mem);
3526
3527 return VK_SUCCESS;
3528
3529 fail_bo:
3530 device->ws->buffer_destroy(mem->bo);
3531 fail:
3532 vk_free2(&device->alloc, pAllocator, mem);
3533
3534 return result;
3535 }
3536
3537 VkResult radv_AllocateMemory(
3538 VkDevice _device,
3539 const VkMemoryAllocateInfo* pAllocateInfo,
3540 const VkAllocationCallbacks* pAllocator,
3541 VkDeviceMemory* pMem)
3542 {
3543 RADV_FROM_HANDLE(radv_device, device, _device);
3544 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3545 }
3546
3547 void radv_FreeMemory(
3548 VkDevice _device,
3549 VkDeviceMemory _mem,
3550 const VkAllocationCallbacks* pAllocator)
3551 {
3552 RADV_FROM_HANDLE(radv_device, device, _device);
3553 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3554
3555 if (mem == NULL)
3556 return;
3557
3558 radv_bo_list_remove(device, mem->bo);
3559 device->ws->buffer_destroy(mem->bo);
3560 mem->bo = NULL;
3561
3562 vk_free2(&device->alloc, pAllocator, mem);
3563 }
3564
3565 VkResult radv_MapMemory(
3566 VkDevice _device,
3567 VkDeviceMemory _memory,
3568 VkDeviceSize offset,
3569 VkDeviceSize size,
3570 VkMemoryMapFlags flags,
3571 void** ppData)
3572 {
3573 RADV_FROM_HANDLE(radv_device, device, _device);
3574 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3575
3576 if (mem == NULL) {
3577 *ppData = NULL;
3578 return VK_SUCCESS;
3579 }
3580
3581 if (mem->user_ptr)
3582 *ppData = mem->user_ptr;
3583 else
3584 *ppData = device->ws->buffer_map(mem->bo);
3585
3586 if (*ppData) {
3587 *ppData += offset;
3588 return VK_SUCCESS;
3589 }
3590
3591 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3592 }
3593
3594 void radv_UnmapMemory(
3595 VkDevice _device,
3596 VkDeviceMemory _memory)
3597 {
3598 RADV_FROM_HANDLE(radv_device, device, _device);
3599 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3600
3601 if (mem == NULL)
3602 return;
3603
3604 if (mem->user_ptr == NULL)
3605 device->ws->buffer_unmap(mem->bo);
3606 }
3607
3608 VkResult radv_FlushMappedMemoryRanges(
3609 VkDevice _device,
3610 uint32_t memoryRangeCount,
3611 const VkMappedMemoryRange* pMemoryRanges)
3612 {
3613 return VK_SUCCESS;
3614 }
3615
3616 VkResult radv_InvalidateMappedMemoryRanges(
3617 VkDevice _device,
3618 uint32_t memoryRangeCount,
3619 const VkMappedMemoryRange* pMemoryRanges)
3620 {
3621 return VK_SUCCESS;
3622 }
3623
3624 void radv_GetBufferMemoryRequirements(
3625 VkDevice _device,
3626 VkBuffer _buffer,
3627 VkMemoryRequirements* pMemoryRequirements)
3628 {
3629 RADV_FROM_HANDLE(radv_device, device, _device);
3630 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3631
3632 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3633
3634 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3635 pMemoryRequirements->alignment = 4096;
3636 else
3637 pMemoryRequirements->alignment = 16;
3638
3639 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3640 }
3641
3642 void radv_GetBufferMemoryRequirements2(
3643 VkDevice device,
3644 const VkBufferMemoryRequirementsInfo2 *pInfo,
3645 VkMemoryRequirements2 *pMemoryRequirements)
3646 {
3647 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3648 &pMemoryRequirements->memoryRequirements);
3649 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3650 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3651 switch (ext->sType) {
3652 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3653 VkMemoryDedicatedRequirements *req =
3654 (VkMemoryDedicatedRequirements *) ext;
3655 req->requiresDedicatedAllocation = buffer->shareable;
3656 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3657 break;
3658 }
3659 default:
3660 break;
3661 }
3662 }
3663 }
3664
3665 void radv_GetImageMemoryRequirements(
3666 VkDevice _device,
3667 VkImage _image,
3668 VkMemoryRequirements* pMemoryRequirements)
3669 {
3670 RADV_FROM_HANDLE(radv_device, device, _device);
3671 RADV_FROM_HANDLE(radv_image, image, _image);
3672
3673 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3674
3675 pMemoryRequirements->size = image->size;
3676 pMemoryRequirements->alignment = image->alignment;
3677 }
3678
3679 void radv_GetImageMemoryRequirements2(
3680 VkDevice device,
3681 const VkImageMemoryRequirementsInfo2 *pInfo,
3682 VkMemoryRequirements2 *pMemoryRequirements)
3683 {
3684 radv_GetImageMemoryRequirements(device, pInfo->image,
3685 &pMemoryRequirements->memoryRequirements);
3686
3687 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3688
3689 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3690 switch (ext->sType) {
3691 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3692 VkMemoryDedicatedRequirements *req =
3693 (VkMemoryDedicatedRequirements *) ext;
3694 req->requiresDedicatedAllocation = image->shareable;
3695 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3696 break;
3697 }
3698 default:
3699 break;
3700 }
3701 }
3702 }
3703
3704 void radv_GetImageSparseMemoryRequirements(
3705 VkDevice device,
3706 VkImage image,
3707 uint32_t* pSparseMemoryRequirementCount,
3708 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3709 {
3710 stub();
3711 }
3712
3713 void radv_GetImageSparseMemoryRequirements2(
3714 VkDevice device,
3715 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3716 uint32_t* pSparseMemoryRequirementCount,
3717 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3718 {
3719 stub();
3720 }
3721
3722 void radv_GetDeviceMemoryCommitment(
3723 VkDevice device,
3724 VkDeviceMemory memory,
3725 VkDeviceSize* pCommittedMemoryInBytes)
3726 {
3727 *pCommittedMemoryInBytes = 0;
3728 }
3729
3730 VkResult radv_BindBufferMemory2(VkDevice device,
3731 uint32_t bindInfoCount,
3732 const VkBindBufferMemoryInfo *pBindInfos)
3733 {
3734 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3735 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3736 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3737
3738 if (mem) {
3739 buffer->bo = mem->bo;
3740 buffer->offset = pBindInfos[i].memoryOffset;
3741 } else {
3742 buffer->bo = NULL;
3743 }
3744 }
3745 return VK_SUCCESS;
3746 }
3747
3748 VkResult radv_BindBufferMemory(
3749 VkDevice device,
3750 VkBuffer buffer,
3751 VkDeviceMemory memory,
3752 VkDeviceSize memoryOffset)
3753 {
3754 const VkBindBufferMemoryInfo info = {
3755 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3756 .buffer = buffer,
3757 .memory = memory,
3758 .memoryOffset = memoryOffset
3759 };
3760
3761 return radv_BindBufferMemory2(device, 1, &info);
3762 }
3763
3764 VkResult radv_BindImageMemory2(VkDevice device,
3765 uint32_t bindInfoCount,
3766 const VkBindImageMemoryInfo *pBindInfos)
3767 {
3768 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3769 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3770 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3771
3772 if (mem) {
3773 image->bo = mem->bo;
3774 image->offset = pBindInfos[i].memoryOffset;
3775 } else {
3776 image->bo = NULL;
3777 image->offset = 0;
3778 }
3779 }
3780 return VK_SUCCESS;
3781 }
3782
3783
3784 VkResult radv_BindImageMemory(
3785 VkDevice device,
3786 VkImage image,
3787 VkDeviceMemory memory,
3788 VkDeviceSize memoryOffset)
3789 {
3790 const VkBindImageMemoryInfo info = {
3791 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3792 .image = image,
3793 .memory = memory,
3794 .memoryOffset = memoryOffset
3795 };
3796
3797 return radv_BindImageMemory2(device, 1, &info);
3798 }
3799
3800
3801 static void
3802 radv_sparse_buffer_bind_memory(struct radv_device *device,
3803 const VkSparseBufferMemoryBindInfo *bind)
3804 {
3805 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3806
3807 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3808 struct radv_device_memory *mem = NULL;
3809
3810 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3811 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3812
3813 device->ws->buffer_virtual_bind(buffer->bo,
3814 bind->pBinds[i].resourceOffset,
3815 bind->pBinds[i].size,
3816 mem ? mem->bo : NULL,
3817 bind->pBinds[i].memoryOffset);
3818 }
3819 }
3820
3821 static void
3822 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3823 const VkSparseImageOpaqueMemoryBindInfo *bind)
3824 {
3825 RADV_FROM_HANDLE(radv_image, image, bind->image);
3826
3827 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3828 struct radv_device_memory *mem = NULL;
3829
3830 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3831 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3832
3833 device->ws->buffer_virtual_bind(image->bo,
3834 bind->pBinds[i].resourceOffset,
3835 bind->pBinds[i].size,
3836 mem ? mem->bo : NULL,
3837 bind->pBinds[i].memoryOffset);
3838 }
3839 }
3840
3841 VkResult radv_QueueBindSparse(
3842 VkQueue _queue,
3843 uint32_t bindInfoCount,
3844 const VkBindSparseInfo* pBindInfo,
3845 VkFence _fence)
3846 {
3847 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3848 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3849 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3850 bool fence_emitted = false;
3851 VkResult result;
3852 int ret;
3853
3854 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3855 struct radv_winsys_sem_info sem_info;
3856 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3857 radv_sparse_buffer_bind_memory(queue->device,
3858 pBindInfo[i].pBufferBinds + j);
3859 }
3860
3861 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3862 radv_sparse_image_opaque_bind_memory(queue->device,
3863 pBindInfo[i].pImageOpaqueBinds + j);
3864 }
3865
3866 VkResult result;
3867 result = radv_alloc_sem_info(queue->device->instance,
3868 &sem_info,
3869 pBindInfo[i].waitSemaphoreCount,
3870 pBindInfo[i].pWaitSemaphores,
3871 pBindInfo[i].signalSemaphoreCount,
3872 pBindInfo[i].pSignalSemaphores,
3873 _fence);
3874 if (result != VK_SUCCESS)
3875 return result;
3876
3877 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3878 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3879 &queue->device->empty_cs[queue->queue_family_index],
3880 1, NULL, NULL,
3881 &sem_info, NULL,
3882 false, base_fence);
3883 if (ret) {
3884 radv_loge("failed to submit CS %d\n", i);
3885 abort();
3886 }
3887
3888 fence_emitted = true;
3889 }
3890
3891 radv_free_sem_info(&sem_info);
3892
3893 }
3894
3895 if (fence) {
3896 if (!fence_emitted) {
3897 result = radv_signal_fence(queue, fence);
3898 if (result != VK_SUCCESS)
3899 return result;
3900 }
3901 }
3902
3903 return VK_SUCCESS;
3904 }
3905
3906 VkResult radv_CreateFence(
3907 VkDevice _device,
3908 const VkFenceCreateInfo* pCreateInfo,
3909 const VkAllocationCallbacks* pAllocator,
3910 VkFence* pFence)
3911 {
3912 RADV_FROM_HANDLE(radv_device, device, _device);
3913 const VkExportFenceCreateInfo *export =
3914 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3915 VkExternalFenceHandleTypeFlags handleTypes =
3916 export ? export->handleTypes : 0;
3917
3918 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3919 sizeof(*fence), 8,
3920 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3921
3922 if (!fence)
3923 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3924
3925 fence->fence_wsi = NULL;
3926 fence->temp_syncobj = 0;
3927 if (device->always_use_syncobj || handleTypes) {
3928 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3929 if (ret) {
3930 vk_free2(&device->alloc, pAllocator, fence);
3931 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3932 }
3933 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3934 device->ws->signal_syncobj(device->ws, fence->syncobj);
3935 }
3936 fence->fence = NULL;
3937 } else {
3938 fence->fence = device->ws->create_fence();
3939 if (!fence->fence) {
3940 vk_free2(&device->alloc, pAllocator, fence);
3941 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3942 }
3943 fence->syncobj = 0;
3944 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3945 device->ws->signal_fence(fence->fence);
3946 }
3947
3948 *pFence = radv_fence_to_handle(fence);
3949
3950 return VK_SUCCESS;
3951 }
3952
3953 void radv_DestroyFence(
3954 VkDevice _device,
3955 VkFence _fence,
3956 const VkAllocationCallbacks* pAllocator)
3957 {
3958 RADV_FROM_HANDLE(radv_device, device, _device);
3959 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3960
3961 if (!fence)
3962 return;
3963
3964 if (fence->temp_syncobj)
3965 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3966 if (fence->syncobj)
3967 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3968 if (fence->fence)
3969 device->ws->destroy_fence(fence->fence);
3970 if (fence->fence_wsi)
3971 fence->fence_wsi->destroy(fence->fence_wsi);
3972 vk_free2(&device->alloc, pAllocator, fence);
3973 }
3974
3975
3976 uint64_t radv_get_current_time(void)
3977 {
3978 struct timespec tv;
3979 clock_gettime(CLOCK_MONOTONIC, &tv);
3980 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3981 }
3982
3983 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3984 {
3985 uint64_t current_time = radv_get_current_time();
3986
3987 timeout = MIN2(UINT64_MAX - current_time, timeout);
3988
3989 return current_time + timeout;
3990 }
3991
3992
3993 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3994 uint32_t fenceCount, const VkFence *pFences)
3995 {
3996 for (uint32_t i = 0; i < fenceCount; ++i) {
3997 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3998 if (fence->fence == NULL || fence->syncobj ||
3999 fence->temp_syncobj || fence->fence_wsi ||
4000 (!device->ws->is_fence_waitable(fence->fence)))
4001 return false;
4002 }
4003 return true;
4004 }
4005
4006 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
4007 {
4008 for (uint32_t i = 0; i < fenceCount; ++i) {
4009 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4010 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
4011 return false;
4012 }
4013 return true;
4014 }
4015
4016 VkResult radv_WaitForFences(
4017 VkDevice _device,
4018 uint32_t fenceCount,
4019 const VkFence* pFences,
4020 VkBool32 waitAll,
4021 uint64_t timeout)
4022 {
4023 RADV_FROM_HANDLE(radv_device, device, _device);
4024 timeout = radv_get_absolute_timeout(timeout);
4025
4026 if (device->always_use_syncobj &&
4027 radv_all_fences_syncobj(fenceCount, pFences))
4028 {
4029 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
4030 if (!handles)
4031 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4032
4033 for (uint32_t i = 0; i < fenceCount; ++i) {
4034 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4035 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
4036 }
4037
4038 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
4039
4040 free(handles);
4041 return success ? VK_SUCCESS : VK_TIMEOUT;
4042 }
4043
4044 if (!waitAll && fenceCount > 1) {
4045 /* Not doing this by default for waitAll, due to needing to allocate twice. */
4046 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
4047 uint32_t wait_count = 0;
4048 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
4049 if (!fences)
4050 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4051
4052 for (uint32_t i = 0; i < fenceCount; ++i) {
4053 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4054
4055 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
4056 free(fences);
4057 return VK_SUCCESS;
4058 }
4059
4060 fences[wait_count++] = fence->fence;
4061 }
4062
4063 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
4064 waitAll, timeout - radv_get_current_time());
4065
4066 free(fences);
4067 return success ? VK_SUCCESS : VK_TIMEOUT;
4068 }
4069
4070 while(radv_get_current_time() <= timeout) {
4071 for (uint32_t i = 0; i < fenceCount; ++i) {
4072 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
4073 return VK_SUCCESS;
4074 }
4075 }
4076 return VK_TIMEOUT;
4077 }
4078
4079 for (uint32_t i = 0; i < fenceCount; ++i) {
4080 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4081 bool expired = false;
4082
4083 if (fence->temp_syncobj) {
4084 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4085 return VK_TIMEOUT;
4086 continue;
4087 }
4088
4089 if (fence->syncobj) {
4090 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4091 return VK_TIMEOUT;
4092 continue;
4093 }
4094
4095 if (fence->fence) {
4096 if (!device->ws->is_fence_waitable(fence->fence)) {
4097 while(!device->ws->is_fence_waitable(fence->fence) &&
4098 radv_get_current_time() <= timeout)
4099 /* Do nothing */;
4100 }
4101
4102 expired = device->ws->fence_wait(device->ws,
4103 fence->fence,
4104 true, timeout);
4105 if (!expired)
4106 return VK_TIMEOUT;
4107 }
4108
4109 if (fence->fence_wsi) {
4110 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4111 if (result != VK_SUCCESS)
4112 return result;
4113 }
4114 }
4115
4116 return VK_SUCCESS;
4117 }
4118
4119 VkResult radv_ResetFences(VkDevice _device,
4120 uint32_t fenceCount,
4121 const VkFence *pFences)
4122 {
4123 RADV_FROM_HANDLE(radv_device, device, _device);
4124
4125 for (unsigned i = 0; i < fenceCount; ++i) {
4126 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4127 if (fence->fence)
4128 device->ws->reset_fence(fence->fence);
4129
4130 /* Per spec, we first restore the permanent payload, and then reset, so
4131 * having a temp syncobj should not skip resetting the permanent syncobj. */
4132 if (fence->temp_syncobj) {
4133 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4134 fence->temp_syncobj = 0;
4135 }
4136
4137 if (fence->syncobj) {
4138 device->ws->reset_syncobj(device->ws, fence->syncobj);
4139 }
4140 }
4141
4142 return VK_SUCCESS;
4143 }
4144
4145 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4146 {
4147 RADV_FROM_HANDLE(radv_device, device, _device);
4148 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4149
4150 if (fence->temp_syncobj) {
4151 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4152 return success ? VK_SUCCESS : VK_NOT_READY;
4153 }
4154
4155 if (fence->syncobj) {
4156 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4157 return success ? VK_SUCCESS : VK_NOT_READY;
4158 }
4159
4160 if (fence->fence) {
4161 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4162 return VK_NOT_READY;
4163 }
4164 if (fence->fence_wsi) {
4165 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4166
4167 if (result != VK_SUCCESS) {
4168 if (result == VK_TIMEOUT)
4169 return VK_NOT_READY;
4170 return result;
4171 }
4172 }
4173 return VK_SUCCESS;
4174 }
4175
4176
4177 // Queue semaphore functions
4178
4179 VkResult radv_CreateSemaphore(
4180 VkDevice _device,
4181 const VkSemaphoreCreateInfo* pCreateInfo,
4182 const VkAllocationCallbacks* pAllocator,
4183 VkSemaphore* pSemaphore)
4184 {
4185 RADV_FROM_HANDLE(radv_device, device, _device);
4186 const VkExportSemaphoreCreateInfo *export =
4187 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4188 VkExternalSemaphoreHandleTypeFlags handleTypes =
4189 export ? export->handleTypes : 0;
4190
4191 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4192 sizeof(*sem), 8,
4193 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4194 if (!sem)
4195 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4196
4197 sem->temp_syncobj = 0;
4198 /* create a syncobject if we are going to export this semaphore */
4199 if (device->always_use_syncobj || handleTypes) {
4200 assert (device->physical_device->rad_info.has_syncobj);
4201 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4202 if (ret) {
4203 vk_free2(&device->alloc, pAllocator, sem);
4204 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4205 }
4206 sem->sem = NULL;
4207 } else {
4208 sem->sem = device->ws->create_sem(device->ws);
4209 if (!sem->sem) {
4210 vk_free2(&device->alloc, pAllocator, sem);
4211 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4212 }
4213 sem->syncobj = 0;
4214 }
4215
4216 *pSemaphore = radv_semaphore_to_handle(sem);
4217 return VK_SUCCESS;
4218 }
4219
4220 void radv_DestroySemaphore(
4221 VkDevice _device,
4222 VkSemaphore _semaphore,
4223 const VkAllocationCallbacks* pAllocator)
4224 {
4225 RADV_FROM_HANDLE(radv_device, device, _device);
4226 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4227 if (!_semaphore)
4228 return;
4229
4230 if (sem->syncobj)
4231 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4232 else
4233 device->ws->destroy_sem(sem->sem);
4234 vk_free2(&device->alloc, pAllocator, sem);
4235 }
4236
4237 VkResult radv_CreateEvent(
4238 VkDevice _device,
4239 const VkEventCreateInfo* pCreateInfo,
4240 const VkAllocationCallbacks* pAllocator,
4241 VkEvent* pEvent)
4242 {
4243 RADV_FROM_HANDLE(radv_device, device, _device);
4244 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4245 sizeof(*event), 8,
4246 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4247
4248 if (!event)
4249 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4250
4251 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4252 RADEON_DOMAIN_GTT,
4253 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4254 RADV_BO_PRIORITY_FENCE);
4255 if (!event->bo) {
4256 vk_free2(&device->alloc, pAllocator, event);
4257 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4258 }
4259
4260 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4261
4262 *pEvent = radv_event_to_handle(event);
4263
4264 return VK_SUCCESS;
4265 }
4266
4267 void radv_DestroyEvent(
4268 VkDevice _device,
4269 VkEvent _event,
4270 const VkAllocationCallbacks* pAllocator)
4271 {
4272 RADV_FROM_HANDLE(radv_device, device, _device);
4273 RADV_FROM_HANDLE(radv_event, event, _event);
4274
4275 if (!event)
4276 return;
4277 device->ws->buffer_destroy(event->bo);
4278 vk_free2(&device->alloc, pAllocator, event);
4279 }
4280
4281 VkResult radv_GetEventStatus(
4282 VkDevice _device,
4283 VkEvent _event)
4284 {
4285 RADV_FROM_HANDLE(radv_event, event, _event);
4286
4287 if (*event->map == 1)
4288 return VK_EVENT_SET;
4289 return VK_EVENT_RESET;
4290 }
4291
4292 VkResult radv_SetEvent(
4293 VkDevice _device,
4294 VkEvent _event)
4295 {
4296 RADV_FROM_HANDLE(radv_event, event, _event);
4297 *event->map = 1;
4298
4299 return VK_SUCCESS;
4300 }
4301
4302 VkResult radv_ResetEvent(
4303 VkDevice _device,
4304 VkEvent _event)
4305 {
4306 RADV_FROM_HANDLE(radv_event, event, _event);
4307 *event->map = 0;
4308
4309 return VK_SUCCESS;
4310 }
4311
4312 VkResult radv_CreateBuffer(
4313 VkDevice _device,
4314 const VkBufferCreateInfo* pCreateInfo,
4315 const VkAllocationCallbacks* pAllocator,
4316 VkBuffer* pBuffer)
4317 {
4318 RADV_FROM_HANDLE(radv_device, device, _device);
4319 struct radv_buffer *buffer;
4320
4321 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4322
4323 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4324 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4325 if (buffer == NULL)
4326 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4327
4328 buffer->size = pCreateInfo->size;
4329 buffer->usage = pCreateInfo->usage;
4330 buffer->bo = NULL;
4331 buffer->offset = 0;
4332 buffer->flags = pCreateInfo->flags;
4333
4334 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4335 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4336
4337 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4338 buffer->bo = device->ws->buffer_create(device->ws,
4339 align64(buffer->size, 4096),
4340 4096, 0, RADEON_FLAG_VIRTUAL,
4341 RADV_BO_PRIORITY_VIRTUAL);
4342 if (!buffer->bo) {
4343 vk_free2(&device->alloc, pAllocator, buffer);
4344 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4345 }
4346 }
4347
4348 *pBuffer = radv_buffer_to_handle(buffer);
4349
4350 return VK_SUCCESS;
4351 }
4352
4353 void radv_DestroyBuffer(
4354 VkDevice _device,
4355 VkBuffer _buffer,
4356 const VkAllocationCallbacks* pAllocator)
4357 {
4358 RADV_FROM_HANDLE(radv_device, device, _device);
4359 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4360
4361 if (!buffer)
4362 return;
4363
4364 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4365 device->ws->buffer_destroy(buffer->bo);
4366
4367 vk_free2(&device->alloc, pAllocator, buffer);
4368 }
4369
4370 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4371 VkDevice device,
4372 const VkBufferDeviceAddressInfoEXT* pInfo)
4373 {
4374 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4375 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4376 }
4377
4378
4379 static inline unsigned
4380 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4381 {
4382 if (stencil)
4383 return plane->surface.u.legacy.stencil_tiling_index[level];
4384 else
4385 return plane->surface.u.legacy.tiling_index[level];
4386 }
4387
4388 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4389 {
4390 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4391 }
4392
4393 static uint32_t
4394 radv_init_dcc_control_reg(struct radv_device *device,
4395 struct radv_image_view *iview)
4396 {
4397 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4398 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4399 unsigned max_compressed_block_size;
4400 unsigned independent_128b_blocks;
4401 unsigned independent_64b_blocks;
4402
4403 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4404 return 0;
4405
4406 if (!device->physical_device->rad_info.has_dedicated_vram) {
4407 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4408 * dGPU and 64 for APU because all of our APUs to date use
4409 * DIMMs which have a request granularity size of 64B while all
4410 * other chips have a 32B request size.
4411 */
4412 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4413 }
4414
4415 if (device->physical_device->rad_info.chip_class >= GFX10) {
4416 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4417 independent_64b_blocks = 0;
4418 independent_128b_blocks = 1;
4419 } else {
4420 independent_128b_blocks = 0;
4421
4422 if (iview->image->info.samples > 1) {
4423 if (iview->image->planes[0].surface.bpe == 1)
4424 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4425 else if (iview->image->planes[0].surface.bpe == 2)
4426 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4427 }
4428
4429 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4430 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4431 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4432 /* If this DCC image is potentially going to be used in texture
4433 * fetches, we need some special settings.
4434 */
4435 independent_64b_blocks = 1;
4436 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4437 } else {
4438 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4439 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4440 * big as possible for better compression state.
4441 */
4442 independent_64b_blocks = 0;
4443 max_compressed_block_size = max_uncompressed_block_size;
4444 }
4445 }
4446
4447 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4448 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4449 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4450 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4451 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4452 }
4453
4454 void
4455 radv_initialise_color_surface(struct radv_device *device,
4456 struct radv_color_buffer_info *cb,
4457 struct radv_image_view *iview)
4458 {
4459 const struct vk_format_description *desc;
4460 unsigned ntype, format, swap, endian;
4461 unsigned blend_clamp = 0, blend_bypass = 0;
4462 uint64_t va;
4463 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4464 const struct radeon_surf *surf = &plane->surface;
4465
4466 desc = vk_format_description(iview->vk_format);
4467
4468 memset(cb, 0, sizeof(*cb));
4469
4470 /* Intensity is implemented as Red, so treat it that way. */
4471 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4472
4473 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4474
4475 cb->cb_color_base = va >> 8;
4476
4477 if (device->physical_device->rad_info.chip_class >= GFX9) {
4478 struct gfx9_surf_meta_flags meta;
4479 if (iview->image->dcc_offset)
4480 meta = surf->u.gfx9.dcc;
4481 else
4482 meta = surf->u.gfx9.cmask;
4483
4484 if (device->physical_device->rad_info.chip_class >= GFX10) {
4485 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4486 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4487 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4488 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4489 } else {
4490 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4491 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4492 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4493 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4494 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4495 }
4496
4497 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4498 cb->cb_color_base |= surf->tile_swizzle;
4499 } else {
4500 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4501 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4502
4503 cb->cb_color_base += level_info->offset >> 8;
4504 if (level_info->mode == RADEON_SURF_MODE_2D)
4505 cb->cb_color_base |= surf->tile_swizzle;
4506
4507 pitch_tile_max = level_info->nblk_x / 8 - 1;
4508 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4509 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4510
4511 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4512 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4513 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4514
4515 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4516
4517 if (radv_image_has_fmask(iview->image)) {
4518 if (device->physical_device->rad_info.chip_class >= GFX7)
4519 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4520 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4521 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4522 } else {
4523 /* This must be set for fast clear to work without FMASK. */
4524 if (device->physical_device->rad_info.chip_class >= GFX7)
4525 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4526 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4527 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4528 }
4529 }
4530
4531 /* CMASK variables */
4532 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4533 va += iview->image->cmask_offset;
4534 cb->cb_color_cmask = va >> 8;
4535
4536 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4537 va += iview->image->dcc_offset;
4538
4539 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4540 device->physical_device->rad_info.chip_class <= GFX8)
4541 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4542
4543 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4544 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4545
4546 cb->cb_dcc_base = va >> 8;
4547 cb->cb_dcc_base |= dcc_tile_swizzle;
4548
4549 /* GFX10 field has the same base shift as the GFX6 field. */
4550 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4551 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4552 S_028C6C_SLICE_MAX_GFX10(max_slice);
4553
4554 if (iview->image->info.samples > 1) {
4555 unsigned log_samples = util_logbase2(iview->image->info.samples);
4556
4557 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4558 S_028C74_NUM_FRAGMENTS(log_samples);
4559 }
4560
4561 if (radv_image_has_fmask(iview->image)) {
4562 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4563 cb->cb_color_fmask = va >> 8;
4564 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4565 } else {
4566 cb->cb_color_fmask = cb->cb_color_base;
4567 }
4568
4569 ntype = radv_translate_color_numformat(iview->vk_format,
4570 desc,
4571 vk_format_get_first_non_void_channel(iview->vk_format));
4572 format = radv_translate_colorformat(iview->vk_format);
4573 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4574 radv_finishme("Illegal color\n");
4575 swap = radv_translate_colorswap(iview->vk_format, false);
4576 endian = radv_colorformat_endian_swap(format);
4577
4578 /* blend clamp should be set for all NORM/SRGB types */
4579 if (ntype == V_028C70_NUMBER_UNORM ||
4580 ntype == V_028C70_NUMBER_SNORM ||
4581 ntype == V_028C70_NUMBER_SRGB)
4582 blend_clamp = 1;
4583
4584 /* set blend bypass according to docs if SINT/UINT or
4585 8/24 COLOR variants */
4586 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4587 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4588 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4589 blend_clamp = 0;
4590 blend_bypass = 1;
4591 }
4592 #if 0
4593 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4594 (format == V_028C70_COLOR_8 ||
4595 format == V_028C70_COLOR_8_8 ||
4596 format == V_028C70_COLOR_8_8_8_8))
4597 ->color_is_int8 = true;
4598 #endif
4599 cb->cb_color_info = S_028C70_FORMAT(format) |
4600 S_028C70_COMP_SWAP(swap) |
4601 S_028C70_BLEND_CLAMP(blend_clamp) |
4602 S_028C70_BLEND_BYPASS(blend_bypass) |
4603 S_028C70_SIMPLE_FLOAT(1) |
4604 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4605 ntype != V_028C70_NUMBER_SNORM &&
4606 ntype != V_028C70_NUMBER_SRGB &&
4607 format != V_028C70_COLOR_8_24 &&
4608 format != V_028C70_COLOR_24_8) |
4609 S_028C70_NUMBER_TYPE(ntype) |
4610 S_028C70_ENDIAN(endian);
4611 if (radv_image_has_fmask(iview->image)) {
4612 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4613 if (device->physical_device->rad_info.chip_class == GFX6) {
4614 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4615 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4616 }
4617
4618 if (radv_image_is_tc_compat_cmask(iview->image)) {
4619 /* Allow the texture block to read FMASK directly
4620 * without decompressing it. This bit must be cleared
4621 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4622 * otherwise the operation doesn't happen.
4623 */
4624 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4625
4626 /* Set CMASK into a tiling format that allows the
4627 * texture block to read it.
4628 */
4629 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4630 }
4631 }
4632
4633 if (radv_image_has_cmask(iview->image) &&
4634 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4635 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4636
4637 if (radv_dcc_enabled(iview->image, iview->base_mip))
4638 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4639
4640 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4641
4642 /* This must be set for fast clear to work without FMASK. */
4643 if (!radv_image_has_fmask(iview->image) &&
4644 device->physical_device->rad_info.chip_class == GFX6) {
4645 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4646 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4647 }
4648
4649 if (device->physical_device->rad_info.chip_class >= GFX9) {
4650 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4651
4652 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4653 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4654 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4655 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4656
4657 if (device->physical_device->rad_info.chip_class >= GFX10) {
4658 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4659
4660 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4661 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4662 S_028EE0_RESOURCE_LEVEL(1);
4663 } else {
4664 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4665 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4666 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4667 }
4668
4669 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4670 S_028C68_MIP0_HEIGHT(height - 1) |
4671 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4672 }
4673 }
4674
4675 static unsigned
4676 radv_calc_decompress_on_z_planes(struct radv_device *device,
4677 struct radv_image_view *iview)
4678 {
4679 unsigned max_zplanes = 0;
4680
4681 assert(radv_image_is_tc_compat_htile(iview->image));
4682
4683 if (device->physical_device->rad_info.chip_class >= GFX9) {
4684 /* Default value for 32-bit depth surfaces. */
4685 max_zplanes = 4;
4686
4687 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4688 iview->image->info.samples > 1)
4689 max_zplanes = 2;
4690
4691 max_zplanes = max_zplanes + 1;
4692 } else {
4693 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4694 /* Do not enable Z plane compression for 16-bit depth
4695 * surfaces because isn't supported on GFX8. Only
4696 * 32-bit depth surfaces are supported by the hardware.
4697 * This allows to maintain shader compatibility and to
4698 * reduce the number of depth decompressions.
4699 */
4700 max_zplanes = 1;
4701 } else {
4702 if (iview->image->info.samples <= 1)
4703 max_zplanes = 5;
4704 else if (iview->image->info.samples <= 4)
4705 max_zplanes = 3;
4706 else
4707 max_zplanes = 2;
4708 }
4709 }
4710
4711 return max_zplanes;
4712 }
4713
4714 void
4715 radv_initialise_ds_surface(struct radv_device *device,
4716 struct radv_ds_buffer_info *ds,
4717 struct radv_image_view *iview)
4718 {
4719 unsigned level = iview->base_mip;
4720 unsigned format, stencil_format;
4721 uint64_t va, s_offs, z_offs;
4722 bool stencil_only = false;
4723 const struct radv_image_plane *plane = &iview->image->planes[0];
4724 const struct radeon_surf *surf = &plane->surface;
4725
4726 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4727
4728 memset(ds, 0, sizeof(*ds));
4729 switch (iview->image->vk_format) {
4730 case VK_FORMAT_D24_UNORM_S8_UINT:
4731 case VK_FORMAT_X8_D24_UNORM_PACK32:
4732 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4733 ds->offset_scale = 2.0f;
4734 break;
4735 case VK_FORMAT_D16_UNORM:
4736 case VK_FORMAT_D16_UNORM_S8_UINT:
4737 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4738 ds->offset_scale = 4.0f;
4739 break;
4740 case VK_FORMAT_D32_SFLOAT:
4741 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4742 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4743 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4744 ds->offset_scale = 1.0f;
4745 break;
4746 case VK_FORMAT_S8_UINT:
4747 stencil_only = true;
4748 break;
4749 default:
4750 break;
4751 }
4752
4753 format = radv_translate_dbformat(iview->image->vk_format);
4754 stencil_format = surf->has_stencil ?
4755 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4756
4757 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4758 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4759 S_028008_SLICE_MAX(max_slice);
4760 if (device->physical_device->rad_info.chip_class >= GFX10) {
4761 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4762 S_028008_SLICE_MAX_HI(max_slice >> 11);
4763 }
4764
4765 ds->db_htile_data_base = 0;
4766 ds->db_htile_surface = 0;
4767
4768 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4769 s_offs = z_offs = va;
4770
4771 if (device->physical_device->rad_info.chip_class >= GFX9) {
4772 assert(surf->u.gfx9.surf_offset == 0);
4773 s_offs += surf->u.gfx9.stencil_offset;
4774
4775 ds->db_z_info = S_028038_FORMAT(format) |
4776 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4777 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4778 S_028038_MAXMIP(iview->image->info.levels - 1) |
4779 S_028038_ZRANGE_PRECISION(1);
4780 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4781 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4782
4783 if (device->physical_device->rad_info.chip_class == GFX9) {
4784 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4785 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4786 }
4787
4788 ds->db_depth_view |= S_028008_MIPID(level);
4789 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4790 S_02801C_Y_MAX(iview->image->info.height - 1);
4791
4792 if (radv_htile_enabled(iview->image, level)) {
4793 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4794
4795 if (radv_image_is_tc_compat_htile(iview->image)) {
4796 unsigned max_zplanes =
4797 radv_calc_decompress_on_z_planes(device, iview);
4798
4799 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4800
4801 if (device->physical_device->rad_info.chip_class >= GFX10) {
4802 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4803 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4804 } else {
4805 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4806 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4807 }
4808 }
4809
4810 if (!surf->has_stencil)
4811 /* Use all of the htile_buffer for depth if there's no stencil. */
4812 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4813 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4814 iview->image->htile_offset;
4815 ds->db_htile_data_base = va >> 8;
4816 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4817 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4818
4819 if (device->physical_device->rad_info.chip_class == GFX9) {
4820 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4821 }
4822 }
4823 } else {
4824 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4825
4826 if (stencil_only)
4827 level_info = &surf->u.legacy.stencil_level[level];
4828
4829 z_offs += surf->u.legacy.level[level].offset;
4830 s_offs += surf->u.legacy.stencil_level[level].offset;
4831
4832 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4833 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4834 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4835
4836 if (iview->image->info.samples > 1)
4837 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4838
4839 if (device->physical_device->rad_info.chip_class >= GFX7) {
4840 struct radeon_info *info = &device->physical_device->rad_info;
4841 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4842 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4843 unsigned macro_index = surf->u.legacy.macro_tile_index;
4844 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4845 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4846 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4847
4848 if (stencil_only)
4849 tile_mode = stencil_tile_mode;
4850
4851 ds->db_depth_info |=
4852 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4853 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4854 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4855 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4856 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4857 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4858 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4859 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4860 } else {
4861 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4862 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4863 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4864 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4865 if (stencil_only)
4866 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4867 }
4868
4869 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4870 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4871 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4872
4873 if (radv_htile_enabled(iview->image, level)) {
4874 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4875
4876 if (!surf->has_stencil &&
4877 !radv_image_is_tc_compat_htile(iview->image))
4878 /* Use all of the htile_buffer for depth if there's no stencil. */
4879 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4880
4881 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4882 iview->image->htile_offset;
4883 ds->db_htile_data_base = va >> 8;
4884 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4885
4886 if (radv_image_is_tc_compat_htile(iview->image)) {
4887 unsigned max_zplanes =
4888 radv_calc_decompress_on_z_planes(device, iview);
4889
4890 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4891 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4892 }
4893 }
4894 }
4895
4896 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4897 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4898 }
4899
4900 VkResult radv_CreateFramebuffer(
4901 VkDevice _device,
4902 const VkFramebufferCreateInfo* pCreateInfo,
4903 const VkAllocationCallbacks* pAllocator,
4904 VkFramebuffer* pFramebuffer)
4905 {
4906 RADV_FROM_HANDLE(radv_device, device, _device);
4907 struct radv_framebuffer *framebuffer;
4908 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4909 vk_find_struct_const(pCreateInfo->pNext,
4910 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4911
4912 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4913
4914 size_t size = sizeof(*framebuffer);
4915 if (!imageless_create_info)
4916 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4917 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4918 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4919 if (framebuffer == NULL)
4920 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4921
4922 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4923 framebuffer->width = pCreateInfo->width;
4924 framebuffer->height = pCreateInfo->height;
4925 framebuffer->layers = pCreateInfo->layers;
4926 if (imageless_create_info) {
4927 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4928 const VkFramebufferAttachmentImageInfoKHR *attachment =
4929 imageless_create_info->pAttachmentImageInfos + i;
4930 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4931 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4932 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4933 }
4934 } else {
4935 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4936 VkImageView _iview = pCreateInfo->pAttachments[i];
4937 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4938 framebuffer->attachments[i] = iview;
4939 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4940 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4941 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4942 }
4943 }
4944
4945 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4946 return VK_SUCCESS;
4947 }
4948
4949 void radv_DestroyFramebuffer(
4950 VkDevice _device,
4951 VkFramebuffer _fb,
4952 const VkAllocationCallbacks* pAllocator)
4953 {
4954 RADV_FROM_HANDLE(radv_device, device, _device);
4955 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4956
4957 if (!fb)
4958 return;
4959 vk_free2(&device->alloc, pAllocator, fb);
4960 }
4961
4962 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4963 {
4964 switch (address_mode) {
4965 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4966 return V_008F30_SQ_TEX_WRAP;
4967 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4968 return V_008F30_SQ_TEX_MIRROR;
4969 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4970 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4971 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4972 return V_008F30_SQ_TEX_CLAMP_BORDER;
4973 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4974 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4975 default:
4976 unreachable("illegal tex wrap mode");
4977 break;
4978 }
4979 }
4980
4981 static unsigned
4982 radv_tex_compare(VkCompareOp op)
4983 {
4984 switch (op) {
4985 case VK_COMPARE_OP_NEVER:
4986 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4987 case VK_COMPARE_OP_LESS:
4988 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4989 case VK_COMPARE_OP_EQUAL:
4990 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4991 case VK_COMPARE_OP_LESS_OR_EQUAL:
4992 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4993 case VK_COMPARE_OP_GREATER:
4994 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4995 case VK_COMPARE_OP_NOT_EQUAL:
4996 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4997 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4998 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4999 case VK_COMPARE_OP_ALWAYS:
5000 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
5001 default:
5002 unreachable("illegal compare mode");
5003 break;
5004 }
5005 }
5006
5007 static unsigned
5008 radv_tex_filter(VkFilter filter, unsigned max_ansio)
5009 {
5010 switch (filter) {
5011 case VK_FILTER_NEAREST:
5012 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
5013 V_008F38_SQ_TEX_XY_FILTER_POINT);
5014 case VK_FILTER_LINEAR:
5015 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
5016 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
5017 case VK_FILTER_CUBIC_IMG:
5018 default:
5019 fprintf(stderr, "illegal texture filter");
5020 return 0;
5021 }
5022 }
5023
5024 static unsigned
5025 radv_tex_mipfilter(VkSamplerMipmapMode mode)
5026 {
5027 switch (mode) {
5028 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
5029 return V_008F38_SQ_TEX_Z_FILTER_POINT;
5030 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
5031 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
5032 default:
5033 return V_008F38_SQ_TEX_Z_FILTER_NONE;
5034 }
5035 }
5036
5037 static unsigned
5038 radv_tex_bordercolor(VkBorderColor bcolor)
5039 {
5040 switch (bcolor) {
5041 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
5042 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
5043 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
5044 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
5045 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
5046 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
5047 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
5048 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
5049 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
5050 default:
5051 break;
5052 }
5053 return 0;
5054 }
5055
5056 static unsigned
5057 radv_tex_aniso_filter(unsigned filter)
5058 {
5059 if (filter < 2)
5060 return 0;
5061 if (filter < 4)
5062 return 1;
5063 if (filter < 8)
5064 return 2;
5065 if (filter < 16)
5066 return 3;
5067 return 4;
5068 }
5069
5070 static unsigned
5071 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
5072 {
5073 switch (mode) {
5074 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
5075 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5076 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5077 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5078 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5079 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5080 default:
5081 break;
5082 }
5083 return 0;
5084 }
5085
5086 static uint32_t
5087 radv_get_max_anisotropy(struct radv_device *device,
5088 const VkSamplerCreateInfo *pCreateInfo)
5089 {
5090 if (device->force_aniso >= 0)
5091 return device->force_aniso;
5092
5093 if (pCreateInfo->anisotropyEnable &&
5094 pCreateInfo->maxAnisotropy > 1.0f)
5095 return (uint32_t)pCreateInfo->maxAnisotropy;
5096
5097 return 0;
5098 }
5099
5100 static void
5101 radv_init_sampler(struct radv_device *device,
5102 struct radv_sampler *sampler,
5103 const VkSamplerCreateInfo *pCreateInfo)
5104 {
5105 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5106 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5107 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5108 device->physical_device->rad_info.chip_class == GFX9;
5109 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5110
5111 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5112 vk_find_struct_const(pCreateInfo->pNext,
5113 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5114 if (sampler_reduction)
5115 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5116
5117 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5118 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5119 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5120 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5121 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5122 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5123 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5124 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5125 S_008F30_DISABLE_CUBE_WRAP(0) |
5126 S_008F30_COMPAT_MODE(compat_mode) |
5127 S_008F30_FILTER_MODE(filter_mode));
5128 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5129 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5130 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5131 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5132 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5133 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5134 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5135 S_008F38_MIP_POINT_PRECLAMP(0));
5136 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5137 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5138
5139 if (device->physical_device->rad_info.chip_class >= GFX10) {
5140 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5141 } else {
5142 sampler->state[2] |=
5143 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5144 S_008F38_FILTER_PREC_FIX(1) |
5145 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5146 }
5147 }
5148
5149 VkResult radv_CreateSampler(
5150 VkDevice _device,
5151 const VkSamplerCreateInfo* pCreateInfo,
5152 const VkAllocationCallbacks* pAllocator,
5153 VkSampler* pSampler)
5154 {
5155 RADV_FROM_HANDLE(radv_device, device, _device);
5156 struct radv_sampler *sampler;
5157
5158 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5159 vk_find_struct_const(pCreateInfo->pNext,
5160 SAMPLER_YCBCR_CONVERSION_INFO);
5161
5162 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5163
5164 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5165 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5166 if (!sampler)
5167 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5168
5169 radv_init_sampler(device, sampler, pCreateInfo);
5170
5171 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5172 *pSampler = radv_sampler_to_handle(sampler);
5173
5174 return VK_SUCCESS;
5175 }
5176
5177 void radv_DestroySampler(
5178 VkDevice _device,
5179 VkSampler _sampler,
5180 const VkAllocationCallbacks* pAllocator)
5181 {
5182 RADV_FROM_HANDLE(radv_device, device, _device);
5183 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5184
5185 if (!sampler)
5186 return;
5187 vk_free2(&device->alloc, pAllocator, sampler);
5188 }
5189
5190 /* vk_icd.h does not declare this function, so we declare it here to
5191 * suppress Wmissing-prototypes.
5192 */
5193 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5194 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5195
5196 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5197 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5198 {
5199 /* For the full details on loader interface versioning, see
5200 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5201 * What follows is a condensed summary, to help you navigate the large and
5202 * confusing official doc.
5203 *
5204 * - Loader interface v0 is incompatible with later versions. We don't
5205 * support it.
5206 *
5207 * - In loader interface v1:
5208 * - The first ICD entrypoint called by the loader is
5209 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5210 * entrypoint.
5211 * - The ICD must statically expose no other Vulkan symbol unless it is
5212 * linked with -Bsymbolic.
5213 * - Each dispatchable Vulkan handle created by the ICD must be
5214 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5215 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5216 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5217 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5218 * such loader-managed surfaces.
5219 *
5220 * - Loader interface v2 differs from v1 in:
5221 * - The first ICD entrypoint called by the loader is
5222 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5223 * statically expose this entrypoint.
5224 *
5225 * - Loader interface v3 differs from v2 in:
5226 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5227 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5228 * because the loader no longer does so.
5229 */
5230 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5231 return VK_SUCCESS;
5232 }
5233
5234 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5235 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5236 int *pFD)
5237 {
5238 RADV_FROM_HANDLE(radv_device, device, _device);
5239 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5240
5241 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5242
5243 /* At the moment, we support only the below handle types. */
5244 assert(pGetFdInfo->handleType ==
5245 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5246 pGetFdInfo->handleType ==
5247 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5248
5249 bool ret = radv_get_memory_fd(device, memory, pFD);
5250 if (ret == false)
5251 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5252 return VK_SUCCESS;
5253 }
5254
5255 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5256 VkExternalMemoryHandleTypeFlagBits handleType,
5257 int fd,
5258 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5259 {
5260 RADV_FROM_HANDLE(radv_device, device, _device);
5261
5262 switch (handleType) {
5263 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5264 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5265 return VK_SUCCESS;
5266
5267 default:
5268 /* The valid usage section for this function says:
5269 *
5270 * "handleType must not be one of the handle types defined as
5271 * opaque."
5272 *
5273 * So opaque handle types fall into the default "unsupported" case.
5274 */
5275 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5276 }
5277 }
5278
5279 static VkResult radv_import_opaque_fd(struct radv_device *device,
5280 int fd,
5281 uint32_t *syncobj)
5282 {
5283 uint32_t syncobj_handle = 0;
5284 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5285 if (ret != 0)
5286 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5287
5288 if (*syncobj)
5289 device->ws->destroy_syncobj(device->ws, *syncobj);
5290
5291 *syncobj = syncobj_handle;
5292 close(fd);
5293
5294 return VK_SUCCESS;
5295 }
5296
5297 static VkResult radv_import_sync_fd(struct radv_device *device,
5298 int fd,
5299 uint32_t *syncobj)
5300 {
5301 /* If we create a syncobj we do it locally so that if we have an error, we don't
5302 * leave a syncobj in an undetermined state in the fence. */
5303 uint32_t syncobj_handle = *syncobj;
5304 if (!syncobj_handle) {
5305 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5306 if (ret) {
5307 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5308 }
5309 }
5310
5311 if (fd == -1) {
5312 device->ws->signal_syncobj(device->ws, syncobj_handle);
5313 } else {
5314 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5315 if (ret != 0)
5316 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5317 }
5318
5319 *syncobj = syncobj_handle;
5320 if (fd != -1)
5321 close(fd);
5322
5323 return VK_SUCCESS;
5324 }
5325
5326 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5327 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5328 {
5329 RADV_FROM_HANDLE(radv_device, device, _device);
5330 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5331 uint32_t *syncobj_dst = NULL;
5332
5333 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5334 syncobj_dst = &sem->temp_syncobj;
5335 } else {
5336 syncobj_dst = &sem->syncobj;
5337 }
5338
5339 switch(pImportSemaphoreFdInfo->handleType) {
5340 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5341 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5342 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5343 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5344 default:
5345 unreachable("Unhandled semaphore handle type");
5346 }
5347 }
5348
5349 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5350 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5351 int *pFd)
5352 {
5353 RADV_FROM_HANDLE(radv_device, device, _device);
5354 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5355 int ret;
5356 uint32_t syncobj_handle;
5357
5358 if (sem->temp_syncobj)
5359 syncobj_handle = sem->temp_syncobj;
5360 else
5361 syncobj_handle = sem->syncobj;
5362
5363 switch(pGetFdInfo->handleType) {
5364 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5365 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5366 break;
5367 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5368 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5369 if (!ret) {
5370 if (sem->temp_syncobj) {
5371 close (sem->temp_syncobj);
5372 sem->temp_syncobj = 0;
5373 } else {
5374 device->ws->reset_syncobj(device->ws, syncobj_handle);
5375 }
5376 }
5377 break;
5378 default:
5379 unreachable("Unhandled semaphore handle type");
5380 }
5381
5382 if (ret)
5383 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5384 return VK_SUCCESS;
5385 }
5386
5387 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5388 VkPhysicalDevice physicalDevice,
5389 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5390 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5391 {
5392 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5393
5394 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5395 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5396 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5397 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5398 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5399 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5400 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5401 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5402 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5403 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5404 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5405 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5406 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5407 } else {
5408 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5409 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5410 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5411 }
5412 }
5413
5414 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5415 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5416 {
5417 RADV_FROM_HANDLE(radv_device, device, _device);
5418 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5419 uint32_t *syncobj_dst = NULL;
5420
5421
5422 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5423 syncobj_dst = &fence->temp_syncobj;
5424 } else {
5425 syncobj_dst = &fence->syncobj;
5426 }
5427
5428 switch(pImportFenceFdInfo->handleType) {
5429 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5430 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5431 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5432 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5433 default:
5434 unreachable("Unhandled fence handle type");
5435 }
5436 }
5437
5438 VkResult radv_GetFenceFdKHR(VkDevice _device,
5439 const VkFenceGetFdInfoKHR *pGetFdInfo,
5440 int *pFd)
5441 {
5442 RADV_FROM_HANDLE(radv_device, device, _device);
5443 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5444 int ret;
5445 uint32_t syncobj_handle;
5446
5447 if (fence->temp_syncobj)
5448 syncobj_handle = fence->temp_syncobj;
5449 else
5450 syncobj_handle = fence->syncobj;
5451
5452 switch(pGetFdInfo->handleType) {
5453 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5454 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5455 break;
5456 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5457 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5458 if (!ret) {
5459 if (fence->temp_syncobj) {
5460 close (fence->temp_syncobj);
5461 fence->temp_syncobj = 0;
5462 } else {
5463 device->ws->reset_syncobj(device->ws, syncobj_handle);
5464 }
5465 }
5466 break;
5467 default:
5468 unreachable("Unhandled fence handle type");
5469 }
5470
5471 if (ret)
5472 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5473 return VK_SUCCESS;
5474 }
5475
5476 void radv_GetPhysicalDeviceExternalFenceProperties(
5477 VkPhysicalDevice physicalDevice,
5478 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5479 VkExternalFenceProperties *pExternalFenceProperties)
5480 {
5481 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5482
5483 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5484 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5485 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5486 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5487 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5488 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5489 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5490 } else {
5491 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5492 pExternalFenceProperties->compatibleHandleTypes = 0;
5493 pExternalFenceProperties->externalFenceFeatures = 0;
5494 }
5495 }
5496
5497 VkResult
5498 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5499 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5500 const VkAllocationCallbacks* pAllocator,
5501 VkDebugReportCallbackEXT* pCallback)
5502 {
5503 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5504 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5505 pCreateInfo, pAllocator, &instance->alloc,
5506 pCallback);
5507 }
5508
5509 void
5510 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5511 VkDebugReportCallbackEXT _callback,
5512 const VkAllocationCallbacks* pAllocator)
5513 {
5514 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5515 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5516 _callback, pAllocator, &instance->alloc);
5517 }
5518
5519 void
5520 radv_DebugReportMessageEXT(VkInstance _instance,
5521 VkDebugReportFlagsEXT flags,
5522 VkDebugReportObjectTypeEXT objectType,
5523 uint64_t object,
5524 size_t location,
5525 int32_t messageCode,
5526 const char* pLayerPrefix,
5527 const char* pMessage)
5528 {
5529 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5530 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5531 object, location, messageCode, pLayerPrefix, pMessage);
5532 }
5533
5534 void
5535 radv_GetDeviceGroupPeerMemoryFeatures(
5536 VkDevice device,
5537 uint32_t heapIndex,
5538 uint32_t localDeviceIndex,
5539 uint32_t remoteDeviceIndex,
5540 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5541 {
5542 assert(localDeviceIndex == remoteDeviceIndex);
5543
5544 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5545 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5546 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5547 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5548 }
5549
5550 static const VkTimeDomainEXT radv_time_domains[] = {
5551 VK_TIME_DOMAIN_DEVICE_EXT,
5552 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5553 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5554 };
5555
5556 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5557 VkPhysicalDevice physicalDevice,
5558 uint32_t *pTimeDomainCount,
5559 VkTimeDomainEXT *pTimeDomains)
5560 {
5561 int d;
5562 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5563
5564 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5565 vk_outarray_append(&out, i) {
5566 *i = radv_time_domains[d];
5567 }
5568 }
5569
5570 return vk_outarray_status(&out);
5571 }
5572
5573 static uint64_t
5574 radv_clock_gettime(clockid_t clock_id)
5575 {
5576 struct timespec current;
5577 int ret;
5578
5579 ret = clock_gettime(clock_id, &current);
5580 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5581 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5582 if (ret < 0)
5583 return 0;
5584
5585 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5586 }
5587
5588 VkResult radv_GetCalibratedTimestampsEXT(
5589 VkDevice _device,
5590 uint32_t timestampCount,
5591 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5592 uint64_t *pTimestamps,
5593 uint64_t *pMaxDeviation)
5594 {
5595 RADV_FROM_HANDLE(radv_device, device, _device);
5596 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5597 int d;
5598 uint64_t begin, end;
5599 uint64_t max_clock_period = 0;
5600
5601 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5602
5603 for (d = 0; d < timestampCount; d++) {
5604 switch (pTimestampInfos[d].timeDomain) {
5605 case VK_TIME_DOMAIN_DEVICE_EXT:
5606 pTimestamps[d] = device->ws->query_value(device->ws,
5607 RADEON_TIMESTAMP);
5608 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5609 max_clock_period = MAX2(max_clock_period, device_period);
5610 break;
5611 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5612 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5613 max_clock_period = MAX2(max_clock_period, 1);
5614 break;
5615
5616 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5617 pTimestamps[d] = begin;
5618 break;
5619 default:
5620 pTimestamps[d] = 0;
5621 break;
5622 }
5623 }
5624
5625 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5626
5627 /*
5628 * The maximum deviation is the sum of the interval over which we
5629 * perform the sampling and the maximum period of any sampled
5630 * clock. That's because the maximum skew between any two sampled
5631 * clock edges is when the sampled clock with the largest period is
5632 * sampled at the end of that period but right at the beginning of the
5633 * sampling interval and some other clock is sampled right at the
5634 * begining of its sampling period and right at the end of the
5635 * sampling interval. Let's assume the GPU has the longest clock
5636 * period and that the application is sampling GPU and monotonic:
5637 *
5638 * s e
5639 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5640 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5641 *
5642 * g
5643 * 0 1 2 3
5644 * GPU -----_____-----_____-----_____-----_____
5645 *
5646 * m
5647 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5648 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5649 *
5650 * Interval <----------------->
5651 * Deviation <-------------------------->
5652 *
5653 * s = read(raw) 2
5654 * g = read(GPU) 1
5655 * m = read(monotonic) 2
5656 * e = read(raw) b
5657 *
5658 * We round the sample interval up by one tick to cover sampling error
5659 * in the interval clock
5660 */
5661
5662 uint64_t sample_interval = end - begin + 1;
5663
5664 *pMaxDeviation = sample_interval + max_clock_period;
5665
5666 return VK_SUCCESS;
5667 }
5668
5669 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5670 VkPhysicalDevice physicalDevice,
5671 VkSampleCountFlagBits samples,
5672 VkMultisamplePropertiesEXT* pMultisampleProperties)
5673 {
5674 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5675 VK_SAMPLE_COUNT_4_BIT |
5676 VK_SAMPLE_COUNT_8_BIT)) {
5677 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5678 } else {
5679 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5680 }
5681 }