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radv: Implement VK_EXT_buffer_device_address.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 radv_physical_device_init_mem_types(device);
373 radv_fill_device_extension_table(device, &device->supported_extensions);
374
375 device->bus_info = *drm_device->businfo.pci;
376
377 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
378 ac_print_gpu_info(&device->rad_info);
379
380 /* The WSI is structured as a layer on top of the driver, so this has
381 * to be the last part of initialization (at least until we get other
382 * semi-layers).
383 */
384 result = radv_init_wsi(device);
385 if (result != VK_SUCCESS) {
386 device->ws->destroy(device->ws);
387 vk_error(instance, result);
388 goto fail;
389 }
390
391 return VK_SUCCESS;
392
393 fail:
394 close(fd);
395 if (master_fd != -1)
396 close(master_fd);
397 return result;
398 }
399
400 static void
401 radv_physical_device_finish(struct radv_physical_device *device)
402 {
403 radv_finish_wsi(device);
404 device->ws->destroy(device->ws);
405 disk_cache_destroy(device->disk_cache);
406 close(device->local_fd);
407 if (device->master_fd != -1)
408 close(device->master_fd);
409 }
410
411 static void *
412 default_alloc_func(void *pUserData, size_t size, size_t align,
413 VkSystemAllocationScope allocationScope)
414 {
415 return malloc(size);
416 }
417
418 static void *
419 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
420 size_t align, VkSystemAllocationScope allocationScope)
421 {
422 return realloc(pOriginal, size);
423 }
424
425 static void
426 default_free_func(void *pUserData, void *pMemory)
427 {
428 free(pMemory);
429 }
430
431 static const VkAllocationCallbacks default_alloc = {
432 .pUserData = NULL,
433 .pfnAllocation = default_alloc_func,
434 .pfnReallocation = default_realloc_func,
435 .pfnFree = default_free_func,
436 };
437
438 static const struct debug_control radv_debug_options[] = {
439 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
440 {"nodcc", RADV_DEBUG_NO_DCC},
441 {"shaders", RADV_DEBUG_DUMP_SHADERS},
442 {"nocache", RADV_DEBUG_NO_CACHE},
443 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
444 {"nohiz", RADV_DEBUG_NO_HIZ},
445 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
446 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
447 {"allbos", RADV_DEBUG_ALL_BOS},
448 {"noibs", RADV_DEBUG_NO_IBS},
449 {"spirv", RADV_DEBUG_DUMP_SPIRV},
450 {"vmfaults", RADV_DEBUG_VM_FAULTS},
451 {"zerovram", RADV_DEBUG_ZERO_VRAM},
452 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
453 {"nosisched", RADV_DEBUG_NO_SISCHED},
454 {"preoptir", RADV_DEBUG_PREOPTIR},
455 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
456 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
457 {"info", RADV_DEBUG_INFO},
458 {"errors", RADV_DEBUG_ERRORS},
459 {"startup", RADV_DEBUG_STARTUP},
460 {"checkir", RADV_DEBUG_CHECKIR},
461 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
462 {"nobinning", RADV_DEBUG_NOBINNING},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_debug_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_debug_options[id].string;
471 }
472
473 static const struct debug_control radv_perftest_options[] = {
474 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
475 {"sisched", RADV_PERFTEST_SISCHED},
476 {"localbos", RADV_PERFTEST_LOCAL_BOS},
477 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
478 {NULL, 0}
479 };
480
481 const char *
482 radv_get_perftest_option_name(int id)
483 {
484 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
485 return radv_perftest_options[id].string;
486 }
487
488 static void
489 radv_handle_per_app_options(struct radv_instance *instance,
490 const VkApplicationInfo *info)
491 {
492 const char *name = info ? info->pApplicationName : NULL;
493
494 if (!name)
495 return;
496
497 if (!strcmp(name, "Talos - Linux - 32bit") ||
498 !strcmp(name, "Talos - Linux - 64bit")) {
499 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
500 /* Force enable LLVM sisched for Talos because it looks
501 * safe and it gives few more FPS.
502 */
503 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
504 }
505 } else if (!strcmp(name, "DOOM_VFR")) {
506 /* Work around a Doom VFR game bug */
507 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
508 }
509 }
510
511 static int radv_get_instance_extension_index(const char *name)
512 {
513 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
514 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
515 return i;
516 }
517 return -1;
518 }
519
520
521 VkResult radv_CreateInstance(
522 const VkInstanceCreateInfo* pCreateInfo,
523 const VkAllocationCallbacks* pAllocator,
524 VkInstance* pInstance)
525 {
526 struct radv_instance *instance;
527 VkResult result;
528
529 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
530
531 uint32_t client_version;
532 if (pCreateInfo->pApplicationInfo &&
533 pCreateInfo->pApplicationInfo->apiVersion != 0) {
534 client_version = pCreateInfo->pApplicationInfo->apiVersion;
535 } else {
536 client_version = VK_API_VERSION_1_0;
537 }
538
539 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
540 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
541 if (!instance)
542 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
543
544 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
545
546 if (pAllocator)
547 instance->alloc = *pAllocator;
548 else
549 instance->alloc = default_alloc;
550
551 instance->apiVersion = client_version;
552 instance->physicalDeviceCount = -1;
553
554 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
555 radv_debug_options);
556
557 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
558 radv_perftest_options);
559
560
561 if (instance->debug_flags & RADV_DEBUG_STARTUP)
562 radv_logi("Created an instance");
563
564 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
565 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
566 int index = radv_get_instance_extension_index(ext_name);
567
568 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
569 vk_free2(&default_alloc, pAllocator, instance);
570 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
571 }
572
573 instance->enabled_extensions.extensions[index] = true;
574 }
575
576 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
577 if (result != VK_SUCCESS) {
578 vk_free2(&default_alloc, pAllocator, instance);
579 return vk_error(instance, result);
580 }
581
582 _mesa_locale_init();
583
584 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
585
586 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
587
588 *pInstance = radv_instance_to_handle(instance);
589
590 return VK_SUCCESS;
591 }
592
593 void radv_DestroyInstance(
594 VkInstance _instance,
595 const VkAllocationCallbacks* pAllocator)
596 {
597 RADV_FROM_HANDLE(radv_instance, instance, _instance);
598
599 if (!instance)
600 return;
601
602 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
603 radv_physical_device_finish(instance->physicalDevices + i);
604 }
605
606 VG(VALGRIND_DESTROY_MEMPOOL(instance));
607
608 _mesa_locale_fini();
609
610 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
611
612 vk_free(&instance->alloc, instance);
613 }
614
615 static VkResult
616 radv_enumerate_devices(struct radv_instance *instance)
617 {
618 /* TODO: Check for more devices ? */
619 drmDevicePtr devices[8];
620 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
621 int max_devices;
622
623 instance->physicalDeviceCount = 0;
624
625 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
626
627 if (instance->debug_flags & RADV_DEBUG_STARTUP)
628 radv_logi("Found %d drm nodes", max_devices);
629
630 if (max_devices < 1)
631 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
632
633 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
634 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
635 devices[i]->bustype == DRM_BUS_PCI &&
636 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
637
638 result = radv_physical_device_init(instance->physicalDevices +
639 instance->physicalDeviceCount,
640 instance,
641 devices[i]);
642 if (result == VK_SUCCESS)
643 ++instance->physicalDeviceCount;
644 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
645 break;
646 }
647 }
648 drmFreeDevices(devices, max_devices);
649
650 return result;
651 }
652
653 VkResult radv_EnumeratePhysicalDevices(
654 VkInstance _instance,
655 uint32_t* pPhysicalDeviceCount,
656 VkPhysicalDevice* pPhysicalDevices)
657 {
658 RADV_FROM_HANDLE(radv_instance, instance, _instance);
659 VkResult result;
660
661 if (instance->physicalDeviceCount < 0) {
662 result = radv_enumerate_devices(instance);
663 if (result != VK_SUCCESS &&
664 result != VK_ERROR_INCOMPATIBLE_DRIVER)
665 return result;
666 }
667
668 if (!pPhysicalDevices) {
669 *pPhysicalDeviceCount = instance->physicalDeviceCount;
670 } else {
671 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
672 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
673 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
674 }
675
676 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
677 : VK_SUCCESS;
678 }
679
680 VkResult radv_EnumeratePhysicalDeviceGroups(
681 VkInstance _instance,
682 uint32_t* pPhysicalDeviceGroupCount,
683 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
684 {
685 RADV_FROM_HANDLE(radv_instance, instance, _instance);
686 VkResult result;
687
688 if (instance->physicalDeviceCount < 0) {
689 result = radv_enumerate_devices(instance);
690 if (result != VK_SUCCESS &&
691 result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 return result;
693 }
694
695 if (!pPhysicalDeviceGroupProperties) {
696 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
697 } else {
698 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
699 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
700 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
701 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
702 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
703 }
704 }
705 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
706 : VK_SUCCESS;
707 }
708
709 void radv_GetPhysicalDeviceFeatures(
710 VkPhysicalDevice physicalDevice,
711 VkPhysicalDeviceFeatures* pFeatures)
712 {
713 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
714 memset(pFeatures, 0, sizeof(*pFeatures));
715
716 *pFeatures = (VkPhysicalDeviceFeatures) {
717 .robustBufferAccess = true,
718 .fullDrawIndexUint32 = true,
719 .imageCubeArray = true,
720 .independentBlend = true,
721 .geometryShader = true,
722 .tessellationShader = true,
723 .sampleRateShading = true,
724 .dualSrcBlend = true,
725 .logicOp = true,
726 .multiDrawIndirect = true,
727 .drawIndirectFirstInstance = true,
728 .depthClamp = true,
729 .depthBiasClamp = true,
730 .fillModeNonSolid = true,
731 .depthBounds = true,
732 .wideLines = true,
733 .largePoints = true,
734 .alphaToOne = true,
735 .multiViewport = true,
736 .samplerAnisotropy = true,
737 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
738 pdevice->rad_info.family == CHIP_STONEY,
739 .textureCompressionASTC_LDR = false,
740 .textureCompressionBC = true,
741 .occlusionQueryPrecise = true,
742 .pipelineStatisticsQuery = true,
743 .vertexPipelineStoresAndAtomics = true,
744 .fragmentStoresAndAtomics = true,
745 .shaderTessellationAndGeometryPointSize = true,
746 .shaderImageGatherExtended = true,
747 .shaderStorageImageExtendedFormats = true,
748 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
749 .shaderUniformBufferArrayDynamicIndexing = true,
750 .shaderSampledImageArrayDynamicIndexing = true,
751 .shaderStorageBufferArrayDynamicIndexing = true,
752 .shaderStorageImageArrayDynamicIndexing = true,
753 .shaderStorageImageReadWithoutFormat = true,
754 .shaderStorageImageWriteWithoutFormat = true,
755 .shaderClipDistance = true,
756 .shaderCullDistance = true,
757 .shaderFloat64 = true,
758 .shaderInt64 = true,
759 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
760 .sparseBinding = true,
761 .variableMultisampleRate = true,
762 .inheritedQueries = true,
763 };
764 }
765
766 void radv_GetPhysicalDeviceFeatures2(
767 VkPhysicalDevice physicalDevice,
768 VkPhysicalDeviceFeatures2 *pFeatures)
769 {
770 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
771 vk_foreach_struct(ext, pFeatures->pNext) {
772 switch (ext->sType) {
773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
774 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
775 features->variablePointersStorageBuffer = true;
776 features->variablePointers = true;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
780 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
781 features->multiview = true;
782 features->multiviewGeometryShader = true;
783 features->multiviewTessellationShader = true;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
787 VkPhysicalDeviceShaderDrawParameterFeatures *features =
788 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
789 features->shaderDrawParameters = true;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
793 VkPhysicalDeviceProtectedMemoryFeatures *features =
794 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
795 features->protectedMemory = false;
796 break;
797 }
798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
799 VkPhysicalDevice16BitStorageFeatures *features =
800 (VkPhysicalDevice16BitStorageFeatures*)ext;
801 bool enabled = pdevice->rad_info.chip_class >= VI;
802 features->storageBuffer16BitAccess = enabled;
803 features->uniformAndStorageBuffer16BitAccess = enabled;
804 features->storagePushConstant16 = enabled;
805 features->storageInputOutput16 = enabled;
806 break;
807 }
808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
809 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
810 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
811 features->samplerYcbcrConversion = false;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
815 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
816 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
817 features->shaderInputAttachmentArrayDynamicIndexing = true;
818 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
819 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
820 features->shaderUniformBufferArrayNonUniformIndexing = false;
821 features->shaderSampledImageArrayNonUniformIndexing = false;
822 features->shaderStorageBufferArrayNonUniformIndexing = false;
823 features->shaderStorageImageArrayNonUniformIndexing = false;
824 features->shaderInputAttachmentArrayNonUniformIndexing = false;
825 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
826 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
827 features->descriptorBindingUniformBufferUpdateAfterBind = true;
828 features->descriptorBindingSampledImageUpdateAfterBind = true;
829 features->descriptorBindingStorageImageUpdateAfterBind = true;
830 features->descriptorBindingStorageBufferUpdateAfterBind = true;
831 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
832 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
833 features->descriptorBindingUpdateUnusedWhilePending = true;
834 features->descriptorBindingPartiallyBound = true;
835 features->descriptorBindingVariableDescriptorCount = true;
836 features->runtimeDescriptorArray = true;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
840 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
841 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
842 features->conditionalRendering = true;
843 features->inheritedConditionalRendering = false;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
847 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
848 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
849 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
850 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
854 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
855 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
856 features->transformFeedback = true;
857 features->geometryStreams = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
861 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
862 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
863 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
864 break;
865 }
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
867 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
868 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
869 features->memoryPriority = VK_TRUE;
870 break;
871 }
872 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
873 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
874 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
875 features->bufferDeviceAddress = true;
876 features->bufferDeviceAddressCaptureReplay = false;
877 features->bufferDeviceAddressMultiDevice = false;
878 break;
879 }
880 default:
881 break;
882 }
883 }
884 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
885 }
886
887 void radv_GetPhysicalDeviceProperties(
888 VkPhysicalDevice physicalDevice,
889 VkPhysicalDeviceProperties* pProperties)
890 {
891 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
892 VkSampleCountFlags sample_counts = 0xf;
893
894 /* make sure that the entire descriptor set is addressable with a signed
895 * 32-bit int. So the sum of all limits scaled by descriptor size has to
896 * be at most 2 GiB. the combined image & samples object count as one of
897 * both. This limit is for the pipeline layout, not for the set layout, but
898 * there is no set limit, so we just set a pipeline limit. I don't think
899 * any app is going to hit this soon. */
900 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
901 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
902 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
903 32 /* sampler, largest when combined with image */ +
904 64 /* sampled image */ +
905 64 /* storage image */);
906
907 VkPhysicalDeviceLimits limits = {
908 .maxImageDimension1D = (1 << 14),
909 .maxImageDimension2D = (1 << 14),
910 .maxImageDimension3D = (1 << 11),
911 .maxImageDimensionCube = (1 << 14),
912 .maxImageArrayLayers = (1 << 11),
913 .maxTexelBufferElements = 128 * 1024 * 1024,
914 .maxUniformBufferRange = UINT32_MAX,
915 .maxStorageBufferRange = UINT32_MAX,
916 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
917 .maxMemoryAllocationCount = UINT32_MAX,
918 .maxSamplerAllocationCount = 64 * 1024,
919 .bufferImageGranularity = 64, /* A cache line */
920 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
921 .maxBoundDescriptorSets = MAX_SETS,
922 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
923 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
924 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
925 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
926 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
927 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
928 .maxPerStageResources = max_descriptor_set_size,
929 .maxDescriptorSetSamplers = max_descriptor_set_size,
930 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
931 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
932 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
933 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
934 .maxDescriptorSetSampledImages = max_descriptor_set_size,
935 .maxDescriptorSetStorageImages = max_descriptor_set_size,
936 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
937 .maxVertexInputAttributes = 32,
938 .maxVertexInputBindings = 32,
939 .maxVertexInputAttributeOffset = 2047,
940 .maxVertexInputBindingStride = 2048,
941 .maxVertexOutputComponents = 128,
942 .maxTessellationGenerationLevel = 64,
943 .maxTessellationPatchSize = 32,
944 .maxTessellationControlPerVertexInputComponents = 128,
945 .maxTessellationControlPerVertexOutputComponents = 128,
946 .maxTessellationControlPerPatchOutputComponents = 120,
947 .maxTessellationControlTotalOutputComponents = 4096,
948 .maxTessellationEvaluationInputComponents = 128,
949 .maxTessellationEvaluationOutputComponents = 128,
950 .maxGeometryShaderInvocations = 127,
951 .maxGeometryInputComponents = 64,
952 .maxGeometryOutputComponents = 128,
953 .maxGeometryOutputVertices = 256,
954 .maxGeometryTotalOutputComponents = 1024,
955 .maxFragmentInputComponents = 128,
956 .maxFragmentOutputAttachments = 8,
957 .maxFragmentDualSrcAttachments = 1,
958 .maxFragmentCombinedOutputResources = 8,
959 .maxComputeSharedMemorySize = 32768,
960 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
961 .maxComputeWorkGroupInvocations = 2048,
962 .maxComputeWorkGroupSize = {
963 2048,
964 2048,
965 2048
966 },
967 .subPixelPrecisionBits = 8,
968 .subTexelPrecisionBits = 8,
969 .mipmapPrecisionBits = 8,
970 .maxDrawIndexedIndexValue = UINT32_MAX,
971 .maxDrawIndirectCount = UINT32_MAX,
972 .maxSamplerLodBias = 16,
973 .maxSamplerAnisotropy = 16,
974 .maxViewports = MAX_VIEWPORTS,
975 .maxViewportDimensions = { (1 << 14), (1 << 14) },
976 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
977 .viewportSubPixelBits = 8,
978 .minMemoryMapAlignment = 4096, /* A page */
979 .minTexelBufferOffsetAlignment = 1,
980 .minUniformBufferOffsetAlignment = 4,
981 .minStorageBufferOffsetAlignment = 4,
982 .minTexelOffset = -32,
983 .maxTexelOffset = 31,
984 .minTexelGatherOffset = -32,
985 .maxTexelGatherOffset = 31,
986 .minInterpolationOffset = -2,
987 .maxInterpolationOffset = 2,
988 .subPixelInterpolationOffsetBits = 8,
989 .maxFramebufferWidth = (1 << 14),
990 .maxFramebufferHeight = (1 << 14),
991 .maxFramebufferLayers = (1 << 10),
992 .framebufferColorSampleCounts = sample_counts,
993 .framebufferDepthSampleCounts = sample_counts,
994 .framebufferStencilSampleCounts = sample_counts,
995 .framebufferNoAttachmentsSampleCounts = sample_counts,
996 .maxColorAttachments = MAX_RTS,
997 .sampledImageColorSampleCounts = sample_counts,
998 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
999 .sampledImageDepthSampleCounts = sample_counts,
1000 .sampledImageStencilSampleCounts = sample_counts,
1001 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1002 .maxSampleMaskWords = 1,
1003 .timestampComputeAndGraphics = true,
1004 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1005 .maxClipDistances = 8,
1006 .maxCullDistances = 8,
1007 .maxCombinedClipAndCullDistances = 8,
1008 .discreteQueuePriorities = 2,
1009 .pointSizeRange = { 0.125, 255.875 },
1010 .lineWidthRange = { 0.0, 7.9921875 },
1011 .pointSizeGranularity = (1.0 / 8.0),
1012 .lineWidthGranularity = (1.0 / 128.0),
1013 .strictLines = false, /* FINISHME */
1014 .standardSampleLocations = true,
1015 .optimalBufferCopyOffsetAlignment = 128,
1016 .optimalBufferCopyRowPitchAlignment = 128,
1017 .nonCoherentAtomSize = 64,
1018 };
1019
1020 *pProperties = (VkPhysicalDeviceProperties) {
1021 .apiVersion = radv_physical_device_api_version(pdevice),
1022 .driverVersion = vk_get_driver_version(),
1023 .vendorID = ATI_VENDOR_ID,
1024 .deviceID = pdevice->rad_info.pci_id,
1025 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1026 .limits = limits,
1027 .sparseProperties = {0},
1028 };
1029
1030 strcpy(pProperties->deviceName, pdevice->name);
1031 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1032 }
1033
1034 void radv_GetPhysicalDeviceProperties2(
1035 VkPhysicalDevice physicalDevice,
1036 VkPhysicalDeviceProperties2 *pProperties)
1037 {
1038 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1039 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1040
1041 vk_foreach_struct(ext, pProperties->pNext) {
1042 switch (ext->sType) {
1043 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1044 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1045 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1046 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1050 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1051 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1052 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1053 properties->deviceLUIDValid = false;
1054 break;
1055 }
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1057 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1058 properties->maxMultiviewViewCount = MAX_VIEWS;
1059 properties->maxMultiviewInstanceIndex = INT_MAX;
1060 break;
1061 }
1062 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1063 VkPhysicalDevicePointClippingProperties *properties =
1064 (VkPhysicalDevicePointClippingProperties*)ext;
1065 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1066 break;
1067 }
1068 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1069 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1070 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1071 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1072 break;
1073 }
1074 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1075 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1076 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1077 properties->minImportedHostPointerAlignment = 4096;
1078 break;
1079 }
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1081 VkPhysicalDeviceSubgroupProperties *properties =
1082 (VkPhysicalDeviceSubgroupProperties*)ext;
1083 properties->subgroupSize = 64;
1084 properties->supportedStages = VK_SHADER_STAGE_ALL;
1085 properties->supportedOperations =
1086 VK_SUBGROUP_FEATURE_BASIC_BIT |
1087 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1088 VK_SUBGROUP_FEATURE_QUAD_BIT |
1089 VK_SUBGROUP_FEATURE_VOTE_BIT;
1090 if (pdevice->rad_info.chip_class >= VI) {
1091 properties->supportedOperations |=
1092 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1093 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1094 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1095 }
1096 properties->quadOperationsInAllStages = true;
1097 break;
1098 }
1099 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1100 VkPhysicalDeviceMaintenance3Properties *properties =
1101 (VkPhysicalDeviceMaintenance3Properties*)ext;
1102 /* Make sure everything is addressable by a signed 32-bit int, and
1103 * our largest descriptors are 96 bytes. */
1104 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1105 /* Our buffer size fields allow only this much */
1106 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1110 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1111 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1112 /* GFX6-8 only support single channel min/max filter. */
1113 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1114 properties->filterMinmaxSingleComponentFormats = true;
1115 break;
1116 }
1117 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1118 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1119 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1120
1121 /* Shader engines. */
1122 properties->shaderEngineCount =
1123 pdevice->rad_info.max_se;
1124 properties->shaderArraysPerEngineCount =
1125 pdevice->rad_info.max_sh_per_se;
1126 properties->computeUnitsPerShaderArray =
1127 pdevice->rad_info.num_good_cu_per_sh;
1128 properties->simdPerComputeUnit = 4;
1129 properties->wavefrontsPerSimd =
1130 pdevice->rad_info.family == CHIP_TONGA ||
1131 pdevice->rad_info.family == CHIP_ICELAND ||
1132 pdevice->rad_info.family == CHIP_POLARIS10 ||
1133 pdevice->rad_info.family == CHIP_POLARIS11 ||
1134 pdevice->rad_info.family == CHIP_POLARIS12 ||
1135 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1136 properties->wavefrontSize = 64;
1137
1138 /* SGPR. */
1139 properties->sgprsPerSimd =
1140 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1141 properties->minSgprAllocation =
1142 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1143 properties->maxSgprAllocation =
1144 pdevice->rad_info.family == CHIP_TONGA ||
1145 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1146 properties->sgprAllocationGranularity =
1147 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1148
1149 /* VGPR. */
1150 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1151 properties->minVgprAllocation = 4;
1152 properties->maxVgprAllocation = 256;
1153 properties->vgprAllocationGranularity = 4;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1157 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1158 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1159 properties->maxVertexAttribDivisor = UINT32_MAX;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1163 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1164 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1165 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1166 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1167 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1168 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1169 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1170 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1171 properties->robustBufferAccessUpdateAfterBind = false;
1172 properties->quadDivergentImplicitLod = false;
1173
1174 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1175 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1176 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1177 32 /* sampler, largest when combined with image */ +
1178 64 /* sampled image */ +
1179 64 /* storage image */);
1180 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1181 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1182 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1183 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1184 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1185 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1186 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1187 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1188 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1189 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1190 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1191 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1192 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1193 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1194 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1195 break;
1196 }
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1198 VkPhysicalDeviceProtectedMemoryProperties *properties =
1199 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1200 properties->protectedNoFault = false;
1201 break;
1202 }
1203 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1204 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1205 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1206 properties->primitiveOverestimationSize = 0;
1207 properties->maxExtraPrimitiveOverestimationSize = 0;
1208 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1209 properties->primitiveUnderestimation = VK_FALSE;
1210 properties->conservativePointAndLineRasterization = VK_FALSE;
1211 properties->degenerateTrianglesRasterized = VK_FALSE;
1212 properties->degenerateLinesRasterized = VK_FALSE;
1213 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1214 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1218 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1219 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1220 properties->pciDomain = pdevice->bus_info.domain;
1221 properties->pciBus = pdevice->bus_info.bus;
1222 properties->pciDevice = pdevice->bus_info.dev;
1223 properties->pciFunction = pdevice->bus_info.func;
1224 break;
1225 }
1226 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1227 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1228 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1229
1230 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1231 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1232 strcpy(driver_props->driverName, "radv");
1233
1234 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1235 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1236 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1237 " (LLVM %d.%d.%d)",
1238 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1239 MESA_LLVM_VERSION_PATCH);
1240
1241 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1242 .major = 1,
1243 .minor = 1,
1244 .subminor = 2,
1245 .patch = 0,
1246 };
1247 break;
1248 }
1249 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1250 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1251 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1252 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1253 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1254 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1255 properties->maxTransformFeedbackStreamDataSize = 512;
1256 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1257 properties->maxTransformFeedbackBufferDataStride = 512;
1258 properties->transformFeedbackQueries = true;
1259 properties->transformFeedbackStreamsLinesTriangles = false;
1260 properties->transformFeedbackRasterizationStreamSelect = false;
1261 properties->transformFeedbackDraw = true;
1262 break;
1263 }
1264 default:
1265 break;
1266 }
1267 }
1268 }
1269
1270 static void radv_get_physical_device_queue_family_properties(
1271 struct radv_physical_device* pdevice,
1272 uint32_t* pCount,
1273 VkQueueFamilyProperties** pQueueFamilyProperties)
1274 {
1275 int num_queue_families = 1;
1276 int idx;
1277 if (pdevice->rad_info.num_compute_rings > 0 &&
1278 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1279 num_queue_families++;
1280
1281 if (pQueueFamilyProperties == NULL) {
1282 *pCount = num_queue_families;
1283 return;
1284 }
1285
1286 if (!*pCount)
1287 return;
1288
1289 idx = 0;
1290 if (*pCount >= 1) {
1291 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1292 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1293 VK_QUEUE_COMPUTE_BIT |
1294 VK_QUEUE_TRANSFER_BIT |
1295 VK_QUEUE_SPARSE_BINDING_BIT,
1296 .queueCount = 1,
1297 .timestampValidBits = 64,
1298 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1299 };
1300 idx++;
1301 }
1302
1303 if (pdevice->rad_info.num_compute_rings > 0 &&
1304 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1305 if (*pCount > idx) {
1306 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1307 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1308 VK_QUEUE_TRANSFER_BIT |
1309 VK_QUEUE_SPARSE_BINDING_BIT,
1310 .queueCount = pdevice->rad_info.num_compute_rings,
1311 .timestampValidBits = 64,
1312 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1313 };
1314 idx++;
1315 }
1316 }
1317 *pCount = idx;
1318 }
1319
1320 void radv_GetPhysicalDeviceQueueFamilyProperties(
1321 VkPhysicalDevice physicalDevice,
1322 uint32_t* pCount,
1323 VkQueueFamilyProperties* pQueueFamilyProperties)
1324 {
1325 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1326 if (!pQueueFamilyProperties) {
1327 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1328 return;
1329 }
1330 VkQueueFamilyProperties *properties[] = {
1331 pQueueFamilyProperties + 0,
1332 pQueueFamilyProperties + 1,
1333 pQueueFamilyProperties + 2,
1334 };
1335 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1336 assert(*pCount <= 3);
1337 }
1338
1339 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1340 VkPhysicalDevice physicalDevice,
1341 uint32_t* pCount,
1342 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1343 {
1344 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1345 if (!pQueueFamilyProperties) {
1346 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1347 return;
1348 }
1349 VkQueueFamilyProperties *properties[] = {
1350 &pQueueFamilyProperties[0].queueFamilyProperties,
1351 &pQueueFamilyProperties[1].queueFamilyProperties,
1352 &pQueueFamilyProperties[2].queueFamilyProperties,
1353 };
1354 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1355 assert(*pCount <= 3);
1356 }
1357
1358 void radv_GetPhysicalDeviceMemoryProperties(
1359 VkPhysicalDevice physicalDevice,
1360 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1361 {
1362 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1363
1364 *pMemoryProperties = physical_device->memory_properties;
1365 }
1366
1367 static void
1368 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1369 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1370 {
1371 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1372 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1373 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1374 uint64_t vram_size = radv_get_vram_size(device);
1375 uint64_t gtt_size = device->rad_info.gart_size;
1376 uint64_t heap_budget, heap_usage;
1377
1378 /* For all memory heaps, the computation of budget is as follow:
1379 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1380 *
1381 * The Vulkan spec 1.1.97 says that the budget should include any
1382 * currently allocated device memory.
1383 *
1384 * Note that the application heap usages are not really accurate (eg.
1385 * in presence of shared buffers).
1386 */
1387 if (vram_size) {
1388 heap_usage = device->ws->query_value(device->ws,
1389 RADEON_ALLOCATED_VRAM);
1390
1391 heap_budget = vram_size -
1392 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1393 heap_usage;
1394
1395 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1396 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1397 }
1398
1399 if (visible_vram_size) {
1400 heap_usage = device->ws->query_value(device->ws,
1401 RADEON_ALLOCATED_VRAM_VIS);
1402
1403 heap_budget = visible_vram_size -
1404 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1405 heap_usage;
1406
1407 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1408 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1409 }
1410
1411 if (gtt_size) {
1412 heap_usage = device->ws->query_value(device->ws,
1413 RADEON_ALLOCATED_GTT);
1414
1415 heap_budget = gtt_size -
1416 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1417 heap_usage;
1418
1419 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1420 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1421 }
1422
1423 /* The heapBudget and heapUsage values must be zero for array elements
1424 * greater than or equal to
1425 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1426 */
1427 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1428 memoryBudget->heapBudget[i] = 0;
1429 memoryBudget->heapUsage[i] = 0;
1430 }
1431 }
1432
1433 void radv_GetPhysicalDeviceMemoryProperties2(
1434 VkPhysicalDevice physicalDevice,
1435 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1436 {
1437 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1438 &pMemoryProperties->memoryProperties);
1439
1440 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1441 vk_find_struct(pMemoryProperties->pNext,
1442 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1443 if (memory_budget)
1444 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1445 }
1446
1447 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1448 VkDevice _device,
1449 VkExternalMemoryHandleTypeFlagBits handleType,
1450 const void *pHostPointer,
1451 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1452 {
1453 RADV_FROM_HANDLE(radv_device, device, _device);
1454
1455 switch (handleType)
1456 {
1457 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1458 const struct radv_physical_device *physical_device = device->physical_device;
1459 uint32_t memoryTypeBits = 0;
1460 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1461 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1462 memoryTypeBits = (1 << i);
1463 break;
1464 }
1465 }
1466 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1467 return VK_SUCCESS;
1468 }
1469 default:
1470 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1471 }
1472 }
1473
1474 static enum radeon_ctx_priority
1475 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1476 {
1477 /* Default to MEDIUM when a specific global priority isn't requested */
1478 if (!pObj)
1479 return RADEON_CTX_PRIORITY_MEDIUM;
1480
1481 switch(pObj->globalPriority) {
1482 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1483 return RADEON_CTX_PRIORITY_REALTIME;
1484 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1485 return RADEON_CTX_PRIORITY_HIGH;
1486 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1487 return RADEON_CTX_PRIORITY_MEDIUM;
1488 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1489 return RADEON_CTX_PRIORITY_LOW;
1490 default:
1491 unreachable("Illegal global priority value");
1492 return RADEON_CTX_PRIORITY_INVALID;
1493 }
1494 }
1495
1496 static int
1497 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1498 uint32_t queue_family_index, int idx,
1499 VkDeviceQueueCreateFlags flags,
1500 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1501 {
1502 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1503 queue->device = device;
1504 queue->queue_family_index = queue_family_index;
1505 queue->queue_idx = idx;
1506 queue->priority = radv_get_queue_global_priority(global_priority);
1507 queue->flags = flags;
1508
1509 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1510 if (!queue->hw_ctx)
1511 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1512
1513 return VK_SUCCESS;
1514 }
1515
1516 static void
1517 radv_queue_finish(struct radv_queue *queue)
1518 {
1519 if (queue->hw_ctx)
1520 queue->device->ws->ctx_destroy(queue->hw_ctx);
1521
1522 if (queue->initial_full_flush_preamble_cs)
1523 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1524 if (queue->initial_preamble_cs)
1525 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1526 if (queue->continue_preamble_cs)
1527 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1528 if (queue->descriptor_bo)
1529 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1530 if (queue->scratch_bo)
1531 queue->device->ws->buffer_destroy(queue->scratch_bo);
1532 if (queue->esgs_ring_bo)
1533 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1534 if (queue->gsvs_ring_bo)
1535 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1536 if (queue->tess_rings_bo)
1537 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1538 if (queue->compute_scratch_bo)
1539 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1540 }
1541
1542 static void
1543 radv_bo_list_init(struct radv_bo_list *bo_list)
1544 {
1545 pthread_mutex_init(&bo_list->mutex, NULL);
1546 bo_list->list.count = bo_list->capacity = 0;
1547 bo_list->list.bos = NULL;
1548 }
1549
1550 static void
1551 radv_bo_list_finish(struct radv_bo_list *bo_list)
1552 {
1553 free(bo_list->list.bos);
1554 pthread_mutex_destroy(&bo_list->mutex);
1555 }
1556
1557 static VkResult radv_bo_list_add(struct radv_device *device,
1558 struct radeon_winsys_bo *bo)
1559 {
1560 struct radv_bo_list *bo_list = &device->bo_list;
1561
1562 if (bo->is_local)
1563 return VK_SUCCESS;
1564
1565 if (unlikely(!device->use_global_bo_list))
1566 return VK_SUCCESS;
1567
1568 pthread_mutex_lock(&bo_list->mutex);
1569 if (bo_list->list.count == bo_list->capacity) {
1570 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1571 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1572
1573 if (!data) {
1574 pthread_mutex_unlock(&bo_list->mutex);
1575 return VK_ERROR_OUT_OF_HOST_MEMORY;
1576 }
1577
1578 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1579 bo_list->capacity = capacity;
1580 }
1581
1582 bo_list->list.bos[bo_list->list.count++] = bo;
1583 pthread_mutex_unlock(&bo_list->mutex);
1584 return VK_SUCCESS;
1585 }
1586
1587 static void radv_bo_list_remove(struct radv_device *device,
1588 struct radeon_winsys_bo *bo)
1589 {
1590 struct radv_bo_list *bo_list = &device->bo_list;
1591
1592 if (bo->is_local)
1593 return;
1594
1595 if (unlikely(!device->use_global_bo_list))
1596 return;
1597
1598 pthread_mutex_lock(&bo_list->mutex);
1599 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1600 if (bo_list->list.bos[i] == bo) {
1601 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1602 --bo_list->list.count;
1603 break;
1604 }
1605 }
1606 pthread_mutex_unlock(&bo_list->mutex);
1607 }
1608
1609 static void
1610 radv_device_init_gs_info(struct radv_device *device)
1611 {
1612 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1613 device->physical_device->rad_info.family);
1614 }
1615
1616 static int radv_get_device_extension_index(const char *name)
1617 {
1618 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1619 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1620 return i;
1621 }
1622 return -1;
1623 }
1624
1625 static int
1626 radv_get_int_debug_option(const char *name, int default_value)
1627 {
1628 const char *str;
1629 int result;
1630
1631 str = getenv(name);
1632 if (!str) {
1633 result = default_value;
1634 } else {
1635 char *endptr;
1636
1637 result = strtol(str, &endptr, 0);
1638 if (str == endptr) {
1639 /* No digits founs. */
1640 result = default_value;
1641 }
1642 }
1643
1644 return result;
1645 }
1646
1647 VkResult radv_CreateDevice(
1648 VkPhysicalDevice physicalDevice,
1649 const VkDeviceCreateInfo* pCreateInfo,
1650 const VkAllocationCallbacks* pAllocator,
1651 VkDevice* pDevice)
1652 {
1653 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1654 VkResult result;
1655 struct radv_device *device;
1656
1657 bool keep_shader_info = false;
1658
1659 /* Check enabled features */
1660 if (pCreateInfo->pEnabledFeatures) {
1661 VkPhysicalDeviceFeatures supported_features;
1662 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1663 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1664 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1665 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1666 for (uint32_t i = 0; i < num_features; i++) {
1667 if (enabled_feature[i] && !supported_feature[i])
1668 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1669 }
1670 }
1671
1672 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1673 sizeof(*device), 8,
1674 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1675 if (!device)
1676 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1677
1678 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1679 device->instance = physical_device->instance;
1680 device->physical_device = physical_device;
1681
1682 device->ws = physical_device->ws;
1683 if (pAllocator)
1684 device->alloc = *pAllocator;
1685 else
1686 device->alloc = physical_device->instance->alloc;
1687
1688 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1689 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1690 int index = radv_get_device_extension_index(ext_name);
1691 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1692 vk_free(&device->alloc, device);
1693 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1694 }
1695
1696 device->enabled_extensions.extensions[index] = true;
1697 }
1698
1699 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1700
1701 /* With update after bind we can't attach bo's to the command buffer
1702 * from the descriptor set anymore, so we have to use a global BO list.
1703 */
1704 device->use_global_bo_list =
1705 device->enabled_extensions.EXT_descriptor_indexing ||
1706 device->enabled_extensions.EXT_buffer_device_address;
1707
1708 mtx_init(&device->shader_slab_mutex, mtx_plain);
1709 list_inithead(&device->shader_slabs);
1710
1711 radv_bo_list_init(&device->bo_list);
1712
1713 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1714 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1715 uint32_t qfi = queue_create->queueFamilyIndex;
1716 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1717 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1718
1719 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1720
1721 device->queues[qfi] = vk_alloc(&device->alloc,
1722 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1723 if (!device->queues[qfi]) {
1724 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1725 goto fail;
1726 }
1727
1728 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1729
1730 device->queue_count[qfi] = queue_create->queueCount;
1731
1732 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1733 result = radv_queue_init(device, &device->queues[qfi][q],
1734 qfi, q, queue_create->flags,
1735 global_priority);
1736 if (result != VK_SUCCESS)
1737 goto fail;
1738 }
1739 }
1740
1741 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1742 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1743
1744 /* Disabled and not implemented for now. */
1745 device->dfsm_allowed = device->pbb_allowed &&
1746 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1747 device->physical_device->rad_info.family == CHIP_RAVEN2);
1748
1749 #ifdef ANDROID
1750 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1751 #endif
1752
1753 /* The maximum number of scratch waves. Scratch space isn't divided
1754 * evenly between CUs. The number is only a function of the number of CUs.
1755 * We can decrease the constant to decrease the scratch buffer size.
1756 *
1757 * sctx->scratch_waves must be >= the maximum possible size of
1758 * 1 threadgroup, so that the hw doesn't hang from being unable
1759 * to start any.
1760 *
1761 * The recommended value is 4 per CU at most. Higher numbers don't
1762 * bring much benefit, but they still occupy chip resources (think
1763 * async compute). I've seen ~2% performance difference between 4 and 32.
1764 */
1765 uint32_t max_threads_per_block = 2048;
1766 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1767 max_threads_per_block / 64);
1768
1769 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1770
1771 if (device->physical_device->rad_info.chip_class >= CIK) {
1772 /* If the KMD allows it (there is a KMD hw register for it),
1773 * allow launching waves out-of-order.
1774 */
1775 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1776 }
1777
1778 radv_device_init_gs_info(device);
1779
1780 device->tess_offchip_block_dw_size =
1781 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1782 device->has_distributed_tess =
1783 device->physical_device->rad_info.chip_class >= VI &&
1784 device->physical_device->rad_info.max_se >= 2;
1785
1786 if (getenv("RADV_TRACE_FILE")) {
1787 const char *filename = getenv("RADV_TRACE_FILE");
1788
1789 keep_shader_info = true;
1790
1791 if (!radv_init_trace(device))
1792 goto fail;
1793
1794 fprintf(stderr, "*****************************************************************************\n");
1795 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1796 fprintf(stderr, "*****************************************************************************\n");
1797
1798 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1799 radv_dump_enabled_options(device, stderr);
1800 }
1801
1802 device->keep_shader_info = keep_shader_info;
1803
1804 result = radv_device_init_meta(device);
1805 if (result != VK_SUCCESS)
1806 goto fail;
1807
1808 radv_device_init_msaa(device);
1809
1810 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1811 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1812 switch (family) {
1813 case RADV_QUEUE_GENERAL:
1814 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1815 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1816 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1817 break;
1818 case RADV_QUEUE_COMPUTE:
1819 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1820 radeon_emit(device->empty_cs[family], 0);
1821 break;
1822 }
1823 device->ws->cs_finalize(device->empty_cs[family]);
1824 }
1825
1826 if (device->physical_device->rad_info.chip_class >= CIK)
1827 cik_create_gfx_config(device);
1828
1829 VkPipelineCacheCreateInfo ci;
1830 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1831 ci.pNext = NULL;
1832 ci.flags = 0;
1833 ci.pInitialData = NULL;
1834 ci.initialDataSize = 0;
1835 VkPipelineCache pc;
1836 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1837 &ci, NULL, &pc);
1838 if (result != VK_SUCCESS)
1839 goto fail_meta;
1840
1841 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1842
1843 device->force_aniso =
1844 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1845 if (device->force_aniso >= 0) {
1846 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1847 1 << util_logbase2(device->force_aniso));
1848 }
1849
1850 *pDevice = radv_device_to_handle(device);
1851 return VK_SUCCESS;
1852
1853 fail_meta:
1854 radv_device_finish_meta(device);
1855 fail:
1856 radv_bo_list_finish(&device->bo_list);
1857
1858 if (device->trace_bo)
1859 device->ws->buffer_destroy(device->trace_bo);
1860
1861 if (device->gfx_init)
1862 device->ws->buffer_destroy(device->gfx_init);
1863
1864 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1865 for (unsigned q = 0; q < device->queue_count[i]; q++)
1866 radv_queue_finish(&device->queues[i][q]);
1867 if (device->queue_count[i])
1868 vk_free(&device->alloc, device->queues[i]);
1869 }
1870
1871 vk_free(&device->alloc, device);
1872 return result;
1873 }
1874
1875 void radv_DestroyDevice(
1876 VkDevice _device,
1877 const VkAllocationCallbacks* pAllocator)
1878 {
1879 RADV_FROM_HANDLE(radv_device, device, _device);
1880
1881 if (!device)
1882 return;
1883
1884 if (device->trace_bo)
1885 device->ws->buffer_destroy(device->trace_bo);
1886
1887 if (device->gfx_init)
1888 device->ws->buffer_destroy(device->gfx_init);
1889
1890 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1891 for (unsigned q = 0; q < device->queue_count[i]; q++)
1892 radv_queue_finish(&device->queues[i][q]);
1893 if (device->queue_count[i])
1894 vk_free(&device->alloc, device->queues[i]);
1895 if (device->empty_cs[i])
1896 device->ws->cs_destroy(device->empty_cs[i]);
1897 }
1898 radv_device_finish_meta(device);
1899
1900 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1901 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1902
1903 radv_destroy_shader_slabs(device);
1904
1905 radv_bo_list_finish(&device->bo_list);
1906 vk_free(&device->alloc, device);
1907 }
1908
1909 VkResult radv_EnumerateInstanceLayerProperties(
1910 uint32_t* pPropertyCount,
1911 VkLayerProperties* pProperties)
1912 {
1913 if (pProperties == NULL) {
1914 *pPropertyCount = 0;
1915 return VK_SUCCESS;
1916 }
1917
1918 /* None supported at this time */
1919 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1920 }
1921
1922 VkResult radv_EnumerateDeviceLayerProperties(
1923 VkPhysicalDevice physicalDevice,
1924 uint32_t* pPropertyCount,
1925 VkLayerProperties* pProperties)
1926 {
1927 if (pProperties == NULL) {
1928 *pPropertyCount = 0;
1929 return VK_SUCCESS;
1930 }
1931
1932 /* None supported at this time */
1933 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1934 }
1935
1936 void radv_GetDeviceQueue2(
1937 VkDevice _device,
1938 const VkDeviceQueueInfo2* pQueueInfo,
1939 VkQueue* pQueue)
1940 {
1941 RADV_FROM_HANDLE(radv_device, device, _device);
1942 struct radv_queue *queue;
1943
1944 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1945 if (pQueueInfo->flags != queue->flags) {
1946 /* From the Vulkan 1.1.70 spec:
1947 *
1948 * "The queue returned by vkGetDeviceQueue2 must have the same
1949 * flags value from this structure as that used at device
1950 * creation time in a VkDeviceQueueCreateInfo instance. If no
1951 * matching flags were specified at device creation time then
1952 * pQueue will return VK_NULL_HANDLE."
1953 */
1954 *pQueue = VK_NULL_HANDLE;
1955 return;
1956 }
1957
1958 *pQueue = radv_queue_to_handle(queue);
1959 }
1960
1961 void radv_GetDeviceQueue(
1962 VkDevice _device,
1963 uint32_t queueFamilyIndex,
1964 uint32_t queueIndex,
1965 VkQueue* pQueue)
1966 {
1967 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1968 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1969 .queueFamilyIndex = queueFamilyIndex,
1970 .queueIndex = queueIndex
1971 };
1972
1973 radv_GetDeviceQueue2(_device, &info, pQueue);
1974 }
1975
1976 static void
1977 fill_geom_tess_rings(struct radv_queue *queue,
1978 uint32_t *map,
1979 bool add_sample_positions,
1980 uint32_t esgs_ring_size,
1981 struct radeon_winsys_bo *esgs_ring_bo,
1982 uint32_t gsvs_ring_size,
1983 struct radeon_winsys_bo *gsvs_ring_bo,
1984 uint32_t tess_factor_ring_size,
1985 uint32_t tess_offchip_ring_offset,
1986 uint32_t tess_offchip_ring_size,
1987 struct radeon_winsys_bo *tess_rings_bo)
1988 {
1989 uint32_t *desc = &map[4];
1990
1991 if (esgs_ring_bo) {
1992 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
1993
1994 /* stride 0, num records - size, add tid, swizzle, elsize4,
1995 index stride 64 */
1996 desc[0] = esgs_va;
1997 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1998 S_008F04_STRIDE(0) |
1999 S_008F04_SWIZZLE_ENABLE(true);
2000 desc[2] = esgs_ring_size;
2001 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2002 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2003 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2004 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2005 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2006 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2007 S_008F0C_ELEMENT_SIZE(1) |
2008 S_008F0C_INDEX_STRIDE(3) |
2009 S_008F0C_ADD_TID_ENABLE(true);
2010
2011 /* GS entry for ES->GS ring */
2012 /* stride 0, num records - size, elsize0,
2013 index stride 0 */
2014 desc[4] = esgs_va;
2015 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2016 S_008F04_STRIDE(0) |
2017 S_008F04_SWIZZLE_ENABLE(false);
2018 desc[6] = esgs_ring_size;
2019 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2020 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2021 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2022 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2023 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2024 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2025 S_008F0C_ELEMENT_SIZE(0) |
2026 S_008F0C_INDEX_STRIDE(0) |
2027 S_008F0C_ADD_TID_ENABLE(false);
2028 }
2029
2030 desc += 8;
2031
2032 if (gsvs_ring_bo) {
2033 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2034
2035 /* VS entry for GS->VS ring */
2036 /* stride 0, num records - size, elsize0,
2037 index stride 0 */
2038 desc[0] = gsvs_va;
2039 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2040 S_008F04_STRIDE(0) |
2041 S_008F04_SWIZZLE_ENABLE(false);
2042 desc[2] = gsvs_ring_size;
2043 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2044 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2045 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2046 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2047 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2048 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2049 S_008F0C_ELEMENT_SIZE(0) |
2050 S_008F0C_INDEX_STRIDE(0) |
2051 S_008F0C_ADD_TID_ENABLE(false);
2052
2053 /* stride gsvs_itemsize, num records 64
2054 elsize 4, index stride 16 */
2055 /* shader will patch stride and desc[2] */
2056 desc[4] = gsvs_va;
2057 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2058 S_008F04_STRIDE(0) |
2059 S_008F04_SWIZZLE_ENABLE(true);
2060 desc[6] = 0;
2061 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2062 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2063 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2064 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2065 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2066 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2067 S_008F0C_ELEMENT_SIZE(1) |
2068 S_008F0C_INDEX_STRIDE(1) |
2069 S_008F0C_ADD_TID_ENABLE(true);
2070 }
2071
2072 desc += 8;
2073
2074 if (tess_rings_bo) {
2075 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2076 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2077
2078 desc[0] = tess_va;
2079 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2080 S_008F04_STRIDE(0) |
2081 S_008F04_SWIZZLE_ENABLE(false);
2082 desc[2] = tess_factor_ring_size;
2083 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2084 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2085 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2086 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2087 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2088 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2089 S_008F0C_ELEMENT_SIZE(0) |
2090 S_008F0C_INDEX_STRIDE(0) |
2091 S_008F0C_ADD_TID_ENABLE(false);
2092
2093 desc[4] = tess_offchip_va;
2094 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2095 S_008F04_STRIDE(0) |
2096 S_008F04_SWIZZLE_ENABLE(false);
2097 desc[6] = tess_offchip_ring_size;
2098 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2099 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2100 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2101 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2102 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2103 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2104 S_008F0C_ELEMENT_SIZE(0) |
2105 S_008F0C_INDEX_STRIDE(0) |
2106 S_008F0C_ADD_TID_ENABLE(false);
2107 }
2108
2109 desc += 8;
2110
2111 if (add_sample_positions) {
2112 /* add sample positions after all rings */
2113 memcpy(desc, queue->device->sample_locations_1x, 8);
2114 desc += 2;
2115 memcpy(desc, queue->device->sample_locations_2x, 16);
2116 desc += 4;
2117 memcpy(desc, queue->device->sample_locations_4x, 32);
2118 desc += 8;
2119 memcpy(desc, queue->device->sample_locations_8x, 64);
2120 }
2121 }
2122
2123 static unsigned
2124 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2125 {
2126 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2127 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2128 device->physical_device->rad_info.family != CHIP_STONEY;
2129 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2130 unsigned max_offchip_buffers;
2131 unsigned offchip_granularity;
2132 unsigned hs_offchip_param;
2133
2134 /*
2135 * Per RadeonSI:
2136 * This must be one less than the maximum number due to a hw limitation.
2137 * Various hardware bugs in SI, CIK, and GFX9 need this.
2138 *
2139 * Per AMDVLK:
2140 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2141 * Gfx7 should limit max_offchip_buffers to 508
2142 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2143 *
2144 * Follow AMDVLK here.
2145 */
2146 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2147 device->physical_device->rad_info.chip_class == CIK ||
2148 device->physical_device->rad_info.chip_class == SI)
2149 --max_offchip_buffers_per_se;
2150
2151 max_offchip_buffers = max_offchip_buffers_per_se *
2152 device->physical_device->rad_info.max_se;
2153
2154 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2155 * around by setting 4K granularity.
2156 */
2157 if (device->tess_offchip_block_dw_size == 4096) {
2158 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2159 offchip_granularity = V_03093C_X_4K_DWORDS;
2160 } else {
2161 assert(device->tess_offchip_block_dw_size == 8192);
2162 offchip_granularity = V_03093C_X_8K_DWORDS;
2163 }
2164
2165 switch (device->physical_device->rad_info.chip_class) {
2166 case SI:
2167 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2168 break;
2169 case CIK:
2170 case VI:
2171 case GFX9:
2172 default:
2173 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2174 break;
2175 }
2176
2177 *max_offchip_buffers_p = max_offchip_buffers;
2178 if (device->physical_device->rad_info.chip_class >= CIK) {
2179 if (device->physical_device->rad_info.chip_class >= VI)
2180 --max_offchip_buffers;
2181 hs_offchip_param =
2182 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2183 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2184 } else {
2185 hs_offchip_param =
2186 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2187 }
2188 return hs_offchip_param;
2189 }
2190
2191 static void
2192 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2193 struct radeon_winsys_bo *esgs_ring_bo,
2194 uint32_t esgs_ring_size,
2195 struct radeon_winsys_bo *gsvs_ring_bo,
2196 uint32_t gsvs_ring_size)
2197 {
2198 if (!esgs_ring_bo && !gsvs_ring_bo)
2199 return;
2200
2201 if (esgs_ring_bo)
2202 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2203
2204 if (gsvs_ring_bo)
2205 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2206
2207 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2208 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2209 radeon_emit(cs, esgs_ring_size >> 8);
2210 radeon_emit(cs, gsvs_ring_size >> 8);
2211 } else {
2212 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2213 radeon_emit(cs, esgs_ring_size >> 8);
2214 radeon_emit(cs, gsvs_ring_size >> 8);
2215 }
2216 }
2217
2218 static void
2219 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2220 unsigned hs_offchip_param, unsigned tf_ring_size,
2221 struct radeon_winsys_bo *tess_rings_bo)
2222 {
2223 uint64_t tf_va;
2224
2225 if (!tess_rings_bo)
2226 return;
2227
2228 tf_va = radv_buffer_get_va(tess_rings_bo);
2229
2230 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2231
2232 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2233 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2234 S_030938_SIZE(tf_ring_size / 4));
2235 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2236 tf_va >> 8);
2237 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2238 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2239 S_030944_BASE_HI(tf_va >> 40));
2240 }
2241 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2242 hs_offchip_param);
2243 } else {
2244 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2245 S_008988_SIZE(tf_ring_size / 4));
2246 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2247 tf_va >> 8);
2248 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2249 hs_offchip_param);
2250 }
2251 }
2252
2253 static void
2254 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2255 struct radeon_winsys_bo *compute_scratch_bo)
2256 {
2257 uint64_t scratch_va;
2258
2259 if (!compute_scratch_bo)
2260 return;
2261
2262 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2263
2264 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2265
2266 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2267 radeon_emit(cs, scratch_va);
2268 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2269 S_008F04_SWIZZLE_ENABLE(1));
2270 }
2271
2272 static void
2273 radv_emit_global_shader_pointers(struct radv_queue *queue,
2274 struct radeon_cmdbuf *cs,
2275 struct radeon_winsys_bo *descriptor_bo)
2276 {
2277 uint64_t va;
2278
2279 if (!descriptor_bo)
2280 return;
2281
2282 va = radv_buffer_get_va(descriptor_bo);
2283
2284 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2285
2286 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2287 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2288 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2289 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2290 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2291
2292 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2293 radv_emit_shader_pointer(queue->device, cs, regs[i],
2294 va, true);
2295 }
2296 } else {
2297 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2298 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2299 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2300 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2301 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2302 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2303
2304 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2305 radv_emit_shader_pointer(queue->device, cs, regs[i],
2306 va, true);
2307 }
2308 }
2309 }
2310
2311 static void
2312 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2313 {
2314 struct radv_device *device = queue->device;
2315
2316 if (device->gfx_init) {
2317 uint64_t va = radv_buffer_get_va(device->gfx_init);
2318
2319 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2320 radeon_emit(cs, va);
2321 radeon_emit(cs, va >> 32);
2322 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2323
2324 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2325 } else {
2326 struct radv_physical_device *physical_device = device->physical_device;
2327 si_emit_graphics(physical_device, cs);
2328 }
2329 }
2330
2331 static void
2332 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2333 {
2334 struct radv_physical_device *physical_device = queue->device->physical_device;
2335 si_emit_compute(physical_device, cs);
2336 }
2337
2338 static VkResult
2339 radv_get_preamble_cs(struct radv_queue *queue,
2340 uint32_t scratch_size,
2341 uint32_t compute_scratch_size,
2342 uint32_t esgs_ring_size,
2343 uint32_t gsvs_ring_size,
2344 bool needs_tess_rings,
2345 bool needs_sample_positions,
2346 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2347 struct radeon_cmdbuf **initial_preamble_cs,
2348 struct radeon_cmdbuf **continue_preamble_cs)
2349 {
2350 struct radeon_winsys_bo *scratch_bo = NULL;
2351 struct radeon_winsys_bo *descriptor_bo = NULL;
2352 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2353 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2354 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2355 struct radeon_winsys_bo *tess_rings_bo = NULL;
2356 struct radeon_cmdbuf *dest_cs[3] = {0};
2357 bool add_tess_rings = false, add_sample_positions = false;
2358 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2359 unsigned max_offchip_buffers;
2360 unsigned hs_offchip_param = 0;
2361 unsigned tess_offchip_ring_offset;
2362 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2363 if (!queue->has_tess_rings) {
2364 if (needs_tess_rings)
2365 add_tess_rings = true;
2366 }
2367 if (!queue->has_sample_positions) {
2368 if (needs_sample_positions)
2369 add_sample_positions = true;
2370 }
2371 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2372 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2373 &max_offchip_buffers);
2374 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2375 tess_offchip_ring_size = max_offchip_buffers *
2376 queue->device->tess_offchip_block_dw_size * 4;
2377
2378 if (scratch_size <= queue->scratch_size &&
2379 compute_scratch_size <= queue->compute_scratch_size &&
2380 esgs_ring_size <= queue->esgs_ring_size &&
2381 gsvs_ring_size <= queue->gsvs_ring_size &&
2382 !add_tess_rings && !add_sample_positions &&
2383 queue->initial_preamble_cs) {
2384 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2385 *initial_preamble_cs = queue->initial_preamble_cs;
2386 *continue_preamble_cs = queue->continue_preamble_cs;
2387 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2388 *continue_preamble_cs = NULL;
2389 return VK_SUCCESS;
2390 }
2391
2392 if (scratch_size > queue->scratch_size) {
2393 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2394 scratch_size,
2395 4096,
2396 RADEON_DOMAIN_VRAM,
2397 ring_bo_flags,
2398 RADV_BO_PRIORITY_SCRATCH);
2399 if (!scratch_bo)
2400 goto fail;
2401 } else
2402 scratch_bo = queue->scratch_bo;
2403
2404 if (compute_scratch_size > queue->compute_scratch_size) {
2405 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2406 compute_scratch_size,
2407 4096,
2408 RADEON_DOMAIN_VRAM,
2409 ring_bo_flags,
2410 RADV_BO_PRIORITY_SCRATCH);
2411 if (!compute_scratch_bo)
2412 goto fail;
2413
2414 } else
2415 compute_scratch_bo = queue->compute_scratch_bo;
2416
2417 if (esgs_ring_size > queue->esgs_ring_size) {
2418 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2419 esgs_ring_size,
2420 4096,
2421 RADEON_DOMAIN_VRAM,
2422 ring_bo_flags,
2423 RADV_BO_PRIORITY_SCRATCH);
2424 if (!esgs_ring_bo)
2425 goto fail;
2426 } else {
2427 esgs_ring_bo = queue->esgs_ring_bo;
2428 esgs_ring_size = queue->esgs_ring_size;
2429 }
2430
2431 if (gsvs_ring_size > queue->gsvs_ring_size) {
2432 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2433 gsvs_ring_size,
2434 4096,
2435 RADEON_DOMAIN_VRAM,
2436 ring_bo_flags,
2437 RADV_BO_PRIORITY_SCRATCH);
2438 if (!gsvs_ring_bo)
2439 goto fail;
2440 } else {
2441 gsvs_ring_bo = queue->gsvs_ring_bo;
2442 gsvs_ring_size = queue->gsvs_ring_size;
2443 }
2444
2445 if (add_tess_rings) {
2446 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2447 tess_offchip_ring_offset + tess_offchip_ring_size,
2448 256,
2449 RADEON_DOMAIN_VRAM,
2450 ring_bo_flags,
2451 RADV_BO_PRIORITY_SCRATCH);
2452 if (!tess_rings_bo)
2453 goto fail;
2454 } else {
2455 tess_rings_bo = queue->tess_rings_bo;
2456 }
2457
2458 if (scratch_bo != queue->scratch_bo ||
2459 esgs_ring_bo != queue->esgs_ring_bo ||
2460 gsvs_ring_bo != queue->gsvs_ring_bo ||
2461 tess_rings_bo != queue->tess_rings_bo ||
2462 add_sample_positions) {
2463 uint32_t size = 0;
2464 if (gsvs_ring_bo || esgs_ring_bo ||
2465 tess_rings_bo || add_sample_positions) {
2466 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2467 if (add_sample_positions)
2468 size += 128; /* 64+32+16+8 = 120 bytes */
2469 }
2470 else if (scratch_bo)
2471 size = 8; /* 2 dword */
2472
2473 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2474 size,
2475 4096,
2476 RADEON_DOMAIN_VRAM,
2477 RADEON_FLAG_CPU_ACCESS |
2478 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2479 RADEON_FLAG_READ_ONLY,
2480 RADV_BO_PRIORITY_DESCRIPTOR);
2481 if (!descriptor_bo)
2482 goto fail;
2483 } else
2484 descriptor_bo = queue->descriptor_bo;
2485
2486 if (descriptor_bo != queue->descriptor_bo) {
2487 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2488
2489 if (scratch_bo) {
2490 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2491 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2492 S_008F04_SWIZZLE_ENABLE(1);
2493 map[0] = scratch_va;
2494 map[1] = rsrc1;
2495 }
2496
2497 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2498 fill_geom_tess_rings(queue, map, add_sample_positions,
2499 esgs_ring_size, esgs_ring_bo,
2500 gsvs_ring_size, gsvs_ring_bo,
2501 tess_factor_ring_size,
2502 tess_offchip_ring_offset,
2503 tess_offchip_ring_size,
2504 tess_rings_bo);
2505
2506 queue->device->ws->buffer_unmap(descriptor_bo);
2507 }
2508
2509 for(int i = 0; i < 3; ++i) {
2510 struct radeon_cmdbuf *cs = NULL;
2511 cs = queue->device->ws->cs_create(queue->device->ws,
2512 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2513 if (!cs)
2514 goto fail;
2515
2516 dest_cs[i] = cs;
2517
2518 if (scratch_bo)
2519 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2520
2521 /* Emit initial configuration. */
2522 switch (queue->queue_family_index) {
2523 case RADV_QUEUE_GENERAL:
2524 radv_init_graphics_state(cs, queue);
2525 break;
2526 case RADV_QUEUE_COMPUTE:
2527 radv_init_compute_state(cs, queue);
2528 break;
2529 case RADV_QUEUE_TRANSFER:
2530 break;
2531 }
2532
2533 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2534 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2535 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2536 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2537 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2538 }
2539
2540 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2541 gsvs_ring_bo, gsvs_ring_size);
2542 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2543 tess_factor_ring_size, tess_rings_bo);
2544 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2545 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2546
2547 if (i == 0) {
2548 si_cs_emit_cache_flush(cs,
2549 queue->device->physical_device->rad_info.chip_class,
2550 NULL, 0,
2551 queue->queue_family_index == RING_COMPUTE &&
2552 queue->device->physical_device->rad_info.chip_class >= CIK,
2553 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2554 RADV_CMD_FLAG_INV_ICACHE |
2555 RADV_CMD_FLAG_INV_SMEM_L1 |
2556 RADV_CMD_FLAG_INV_VMEM_L1 |
2557 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2558 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2559 } else if (i == 1) {
2560 si_cs_emit_cache_flush(cs,
2561 queue->device->physical_device->rad_info.chip_class,
2562 NULL, 0,
2563 queue->queue_family_index == RING_COMPUTE &&
2564 queue->device->physical_device->rad_info.chip_class >= CIK,
2565 RADV_CMD_FLAG_INV_ICACHE |
2566 RADV_CMD_FLAG_INV_SMEM_L1 |
2567 RADV_CMD_FLAG_INV_VMEM_L1 |
2568 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2569 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2570 }
2571
2572 if (!queue->device->ws->cs_finalize(cs))
2573 goto fail;
2574 }
2575
2576 if (queue->initial_full_flush_preamble_cs)
2577 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2578
2579 if (queue->initial_preamble_cs)
2580 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2581
2582 if (queue->continue_preamble_cs)
2583 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2584
2585 queue->initial_full_flush_preamble_cs = dest_cs[0];
2586 queue->initial_preamble_cs = dest_cs[1];
2587 queue->continue_preamble_cs = dest_cs[2];
2588
2589 if (scratch_bo != queue->scratch_bo) {
2590 if (queue->scratch_bo)
2591 queue->device->ws->buffer_destroy(queue->scratch_bo);
2592 queue->scratch_bo = scratch_bo;
2593 queue->scratch_size = scratch_size;
2594 }
2595
2596 if (compute_scratch_bo != queue->compute_scratch_bo) {
2597 if (queue->compute_scratch_bo)
2598 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2599 queue->compute_scratch_bo = compute_scratch_bo;
2600 queue->compute_scratch_size = compute_scratch_size;
2601 }
2602
2603 if (esgs_ring_bo != queue->esgs_ring_bo) {
2604 if (queue->esgs_ring_bo)
2605 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2606 queue->esgs_ring_bo = esgs_ring_bo;
2607 queue->esgs_ring_size = esgs_ring_size;
2608 }
2609
2610 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2611 if (queue->gsvs_ring_bo)
2612 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2613 queue->gsvs_ring_bo = gsvs_ring_bo;
2614 queue->gsvs_ring_size = gsvs_ring_size;
2615 }
2616
2617 if (tess_rings_bo != queue->tess_rings_bo) {
2618 queue->tess_rings_bo = tess_rings_bo;
2619 queue->has_tess_rings = true;
2620 }
2621
2622 if (descriptor_bo != queue->descriptor_bo) {
2623 if (queue->descriptor_bo)
2624 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2625
2626 queue->descriptor_bo = descriptor_bo;
2627 }
2628
2629 if (add_sample_positions)
2630 queue->has_sample_positions = true;
2631
2632 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2633 *initial_preamble_cs = queue->initial_preamble_cs;
2634 *continue_preamble_cs = queue->continue_preamble_cs;
2635 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2636 *continue_preamble_cs = NULL;
2637 return VK_SUCCESS;
2638 fail:
2639 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2640 if (dest_cs[i])
2641 queue->device->ws->cs_destroy(dest_cs[i]);
2642 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2643 queue->device->ws->buffer_destroy(descriptor_bo);
2644 if (scratch_bo && scratch_bo != queue->scratch_bo)
2645 queue->device->ws->buffer_destroy(scratch_bo);
2646 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2647 queue->device->ws->buffer_destroy(compute_scratch_bo);
2648 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2649 queue->device->ws->buffer_destroy(esgs_ring_bo);
2650 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2651 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2652 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2653 queue->device->ws->buffer_destroy(tess_rings_bo);
2654 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2655 }
2656
2657 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2658 struct radv_winsys_sem_counts *counts,
2659 int num_sems,
2660 const VkSemaphore *sems,
2661 VkFence _fence,
2662 bool reset_temp)
2663 {
2664 int syncobj_idx = 0, sem_idx = 0;
2665
2666 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2667 return VK_SUCCESS;
2668
2669 for (uint32_t i = 0; i < num_sems; i++) {
2670 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2671
2672 if (sem->temp_syncobj || sem->syncobj)
2673 counts->syncobj_count++;
2674 else
2675 counts->sem_count++;
2676 }
2677
2678 if (_fence != VK_NULL_HANDLE) {
2679 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2680 if (fence->temp_syncobj || fence->syncobj)
2681 counts->syncobj_count++;
2682 }
2683
2684 if (counts->syncobj_count) {
2685 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2686 if (!counts->syncobj)
2687 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2688 }
2689
2690 if (counts->sem_count) {
2691 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2692 if (!counts->sem) {
2693 free(counts->syncobj);
2694 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2695 }
2696 }
2697
2698 for (uint32_t i = 0; i < num_sems; i++) {
2699 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2700
2701 if (sem->temp_syncobj) {
2702 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2703 }
2704 else if (sem->syncobj)
2705 counts->syncobj[syncobj_idx++] = sem->syncobj;
2706 else {
2707 assert(sem->sem);
2708 counts->sem[sem_idx++] = sem->sem;
2709 }
2710 }
2711
2712 if (_fence != VK_NULL_HANDLE) {
2713 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2714 if (fence->temp_syncobj)
2715 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2716 else if (fence->syncobj)
2717 counts->syncobj[syncobj_idx++] = fence->syncobj;
2718 }
2719
2720 return VK_SUCCESS;
2721 }
2722
2723 static void
2724 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2725 {
2726 free(sem_info->wait.syncobj);
2727 free(sem_info->wait.sem);
2728 free(sem_info->signal.syncobj);
2729 free(sem_info->signal.sem);
2730 }
2731
2732
2733 static void radv_free_temp_syncobjs(struct radv_device *device,
2734 int num_sems,
2735 const VkSemaphore *sems)
2736 {
2737 for (uint32_t i = 0; i < num_sems; i++) {
2738 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2739
2740 if (sem->temp_syncobj) {
2741 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2742 sem->temp_syncobj = 0;
2743 }
2744 }
2745 }
2746
2747 static VkResult
2748 radv_alloc_sem_info(struct radv_instance *instance,
2749 struct radv_winsys_sem_info *sem_info,
2750 int num_wait_sems,
2751 const VkSemaphore *wait_sems,
2752 int num_signal_sems,
2753 const VkSemaphore *signal_sems,
2754 VkFence fence)
2755 {
2756 VkResult ret;
2757 memset(sem_info, 0, sizeof(*sem_info));
2758
2759 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2760 if (ret)
2761 return ret;
2762 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2763 if (ret)
2764 radv_free_sem_info(sem_info);
2765
2766 /* caller can override these */
2767 sem_info->cs_emit_wait = true;
2768 sem_info->cs_emit_signal = true;
2769 return ret;
2770 }
2771
2772 /* Signals fence as soon as all the work currently put on queue is done. */
2773 static VkResult radv_signal_fence(struct radv_queue *queue,
2774 struct radv_fence *fence)
2775 {
2776 int ret;
2777 VkResult result;
2778 struct radv_winsys_sem_info sem_info;
2779
2780 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2781 radv_fence_to_handle(fence));
2782 if (result != VK_SUCCESS)
2783 return result;
2784
2785 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2786 &queue->device->empty_cs[queue->queue_family_index],
2787 1, NULL, NULL, &sem_info, NULL,
2788 false, fence->fence);
2789 radv_free_sem_info(&sem_info);
2790
2791 if (ret)
2792 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2793
2794 return VK_SUCCESS;
2795 }
2796
2797 VkResult radv_QueueSubmit(
2798 VkQueue _queue,
2799 uint32_t submitCount,
2800 const VkSubmitInfo* pSubmits,
2801 VkFence _fence)
2802 {
2803 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2804 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2805 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2806 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2807 int ret;
2808 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2809 uint32_t scratch_size = 0;
2810 uint32_t compute_scratch_size = 0;
2811 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2812 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2813 VkResult result;
2814 bool fence_emitted = false;
2815 bool tess_rings_needed = false;
2816 bool sample_positions_needed = false;
2817
2818 /* Do this first so failing to allocate scratch buffers can't result in
2819 * partially executed submissions. */
2820 for (uint32_t i = 0; i < submitCount; i++) {
2821 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2822 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2823 pSubmits[i].pCommandBuffers[j]);
2824
2825 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2826 compute_scratch_size = MAX2(compute_scratch_size,
2827 cmd_buffer->compute_scratch_size_needed);
2828 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2829 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2830 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2831 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2832 }
2833 }
2834
2835 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2836 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2837 sample_positions_needed, &initial_flush_preamble_cs,
2838 &initial_preamble_cs, &continue_preamble_cs);
2839 if (result != VK_SUCCESS)
2840 return result;
2841
2842 for (uint32_t i = 0; i < submitCount; i++) {
2843 struct radeon_cmdbuf **cs_array;
2844 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2845 bool can_patch = true;
2846 uint32_t advance;
2847 struct radv_winsys_sem_info sem_info;
2848
2849 result = radv_alloc_sem_info(queue->device->instance,
2850 &sem_info,
2851 pSubmits[i].waitSemaphoreCount,
2852 pSubmits[i].pWaitSemaphores,
2853 pSubmits[i].signalSemaphoreCount,
2854 pSubmits[i].pSignalSemaphores,
2855 _fence);
2856 if (result != VK_SUCCESS)
2857 return result;
2858
2859 if (!pSubmits[i].commandBufferCount) {
2860 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2861 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2862 &queue->device->empty_cs[queue->queue_family_index],
2863 1, NULL, NULL,
2864 &sem_info, NULL,
2865 false, base_fence);
2866 if (ret) {
2867 radv_loge("failed to submit CS %d\n", i);
2868 abort();
2869 }
2870 fence_emitted = true;
2871 }
2872 radv_free_sem_info(&sem_info);
2873 continue;
2874 }
2875
2876 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2877 (pSubmits[i].commandBufferCount));
2878
2879 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2880 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2881 pSubmits[i].pCommandBuffers[j]);
2882 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2883
2884 cs_array[j] = cmd_buffer->cs;
2885 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2886 can_patch = false;
2887
2888 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2889 }
2890
2891 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2892 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2893 const struct radv_winsys_bo_list *bo_list = NULL;
2894
2895 advance = MIN2(max_cs_submission,
2896 pSubmits[i].commandBufferCount - j);
2897
2898 if (queue->device->trace_bo)
2899 *queue->device->trace_id_ptr = 0;
2900
2901 sem_info.cs_emit_wait = j == 0;
2902 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2903
2904 if (unlikely(queue->device->use_global_bo_list)) {
2905 pthread_mutex_lock(&queue->device->bo_list.mutex);
2906 bo_list = &queue->device->bo_list.list;
2907 }
2908
2909 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2910 advance, initial_preamble, continue_preamble_cs,
2911 &sem_info, bo_list,
2912 can_patch, base_fence);
2913
2914 if (unlikely(queue->device->use_global_bo_list))
2915 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2916
2917 if (ret) {
2918 radv_loge("failed to submit CS %d\n", i);
2919 abort();
2920 }
2921 fence_emitted = true;
2922 if (queue->device->trace_bo) {
2923 radv_check_gpu_hangs(queue, cs_array[j]);
2924 }
2925 }
2926
2927 radv_free_temp_syncobjs(queue->device,
2928 pSubmits[i].waitSemaphoreCount,
2929 pSubmits[i].pWaitSemaphores);
2930 radv_free_sem_info(&sem_info);
2931 free(cs_array);
2932 }
2933
2934 if (fence) {
2935 if (!fence_emitted) {
2936 result = radv_signal_fence(queue, fence);
2937 if (result != VK_SUCCESS)
2938 return result;
2939 }
2940 fence->submitted = true;
2941 }
2942
2943 return VK_SUCCESS;
2944 }
2945
2946 VkResult radv_QueueWaitIdle(
2947 VkQueue _queue)
2948 {
2949 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2950
2951 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2952 radv_queue_family_to_ring(queue->queue_family_index),
2953 queue->queue_idx);
2954 return VK_SUCCESS;
2955 }
2956
2957 VkResult radv_DeviceWaitIdle(
2958 VkDevice _device)
2959 {
2960 RADV_FROM_HANDLE(radv_device, device, _device);
2961
2962 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2963 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2964 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2965 }
2966 }
2967 return VK_SUCCESS;
2968 }
2969
2970 VkResult radv_EnumerateInstanceExtensionProperties(
2971 const char* pLayerName,
2972 uint32_t* pPropertyCount,
2973 VkExtensionProperties* pProperties)
2974 {
2975 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2976
2977 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2978 if (radv_supported_instance_extensions.extensions[i]) {
2979 vk_outarray_append(&out, prop) {
2980 *prop = radv_instance_extensions[i];
2981 }
2982 }
2983 }
2984
2985 return vk_outarray_status(&out);
2986 }
2987
2988 VkResult radv_EnumerateDeviceExtensionProperties(
2989 VkPhysicalDevice physicalDevice,
2990 const char* pLayerName,
2991 uint32_t* pPropertyCount,
2992 VkExtensionProperties* pProperties)
2993 {
2994 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2995 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2996
2997 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2998 if (device->supported_extensions.extensions[i]) {
2999 vk_outarray_append(&out, prop) {
3000 *prop = radv_device_extensions[i];
3001 }
3002 }
3003 }
3004
3005 return vk_outarray_status(&out);
3006 }
3007
3008 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3009 VkInstance _instance,
3010 const char* pName)
3011 {
3012 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3013
3014 return radv_lookup_entrypoint_checked(pName,
3015 instance ? instance->apiVersion : 0,
3016 instance ? &instance->enabled_extensions : NULL,
3017 NULL);
3018 }
3019
3020 /* The loader wants us to expose a second GetInstanceProcAddr function
3021 * to work around certain LD_PRELOAD issues seen in apps.
3022 */
3023 PUBLIC
3024 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3025 VkInstance instance,
3026 const char* pName);
3027
3028 PUBLIC
3029 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3030 VkInstance instance,
3031 const char* pName)
3032 {
3033 return radv_GetInstanceProcAddr(instance, pName);
3034 }
3035
3036 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3037 VkDevice _device,
3038 const char* pName)
3039 {
3040 RADV_FROM_HANDLE(radv_device, device, _device);
3041
3042 return radv_lookup_entrypoint_checked(pName,
3043 device->instance->apiVersion,
3044 &device->instance->enabled_extensions,
3045 &device->enabled_extensions);
3046 }
3047
3048 bool radv_get_memory_fd(struct radv_device *device,
3049 struct radv_device_memory *memory,
3050 int *pFD)
3051 {
3052 struct radeon_bo_metadata metadata;
3053
3054 if (memory->image) {
3055 radv_init_metadata(device, memory->image, &metadata);
3056 device->ws->buffer_set_metadata(memory->bo, &metadata);
3057 }
3058
3059 return device->ws->buffer_get_fd(device->ws, memory->bo,
3060 pFD);
3061 }
3062
3063 static VkResult radv_alloc_memory(struct radv_device *device,
3064 const VkMemoryAllocateInfo* pAllocateInfo,
3065 const VkAllocationCallbacks* pAllocator,
3066 VkDeviceMemory* pMem)
3067 {
3068 struct radv_device_memory *mem;
3069 VkResult result;
3070 enum radeon_bo_domain domain;
3071 uint32_t flags = 0;
3072 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3073
3074 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3075
3076 if (pAllocateInfo->allocationSize == 0) {
3077 /* Apparently, this is allowed */
3078 *pMem = VK_NULL_HANDLE;
3079 return VK_SUCCESS;
3080 }
3081
3082 const VkImportMemoryFdInfoKHR *import_info =
3083 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3084 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3085 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3086 const VkExportMemoryAllocateInfo *export_info =
3087 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3088 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3089 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3090
3091 const struct wsi_memory_allocate_info *wsi_info =
3092 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3093
3094 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3095 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3096 if (mem == NULL)
3097 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3098
3099 if (wsi_info && wsi_info->implicit_sync)
3100 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3101
3102 if (dedicate_info) {
3103 mem->image = radv_image_from_handle(dedicate_info->image);
3104 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3105 } else {
3106 mem->image = NULL;
3107 mem->buffer = NULL;
3108 }
3109
3110 float priority_float = 0.5;
3111 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3112 vk_find_struct_const(pAllocateInfo->pNext,
3113 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3114 if (priority_ext)
3115 priority_float = priority_ext->priority;
3116
3117 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3118 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3119
3120 mem->user_ptr = NULL;
3121
3122 if (import_info) {
3123 assert(import_info->handleType ==
3124 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3125 import_info->handleType ==
3126 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3127 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3128 priority, NULL, NULL);
3129 if (!mem->bo) {
3130 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3131 goto fail;
3132 } else {
3133 close(import_info->fd);
3134 }
3135 } else if (host_ptr_info) {
3136 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3137 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3138 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3139 pAllocateInfo->allocationSize,
3140 priority);
3141 if (!mem->bo) {
3142 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3143 goto fail;
3144 } else {
3145 mem->user_ptr = host_ptr_info->pHostPointer;
3146 }
3147 } else {
3148 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3149 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3150 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3151 domain = RADEON_DOMAIN_GTT;
3152 else
3153 domain = RADEON_DOMAIN_VRAM;
3154
3155 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3156 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3157 else
3158 flags |= RADEON_FLAG_CPU_ACCESS;
3159
3160 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3161 flags |= RADEON_FLAG_GTT_WC;
3162
3163 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3164 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3165
3166 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3167 domain, flags, priority);
3168
3169 if (!mem->bo) {
3170 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3171 goto fail;
3172 }
3173 mem->type_index = mem_type_index;
3174 }
3175
3176 result = radv_bo_list_add(device, mem->bo);
3177 if (result != VK_SUCCESS)
3178 goto fail_bo;
3179
3180 *pMem = radv_device_memory_to_handle(mem);
3181
3182 return VK_SUCCESS;
3183
3184 fail_bo:
3185 device->ws->buffer_destroy(mem->bo);
3186 fail:
3187 vk_free2(&device->alloc, pAllocator, mem);
3188
3189 return result;
3190 }
3191
3192 VkResult radv_AllocateMemory(
3193 VkDevice _device,
3194 const VkMemoryAllocateInfo* pAllocateInfo,
3195 const VkAllocationCallbacks* pAllocator,
3196 VkDeviceMemory* pMem)
3197 {
3198 RADV_FROM_HANDLE(radv_device, device, _device);
3199 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3200 }
3201
3202 void radv_FreeMemory(
3203 VkDevice _device,
3204 VkDeviceMemory _mem,
3205 const VkAllocationCallbacks* pAllocator)
3206 {
3207 RADV_FROM_HANDLE(radv_device, device, _device);
3208 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3209
3210 if (mem == NULL)
3211 return;
3212
3213 radv_bo_list_remove(device, mem->bo);
3214 device->ws->buffer_destroy(mem->bo);
3215 mem->bo = NULL;
3216
3217 vk_free2(&device->alloc, pAllocator, mem);
3218 }
3219
3220 VkResult radv_MapMemory(
3221 VkDevice _device,
3222 VkDeviceMemory _memory,
3223 VkDeviceSize offset,
3224 VkDeviceSize size,
3225 VkMemoryMapFlags flags,
3226 void** ppData)
3227 {
3228 RADV_FROM_HANDLE(radv_device, device, _device);
3229 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3230
3231 if (mem == NULL) {
3232 *ppData = NULL;
3233 return VK_SUCCESS;
3234 }
3235
3236 if (mem->user_ptr)
3237 *ppData = mem->user_ptr;
3238 else
3239 *ppData = device->ws->buffer_map(mem->bo);
3240
3241 if (*ppData) {
3242 *ppData += offset;
3243 return VK_SUCCESS;
3244 }
3245
3246 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3247 }
3248
3249 void radv_UnmapMemory(
3250 VkDevice _device,
3251 VkDeviceMemory _memory)
3252 {
3253 RADV_FROM_HANDLE(radv_device, device, _device);
3254 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3255
3256 if (mem == NULL)
3257 return;
3258
3259 if (mem->user_ptr == NULL)
3260 device->ws->buffer_unmap(mem->bo);
3261 }
3262
3263 VkResult radv_FlushMappedMemoryRanges(
3264 VkDevice _device,
3265 uint32_t memoryRangeCount,
3266 const VkMappedMemoryRange* pMemoryRanges)
3267 {
3268 return VK_SUCCESS;
3269 }
3270
3271 VkResult radv_InvalidateMappedMemoryRanges(
3272 VkDevice _device,
3273 uint32_t memoryRangeCount,
3274 const VkMappedMemoryRange* pMemoryRanges)
3275 {
3276 return VK_SUCCESS;
3277 }
3278
3279 void radv_GetBufferMemoryRequirements(
3280 VkDevice _device,
3281 VkBuffer _buffer,
3282 VkMemoryRequirements* pMemoryRequirements)
3283 {
3284 RADV_FROM_HANDLE(radv_device, device, _device);
3285 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3286
3287 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3288
3289 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3290 pMemoryRequirements->alignment = 4096;
3291 else
3292 pMemoryRequirements->alignment = 16;
3293
3294 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3295 }
3296
3297 void radv_GetBufferMemoryRequirements2(
3298 VkDevice device,
3299 const VkBufferMemoryRequirementsInfo2 *pInfo,
3300 VkMemoryRequirements2 *pMemoryRequirements)
3301 {
3302 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3303 &pMemoryRequirements->memoryRequirements);
3304 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3305 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3306 switch (ext->sType) {
3307 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3308 VkMemoryDedicatedRequirements *req =
3309 (VkMemoryDedicatedRequirements *) ext;
3310 req->requiresDedicatedAllocation = buffer->shareable;
3311 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3312 break;
3313 }
3314 default:
3315 break;
3316 }
3317 }
3318 }
3319
3320 void radv_GetImageMemoryRequirements(
3321 VkDevice _device,
3322 VkImage _image,
3323 VkMemoryRequirements* pMemoryRequirements)
3324 {
3325 RADV_FROM_HANDLE(radv_device, device, _device);
3326 RADV_FROM_HANDLE(radv_image, image, _image);
3327
3328 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3329
3330 pMemoryRequirements->size = image->size;
3331 pMemoryRequirements->alignment = image->alignment;
3332 }
3333
3334 void radv_GetImageMemoryRequirements2(
3335 VkDevice device,
3336 const VkImageMemoryRequirementsInfo2 *pInfo,
3337 VkMemoryRequirements2 *pMemoryRequirements)
3338 {
3339 radv_GetImageMemoryRequirements(device, pInfo->image,
3340 &pMemoryRequirements->memoryRequirements);
3341
3342 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3343
3344 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3345 switch (ext->sType) {
3346 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3347 VkMemoryDedicatedRequirements *req =
3348 (VkMemoryDedicatedRequirements *) ext;
3349 req->requiresDedicatedAllocation = image->shareable;
3350 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3351 break;
3352 }
3353 default:
3354 break;
3355 }
3356 }
3357 }
3358
3359 void radv_GetImageSparseMemoryRequirements(
3360 VkDevice device,
3361 VkImage image,
3362 uint32_t* pSparseMemoryRequirementCount,
3363 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3364 {
3365 stub();
3366 }
3367
3368 void radv_GetImageSparseMemoryRequirements2(
3369 VkDevice device,
3370 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3371 uint32_t* pSparseMemoryRequirementCount,
3372 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3373 {
3374 stub();
3375 }
3376
3377 void radv_GetDeviceMemoryCommitment(
3378 VkDevice device,
3379 VkDeviceMemory memory,
3380 VkDeviceSize* pCommittedMemoryInBytes)
3381 {
3382 *pCommittedMemoryInBytes = 0;
3383 }
3384
3385 VkResult radv_BindBufferMemory2(VkDevice device,
3386 uint32_t bindInfoCount,
3387 const VkBindBufferMemoryInfo *pBindInfos)
3388 {
3389 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3390 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3391 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3392
3393 if (mem) {
3394 buffer->bo = mem->bo;
3395 buffer->offset = pBindInfos[i].memoryOffset;
3396 } else {
3397 buffer->bo = NULL;
3398 }
3399 }
3400 return VK_SUCCESS;
3401 }
3402
3403 VkResult radv_BindBufferMemory(
3404 VkDevice device,
3405 VkBuffer buffer,
3406 VkDeviceMemory memory,
3407 VkDeviceSize memoryOffset)
3408 {
3409 const VkBindBufferMemoryInfo info = {
3410 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3411 .buffer = buffer,
3412 .memory = memory,
3413 .memoryOffset = memoryOffset
3414 };
3415
3416 return radv_BindBufferMemory2(device, 1, &info);
3417 }
3418
3419 VkResult radv_BindImageMemory2(VkDevice device,
3420 uint32_t bindInfoCount,
3421 const VkBindImageMemoryInfo *pBindInfos)
3422 {
3423 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3424 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3425 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3426
3427 if (mem) {
3428 image->bo = mem->bo;
3429 image->offset = pBindInfos[i].memoryOffset;
3430 } else {
3431 image->bo = NULL;
3432 image->offset = 0;
3433 }
3434 }
3435 return VK_SUCCESS;
3436 }
3437
3438
3439 VkResult radv_BindImageMemory(
3440 VkDevice device,
3441 VkImage image,
3442 VkDeviceMemory memory,
3443 VkDeviceSize memoryOffset)
3444 {
3445 const VkBindImageMemoryInfo info = {
3446 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3447 .image = image,
3448 .memory = memory,
3449 .memoryOffset = memoryOffset
3450 };
3451
3452 return radv_BindImageMemory2(device, 1, &info);
3453 }
3454
3455
3456 static void
3457 radv_sparse_buffer_bind_memory(struct radv_device *device,
3458 const VkSparseBufferMemoryBindInfo *bind)
3459 {
3460 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3461
3462 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3463 struct radv_device_memory *mem = NULL;
3464
3465 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3466 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3467
3468 device->ws->buffer_virtual_bind(buffer->bo,
3469 bind->pBinds[i].resourceOffset,
3470 bind->pBinds[i].size,
3471 mem ? mem->bo : NULL,
3472 bind->pBinds[i].memoryOffset);
3473 }
3474 }
3475
3476 static void
3477 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3478 const VkSparseImageOpaqueMemoryBindInfo *bind)
3479 {
3480 RADV_FROM_HANDLE(radv_image, image, bind->image);
3481
3482 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3483 struct radv_device_memory *mem = NULL;
3484
3485 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3486 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3487
3488 device->ws->buffer_virtual_bind(image->bo,
3489 bind->pBinds[i].resourceOffset,
3490 bind->pBinds[i].size,
3491 mem ? mem->bo : NULL,
3492 bind->pBinds[i].memoryOffset);
3493 }
3494 }
3495
3496 VkResult radv_QueueBindSparse(
3497 VkQueue _queue,
3498 uint32_t bindInfoCount,
3499 const VkBindSparseInfo* pBindInfo,
3500 VkFence _fence)
3501 {
3502 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3503 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3504 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3505 bool fence_emitted = false;
3506 VkResult result;
3507 int ret;
3508
3509 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3510 struct radv_winsys_sem_info sem_info;
3511 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3512 radv_sparse_buffer_bind_memory(queue->device,
3513 pBindInfo[i].pBufferBinds + j);
3514 }
3515
3516 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3517 radv_sparse_image_opaque_bind_memory(queue->device,
3518 pBindInfo[i].pImageOpaqueBinds + j);
3519 }
3520
3521 VkResult result;
3522 result = radv_alloc_sem_info(queue->device->instance,
3523 &sem_info,
3524 pBindInfo[i].waitSemaphoreCount,
3525 pBindInfo[i].pWaitSemaphores,
3526 pBindInfo[i].signalSemaphoreCount,
3527 pBindInfo[i].pSignalSemaphores,
3528 _fence);
3529 if (result != VK_SUCCESS)
3530 return result;
3531
3532 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3533 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3534 &queue->device->empty_cs[queue->queue_family_index],
3535 1, NULL, NULL,
3536 &sem_info, NULL,
3537 false, base_fence);
3538 if (ret) {
3539 radv_loge("failed to submit CS %d\n", i);
3540 abort();
3541 }
3542
3543 fence_emitted = true;
3544 if (fence)
3545 fence->submitted = true;
3546 }
3547
3548 radv_free_sem_info(&sem_info);
3549
3550 }
3551
3552 if (fence) {
3553 if (!fence_emitted) {
3554 result = radv_signal_fence(queue, fence);
3555 if (result != VK_SUCCESS)
3556 return result;
3557 }
3558 fence->submitted = true;
3559 }
3560
3561 return VK_SUCCESS;
3562 }
3563
3564 VkResult radv_CreateFence(
3565 VkDevice _device,
3566 const VkFenceCreateInfo* pCreateInfo,
3567 const VkAllocationCallbacks* pAllocator,
3568 VkFence* pFence)
3569 {
3570 RADV_FROM_HANDLE(radv_device, device, _device);
3571 const VkExportFenceCreateInfo *export =
3572 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3573 VkExternalFenceHandleTypeFlags handleTypes =
3574 export ? export->handleTypes : 0;
3575
3576 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3577 sizeof(*fence), 8,
3578 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3579
3580 if (!fence)
3581 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3582
3583 fence->fence_wsi = NULL;
3584 fence->submitted = false;
3585 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3586 fence->temp_syncobj = 0;
3587 if (device->always_use_syncobj || handleTypes) {
3588 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3589 if (ret) {
3590 vk_free2(&device->alloc, pAllocator, fence);
3591 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3592 }
3593 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3594 device->ws->signal_syncobj(device->ws, fence->syncobj);
3595 }
3596 fence->fence = NULL;
3597 } else {
3598 fence->fence = device->ws->create_fence();
3599 if (!fence->fence) {
3600 vk_free2(&device->alloc, pAllocator, fence);
3601 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3602 }
3603 fence->syncobj = 0;
3604 }
3605
3606 *pFence = radv_fence_to_handle(fence);
3607
3608 return VK_SUCCESS;
3609 }
3610
3611 void radv_DestroyFence(
3612 VkDevice _device,
3613 VkFence _fence,
3614 const VkAllocationCallbacks* pAllocator)
3615 {
3616 RADV_FROM_HANDLE(radv_device, device, _device);
3617 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3618
3619 if (!fence)
3620 return;
3621
3622 if (fence->temp_syncobj)
3623 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3624 if (fence->syncobj)
3625 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3626 if (fence->fence)
3627 device->ws->destroy_fence(fence->fence);
3628 if (fence->fence_wsi)
3629 fence->fence_wsi->destroy(fence->fence_wsi);
3630 vk_free2(&device->alloc, pAllocator, fence);
3631 }
3632
3633
3634 static uint64_t radv_get_current_time()
3635 {
3636 struct timespec tv;
3637 clock_gettime(CLOCK_MONOTONIC, &tv);
3638 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3639 }
3640
3641 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3642 {
3643 uint64_t current_time = radv_get_current_time();
3644
3645 timeout = MIN2(UINT64_MAX - current_time, timeout);
3646
3647 return current_time + timeout;
3648 }
3649
3650
3651 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3652 {
3653 for (uint32_t i = 0; i < fenceCount; ++i) {
3654 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3655 if (fence->fence == NULL || fence->syncobj ||
3656 fence->temp_syncobj ||
3657 (!fence->signalled && !fence->submitted))
3658 return false;
3659 }
3660 return true;
3661 }
3662
3663 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3664 {
3665 for (uint32_t i = 0; i < fenceCount; ++i) {
3666 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3667 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3668 return false;
3669 }
3670 return true;
3671 }
3672
3673 VkResult radv_WaitForFences(
3674 VkDevice _device,
3675 uint32_t fenceCount,
3676 const VkFence* pFences,
3677 VkBool32 waitAll,
3678 uint64_t timeout)
3679 {
3680 RADV_FROM_HANDLE(radv_device, device, _device);
3681 timeout = radv_get_absolute_timeout(timeout);
3682
3683 if (device->always_use_syncobj &&
3684 radv_all_fences_syncobj(fenceCount, pFences))
3685 {
3686 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3687 if (!handles)
3688 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3689
3690 for (uint32_t i = 0; i < fenceCount; ++i) {
3691 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3692 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3693 }
3694
3695 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3696
3697 free(handles);
3698 return success ? VK_SUCCESS : VK_TIMEOUT;
3699 }
3700
3701 if (!waitAll && fenceCount > 1) {
3702 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3703 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3704 uint32_t wait_count = 0;
3705 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3706 if (!fences)
3707 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3708
3709 for (uint32_t i = 0; i < fenceCount; ++i) {
3710 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3711
3712 if (fence->signalled) {
3713 free(fences);
3714 return VK_SUCCESS;
3715 }
3716
3717 fences[wait_count++] = fence->fence;
3718 }
3719
3720 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3721 waitAll, timeout - radv_get_current_time());
3722
3723 free(fences);
3724 return success ? VK_SUCCESS : VK_TIMEOUT;
3725 }
3726
3727 while(radv_get_current_time() <= timeout) {
3728 for (uint32_t i = 0; i < fenceCount; ++i) {
3729 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3730 return VK_SUCCESS;
3731 }
3732 }
3733 return VK_TIMEOUT;
3734 }
3735
3736 for (uint32_t i = 0; i < fenceCount; ++i) {
3737 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3738 bool expired = false;
3739
3740 if (fence->temp_syncobj) {
3741 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3742 return VK_TIMEOUT;
3743 continue;
3744 }
3745
3746 if (fence->syncobj) {
3747 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3748 return VK_TIMEOUT;
3749 continue;
3750 }
3751
3752 if (fence->signalled)
3753 continue;
3754
3755 if (fence->fence) {
3756 if (!fence->submitted) {
3757 while(radv_get_current_time() <= timeout &&
3758 !fence->submitted)
3759 /* Do nothing */;
3760
3761 if (!fence->submitted)
3762 return VK_TIMEOUT;
3763
3764 /* Recheck as it may have been set by
3765 * submitting operations. */
3766
3767 if (fence->signalled)
3768 continue;
3769 }
3770
3771 expired = device->ws->fence_wait(device->ws,
3772 fence->fence,
3773 true, timeout);
3774 if (!expired)
3775 return VK_TIMEOUT;
3776 }
3777
3778 if (fence->fence_wsi) {
3779 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3780 if (result != VK_SUCCESS)
3781 return result;
3782 }
3783
3784 fence->signalled = true;
3785 }
3786
3787 return VK_SUCCESS;
3788 }
3789
3790 VkResult radv_ResetFences(VkDevice _device,
3791 uint32_t fenceCount,
3792 const VkFence *pFences)
3793 {
3794 RADV_FROM_HANDLE(radv_device, device, _device);
3795
3796 for (unsigned i = 0; i < fenceCount; ++i) {
3797 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3798 fence->submitted = fence->signalled = false;
3799
3800 /* Per spec, we first restore the permanent payload, and then reset, so
3801 * having a temp syncobj should not skip resetting the permanent syncobj. */
3802 if (fence->temp_syncobj) {
3803 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3804 fence->temp_syncobj = 0;
3805 }
3806
3807 if (fence->syncobj) {
3808 device->ws->reset_syncobj(device->ws, fence->syncobj);
3809 }
3810 }
3811
3812 return VK_SUCCESS;
3813 }
3814
3815 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3816 {
3817 RADV_FROM_HANDLE(radv_device, device, _device);
3818 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3819
3820 if (fence->temp_syncobj) {
3821 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3822 return success ? VK_SUCCESS : VK_NOT_READY;
3823 }
3824
3825 if (fence->syncobj) {
3826 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3827 return success ? VK_SUCCESS : VK_NOT_READY;
3828 }
3829
3830 if (fence->signalled)
3831 return VK_SUCCESS;
3832 if (!fence->submitted)
3833 return VK_NOT_READY;
3834 if (fence->fence) {
3835 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3836 return VK_NOT_READY;
3837 }
3838 if (fence->fence_wsi) {
3839 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3840
3841 if (result != VK_SUCCESS) {
3842 if (result == VK_TIMEOUT)
3843 return VK_NOT_READY;
3844 return result;
3845 }
3846 }
3847 return VK_SUCCESS;
3848 }
3849
3850
3851 // Queue semaphore functions
3852
3853 VkResult radv_CreateSemaphore(
3854 VkDevice _device,
3855 const VkSemaphoreCreateInfo* pCreateInfo,
3856 const VkAllocationCallbacks* pAllocator,
3857 VkSemaphore* pSemaphore)
3858 {
3859 RADV_FROM_HANDLE(radv_device, device, _device);
3860 const VkExportSemaphoreCreateInfo *export =
3861 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3862 VkExternalSemaphoreHandleTypeFlags handleTypes =
3863 export ? export->handleTypes : 0;
3864
3865 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3866 sizeof(*sem), 8,
3867 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3868 if (!sem)
3869 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3870
3871 sem->temp_syncobj = 0;
3872 /* create a syncobject if we are going to export this semaphore */
3873 if (device->always_use_syncobj || handleTypes) {
3874 assert (device->physical_device->rad_info.has_syncobj);
3875 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3876 if (ret) {
3877 vk_free2(&device->alloc, pAllocator, sem);
3878 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3879 }
3880 sem->sem = NULL;
3881 } else {
3882 sem->sem = device->ws->create_sem(device->ws);
3883 if (!sem->sem) {
3884 vk_free2(&device->alloc, pAllocator, sem);
3885 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3886 }
3887 sem->syncobj = 0;
3888 }
3889
3890 *pSemaphore = radv_semaphore_to_handle(sem);
3891 return VK_SUCCESS;
3892 }
3893
3894 void radv_DestroySemaphore(
3895 VkDevice _device,
3896 VkSemaphore _semaphore,
3897 const VkAllocationCallbacks* pAllocator)
3898 {
3899 RADV_FROM_HANDLE(radv_device, device, _device);
3900 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3901 if (!_semaphore)
3902 return;
3903
3904 if (sem->syncobj)
3905 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3906 else
3907 device->ws->destroy_sem(sem->sem);
3908 vk_free2(&device->alloc, pAllocator, sem);
3909 }
3910
3911 VkResult radv_CreateEvent(
3912 VkDevice _device,
3913 const VkEventCreateInfo* pCreateInfo,
3914 const VkAllocationCallbacks* pAllocator,
3915 VkEvent* pEvent)
3916 {
3917 RADV_FROM_HANDLE(radv_device, device, _device);
3918 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3919 sizeof(*event), 8,
3920 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3921
3922 if (!event)
3923 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3924
3925 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3926 RADEON_DOMAIN_GTT,
3927 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3928 RADV_BO_PRIORITY_FENCE);
3929 if (!event->bo) {
3930 vk_free2(&device->alloc, pAllocator, event);
3931 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3932 }
3933
3934 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3935
3936 *pEvent = radv_event_to_handle(event);
3937
3938 return VK_SUCCESS;
3939 }
3940
3941 void radv_DestroyEvent(
3942 VkDevice _device,
3943 VkEvent _event,
3944 const VkAllocationCallbacks* pAllocator)
3945 {
3946 RADV_FROM_HANDLE(radv_device, device, _device);
3947 RADV_FROM_HANDLE(radv_event, event, _event);
3948
3949 if (!event)
3950 return;
3951 device->ws->buffer_destroy(event->bo);
3952 vk_free2(&device->alloc, pAllocator, event);
3953 }
3954
3955 VkResult radv_GetEventStatus(
3956 VkDevice _device,
3957 VkEvent _event)
3958 {
3959 RADV_FROM_HANDLE(radv_event, event, _event);
3960
3961 if (*event->map == 1)
3962 return VK_EVENT_SET;
3963 return VK_EVENT_RESET;
3964 }
3965
3966 VkResult radv_SetEvent(
3967 VkDevice _device,
3968 VkEvent _event)
3969 {
3970 RADV_FROM_HANDLE(radv_event, event, _event);
3971 *event->map = 1;
3972
3973 return VK_SUCCESS;
3974 }
3975
3976 VkResult radv_ResetEvent(
3977 VkDevice _device,
3978 VkEvent _event)
3979 {
3980 RADV_FROM_HANDLE(radv_event, event, _event);
3981 *event->map = 0;
3982
3983 return VK_SUCCESS;
3984 }
3985
3986 VkResult radv_CreateBuffer(
3987 VkDevice _device,
3988 const VkBufferCreateInfo* pCreateInfo,
3989 const VkAllocationCallbacks* pAllocator,
3990 VkBuffer* pBuffer)
3991 {
3992 RADV_FROM_HANDLE(radv_device, device, _device);
3993 struct radv_buffer *buffer;
3994
3995 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3996
3997 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3998 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3999 if (buffer == NULL)
4000 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4001
4002 buffer->size = pCreateInfo->size;
4003 buffer->usage = pCreateInfo->usage;
4004 buffer->bo = NULL;
4005 buffer->offset = 0;
4006 buffer->flags = pCreateInfo->flags;
4007
4008 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4009 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4010
4011 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4012 buffer->bo = device->ws->buffer_create(device->ws,
4013 align64(buffer->size, 4096),
4014 4096, 0, RADEON_FLAG_VIRTUAL,
4015 RADV_BO_PRIORITY_VIRTUAL);
4016 if (!buffer->bo) {
4017 vk_free2(&device->alloc, pAllocator, buffer);
4018 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4019 }
4020 }
4021
4022 *pBuffer = radv_buffer_to_handle(buffer);
4023
4024 return VK_SUCCESS;
4025 }
4026
4027 void radv_DestroyBuffer(
4028 VkDevice _device,
4029 VkBuffer _buffer,
4030 const VkAllocationCallbacks* pAllocator)
4031 {
4032 RADV_FROM_HANDLE(radv_device, device, _device);
4033 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4034
4035 if (!buffer)
4036 return;
4037
4038 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4039 device->ws->buffer_destroy(buffer->bo);
4040
4041 vk_free2(&device->alloc, pAllocator, buffer);
4042 }
4043
4044 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4045 VkDevice device,
4046 const VkBufferDeviceAddressInfoEXT* pInfo)
4047 {
4048 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4049 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4050 }
4051
4052
4053 static inline unsigned
4054 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4055 {
4056 if (stencil)
4057 return image->surface.u.legacy.stencil_tiling_index[level];
4058 else
4059 return image->surface.u.legacy.tiling_index[level];
4060 }
4061
4062 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4063 {
4064 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4065 }
4066
4067 static uint32_t
4068 radv_init_dcc_control_reg(struct radv_device *device,
4069 struct radv_image_view *iview)
4070 {
4071 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4072 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4073 unsigned max_compressed_block_size;
4074 unsigned independent_64b_blocks;
4075
4076 if (!radv_image_has_dcc(iview->image))
4077 return 0;
4078
4079 if (iview->image->info.samples > 1) {
4080 if (iview->image->surface.bpe == 1)
4081 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4082 else if (iview->image->surface.bpe == 2)
4083 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4084 }
4085
4086 if (!device->physical_device->rad_info.has_dedicated_vram) {
4087 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4088 * dGPU and 64 for APU because all of our APUs to date use
4089 * DIMMs which have a request granularity size of 64B while all
4090 * other chips have a 32B request size.
4091 */
4092 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4093 }
4094
4095 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4096 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4097 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4098 /* If this DCC image is potentially going to be used in texture
4099 * fetches, we need some special settings.
4100 */
4101 independent_64b_blocks = 1;
4102 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4103 } else {
4104 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4105 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4106 * big as possible for better compression state.
4107 */
4108 independent_64b_blocks = 0;
4109 max_compressed_block_size = max_uncompressed_block_size;
4110 }
4111
4112 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4113 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4114 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4115 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4116 }
4117
4118 static void
4119 radv_initialise_color_surface(struct radv_device *device,
4120 struct radv_color_buffer_info *cb,
4121 struct radv_image_view *iview)
4122 {
4123 const struct vk_format_description *desc;
4124 unsigned ntype, format, swap, endian;
4125 unsigned blend_clamp = 0, blend_bypass = 0;
4126 uint64_t va;
4127 const struct radeon_surf *surf = &iview->image->surface;
4128
4129 desc = vk_format_description(iview->vk_format);
4130
4131 memset(cb, 0, sizeof(*cb));
4132
4133 /* Intensity is implemented as Red, so treat it that way. */
4134 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4135
4136 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4137
4138 cb->cb_color_base = va >> 8;
4139
4140 if (device->physical_device->rad_info.chip_class >= GFX9) {
4141 struct gfx9_surf_meta_flags meta;
4142 if (iview->image->dcc_offset)
4143 meta = iview->image->surface.u.gfx9.dcc;
4144 else
4145 meta = iview->image->surface.u.gfx9.cmask;
4146
4147 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4148 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4149 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4150 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4151
4152 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4153 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4154 } else {
4155 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4156 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4157
4158 cb->cb_color_base += level_info->offset >> 8;
4159 if (level_info->mode == RADEON_SURF_MODE_2D)
4160 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4161
4162 pitch_tile_max = level_info->nblk_x / 8 - 1;
4163 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4164 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4165
4166 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4167 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4168 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4169
4170 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4171
4172 if (radv_image_has_fmask(iview->image)) {
4173 if (device->physical_device->rad_info.chip_class >= CIK)
4174 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4175 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4176 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4177 } else {
4178 /* This must be set for fast clear to work without FMASK. */
4179 if (device->physical_device->rad_info.chip_class >= CIK)
4180 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4181 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4182 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4183 }
4184 }
4185
4186 /* CMASK variables */
4187 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4188 va += iview->image->cmask.offset;
4189 cb->cb_color_cmask = va >> 8;
4190
4191 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4192 va += iview->image->dcc_offset;
4193 cb->cb_dcc_base = va >> 8;
4194 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4195
4196 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4197 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4198 S_028C6C_SLICE_MAX(max_slice);
4199
4200 if (iview->image->info.samples > 1) {
4201 unsigned log_samples = util_logbase2(iview->image->info.samples);
4202
4203 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4204 S_028C74_NUM_FRAGMENTS(log_samples);
4205 }
4206
4207 if (radv_image_has_fmask(iview->image)) {
4208 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4209 cb->cb_color_fmask = va >> 8;
4210 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4211 } else {
4212 cb->cb_color_fmask = cb->cb_color_base;
4213 }
4214
4215 ntype = radv_translate_color_numformat(iview->vk_format,
4216 desc,
4217 vk_format_get_first_non_void_channel(iview->vk_format));
4218 format = radv_translate_colorformat(iview->vk_format);
4219 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4220 radv_finishme("Illegal color\n");
4221 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4222 endian = radv_colorformat_endian_swap(format);
4223
4224 /* blend clamp should be set for all NORM/SRGB types */
4225 if (ntype == V_028C70_NUMBER_UNORM ||
4226 ntype == V_028C70_NUMBER_SNORM ||
4227 ntype == V_028C70_NUMBER_SRGB)
4228 blend_clamp = 1;
4229
4230 /* set blend bypass according to docs if SINT/UINT or
4231 8/24 COLOR variants */
4232 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4233 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4234 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4235 blend_clamp = 0;
4236 blend_bypass = 1;
4237 }
4238 #if 0
4239 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4240 (format == V_028C70_COLOR_8 ||
4241 format == V_028C70_COLOR_8_8 ||
4242 format == V_028C70_COLOR_8_8_8_8))
4243 ->color_is_int8 = true;
4244 #endif
4245 cb->cb_color_info = S_028C70_FORMAT(format) |
4246 S_028C70_COMP_SWAP(swap) |
4247 S_028C70_BLEND_CLAMP(blend_clamp) |
4248 S_028C70_BLEND_BYPASS(blend_bypass) |
4249 S_028C70_SIMPLE_FLOAT(1) |
4250 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4251 ntype != V_028C70_NUMBER_SNORM &&
4252 ntype != V_028C70_NUMBER_SRGB &&
4253 format != V_028C70_COLOR_8_24 &&
4254 format != V_028C70_COLOR_24_8) |
4255 S_028C70_NUMBER_TYPE(ntype) |
4256 S_028C70_ENDIAN(endian);
4257 if (radv_image_has_fmask(iview->image)) {
4258 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4259 if (device->physical_device->rad_info.chip_class == SI) {
4260 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4261 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4262 }
4263 }
4264
4265 if (radv_image_has_cmask(iview->image) &&
4266 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4267 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4268
4269 if (radv_dcc_enabled(iview->image, iview->base_mip))
4270 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4271
4272 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4273
4274 /* This must be set for fast clear to work without FMASK. */
4275 if (!radv_image_has_fmask(iview->image) &&
4276 device->physical_device->rad_info.chip_class == SI) {
4277 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4278 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4279 }
4280
4281 if (device->physical_device->rad_info.chip_class >= GFX9) {
4282 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4283 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4284
4285 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4286 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4287 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4288 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4289 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4290 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4291 }
4292 }
4293
4294 static unsigned
4295 radv_calc_decompress_on_z_planes(struct radv_device *device,
4296 struct radv_image_view *iview)
4297 {
4298 unsigned max_zplanes = 0;
4299
4300 assert(radv_image_is_tc_compat_htile(iview->image));
4301
4302 if (device->physical_device->rad_info.chip_class >= GFX9) {
4303 /* Default value for 32-bit depth surfaces. */
4304 max_zplanes = 4;
4305
4306 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4307 iview->image->info.samples > 1)
4308 max_zplanes = 2;
4309
4310 max_zplanes = max_zplanes + 1;
4311 } else {
4312 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4313 /* Do not enable Z plane compression for 16-bit depth
4314 * surfaces because isn't supported on GFX8. Only
4315 * 32-bit depth surfaces are supported by the hardware.
4316 * This allows to maintain shader compatibility and to
4317 * reduce the number of depth decompressions.
4318 */
4319 max_zplanes = 1;
4320 } else {
4321 if (iview->image->info.samples <= 1)
4322 max_zplanes = 5;
4323 else if (iview->image->info.samples <= 4)
4324 max_zplanes = 3;
4325 else
4326 max_zplanes = 2;
4327 }
4328 }
4329
4330 return max_zplanes;
4331 }
4332
4333 static void
4334 radv_initialise_ds_surface(struct radv_device *device,
4335 struct radv_ds_buffer_info *ds,
4336 struct radv_image_view *iview)
4337 {
4338 unsigned level = iview->base_mip;
4339 unsigned format, stencil_format;
4340 uint64_t va, s_offs, z_offs;
4341 bool stencil_only = false;
4342 memset(ds, 0, sizeof(*ds));
4343 switch (iview->image->vk_format) {
4344 case VK_FORMAT_D24_UNORM_S8_UINT:
4345 case VK_FORMAT_X8_D24_UNORM_PACK32:
4346 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4347 ds->offset_scale = 2.0f;
4348 break;
4349 case VK_FORMAT_D16_UNORM:
4350 case VK_FORMAT_D16_UNORM_S8_UINT:
4351 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4352 ds->offset_scale = 4.0f;
4353 break;
4354 case VK_FORMAT_D32_SFLOAT:
4355 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4356 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4357 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4358 ds->offset_scale = 1.0f;
4359 break;
4360 case VK_FORMAT_S8_UINT:
4361 stencil_only = true;
4362 break;
4363 default:
4364 break;
4365 }
4366
4367 format = radv_translate_dbformat(iview->image->vk_format);
4368 stencil_format = iview->image->surface.has_stencil ?
4369 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4370
4371 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4372 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4373 S_028008_SLICE_MAX(max_slice);
4374
4375 ds->db_htile_data_base = 0;
4376 ds->db_htile_surface = 0;
4377
4378 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4379 s_offs = z_offs = va;
4380
4381 if (device->physical_device->rad_info.chip_class >= GFX9) {
4382 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4383 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4384
4385 ds->db_z_info = S_028038_FORMAT(format) |
4386 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4387 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4388 S_028038_MAXMIP(iview->image->info.levels - 1) |
4389 S_028038_ZRANGE_PRECISION(1);
4390 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4391 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4392
4393 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4394 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4395 ds->db_depth_view |= S_028008_MIPID(level);
4396
4397 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4398 S_02801C_Y_MAX(iview->image->info.height - 1);
4399
4400 if (radv_htile_enabled(iview->image, level)) {
4401 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4402
4403 if (radv_image_is_tc_compat_htile(iview->image)) {
4404 unsigned max_zplanes =
4405 radv_calc_decompress_on_z_planes(device, iview);
4406
4407 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4408 S_028038_ITERATE_FLUSH(1);
4409 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4410 }
4411
4412 if (!iview->image->surface.has_stencil)
4413 /* Use all of the htile_buffer for depth if there's no stencil. */
4414 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4415 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4416 iview->image->htile_offset;
4417 ds->db_htile_data_base = va >> 8;
4418 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4419 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4420 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4421 }
4422 } else {
4423 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4424
4425 if (stencil_only)
4426 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4427
4428 z_offs += iview->image->surface.u.legacy.level[level].offset;
4429 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4430
4431 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4432 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4433 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4434
4435 if (iview->image->info.samples > 1)
4436 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4437
4438 if (device->physical_device->rad_info.chip_class >= CIK) {
4439 struct radeon_info *info = &device->physical_device->rad_info;
4440 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4441 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4442 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4443 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4444 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4445 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4446
4447 if (stencil_only)
4448 tile_mode = stencil_tile_mode;
4449
4450 ds->db_depth_info |=
4451 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4452 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4453 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4454 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4455 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4456 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4457 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4458 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4459 } else {
4460 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4461 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4462 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4463 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4464 if (stencil_only)
4465 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4466 }
4467
4468 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4469 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4470 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4471
4472 if (radv_htile_enabled(iview->image, level)) {
4473 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4474
4475 if (!iview->image->surface.has_stencil &&
4476 !radv_image_is_tc_compat_htile(iview->image))
4477 /* Use all of the htile_buffer for depth if there's no stencil. */
4478 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4479
4480 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4481 iview->image->htile_offset;
4482 ds->db_htile_data_base = va >> 8;
4483 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4484
4485 if (radv_image_is_tc_compat_htile(iview->image)) {
4486 unsigned max_zplanes =
4487 radv_calc_decompress_on_z_planes(device, iview);
4488
4489 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4490 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4491 }
4492 }
4493 }
4494
4495 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4496 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4497 }
4498
4499 VkResult radv_CreateFramebuffer(
4500 VkDevice _device,
4501 const VkFramebufferCreateInfo* pCreateInfo,
4502 const VkAllocationCallbacks* pAllocator,
4503 VkFramebuffer* pFramebuffer)
4504 {
4505 RADV_FROM_HANDLE(radv_device, device, _device);
4506 struct radv_framebuffer *framebuffer;
4507
4508 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4509
4510 size_t size = sizeof(*framebuffer) +
4511 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4512 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4513 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4514 if (framebuffer == NULL)
4515 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4516
4517 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4518 framebuffer->width = pCreateInfo->width;
4519 framebuffer->height = pCreateInfo->height;
4520 framebuffer->layers = pCreateInfo->layers;
4521 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4522 VkImageView _iview = pCreateInfo->pAttachments[i];
4523 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4524 framebuffer->attachments[i].attachment = iview;
4525 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4526 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4527 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4528 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4529 }
4530 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4531 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4532 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4533 }
4534
4535 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4536 return VK_SUCCESS;
4537 }
4538
4539 void radv_DestroyFramebuffer(
4540 VkDevice _device,
4541 VkFramebuffer _fb,
4542 const VkAllocationCallbacks* pAllocator)
4543 {
4544 RADV_FROM_HANDLE(radv_device, device, _device);
4545 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4546
4547 if (!fb)
4548 return;
4549 vk_free2(&device->alloc, pAllocator, fb);
4550 }
4551
4552 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4553 {
4554 switch (address_mode) {
4555 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4556 return V_008F30_SQ_TEX_WRAP;
4557 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4558 return V_008F30_SQ_TEX_MIRROR;
4559 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4560 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4561 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4562 return V_008F30_SQ_TEX_CLAMP_BORDER;
4563 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4564 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4565 default:
4566 unreachable("illegal tex wrap mode");
4567 break;
4568 }
4569 }
4570
4571 static unsigned
4572 radv_tex_compare(VkCompareOp op)
4573 {
4574 switch (op) {
4575 case VK_COMPARE_OP_NEVER:
4576 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4577 case VK_COMPARE_OP_LESS:
4578 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4579 case VK_COMPARE_OP_EQUAL:
4580 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4581 case VK_COMPARE_OP_LESS_OR_EQUAL:
4582 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4583 case VK_COMPARE_OP_GREATER:
4584 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4585 case VK_COMPARE_OP_NOT_EQUAL:
4586 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4587 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4588 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4589 case VK_COMPARE_OP_ALWAYS:
4590 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4591 default:
4592 unreachable("illegal compare mode");
4593 break;
4594 }
4595 }
4596
4597 static unsigned
4598 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4599 {
4600 switch (filter) {
4601 case VK_FILTER_NEAREST:
4602 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4603 V_008F38_SQ_TEX_XY_FILTER_POINT);
4604 case VK_FILTER_LINEAR:
4605 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4606 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4607 case VK_FILTER_CUBIC_IMG:
4608 default:
4609 fprintf(stderr, "illegal texture filter");
4610 return 0;
4611 }
4612 }
4613
4614 static unsigned
4615 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4616 {
4617 switch (mode) {
4618 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4619 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4620 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4621 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4622 default:
4623 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4624 }
4625 }
4626
4627 static unsigned
4628 radv_tex_bordercolor(VkBorderColor bcolor)
4629 {
4630 switch (bcolor) {
4631 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4632 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4633 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4634 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4635 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4636 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4637 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4638 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4639 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4640 default:
4641 break;
4642 }
4643 return 0;
4644 }
4645
4646 static unsigned
4647 radv_tex_aniso_filter(unsigned filter)
4648 {
4649 if (filter < 2)
4650 return 0;
4651 if (filter < 4)
4652 return 1;
4653 if (filter < 8)
4654 return 2;
4655 if (filter < 16)
4656 return 3;
4657 return 4;
4658 }
4659
4660 static unsigned
4661 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4662 {
4663 switch (mode) {
4664 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4665 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4666 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4667 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4668 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4669 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4670 default:
4671 break;
4672 }
4673 return 0;
4674 }
4675
4676 static uint32_t
4677 radv_get_max_anisotropy(struct radv_device *device,
4678 const VkSamplerCreateInfo *pCreateInfo)
4679 {
4680 if (device->force_aniso >= 0)
4681 return device->force_aniso;
4682
4683 if (pCreateInfo->anisotropyEnable &&
4684 pCreateInfo->maxAnisotropy > 1.0f)
4685 return (uint32_t)pCreateInfo->maxAnisotropy;
4686
4687 return 0;
4688 }
4689
4690 static void
4691 radv_init_sampler(struct radv_device *device,
4692 struct radv_sampler *sampler,
4693 const VkSamplerCreateInfo *pCreateInfo)
4694 {
4695 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4696 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4697 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4698 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4699
4700 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4701 vk_find_struct_const(pCreateInfo->pNext,
4702 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4703 if (sampler_reduction)
4704 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4705
4706 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4707 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4708 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4709 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4710 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4711 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4712 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4713 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4714 S_008F30_DISABLE_CUBE_WRAP(0) |
4715 S_008F30_COMPAT_MODE(is_vi) |
4716 S_008F30_FILTER_MODE(filter_mode));
4717 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4718 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4719 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4720 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4721 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4722 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4723 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4724 S_008F38_MIP_POINT_PRECLAMP(0) |
4725 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4726 S_008F38_FILTER_PREC_FIX(1) |
4727 S_008F38_ANISO_OVERRIDE(is_vi));
4728 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4729 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4730 }
4731
4732 VkResult radv_CreateSampler(
4733 VkDevice _device,
4734 const VkSamplerCreateInfo* pCreateInfo,
4735 const VkAllocationCallbacks* pAllocator,
4736 VkSampler* pSampler)
4737 {
4738 RADV_FROM_HANDLE(radv_device, device, _device);
4739 struct radv_sampler *sampler;
4740
4741 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4742
4743 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4744 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4745 if (!sampler)
4746 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4747
4748 radv_init_sampler(device, sampler, pCreateInfo);
4749 *pSampler = radv_sampler_to_handle(sampler);
4750
4751 return VK_SUCCESS;
4752 }
4753
4754 void radv_DestroySampler(
4755 VkDevice _device,
4756 VkSampler _sampler,
4757 const VkAllocationCallbacks* pAllocator)
4758 {
4759 RADV_FROM_HANDLE(radv_device, device, _device);
4760 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4761
4762 if (!sampler)
4763 return;
4764 vk_free2(&device->alloc, pAllocator, sampler);
4765 }
4766
4767 /* vk_icd.h does not declare this function, so we declare it here to
4768 * suppress Wmissing-prototypes.
4769 */
4770 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4771 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4772
4773 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4774 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4775 {
4776 /* For the full details on loader interface versioning, see
4777 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4778 * What follows is a condensed summary, to help you navigate the large and
4779 * confusing official doc.
4780 *
4781 * - Loader interface v0 is incompatible with later versions. We don't
4782 * support it.
4783 *
4784 * - In loader interface v1:
4785 * - The first ICD entrypoint called by the loader is
4786 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4787 * entrypoint.
4788 * - The ICD must statically expose no other Vulkan symbol unless it is
4789 * linked with -Bsymbolic.
4790 * - Each dispatchable Vulkan handle created by the ICD must be
4791 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4792 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4793 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4794 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4795 * such loader-managed surfaces.
4796 *
4797 * - Loader interface v2 differs from v1 in:
4798 * - The first ICD entrypoint called by the loader is
4799 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4800 * statically expose this entrypoint.
4801 *
4802 * - Loader interface v3 differs from v2 in:
4803 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4804 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4805 * because the loader no longer does so.
4806 */
4807 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4808 return VK_SUCCESS;
4809 }
4810
4811 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4812 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4813 int *pFD)
4814 {
4815 RADV_FROM_HANDLE(radv_device, device, _device);
4816 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4817
4818 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4819
4820 /* At the moment, we support only the below handle types. */
4821 assert(pGetFdInfo->handleType ==
4822 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4823 pGetFdInfo->handleType ==
4824 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4825
4826 bool ret = radv_get_memory_fd(device, memory, pFD);
4827 if (ret == false)
4828 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4829 return VK_SUCCESS;
4830 }
4831
4832 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4833 VkExternalMemoryHandleTypeFlagBits handleType,
4834 int fd,
4835 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4836 {
4837 RADV_FROM_HANDLE(radv_device, device, _device);
4838
4839 switch (handleType) {
4840 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4841 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4842 return VK_SUCCESS;
4843
4844 default:
4845 /* The valid usage section for this function says:
4846 *
4847 * "handleType must not be one of the handle types defined as
4848 * opaque."
4849 *
4850 * So opaque handle types fall into the default "unsupported" case.
4851 */
4852 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4853 }
4854 }
4855
4856 static VkResult radv_import_opaque_fd(struct radv_device *device,
4857 int fd,
4858 uint32_t *syncobj)
4859 {
4860 uint32_t syncobj_handle = 0;
4861 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4862 if (ret != 0)
4863 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4864
4865 if (*syncobj)
4866 device->ws->destroy_syncobj(device->ws, *syncobj);
4867
4868 *syncobj = syncobj_handle;
4869 close(fd);
4870
4871 return VK_SUCCESS;
4872 }
4873
4874 static VkResult radv_import_sync_fd(struct radv_device *device,
4875 int fd,
4876 uint32_t *syncobj)
4877 {
4878 /* If we create a syncobj we do it locally so that if we have an error, we don't
4879 * leave a syncobj in an undetermined state in the fence. */
4880 uint32_t syncobj_handle = *syncobj;
4881 if (!syncobj_handle) {
4882 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4883 if (ret) {
4884 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4885 }
4886 }
4887
4888 if (fd == -1) {
4889 device->ws->signal_syncobj(device->ws, syncobj_handle);
4890 } else {
4891 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4892 if (ret != 0)
4893 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4894 }
4895
4896 *syncobj = syncobj_handle;
4897 if (fd != -1)
4898 close(fd);
4899
4900 return VK_SUCCESS;
4901 }
4902
4903 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4904 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4905 {
4906 RADV_FROM_HANDLE(radv_device, device, _device);
4907 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4908 uint32_t *syncobj_dst = NULL;
4909
4910 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4911 syncobj_dst = &sem->temp_syncobj;
4912 } else {
4913 syncobj_dst = &sem->syncobj;
4914 }
4915
4916 switch(pImportSemaphoreFdInfo->handleType) {
4917 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4918 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4919 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4920 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4921 default:
4922 unreachable("Unhandled semaphore handle type");
4923 }
4924 }
4925
4926 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4927 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4928 int *pFd)
4929 {
4930 RADV_FROM_HANDLE(radv_device, device, _device);
4931 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4932 int ret;
4933 uint32_t syncobj_handle;
4934
4935 if (sem->temp_syncobj)
4936 syncobj_handle = sem->temp_syncobj;
4937 else
4938 syncobj_handle = sem->syncobj;
4939
4940 switch(pGetFdInfo->handleType) {
4941 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4942 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4943 break;
4944 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4945 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4946 if (!ret) {
4947 if (sem->temp_syncobj) {
4948 close (sem->temp_syncobj);
4949 sem->temp_syncobj = 0;
4950 } else {
4951 device->ws->reset_syncobj(device->ws, syncobj_handle);
4952 }
4953 }
4954 break;
4955 default:
4956 unreachable("Unhandled semaphore handle type");
4957 }
4958
4959 if (ret)
4960 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4961 return VK_SUCCESS;
4962 }
4963
4964 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4965 VkPhysicalDevice physicalDevice,
4966 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4967 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4968 {
4969 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4970
4971 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4972 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4973 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4974 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4975 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4976 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4977 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4978 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4979 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4980 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4981 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4982 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4983 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4984 } else {
4985 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4986 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4987 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4988 }
4989 }
4990
4991 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4992 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4993 {
4994 RADV_FROM_HANDLE(radv_device, device, _device);
4995 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4996 uint32_t *syncobj_dst = NULL;
4997
4998
4999 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5000 syncobj_dst = &fence->temp_syncobj;
5001 } else {
5002 syncobj_dst = &fence->syncobj;
5003 }
5004
5005 switch(pImportFenceFdInfo->handleType) {
5006 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5007 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5008 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5009 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5010 default:
5011 unreachable("Unhandled fence handle type");
5012 }
5013 }
5014
5015 VkResult radv_GetFenceFdKHR(VkDevice _device,
5016 const VkFenceGetFdInfoKHR *pGetFdInfo,
5017 int *pFd)
5018 {
5019 RADV_FROM_HANDLE(radv_device, device, _device);
5020 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5021 int ret;
5022 uint32_t syncobj_handle;
5023
5024 if (fence->temp_syncobj)
5025 syncobj_handle = fence->temp_syncobj;
5026 else
5027 syncobj_handle = fence->syncobj;
5028
5029 switch(pGetFdInfo->handleType) {
5030 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5031 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5032 break;
5033 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5034 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5035 if (!ret) {
5036 if (fence->temp_syncobj) {
5037 close (fence->temp_syncobj);
5038 fence->temp_syncobj = 0;
5039 } else {
5040 device->ws->reset_syncobj(device->ws, syncobj_handle);
5041 }
5042 }
5043 break;
5044 default:
5045 unreachable("Unhandled fence handle type");
5046 }
5047
5048 if (ret)
5049 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5050 return VK_SUCCESS;
5051 }
5052
5053 void radv_GetPhysicalDeviceExternalFenceProperties(
5054 VkPhysicalDevice physicalDevice,
5055 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5056 VkExternalFenceProperties *pExternalFenceProperties)
5057 {
5058 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5059
5060 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5061 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5062 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5063 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5064 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5065 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5066 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5067 } else {
5068 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5069 pExternalFenceProperties->compatibleHandleTypes = 0;
5070 pExternalFenceProperties->externalFenceFeatures = 0;
5071 }
5072 }
5073
5074 VkResult
5075 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5076 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5077 const VkAllocationCallbacks* pAllocator,
5078 VkDebugReportCallbackEXT* pCallback)
5079 {
5080 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5081 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5082 pCreateInfo, pAllocator, &instance->alloc,
5083 pCallback);
5084 }
5085
5086 void
5087 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5088 VkDebugReportCallbackEXT _callback,
5089 const VkAllocationCallbacks* pAllocator)
5090 {
5091 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5092 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5093 _callback, pAllocator, &instance->alloc);
5094 }
5095
5096 void
5097 radv_DebugReportMessageEXT(VkInstance _instance,
5098 VkDebugReportFlagsEXT flags,
5099 VkDebugReportObjectTypeEXT objectType,
5100 uint64_t object,
5101 size_t location,
5102 int32_t messageCode,
5103 const char* pLayerPrefix,
5104 const char* pMessage)
5105 {
5106 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5107 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5108 object, location, messageCode, pLayerPrefix, pMessage);
5109 }
5110
5111 void
5112 radv_GetDeviceGroupPeerMemoryFeatures(
5113 VkDevice device,
5114 uint32_t heapIndex,
5115 uint32_t localDeviceIndex,
5116 uint32_t remoteDeviceIndex,
5117 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5118 {
5119 assert(localDeviceIndex == remoteDeviceIndex);
5120
5121 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5122 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5123 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5124 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5125 }
5126
5127 static const VkTimeDomainEXT radv_time_domains[] = {
5128 VK_TIME_DOMAIN_DEVICE_EXT,
5129 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5130 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5131 };
5132
5133 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5134 VkPhysicalDevice physicalDevice,
5135 uint32_t *pTimeDomainCount,
5136 VkTimeDomainEXT *pTimeDomains)
5137 {
5138 int d;
5139 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5140
5141 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5142 vk_outarray_append(&out, i) {
5143 *i = radv_time_domains[d];
5144 }
5145 }
5146
5147 return vk_outarray_status(&out);
5148 }
5149
5150 static uint64_t
5151 radv_clock_gettime(clockid_t clock_id)
5152 {
5153 struct timespec current;
5154 int ret;
5155
5156 ret = clock_gettime(clock_id, &current);
5157 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5158 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5159 if (ret < 0)
5160 return 0;
5161
5162 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5163 }
5164
5165 VkResult radv_GetCalibratedTimestampsEXT(
5166 VkDevice _device,
5167 uint32_t timestampCount,
5168 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5169 uint64_t *pTimestamps,
5170 uint64_t *pMaxDeviation)
5171 {
5172 RADV_FROM_HANDLE(radv_device, device, _device);
5173 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5174 int d;
5175 uint64_t begin, end;
5176 uint64_t max_clock_period = 0;
5177
5178 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5179
5180 for (d = 0; d < timestampCount; d++) {
5181 switch (pTimestampInfos[d].timeDomain) {
5182 case VK_TIME_DOMAIN_DEVICE_EXT:
5183 pTimestamps[d] = device->ws->query_value(device->ws,
5184 RADEON_TIMESTAMP);
5185 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5186 max_clock_period = MAX2(max_clock_period, device_period);
5187 break;
5188 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5189 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5190 max_clock_period = MAX2(max_clock_period, 1);
5191 break;
5192
5193 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5194 pTimestamps[d] = begin;
5195 break;
5196 default:
5197 pTimestamps[d] = 0;
5198 break;
5199 }
5200 }
5201
5202 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5203
5204 /*
5205 * The maximum deviation is the sum of the interval over which we
5206 * perform the sampling and the maximum period of any sampled
5207 * clock. That's because the maximum skew between any two sampled
5208 * clock edges is when the sampled clock with the largest period is
5209 * sampled at the end of that period but right at the beginning of the
5210 * sampling interval and some other clock is sampled right at the
5211 * begining of its sampling period and right at the end of the
5212 * sampling interval. Let's assume the GPU has the longest clock
5213 * period and that the application is sampling GPU and monotonic:
5214 *
5215 * s e
5216 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5217 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5218 *
5219 * g
5220 * 0 1 2 3
5221 * GPU -----_____-----_____-----_____-----_____
5222 *
5223 * m
5224 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5225 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5226 *
5227 * Interval <----------------->
5228 * Deviation <-------------------------->
5229 *
5230 * s = read(raw) 2
5231 * g = read(GPU) 1
5232 * m = read(monotonic) 2
5233 * e = read(raw) b
5234 *
5235 * We round the sample interval up by one tick to cover sampling error
5236 * in the interval clock
5237 */
5238
5239 uint64_t sample_interval = end - begin + 1;
5240
5241 *pMaxDeviation = sample_interval + max_clock_period;
5242
5243 return VK_SUCCESS;
5244 }