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radv: Enable binning and dfsm by default on Raven.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 }
484 }
485
486 static int radv_get_instance_extension_index(const char *name)
487 {
488 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
489 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
490 return i;
491 }
492 return -1;
493 }
494
495
496 VkResult radv_CreateInstance(
497 const VkInstanceCreateInfo* pCreateInfo,
498 const VkAllocationCallbacks* pAllocator,
499 VkInstance* pInstance)
500 {
501 struct radv_instance *instance;
502 VkResult result;
503
504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
505
506 uint32_t client_version;
507 if (pCreateInfo->pApplicationInfo &&
508 pCreateInfo->pApplicationInfo->apiVersion != 0) {
509 client_version = pCreateInfo->pApplicationInfo->apiVersion;
510 } else {
511 radv_EnumerateInstanceVersion(&client_version);
512 }
513
514 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
515 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
516 if (!instance)
517 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
518
519 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
520
521 if (pAllocator)
522 instance->alloc = *pAllocator;
523 else
524 instance->alloc = default_alloc;
525
526 instance->apiVersion = client_version;
527 instance->physicalDeviceCount = -1;
528
529 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
530 radv_debug_options);
531
532 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
533 radv_perftest_options);
534
535
536 if (instance->debug_flags & RADV_DEBUG_STARTUP)
537 radv_logi("Created an instance");
538
539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
541 int index = radv_get_instance_extension_index(ext_name);
542
543 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
544 vk_free2(&default_alloc, pAllocator, instance);
545 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
546 }
547
548 instance->enabled_extensions.extensions[index] = true;
549 }
550
551 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
552 if (result != VK_SUCCESS) {
553 vk_free2(&default_alloc, pAllocator, instance);
554 return vk_error(instance, result);
555 }
556
557 _mesa_locale_init();
558
559 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
560
561 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
562
563 *pInstance = radv_instance_to_handle(instance);
564
565 return VK_SUCCESS;
566 }
567
568 void radv_DestroyInstance(
569 VkInstance _instance,
570 const VkAllocationCallbacks* pAllocator)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573
574 if (!instance)
575 return;
576
577 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
578 radv_physical_device_finish(instance->physicalDevices + i);
579 }
580
581 VG(VALGRIND_DESTROY_MEMPOOL(instance));
582
583 _mesa_locale_fini();
584
585 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
586
587 vk_free(&instance->alloc, instance);
588 }
589
590 static VkResult
591 radv_enumerate_devices(struct radv_instance *instance)
592 {
593 /* TODO: Check for more devices ? */
594 drmDevicePtr devices[8];
595 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
596 int max_devices;
597
598 instance->physicalDeviceCount = 0;
599
600 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Found %d drm nodes", max_devices);
604
605 if (max_devices < 1)
606 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
607
608 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
609 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
610 devices[i]->bustype == DRM_BUS_PCI &&
611 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
612
613 result = radv_physical_device_init(instance->physicalDevices +
614 instance->physicalDeviceCount,
615 instance,
616 devices[i]);
617 if (result == VK_SUCCESS)
618 ++instance->physicalDeviceCount;
619 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 break;
621 }
622 }
623 drmFreeDevices(devices, max_devices);
624
625 return result;
626 }
627
628 VkResult radv_EnumeratePhysicalDevices(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceCount,
631 VkPhysicalDevice* pPhysicalDevices)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDevices) {
644 *pPhysicalDeviceCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
648 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
649 }
650
651 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
652 : VK_SUCCESS;
653 }
654
655 VkResult radv_EnumeratePhysicalDeviceGroups(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceGroupCount,
658 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDeviceGroupProperties) {
671 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
675 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
676 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
678 }
679 }
680 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
681 : VK_SUCCESS;
682 }
683
684 void radv_GetPhysicalDeviceFeatures(
685 VkPhysicalDevice physicalDevice,
686 VkPhysicalDeviceFeatures* pFeatures)
687 {
688 memset(pFeatures, 0, sizeof(*pFeatures));
689
690 *pFeatures = (VkPhysicalDeviceFeatures) {
691 .robustBufferAccess = true,
692 .fullDrawIndexUint32 = true,
693 .imageCubeArray = true,
694 .independentBlend = true,
695 .geometryShader = true,
696 .tessellationShader = true,
697 .sampleRateShading = true,
698 .dualSrcBlend = true,
699 .logicOp = true,
700 .multiDrawIndirect = true,
701 .drawIndirectFirstInstance = true,
702 .depthClamp = true,
703 .depthBiasClamp = true,
704 .fillModeNonSolid = true,
705 .depthBounds = true,
706 .wideLines = true,
707 .largePoints = true,
708 .alphaToOne = true,
709 .multiViewport = true,
710 .samplerAnisotropy = true,
711 .textureCompressionETC2 = false,
712 .textureCompressionASTC_LDR = false,
713 .textureCompressionBC = true,
714 .occlusionQueryPrecise = true,
715 .pipelineStatisticsQuery = true,
716 .vertexPipelineStoresAndAtomics = true,
717 .fragmentStoresAndAtomics = true,
718 .shaderTessellationAndGeometryPointSize = true,
719 .shaderImageGatherExtended = true,
720 .shaderStorageImageExtendedFormats = true,
721 .shaderStorageImageMultisample = false,
722 .shaderUniformBufferArrayDynamicIndexing = true,
723 .shaderSampledImageArrayDynamicIndexing = true,
724 .shaderStorageBufferArrayDynamicIndexing = true,
725 .shaderStorageImageArrayDynamicIndexing = true,
726 .shaderStorageImageReadWithoutFormat = true,
727 .shaderStorageImageWriteWithoutFormat = true,
728 .shaderClipDistance = true,
729 .shaderCullDistance = true,
730 .shaderFloat64 = true,
731 .shaderInt64 = true,
732 .shaderInt16 = false,
733 .sparseBinding = true,
734 .variableMultisampleRate = true,
735 .inheritedQueries = true,
736 };
737 }
738
739 void radv_GetPhysicalDeviceFeatures2(
740 VkPhysicalDevice physicalDevice,
741 VkPhysicalDeviceFeatures2KHR *pFeatures)
742 {
743 vk_foreach_struct(ext, pFeatures->pNext) {
744 switch (ext->sType) {
745 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
746 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
747 features->variablePointersStorageBuffer = true;
748 features->variablePointers = false;
749 break;
750 }
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
752 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
753 features->multiview = true;
754 features->multiviewGeometryShader = true;
755 features->multiviewTessellationShader = true;
756 break;
757 }
758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
759 VkPhysicalDeviceShaderDrawParameterFeatures *features =
760 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
761 features->shaderDrawParameters = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
765 VkPhysicalDeviceProtectedMemoryFeatures *features =
766 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
767 features->protectedMemory = false;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
771 VkPhysicalDevice16BitStorageFeatures *features =
772 (VkPhysicalDevice16BitStorageFeatures*)ext;
773 features->storageBuffer16BitAccess = false;
774 features->uniformAndStorageBuffer16BitAccess = false;
775 features->storagePushConstant16 = false;
776 features->storageInputOutput16 = false;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
780 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
781 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
782 features->samplerYcbcrConversion = false;
783 break;
784 }
785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
786 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
787 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
788 features->shaderInputAttachmentArrayDynamicIndexing = true;
789 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
790 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
791 features->shaderUniformBufferArrayNonUniformIndexing = false;
792 features->shaderSampledImageArrayNonUniformIndexing = false;
793 features->shaderStorageBufferArrayNonUniformIndexing = false;
794 features->shaderStorageImageArrayNonUniformIndexing = false;
795 features->shaderInputAttachmentArrayNonUniformIndexing = false;
796 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
797 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
798 features->descriptorBindingUniformBufferUpdateAfterBind = true;
799 features->descriptorBindingSampledImageUpdateAfterBind = true;
800 features->descriptorBindingStorageImageUpdateAfterBind = true;
801 features->descriptorBindingStorageBufferUpdateAfterBind = true;
802 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
803 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
804 features->descriptorBindingUpdateUnusedWhilePending = true;
805 features->descriptorBindingPartiallyBound = true;
806 features->descriptorBindingVariableDescriptorCount = true;
807 features->runtimeDescriptorArray = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
811 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
812 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
813 features->conditionalRendering = true;
814 features->inheritedConditionalRendering = false;
815 break;
816 }
817 default:
818 break;
819 }
820 }
821 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
822 }
823
824 void radv_GetPhysicalDeviceProperties(
825 VkPhysicalDevice physicalDevice,
826 VkPhysicalDeviceProperties* pProperties)
827 {
828 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
829 VkSampleCountFlags sample_counts = 0xf;
830
831 /* make sure that the entire descriptor set is addressable with a signed
832 * 32-bit int. So the sum of all limits scaled by descriptor size has to
833 * be at most 2 GiB. the combined image & samples object count as one of
834 * both. This limit is for the pipeline layout, not for the set layout, but
835 * there is no set limit, so we just set a pipeline limit. I don't think
836 * any app is going to hit this soon. */
837 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
838 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
839 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
840 32 /* sampler, largest when combined with image */ +
841 64 /* sampled image */ +
842 64 /* storage image */);
843
844 VkPhysicalDeviceLimits limits = {
845 .maxImageDimension1D = (1 << 14),
846 .maxImageDimension2D = (1 << 14),
847 .maxImageDimension3D = (1 << 11),
848 .maxImageDimensionCube = (1 << 14),
849 .maxImageArrayLayers = (1 << 11),
850 .maxTexelBufferElements = 128 * 1024 * 1024,
851 .maxUniformBufferRange = UINT32_MAX,
852 .maxStorageBufferRange = UINT32_MAX,
853 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
854 .maxMemoryAllocationCount = UINT32_MAX,
855 .maxSamplerAllocationCount = 64 * 1024,
856 .bufferImageGranularity = 64, /* A cache line */
857 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
858 .maxBoundDescriptorSets = MAX_SETS,
859 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
860 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
861 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
862 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
863 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
864 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
865 .maxPerStageResources = max_descriptor_set_size,
866 .maxDescriptorSetSamplers = max_descriptor_set_size,
867 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
868 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
869 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
870 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
871 .maxDescriptorSetSampledImages = max_descriptor_set_size,
872 .maxDescriptorSetStorageImages = max_descriptor_set_size,
873 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
874 .maxVertexInputAttributes = 32,
875 .maxVertexInputBindings = 32,
876 .maxVertexInputAttributeOffset = 2047,
877 .maxVertexInputBindingStride = 2048,
878 .maxVertexOutputComponents = 128,
879 .maxTessellationGenerationLevel = 64,
880 .maxTessellationPatchSize = 32,
881 .maxTessellationControlPerVertexInputComponents = 128,
882 .maxTessellationControlPerVertexOutputComponents = 128,
883 .maxTessellationControlPerPatchOutputComponents = 120,
884 .maxTessellationControlTotalOutputComponents = 4096,
885 .maxTessellationEvaluationInputComponents = 128,
886 .maxTessellationEvaluationOutputComponents = 128,
887 .maxGeometryShaderInvocations = 127,
888 .maxGeometryInputComponents = 64,
889 .maxGeometryOutputComponents = 128,
890 .maxGeometryOutputVertices = 256,
891 .maxGeometryTotalOutputComponents = 1024,
892 .maxFragmentInputComponents = 128,
893 .maxFragmentOutputAttachments = 8,
894 .maxFragmentDualSrcAttachments = 1,
895 .maxFragmentCombinedOutputResources = 8,
896 .maxComputeSharedMemorySize = 32768,
897 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
898 .maxComputeWorkGroupInvocations = 2048,
899 .maxComputeWorkGroupSize = {
900 2048,
901 2048,
902 2048
903 },
904 .subPixelPrecisionBits = 4 /* FIXME */,
905 .subTexelPrecisionBits = 4 /* FIXME */,
906 .mipmapPrecisionBits = 4 /* FIXME */,
907 .maxDrawIndexedIndexValue = UINT32_MAX,
908 .maxDrawIndirectCount = UINT32_MAX,
909 .maxSamplerLodBias = 16,
910 .maxSamplerAnisotropy = 16,
911 .maxViewports = MAX_VIEWPORTS,
912 .maxViewportDimensions = { (1 << 14), (1 << 14) },
913 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
914 .viewportSubPixelBits = 8,
915 .minMemoryMapAlignment = 4096, /* A page */
916 .minTexelBufferOffsetAlignment = 1,
917 .minUniformBufferOffsetAlignment = 4,
918 .minStorageBufferOffsetAlignment = 4,
919 .minTexelOffset = -32,
920 .maxTexelOffset = 31,
921 .minTexelGatherOffset = -32,
922 .maxTexelGatherOffset = 31,
923 .minInterpolationOffset = -2,
924 .maxInterpolationOffset = 2,
925 .subPixelInterpolationOffsetBits = 8,
926 .maxFramebufferWidth = (1 << 14),
927 .maxFramebufferHeight = (1 << 14),
928 .maxFramebufferLayers = (1 << 10),
929 .framebufferColorSampleCounts = sample_counts,
930 .framebufferDepthSampleCounts = sample_counts,
931 .framebufferStencilSampleCounts = sample_counts,
932 .framebufferNoAttachmentsSampleCounts = sample_counts,
933 .maxColorAttachments = MAX_RTS,
934 .sampledImageColorSampleCounts = sample_counts,
935 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
936 .sampledImageDepthSampleCounts = sample_counts,
937 .sampledImageStencilSampleCounts = sample_counts,
938 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
939 .maxSampleMaskWords = 1,
940 .timestampComputeAndGraphics = true,
941 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
942 .maxClipDistances = 8,
943 .maxCullDistances = 8,
944 .maxCombinedClipAndCullDistances = 8,
945 .discreteQueuePriorities = 1,
946 .pointSizeRange = { 0.125, 255.875 },
947 .lineWidthRange = { 0.0, 7.9921875 },
948 .pointSizeGranularity = (1.0 / 8.0),
949 .lineWidthGranularity = (1.0 / 128.0),
950 .strictLines = false, /* FINISHME */
951 .standardSampleLocations = true,
952 .optimalBufferCopyOffsetAlignment = 128,
953 .optimalBufferCopyRowPitchAlignment = 128,
954 .nonCoherentAtomSize = 64,
955 };
956
957 *pProperties = (VkPhysicalDeviceProperties) {
958 .apiVersion = radv_physical_device_api_version(pdevice),
959 .driverVersion = vk_get_driver_version(),
960 .vendorID = ATI_VENDOR_ID,
961 .deviceID = pdevice->rad_info.pci_id,
962 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
963 .limits = limits,
964 .sparseProperties = {0},
965 };
966
967 strcpy(pProperties->deviceName, pdevice->name);
968 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
969 }
970
971 void radv_GetPhysicalDeviceProperties2(
972 VkPhysicalDevice physicalDevice,
973 VkPhysicalDeviceProperties2KHR *pProperties)
974 {
975 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
976 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
977
978 vk_foreach_struct(ext, pProperties->pNext) {
979 switch (ext->sType) {
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
981 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
982 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
983 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
987 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
988 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
989 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
990 properties->deviceLUIDValid = false;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
994 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
995 properties->maxMultiviewViewCount = MAX_VIEWS;
996 properties->maxMultiviewInstanceIndex = INT_MAX;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1000 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1001 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1002 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1003 break;
1004 }
1005 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1006 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1007 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1008 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1012 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1013 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1014 properties->minImportedHostPointerAlignment = 4096;
1015 break;
1016 }
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1018 VkPhysicalDeviceSubgroupProperties *properties =
1019 (VkPhysicalDeviceSubgroupProperties*)ext;
1020 properties->subgroupSize = 64;
1021 properties->supportedStages = VK_SHADER_STAGE_ALL;
1022 properties->supportedOperations =
1023 VK_SUBGROUP_FEATURE_BASIC_BIT |
1024 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1025 VK_SUBGROUP_FEATURE_QUAD_BIT |
1026 VK_SUBGROUP_FEATURE_VOTE_BIT;
1027 if (pdevice->rad_info.chip_class >= VI) {
1028 properties->supportedOperations |=
1029 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1030 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1031 }
1032 properties->quadOperationsInAllStages = true;
1033 break;
1034 }
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1036 VkPhysicalDeviceMaintenance3Properties *properties =
1037 (VkPhysicalDeviceMaintenance3Properties*)ext;
1038 /* Make sure everything is addressable by a signed 32-bit int, and
1039 * our largest descriptors are 96 bytes. */
1040 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1041 /* Our buffer size fields allow only this much */
1042 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1043 break;
1044 }
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1046 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1047 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1048 /* GFX6-8 only support single channel min/max filter. */
1049 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1050 properties->filterMinmaxSingleComponentFormats = true;
1051 break;
1052 }
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1054 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1055 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1056
1057 /* Shader engines. */
1058 properties->shaderEngineCount =
1059 pdevice->rad_info.max_se;
1060 properties->shaderArraysPerEngineCount =
1061 pdevice->rad_info.max_sh_per_se;
1062 properties->computeUnitsPerShaderArray =
1063 pdevice->rad_info.num_good_compute_units /
1064 (pdevice->rad_info.max_se *
1065 pdevice->rad_info.max_sh_per_se);
1066 properties->simdPerComputeUnit = 4;
1067 properties->wavefrontsPerSimd =
1068 pdevice->rad_info.family == CHIP_TONGA ||
1069 pdevice->rad_info.family == CHIP_ICELAND ||
1070 pdevice->rad_info.family == CHIP_POLARIS10 ||
1071 pdevice->rad_info.family == CHIP_POLARIS11 ||
1072 pdevice->rad_info.family == CHIP_POLARIS12 ||
1073 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1074 properties->wavefrontSize = 64;
1075
1076 /* SGPR. */
1077 properties->sgprsPerSimd =
1078 radv_get_num_physical_sgprs(pdevice);
1079 properties->minSgprAllocation =
1080 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1081 properties->maxSgprAllocation =
1082 pdevice->rad_info.family == CHIP_TONGA ||
1083 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1084 properties->sgprAllocationGranularity =
1085 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1086
1087 /* VGPR. */
1088 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1089 properties->minVgprAllocation = 4;
1090 properties->maxVgprAllocation = 256;
1091 properties->vgprAllocationGranularity = 4;
1092 break;
1093 }
1094 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1095 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1096 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1097 properties->maxVertexAttribDivisor = UINT32_MAX;
1098 break;
1099 }
1100 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1101 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1102 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1103 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1104 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1105 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1106 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1107 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1108 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1109 properties->robustBufferAccessUpdateAfterBind = false;
1110 properties->quadDivergentImplicitLod = false;
1111
1112 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1113 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1114 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1115 32 /* sampler, largest when combined with image */ +
1116 64 /* sampled image */ +
1117 64 /* storage image */);
1118 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1119 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1120 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1121 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1122 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1123 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1124 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1125 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1126 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1127 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1128 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1129 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1130 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1131 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1132 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1133 break;
1134 }
1135 default:
1136 break;
1137 }
1138 }
1139 }
1140
1141 static void radv_get_physical_device_queue_family_properties(
1142 struct radv_physical_device* pdevice,
1143 uint32_t* pCount,
1144 VkQueueFamilyProperties** pQueueFamilyProperties)
1145 {
1146 int num_queue_families = 1;
1147 int idx;
1148 if (pdevice->rad_info.num_compute_rings > 0 &&
1149 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1150 num_queue_families++;
1151
1152 if (pQueueFamilyProperties == NULL) {
1153 *pCount = num_queue_families;
1154 return;
1155 }
1156
1157 if (!*pCount)
1158 return;
1159
1160 idx = 0;
1161 if (*pCount >= 1) {
1162 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1163 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1164 VK_QUEUE_COMPUTE_BIT |
1165 VK_QUEUE_TRANSFER_BIT |
1166 VK_QUEUE_SPARSE_BINDING_BIT,
1167 .queueCount = 1,
1168 .timestampValidBits = 64,
1169 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1170 };
1171 idx++;
1172 }
1173
1174 if (pdevice->rad_info.num_compute_rings > 0 &&
1175 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1176 if (*pCount > idx) {
1177 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1178 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1179 VK_QUEUE_TRANSFER_BIT |
1180 VK_QUEUE_SPARSE_BINDING_BIT,
1181 .queueCount = pdevice->rad_info.num_compute_rings,
1182 .timestampValidBits = 64,
1183 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1184 };
1185 idx++;
1186 }
1187 }
1188 *pCount = idx;
1189 }
1190
1191 void radv_GetPhysicalDeviceQueueFamilyProperties(
1192 VkPhysicalDevice physicalDevice,
1193 uint32_t* pCount,
1194 VkQueueFamilyProperties* pQueueFamilyProperties)
1195 {
1196 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1197 if (!pQueueFamilyProperties) {
1198 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1199 return;
1200 }
1201 VkQueueFamilyProperties *properties[] = {
1202 pQueueFamilyProperties + 0,
1203 pQueueFamilyProperties + 1,
1204 pQueueFamilyProperties + 2,
1205 };
1206 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1207 assert(*pCount <= 3);
1208 }
1209
1210 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1211 VkPhysicalDevice physicalDevice,
1212 uint32_t* pCount,
1213 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1214 {
1215 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1216 if (!pQueueFamilyProperties) {
1217 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1218 return;
1219 }
1220 VkQueueFamilyProperties *properties[] = {
1221 &pQueueFamilyProperties[0].queueFamilyProperties,
1222 &pQueueFamilyProperties[1].queueFamilyProperties,
1223 &pQueueFamilyProperties[2].queueFamilyProperties,
1224 };
1225 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1226 assert(*pCount <= 3);
1227 }
1228
1229 void radv_GetPhysicalDeviceMemoryProperties(
1230 VkPhysicalDevice physicalDevice,
1231 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1232 {
1233 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1234
1235 *pMemoryProperties = physical_device->memory_properties;
1236 }
1237
1238 void radv_GetPhysicalDeviceMemoryProperties2(
1239 VkPhysicalDevice physicalDevice,
1240 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1241 {
1242 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1243 &pMemoryProperties->memoryProperties);
1244 }
1245
1246 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1247 VkDevice _device,
1248 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1249 const void *pHostPointer,
1250 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1251 {
1252 RADV_FROM_HANDLE(radv_device, device, _device);
1253
1254 switch (handleType)
1255 {
1256 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1257 const struct radv_physical_device *physical_device = device->physical_device;
1258 uint32_t memoryTypeBits = 0;
1259 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1260 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1261 memoryTypeBits = (1 << i);
1262 break;
1263 }
1264 }
1265 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1266 return VK_SUCCESS;
1267 }
1268 default:
1269 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1270 }
1271 }
1272
1273 static enum radeon_ctx_priority
1274 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1275 {
1276 /* Default to MEDIUM when a specific global priority isn't requested */
1277 if (!pObj)
1278 return RADEON_CTX_PRIORITY_MEDIUM;
1279
1280 switch(pObj->globalPriority) {
1281 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1282 return RADEON_CTX_PRIORITY_REALTIME;
1283 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1284 return RADEON_CTX_PRIORITY_HIGH;
1285 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1286 return RADEON_CTX_PRIORITY_MEDIUM;
1287 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1288 return RADEON_CTX_PRIORITY_LOW;
1289 default:
1290 unreachable("Illegal global priority value");
1291 return RADEON_CTX_PRIORITY_INVALID;
1292 }
1293 }
1294
1295 static int
1296 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1297 uint32_t queue_family_index, int idx,
1298 VkDeviceQueueCreateFlags flags,
1299 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1300 {
1301 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1302 queue->device = device;
1303 queue->queue_family_index = queue_family_index;
1304 queue->queue_idx = idx;
1305 queue->priority = radv_get_queue_global_priority(global_priority);
1306 queue->flags = flags;
1307
1308 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1309 if (!queue->hw_ctx)
1310 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1311
1312 return VK_SUCCESS;
1313 }
1314
1315 static void
1316 radv_queue_finish(struct radv_queue *queue)
1317 {
1318 if (queue->hw_ctx)
1319 queue->device->ws->ctx_destroy(queue->hw_ctx);
1320
1321 if (queue->initial_full_flush_preamble_cs)
1322 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1323 if (queue->initial_preamble_cs)
1324 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1325 if (queue->continue_preamble_cs)
1326 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1327 if (queue->descriptor_bo)
1328 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1329 if (queue->scratch_bo)
1330 queue->device->ws->buffer_destroy(queue->scratch_bo);
1331 if (queue->esgs_ring_bo)
1332 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1333 if (queue->gsvs_ring_bo)
1334 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1335 if (queue->tess_rings_bo)
1336 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1337 if (queue->compute_scratch_bo)
1338 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1339 }
1340
1341 static void
1342 radv_bo_list_init(struct radv_bo_list *bo_list)
1343 {
1344 pthread_mutex_init(&bo_list->mutex, NULL);
1345 bo_list->list.count = bo_list->capacity = 0;
1346 bo_list->list.bos = NULL;
1347 }
1348
1349 static void
1350 radv_bo_list_finish(struct radv_bo_list *bo_list)
1351 {
1352 free(bo_list->list.bos);
1353 pthread_mutex_destroy(&bo_list->mutex);
1354 }
1355
1356 static VkResult radv_bo_list_add(struct radv_device *device,
1357 struct radeon_winsys_bo *bo)
1358 {
1359 struct radv_bo_list *bo_list = &device->bo_list;
1360
1361 if (unlikely(!device->use_global_bo_list))
1362 return VK_SUCCESS;
1363
1364 pthread_mutex_lock(&bo_list->mutex);
1365 if (bo_list->list.count == bo_list->capacity) {
1366 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1367 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1368
1369 if (!data) {
1370 pthread_mutex_unlock(&bo_list->mutex);
1371 return VK_ERROR_OUT_OF_HOST_MEMORY;
1372 }
1373
1374 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1375 bo_list->capacity = capacity;
1376 }
1377
1378 bo_list->list.bos[bo_list->list.count++] = bo;
1379 pthread_mutex_unlock(&bo_list->mutex);
1380 return VK_SUCCESS;
1381 }
1382
1383 static void radv_bo_list_remove(struct radv_device *device,
1384 struct radeon_winsys_bo *bo)
1385 {
1386 struct radv_bo_list *bo_list = &device->bo_list;
1387
1388 if (unlikely(!device->use_global_bo_list))
1389 return;
1390
1391 pthread_mutex_lock(&bo_list->mutex);
1392 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1393 if (bo_list->list.bos[i] == bo) {
1394 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1395 --bo_list->list.count;
1396 break;
1397 }
1398 }
1399 pthread_mutex_unlock(&bo_list->mutex);
1400 }
1401
1402 static void
1403 radv_device_init_gs_info(struct radv_device *device)
1404 {
1405 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1406 device->physical_device->rad_info.family);
1407 }
1408
1409 static int radv_get_device_extension_index(const char *name)
1410 {
1411 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1412 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1413 return i;
1414 }
1415 return -1;
1416 }
1417
1418 VkResult radv_CreateDevice(
1419 VkPhysicalDevice physicalDevice,
1420 const VkDeviceCreateInfo* pCreateInfo,
1421 const VkAllocationCallbacks* pAllocator,
1422 VkDevice* pDevice)
1423 {
1424 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1425 VkResult result;
1426 struct radv_device *device;
1427
1428 bool keep_shader_info = false;
1429
1430 /* Check enabled features */
1431 if (pCreateInfo->pEnabledFeatures) {
1432 VkPhysicalDeviceFeatures supported_features;
1433 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1434 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1435 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1436 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1437 for (uint32_t i = 0; i < num_features; i++) {
1438 if (enabled_feature[i] && !supported_feature[i])
1439 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1440 }
1441 }
1442
1443 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1444 sizeof(*device), 8,
1445 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1446 if (!device)
1447 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1448
1449 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1450 device->instance = physical_device->instance;
1451 device->physical_device = physical_device;
1452
1453 device->ws = physical_device->ws;
1454 if (pAllocator)
1455 device->alloc = *pAllocator;
1456 else
1457 device->alloc = physical_device->instance->alloc;
1458
1459 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1460 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1461 int index = radv_get_device_extension_index(ext_name);
1462 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1463 vk_free(&device->alloc, device);
1464 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1465 }
1466
1467 device->enabled_extensions.extensions[index] = true;
1468 }
1469
1470 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1471
1472 /* With update after bind we can't attach bo's to the command buffer
1473 * from the descriptor set anymore, so we have to use a global BO list.
1474 */
1475 device->use_global_bo_list =
1476 device->enabled_extensions.EXT_descriptor_indexing;
1477
1478 mtx_init(&device->shader_slab_mutex, mtx_plain);
1479 list_inithead(&device->shader_slabs);
1480
1481 radv_bo_list_init(&device->bo_list);
1482
1483 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1484 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1485 uint32_t qfi = queue_create->queueFamilyIndex;
1486 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1487 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1488
1489 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1490
1491 device->queues[qfi] = vk_alloc(&device->alloc,
1492 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1493 if (!device->queues[qfi]) {
1494 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1495 goto fail;
1496 }
1497
1498 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1499
1500 device->queue_count[qfi] = queue_create->queueCount;
1501
1502 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1503 result = radv_queue_init(device, &device->queues[qfi][q],
1504 qfi, q, queue_create->flags,
1505 global_priority);
1506 if (result != VK_SUCCESS)
1507 goto fail;
1508 }
1509 }
1510
1511 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1512 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1513 device->physical_device->rad_info.family == CHIP_RAVEN);
1514
1515 /* Disabled and not implemented for now. */
1516 device->dfsm_allowed = device->pbb_allowed &&
1517 device->physical_device->rad_info.family == CHIP_RAVEN;
1518
1519 #ifdef ANDROID
1520 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1521 #endif
1522
1523 /* The maximum number of scratch waves. Scratch space isn't divided
1524 * evenly between CUs. The number is only a function of the number of CUs.
1525 * We can decrease the constant to decrease the scratch buffer size.
1526 *
1527 * sctx->scratch_waves must be >= the maximum possible size of
1528 * 1 threadgroup, so that the hw doesn't hang from being unable
1529 * to start any.
1530 *
1531 * The recommended value is 4 per CU at most. Higher numbers don't
1532 * bring much benefit, but they still occupy chip resources (think
1533 * async compute). I've seen ~2% performance difference between 4 and 32.
1534 */
1535 uint32_t max_threads_per_block = 2048;
1536 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1537 max_threads_per_block / 64);
1538
1539 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1540
1541 if (device->physical_device->rad_info.chip_class >= CIK) {
1542 /* If the KMD allows it (there is a KMD hw register for it),
1543 * allow launching waves out-of-order.
1544 */
1545 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1546 }
1547
1548 radv_device_init_gs_info(device);
1549
1550 device->tess_offchip_block_dw_size =
1551 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1552 device->has_distributed_tess =
1553 device->physical_device->rad_info.chip_class >= VI &&
1554 device->physical_device->rad_info.max_se >= 2;
1555
1556 if (getenv("RADV_TRACE_FILE")) {
1557 const char *filename = getenv("RADV_TRACE_FILE");
1558
1559 keep_shader_info = true;
1560
1561 if (!radv_init_trace(device))
1562 goto fail;
1563
1564 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1565 radv_dump_enabled_options(device, stderr);
1566 }
1567
1568 device->keep_shader_info = keep_shader_info;
1569
1570 result = radv_device_init_meta(device);
1571 if (result != VK_SUCCESS)
1572 goto fail;
1573
1574 radv_device_init_msaa(device);
1575
1576 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1577 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1578 switch (family) {
1579 case RADV_QUEUE_GENERAL:
1580 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1581 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1582 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1583 break;
1584 case RADV_QUEUE_COMPUTE:
1585 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1586 radeon_emit(device->empty_cs[family], 0);
1587 break;
1588 }
1589 device->ws->cs_finalize(device->empty_cs[family]);
1590 }
1591
1592 if (device->physical_device->rad_info.chip_class >= CIK)
1593 cik_create_gfx_config(device);
1594
1595 VkPipelineCacheCreateInfo ci;
1596 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1597 ci.pNext = NULL;
1598 ci.flags = 0;
1599 ci.pInitialData = NULL;
1600 ci.initialDataSize = 0;
1601 VkPipelineCache pc;
1602 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1603 &ci, NULL, &pc);
1604 if (result != VK_SUCCESS)
1605 goto fail_meta;
1606
1607 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1608
1609 *pDevice = radv_device_to_handle(device);
1610 return VK_SUCCESS;
1611
1612 fail_meta:
1613 radv_device_finish_meta(device);
1614 fail:
1615 radv_bo_list_finish(&device->bo_list);
1616
1617 if (device->trace_bo)
1618 device->ws->buffer_destroy(device->trace_bo);
1619
1620 if (device->gfx_init)
1621 device->ws->buffer_destroy(device->gfx_init);
1622
1623 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1624 for (unsigned q = 0; q < device->queue_count[i]; q++)
1625 radv_queue_finish(&device->queues[i][q]);
1626 if (device->queue_count[i])
1627 vk_free(&device->alloc, device->queues[i]);
1628 }
1629
1630 vk_free(&device->alloc, device);
1631 return result;
1632 }
1633
1634 void radv_DestroyDevice(
1635 VkDevice _device,
1636 const VkAllocationCallbacks* pAllocator)
1637 {
1638 RADV_FROM_HANDLE(radv_device, device, _device);
1639
1640 if (!device)
1641 return;
1642
1643 if (device->trace_bo)
1644 device->ws->buffer_destroy(device->trace_bo);
1645
1646 if (device->gfx_init)
1647 device->ws->buffer_destroy(device->gfx_init);
1648
1649 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1650 for (unsigned q = 0; q < device->queue_count[i]; q++)
1651 radv_queue_finish(&device->queues[i][q]);
1652 if (device->queue_count[i])
1653 vk_free(&device->alloc, device->queues[i]);
1654 if (device->empty_cs[i])
1655 device->ws->cs_destroy(device->empty_cs[i]);
1656 }
1657 radv_device_finish_meta(device);
1658
1659 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1660 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1661
1662 radv_destroy_shader_slabs(device);
1663
1664 radv_bo_list_finish(&device->bo_list);
1665 vk_free(&device->alloc, device);
1666 }
1667
1668 VkResult radv_EnumerateInstanceLayerProperties(
1669 uint32_t* pPropertyCount,
1670 VkLayerProperties* pProperties)
1671 {
1672 if (pProperties == NULL) {
1673 *pPropertyCount = 0;
1674 return VK_SUCCESS;
1675 }
1676
1677 /* None supported at this time */
1678 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1679 }
1680
1681 VkResult radv_EnumerateDeviceLayerProperties(
1682 VkPhysicalDevice physicalDevice,
1683 uint32_t* pPropertyCount,
1684 VkLayerProperties* pProperties)
1685 {
1686 if (pProperties == NULL) {
1687 *pPropertyCount = 0;
1688 return VK_SUCCESS;
1689 }
1690
1691 /* None supported at this time */
1692 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1693 }
1694
1695 void radv_GetDeviceQueue2(
1696 VkDevice _device,
1697 const VkDeviceQueueInfo2* pQueueInfo,
1698 VkQueue* pQueue)
1699 {
1700 RADV_FROM_HANDLE(radv_device, device, _device);
1701 struct radv_queue *queue;
1702
1703 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1704 if (pQueueInfo->flags != queue->flags) {
1705 /* From the Vulkan 1.1.70 spec:
1706 *
1707 * "The queue returned by vkGetDeviceQueue2 must have the same
1708 * flags value from this structure as that used at device
1709 * creation time in a VkDeviceQueueCreateInfo instance. If no
1710 * matching flags were specified at device creation time then
1711 * pQueue will return VK_NULL_HANDLE."
1712 */
1713 *pQueue = VK_NULL_HANDLE;
1714 return;
1715 }
1716
1717 *pQueue = radv_queue_to_handle(queue);
1718 }
1719
1720 void radv_GetDeviceQueue(
1721 VkDevice _device,
1722 uint32_t queueFamilyIndex,
1723 uint32_t queueIndex,
1724 VkQueue* pQueue)
1725 {
1726 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1727 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1728 .queueFamilyIndex = queueFamilyIndex,
1729 .queueIndex = queueIndex
1730 };
1731
1732 radv_GetDeviceQueue2(_device, &info, pQueue);
1733 }
1734
1735 static void
1736 fill_geom_tess_rings(struct radv_queue *queue,
1737 uint32_t *map,
1738 bool add_sample_positions,
1739 uint32_t esgs_ring_size,
1740 struct radeon_winsys_bo *esgs_ring_bo,
1741 uint32_t gsvs_ring_size,
1742 struct radeon_winsys_bo *gsvs_ring_bo,
1743 uint32_t tess_factor_ring_size,
1744 uint32_t tess_offchip_ring_offset,
1745 uint32_t tess_offchip_ring_size,
1746 struct radeon_winsys_bo *tess_rings_bo)
1747 {
1748 uint64_t esgs_va = 0, gsvs_va = 0;
1749 uint64_t tess_va = 0, tess_offchip_va = 0;
1750 uint32_t *desc = &map[4];
1751
1752 if (esgs_ring_bo)
1753 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1754 if (gsvs_ring_bo)
1755 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1756 if (tess_rings_bo) {
1757 tess_va = radv_buffer_get_va(tess_rings_bo);
1758 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1759 }
1760
1761 /* stride 0, num records - size, add tid, swizzle, elsize4,
1762 index stride 64 */
1763 desc[0] = esgs_va;
1764 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1765 S_008F04_STRIDE(0) |
1766 S_008F04_SWIZZLE_ENABLE(true);
1767 desc[2] = esgs_ring_size;
1768 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1769 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1770 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1771 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1772 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1773 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1774 S_008F0C_ELEMENT_SIZE(1) |
1775 S_008F0C_INDEX_STRIDE(3) |
1776 S_008F0C_ADD_TID_ENABLE(true);
1777
1778 desc += 4;
1779 /* GS entry for ES->GS ring */
1780 /* stride 0, num records - size, elsize0,
1781 index stride 0 */
1782 desc[0] = esgs_va;
1783 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1784 S_008F04_STRIDE(0) |
1785 S_008F04_SWIZZLE_ENABLE(false);
1786 desc[2] = esgs_ring_size;
1787 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1788 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1789 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1790 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1791 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1792 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1793 S_008F0C_ELEMENT_SIZE(0) |
1794 S_008F0C_INDEX_STRIDE(0) |
1795 S_008F0C_ADD_TID_ENABLE(false);
1796
1797 desc += 4;
1798 /* VS entry for GS->VS ring */
1799 /* stride 0, num records - size, elsize0,
1800 index stride 0 */
1801 desc[0] = gsvs_va;
1802 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1803 S_008F04_STRIDE(0) |
1804 S_008F04_SWIZZLE_ENABLE(false);
1805 desc[2] = gsvs_ring_size;
1806 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1807 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1808 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1809 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1810 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1811 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1812 S_008F0C_ELEMENT_SIZE(0) |
1813 S_008F0C_INDEX_STRIDE(0) |
1814 S_008F0C_ADD_TID_ENABLE(false);
1815 desc += 4;
1816
1817 /* stride gsvs_itemsize, num records 64
1818 elsize 4, index stride 16 */
1819 /* shader will patch stride and desc[2] */
1820 desc[0] = gsvs_va;
1821 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1822 S_008F04_STRIDE(0) |
1823 S_008F04_SWIZZLE_ENABLE(true);
1824 desc[2] = 0;
1825 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1826 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1827 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1828 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1829 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1830 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1831 S_008F0C_ELEMENT_SIZE(1) |
1832 S_008F0C_INDEX_STRIDE(1) |
1833 S_008F0C_ADD_TID_ENABLE(true);
1834 desc += 4;
1835
1836 desc[0] = tess_va;
1837 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1838 S_008F04_STRIDE(0) |
1839 S_008F04_SWIZZLE_ENABLE(false);
1840 desc[2] = tess_factor_ring_size;
1841 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1842 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1843 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1844 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1845 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1846 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1847 S_008F0C_ELEMENT_SIZE(0) |
1848 S_008F0C_INDEX_STRIDE(0) |
1849 S_008F0C_ADD_TID_ENABLE(false);
1850 desc += 4;
1851
1852 desc[0] = tess_offchip_va;
1853 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1854 S_008F04_STRIDE(0) |
1855 S_008F04_SWIZZLE_ENABLE(false);
1856 desc[2] = tess_offchip_ring_size;
1857 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1858 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1859 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1860 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1861 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1862 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1863 S_008F0C_ELEMENT_SIZE(0) |
1864 S_008F0C_INDEX_STRIDE(0) |
1865 S_008F0C_ADD_TID_ENABLE(false);
1866 desc += 4;
1867
1868 /* add sample positions after all rings */
1869 memcpy(desc, queue->device->sample_locations_1x, 8);
1870 desc += 2;
1871 memcpy(desc, queue->device->sample_locations_2x, 16);
1872 desc += 4;
1873 memcpy(desc, queue->device->sample_locations_4x, 32);
1874 desc += 8;
1875 memcpy(desc, queue->device->sample_locations_8x, 64);
1876 desc += 16;
1877 memcpy(desc, queue->device->sample_locations_16x, 128);
1878 }
1879
1880 static unsigned
1881 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1882 {
1883 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1884 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1885 device->physical_device->rad_info.family != CHIP_STONEY;
1886 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1887 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1888 device->physical_device->rad_info.max_se;
1889 unsigned offchip_granularity;
1890 unsigned hs_offchip_param;
1891 switch (device->tess_offchip_block_dw_size) {
1892 default:
1893 assert(0);
1894 /* fall through */
1895 case 8192:
1896 offchip_granularity = V_03093C_X_8K_DWORDS;
1897 break;
1898 case 4096:
1899 offchip_granularity = V_03093C_X_4K_DWORDS;
1900 break;
1901 }
1902
1903 switch (device->physical_device->rad_info.chip_class) {
1904 case SI:
1905 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1906 break;
1907 case CIK:
1908 case VI:
1909 case GFX9:
1910 default:
1911 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1912 break;
1913 }
1914
1915 *max_offchip_buffers_p = max_offchip_buffers;
1916 if (device->physical_device->rad_info.chip_class >= CIK) {
1917 if (device->physical_device->rad_info.chip_class >= VI)
1918 --max_offchip_buffers;
1919 hs_offchip_param =
1920 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1921 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1922 } else {
1923 hs_offchip_param =
1924 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1925 }
1926 return hs_offchip_param;
1927 }
1928
1929 static void
1930 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1931 struct radeon_winsys_bo *esgs_ring_bo,
1932 uint32_t esgs_ring_size,
1933 struct radeon_winsys_bo *gsvs_ring_bo,
1934 uint32_t gsvs_ring_size)
1935 {
1936 if (!esgs_ring_bo && !gsvs_ring_bo)
1937 return;
1938
1939 if (esgs_ring_bo)
1940 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1941
1942 if (gsvs_ring_bo)
1943 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1944
1945 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1946 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1947 radeon_emit(cs, esgs_ring_size >> 8);
1948 radeon_emit(cs, gsvs_ring_size >> 8);
1949 } else {
1950 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1951 radeon_emit(cs, esgs_ring_size >> 8);
1952 radeon_emit(cs, gsvs_ring_size >> 8);
1953 }
1954 }
1955
1956 static void
1957 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1958 unsigned hs_offchip_param, unsigned tf_ring_size,
1959 struct radeon_winsys_bo *tess_rings_bo)
1960 {
1961 uint64_t tf_va;
1962
1963 if (!tess_rings_bo)
1964 return;
1965
1966 tf_va = radv_buffer_get_va(tess_rings_bo);
1967
1968 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
1969
1970 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1971 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1972 S_030938_SIZE(tf_ring_size / 4));
1973 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1974 tf_va >> 8);
1975 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1976 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1977 S_030944_BASE_HI(tf_va >> 40));
1978 }
1979 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1980 hs_offchip_param);
1981 } else {
1982 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1983 S_008988_SIZE(tf_ring_size / 4));
1984 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1985 tf_va >> 8);
1986 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1987 hs_offchip_param);
1988 }
1989 }
1990
1991 static void
1992 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1993 struct radeon_winsys_bo *compute_scratch_bo)
1994 {
1995 uint64_t scratch_va;
1996
1997 if (!compute_scratch_bo)
1998 return;
1999
2000 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2001
2002 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2003
2004 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2005 radeon_emit(cs, scratch_va);
2006 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2007 S_008F04_SWIZZLE_ENABLE(1));
2008 }
2009
2010 static void
2011 radv_emit_global_shader_pointers(struct radv_queue *queue,
2012 struct radeon_cmdbuf *cs,
2013 struct radeon_winsys_bo *descriptor_bo)
2014 {
2015 uint64_t va;
2016
2017 if (!descriptor_bo)
2018 return;
2019
2020 va = radv_buffer_get_va(descriptor_bo);
2021
2022 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2023
2024 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2025 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2026 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2027 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2028 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2029
2030 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2031 radv_emit_shader_pointer(queue->device, cs, regs[i],
2032 va, true);
2033 }
2034 } else {
2035 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2036 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2037 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2038 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2039 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2040 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2041
2042 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2043 radv_emit_shader_pointer(queue->device, cs, regs[i],
2044 va, true);
2045 }
2046 }
2047 }
2048
2049 static VkResult
2050 radv_get_preamble_cs(struct radv_queue *queue,
2051 uint32_t scratch_size,
2052 uint32_t compute_scratch_size,
2053 uint32_t esgs_ring_size,
2054 uint32_t gsvs_ring_size,
2055 bool needs_tess_rings,
2056 bool needs_sample_positions,
2057 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2058 struct radeon_cmdbuf **initial_preamble_cs,
2059 struct radeon_cmdbuf **continue_preamble_cs)
2060 {
2061 struct radeon_winsys_bo *scratch_bo = NULL;
2062 struct radeon_winsys_bo *descriptor_bo = NULL;
2063 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2064 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2065 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2066 struct radeon_winsys_bo *tess_rings_bo = NULL;
2067 struct radeon_cmdbuf *dest_cs[3] = {0};
2068 bool add_tess_rings = false, add_sample_positions = false;
2069 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2070 unsigned max_offchip_buffers;
2071 unsigned hs_offchip_param = 0;
2072 unsigned tess_offchip_ring_offset;
2073 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2074 if (!queue->has_tess_rings) {
2075 if (needs_tess_rings)
2076 add_tess_rings = true;
2077 }
2078 if (!queue->has_sample_positions) {
2079 if (needs_sample_positions)
2080 add_sample_positions = true;
2081 }
2082 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2083 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2084 &max_offchip_buffers);
2085 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2086 tess_offchip_ring_size = max_offchip_buffers *
2087 queue->device->tess_offchip_block_dw_size * 4;
2088
2089 if (scratch_size <= queue->scratch_size &&
2090 compute_scratch_size <= queue->compute_scratch_size &&
2091 esgs_ring_size <= queue->esgs_ring_size &&
2092 gsvs_ring_size <= queue->gsvs_ring_size &&
2093 !add_tess_rings && !add_sample_positions &&
2094 queue->initial_preamble_cs) {
2095 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2096 *initial_preamble_cs = queue->initial_preamble_cs;
2097 *continue_preamble_cs = queue->continue_preamble_cs;
2098 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2099 *continue_preamble_cs = NULL;
2100 return VK_SUCCESS;
2101 }
2102
2103 if (scratch_size > queue->scratch_size) {
2104 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2105 scratch_size,
2106 4096,
2107 RADEON_DOMAIN_VRAM,
2108 ring_bo_flags);
2109 if (!scratch_bo)
2110 goto fail;
2111 } else
2112 scratch_bo = queue->scratch_bo;
2113
2114 if (compute_scratch_size > queue->compute_scratch_size) {
2115 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2116 compute_scratch_size,
2117 4096,
2118 RADEON_DOMAIN_VRAM,
2119 ring_bo_flags);
2120 if (!compute_scratch_bo)
2121 goto fail;
2122
2123 } else
2124 compute_scratch_bo = queue->compute_scratch_bo;
2125
2126 if (esgs_ring_size > queue->esgs_ring_size) {
2127 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2128 esgs_ring_size,
2129 4096,
2130 RADEON_DOMAIN_VRAM,
2131 ring_bo_flags);
2132 if (!esgs_ring_bo)
2133 goto fail;
2134 } else {
2135 esgs_ring_bo = queue->esgs_ring_bo;
2136 esgs_ring_size = queue->esgs_ring_size;
2137 }
2138
2139 if (gsvs_ring_size > queue->gsvs_ring_size) {
2140 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2141 gsvs_ring_size,
2142 4096,
2143 RADEON_DOMAIN_VRAM,
2144 ring_bo_flags);
2145 if (!gsvs_ring_bo)
2146 goto fail;
2147 } else {
2148 gsvs_ring_bo = queue->gsvs_ring_bo;
2149 gsvs_ring_size = queue->gsvs_ring_size;
2150 }
2151
2152 if (add_tess_rings) {
2153 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2154 tess_offchip_ring_offset + tess_offchip_ring_size,
2155 256,
2156 RADEON_DOMAIN_VRAM,
2157 ring_bo_flags);
2158 if (!tess_rings_bo)
2159 goto fail;
2160 } else {
2161 tess_rings_bo = queue->tess_rings_bo;
2162 }
2163
2164 if (scratch_bo != queue->scratch_bo ||
2165 esgs_ring_bo != queue->esgs_ring_bo ||
2166 gsvs_ring_bo != queue->gsvs_ring_bo ||
2167 tess_rings_bo != queue->tess_rings_bo ||
2168 add_sample_positions) {
2169 uint32_t size = 0;
2170 if (gsvs_ring_bo || esgs_ring_bo ||
2171 tess_rings_bo || add_sample_positions) {
2172 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2173 if (add_sample_positions)
2174 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2175 }
2176 else if (scratch_bo)
2177 size = 8; /* 2 dword */
2178
2179 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2180 size,
2181 4096,
2182 RADEON_DOMAIN_VRAM,
2183 RADEON_FLAG_CPU_ACCESS |
2184 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2185 RADEON_FLAG_READ_ONLY);
2186 if (!descriptor_bo)
2187 goto fail;
2188 } else
2189 descriptor_bo = queue->descriptor_bo;
2190
2191 for(int i = 0; i < 3; ++i) {
2192 struct radeon_cmdbuf *cs = NULL;
2193 cs = queue->device->ws->cs_create(queue->device->ws,
2194 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2195 if (!cs)
2196 goto fail;
2197
2198 dest_cs[i] = cs;
2199
2200 if (scratch_bo)
2201 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2202
2203 if (descriptor_bo != queue->descriptor_bo) {
2204 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2205
2206 if (scratch_bo) {
2207 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2208 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2209 S_008F04_SWIZZLE_ENABLE(1);
2210 map[0] = scratch_va;
2211 map[1] = rsrc1;
2212 }
2213
2214 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2215 add_sample_positions)
2216 fill_geom_tess_rings(queue, map, add_sample_positions,
2217 esgs_ring_size, esgs_ring_bo,
2218 gsvs_ring_size, gsvs_ring_bo,
2219 tess_factor_ring_size,
2220 tess_offchip_ring_offset,
2221 tess_offchip_ring_size,
2222 tess_rings_bo);
2223
2224 queue->device->ws->buffer_unmap(descriptor_bo);
2225 }
2226
2227 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2228 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2229 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2230 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2231 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2232 }
2233
2234 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2235 gsvs_ring_bo, gsvs_ring_size);
2236 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2237 tess_factor_ring_size, tess_rings_bo);
2238 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2239 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2240
2241 if (i == 0) {
2242 si_cs_emit_cache_flush(cs,
2243 queue->device->physical_device->rad_info.chip_class,
2244 NULL, 0,
2245 queue->queue_family_index == RING_COMPUTE &&
2246 queue->device->physical_device->rad_info.chip_class >= CIK,
2247 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2248 RADV_CMD_FLAG_INV_ICACHE |
2249 RADV_CMD_FLAG_INV_SMEM_L1 |
2250 RADV_CMD_FLAG_INV_VMEM_L1 |
2251 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2252 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2253 } else if (i == 1) {
2254 si_cs_emit_cache_flush(cs,
2255 queue->device->physical_device->rad_info.chip_class,
2256 NULL, 0,
2257 queue->queue_family_index == RING_COMPUTE &&
2258 queue->device->physical_device->rad_info.chip_class >= CIK,
2259 RADV_CMD_FLAG_INV_ICACHE |
2260 RADV_CMD_FLAG_INV_SMEM_L1 |
2261 RADV_CMD_FLAG_INV_VMEM_L1 |
2262 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2263 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2264 }
2265
2266 if (!queue->device->ws->cs_finalize(cs))
2267 goto fail;
2268 }
2269
2270 if (queue->initial_full_flush_preamble_cs)
2271 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2272
2273 if (queue->initial_preamble_cs)
2274 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2275
2276 if (queue->continue_preamble_cs)
2277 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2278
2279 queue->initial_full_flush_preamble_cs = dest_cs[0];
2280 queue->initial_preamble_cs = dest_cs[1];
2281 queue->continue_preamble_cs = dest_cs[2];
2282
2283 if (scratch_bo != queue->scratch_bo) {
2284 if (queue->scratch_bo)
2285 queue->device->ws->buffer_destroy(queue->scratch_bo);
2286 queue->scratch_bo = scratch_bo;
2287 queue->scratch_size = scratch_size;
2288 }
2289
2290 if (compute_scratch_bo != queue->compute_scratch_bo) {
2291 if (queue->compute_scratch_bo)
2292 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2293 queue->compute_scratch_bo = compute_scratch_bo;
2294 queue->compute_scratch_size = compute_scratch_size;
2295 }
2296
2297 if (esgs_ring_bo != queue->esgs_ring_bo) {
2298 if (queue->esgs_ring_bo)
2299 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2300 queue->esgs_ring_bo = esgs_ring_bo;
2301 queue->esgs_ring_size = esgs_ring_size;
2302 }
2303
2304 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2305 if (queue->gsvs_ring_bo)
2306 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2307 queue->gsvs_ring_bo = gsvs_ring_bo;
2308 queue->gsvs_ring_size = gsvs_ring_size;
2309 }
2310
2311 if (tess_rings_bo != queue->tess_rings_bo) {
2312 queue->tess_rings_bo = tess_rings_bo;
2313 queue->has_tess_rings = true;
2314 }
2315
2316 if (descriptor_bo != queue->descriptor_bo) {
2317 if (queue->descriptor_bo)
2318 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2319
2320 queue->descriptor_bo = descriptor_bo;
2321 }
2322
2323 if (add_sample_positions)
2324 queue->has_sample_positions = true;
2325
2326 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2327 *initial_preamble_cs = queue->initial_preamble_cs;
2328 *continue_preamble_cs = queue->continue_preamble_cs;
2329 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2330 *continue_preamble_cs = NULL;
2331 return VK_SUCCESS;
2332 fail:
2333 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2334 if (dest_cs[i])
2335 queue->device->ws->cs_destroy(dest_cs[i]);
2336 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2337 queue->device->ws->buffer_destroy(descriptor_bo);
2338 if (scratch_bo && scratch_bo != queue->scratch_bo)
2339 queue->device->ws->buffer_destroy(scratch_bo);
2340 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2341 queue->device->ws->buffer_destroy(compute_scratch_bo);
2342 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2343 queue->device->ws->buffer_destroy(esgs_ring_bo);
2344 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2345 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2346 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2347 queue->device->ws->buffer_destroy(tess_rings_bo);
2348 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2349 }
2350
2351 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2352 struct radv_winsys_sem_counts *counts,
2353 int num_sems,
2354 const VkSemaphore *sems,
2355 VkFence _fence,
2356 bool reset_temp)
2357 {
2358 int syncobj_idx = 0, sem_idx = 0;
2359
2360 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2361 return VK_SUCCESS;
2362
2363 for (uint32_t i = 0; i < num_sems; i++) {
2364 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2365
2366 if (sem->temp_syncobj || sem->syncobj)
2367 counts->syncobj_count++;
2368 else
2369 counts->sem_count++;
2370 }
2371
2372 if (_fence != VK_NULL_HANDLE) {
2373 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2374 if (fence->temp_syncobj || fence->syncobj)
2375 counts->syncobj_count++;
2376 }
2377
2378 if (counts->syncobj_count) {
2379 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2380 if (!counts->syncobj)
2381 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2382 }
2383
2384 if (counts->sem_count) {
2385 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2386 if (!counts->sem) {
2387 free(counts->syncobj);
2388 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2389 }
2390 }
2391
2392 for (uint32_t i = 0; i < num_sems; i++) {
2393 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2394
2395 if (sem->temp_syncobj) {
2396 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2397 }
2398 else if (sem->syncobj)
2399 counts->syncobj[syncobj_idx++] = sem->syncobj;
2400 else {
2401 assert(sem->sem);
2402 counts->sem[sem_idx++] = sem->sem;
2403 }
2404 }
2405
2406 if (_fence != VK_NULL_HANDLE) {
2407 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2408 if (fence->temp_syncobj)
2409 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2410 else if (fence->syncobj)
2411 counts->syncobj[syncobj_idx++] = fence->syncobj;
2412 }
2413
2414 return VK_SUCCESS;
2415 }
2416
2417 static void
2418 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2419 {
2420 free(sem_info->wait.syncobj);
2421 free(sem_info->wait.sem);
2422 free(sem_info->signal.syncobj);
2423 free(sem_info->signal.sem);
2424 }
2425
2426
2427 static void radv_free_temp_syncobjs(struct radv_device *device,
2428 int num_sems,
2429 const VkSemaphore *sems)
2430 {
2431 for (uint32_t i = 0; i < num_sems; i++) {
2432 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2433
2434 if (sem->temp_syncobj) {
2435 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2436 sem->temp_syncobj = 0;
2437 }
2438 }
2439 }
2440
2441 static VkResult
2442 radv_alloc_sem_info(struct radv_instance *instance,
2443 struct radv_winsys_sem_info *sem_info,
2444 int num_wait_sems,
2445 const VkSemaphore *wait_sems,
2446 int num_signal_sems,
2447 const VkSemaphore *signal_sems,
2448 VkFence fence)
2449 {
2450 VkResult ret;
2451 memset(sem_info, 0, sizeof(*sem_info));
2452
2453 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2454 if (ret)
2455 return ret;
2456 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2457 if (ret)
2458 radv_free_sem_info(sem_info);
2459
2460 /* caller can override these */
2461 sem_info->cs_emit_wait = true;
2462 sem_info->cs_emit_signal = true;
2463 return ret;
2464 }
2465
2466 /* Signals fence as soon as all the work currently put on queue is done. */
2467 static VkResult radv_signal_fence(struct radv_queue *queue,
2468 struct radv_fence *fence)
2469 {
2470 int ret;
2471 VkResult result;
2472 struct radv_winsys_sem_info sem_info;
2473
2474 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2475 radv_fence_to_handle(fence));
2476 if (result != VK_SUCCESS)
2477 return result;
2478
2479 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2480 &queue->device->empty_cs[queue->queue_family_index],
2481 1, NULL, NULL, &sem_info, NULL,
2482 false, fence->fence);
2483 radv_free_sem_info(&sem_info);
2484
2485 if (ret)
2486 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2487
2488 return VK_SUCCESS;
2489 }
2490
2491 VkResult radv_QueueSubmit(
2492 VkQueue _queue,
2493 uint32_t submitCount,
2494 const VkSubmitInfo* pSubmits,
2495 VkFence _fence)
2496 {
2497 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2498 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2499 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2500 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2501 int ret;
2502 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2503 uint32_t scratch_size = 0;
2504 uint32_t compute_scratch_size = 0;
2505 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2506 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2507 VkResult result;
2508 bool fence_emitted = false;
2509 bool tess_rings_needed = false;
2510 bool sample_positions_needed = false;
2511
2512 /* Do this first so failing to allocate scratch buffers can't result in
2513 * partially executed submissions. */
2514 for (uint32_t i = 0; i < submitCount; i++) {
2515 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2516 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2517 pSubmits[i].pCommandBuffers[j]);
2518
2519 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2520 compute_scratch_size = MAX2(compute_scratch_size,
2521 cmd_buffer->compute_scratch_size_needed);
2522 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2523 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2524 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2525 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2526 }
2527 }
2528
2529 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2530 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2531 sample_positions_needed, &initial_flush_preamble_cs,
2532 &initial_preamble_cs, &continue_preamble_cs);
2533 if (result != VK_SUCCESS)
2534 return result;
2535
2536 for (uint32_t i = 0; i < submitCount; i++) {
2537 struct radeon_cmdbuf **cs_array;
2538 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2539 bool can_patch = true;
2540 uint32_t advance;
2541 struct radv_winsys_sem_info sem_info;
2542
2543 result = radv_alloc_sem_info(queue->device->instance,
2544 &sem_info,
2545 pSubmits[i].waitSemaphoreCount,
2546 pSubmits[i].pWaitSemaphores,
2547 pSubmits[i].signalSemaphoreCount,
2548 pSubmits[i].pSignalSemaphores,
2549 _fence);
2550 if (result != VK_SUCCESS)
2551 return result;
2552
2553 if (!pSubmits[i].commandBufferCount) {
2554 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2555 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2556 &queue->device->empty_cs[queue->queue_family_index],
2557 1, NULL, NULL,
2558 &sem_info, NULL,
2559 false, base_fence);
2560 if (ret) {
2561 radv_loge("failed to submit CS %d\n", i);
2562 abort();
2563 }
2564 fence_emitted = true;
2565 }
2566 radv_free_sem_info(&sem_info);
2567 continue;
2568 }
2569
2570 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2571 (pSubmits[i].commandBufferCount));
2572
2573 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2574 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2575 pSubmits[i].pCommandBuffers[j]);
2576 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2577
2578 cs_array[j] = cmd_buffer->cs;
2579 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2580 can_patch = false;
2581
2582 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2583 }
2584
2585 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2586 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2587 const struct radv_winsys_bo_list *bo_list = NULL;
2588
2589 advance = MIN2(max_cs_submission,
2590 pSubmits[i].commandBufferCount - j);
2591
2592 if (queue->device->trace_bo)
2593 *queue->device->trace_id_ptr = 0;
2594
2595 sem_info.cs_emit_wait = j == 0;
2596 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2597
2598 if (unlikely(queue->device->use_global_bo_list)) {
2599 pthread_mutex_lock(&queue->device->bo_list.mutex);
2600 bo_list = &queue->device->bo_list.list;
2601 }
2602
2603 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2604 advance, initial_preamble, continue_preamble_cs,
2605 &sem_info, bo_list,
2606 can_patch, base_fence);
2607
2608 if (unlikely(queue->device->use_global_bo_list))
2609 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2610
2611 if (ret) {
2612 radv_loge("failed to submit CS %d\n", i);
2613 abort();
2614 }
2615 fence_emitted = true;
2616 if (queue->device->trace_bo) {
2617 radv_check_gpu_hangs(queue, cs_array[j]);
2618 }
2619 }
2620
2621 radv_free_temp_syncobjs(queue->device,
2622 pSubmits[i].waitSemaphoreCount,
2623 pSubmits[i].pWaitSemaphores);
2624 radv_free_sem_info(&sem_info);
2625 free(cs_array);
2626 }
2627
2628 if (fence) {
2629 if (!fence_emitted) {
2630 result = radv_signal_fence(queue, fence);
2631 if (result != VK_SUCCESS)
2632 return result;
2633 }
2634 fence->submitted = true;
2635 }
2636
2637 return VK_SUCCESS;
2638 }
2639
2640 VkResult radv_QueueWaitIdle(
2641 VkQueue _queue)
2642 {
2643 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2644
2645 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2646 radv_queue_family_to_ring(queue->queue_family_index),
2647 queue->queue_idx);
2648 return VK_SUCCESS;
2649 }
2650
2651 VkResult radv_DeviceWaitIdle(
2652 VkDevice _device)
2653 {
2654 RADV_FROM_HANDLE(radv_device, device, _device);
2655
2656 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2657 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2658 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2659 }
2660 }
2661 return VK_SUCCESS;
2662 }
2663
2664 VkResult radv_EnumerateInstanceExtensionProperties(
2665 const char* pLayerName,
2666 uint32_t* pPropertyCount,
2667 VkExtensionProperties* pProperties)
2668 {
2669 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2670
2671 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2672 if (radv_supported_instance_extensions.extensions[i]) {
2673 vk_outarray_append(&out, prop) {
2674 *prop = radv_instance_extensions[i];
2675 }
2676 }
2677 }
2678
2679 return vk_outarray_status(&out);
2680 }
2681
2682 VkResult radv_EnumerateDeviceExtensionProperties(
2683 VkPhysicalDevice physicalDevice,
2684 const char* pLayerName,
2685 uint32_t* pPropertyCount,
2686 VkExtensionProperties* pProperties)
2687 {
2688 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2689 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2690
2691 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2692 if (device->supported_extensions.extensions[i]) {
2693 vk_outarray_append(&out, prop) {
2694 *prop = radv_device_extensions[i];
2695 }
2696 }
2697 }
2698
2699 return vk_outarray_status(&out);
2700 }
2701
2702 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2703 VkInstance _instance,
2704 const char* pName)
2705 {
2706 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2707
2708 return radv_lookup_entrypoint_checked(pName,
2709 instance ? instance->apiVersion : 0,
2710 instance ? &instance->enabled_extensions : NULL,
2711 NULL);
2712 }
2713
2714 /* The loader wants us to expose a second GetInstanceProcAddr function
2715 * to work around certain LD_PRELOAD issues seen in apps.
2716 */
2717 PUBLIC
2718 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2719 VkInstance instance,
2720 const char* pName);
2721
2722 PUBLIC
2723 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2724 VkInstance instance,
2725 const char* pName)
2726 {
2727 return radv_GetInstanceProcAddr(instance, pName);
2728 }
2729
2730 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2731 VkDevice _device,
2732 const char* pName)
2733 {
2734 RADV_FROM_HANDLE(radv_device, device, _device);
2735
2736 return radv_lookup_entrypoint_checked(pName,
2737 device->instance->apiVersion,
2738 &device->instance->enabled_extensions,
2739 &device->enabled_extensions);
2740 }
2741
2742 bool radv_get_memory_fd(struct radv_device *device,
2743 struct radv_device_memory *memory,
2744 int *pFD)
2745 {
2746 struct radeon_bo_metadata metadata;
2747
2748 if (memory->image) {
2749 radv_init_metadata(device, memory->image, &metadata);
2750 device->ws->buffer_set_metadata(memory->bo, &metadata);
2751 }
2752
2753 return device->ws->buffer_get_fd(device->ws, memory->bo,
2754 pFD);
2755 }
2756
2757 static VkResult radv_alloc_memory(struct radv_device *device,
2758 const VkMemoryAllocateInfo* pAllocateInfo,
2759 const VkAllocationCallbacks* pAllocator,
2760 VkDeviceMemory* pMem)
2761 {
2762 struct radv_device_memory *mem;
2763 VkResult result;
2764 enum radeon_bo_domain domain;
2765 uint32_t flags = 0;
2766 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2767
2768 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2769
2770 if (pAllocateInfo->allocationSize == 0) {
2771 /* Apparently, this is allowed */
2772 *pMem = VK_NULL_HANDLE;
2773 return VK_SUCCESS;
2774 }
2775
2776 const VkImportMemoryFdInfoKHR *import_info =
2777 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2778 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2779 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2780 const VkExportMemoryAllocateInfoKHR *export_info =
2781 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2782 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2783 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2784
2785 const struct wsi_memory_allocate_info *wsi_info =
2786 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2787
2788 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2789 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2790 if (mem == NULL)
2791 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2792
2793 if (wsi_info && wsi_info->implicit_sync)
2794 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2795
2796 if (dedicate_info) {
2797 mem->image = radv_image_from_handle(dedicate_info->image);
2798 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2799 } else {
2800 mem->image = NULL;
2801 mem->buffer = NULL;
2802 }
2803
2804 mem->user_ptr = NULL;
2805
2806 if (import_info) {
2807 assert(import_info->handleType ==
2808 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2809 import_info->handleType ==
2810 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2811 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2812 NULL, NULL);
2813 if (!mem->bo) {
2814 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2815 goto fail;
2816 } else {
2817 close(import_info->fd);
2818 }
2819 } else if (host_ptr_info) {
2820 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2821 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2822 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2823 pAllocateInfo->allocationSize);
2824 if (!mem->bo) {
2825 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2826 goto fail;
2827 } else {
2828 mem->user_ptr = host_ptr_info->pHostPointer;
2829 }
2830 } else {
2831 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2832 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2833 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2834 domain = RADEON_DOMAIN_GTT;
2835 else
2836 domain = RADEON_DOMAIN_VRAM;
2837
2838 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2839 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2840 else
2841 flags |= RADEON_FLAG_CPU_ACCESS;
2842
2843 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2844 flags |= RADEON_FLAG_GTT_WC;
2845
2846 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2847 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2848
2849 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2850 domain, flags);
2851
2852 if (!mem->bo) {
2853 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2854 goto fail;
2855 }
2856 mem->type_index = mem_type_index;
2857 }
2858
2859 result = radv_bo_list_add(device, mem->bo);
2860 if (result != VK_SUCCESS)
2861 goto fail_bo;
2862
2863 *pMem = radv_device_memory_to_handle(mem);
2864
2865 return VK_SUCCESS;
2866
2867 fail_bo:
2868 device->ws->buffer_destroy(mem->bo);
2869 fail:
2870 vk_free2(&device->alloc, pAllocator, mem);
2871
2872 return result;
2873 }
2874
2875 VkResult radv_AllocateMemory(
2876 VkDevice _device,
2877 const VkMemoryAllocateInfo* pAllocateInfo,
2878 const VkAllocationCallbacks* pAllocator,
2879 VkDeviceMemory* pMem)
2880 {
2881 RADV_FROM_HANDLE(radv_device, device, _device);
2882 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2883 }
2884
2885 void radv_FreeMemory(
2886 VkDevice _device,
2887 VkDeviceMemory _mem,
2888 const VkAllocationCallbacks* pAllocator)
2889 {
2890 RADV_FROM_HANDLE(radv_device, device, _device);
2891 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2892
2893 if (mem == NULL)
2894 return;
2895
2896 radv_bo_list_remove(device, mem->bo);
2897 device->ws->buffer_destroy(mem->bo);
2898 mem->bo = NULL;
2899
2900 vk_free2(&device->alloc, pAllocator, mem);
2901 }
2902
2903 VkResult radv_MapMemory(
2904 VkDevice _device,
2905 VkDeviceMemory _memory,
2906 VkDeviceSize offset,
2907 VkDeviceSize size,
2908 VkMemoryMapFlags flags,
2909 void** ppData)
2910 {
2911 RADV_FROM_HANDLE(radv_device, device, _device);
2912 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2913
2914 if (mem == NULL) {
2915 *ppData = NULL;
2916 return VK_SUCCESS;
2917 }
2918
2919 if (mem->user_ptr)
2920 *ppData = mem->user_ptr;
2921 else
2922 *ppData = device->ws->buffer_map(mem->bo);
2923
2924 if (*ppData) {
2925 *ppData += offset;
2926 return VK_SUCCESS;
2927 }
2928
2929 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2930 }
2931
2932 void radv_UnmapMemory(
2933 VkDevice _device,
2934 VkDeviceMemory _memory)
2935 {
2936 RADV_FROM_HANDLE(radv_device, device, _device);
2937 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2938
2939 if (mem == NULL)
2940 return;
2941
2942 if (mem->user_ptr == NULL)
2943 device->ws->buffer_unmap(mem->bo);
2944 }
2945
2946 VkResult radv_FlushMappedMemoryRanges(
2947 VkDevice _device,
2948 uint32_t memoryRangeCount,
2949 const VkMappedMemoryRange* pMemoryRanges)
2950 {
2951 return VK_SUCCESS;
2952 }
2953
2954 VkResult radv_InvalidateMappedMemoryRanges(
2955 VkDevice _device,
2956 uint32_t memoryRangeCount,
2957 const VkMappedMemoryRange* pMemoryRanges)
2958 {
2959 return VK_SUCCESS;
2960 }
2961
2962 void radv_GetBufferMemoryRequirements(
2963 VkDevice _device,
2964 VkBuffer _buffer,
2965 VkMemoryRequirements* pMemoryRequirements)
2966 {
2967 RADV_FROM_HANDLE(radv_device, device, _device);
2968 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2969
2970 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2971
2972 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2973 pMemoryRequirements->alignment = 4096;
2974 else
2975 pMemoryRequirements->alignment = 16;
2976
2977 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2978 }
2979
2980 void radv_GetBufferMemoryRequirements2(
2981 VkDevice device,
2982 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2983 VkMemoryRequirements2KHR* pMemoryRequirements)
2984 {
2985 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2986 &pMemoryRequirements->memoryRequirements);
2987 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2988 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2989 switch (ext->sType) {
2990 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2991 VkMemoryDedicatedRequirementsKHR *req =
2992 (VkMemoryDedicatedRequirementsKHR *) ext;
2993 req->requiresDedicatedAllocation = buffer->shareable;
2994 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2995 break;
2996 }
2997 default:
2998 break;
2999 }
3000 }
3001 }
3002
3003 void radv_GetImageMemoryRequirements(
3004 VkDevice _device,
3005 VkImage _image,
3006 VkMemoryRequirements* pMemoryRequirements)
3007 {
3008 RADV_FROM_HANDLE(radv_device, device, _device);
3009 RADV_FROM_HANDLE(radv_image, image, _image);
3010
3011 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3012
3013 pMemoryRequirements->size = image->size;
3014 pMemoryRequirements->alignment = image->alignment;
3015 }
3016
3017 void radv_GetImageMemoryRequirements2(
3018 VkDevice device,
3019 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3020 VkMemoryRequirements2KHR* pMemoryRequirements)
3021 {
3022 radv_GetImageMemoryRequirements(device, pInfo->image,
3023 &pMemoryRequirements->memoryRequirements);
3024
3025 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3026
3027 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3028 switch (ext->sType) {
3029 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3030 VkMemoryDedicatedRequirementsKHR *req =
3031 (VkMemoryDedicatedRequirementsKHR *) ext;
3032 req->requiresDedicatedAllocation = image->shareable;
3033 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3034 break;
3035 }
3036 default:
3037 break;
3038 }
3039 }
3040 }
3041
3042 void radv_GetImageSparseMemoryRequirements(
3043 VkDevice device,
3044 VkImage image,
3045 uint32_t* pSparseMemoryRequirementCount,
3046 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3047 {
3048 stub();
3049 }
3050
3051 void radv_GetImageSparseMemoryRequirements2(
3052 VkDevice device,
3053 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3054 uint32_t* pSparseMemoryRequirementCount,
3055 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3056 {
3057 stub();
3058 }
3059
3060 void radv_GetDeviceMemoryCommitment(
3061 VkDevice device,
3062 VkDeviceMemory memory,
3063 VkDeviceSize* pCommittedMemoryInBytes)
3064 {
3065 *pCommittedMemoryInBytes = 0;
3066 }
3067
3068 VkResult radv_BindBufferMemory2(VkDevice device,
3069 uint32_t bindInfoCount,
3070 const VkBindBufferMemoryInfoKHR *pBindInfos)
3071 {
3072 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3073 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3074 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3075
3076 if (mem) {
3077 buffer->bo = mem->bo;
3078 buffer->offset = pBindInfos[i].memoryOffset;
3079 } else {
3080 buffer->bo = NULL;
3081 }
3082 }
3083 return VK_SUCCESS;
3084 }
3085
3086 VkResult radv_BindBufferMemory(
3087 VkDevice device,
3088 VkBuffer buffer,
3089 VkDeviceMemory memory,
3090 VkDeviceSize memoryOffset)
3091 {
3092 const VkBindBufferMemoryInfoKHR info = {
3093 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3094 .buffer = buffer,
3095 .memory = memory,
3096 .memoryOffset = memoryOffset
3097 };
3098
3099 return radv_BindBufferMemory2(device, 1, &info);
3100 }
3101
3102 VkResult radv_BindImageMemory2(VkDevice device,
3103 uint32_t bindInfoCount,
3104 const VkBindImageMemoryInfoKHR *pBindInfos)
3105 {
3106 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3107 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3108 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3109
3110 if (mem) {
3111 image->bo = mem->bo;
3112 image->offset = pBindInfos[i].memoryOffset;
3113 } else {
3114 image->bo = NULL;
3115 image->offset = 0;
3116 }
3117 }
3118 return VK_SUCCESS;
3119 }
3120
3121
3122 VkResult radv_BindImageMemory(
3123 VkDevice device,
3124 VkImage image,
3125 VkDeviceMemory memory,
3126 VkDeviceSize memoryOffset)
3127 {
3128 const VkBindImageMemoryInfoKHR info = {
3129 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3130 .image = image,
3131 .memory = memory,
3132 .memoryOffset = memoryOffset
3133 };
3134
3135 return radv_BindImageMemory2(device, 1, &info);
3136 }
3137
3138
3139 static void
3140 radv_sparse_buffer_bind_memory(struct radv_device *device,
3141 const VkSparseBufferMemoryBindInfo *bind)
3142 {
3143 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3144
3145 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3146 struct radv_device_memory *mem = NULL;
3147
3148 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3149 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3150
3151 device->ws->buffer_virtual_bind(buffer->bo,
3152 bind->pBinds[i].resourceOffset,
3153 bind->pBinds[i].size,
3154 mem ? mem->bo : NULL,
3155 bind->pBinds[i].memoryOffset);
3156 }
3157 }
3158
3159 static void
3160 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3161 const VkSparseImageOpaqueMemoryBindInfo *bind)
3162 {
3163 RADV_FROM_HANDLE(radv_image, image, bind->image);
3164
3165 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3166 struct radv_device_memory *mem = NULL;
3167
3168 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3169 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3170
3171 device->ws->buffer_virtual_bind(image->bo,
3172 bind->pBinds[i].resourceOffset,
3173 bind->pBinds[i].size,
3174 mem ? mem->bo : NULL,
3175 bind->pBinds[i].memoryOffset);
3176 }
3177 }
3178
3179 VkResult radv_QueueBindSparse(
3180 VkQueue _queue,
3181 uint32_t bindInfoCount,
3182 const VkBindSparseInfo* pBindInfo,
3183 VkFence _fence)
3184 {
3185 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3186 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3187 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3188 bool fence_emitted = false;
3189 VkResult result;
3190 int ret;
3191
3192 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3193 struct radv_winsys_sem_info sem_info;
3194 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3195 radv_sparse_buffer_bind_memory(queue->device,
3196 pBindInfo[i].pBufferBinds + j);
3197 }
3198
3199 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3200 radv_sparse_image_opaque_bind_memory(queue->device,
3201 pBindInfo[i].pImageOpaqueBinds + j);
3202 }
3203
3204 VkResult result;
3205 result = radv_alloc_sem_info(queue->device->instance,
3206 &sem_info,
3207 pBindInfo[i].waitSemaphoreCount,
3208 pBindInfo[i].pWaitSemaphores,
3209 pBindInfo[i].signalSemaphoreCount,
3210 pBindInfo[i].pSignalSemaphores,
3211 _fence);
3212 if (result != VK_SUCCESS)
3213 return result;
3214
3215 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3216 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3217 &queue->device->empty_cs[queue->queue_family_index],
3218 1, NULL, NULL,
3219 &sem_info, NULL,
3220 false, base_fence);
3221 if (ret) {
3222 radv_loge("failed to submit CS %d\n", i);
3223 abort();
3224 }
3225
3226 fence_emitted = true;
3227 if (fence)
3228 fence->submitted = true;
3229 }
3230
3231 radv_free_sem_info(&sem_info);
3232
3233 }
3234
3235 if (fence) {
3236 if (!fence_emitted) {
3237 result = radv_signal_fence(queue, fence);
3238 if (result != VK_SUCCESS)
3239 return result;
3240 }
3241 fence->submitted = true;
3242 }
3243
3244 return VK_SUCCESS;
3245 }
3246
3247 VkResult radv_CreateFence(
3248 VkDevice _device,
3249 const VkFenceCreateInfo* pCreateInfo,
3250 const VkAllocationCallbacks* pAllocator,
3251 VkFence* pFence)
3252 {
3253 RADV_FROM_HANDLE(radv_device, device, _device);
3254 const VkExportFenceCreateInfoKHR *export =
3255 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3256 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3257 export ? export->handleTypes : 0;
3258
3259 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3260 sizeof(*fence), 8,
3261 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3262
3263 if (!fence)
3264 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3265
3266 fence->fence_wsi = NULL;
3267 fence->submitted = false;
3268 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3269 fence->temp_syncobj = 0;
3270 if (device->always_use_syncobj || handleTypes) {
3271 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3272 if (ret) {
3273 vk_free2(&device->alloc, pAllocator, fence);
3274 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3275 }
3276 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3277 device->ws->signal_syncobj(device->ws, fence->syncobj);
3278 }
3279 fence->fence = NULL;
3280 } else {
3281 fence->fence = device->ws->create_fence();
3282 if (!fence->fence) {
3283 vk_free2(&device->alloc, pAllocator, fence);
3284 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3285 }
3286 fence->syncobj = 0;
3287 }
3288
3289 *pFence = radv_fence_to_handle(fence);
3290
3291 return VK_SUCCESS;
3292 }
3293
3294 void radv_DestroyFence(
3295 VkDevice _device,
3296 VkFence _fence,
3297 const VkAllocationCallbacks* pAllocator)
3298 {
3299 RADV_FROM_HANDLE(radv_device, device, _device);
3300 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3301
3302 if (!fence)
3303 return;
3304
3305 if (fence->temp_syncobj)
3306 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3307 if (fence->syncobj)
3308 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3309 if (fence->fence)
3310 device->ws->destroy_fence(fence->fence);
3311 if (fence->fence_wsi)
3312 fence->fence_wsi->destroy(fence->fence_wsi);
3313 vk_free2(&device->alloc, pAllocator, fence);
3314 }
3315
3316
3317 static uint64_t radv_get_current_time()
3318 {
3319 struct timespec tv;
3320 clock_gettime(CLOCK_MONOTONIC, &tv);
3321 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3322 }
3323
3324 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3325 {
3326 uint64_t current_time = radv_get_current_time();
3327
3328 timeout = MIN2(UINT64_MAX - current_time, timeout);
3329
3330 return current_time + timeout;
3331 }
3332
3333
3334 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3335 {
3336 for (uint32_t i = 0; i < fenceCount; ++i) {
3337 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3338 if (fence->fence == NULL || fence->syncobj ||
3339 fence->temp_syncobj ||
3340 (!fence->signalled && !fence->submitted))
3341 return false;
3342 }
3343 return true;
3344 }
3345
3346 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3347 {
3348 for (uint32_t i = 0; i < fenceCount; ++i) {
3349 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3350 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3351 return false;
3352 }
3353 return true;
3354 }
3355
3356 VkResult radv_WaitForFences(
3357 VkDevice _device,
3358 uint32_t fenceCount,
3359 const VkFence* pFences,
3360 VkBool32 waitAll,
3361 uint64_t timeout)
3362 {
3363 RADV_FROM_HANDLE(radv_device, device, _device);
3364 timeout = radv_get_absolute_timeout(timeout);
3365
3366 if (device->always_use_syncobj &&
3367 radv_all_fences_syncobj(fenceCount, pFences))
3368 {
3369 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3370 if (!handles)
3371 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3372
3373 for (uint32_t i = 0; i < fenceCount; ++i) {
3374 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3375 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3376 }
3377
3378 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3379
3380 free(handles);
3381 return success ? VK_SUCCESS : VK_TIMEOUT;
3382 }
3383
3384 if (!waitAll && fenceCount > 1) {
3385 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3386 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3387 uint32_t wait_count = 0;
3388 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3389 if (!fences)
3390 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3391
3392 for (uint32_t i = 0; i < fenceCount; ++i) {
3393 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3394
3395 if (fence->signalled) {
3396 free(fences);
3397 return VK_SUCCESS;
3398 }
3399
3400 fences[wait_count++] = fence->fence;
3401 }
3402
3403 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3404 waitAll, timeout - radv_get_current_time());
3405
3406 free(fences);
3407 return success ? VK_SUCCESS : VK_TIMEOUT;
3408 }
3409
3410 while(radv_get_current_time() <= timeout) {
3411 for (uint32_t i = 0; i < fenceCount; ++i) {
3412 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3413 return VK_SUCCESS;
3414 }
3415 }
3416 return VK_TIMEOUT;
3417 }
3418
3419 for (uint32_t i = 0; i < fenceCount; ++i) {
3420 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3421 bool expired = false;
3422
3423 if (fence->temp_syncobj) {
3424 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3425 return VK_TIMEOUT;
3426 continue;
3427 }
3428
3429 if (fence->syncobj) {
3430 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3431 return VK_TIMEOUT;
3432 continue;
3433 }
3434
3435 if (fence->signalled)
3436 continue;
3437
3438 if (fence->fence) {
3439 if (!fence->submitted) {
3440 while(radv_get_current_time() <= timeout &&
3441 !fence->submitted)
3442 /* Do nothing */;
3443
3444 if (!fence->submitted)
3445 return VK_TIMEOUT;
3446
3447 /* Recheck as it may have been set by
3448 * submitting operations. */
3449
3450 if (fence->signalled)
3451 continue;
3452 }
3453
3454 expired = device->ws->fence_wait(device->ws,
3455 fence->fence,
3456 true, timeout);
3457 if (!expired)
3458 return VK_TIMEOUT;
3459 }
3460
3461 if (fence->fence_wsi) {
3462 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3463 if (result != VK_SUCCESS)
3464 return result;
3465 }
3466
3467 fence->signalled = true;
3468 }
3469
3470 return VK_SUCCESS;
3471 }
3472
3473 VkResult radv_ResetFences(VkDevice _device,
3474 uint32_t fenceCount,
3475 const VkFence *pFences)
3476 {
3477 RADV_FROM_HANDLE(radv_device, device, _device);
3478
3479 for (unsigned i = 0; i < fenceCount; ++i) {
3480 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3481 fence->submitted = fence->signalled = false;
3482
3483 /* Per spec, we first restore the permanent payload, and then reset, so
3484 * having a temp syncobj should not skip resetting the permanent syncobj. */
3485 if (fence->temp_syncobj) {
3486 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3487 fence->temp_syncobj = 0;
3488 }
3489
3490 if (fence->syncobj) {
3491 device->ws->reset_syncobj(device->ws, fence->syncobj);
3492 }
3493 }
3494
3495 return VK_SUCCESS;
3496 }
3497
3498 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3499 {
3500 RADV_FROM_HANDLE(radv_device, device, _device);
3501 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3502
3503 if (fence->temp_syncobj) {
3504 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3505 return success ? VK_SUCCESS : VK_NOT_READY;
3506 }
3507
3508 if (fence->syncobj) {
3509 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3510 return success ? VK_SUCCESS : VK_NOT_READY;
3511 }
3512
3513 if (fence->signalled)
3514 return VK_SUCCESS;
3515 if (!fence->submitted)
3516 return VK_NOT_READY;
3517 if (fence->fence) {
3518 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3519 return VK_NOT_READY;
3520 }
3521 if (fence->fence_wsi) {
3522 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3523
3524 if (result != VK_SUCCESS) {
3525 if (result == VK_TIMEOUT)
3526 return VK_NOT_READY;
3527 return result;
3528 }
3529 }
3530 return VK_SUCCESS;
3531 }
3532
3533
3534 // Queue semaphore functions
3535
3536 VkResult radv_CreateSemaphore(
3537 VkDevice _device,
3538 const VkSemaphoreCreateInfo* pCreateInfo,
3539 const VkAllocationCallbacks* pAllocator,
3540 VkSemaphore* pSemaphore)
3541 {
3542 RADV_FROM_HANDLE(radv_device, device, _device);
3543 const VkExportSemaphoreCreateInfoKHR *export =
3544 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3545 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3546 export ? export->handleTypes : 0;
3547
3548 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3549 sizeof(*sem), 8,
3550 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3551 if (!sem)
3552 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3553
3554 sem->temp_syncobj = 0;
3555 /* create a syncobject if we are going to export this semaphore */
3556 if (device->always_use_syncobj || handleTypes) {
3557 assert (device->physical_device->rad_info.has_syncobj);
3558 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3559 if (ret) {
3560 vk_free2(&device->alloc, pAllocator, sem);
3561 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3562 }
3563 sem->sem = NULL;
3564 } else {
3565 sem->sem = device->ws->create_sem(device->ws);
3566 if (!sem->sem) {
3567 vk_free2(&device->alloc, pAllocator, sem);
3568 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3569 }
3570 sem->syncobj = 0;
3571 }
3572
3573 *pSemaphore = radv_semaphore_to_handle(sem);
3574 return VK_SUCCESS;
3575 }
3576
3577 void radv_DestroySemaphore(
3578 VkDevice _device,
3579 VkSemaphore _semaphore,
3580 const VkAllocationCallbacks* pAllocator)
3581 {
3582 RADV_FROM_HANDLE(radv_device, device, _device);
3583 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3584 if (!_semaphore)
3585 return;
3586
3587 if (sem->syncobj)
3588 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3589 else
3590 device->ws->destroy_sem(sem->sem);
3591 vk_free2(&device->alloc, pAllocator, sem);
3592 }
3593
3594 VkResult radv_CreateEvent(
3595 VkDevice _device,
3596 const VkEventCreateInfo* pCreateInfo,
3597 const VkAllocationCallbacks* pAllocator,
3598 VkEvent* pEvent)
3599 {
3600 RADV_FROM_HANDLE(radv_device, device, _device);
3601 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3602 sizeof(*event), 8,
3603 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3604
3605 if (!event)
3606 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3607
3608 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3609 RADEON_DOMAIN_GTT,
3610 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3611 if (!event->bo) {
3612 vk_free2(&device->alloc, pAllocator, event);
3613 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3614 }
3615
3616 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3617
3618 *pEvent = radv_event_to_handle(event);
3619
3620 return VK_SUCCESS;
3621 }
3622
3623 void radv_DestroyEvent(
3624 VkDevice _device,
3625 VkEvent _event,
3626 const VkAllocationCallbacks* pAllocator)
3627 {
3628 RADV_FROM_HANDLE(radv_device, device, _device);
3629 RADV_FROM_HANDLE(radv_event, event, _event);
3630
3631 if (!event)
3632 return;
3633 device->ws->buffer_destroy(event->bo);
3634 vk_free2(&device->alloc, pAllocator, event);
3635 }
3636
3637 VkResult radv_GetEventStatus(
3638 VkDevice _device,
3639 VkEvent _event)
3640 {
3641 RADV_FROM_HANDLE(radv_event, event, _event);
3642
3643 if (*event->map == 1)
3644 return VK_EVENT_SET;
3645 return VK_EVENT_RESET;
3646 }
3647
3648 VkResult radv_SetEvent(
3649 VkDevice _device,
3650 VkEvent _event)
3651 {
3652 RADV_FROM_HANDLE(radv_event, event, _event);
3653 *event->map = 1;
3654
3655 return VK_SUCCESS;
3656 }
3657
3658 VkResult radv_ResetEvent(
3659 VkDevice _device,
3660 VkEvent _event)
3661 {
3662 RADV_FROM_HANDLE(radv_event, event, _event);
3663 *event->map = 0;
3664
3665 return VK_SUCCESS;
3666 }
3667
3668 VkResult radv_CreateBuffer(
3669 VkDevice _device,
3670 const VkBufferCreateInfo* pCreateInfo,
3671 const VkAllocationCallbacks* pAllocator,
3672 VkBuffer* pBuffer)
3673 {
3674 RADV_FROM_HANDLE(radv_device, device, _device);
3675 struct radv_buffer *buffer;
3676
3677 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3678
3679 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3680 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3681 if (buffer == NULL)
3682 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3683
3684 buffer->size = pCreateInfo->size;
3685 buffer->usage = pCreateInfo->usage;
3686 buffer->bo = NULL;
3687 buffer->offset = 0;
3688 buffer->flags = pCreateInfo->flags;
3689
3690 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3691 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3692
3693 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3694 buffer->bo = device->ws->buffer_create(device->ws,
3695 align64(buffer->size, 4096),
3696 4096, 0, RADEON_FLAG_VIRTUAL);
3697 if (!buffer->bo) {
3698 vk_free2(&device->alloc, pAllocator, buffer);
3699 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3700 }
3701 }
3702
3703 *pBuffer = radv_buffer_to_handle(buffer);
3704
3705 return VK_SUCCESS;
3706 }
3707
3708 void radv_DestroyBuffer(
3709 VkDevice _device,
3710 VkBuffer _buffer,
3711 const VkAllocationCallbacks* pAllocator)
3712 {
3713 RADV_FROM_HANDLE(radv_device, device, _device);
3714 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3715
3716 if (!buffer)
3717 return;
3718
3719 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3720 device->ws->buffer_destroy(buffer->bo);
3721
3722 vk_free2(&device->alloc, pAllocator, buffer);
3723 }
3724
3725 static inline unsigned
3726 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3727 {
3728 if (stencil)
3729 return image->surface.u.legacy.stencil_tiling_index[level];
3730 else
3731 return image->surface.u.legacy.tiling_index[level];
3732 }
3733
3734 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3735 {
3736 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3737 }
3738
3739 static uint32_t
3740 radv_init_dcc_control_reg(struct radv_device *device,
3741 struct radv_image_view *iview)
3742 {
3743 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3744 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3745 unsigned max_compressed_block_size;
3746 unsigned independent_64b_blocks;
3747
3748 if (device->physical_device->rad_info.chip_class < VI)
3749 return 0;
3750
3751 if (iview->image->info.samples > 1) {
3752 if (iview->image->surface.bpe == 1)
3753 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3754 else if (iview->image->surface.bpe == 2)
3755 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3756 }
3757
3758 if (!device->physical_device->rad_info.has_dedicated_vram) {
3759 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3760 * dGPU and 64 for APU because all of our APUs to date use
3761 * DIMMs which have a request granularity size of 64B while all
3762 * other chips have a 32B request size.
3763 */
3764 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3765 }
3766
3767 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3768 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3769 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3770 /* If this DCC image is potentially going to be used in texture
3771 * fetches, we need some special settings.
3772 */
3773 independent_64b_blocks = 1;
3774 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3775 } else {
3776 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3777 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3778 * big as possible for better compression state.
3779 */
3780 independent_64b_blocks = 0;
3781 max_compressed_block_size = max_uncompressed_block_size;
3782 }
3783
3784 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3785 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3786 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3787 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3788 }
3789
3790 static void
3791 radv_initialise_color_surface(struct radv_device *device,
3792 struct radv_color_buffer_info *cb,
3793 struct radv_image_view *iview)
3794 {
3795 const struct vk_format_description *desc;
3796 unsigned ntype, format, swap, endian;
3797 unsigned blend_clamp = 0, blend_bypass = 0;
3798 uint64_t va;
3799 const struct radeon_surf *surf = &iview->image->surface;
3800
3801 desc = vk_format_description(iview->vk_format);
3802
3803 memset(cb, 0, sizeof(*cb));
3804
3805 /* Intensity is implemented as Red, so treat it that way. */
3806 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3807
3808 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3809
3810 cb->cb_color_base = va >> 8;
3811
3812 if (device->physical_device->rad_info.chip_class >= GFX9) {
3813 struct gfx9_surf_meta_flags meta;
3814 if (iview->image->dcc_offset)
3815 meta = iview->image->surface.u.gfx9.dcc;
3816 else
3817 meta = iview->image->surface.u.gfx9.cmask;
3818
3819 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3820 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3821 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3822 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3823
3824 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3825 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3826 } else {
3827 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3828 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3829
3830 cb->cb_color_base += level_info->offset >> 8;
3831 if (level_info->mode == RADEON_SURF_MODE_2D)
3832 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3833
3834 pitch_tile_max = level_info->nblk_x / 8 - 1;
3835 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3836 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3837
3838 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3839 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3840 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3841
3842 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3843
3844 if (radv_image_has_fmask(iview->image)) {
3845 if (device->physical_device->rad_info.chip_class >= CIK)
3846 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3847 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3848 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3849 } else {
3850 /* This must be set for fast clear to work without FMASK. */
3851 if (device->physical_device->rad_info.chip_class >= CIK)
3852 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3853 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3854 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3855 }
3856 }
3857
3858 /* CMASK variables */
3859 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3860 va += iview->image->cmask.offset;
3861 cb->cb_color_cmask = va >> 8;
3862
3863 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3864 va += iview->image->dcc_offset;
3865 cb->cb_dcc_base = va >> 8;
3866 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3867
3868 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3869 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3870 S_028C6C_SLICE_MAX(max_slice);
3871
3872 if (iview->image->info.samples > 1) {
3873 unsigned log_samples = util_logbase2(iview->image->info.samples);
3874
3875 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3876 S_028C74_NUM_FRAGMENTS(log_samples);
3877 }
3878
3879 if (radv_image_has_fmask(iview->image)) {
3880 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3881 cb->cb_color_fmask = va >> 8;
3882 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3883 } else {
3884 cb->cb_color_fmask = cb->cb_color_base;
3885 }
3886
3887 ntype = radv_translate_color_numformat(iview->vk_format,
3888 desc,
3889 vk_format_get_first_non_void_channel(iview->vk_format));
3890 format = radv_translate_colorformat(iview->vk_format);
3891 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3892 radv_finishme("Illegal color\n");
3893 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3894 endian = radv_colorformat_endian_swap(format);
3895
3896 /* blend clamp should be set for all NORM/SRGB types */
3897 if (ntype == V_028C70_NUMBER_UNORM ||
3898 ntype == V_028C70_NUMBER_SNORM ||
3899 ntype == V_028C70_NUMBER_SRGB)
3900 blend_clamp = 1;
3901
3902 /* set blend bypass according to docs if SINT/UINT or
3903 8/24 COLOR variants */
3904 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3905 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3906 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3907 blend_clamp = 0;
3908 blend_bypass = 1;
3909 }
3910 #if 0
3911 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3912 (format == V_028C70_COLOR_8 ||
3913 format == V_028C70_COLOR_8_8 ||
3914 format == V_028C70_COLOR_8_8_8_8))
3915 ->color_is_int8 = true;
3916 #endif
3917 cb->cb_color_info = S_028C70_FORMAT(format) |
3918 S_028C70_COMP_SWAP(swap) |
3919 S_028C70_BLEND_CLAMP(blend_clamp) |
3920 S_028C70_BLEND_BYPASS(blend_bypass) |
3921 S_028C70_SIMPLE_FLOAT(1) |
3922 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3923 ntype != V_028C70_NUMBER_SNORM &&
3924 ntype != V_028C70_NUMBER_SRGB &&
3925 format != V_028C70_COLOR_8_24 &&
3926 format != V_028C70_COLOR_24_8) |
3927 S_028C70_NUMBER_TYPE(ntype) |
3928 S_028C70_ENDIAN(endian);
3929 if (radv_image_has_fmask(iview->image)) {
3930 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3931 if (device->physical_device->rad_info.chip_class == SI) {
3932 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3933 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3934 }
3935 }
3936
3937 if (radv_image_has_cmask(iview->image) &&
3938 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3939 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3940
3941 if (radv_dcc_enabled(iview->image, iview->base_mip))
3942 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3943
3944 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3945
3946 /* This must be set for fast clear to work without FMASK. */
3947 if (!radv_image_has_fmask(iview->image) &&
3948 device->physical_device->rad_info.chip_class == SI) {
3949 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3950 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3951 }
3952
3953 if (device->physical_device->rad_info.chip_class >= GFX9) {
3954 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3955 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3956
3957 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3958 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3959 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3960 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3961 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3962 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3963 }
3964 }
3965
3966 static unsigned
3967 radv_calc_decompress_on_z_planes(struct radv_device *device,
3968 struct radv_image_view *iview)
3969 {
3970 unsigned max_zplanes = 0;
3971
3972 assert(radv_image_is_tc_compat_htile(iview->image));
3973
3974 if (device->physical_device->rad_info.chip_class >= GFX9) {
3975 /* Default value for 32-bit depth surfaces. */
3976 max_zplanes = 4;
3977
3978 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3979 iview->image->info.samples > 1)
3980 max_zplanes = 2;
3981
3982 max_zplanes = max_zplanes + 1;
3983 } else {
3984 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3985 /* Do not enable Z plane compression for 16-bit depth
3986 * surfaces because isn't supported on GFX8. Only
3987 * 32-bit depth surfaces are supported by the hardware.
3988 * This allows to maintain shader compatibility and to
3989 * reduce the number of depth decompressions.
3990 */
3991 max_zplanes = 1;
3992 } else {
3993 if (iview->image->info.samples <= 1)
3994 max_zplanes = 5;
3995 else if (iview->image->info.samples <= 4)
3996 max_zplanes = 3;
3997 else
3998 max_zplanes = 2;
3999 }
4000 }
4001
4002 return max_zplanes;
4003 }
4004
4005 static void
4006 radv_initialise_ds_surface(struct radv_device *device,
4007 struct radv_ds_buffer_info *ds,
4008 struct radv_image_view *iview)
4009 {
4010 unsigned level = iview->base_mip;
4011 unsigned format, stencil_format;
4012 uint64_t va, s_offs, z_offs;
4013 bool stencil_only = false;
4014 memset(ds, 0, sizeof(*ds));
4015 switch (iview->image->vk_format) {
4016 case VK_FORMAT_D24_UNORM_S8_UINT:
4017 case VK_FORMAT_X8_D24_UNORM_PACK32:
4018 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4019 ds->offset_scale = 2.0f;
4020 break;
4021 case VK_FORMAT_D16_UNORM:
4022 case VK_FORMAT_D16_UNORM_S8_UINT:
4023 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4024 ds->offset_scale = 4.0f;
4025 break;
4026 case VK_FORMAT_D32_SFLOAT:
4027 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4028 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4029 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4030 ds->offset_scale = 1.0f;
4031 break;
4032 case VK_FORMAT_S8_UINT:
4033 stencil_only = true;
4034 break;
4035 default:
4036 break;
4037 }
4038
4039 format = radv_translate_dbformat(iview->image->vk_format);
4040 stencil_format = iview->image->surface.has_stencil ?
4041 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4042
4043 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4044 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4045 S_028008_SLICE_MAX(max_slice);
4046
4047 ds->db_htile_data_base = 0;
4048 ds->db_htile_surface = 0;
4049
4050 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4051 s_offs = z_offs = va;
4052
4053 if (device->physical_device->rad_info.chip_class >= GFX9) {
4054 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4055 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4056
4057 ds->db_z_info = S_028038_FORMAT(format) |
4058 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4059 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4060 S_028038_MAXMIP(iview->image->info.levels - 1) |
4061 S_028038_ZRANGE_PRECISION(1);
4062 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4063 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4064
4065 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4066 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4067 ds->db_depth_view |= S_028008_MIPID(level);
4068
4069 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4070 S_02801C_Y_MAX(iview->image->info.height - 1);
4071
4072 if (radv_htile_enabled(iview->image, level)) {
4073 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4074
4075 if (radv_image_is_tc_compat_htile(iview->image)) {
4076 unsigned max_zplanes =
4077 radv_calc_decompress_on_z_planes(device, iview);
4078
4079 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4080 S_028038_ITERATE_FLUSH(1);
4081 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4082 }
4083
4084 if (!iview->image->surface.has_stencil)
4085 /* Use all of the htile_buffer for depth if there's no stencil. */
4086 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4087 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4088 iview->image->htile_offset;
4089 ds->db_htile_data_base = va >> 8;
4090 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4091 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4092 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4093 }
4094 } else {
4095 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4096
4097 if (stencil_only)
4098 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4099
4100 z_offs += iview->image->surface.u.legacy.level[level].offset;
4101 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4102
4103 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4104 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4105 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4106
4107 if (iview->image->info.samples > 1)
4108 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4109
4110 if (device->physical_device->rad_info.chip_class >= CIK) {
4111 struct radeon_info *info = &device->physical_device->rad_info;
4112 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4113 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4114 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4115 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4116 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4117 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4118
4119 if (stencil_only)
4120 tile_mode = stencil_tile_mode;
4121
4122 ds->db_depth_info |=
4123 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4124 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4125 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4126 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4127 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4128 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4129 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4130 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4131 } else {
4132 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4133 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4134 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4135 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4136 if (stencil_only)
4137 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4138 }
4139
4140 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4141 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4142 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4143
4144 if (radv_htile_enabled(iview->image, level)) {
4145 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4146
4147 if (!iview->image->surface.has_stencil &&
4148 !radv_image_is_tc_compat_htile(iview->image))
4149 /* Use all of the htile_buffer for depth if there's no stencil. */
4150 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4151
4152 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4153 iview->image->htile_offset;
4154 ds->db_htile_data_base = va >> 8;
4155 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4156
4157 if (radv_image_is_tc_compat_htile(iview->image)) {
4158 unsigned max_zplanes =
4159 radv_calc_decompress_on_z_planes(device, iview);
4160
4161 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4162 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4163 }
4164 }
4165 }
4166
4167 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4168 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4169 }
4170
4171 VkResult radv_CreateFramebuffer(
4172 VkDevice _device,
4173 const VkFramebufferCreateInfo* pCreateInfo,
4174 const VkAllocationCallbacks* pAllocator,
4175 VkFramebuffer* pFramebuffer)
4176 {
4177 RADV_FROM_HANDLE(radv_device, device, _device);
4178 struct radv_framebuffer *framebuffer;
4179
4180 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4181
4182 size_t size = sizeof(*framebuffer) +
4183 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4184 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4185 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4186 if (framebuffer == NULL)
4187 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4188
4189 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4190 framebuffer->width = pCreateInfo->width;
4191 framebuffer->height = pCreateInfo->height;
4192 framebuffer->layers = pCreateInfo->layers;
4193 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4194 VkImageView _iview = pCreateInfo->pAttachments[i];
4195 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4196 framebuffer->attachments[i].attachment = iview;
4197 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4198 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4199 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4200 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4201 }
4202 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4203 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4204 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4205 }
4206
4207 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4208 return VK_SUCCESS;
4209 }
4210
4211 void radv_DestroyFramebuffer(
4212 VkDevice _device,
4213 VkFramebuffer _fb,
4214 const VkAllocationCallbacks* pAllocator)
4215 {
4216 RADV_FROM_HANDLE(radv_device, device, _device);
4217 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4218
4219 if (!fb)
4220 return;
4221 vk_free2(&device->alloc, pAllocator, fb);
4222 }
4223
4224 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4225 {
4226 switch (address_mode) {
4227 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4228 return V_008F30_SQ_TEX_WRAP;
4229 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4230 return V_008F30_SQ_TEX_MIRROR;
4231 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4232 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4233 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4234 return V_008F30_SQ_TEX_CLAMP_BORDER;
4235 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4236 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4237 default:
4238 unreachable("illegal tex wrap mode");
4239 break;
4240 }
4241 }
4242
4243 static unsigned
4244 radv_tex_compare(VkCompareOp op)
4245 {
4246 switch (op) {
4247 case VK_COMPARE_OP_NEVER:
4248 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4249 case VK_COMPARE_OP_LESS:
4250 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4251 case VK_COMPARE_OP_EQUAL:
4252 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4253 case VK_COMPARE_OP_LESS_OR_EQUAL:
4254 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4255 case VK_COMPARE_OP_GREATER:
4256 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4257 case VK_COMPARE_OP_NOT_EQUAL:
4258 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4259 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4260 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4261 case VK_COMPARE_OP_ALWAYS:
4262 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4263 default:
4264 unreachable("illegal compare mode");
4265 break;
4266 }
4267 }
4268
4269 static unsigned
4270 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4271 {
4272 switch (filter) {
4273 case VK_FILTER_NEAREST:
4274 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4275 V_008F38_SQ_TEX_XY_FILTER_POINT);
4276 case VK_FILTER_LINEAR:
4277 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4278 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4279 case VK_FILTER_CUBIC_IMG:
4280 default:
4281 fprintf(stderr, "illegal texture filter");
4282 return 0;
4283 }
4284 }
4285
4286 static unsigned
4287 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4288 {
4289 switch (mode) {
4290 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4291 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4292 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4293 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4294 default:
4295 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4296 }
4297 }
4298
4299 static unsigned
4300 radv_tex_bordercolor(VkBorderColor bcolor)
4301 {
4302 switch (bcolor) {
4303 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4304 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4305 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4306 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4307 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4308 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4309 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4310 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4311 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4312 default:
4313 break;
4314 }
4315 return 0;
4316 }
4317
4318 static unsigned
4319 radv_tex_aniso_filter(unsigned filter)
4320 {
4321 if (filter < 2)
4322 return 0;
4323 if (filter < 4)
4324 return 1;
4325 if (filter < 8)
4326 return 2;
4327 if (filter < 16)
4328 return 3;
4329 return 4;
4330 }
4331
4332 static unsigned
4333 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4334 {
4335 switch (mode) {
4336 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4337 return SQ_IMG_FILTER_MODE_BLEND;
4338 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4339 return SQ_IMG_FILTER_MODE_MIN;
4340 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4341 return SQ_IMG_FILTER_MODE_MAX;
4342 default:
4343 break;
4344 }
4345 return 0;
4346 }
4347
4348 static void
4349 radv_init_sampler(struct radv_device *device,
4350 struct radv_sampler *sampler,
4351 const VkSamplerCreateInfo *pCreateInfo)
4352 {
4353 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4354 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4355 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4356 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4357 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4358
4359 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4360 vk_find_struct_const(pCreateInfo->pNext,
4361 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4362 if (sampler_reduction)
4363 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4364
4365 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4366 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4367 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4368 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4369 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4370 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4371 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4372 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4373 S_008F30_DISABLE_CUBE_WRAP(0) |
4374 S_008F30_COMPAT_MODE(is_vi) |
4375 S_008F30_FILTER_MODE(filter_mode));
4376 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4377 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4378 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4379 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4380 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4381 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4382 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4383 S_008F38_MIP_POINT_PRECLAMP(0) |
4384 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4385 S_008F38_FILTER_PREC_FIX(1) |
4386 S_008F38_ANISO_OVERRIDE(is_vi));
4387 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4388 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4389 }
4390
4391 VkResult radv_CreateSampler(
4392 VkDevice _device,
4393 const VkSamplerCreateInfo* pCreateInfo,
4394 const VkAllocationCallbacks* pAllocator,
4395 VkSampler* pSampler)
4396 {
4397 RADV_FROM_HANDLE(radv_device, device, _device);
4398 struct radv_sampler *sampler;
4399
4400 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4401
4402 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4403 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4404 if (!sampler)
4405 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4406
4407 radv_init_sampler(device, sampler, pCreateInfo);
4408 *pSampler = radv_sampler_to_handle(sampler);
4409
4410 return VK_SUCCESS;
4411 }
4412
4413 void radv_DestroySampler(
4414 VkDevice _device,
4415 VkSampler _sampler,
4416 const VkAllocationCallbacks* pAllocator)
4417 {
4418 RADV_FROM_HANDLE(radv_device, device, _device);
4419 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4420
4421 if (!sampler)
4422 return;
4423 vk_free2(&device->alloc, pAllocator, sampler);
4424 }
4425
4426 /* vk_icd.h does not declare this function, so we declare it here to
4427 * suppress Wmissing-prototypes.
4428 */
4429 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4430 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4431
4432 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4433 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4434 {
4435 /* For the full details on loader interface versioning, see
4436 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4437 * What follows is a condensed summary, to help you navigate the large and
4438 * confusing official doc.
4439 *
4440 * - Loader interface v0 is incompatible with later versions. We don't
4441 * support it.
4442 *
4443 * - In loader interface v1:
4444 * - The first ICD entrypoint called by the loader is
4445 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4446 * entrypoint.
4447 * - The ICD must statically expose no other Vulkan symbol unless it is
4448 * linked with -Bsymbolic.
4449 * - Each dispatchable Vulkan handle created by the ICD must be
4450 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4451 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4452 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4453 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4454 * such loader-managed surfaces.
4455 *
4456 * - Loader interface v2 differs from v1 in:
4457 * - The first ICD entrypoint called by the loader is
4458 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4459 * statically expose this entrypoint.
4460 *
4461 * - Loader interface v3 differs from v2 in:
4462 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4463 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4464 * because the loader no longer does so.
4465 */
4466 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4467 return VK_SUCCESS;
4468 }
4469
4470 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4471 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4472 int *pFD)
4473 {
4474 RADV_FROM_HANDLE(radv_device, device, _device);
4475 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4476
4477 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4478
4479 /* At the moment, we support only the below handle types. */
4480 assert(pGetFdInfo->handleType ==
4481 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4482 pGetFdInfo->handleType ==
4483 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4484
4485 bool ret = radv_get_memory_fd(device, memory, pFD);
4486 if (ret == false)
4487 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4488 return VK_SUCCESS;
4489 }
4490
4491 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4492 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4493 int fd,
4494 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4495 {
4496 RADV_FROM_HANDLE(radv_device, device, _device);
4497
4498 switch (handleType) {
4499 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4500 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4501 return VK_SUCCESS;
4502
4503 default:
4504 /* The valid usage section for this function says:
4505 *
4506 * "handleType must not be one of the handle types defined as
4507 * opaque."
4508 *
4509 * So opaque handle types fall into the default "unsupported" case.
4510 */
4511 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4512 }
4513 }
4514
4515 static VkResult radv_import_opaque_fd(struct radv_device *device,
4516 int fd,
4517 uint32_t *syncobj)
4518 {
4519 uint32_t syncobj_handle = 0;
4520 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4521 if (ret != 0)
4522 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4523
4524 if (*syncobj)
4525 device->ws->destroy_syncobj(device->ws, *syncobj);
4526
4527 *syncobj = syncobj_handle;
4528 close(fd);
4529
4530 return VK_SUCCESS;
4531 }
4532
4533 static VkResult radv_import_sync_fd(struct radv_device *device,
4534 int fd,
4535 uint32_t *syncobj)
4536 {
4537 /* If we create a syncobj we do it locally so that if we have an error, we don't
4538 * leave a syncobj in an undetermined state in the fence. */
4539 uint32_t syncobj_handle = *syncobj;
4540 if (!syncobj_handle) {
4541 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4542 if (ret) {
4543 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4544 }
4545 }
4546
4547 if (fd == -1) {
4548 device->ws->signal_syncobj(device->ws, syncobj_handle);
4549 } else {
4550 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4551 if (ret != 0)
4552 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4553 }
4554
4555 *syncobj = syncobj_handle;
4556 if (fd != -1)
4557 close(fd);
4558
4559 return VK_SUCCESS;
4560 }
4561
4562 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4563 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4564 {
4565 RADV_FROM_HANDLE(radv_device, device, _device);
4566 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4567 uint32_t *syncobj_dst = NULL;
4568
4569 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4570 syncobj_dst = &sem->temp_syncobj;
4571 } else {
4572 syncobj_dst = &sem->syncobj;
4573 }
4574
4575 switch(pImportSemaphoreFdInfo->handleType) {
4576 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4577 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4578 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4579 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4580 default:
4581 unreachable("Unhandled semaphore handle type");
4582 }
4583 }
4584
4585 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4586 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4587 int *pFd)
4588 {
4589 RADV_FROM_HANDLE(radv_device, device, _device);
4590 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4591 int ret;
4592 uint32_t syncobj_handle;
4593
4594 if (sem->temp_syncobj)
4595 syncobj_handle = sem->temp_syncobj;
4596 else
4597 syncobj_handle = sem->syncobj;
4598
4599 switch(pGetFdInfo->handleType) {
4600 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4601 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4602 break;
4603 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4604 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4605 if (!ret) {
4606 if (sem->temp_syncobj) {
4607 close (sem->temp_syncobj);
4608 sem->temp_syncobj = 0;
4609 } else {
4610 device->ws->reset_syncobj(device->ws, syncobj_handle);
4611 }
4612 }
4613 break;
4614 default:
4615 unreachable("Unhandled semaphore handle type");
4616 }
4617
4618 if (ret)
4619 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4620 return VK_SUCCESS;
4621 }
4622
4623 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4624 VkPhysicalDevice physicalDevice,
4625 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4626 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4627 {
4628 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4629
4630 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4631 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4632 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4633 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4634 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4635 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4636 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4637 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4638 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4639 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4640 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4641 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4642 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4643 } else {
4644 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4645 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4646 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4647 }
4648 }
4649
4650 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4651 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4652 {
4653 RADV_FROM_HANDLE(radv_device, device, _device);
4654 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4655 uint32_t *syncobj_dst = NULL;
4656
4657
4658 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4659 syncobj_dst = &fence->temp_syncobj;
4660 } else {
4661 syncobj_dst = &fence->syncobj;
4662 }
4663
4664 switch(pImportFenceFdInfo->handleType) {
4665 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4666 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4667 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4668 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4669 default:
4670 unreachable("Unhandled fence handle type");
4671 }
4672 }
4673
4674 VkResult radv_GetFenceFdKHR(VkDevice _device,
4675 const VkFenceGetFdInfoKHR *pGetFdInfo,
4676 int *pFd)
4677 {
4678 RADV_FROM_HANDLE(radv_device, device, _device);
4679 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4680 int ret;
4681 uint32_t syncobj_handle;
4682
4683 if (fence->temp_syncobj)
4684 syncobj_handle = fence->temp_syncobj;
4685 else
4686 syncobj_handle = fence->syncobj;
4687
4688 switch(pGetFdInfo->handleType) {
4689 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4690 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4691 break;
4692 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4693 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4694 if (!ret) {
4695 if (fence->temp_syncobj) {
4696 close (fence->temp_syncobj);
4697 fence->temp_syncobj = 0;
4698 } else {
4699 device->ws->reset_syncobj(device->ws, syncobj_handle);
4700 }
4701 }
4702 break;
4703 default:
4704 unreachable("Unhandled fence handle type");
4705 }
4706
4707 if (ret)
4708 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4709 return VK_SUCCESS;
4710 }
4711
4712 void radv_GetPhysicalDeviceExternalFenceProperties(
4713 VkPhysicalDevice physicalDevice,
4714 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4715 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4716 {
4717 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4718
4719 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4720 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4721 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4722 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4723 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4724 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4725 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4726 } else {
4727 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4728 pExternalFenceProperties->compatibleHandleTypes = 0;
4729 pExternalFenceProperties->externalFenceFeatures = 0;
4730 }
4731 }
4732
4733 VkResult
4734 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4735 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4736 const VkAllocationCallbacks* pAllocator,
4737 VkDebugReportCallbackEXT* pCallback)
4738 {
4739 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4740 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4741 pCreateInfo, pAllocator, &instance->alloc,
4742 pCallback);
4743 }
4744
4745 void
4746 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4747 VkDebugReportCallbackEXT _callback,
4748 const VkAllocationCallbacks* pAllocator)
4749 {
4750 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4751 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4752 _callback, pAllocator, &instance->alloc);
4753 }
4754
4755 void
4756 radv_DebugReportMessageEXT(VkInstance _instance,
4757 VkDebugReportFlagsEXT flags,
4758 VkDebugReportObjectTypeEXT objectType,
4759 uint64_t object,
4760 size_t location,
4761 int32_t messageCode,
4762 const char* pLayerPrefix,
4763 const char* pMessage)
4764 {
4765 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4766 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4767 object, location, messageCode, pLayerPrefix, pMessage);
4768 }
4769
4770 void
4771 radv_GetDeviceGroupPeerMemoryFeatures(
4772 VkDevice device,
4773 uint32_t heapIndex,
4774 uint32_t localDeviceIndex,
4775 uint32_t remoteDeviceIndex,
4776 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4777 {
4778 assert(localDeviceIndex == remoteDeviceIndex);
4779
4780 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4781 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4782 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4783 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4784 }