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radv: Add VK_KHR_bind_memory2 support.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 {
174 .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_BIND_MEMORY_2_EXTENSION_NAME,
179 .specVersion = 1,
180 },
181 };
182 static const VkExtensionProperties ext_sema_device_extensions[] = {
183 {
184 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
185 .specVersion = 1,
186 },
187 {
188 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
189 .specVersion = 1,
190 },
191 {
192 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
193 .specVersion = 1,
194 },
195 };
196
197 static VkResult
198 radv_extensions_register(struct radv_instance *instance,
199 struct radv_extensions *extensions,
200 const VkExtensionProperties *new_ext,
201 uint32_t num_ext)
202 {
203 size_t new_size;
204 VkExtensionProperties *new_ptr;
205
206 assert(new_ext && num_ext > 0);
207
208 if (!new_ext)
209 return VK_ERROR_INITIALIZATION_FAILED;
210
211 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
212 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
213 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
214
215 /* Old array continues to be valid, update nothing */
216 if (!new_ptr)
217 return VK_ERROR_OUT_OF_HOST_MEMORY;
218
219 memcpy(&new_ptr[extensions->num_ext], new_ext,
220 num_ext * sizeof(VkExtensionProperties));
221 extensions->ext_array = new_ptr;
222 extensions->num_ext += num_ext;
223
224 return VK_SUCCESS;
225 }
226
227 static void
228 radv_extensions_finish(struct radv_instance *instance,
229 struct radv_extensions *extensions)
230 {
231 assert(extensions);
232
233 if (!extensions)
234 radv_loge("Attemted to free invalid extension struct\n");
235
236 if (extensions->ext_array)
237 vk_free(&instance->alloc, extensions->ext_array);
238 }
239
240 static bool
241 is_extension_enabled(const VkExtensionProperties *extensions,
242 size_t num_ext,
243 const char *name)
244 {
245 assert(extensions && name);
246
247 for (uint32_t i = 0; i < num_ext; i++) {
248 if (strcmp(name, extensions[i].extensionName) == 0)
249 return true;
250 }
251
252 return false;
253 }
254
255 static const char *
256 get_chip_name(enum radeon_family family)
257 {
258 switch (family) {
259 case CHIP_TAHITI: return "AMD RADV TAHITI";
260 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
261 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
262 case CHIP_OLAND: return "AMD RADV OLAND";
263 case CHIP_HAINAN: return "AMD RADV HAINAN";
264 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
265 case CHIP_KAVERI: return "AMD RADV KAVERI";
266 case CHIP_KABINI: return "AMD RADV KABINI";
267 case CHIP_HAWAII: return "AMD RADV HAWAII";
268 case CHIP_MULLINS: return "AMD RADV MULLINS";
269 case CHIP_TONGA: return "AMD RADV TONGA";
270 case CHIP_ICELAND: return "AMD RADV ICELAND";
271 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
272 case CHIP_FIJI: return "AMD RADV FIJI";
273 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
274 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
275 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
276 case CHIP_STONEY: return "AMD RADV STONEY";
277 case CHIP_VEGA10: return "AMD RADV VEGA";
278 case CHIP_RAVEN: return "AMD RADV RAVEN";
279 default: return "AMD RADV unknown";
280 }
281 }
282
283 static VkResult
284 radv_physical_device_init(struct radv_physical_device *device,
285 struct radv_instance *instance,
286 drmDevicePtr drm_device)
287 {
288 const char *path = drm_device->nodes[DRM_NODE_RENDER];
289 VkResult result;
290 drmVersionPtr version;
291 int fd;
292
293 fd = open(path, O_RDWR | O_CLOEXEC);
294 if (fd < 0)
295 return VK_ERROR_INCOMPATIBLE_DRIVER;
296
297 version = drmGetVersion(fd);
298 if (!version) {
299 close(fd);
300 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
301 "failed to get version %s: %m", path);
302 }
303
304 if (strcmp(version->name, "amdgpu")) {
305 drmFreeVersion(version);
306 close(fd);
307 return VK_ERROR_INCOMPATIBLE_DRIVER;
308 }
309 drmFreeVersion(version);
310
311 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
312 device->instance = instance;
313 assert(strlen(path) < ARRAY_SIZE(device->path));
314 strncpy(device->path, path, ARRAY_SIZE(device->path));
315
316 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
317 instance->perftest_flags);
318 if (!device->ws) {
319 result = VK_ERROR_INCOMPATIBLE_DRIVER;
320 goto fail;
321 }
322
323 device->local_fd = fd;
324 device->ws->query_info(device->ws, &device->rad_info);
325 result = radv_init_wsi(device);
326 if (result != VK_SUCCESS) {
327 device->ws->destroy(device->ws);
328 goto fail;
329 }
330
331 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
332 radv_finish_wsi(device);
333 device->ws->destroy(device->ws);
334 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
335 "cannot generate UUID");
336 goto fail;
337 }
338
339 result = radv_extensions_register(instance,
340 &device->extensions,
341 common_device_extensions,
342 ARRAY_SIZE(common_device_extensions));
343 if (result != VK_SUCCESS)
344 goto fail;
345
346 if (device->rad_info.has_syncobj) {
347 result = radv_extensions_register(instance,
348 &device->extensions,
349 ext_sema_device_extensions,
350 ARRAY_SIZE(ext_sema_device_extensions));
351 if (result != VK_SUCCESS)
352 goto fail;
353 }
354
355 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
356 device->name = get_chip_name(device->rad_info.family);
357
358 radv_get_driver_uuid(&device->device_uuid);
359 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
360
361 if (device->rad_info.family == CHIP_STONEY ||
362 device->rad_info.chip_class >= GFX9) {
363 device->has_rbplus = true;
364 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
365 }
366
367 return VK_SUCCESS;
368
369 fail:
370 close(fd);
371 return result;
372 }
373
374 static void
375 radv_physical_device_finish(struct radv_physical_device *device)
376 {
377 radv_extensions_finish(device->instance, &device->extensions);
378 radv_finish_wsi(device);
379 device->ws->destroy(device->ws);
380 close(device->local_fd);
381 }
382
383 static void *
384 default_alloc_func(void *pUserData, size_t size, size_t align,
385 VkSystemAllocationScope allocationScope)
386 {
387 return malloc(size);
388 }
389
390 static void *
391 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
392 size_t align, VkSystemAllocationScope allocationScope)
393 {
394 return realloc(pOriginal, size);
395 }
396
397 static void
398 default_free_func(void *pUserData, void *pMemory)
399 {
400 free(pMemory);
401 }
402
403 static const VkAllocationCallbacks default_alloc = {
404 .pUserData = NULL,
405 .pfnAllocation = default_alloc_func,
406 .pfnReallocation = default_realloc_func,
407 .pfnFree = default_free_func,
408 };
409
410 static const struct debug_control radv_debug_options[] = {
411 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
412 {"nodcc", RADV_DEBUG_NO_DCC},
413 {"shaders", RADV_DEBUG_DUMP_SHADERS},
414 {"nocache", RADV_DEBUG_NO_CACHE},
415 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
416 {"nohiz", RADV_DEBUG_NO_HIZ},
417 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
418 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
419 {"allbos", RADV_DEBUG_ALL_BOS},
420 {"noibs", RADV_DEBUG_NO_IBS},
421 {"spirv", RADV_DEBUG_DUMP_SPIRV},
422 {"vmfaults", RADV_DEBUG_VM_FAULTS},
423 {"zerovram", RADV_DEBUG_ZERO_VRAM},
424 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
425 {NULL, 0}
426 };
427
428 const char *
429 radv_get_debug_option_name(int id)
430 {
431 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
432 return radv_debug_options[id].string;
433 }
434
435 static const struct debug_control radv_perftest_options[] = {
436 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
437 {"sisched", RADV_PERFTEST_SISCHED},
438 {NULL, 0}
439 };
440
441 const char *
442 radv_get_perftest_option_name(int id)
443 {
444 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
445 return radv_perftest_options[id].string;
446 }
447
448 VkResult radv_CreateInstance(
449 const VkInstanceCreateInfo* pCreateInfo,
450 const VkAllocationCallbacks* pAllocator,
451 VkInstance* pInstance)
452 {
453 struct radv_instance *instance;
454
455 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
456
457 uint32_t client_version;
458 if (pCreateInfo->pApplicationInfo &&
459 pCreateInfo->pApplicationInfo->apiVersion != 0) {
460 client_version = pCreateInfo->pApplicationInfo->apiVersion;
461 } else {
462 client_version = VK_MAKE_VERSION(1, 0, 0);
463 }
464
465 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
466 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
467 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
468 "Client requested version %d.%d.%d",
469 VK_VERSION_MAJOR(client_version),
470 VK_VERSION_MINOR(client_version),
471 VK_VERSION_PATCH(client_version));
472 }
473
474 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
475 if (!is_extension_enabled(instance_extensions,
476 ARRAY_SIZE(instance_extensions),
477 pCreateInfo->ppEnabledExtensionNames[i]))
478 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
479 }
480
481 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
482 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
483 if (!instance)
484 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
485
486 memset(instance, 0, sizeof(*instance));
487
488 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
489
490 if (pAllocator)
491 instance->alloc = *pAllocator;
492 else
493 instance->alloc = default_alloc;
494
495 instance->apiVersion = client_version;
496 instance->physicalDeviceCount = -1;
497
498 _mesa_locale_init();
499
500 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
501
502 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
503 radv_debug_options);
504
505 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
506 radv_perftest_options);
507
508 *pInstance = radv_instance_to_handle(instance);
509
510 return VK_SUCCESS;
511 }
512
513 void radv_DestroyInstance(
514 VkInstance _instance,
515 const VkAllocationCallbacks* pAllocator)
516 {
517 RADV_FROM_HANDLE(radv_instance, instance, _instance);
518
519 if (!instance)
520 return;
521
522 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
523 radv_physical_device_finish(instance->physicalDevices + i);
524 }
525
526 VG(VALGRIND_DESTROY_MEMPOOL(instance));
527
528 _mesa_locale_fini();
529
530 vk_free(&instance->alloc, instance);
531 }
532
533 static VkResult
534 radv_enumerate_devices(struct radv_instance *instance)
535 {
536 /* TODO: Check for more devices ? */
537 drmDevicePtr devices[8];
538 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
539 int max_devices;
540
541 instance->physicalDeviceCount = 0;
542
543 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
544 if (max_devices < 1)
545 return VK_ERROR_INCOMPATIBLE_DRIVER;
546
547 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
548 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
549 devices[i]->bustype == DRM_BUS_PCI &&
550 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
551
552 result = radv_physical_device_init(instance->physicalDevices +
553 instance->physicalDeviceCount,
554 instance,
555 devices[i]);
556 if (result == VK_SUCCESS)
557 ++instance->physicalDeviceCount;
558 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
559 break;
560 }
561 }
562 drmFreeDevices(devices, max_devices);
563
564 return result;
565 }
566
567 VkResult radv_EnumeratePhysicalDevices(
568 VkInstance _instance,
569 uint32_t* pPhysicalDeviceCount,
570 VkPhysicalDevice* pPhysicalDevices)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573 VkResult result;
574
575 if (instance->physicalDeviceCount < 0) {
576 result = radv_enumerate_devices(instance);
577 if (result != VK_SUCCESS &&
578 result != VK_ERROR_INCOMPATIBLE_DRIVER)
579 return result;
580 }
581
582 if (!pPhysicalDevices) {
583 *pPhysicalDeviceCount = instance->physicalDeviceCount;
584 } else {
585 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
586 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
587 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
588 }
589
590 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
591 : VK_SUCCESS;
592 }
593
594 void radv_GetPhysicalDeviceFeatures(
595 VkPhysicalDevice physicalDevice,
596 VkPhysicalDeviceFeatures* pFeatures)
597 {
598 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
599 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
600 memset(pFeatures, 0, sizeof(*pFeatures));
601
602 *pFeatures = (VkPhysicalDeviceFeatures) {
603 .robustBufferAccess = true,
604 .fullDrawIndexUint32 = true,
605 .imageCubeArray = true,
606 .independentBlend = true,
607 .geometryShader = !is_gfx9,
608 .tessellationShader = !is_gfx9,
609 .sampleRateShading = true,
610 .dualSrcBlend = true,
611 .logicOp = true,
612 .multiDrawIndirect = true,
613 .drawIndirectFirstInstance = true,
614 .depthClamp = true,
615 .depthBiasClamp = true,
616 .fillModeNonSolid = true,
617 .depthBounds = true,
618 .wideLines = true,
619 .largePoints = true,
620 .alphaToOne = true,
621 .multiViewport = true,
622 .samplerAnisotropy = true,
623 .textureCompressionETC2 = false,
624 .textureCompressionASTC_LDR = false,
625 .textureCompressionBC = true,
626 .occlusionQueryPrecise = true,
627 .pipelineStatisticsQuery = true,
628 .vertexPipelineStoresAndAtomics = true,
629 .fragmentStoresAndAtomics = true,
630 .shaderTessellationAndGeometryPointSize = true,
631 .shaderImageGatherExtended = true,
632 .shaderStorageImageExtendedFormats = true,
633 .shaderStorageImageMultisample = false,
634 .shaderUniformBufferArrayDynamicIndexing = true,
635 .shaderSampledImageArrayDynamicIndexing = true,
636 .shaderStorageBufferArrayDynamicIndexing = true,
637 .shaderStorageImageArrayDynamicIndexing = true,
638 .shaderStorageImageReadWithoutFormat = true,
639 .shaderStorageImageWriteWithoutFormat = true,
640 .shaderClipDistance = true,
641 .shaderCullDistance = true,
642 .shaderFloat64 = true,
643 .shaderInt64 = true,
644 .shaderInt16 = false,
645 .sparseBinding = true,
646 .variableMultisampleRate = true,
647 .inheritedQueries = true,
648 };
649 }
650
651 void radv_GetPhysicalDeviceFeatures2KHR(
652 VkPhysicalDevice physicalDevice,
653 VkPhysicalDeviceFeatures2KHR *pFeatures)
654 {
655 vk_foreach_struct(ext, pFeatures->pNext) {
656 switch (ext->sType) {
657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
658 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
659 features->variablePointersStorageBuffer = true;
660 features->variablePointers = false;
661 break;
662 }
663 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
664 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
665 features->multiview = true;
666 features->multiviewGeometryShader = true;
667 features->multiviewTessellationShader = true;
668 break;
669 }
670 default:
671 break;
672 }
673 }
674 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
675 }
676
677 void radv_GetPhysicalDeviceProperties(
678 VkPhysicalDevice physicalDevice,
679 VkPhysicalDeviceProperties* pProperties)
680 {
681 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
682 VkSampleCountFlags sample_counts = 0xf;
683
684 /* make sure that the entire descriptor set is addressable with a signed
685 * 32-bit int. So the sum of all limits scaled by descriptor size has to
686 * be at most 2 GiB. the combined image & samples object count as one of
687 * both. This limit is for the pipeline layout, not for the set layout, but
688 * there is no set limit, so we just set a pipeline limit. I don't think
689 * any app is going to hit this soon. */
690 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
691 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
692 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
693 32 /* sampler, largest when combined with image */ +
694 64 /* sampled image */ +
695 64 /* storage image */);
696
697 VkPhysicalDeviceLimits limits = {
698 .maxImageDimension1D = (1 << 14),
699 .maxImageDimension2D = (1 << 14),
700 .maxImageDimension3D = (1 << 11),
701 .maxImageDimensionCube = (1 << 14),
702 .maxImageArrayLayers = (1 << 11),
703 .maxTexelBufferElements = 128 * 1024 * 1024,
704 .maxUniformBufferRange = UINT32_MAX,
705 .maxStorageBufferRange = UINT32_MAX,
706 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
707 .maxMemoryAllocationCount = UINT32_MAX,
708 .maxSamplerAllocationCount = 64 * 1024,
709 .bufferImageGranularity = 64, /* A cache line */
710 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
711 .maxBoundDescriptorSets = MAX_SETS,
712 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
713 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
714 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
715 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
716 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
717 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
718 .maxPerStageResources = max_descriptor_set_size,
719 .maxDescriptorSetSamplers = max_descriptor_set_size,
720 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
721 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
722 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
723 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
724 .maxDescriptorSetSampledImages = max_descriptor_set_size,
725 .maxDescriptorSetStorageImages = max_descriptor_set_size,
726 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
727 .maxVertexInputAttributes = 32,
728 .maxVertexInputBindings = 32,
729 .maxVertexInputAttributeOffset = 2047,
730 .maxVertexInputBindingStride = 2048,
731 .maxVertexOutputComponents = 128,
732 .maxTessellationGenerationLevel = 64,
733 .maxTessellationPatchSize = 32,
734 .maxTessellationControlPerVertexInputComponents = 128,
735 .maxTessellationControlPerVertexOutputComponents = 128,
736 .maxTessellationControlPerPatchOutputComponents = 120,
737 .maxTessellationControlTotalOutputComponents = 4096,
738 .maxTessellationEvaluationInputComponents = 128,
739 .maxTessellationEvaluationOutputComponents = 128,
740 .maxGeometryShaderInvocations = 127,
741 .maxGeometryInputComponents = 64,
742 .maxGeometryOutputComponents = 128,
743 .maxGeometryOutputVertices = 256,
744 .maxGeometryTotalOutputComponents = 1024,
745 .maxFragmentInputComponents = 128,
746 .maxFragmentOutputAttachments = 8,
747 .maxFragmentDualSrcAttachments = 1,
748 .maxFragmentCombinedOutputResources = 8,
749 .maxComputeSharedMemorySize = 32768,
750 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
751 .maxComputeWorkGroupInvocations = 2048,
752 .maxComputeWorkGroupSize = {
753 2048,
754 2048,
755 2048
756 },
757 .subPixelPrecisionBits = 4 /* FIXME */,
758 .subTexelPrecisionBits = 4 /* FIXME */,
759 .mipmapPrecisionBits = 4 /* FIXME */,
760 .maxDrawIndexedIndexValue = UINT32_MAX,
761 .maxDrawIndirectCount = UINT32_MAX,
762 .maxSamplerLodBias = 16,
763 .maxSamplerAnisotropy = 16,
764 .maxViewports = MAX_VIEWPORTS,
765 .maxViewportDimensions = { (1 << 14), (1 << 14) },
766 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
767 .viewportSubPixelBits = 13, /* We take a float? */
768 .minMemoryMapAlignment = 4096, /* A page */
769 .minTexelBufferOffsetAlignment = 1,
770 .minUniformBufferOffsetAlignment = 4,
771 .minStorageBufferOffsetAlignment = 4,
772 .minTexelOffset = -32,
773 .maxTexelOffset = 31,
774 .minTexelGatherOffset = -32,
775 .maxTexelGatherOffset = 31,
776 .minInterpolationOffset = -2,
777 .maxInterpolationOffset = 2,
778 .subPixelInterpolationOffsetBits = 8,
779 .maxFramebufferWidth = (1 << 14),
780 .maxFramebufferHeight = (1 << 14),
781 .maxFramebufferLayers = (1 << 10),
782 .framebufferColorSampleCounts = sample_counts,
783 .framebufferDepthSampleCounts = sample_counts,
784 .framebufferStencilSampleCounts = sample_counts,
785 .framebufferNoAttachmentsSampleCounts = sample_counts,
786 .maxColorAttachments = MAX_RTS,
787 .sampledImageColorSampleCounts = sample_counts,
788 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
789 .sampledImageDepthSampleCounts = sample_counts,
790 .sampledImageStencilSampleCounts = sample_counts,
791 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
792 .maxSampleMaskWords = 1,
793 .timestampComputeAndGraphics = true,
794 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
795 .maxClipDistances = 8,
796 .maxCullDistances = 8,
797 .maxCombinedClipAndCullDistances = 8,
798 .discreteQueuePriorities = 1,
799 .pointSizeRange = { 0.125, 255.875 },
800 .lineWidthRange = { 0.0, 7.9921875 },
801 .pointSizeGranularity = (1.0 / 8.0),
802 .lineWidthGranularity = (1.0 / 128.0),
803 .strictLines = false, /* FINISHME */
804 .standardSampleLocations = true,
805 .optimalBufferCopyOffsetAlignment = 128,
806 .optimalBufferCopyRowPitchAlignment = 128,
807 .nonCoherentAtomSize = 64,
808 };
809
810 *pProperties = (VkPhysicalDeviceProperties) {
811 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
812 .driverVersion = vk_get_driver_version(),
813 .vendorID = 0x1002,
814 .deviceID = pdevice->rad_info.pci_id,
815 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
816 .limits = limits,
817 .sparseProperties = {0},
818 };
819
820 strcpy(pProperties->deviceName, pdevice->name);
821 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
822 }
823
824 void radv_GetPhysicalDeviceProperties2KHR(
825 VkPhysicalDevice physicalDevice,
826 VkPhysicalDeviceProperties2KHR *pProperties)
827 {
828 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
829 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
830
831 vk_foreach_struct(ext, pProperties->pNext) {
832 switch (ext->sType) {
833 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
834 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
835 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
836 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
840 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
841 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
842 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
843 properties->deviceLUIDValid = false;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
847 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
848 properties->maxMultiviewViewCount = MAX_VIEWS;
849 properties->maxMultiviewInstanceIndex = INT_MAX;
850 break;
851 }
852 default:
853 break;
854 }
855 }
856 }
857
858 static void radv_get_physical_device_queue_family_properties(
859 struct radv_physical_device* pdevice,
860 uint32_t* pCount,
861 VkQueueFamilyProperties** pQueueFamilyProperties)
862 {
863 int num_queue_families = 1;
864 int idx;
865 if (pdevice->rad_info.num_compute_rings > 0 &&
866 pdevice->rad_info.chip_class >= CIK &&
867 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
868 num_queue_families++;
869
870 if (pQueueFamilyProperties == NULL) {
871 *pCount = num_queue_families;
872 return;
873 }
874
875 if (!*pCount)
876 return;
877
878 idx = 0;
879 if (*pCount >= 1) {
880 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
881 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
882 VK_QUEUE_COMPUTE_BIT |
883 VK_QUEUE_TRANSFER_BIT |
884 VK_QUEUE_SPARSE_BINDING_BIT,
885 .queueCount = 1,
886 .timestampValidBits = 64,
887 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
888 };
889 idx++;
890 }
891
892 if (pdevice->rad_info.num_compute_rings > 0 &&
893 pdevice->rad_info.chip_class >= CIK &&
894 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
895 if (*pCount > idx) {
896 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
897 .queueFlags = VK_QUEUE_COMPUTE_BIT |
898 VK_QUEUE_TRANSFER_BIT |
899 VK_QUEUE_SPARSE_BINDING_BIT,
900 .queueCount = pdevice->rad_info.num_compute_rings,
901 .timestampValidBits = 64,
902 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
903 };
904 idx++;
905 }
906 }
907 *pCount = idx;
908 }
909
910 void radv_GetPhysicalDeviceQueueFamilyProperties(
911 VkPhysicalDevice physicalDevice,
912 uint32_t* pCount,
913 VkQueueFamilyProperties* pQueueFamilyProperties)
914 {
915 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
916 if (!pQueueFamilyProperties) {
917 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
918 return;
919 }
920 VkQueueFamilyProperties *properties[] = {
921 pQueueFamilyProperties + 0,
922 pQueueFamilyProperties + 1,
923 pQueueFamilyProperties + 2,
924 };
925 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
926 assert(*pCount <= 3);
927 }
928
929 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
930 VkPhysicalDevice physicalDevice,
931 uint32_t* pCount,
932 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
933 {
934 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
935 if (!pQueueFamilyProperties) {
936 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
937 return;
938 }
939 VkQueueFamilyProperties *properties[] = {
940 &pQueueFamilyProperties[0].queueFamilyProperties,
941 &pQueueFamilyProperties[1].queueFamilyProperties,
942 &pQueueFamilyProperties[2].queueFamilyProperties,
943 };
944 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
945 assert(*pCount <= 3);
946 }
947
948 void radv_GetPhysicalDeviceMemoryProperties(
949 VkPhysicalDevice physicalDevice,
950 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
951 {
952 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
953
954 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
955
956 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
957 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
958 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
959 .heapIndex = RADV_MEM_HEAP_VRAM,
960 };
961 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
962 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
963 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
964 .heapIndex = RADV_MEM_HEAP_GTT,
965 };
966 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
967 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
968 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
969 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
970 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
971 };
972 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
973 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
974 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
975 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
976 .heapIndex = RADV_MEM_HEAP_GTT,
977 };
978
979 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
980 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
981 physical_device->rad_info.vram_vis_size);
982
983 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
984 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
985 .size = physical_device->rad_info.vram_size -
986 visible_vram_size,
987 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
988 };
989 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
990 .size = visible_vram_size,
991 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
992 };
993 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
994 .size = physical_device->rad_info.gart_size,
995 .flags = 0,
996 };
997 }
998
999 void radv_GetPhysicalDeviceMemoryProperties2KHR(
1000 VkPhysicalDevice physicalDevice,
1001 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1002 {
1003 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1004 &pMemoryProperties->memoryProperties);
1005 }
1006
1007 static int
1008 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1009 int queue_family_index, int idx)
1010 {
1011 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1012 queue->device = device;
1013 queue->queue_family_index = queue_family_index;
1014 queue->queue_idx = idx;
1015
1016 queue->hw_ctx = device->ws->ctx_create(device->ws);
1017 if (!queue->hw_ctx)
1018 return VK_ERROR_OUT_OF_HOST_MEMORY;
1019
1020 return VK_SUCCESS;
1021 }
1022
1023 static void
1024 radv_queue_finish(struct radv_queue *queue)
1025 {
1026 if (queue->hw_ctx)
1027 queue->device->ws->ctx_destroy(queue->hw_ctx);
1028
1029 if (queue->initial_full_flush_preamble_cs)
1030 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1031 if (queue->initial_preamble_cs)
1032 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1033 if (queue->continue_preamble_cs)
1034 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1035 if (queue->descriptor_bo)
1036 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1037 if (queue->scratch_bo)
1038 queue->device->ws->buffer_destroy(queue->scratch_bo);
1039 if (queue->esgs_ring_bo)
1040 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1041 if (queue->gsvs_ring_bo)
1042 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1043 if (queue->tess_factor_ring_bo)
1044 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1045 if (queue->tess_offchip_ring_bo)
1046 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1047 if (queue->compute_scratch_bo)
1048 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1049 }
1050
1051 static void
1052 radv_device_init_gs_info(struct radv_device *device)
1053 {
1054 switch (device->physical_device->rad_info.family) {
1055 case CHIP_OLAND:
1056 case CHIP_HAINAN:
1057 case CHIP_KAVERI:
1058 case CHIP_KABINI:
1059 case CHIP_MULLINS:
1060 case CHIP_ICELAND:
1061 case CHIP_CARRIZO:
1062 case CHIP_STONEY:
1063 device->gs_table_depth = 16;
1064 return;
1065 case CHIP_TAHITI:
1066 case CHIP_PITCAIRN:
1067 case CHIP_VERDE:
1068 case CHIP_BONAIRE:
1069 case CHIP_HAWAII:
1070 case CHIP_TONGA:
1071 case CHIP_FIJI:
1072 case CHIP_POLARIS10:
1073 case CHIP_POLARIS11:
1074 case CHIP_POLARIS12:
1075 case CHIP_VEGA10:
1076 case CHIP_RAVEN:
1077 device->gs_table_depth = 32;
1078 return;
1079 default:
1080 unreachable("unknown GPU");
1081 }
1082 }
1083
1084 VkResult radv_CreateDevice(
1085 VkPhysicalDevice physicalDevice,
1086 const VkDeviceCreateInfo* pCreateInfo,
1087 const VkAllocationCallbacks* pAllocator,
1088 VkDevice* pDevice)
1089 {
1090 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1091 VkResult result;
1092 struct radv_device *device;
1093
1094 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1095 if (!is_extension_enabled(physical_device->extensions.ext_array,
1096 physical_device->extensions.num_ext,
1097 pCreateInfo->ppEnabledExtensionNames[i]))
1098 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1099 }
1100
1101 /* Check enabled features */
1102 if (pCreateInfo->pEnabledFeatures) {
1103 VkPhysicalDeviceFeatures supported_features;
1104 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1105 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1106 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1107 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1108 for (uint32_t i = 0; i < num_features; i++) {
1109 if (enabled_feature[i] && !supported_feature[i])
1110 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1111 }
1112 }
1113
1114 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1115 sizeof(*device), 8,
1116 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1117 if (!device)
1118 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1119
1120 memset(device, 0, sizeof(*device));
1121
1122 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1123 device->instance = physical_device->instance;
1124 device->physical_device = physical_device;
1125
1126 device->debug_flags = device->instance->debug_flags;
1127
1128 device->ws = physical_device->ws;
1129 if (pAllocator)
1130 device->alloc = *pAllocator;
1131 else
1132 device->alloc = physical_device->instance->alloc;
1133
1134 mtx_init(&device->shader_slab_mutex, mtx_plain);
1135 list_inithead(&device->shader_slabs);
1136
1137 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1138 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1139 uint32_t qfi = queue_create->queueFamilyIndex;
1140
1141 device->queues[qfi] = vk_alloc(&device->alloc,
1142 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1143 if (!device->queues[qfi]) {
1144 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1145 goto fail;
1146 }
1147
1148 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1149
1150 device->queue_count[qfi] = queue_create->queueCount;
1151
1152 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1153 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1154 if (result != VK_SUCCESS)
1155 goto fail;
1156 }
1157 }
1158
1159 #if HAVE_LLVM < 0x0400
1160 device->llvm_supports_spill = false;
1161 #else
1162 device->llvm_supports_spill = true;
1163 #endif
1164
1165 /* The maximum number of scratch waves. Scratch space isn't divided
1166 * evenly between CUs. The number is only a function of the number of CUs.
1167 * We can decrease the constant to decrease the scratch buffer size.
1168 *
1169 * sctx->scratch_waves must be >= the maximum posible size of
1170 * 1 threadgroup, so that the hw doesn't hang from being unable
1171 * to start any.
1172 *
1173 * The recommended value is 4 per CU at most. Higher numbers don't
1174 * bring much benefit, but they still occupy chip resources (think
1175 * async compute). I've seen ~2% performance difference between 4 and 32.
1176 */
1177 uint32_t max_threads_per_block = 2048;
1178 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1179 max_threads_per_block / 64);
1180
1181 radv_device_init_gs_info(device);
1182
1183 device->tess_offchip_block_dw_size =
1184 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1185 device->has_distributed_tess =
1186 device->physical_device->rad_info.chip_class >= VI &&
1187 device->physical_device->rad_info.max_se >= 2;
1188
1189 result = radv_device_init_meta(device);
1190 if (result != VK_SUCCESS)
1191 goto fail;
1192
1193 radv_device_init_msaa(device);
1194
1195 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1196 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1197 switch (family) {
1198 case RADV_QUEUE_GENERAL:
1199 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1200 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1201 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1202 break;
1203 case RADV_QUEUE_COMPUTE:
1204 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1205 radeon_emit(device->empty_cs[family], 0);
1206 break;
1207 }
1208 device->ws->cs_finalize(device->empty_cs[family]);
1209 }
1210
1211 if (getenv("RADV_TRACE_FILE")) {
1212 if (!radv_init_trace(device))
1213 goto fail;
1214 }
1215
1216 if (device->physical_device->rad_info.chip_class >= CIK)
1217 cik_create_gfx_config(device);
1218
1219 VkPipelineCacheCreateInfo ci;
1220 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1221 ci.pNext = NULL;
1222 ci.flags = 0;
1223 ci.pInitialData = NULL;
1224 ci.initialDataSize = 0;
1225 VkPipelineCache pc;
1226 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1227 &ci, NULL, &pc);
1228 if (result != VK_SUCCESS)
1229 goto fail;
1230
1231 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1232
1233 *pDevice = radv_device_to_handle(device);
1234 return VK_SUCCESS;
1235
1236 fail:
1237 if (device->trace_bo)
1238 device->ws->buffer_destroy(device->trace_bo);
1239
1240 if (device->gfx_init)
1241 device->ws->buffer_destroy(device->gfx_init);
1242
1243 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1244 for (unsigned q = 0; q < device->queue_count[i]; q++)
1245 radv_queue_finish(&device->queues[i][q]);
1246 if (device->queue_count[i])
1247 vk_free(&device->alloc, device->queues[i]);
1248 }
1249
1250 vk_free(&device->alloc, device);
1251 return result;
1252 }
1253
1254 void radv_DestroyDevice(
1255 VkDevice _device,
1256 const VkAllocationCallbacks* pAllocator)
1257 {
1258 RADV_FROM_HANDLE(radv_device, device, _device);
1259
1260 if (!device)
1261 return;
1262
1263 if (device->trace_bo)
1264 device->ws->buffer_destroy(device->trace_bo);
1265
1266 if (device->gfx_init)
1267 device->ws->buffer_destroy(device->gfx_init);
1268
1269 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1270 for (unsigned q = 0; q < device->queue_count[i]; q++)
1271 radv_queue_finish(&device->queues[i][q]);
1272 if (device->queue_count[i])
1273 vk_free(&device->alloc, device->queues[i]);
1274 if (device->empty_cs[i])
1275 device->ws->cs_destroy(device->empty_cs[i]);
1276 }
1277 radv_device_finish_meta(device);
1278
1279 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1280 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1281
1282 radv_destroy_shader_slabs(device);
1283
1284 vk_free(&device->alloc, device);
1285 }
1286
1287 VkResult radv_EnumerateInstanceExtensionProperties(
1288 const char* pLayerName,
1289 uint32_t* pPropertyCount,
1290 VkExtensionProperties* pProperties)
1291 {
1292 if (pProperties == NULL) {
1293 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1294 return VK_SUCCESS;
1295 }
1296
1297 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1298 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1299
1300 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1301 return VK_INCOMPLETE;
1302
1303 return VK_SUCCESS;
1304 }
1305
1306 VkResult radv_EnumerateDeviceExtensionProperties(
1307 VkPhysicalDevice physicalDevice,
1308 const char* pLayerName,
1309 uint32_t* pPropertyCount,
1310 VkExtensionProperties* pProperties)
1311 {
1312 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1313
1314 if (pProperties == NULL) {
1315 *pPropertyCount = pdevice->extensions.num_ext;
1316 return VK_SUCCESS;
1317 }
1318
1319 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1320 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1321
1322 if (*pPropertyCount < pdevice->extensions.num_ext)
1323 return VK_INCOMPLETE;
1324
1325 return VK_SUCCESS;
1326 }
1327
1328 VkResult radv_EnumerateInstanceLayerProperties(
1329 uint32_t* pPropertyCount,
1330 VkLayerProperties* pProperties)
1331 {
1332 if (pProperties == NULL) {
1333 *pPropertyCount = 0;
1334 return VK_SUCCESS;
1335 }
1336
1337 /* None supported at this time */
1338 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1339 }
1340
1341 VkResult radv_EnumerateDeviceLayerProperties(
1342 VkPhysicalDevice physicalDevice,
1343 uint32_t* pPropertyCount,
1344 VkLayerProperties* pProperties)
1345 {
1346 if (pProperties == NULL) {
1347 *pPropertyCount = 0;
1348 return VK_SUCCESS;
1349 }
1350
1351 /* None supported at this time */
1352 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1353 }
1354
1355 void radv_GetDeviceQueue(
1356 VkDevice _device,
1357 uint32_t queueFamilyIndex,
1358 uint32_t queueIndex,
1359 VkQueue* pQueue)
1360 {
1361 RADV_FROM_HANDLE(radv_device, device, _device);
1362
1363 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1364 }
1365
1366 static void
1367 fill_geom_tess_rings(struct radv_queue *queue,
1368 uint32_t *map,
1369 bool add_sample_positions,
1370 uint32_t esgs_ring_size,
1371 struct radeon_winsys_bo *esgs_ring_bo,
1372 uint32_t gsvs_ring_size,
1373 struct radeon_winsys_bo *gsvs_ring_bo,
1374 uint32_t tess_factor_ring_size,
1375 struct radeon_winsys_bo *tess_factor_ring_bo,
1376 uint32_t tess_offchip_ring_size,
1377 struct radeon_winsys_bo *tess_offchip_ring_bo)
1378 {
1379 uint64_t esgs_va = 0, gsvs_va = 0;
1380 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1381 uint32_t *desc = &map[4];
1382
1383 if (esgs_ring_bo)
1384 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1385 if (gsvs_ring_bo)
1386 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1387 if (tess_factor_ring_bo)
1388 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1389 if (tess_offchip_ring_bo)
1390 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1391
1392 /* stride 0, num records - size, add tid, swizzle, elsize4,
1393 index stride 64 */
1394 desc[0] = esgs_va;
1395 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1396 S_008F04_STRIDE(0) |
1397 S_008F04_SWIZZLE_ENABLE(true);
1398 desc[2] = esgs_ring_size;
1399 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1400 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1401 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1402 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1403 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1404 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1405 S_008F0C_ELEMENT_SIZE(1) |
1406 S_008F0C_INDEX_STRIDE(3) |
1407 S_008F0C_ADD_TID_ENABLE(true);
1408
1409 desc += 4;
1410 /* GS entry for ES->GS ring */
1411 /* stride 0, num records - size, elsize0,
1412 index stride 0 */
1413 desc[0] = esgs_va;
1414 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1415 S_008F04_STRIDE(0) |
1416 S_008F04_SWIZZLE_ENABLE(false);
1417 desc[2] = esgs_ring_size;
1418 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1419 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1420 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1421 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1422 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1423 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1424 S_008F0C_ELEMENT_SIZE(0) |
1425 S_008F0C_INDEX_STRIDE(0) |
1426 S_008F0C_ADD_TID_ENABLE(false);
1427
1428 desc += 4;
1429 /* VS entry for GS->VS ring */
1430 /* stride 0, num records - size, elsize0,
1431 index stride 0 */
1432 desc[0] = gsvs_va;
1433 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1434 S_008F04_STRIDE(0) |
1435 S_008F04_SWIZZLE_ENABLE(false);
1436 desc[2] = gsvs_ring_size;
1437 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1438 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1439 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1440 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1441 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1442 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1443 S_008F0C_ELEMENT_SIZE(0) |
1444 S_008F0C_INDEX_STRIDE(0) |
1445 S_008F0C_ADD_TID_ENABLE(false);
1446 desc += 4;
1447
1448 /* stride gsvs_itemsize, num records 64
1449 elsize 4, index stride 16 */
1450 /* shader will patch stride and desc[2] */
1451 desc[0] = gsvs_va;
1452 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1453 S_008F04_STRIDE(0) |
1454 S_008F04_SWIZZLE_ENABLE(true);
1455 desc[2] = 0;
1456 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1457 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1458 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1459 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1460 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1461 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1462 S_008F0C_ELEMENT_SIZE(1) |
1463 S_008F0C_INDEX_STRIDE(1) |
1464 S_008F0C_ADD_TID_ENABLE(true);
1465 desc += 4;
1466
1467 desc[0] = tess_factor_va;
1468 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1469 S_008F04_STRIDE(0) |
1470 S_008F04_SWIZZLE_ENABLE(false);
1471 desc[2] = tess_factor_ring_size;
1472 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1473 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1474 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1475 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1476 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1477 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1478 S_008F0C_ELEMENT_SIZE(0) |
1479 S_008F0C_INDEX_STRIDE(0) |
1480 S_008F0C_ADD_TID_ENABLE(false);
1481 desc += 4;
1482
1483 desc[0] = tess_offchip_va;
1484 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1485 S_008F04_STRIDE(0) |
1486 S_008F04_SWIZZLE_ENABLE(false);
1487 desc[2] = tess_offchip_ring_size;
1488 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1489 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1490 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1491 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1492 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1493 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1494 S_008F0C_ELEMENT_SIZE(0) |
1495 S_008F0C_INDEX_STRIDE(0) |
1496 S_008F0C_ADD_TID_ENABLE(false);
1497 desc += 4;
1498
1499 /* add sample positions after all rings */
1500 memcpy(desc, queue->device->sample_locations_1x, 8);
1501 desc += 2;
1502 memcpy(desc, queue->device->sample_locations_2x, 16);
1503 desc += 4;
1504 memcpy(desc, queue->device->sample_locations_4x, 32);
1505 desc += 8;
1506 memcpy(desc, queue->device->sample_locations_8x, 64);
1507 desc += 16;
1508 memcpy(desc, queue->device->sample_locations_16x, 128);
1509 }
1510
1511 static unsigned
1512 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1513 {
1514 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1515 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1516 device->physical_device->rad_info.family != CHIP_STONEY;
1517 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1518 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1519 device->physical_device->rad_info.max_se;
1520 unsigned offchip_granularity;
1521 unsigned hs_offchip_param;
1522 switch (device->tess_offchip_block_dw_size) {
1523 default:
1524 assert(0);
1525 /* fall through */
1526 case 8192:
1527 offchip_granularity = V_03093C_X_8K_DWORDS;
1528 break;
1529 case 4096:
1530 offchip_granularity = V_03093C_X_4K_DWORDS;
1531 break;
1532 }
1533
1534 switch (device->physical_device->rad_info.chip_class) {
1535 case SI:
1536 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1537 break;
1538 case CIK:
1539 case VI:
1540 case GFX9:
1541 default:
1542 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1543 break;
1544 }
1545
1546 *max_offchip_buffers_p = max_offchip_buffers;
1547 if (device->physical_device->rad_info.chip_class >= CIK) {
1548 if (device->physical_device->rad_info.chip_class >= VI)
1549 --max_offchip_buffers;
1550 hs_offchip_param =
1551 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1552 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1553 } else {
1554 hs_offchip_param =
1555 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1556 }
1557 return hs_offchip_param;
1558 }
1559
1560 static VkResult
1561 radv_get_preamble_cs(struct radv_queue *queue,
1562 uint32_t scratch_size,
1563 uint32_t compute_scratch_size,
1564 uint32_t esgs_ring_size,
1565 uint32_t gsvs_ring_size,
1566 bool needs_tess_rings,
1567 bool needs_sample_positions,
1568 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1569 struct radeon_winsys_cs **initial_preamble_cs,
1570 struct radeon_winsys_cs **continue_preamble_cs)
1571 {
1572 struct radeon_winsys_bo *scratch_bo = NULL;
1573 struct radeon_winsys_bo *descriptor_bo = NULL;
1574 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1575 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1576 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1577 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1578 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1579 struct radeon_winsys_cs *dest_cs[3] = {0};
1580 bool add_tess_rings = false, add_sample_positions = false;
1581 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1582 unsigned max_offchip_buffers;
1583 unsigned hs_offchip_param = 0;
1584 if (!queue->has_tess_rings) {
1585 if (needs_tess_rings)
1586 add_tess_rings = true;
1587 }
1588 if (!queue->has_sample_positions) {
1589 if (needs_sample_positions)
1590 add_sample_positions = true;
1591 }
1592 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1593 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1594 &max_offchip_buffers);
1595 tess_offchip_ring_size = max_offchip_buffers *
1596 queue->device->tess_offchip_block_dw_size * 4;
1597
1598 if (scratch_size <= queue->scratch_size &&
1599 compute_scratch_size <= queue->compute_scratch_size &&
1600 esgs_ring_size <= queue->esgs_ring_size &&
1601 gsvs_ring_size <= queue->gsvs_ring_size &&
1602 !add_tess_rings && !add_sample_positions &&
1603 queue->initial_preamble_cs) {
1604 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1605 *initial_preamble_cs = queue->initial_preamble_cs;
1606 *continue_preamble_cs = queue->continue_preamble_cs;
1607 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1608 *continue_preamble_cs = NULL;
1609 return VK_SUCCESS;
1610 }
1611
1612 if (scratch_size > queue->scratch_size) {
1613 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1614 scratch_size,
1615 4096,
1616 RADEON_DOMAIN_VRAM,
1617 RADEON_FLAG_NO_CPU_ACCESS);
1618 if (!scratch_bo)
1619 goto fail;
1620 } else
1621 scratch_bo = queue->scratch_bo;
1622
1623 if (compute_scratch_size > queue->compute_scratch_size) {
1624 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1625 compute_scratch_size,
1626 4096,
1627 RADEON_DOMAIN_VRAM,
1628 RADEON_FLAG_NO_CPU_ACCESS);
1629 if (!compute_scratch_bo)
1630 goto fail;
1631
1632 } else
1633 compute_scratch_bo = queue->compute_scratch_bo;
1634
1635 if (esgs_ring_size > queue->esgs_ring_size) {
1636 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1637 esgs_ring_size,
1638 4096,
1639 RADEON_DOMAIN_VRAM,
1640 RADEON_FLAG_NO_CPU_ACCESS);
1641 if (!esgs_ring_bo)
1642 goto fail;
1643 } else {
1644 esgs_ring_bo = queue->esgs_ring_bo;
1645 esgs_ring_size = queue->esgs_ring_size;
1646 }
1647
1648 if (gsvs_ring_size > queue->gsvs_ring_size) {
1649 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1650 gsvs_ring_size,
1651 4096,
1652 RADEON_DOMAIN_VRAM,
1653 RADEON_FLAG_NO_CPU_ACCESS);
1654 if (!gsvs_ring_bo)
1655 goto fail;
1656 } else {
1657 gsvs_ring_bo = queue->gsvs_ring_bo;
1658 gsvs_ring_size = queue->gsvs_ring_size;
1659 }
1660
1661 if (add_tess_rings) {
1662 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1663 tess_factor_ring_size,
1664 256,
1665 RADEON_DOMAIN_VRAM,
1666 RADEON_FLAG_NO_CPU_ACCESS);
1667 if (!tess_factor_ring_bo)
1668 goto fail;
1669 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1670 tess_offchip_ring_size,
1671 256,
1672 RADEON_DOMAIN_VRAM,
1673 RADEON_FLAG_NO_CPU_ACCESS);
1674 if (!tess_offchip_ring_bo)
1675 goto fail;
1676 } else {
1677 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1678 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1679 }
1680
1681 if (scratch_bo != queue->scratch_bo ||
1682 esgs_ring_bo != queue->esgs_ring_bo ||
1683 gsvs_ring_bo != queue->gsvs_ring_bo ||
1684 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1685 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1686 uint32_t size = 0;
1687 if (gsvs_ring_bo || esgs_ring_bo ||
1688 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1689 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1690 if (add_sample_positions)
1691 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1692 }
1693 else if (scratch_bo)
1694 size = 8; /* 2 dword */
1695
1696 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1697 size,
1698 4096,
1699 RADEON_DOMAIN_VRAM,
1700 RADEON_FLAG_CPU_ACCESS);
1701 if (!descriptor_bo)
1702 goto fail;
1703 } else
1704 descriptor_bo = queue->descriptor_bo;
1705
1706 for(int i = 0; i < 3; ++i) {
1707 struct radeon_winsys_cs *cs = NULL;
1708 cs = queue->device->ws->cs_create(queue->device->ws,
1709 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1710 if (!cs)
1711 goto fail;
1712
1713 dest_cs[i] = cs;
1714
1715 if (scratch_bo)
1716 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1717
1718 if (esgs_ring_bo)
1719 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1720
1721 if (gsvs_ring_bo)
1722 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1723
1724 if (tess_factor_ring_bo)
1725 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1726
1727 if (tess_offchip_ring_bo)
1728 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1729
1730 if (descriptor_bo)
1731 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1732
1733 if (descriptor_bo != queue->descriptor_bo) {
1734 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1735
1736 if (scratch_bo) {
1737 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1738 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1739 S_008F04_SWIZZLE_ENABLE(1);
1740 map[0] = scratch_va;
1741 map[1] = rsrc1;
1742 }
1743
1744 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1745 add_sample_positions)
1746 fill_geom_tess_rings(queue, map, add_sample_positions,
1747 esgs_ring_size, esgs_ring_bo,
1748 gsvs_ring_size, gsvs_ring_bo,
1749 tess_factor_ring_size, tess_factor_ring_bo,
1750 tess_offchip_ring_size, tess_offchip_ring_bo);
1751
1752 queue->device->ws->buffer_unmap(descriptor_bo);
1753 }
1754
1755 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1756 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1757 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1758 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1759 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1760 }
1761
1762 if (esgs_ring_bo || gsvs_ring_bo) {
1763 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1764 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1765 radeon_emit(cs, esgs_ring_size >> 8);
1766 radeon_emit(cs, gsvs_ring_size >> 8);
1767 } else {
1768 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1769 radeon_emit(cs, esgs_ring_size >> 8);
1770 radeon_emit(cs, gsvs_ring_size >> 8);
1771 }
1772 }
1773
1774 if (tess_factor_ring_bo) {
1775 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1776 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1777 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1778 S_030938_SIZE(tess_factor_ring_size / 4));
1779 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1780 tf_va >> 8);
1781 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1782 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1783 tf_va >> 40);
1784 }
1785 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1786 } else {
1787 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1788 S_008988_SIZE(tess_factor_ring_size / 4));
1789 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1790 tf_va >> 8);
1791 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1792 hs_offchip_param);
1793 }
1794 }
1795
1796 if (descriptor_bo) {
1797 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1798 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1799 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1800 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1801 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1802 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1803
1804 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1805
1806 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1807 radeon_set_sh_reg_seq(cs, regs[i], 2);
1808 radeon_emit(cs, va);
1809 radeon_emit(cs, va >> 32);
1810 }
1811 }
1812
1813 if (compute_scratch_bo) {
1814 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1815 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1816 S_008F04_SWIZZLE_ENABLE(1);
1817
1818 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1819
1820 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1821 radeon_emit(cs, scratch_va);
1822 radeon_emit(cs, rsrc1);
1823 }
1824
1825 if (i == 0) {
1826 si_cs_emit_cache_flush(cs,
1827 false,
1828 queue->device->physical_device->rad_info.chip_class,
1829 NULL, 0,
1830 queue->queue_family_index == RING_COMPUTE &&
1831 queue->device->physical_device->rad_info.chip_class >= CIK,
1832 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1833 RADV_CMD_FLAG_INV_ICACHE |
1834 RADV_CMD_FLAG_INV_SMEM_L1 |
1835 RADV_CMD_FLAG_INV_VMEM_L1 |
1836 RADV_CMD_FLAG_INV_GLOBAL_L2);
1837 } else if (i == 1) {
1838 si_cs_emit_cache_flush(cs,
1839 false,
1840 queue->device->physical_device->rad_info.chip_class,
1841 NULL, 0,
1842 queue->queue_family_index == RING_COMPUTE &&
1843 queue->device->physical_device->rad_info.chip_class >= CIK,
1844 RADV_CMD_FLAG_INV_ICACHE |
1845 RADV_CMD_FLAG_INV_SMEM_L1 |
1846 RADV_CMD_FLAG_INV_VMEM_L1 |
1847 RADV_CMD_FLAG_INV_GLOBAL_L2);
1848 }
1849
1850 if (!queue->device->ws->cs_finalize(cs))
1851 goto fail;
1852 }
1853
1854 if (queue->initial_full_flush_preamble_cs)
1855 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1856
1857 if (queue->initial_preamble_cs)
1858 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1859
1860 if (queue->continue_preamble_cs)
1861 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1862
1863 queue->initial_full_flush_preamble_cs = dest_cs[0];
1864 queue->initial_preamble_cs = dest_cs[1];
1865 queue->continue_preamble_cs = dest_cs[2];
1866
1867 if (scratch_bo != queue->scratch_bo) {
1868 if (queue->scratch_bo)
1869 queue->device->ws->buffer_destroy(queue->scratch_bo);
1870 queue->scratch_bo = scratch_bo;
1871 queue->scratch_size = scratch_size;
1872 }
1873
1874 if (compute_scratch_bo != queue->compute_scratch_bo) {
1875 if (queue->compute_scratch_bo)
1876 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1877 queue->compute_scratch_bo = compute_scratch_bo;
1878 queue->compute_scratch_size = compute_scratch_size;
1879 }
1880
1881 if (esgs_ring_bo != queue->esgs_ring_bo) {
1882 if (queue->esgs_ring_bo)
1883 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1884 queue->esgs_ring_bo = esgs_ring_bo;
1885 queue->esgs_ring_size = esgs_ring_size;
1886 }
1887
1888 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1889 if (queue->gsvs_ring_bo)
1890 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1891 queue->gsvs_ring_bo = gsvs_ring_bo;
1892 queue->gsvs_ring_size = gsvs_ring_size;
1893 }
1894
1895 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1896 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1897 }
1898
1899 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1900 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1901 queue->has_tess_rings = true;
1902 }
1903
1904 if (descriptor_bo != queue->descriptor_bo) {
1905 if (queue->descriptor_bo)
1906 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1907
1908 queue->descriptor_bo = descriptor_bo;
1909 }
1910
1911 if (add_sample_positions)
1912 queue->has_sample_positions = true;
1913
1914 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1915 *initial_preamble_cs = queue->initial_preamble_cs;
1916 *continue_preamble_cs = queue->continue_preamble_cs;
1917 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1918 *continue_preamble_cs = NULL;
1919 return VK_SUCCESS;
1920 fail:
1921 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1922 if (dest_cs[i])
1923 queue->device->ws->cs_destroy(dest_cs[i]);
1924 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1925 queue->device->ws->buffer_destroy(descriptor_bo);
1926 if (scratch_bo && scratch_bo != queue->scratch_bo)
1927 queue->device->ws->buffer_destroy(scratch_bo);
1928 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1929 queue->device->ws->buffer_destroy(compute_scratch_bo);
1930 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1931 queue->device->ws->buffer_destroy(esgs_ring_bo);
1932 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1933 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1934 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1935 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1936 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1937 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1938 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1939 }
1940
1941 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1942 int num_sems,
1943 const VkSemaphore *sems,
1944 bool reset_temp)
1945 {
1946 int syncobj_idx = 0, sem_idx = 0;
1947
1948 if (num_sems == 0)
1949 return VK_SUCCESS;
1950 for (uint32_t i = 0; i < num_sems; i++) {
1951 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1952
1953 if (sem->temp_syncobj || sem->syncobj)
1954 counts->syncobj_count++;
1955 else
1956 counts->sem_count++;
1957 }
1958
1959 if (counts->syncobj_count) {
1960 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1961 if (!counts->syncobj)
1962 return VK_ERROR_OUT_OF_HOST_MEMORY;
1963 }
1964
1965 if (counts->sem_count) {
1966 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1967 if (!counts->sem) {
1968 free(counts->syncobj);
1969 return VK_ERROR_OUT_OF_HOST_MEMORY;
1970 }
1971 }
1972
1973 for (uint32_t i = 0; i < num_sems; i++) {
1974 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1975
1976 if (sem->temp_syncobj) {
1977 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1978 if (reset_temp) {
1979 /* after we wait on a temp import - drop it */
1980 sem->temp_syncobj = 0;
1981 }
1982 }
1983 else if (sem->syncobj)
1984 counts->syncobj[syncobj_idx++] = sem->syncobj;
1985 else {
1986 assert(sem->sem);
1987 counts->sem[sem_idx++] = sem->sem;
1988 }
1989 }
1990
1991 return VK_SUCCESS;
1992 }
1993
1994 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1995 {
1996 free(sem_info->wait.syncobj);
1997 free(sem_info->wait.sem);
1998 free(sem_info->signal.syncobj);
1999 free(sem_info->signal.sem);
2000 }
2001
2002 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2003 int num_wait_sems,
2004 const VkSemaphore *wait_sems,
2005 int num_signal_sems,
2006 const VkSemaphore *signal_sems)
2007 {
2008 VkResult ret;
2009 memset(sem_info, 0, sizeof(*sem_info));
2010
2011 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2012 if (ret)
2013 return ret;
2014 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2015 if (ret)
2016 radv_free_sem_info(sem_info);
2017
2018 /* caller can override these */
2019 sem_info->cs_emit_wait = true;
2020 sem_info->cs_emit_signal = true;
2021 return ret;
2022 }
2023
2024 VkResult radv_QueueSubmit(
2025 VkQueue _queue,
2026 uint32_t submitCount,
2027 const VkSubmitInfo* pSubmits,
2028 VkFence _fence)
2029 {
2030 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2031 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2032 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2033 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2034 int ret;
2035 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2036 uint32_t scratch_size = 0;
2037 uint32_t compute_scratch_size = 0;
2038 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2039 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2040 VkResult result;
2041 bool fence_emitted = false;
2042 bool tess_rings_needed = false;
2043 bool sample_positions_needed = false;
2044
2045 /* Do this first so failing to allocate scratch buffers can't result in
2046 * partially executed submissions. */
2047 for (uint32_t i = 0; i < submitCount; i++) {
2048 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2049 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2050 pSubmits[i].pCommandBuffers[j]);
2051
2052 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2053 compute_scratch_size = MAX2(compute_scratch_size,
2054 cmd_buffer->compute_scratch_size_needed);
2055 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2056 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2057 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2058 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2059 }
2060 }
2061
2062 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2063 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2064 sample_positions_needed, &initial_flush_preamble_cs,
2065 &initial_preamble_cs, &continue_preamble_cs);
2066 if (result != VK_SUCCESS)
2067 return result;
2068
2069 for (uint32_t i = 0; i < submitCount; i++) {
2070 struct radeon_winsys_cs **cs_array;
2071 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2072 bool can_patch = true;
2073 uint32_t advance;
2074 struct radv_winsys_sem_info sem_info;
2075
2076 result = radv_alloc_sem_info(&sem_info,
2077 pSubmits[i].waitSemaphoreCount,
2078 pSubmits[i].pWaitSemaphores,
2079 pSubmits[i].signalSemaphoreCount,
2080 pSubmits[i].pSignalSemaphores);
2081 if (result != VK_SUCCESS)
2082 return result;
2083
2084 if (!pSubmits[i].commandBufferCount) {
2085 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2086 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2087 &queue->device->empty_cs[queue->queue_family_index],
2088 1, NULL, NULL,
2089 &sem_info,
2090 false, base_fence);
2091 if (ret) {
2092 radv_loge("failed to submit CS %d\n", i);
2093 abort();
2094 }
2095 fence_emitted = true;
2096 }
2097 radv_free_sem_info(&sem_info);
2098 continue;
2099 }
2100
2101 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2102 (pSubmits[i].commandBufferCount));
2103
2104 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2105 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2106 pSubmits[i].pCommandBuffers[j]);
2107 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2108
2109 cs_array[j] = cmd_buffer->cs;
2110 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2111 can_patch = false;
2112 }
2113
2114 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2115 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2116 advance = MIN2(max_cs_submission,
2117 pSubmits[i].commandBufferCount - j);
2118
2119 if (queue->device->trace_bo)
2120 *queue->device->trace_id_ptr = 0;
2121
2122 sem_info.cs_emit_wait = j == 0;
2123 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2124
2125 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2126 advance, initial_preamble, continue_preamble_cs,
2127 &sem_info,
2128 can_patch, base_fence);
2129
2130 if (ret) {
2131 radv_loge("failed to submit CS %d\n", i);
2132 abort();
2133 }
2134 fence_emitted = true;
2135 if (queue->device->trace_bo) {
2136 radv_check_gpu_hangs(queue, cs_array[j]);
2137 }
2138 }
2139
2140 radv_free_sem_info(&sem_info);
2141 free(cs_array);
2142 }
2143
2144 if (fence) {
2145 if (!fence_emitted) {
2146 struct radv_winsys_sem_info sem_info = {0};
2147 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2148 &queue->device->empty_cs[queue->queue_family_index],
2149 1, NULL, NULL, &sem_info,
2150 false, base_fence);
2151 }
2152 fence->submitted = true;
2153 }
2154
2155 return VK_SUCCESS;
2156 }
2157
2158 VkResult radv_QueueWaitIdle(
2159 VkQueue _queue)
2160 {
2161 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2162
2163 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2164 radv_queue_family_to_ring(queue->queue_family_index),
2165 queue->queue_idx);
2166 return VK_SUCCESS;
2167 }
2168
2169 VkResult radv_DeviceWaitIdle(
2170 VkDevice _device)
2171 {
2172 RADV_FROM_HANDLE(radv_device, device, _device);
2173
2174 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2175 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2176 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2177 }
2178 }
2179 return VK_SUCCESS;
2180 }
2181
2182 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2183 VkInstance instance,
2184 const char* pName)
2185 {
2186 return radv_lookup_entrypoint(pName);
2187 }
2188
2189 /* The loader wants us to expose a second GetInstanceProcAddr function
2190 * to work around certain LD_PRELOAD issues seen in apps.
2191 */
2192 PUBLIC
2193 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2194 VkInstance instance,
2195 const char* pName);
2196
2197 PUBLIC
2198 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2199 VkInstance instance,
2200 const char* pName)
2201 {
2202 return radv_GetInstanceProcAddr(instance, pName);
2203 }
2204
2205 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2206 VkDevice device,
2207 const char* pName)
2208 {
2209 return radv_lookup_entrypoint(pName);
2210 }
2211
2212 bool radv_get_memory_fd(struct radv_device *device,
2213 struct radv_device_memory *memory,
2214 int *pFD)
2215 {
2216 struct radeon_bo_metadata metadata;
2217
2218 if (memory->image) {
2219 radv_init_metadata(device, memory->image, &metadata);
2220 device->ws->buffer_set_metadata(memory->bo, &metadata);
2221 }
2222
2223 return device->ws->buffer_get_fd(device->ws, memory->bo,
2224 pFD);
2225 }
2226
2227 VkResult radv_AllocateMemory(
2228 VkDevice _device,
2229 const VkMemoryAllocateInfo* pAllocateInfo,
2230 const VkAllocationCallbacks* pAllocator,
2231 VkDeviceMemory* pMem)
2232 {
2233 RADV_FROM_HANDLE(radv_device, device, _device);
2234 struct radv_device_memory *mem;
2235 VkResult result;
2236 enum radeon_bo_domain domain;
2237 uint32_t flags = 0;
2238
2239 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2240
2241 if (pAllocateInfo->allocationSize == 0) {
2242 /* Apparently, this is allowed */
2243 *pMem = VK_NULL_HANDLE;
2244 return VK_SUCCESS;
2245 }
2246
2247 const VkImportMemoryFdInfoKHR *import_info =
2248 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2249 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2250 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2251
2252 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2253 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2254 if (mem == NULL)
2255 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2256
2257 if (dedicate_info) {
2258 mem->image = radv_image_from_handle(dedicate_info->image);
2259 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2260 } else {
2261 mem->image = NULL;
2262 mem->buffer = NULL;
2263 }
2264
2265 if (import_info) {
2266 assert(import_info->handleType ==
2267 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2268 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2269 NULL, NULL);
2270 if (!mem->bo) {
2271 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2272 goto fail;
2273 } else {
2274 close(import_info->fd);
2275 goto out_success;
2276 }
2277 }
2278
2279 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2280 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2281 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2282 domain = RADEON_DOMAIN_GTT;
2283 else
2284 domain = RADEON_DOMAIN_VRAM;
2285
2286 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2287 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2288 else
2289 flags |= RADEON_FLAG_CPU_ACCESS;
2290
2291 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2292 flags |= RADEON_FLAG_GTT_WC;
2293
2294 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2295 domain, flags);
2296
2297 if (!mem->bo) {
2298 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2299 goto fail;
2300 }
2301 mem->type_index = pAllocateInfo->memoryTypeIndex;
2302 out_success:
2303 *pMem = radv_device_memory_to_handle(mem);
2304
2305 return VK_SUCCESS;
2306
2307 fail:
2308 vk_free2(&device->alloc, pAllocator, mem);
2309
2310 return result;
2311 }
2312
2313 void radv_FreeMemory(
2314 VkDevice _device,
2315 VkDeviceMemory _mem,
2316 const VkAllocationCallbacks* pAllocator)
2317 {
2318 RADV_FROM_HANDLE(radv_device, device, _device);
2319 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2320
2321 if (mem == NULL)
2322 return;
2323
2324 device->ws->buffer_destroy(mem->bo);
2325 mem->bo = NULL;
2326
2327 vk_free2(&device->alloc, pAllocator, mem);
2328 }
2329
2330 VkResult radv_MapMemory(
2331 VkDevice _device,
2332 VkDeviceMemory _memory,
2333 VkDeviceSize offset,
2334 VkDeviceSize size,
2335 VkMemoryMapFlags flags,
2336 void** ppData)
2337 {
2338 RADV_FROM_HANDLE(radv_device, device, _device);
2339 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2340
2341 if (mem == NULL) {
2342 *ppData = NULL;
2343 return VK_SUCCESS;
2344 }
2345
2346 *ppData = device->ws->buffer_map(mem->bo);
2347 if (*ppData) {
2348 *ppData += offset;
2349 return VK_SUCCESS;
2350 }
2351
2352 return VK_ERROR_MEMORY_MAP_FAILED;
2353 }
2354
2355 void radv_UnmapMemory(
2356 VkDevice _device,
2357 VkDeviceMemory _memory)
2358 {
2359 RADV_FROM_HANDLE(radv_device, device, _device);
2360 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2361
2362 if (mem == NULL)
2363 return;
2364
2365 device->ws->buffer_unmap(mem->bo);
2366 }
2367
2368 VkResult radv_FlushMappedMemoryRanges(
2369 VkDevice _device,
2370 uint32_t memoryRangeCount,
2371 const VkMappedMemoryRange* pMemoryRanges)
2372 {
2373 return VK_SUCCESS;
2374 }
2375
2376 VkResult radv_InvalidateMappedMemoryRanges(
2377 VkDevice _device,
2378 uint32_t memoryRangeCount,
2379 const VkMappedMemoryRange* pMemoryRanges)
2380 {
2381 return VK_SUCCESS;
2382 }
2383
2384 void radv_GetBufferMemoryRequirements(
2385 VkDevice device,
2386 VkBuffer _buffer,
2387 VkMemoryRequirements* pMemoryRequirements)
2388 {
2389 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2390
2391 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2392
2393 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2394 pMemoryRequirements->alignment = 4096;
2395 else
2396 pMemoryRequirements->alignment = 16;
2397
2398 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2399 }
2400
2401 void radv_GetBufferMemoryRequirements2KHR(
2402 VkDevice device,
2403 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2404 VkMemoryRequirements2KHR* pMemoryRequirements)
2405 {
2406 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2407 &pMemoryRequirements->memoryRequirements);
2408
2409 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2410 switch (ext->sType) {
2411 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2412 VkMemoryDedicatedRequirementsKHR *req =
2413 (VkMemoryDedicatedRequirementsKHR *) ext;
2414 req->requiresDedicatedAllocation = false;
2415 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2416 break;
2417 }
2418 default:
2419 break;
2420 }
2421 }
2422 }
2423
2424 void radv_GetImageMemoryRequirements(
2425 VkDevice device,
2426 VkImage _image,
2427 VkMemoryRequirements* pMemoryRequirements)
2428 {
2429 RADV_FROM_HANDLE(radv_image, image, _image);
2430
2431 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2432
2433 pMemoryRequirements->size = image->size;
2434 pMemoryRequirements->alignment = image->alignment;
2435 }
2436
2437 void radv_GetImageMemoryRequirements2KHR(
2438 VkDevice device,
2439 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2440 VkMemoryRequirements2KHR* pMemoryRequirements)
2441 {
2442 radv_GetImageMemoryRequirements(device, pInfo->image,
2443 &pMemoryRequirements->memoryRequirements);
2444
2445 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2446
2447 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2448 switch (ext->sType) {
2449 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2450 VkMemoryDedicatedRequirementsKHR *req =
2451 (VkMemoryDedicatedRequirementsKHR *) ext;
2452 req->requiresDedicatedAllocation = image->shareable;
2453 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2454 break;
2455 }
2456 default:
2457 break;
2458 }
2459 }
2460 }
2461
2462 void radv_GetImageSparseMemoryRequirements(
2463 VkDevice device,
2464 VkImage image,
2465 uint32_t* pSparseMemoryRequirementCount,
2466 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2467 {
2468 stub();
2469 }
2470
2471 void radv_GetImageSparseMemoryRequirements2KHR(
2472 VkDevice device,
2473 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2474 uint32_t* pSparseMemoryRequirementCount,
2475 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2476 {
2477 stub();
2478 }
2479
2480 void radv_GetDeviceMemoryCommitment(
2481 VkDevice device,
2482 VkDeviceMemory memory,
2483 VkDeviceSize* pCommittedMemoryInBytes)
2484 {
2485 *pCommittedMemoryInBytes = 0;
2486 }
2487
2488 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2489 uint32_t bindInfoCount,
2490 const VkBindBufferMemoryInfoKHR *pBindInfos)
2491 {
2492 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2493 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2494 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2495
2496 if (mem) {
2497 buffer->bo = mem->bo;
2498 buffer->offset = pBindInfos[i].memoryOffset;
2499 } else {
2500 buffer->bo = NULL;
2501 }
2502 }
2503 return VK_SUCCESS;
2504 }
2505
2506 VkResult radv_BindBufferMemory(
2507 VkDevice device,
2508 VkBuffer buffer,
2509 VkDeviceMemory memory,
2510 VkDeviceSize memoryOffset)
2511 {
2512 const VkBindBufferMemoryInfoKHR info = {
2513 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2514 .buffer = buffer,
2515 .memory = memory,
2516 .memoryOffset = memoryOffset
2517 };
2518
2519 return radv_BindBufferMemory2KHR(device, 1, &info);
2520 }
2521
2522 VkResult radv_BindImageMemory2KHR(VkDevice device,
2523 uint32_t bindInfoCount,
2524 const VkBindImageMemoryInfoKHR *pBindInfos)
2525 {
2526 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2527 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2528 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2529
2530 if (mem) {
2531 image->bo = mem->bo;
2532 image->offset = pBindInfos[i].memoryOffset;
2533 } else {
2534 image->bo = NULL;
2535 image->offset = 0;
2536 }
2537 }
2538 return VK_SUCCESS;
2539 }
2540
2541
2542 VkResult radv_BindImageMemory(
2543 VkDevice device,
2544 VkImage image,
2545 VkDeviceMemory memory,
2546 VkDeviceSize memoryOffset)
2547 {
2548 const VkBindImageMemoryInfoKHR info = {
2549 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2550 .image = image,
2551 .memory = memory,
2552 .memoryOffset = memoryOffset
2553 };
2554
2555 return radv_BindImageMemory2KHR(device, 1, &info);
2556 }
2557
2558
2559 static void
2560 radv_sparse_buffer_bind_memory(struct radv_device *device,
2561 const VkSparseBufferMemoryBindInfo *bind)
2562 {
2563 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2564
2565 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2566 struct radv_device_memory *mem = NULL;
2567
2568 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2569 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2570
2571 device->ws->buffer_virtual_bind(buffer->bo,
2572 bind->pBinds[i].resourceOffset,
2573 bind->pBinds[i].size,
2574 mem ? mem->bo : NULL,
2575 bind->pBinds[i].memoryOffset);
2576 }
2577 }
2578
2579 static void
2580 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2581 const VkSparseImageOpaqueMemoryBindInfo *bind)
2582 {
2583 RADV_FROM_HANDLE(radv_image, image, bind->image);
2584
2585 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2586 struct radv_device_memory *mem = NULL;
2587
2588 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2589 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2590
2591 device->ws->buffer_virtual_bind(image->bo,
2592 bind->pBinds[i].resourceOffset,
2593 bind->pBinds[i].size,
2594 mem ? mem->bo : NULL,
2595 bind->pBinds[i].memoryOffset);
2596 }
2597 }
2598
2599 VkResult radv_QueueBindSparse(
2600 VkQueue _queue,
2601 uint32_t bindInfoCount,
2602 const VkBindSparseInfo* pBindInfo,
2603 VkFence _fence)
2604 {
2605 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2606 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2607 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2608 bool fence_emitted = false;
2609
2610 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2611 struct radv_winsys_sem_info sem_info;
2612 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2613 radv_sparse_buffer_bind_memory(queue->device,
2614 pBindInfo[i].pBufferBinds + j);
2615 }
2616
2617 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2618 radv_sparse_image_opaque_bind_memory(queue->device,
2619 pBindInfo[i].pImageOpaqueBinds + j);
2620 }
2621
2622 VkResult result;
2623 result = radv_alloc_sem_info(&sem_info,
2624 pBindInfo[i].waitSemaphoreCount,
2625 pBindInfo[i].pWaitSemaphores,
2626 pBindInfo[i].signalSemaphoreCount,
2627 pBindInfo[i].pSignalSemaphores);
2628 if (result != VK_SUCCESS)
2629 return result;
2630
2631 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2632 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2633 &queue->device->empty_cs[queue->queue_family_index],
2634 1, NULL, NULL,
2635 &sem_info,
2636 false, base_fence);
2637 fence_emitted = true;
2638 if (fence)
2639 fence->submitted = true;
2640 }
2641
2642 radv_free_sem_info(&sem_info);
2643
2644 }
2645
2646 if (fence && !fence_emitted) {
2647 fence->signalled = true;
2648 }
2649
2650 return VK_SUCCESS;
2651 }
2652
2653 VkResult radv_CreateFence(
2654 VkDevice _device,
2655 const VkFenceCreateInfo* pCreateInfo,
2656 const VkAllocationCallbacks* pAllocator,
2657 VkFence* pFence)
2658 {
2659 RADV_FROM_HANDLE(radv_device, device, _device);
2660 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2661 sizeof(*fence), 8,
2662 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2663
2664 if (!fence)
2665 return VK_ERROR_OUT_OF_HOST_MEMORY;
2666
2667 memset(fence, 0, sizeof(*fence));
2668 fence->submitted = false;
2669 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2670 fence->fence = device->ws->create_fence();
2671 if (!fence->fence) {
2672 vk_free2(&device->alloc, pAllocator, fence);
2673 return VK_ERROR_OUT_OF_HOST_MEMORY;
2674 }
2675
2676 *pFence = radv_fence_to_handle(fence);
2677
2678 return VK_SUCCESS;
2679 }
2680
2681 void radv_DestroyFence(
2682 VkDevice _device,
2683 VkFence _fence,
2684 const VkAllocationCallbacks* pAllocator)
2685 {
2686 RADV_FROM_HANDLE(radv_device, device, _device);
2687 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2688
2689 if (!fence)
2690 return;
2691 device->ws->destroy_fence(fence->fence);
2692 vk_free2(&device->alloc, pAllocator, fence);
2693 }
2694
2695 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2696 {
2697 uint64_t current_time;
2698 struct timespec tv;
2699
2700 clock_gettime(CLOCK_MONOTONIC, &tv);
2701 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2702
2703 timeout = MIN2(UINT64_MAX - current_time, timeout);
2704
2705 return current_time + timeout;
2706 }
2707
2708 VkResult radv_WaitForFences(
2709 VkDevice _device,
2710 uint32_t fenceCount,
2711 const VkFence* pFences,
2712 VkBool32 waitAll,
2713 uint64_t timeout)
2714 {
2715 RADV_FROM_HANDLE(radv_device, device, _device);
2716 timeout = radv_get_absolute_timeout(timeout);
2717
2718 if (!waitAll && fenceCount > 1) {
2719 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2720 }
2721
2722 for (uint32_t i = 0; i < fenceCount; ++i) {
2723 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2724 bool expired = false;
2725
2726 if (fence->signalled)
2727 continue;
2728
2729 if (!fence->submitted)
2730 return VK_TIMEOUT;
2731
2732 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2733 if (!expired)
2734 return VK_TIMEOUT;
2735
2736 fence->signalled = true;
2737 }
2738
2739 return VK_SUCCESS;
2740 }
2741
2742 VkResult radv_ResetFences(VkDevice device,
2743 uint32_t fenceCount,
2744 const VkFence *pFences)
2745 {
2746 for (unsigned i = 0; i < fenceCount; ++i) {
2747 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2748 fence->submitted = fence->signalled = false;
2749 }
2750
2751 return VK_SUCCESS;
2752 }
2753
2754 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2755 {
2756 RADV_FROM_HANDLE(radv_device, device, _device);
2757 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2758
2759 if (fence->signalled)
2760 return VK_SUCCESS;
2761 if (!fence->submitted)
2762 return VK_NOT_READY;
2763
2764 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2765 return VK_NOT_READY;
2766
2767 return VK_SUCCESS;
2768 }
2769
2770
2771 // Queue semaphore functions
2772
2773 VkResult radv_CreateSemaphore(
2774 VkDevice _device,
2775 const VkSemaphoreCreateInfo* pCreateInfo,
2776 const VkAllocationCallbacks* pAllocator,
2777 VkSemaphore* pSemaphore)
2778 {
2779 RADV_FROM_HANDLE(radv_device, device, _device);
2780 const VkExportSemaphoreCreateInfoKHR *export =
2781 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2782 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2783 export ? export->handleTypes : 0;
2784
2785 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2786 sizeof(*sem), 8,
2787 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2788 if (!sem)
2789 return VK_ERROR_OUT_OF_HOST_MEMORY;
2790
2791 sem->temp_syncobj = 0;
2792 /* create a syncobject if we are going to export this semaphore */
2793 if (handleTypes) {
2794 assert (device->physical_device->rad_info.has_syncobj);
2795 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2796 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2797 if (ret) {
2798 vk_free2(&device->alloc, pAllocator, sem);
2799 return VK_ERROR_OUT_OF_HOST_MEMORY;
2800 }
2801 sem->sem = NULL;
2802 } else {
2803 sem->sem = device->ws->create_sem(device->ws);
2804 if (!sem->sem) {
2805 vk_free2(&device->alloc, pAllocator, sem);
2806 return VK_ERROR_OUT_OF_HOST_MEMORY;
2807 }
2808 sem->syncobj = 0;
2809 }
2810
2811 *pSemaphore = radv_semaphore_to_handle(sem);
2812 return VK_SUCCESS;
2813 }
2814
2815 void radv_DestroySemaphore(
2816 VkDevice _device,
2817 VkSemaphore _semaphore,
2818 const VkAllocationCallbacks* pAllocator)
2819 {
2820 RADV_FROM_HANDLE(radv_device, device, _device);
2821 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2822 if (!_semaphore)
2823 return;
2824
2825 if (sem->syncobj)
2826 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2827 else
2828 device->ws->destroy_sem(sem->sem);
2829 vk_free2(&device->alloc, pAllocator, sem);
2830 }
2831
2832 VkResult radv_CreateEvent(
2833 VkDevice _device,
2834 const VkEventCreateInfo* pCreateInfo,
2835 const VkAllocationCallbacks* pAllocator,
2836 VkEvent* pEvent)
2837 {
2838 RADV_FROM_HANDLE(radv_device, device, _device);
2839 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2840 sizeof(*event), 8,
2841 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2842
2843 if (!event)
2844 return VK_ERROR_OUT_OF_HOST_MEMORY;
2845
2846 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2847 RADEON_DOMAIN_GTT,
2848 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2849 if (!event->bo) {
2850 vk_free2(&device->alloc, pAllocator, event);
2851 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2852 }
2853
2854 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2855
2856 *pEvent = radv_event_to_handle(event);
2857
2858 return VK_SUCCESS;
2859 }
2860
2861 void radv_DestroyEvent(
2862 VkDevice _device,
2863 VkEvent _event,
2864 const VkAllocationCallbacks* pAllocator)
2865 {
2866 RADV_FROM_HANDLE(radv_device, device, _device);
2867 RADV_FROM_HANDLE(radv_event, event, _event);
2868
2869 if (!event)
2870 return;
2871 device->ws->buffer_destroy(event->bo);
2872 vk_free2(&device->alloc, pAllocator, event);
2873 }
2874
2875 VkResult radv_GetEventStatus(
2876 VkDevice _device,
2877 VkEvent _event)
2878 {
2879 RADV_FROM_HANDLE(radv_event, event, _event);
2880
2881 if (*event->map == 1)
2882 return VK_EVENT_SET;
2883 return VK_EVENT_RESET;
2884 }
2885
2886 VkResult radv_SetEvent(
2887 VkDevice _device,
2888 VkEvent _event)
2889 {
2890 RADV_FROM_HANDLE(radv_event, event, _event);
2891 *event->map = 1;
2892
2893 return VK_SUCCESS;
2894 }
2895
2896 VkResult radv_ResetEvent(
2897 VkDevice _device,
2898 VkEvent _event)
2899 {
2900 RADV_FROM_HANDLE(radv_event, event, _event);
2901 *event->map = 0;
2902
2903 return VK_SUCCESS;
2904 }
2905
2906 VkResult radv_CreateBuffer(
2907 VkDevice _device,
2908 const VkBufferCreateInfo* pCreateInfo,
2909 const VkAllocationCallbacks* pAllocator,
2910 VkBuffer* pBuffer)
2911 {
2912 RADV_FROM_HANDLE(radv_device, device, _device);
2913 struct radv_buffer *buffer;
2914
2915 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2916
2917 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2918 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2919 if (buffer == NULL)
2920 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2921
2922 buffer->size = pCreateInfo->size;
2923 buffer->usage = pCreateInfo->usage;
2924 buffer->bo = NULL;
2925 buffer->offset = 0;
2926 buffer->flags = pCreateInfo->flags;
2927
2928 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2929 buffer->bo = device->ws->buffer_create(device->ws,
2930 align64(buffer->size, 4096),
2931 4096, 0, RADEON_FLAG_VIRTUAL);
2932 if (!buffer->bo) {
2933 vk_free2(&device->alloc, pAllocator, buffer);
2934 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2935 }
2936 }
2937
2938 *pBuffer = radv_buffer_to_handle(buffer);
2939
2940 return VK_SUCCESS;
2941 }
2942
2943 void radv_DestroyBuffer(
2944 VkDevice _device,
2945 VkBuffer _buffer,
2946 const VkAllocationCallbacks* pAllocator)
2947 {
2948 RADV_FROM_HANDLE(radv_device, device, _device);
2949 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2950
2951 if (!buffer)
2952 return;
2953
2954 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2955 device->ws->buffer_destroy(buffer->bo);
2956
2957 vk_free2(&device->alloc, pAllocator, buffer);
2958 }
2959
2960 static inline unsigned
2961 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2962 {
2963 if (stencil)
2964 return image->surface.u.legacy.stencil_tiling_index[level];
2965 else
2966 return image->surface.u.legacy.tiling_index[level];
2967 }
2968
2969 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2970 {
2971 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2972 }
2973
2974 static void
2975 radv_initialise_color_surface(struct radv_device *device,
2976 struct radv_color_buffer_info *cb,
2977 struct radv_image_view *iview)
2978 {
2979 const struct vk_format_description *desc;
2980 unsigned ntype, format, swap, endian;
2981 unsigned blend_clamp = 0, blend_bypass = 0;
2982 uint64_t va;
2983 const struct radeon_surf *surf = &iview->image->surface;
2984
2985 desc = vk_format_description(iview->vk_format);
2986
2987 memset(cb, 0, sizeof(*cb));
2988
2989 /* Intensity is implemented as Red, so treat it that way. */
2990 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2991
2992 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2993
2994 cb->cb_color_base = va >> 8;
2995
2996 if (device->physical_device->rad_info.chip_class >= GFX9) {
2997 struct gfx9_surf_meta_flags meta;
2998 if (iview->image->dcc_offset)
2999 meta = iview->image->surface.u.gfx9.dcc;
3000 else
3001 meta = iview->image->surface.u.gfx9.cmask;
3002
3003 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3004 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3005 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3006 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3007
3008 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3009 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3010 } else {
3011 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3012 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3013
3014 cb->cb_color_base += level_info->offset >> 8;
3015 if (level_info->mode == RADEON_SURF_MODE_2D)
3016 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3017
3018 pitch_tile_max = level_info->nblk_x / 8 - 1;
3019 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3020 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3021
3022 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3023 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3024 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3025
3026 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3027 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3028
3029 if (iview->image->fmask.size) {
3030 if (device->physical_device->rad_info.chip_class >= CIK)
3031 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3032 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3033 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3034 } else {
3035 /* This must be set for fast clear to work without FMASK. */
3036 if (device->physical_device->rad_info.chip_class >= CIK)
3037 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3038 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3039 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3040 }
3041 }
3042
3043 /* CMASK variables */
3044 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3045 va += iview->image->cmask.offset;
3046 cb->cb_color_cmask = va >> 8;
3047
3048 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3049 va += iview->image->dcc_offset;
3050 cb->cb_dcc_base = va >> 8;
3051 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3052
3053 uint32_t max_slice = radv_surface_layer_count(iview);
3054 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3055 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3056
3057 if (iview->image->info.samples > 1) {
3058 unsigned log_samples = util_logbase2(iview->image->info.samples);
3059
3060 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3061 S_028C74_NUM_FRAGMENTS(log_samples);
3062 }
3063
3064 if (iview->image->fmask.size) {
3065 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3066 cb->cb_color_fmask = va >> 8;
3067 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3068 } else {
3069 cb->cb_color_fmask = cb->cb_color_base;
3070 }
3071
3072 ntype = radv_translate_color_numformat(iview->vk_format,
3073 desc,
3074 vk_format_get_first_non_void_channel(iview->vk_format));
3075 format = radv_translate_colorformat(iview->vk_format);
3076 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3077 radv_finishme("Illegal color\n");
3078 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3079 endian = radv_colorformat_endian_swap(format);
3080
3081 /* blend clamp should be set for all NORM/SRGB types */
3082 if (ntype == V_028C70_NUMBER_UNORM ||
3083 ntype == V_028C70_NUMBER_SNORM ||
3084 ntype == V_028C70_NUMBER_SRGB)
3085 blend_clamp = 1;
3086
3087 /* set blend bypass according to docs if SINT/UINT or
3088 8/24 COLOR variants */
3089 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3090 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3091 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3092 blend_clamp = 0;
3093 blend_bypass = 1;
3094 }
3095 #if 0
3096 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3097 (format == V_028C70_COLOR_8 ||
3098 format == V_028C70_COLOR_8_8 ||
3099 format == V_028C70_COLOR_8_8_8_8))
3100 ->color_is_int8 = true;
3101 #endif
3102 cb->cb_color_info = S_028C70_FORMAT(format) |
3103 S_028C70_COMP_SWAP(swap) |
3104 S_028C70_BLEND_CLAMP(blend_clamp) |
3105 S_028C70_BLEND_BYPASS(blend_bypass) |
3106 S_028C70_SIMPLE_FLOAT(1) |
3107 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3108 ntype != V_028C70_NUMBER_SNORM &&
3109 ntype != V_028C70_NUMBER_SRGB &&
3110 format != V_028C70_COLOR_8_24 &&
3111 format != V_028C70_COLOR_24_8) |
3112 S_028C70_NUMBER_TYPE(ntype) |
3113 S_028C70_ENDIAN(endian);
3114 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3115 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3116 if (device->physical_device->rad_info.chip_class == SI) {
3117 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3118 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3119 }
3120 }
3121
3122 if (iview->image->cmask.size &&
3123 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3124 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3125
3126 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3127 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3128
3129 if (device->physical_device->rad_info.chip_class >= VI) {
3130 unsigned max_uncompressed_block_size = 2;
3131 if (iview->image->info.samples > 1) {
3132 if (iview->image->surface.bpe == 1)
3133 max_uncompressed_block_size = 0;
3134 else if (iview->image->surface.bpe == 2)
3135 max_uncompressed_block_size = 1;
3136 }
3137
3138 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3139 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3140 }
3141
3142 /* This must be set for fast clear to work without FMASK. */
3143 if (!iview->image->fmask.size &&
3144 device->physical_device->rad_info.chip_class == SI) {
3145 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3146 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3147 }
3148
3149 if (device->physical_device->rad_info.chip_class >= GFX9) {
3150 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3151 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3152
3153 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3154 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3155 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3156 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3157 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3158 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3159
3160 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3161
3162 }
3163 }
3164
3165 static void
3166 radv_initialise_ds_surface(struct radv_device *device,
3167 struct radv_ds_buffer_info *ds,
3168 struct radv_image_view *iview)
3169 {
3170 unsigned level = iview->base_mip;
3171 unsigned format, stencil_format;
3172 uint64_t va, s_offs, z_offs;
3173 bool stencil_only = false;
3174 memset(ds, 0, sizeof(*ds));
3175 switch (iview->image->vk_format) {
3176 case VK_FORMAT_D24_UNORM_S8_UINT:
3177 case VK_FORMAT_X8_D24_UNORM_PACK32:
3178 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3179 ds->offset_scale = 2.0f;
3180 break;
3181 case VK_FORMAT_D16_UNORM:
3182 case VK_FORMAT_D16_UNORM_S8_UINT:
3183 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3184 ds->offset_scale = 4.0f;
3185 break;
3186 case VK_FORMAT_D32_SFLOAT:
3187 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3188 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3189 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3190 ds->offset_scale = 1.0f;
3191 break;
3192 case VK_FORMAT_S8_UINT:
3193 stencil_only = true;
3194 break;
3195 default:
3196 break;
3197 }
3198
3199 format = radv_translate_dbformat(iview->image->vk_format);
3200 stencil_format = iview->image->surface.has_stencil ?
3201 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3202
3203 uint32_t max_slice = radv_surface_layer_count(iview);
3204 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3205 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3206
3207 ds->db_htile_data_base = 0;
3208 ds->db_htile_surface = 0;
3209
3210 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3211 s_offs = z_offs = va;
3212
3213 if (device->physical_device->rad_info.chip_class >= GFX9) {
3214 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3215 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3216
3217 ds->db_z_info = S_028038_FORMAT(format) |
3218 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3219 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3220 S_028038_MAXMIP(iview->image->info.levels - 1);
3221 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3222 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3223
3224 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3225 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3226 ds->db_depth_view |= S_028008_MIPID(level);
3227
3228 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3229 S_02801C_Y_MAX(iview->image->info.height - 1);
3230
3231 /* Only use HTILE for the first level. */
3232 if (iview->image->surface.htile_size && !level) {
3233 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3234
3235 if (!iview->image->surface.has_stencil)
3236 /* Use all of the htile_buffer for depth if there's no stencil. */
3237 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3238 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3239 iview->image->htile_offset;
3240 ds->db_htile_data_base = va >> 8;
3241 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3242 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3243 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3244 }
3245 } else {
3246 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3247
3248 if (stencil_only)
3249 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3250
3251 z_offs += iview->image->surface.u.legacy.level[level].offset;
3252 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3253
3254 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3255 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3256 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3257
3258 if (iview->image->info.samples > 1)
3259 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3260
3261 if (device->physical_device->rad_info.chip_class >= CIK) {
3262 struct radeon_info *info = &device->physical_device->rad_info;
3263 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3264 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3265 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3266 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3267 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3268 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3269
3270 if (stencil_only)
3271 tile_mode = stencil_tile_mode;
3272
3273 ds->db_depth_info |=
3274 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3275 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3276 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3277 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3278 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3279 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3280 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3281 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3282 } else {
3283 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3284 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3285 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3286 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3287 if (stencil_only)
3288 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3289 }
3290
3291 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3292 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3293 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3294
3295 if (iview->image->surface.htile_size && !level) {
3296 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3297
3298 if (!iview->image->surface.has_stencil)
3299 /* Use all of the htile_buffer for depth if there's no stencil. */
3300 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3301
3302 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3303 iview->image->htile_offset;
3304 ds->db_htile_data_base = va >> 8;
3305 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3306 }
3307 }
3308
3309 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3310 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3311 }
3312
3313 VkResult radv_CreateFramebuffer(
3314 VkDevice _device,
3315 const VkFramebufferCreateInfo* pCreateInfo,
3316 const VkAllocationCallbacks* pAllocator,
3317 VkFramebuffer* pFramebuffer)
3318 {
3319 RADV_FROM_HANDLE(radv_device, device, _device);
3320 struct radv_framebuffer *framebuffer;
3321
3322 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3323
3324 size_t size = sizeof(*framebuffer) +
3325 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3326 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3327 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3328 if (framebuffer == NULL)
3329 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3330
3331 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3332 framebuffer->width = pCreateInfo->width;
3333 framebuffer->height = pCreateInfo->height;
3334 framebuffer->layers = pCreateInfo->layers;
3335 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3336 VkImageView _iview = pCreateInfo->pAttachments[i];
3337 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3338 framebuffer->attachments[i].attachment = iview;
3339 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3340 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3341 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3342 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3343 }
3344 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3345 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3346 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3347 }
3348
3349 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3350 return VK_SUCCESS;
3351 }
3352
3353 void radv_DestroyFramebuffer(
3354 VkDevice _device,
3355 VkFramebuffer _fb,
3356 const VkAllocationCallbacks* pAllocator)
3357 {
3358 RADV_FROM_HANDLE(radv_device, device, _device);
3359 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3360
3361 if (!fb)
3362 return;
3363 vk_free2(&device->alloc, pAllocator, fb);
3364 }
3365
3366 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3367 {
3368 switch (address_mode) {
3369 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3370 return V_008F30_SQ_TEX_WRAP;
3371 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3372 return V_008F30_SQ_TEX_MIRROR;
3373 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3374 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3375 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3376 return V_008F30_SQ_TEX_CLAMP_BORDER;
3377 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3378 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3379 default:
3380 unreachable("illegal tex wrap mode");
3381 break;
3382 }
3383 }
3384
3385 static unsigned
3386 radv_tex_compare(VkCompareOp op)
3387 {
3388 switch (op) {
3389 case VK_COMPARE_OP_NEVER:
3390 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3391 case VK_COMPARE_OP_LESS:
3392 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3393 case VK_COMPARE_OP_EQUAL:
3394 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3395 case VK_COMPARE_OP_LESS_OR_EQUAL:
3396 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3397 case VK_COMPARE_OP_GREATER:
3398 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3399 case VK_COMPARE_OP_NOT_EQUAL:
3400 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3401 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3402 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3403 case VK_COMPARE_OP_ALWAYS:
3404 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3405 default:
3406 unreachable("illegal compare mode");
3407 break;
3408 }
3409 }
3410
3411 static unsigned
3412 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3413 {
3414 switch (filter) {
3415 case VK_FILTER_NEAREST:
3416 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3417 V_008F38_SQ_TEX_XY_FILTER_POINT);
3418 case VK_FILTER_LINEAR:
3419 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3420 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3421 case VK_FILTER_CUBIC_IMG:
3422 default:
3423 fprintf(stderr, "illegal texture filter");
3424 return 0;
3425 }
3426 }
3427
3428 static unsigned
3429 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3430 {
3431 switch (mode) {
3432 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3433 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3434 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3435 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3436 default:
3437 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3438 }
3439 }
3440
3441 static unsigned
3442 radv_tex_bordercolor(VkBorderColor bcolor)
3443 {
3444 switch (bcolor) {
3445 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3446 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3447 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3448 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3449 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3450 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3451 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3452 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3453 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3454 default:
3455 break;
3456 }
3457 return 0;
3458 }
3459
3460 static unsigned
3461 radv_tex_aniso_filter(unsigned filter)
3462 {
3463 if (filter < 2)
3464 return 0;
3465 if (filter < 4)
3466 return 1;
3467 if (filter < 8)
3468 return 2;
3469 if (filter < 16)
3470 return 3;
3471 return 4;
3472 }
3473
3474 static void
3475 radv_init_sampler(struct radv_device *device,
3476 struct radv_sampler *sampler,
3477 const VkSamplerCreateInfo *pCreateInfo)
3478 {
3479 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3480 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3481 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3482 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3483
3484 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3485 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3486 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3487 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3488 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3489 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3490 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3491 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3492 S_008F30_DISABLE_CUBE_WRAP(0) |
3493 S_008F30_COMPAT_MODE(is_vi));
3494 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3495 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3496 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3497 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3498 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3499 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3500 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3501 S_008F38_MIP_POINT_PRECLAMP(0) |
3502 S_008F38_DISABLE_LSB_CEIL(1) |
3503 S_008F38_FILTER_PREC_FIX(1) |
3504 S_008F38_ANISO_OVERRIDE(is_vi));
3505 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3506 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3507 }
3508
3509 VkResult radv_CreateSampler(
3510 VkDevice _device,
3511 const VkSamplerCreateInfo* pCreateInfo,
3512 const VkAllocationCallbacks* pAllocator,
3513 VkSampler* pSampler)
3514 {
3515 RADV_FROM_HANDLE(radv_device, device, _device);
3516 struct radv_sampler *sampler;
3517
3518 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3519
3520 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3521 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3522 if (!sampler)
3523 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3524
3525 radv_init_sampler(device, sampler, pCreateInfo);
3526 *pSampler = radv_sampler_to_handle(sampler);
3527
3528 return VK_SUCCESS;
3529 }
3530
3531 void radv_DestroySampler(
3532 VkDevice _device,
3533 VkSampler _sampler,
3534 const VkAllocationCallbacks* pAllocator)
3535 {
3536 RADV_FROM_HANDLE(radv_device, device, _device);
3537 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3538
3539 if (!sampler)
3540 return;
3541 vk_free2(&device->alloc, pAllocator, sampler);
3542 }
3543
3544 /* vk_icd.h does not declare this function, so we declare it here to
3545 * suppress Wmissing-prototypes.
3546 */
3547 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3548 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3549
3550 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3551 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3552 {
3553 /* For the full details on loader interface versioning, see
3554 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3555 * What follows is a condensed summary, to help you navigate the large and
3556 * confusing official doc.
3557 *
3558 * - Loader interface v0 is incompatible with later versions. We don't
3559 * support it.
3560 *
3561 * - In loader interface v1:
3562 * - The first ICD entrypoint called by the loader is
3563 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3564 * entrypoint.
3565 * - The ICD must statically expose no other Vulkan symbol unless it is
3566 * linked with -Bsymbolic.
3567 * - Each dispatchable Vulkan handle created by the ICD must be
3568 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3569 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3570 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3571 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3572 * such loader-managed surfaces.
3573 *
3574 * - Loader interface v2 differs from v1 in:
3575 * - The first ICD entrypoint called by the loader is
3576 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3577 * statically expose this entrypoint.
3578 *
3579 * - Loader interface v3 differs from v2 in:
3580 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3581 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3582 * because the loader no longer does so.
3583 */
3584 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3585 return VK_SUCCESS;
3586 }
3587
3588 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3589 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3590 int *pFD)
3591 {
3592 RADV_FROM_HANDLE(radv_device, device, _device);
3593 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3594
3595 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3596
3597 /* We support only one handle type. */
3598 assert(pGetFdInfo->handleType ==
3599 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3600
3601 bool ret = radv_get_memory_fd(device, memory, pFD);
3602 if (ret == false)
3603 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3604 return VK_SUCCESS;
3605 }
3606
3607 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3608 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3609 int fd,
3610 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3611 {
3612 /* The valid usage section for this function says:
3613 *
3614 * "handleType must not be one of the handle types defined as opaque."
3615 *
3616 * Since we only handle opaque handles for now, there are no FD properties.
3617 */
3618 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3619 }
3620
3621 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3622 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3623 {
3624 RADV_FROM_HANDLE(radv_device, device, _device);
3625 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3626 uint32_t syncobj_handle = 0;
3627 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3628
3629 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3630 if (ret != 0)
3631 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3632
3633 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3634 sem->temp_syncobj = syncobj_handle;
3635 } else {
3636 sem->syncobj = syncobj_handle;
3637 }
3638 close(pImportSemaphoreFdInfo->fd);
3639 return VK_SUCCESS;
3640 }
3641
3642 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3643 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3644 int *pFd)
3645 {
3646 RADV_FROM_HANDLE(radv_device, device, _device);
3647 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3648 int ret;
3649 uint32_t syncobj_handle;
3650
3651 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3652 if (sem->temp_syncobj)
3653 syncobj_handle = sem->temp_syncobj;
3654 else
3655 syncobj_handle = sem->syncobj;
3656 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3657 if (ret)
3658 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3659 return VK_SUCCESS;
3660 }
3661
3662 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3663 VkPhysicalDevice physicalDevice,
3664 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3665 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3666 {
3667 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3668 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3669 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3670 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3671 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3672 } else {
3673 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3674 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3675 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3676 }
3677 }