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radv: Add debug option to dump meta shaders.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include <llvm/Config/llvm-config.h>
33 #include "radv_debug.h"
34 #include "radv_private.h"
35 #include "radv_shader.h"
36 #include "radv_cs.h"
37 #include "util/disk_cache.h"
38 #include "util/strtod.h"
39 #include "vk_util.h"
40 #include <xf86drm.h>
41 #include <amdgpu.h>
42 #include <amdgpu_drm.h>
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "git_sha1.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len, bool aco)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "OLAND"; break;
98 case CHIP_HAINAN: chip_string = "HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "KAVERI"; break;
101 case CHIP_KABINI: chip_string = "KABINI"; break;
102 case CHIP_HAWAII: chip_string = "HAWAII"; break;
103 case CHIP_TONGA: chip_string = "TONGA"; break;
104 case CHIP_ICELAND: chip_string = "ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "STONEY"; break;
111 case CHIP_VEGAM: chip_string = "VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "VEGA12"; break;
114 case CHIP_VEGA20: chip_string = "VEGA20"; break;
115 case CHIP_RAVEN: chip_string = "RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "RAVEN2"; break;
117 case CHIP_NAVI10: chip_string = "NAVI10"; break;
118 case CHIP_NAVI12: chip_string = "NAVI12"; break;
119 case CHIP_NAVI14: chip_string = "NAVI14"; break;
120 default: chip_string = "unknown"; break;
121 }
122
123 snprintf(name, name_len, "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", aco ? "/ACO" : "", chip_string);
124 }
125
126 static uint64_t
127 radv_get_visible_vram_size(struct radv_physical_device *device)
128 {
129 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
130 }
131
132 static uint64_t
133 radv_get_vram_size(struct radv_physical_device *device)
134 {
135 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
136 }
137
138 static void
139 radv_physical_device_init_mem_types(struct radv_physical_device *device)
140 {
141 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
142 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
143 uint64_t vram_size = radv_get_vram_size(device);
144 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
145 device->memory_properties.memoryHeapCount = 0;
146 if (vram_size > 0) {
147 vram_index = device->memory_properties.memoryHeapCount++;
148 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
149 .size = vram_size,
150 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
151 };
152 }
153 if (visible_vram_size) {
154 visible_vram_index = device->memory_properties.memoryHeapCount++;
155 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
156 .size = visible_vram_size,
157 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
158 };
159 }
160 if (device->rad_info.gart_size > 0) {
161 gart_index = device->memory_properties.memoryHeapCount++;
162 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
163 .size = device->rad_info.gart_size,
164 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
165 };
166 }
167
168 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
169 unsigned type_count = 0;
170 if (vram_index >= 0) {
171 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
172 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
173 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
174 .heapIndex = vram_index,
175 };
176 }
177 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
181 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
195 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
196 * as they have identical property flags, and according to the
197 * spec, for types with identical flags, the one with greater
198 * performance must be given a lower index. */
199 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
200 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
201 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
202 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
203 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
204 .heapIndex = gart_index,
205 };
206 }
207 if (gart_index >= 0) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
212 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
213 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
214 .heapIndex = gart_index,
215 };
216 }
217 device->memory_properties.memoryTypeCount = type_count;
218 }
219
220 static void
221 radv_handle_env_var_force_family(struct radv_physical_device *device)
222 {
223 const char *family = getenv("RADV_FORCE_FAMILY");
224 unsigned i;
225
226 if (!family)
227 return;
228
229 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
230 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
231 /* Override family and chip_class. */
232 device->rad_info.family = i;
233
234 if (i >= CHIP_NAVI10)
235 device->rad_info.chip_class = GFX10;
236 else if (i >= CHIP_VEGA10)
237 device->rad_info.chip_class = GFX9;
238 else if (i >= CHIP_TONGA)
239 device->rad_info.chip_class = GFX8;
240 else if (i >= CHIP_BONAIRE)
241 device->rad_info.chip_class = GFX7;
242 else
243 device->rad_info.chip_class = GFX6;
244
245 return;
246 }
247 }
248
249 fprintf(stderr, "radv: Unknown family: %s\n", family);
250 exit(1);
251 }
252
253 static VkResult
254 radv_physical_device_init(struct radv_physical_device *device,
255 struct radv_instance *instance,
256 drmDevicePtr drm_device)
257 {
258 const char *path = drm_device->nodes[DRM_NODE_RENDER];
259 VkResult result;
260 drmVersionPtr version;
261 int fd;
262 int master_fd = -1;
263
264 fd = open(path, O_RDWR | O_CLOEXEC);
265 if (fd < 0) {
266 if (instance->debug_flags & RADV_DEBUG_STARTUP)
267 radv_logi("Could not open device '%s'", path);
268
269 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
270 }
271
272 version = drmGetVersion(fd);
273 if (!version) {
274 close(fd);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Could not get the kernel driver version for device '%s'", path);
278
279 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
280 "failed to get version %s: %m", path);
281 }
282
283 if (strcmp(version->name, "amdgpu")) {
284 drmFreeVersion(version);
285 close(fd);
286
287 if (instance->debug_flags & RADV_DEBUG_STARTUP)
288 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
289
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Found compatible device '%s'.", path);
296
297 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
298 device->instance = instance;
299
300 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
301 instance->perftest_flags);
302 if (!device->ws) {
303 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
304 goto fail;
305 }
306
307 if (instance->enabled_extensions.KHR_display) {
308 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
309 if (master_fd >= 0) {
310 uint32_t accel_working = 0;
311 struct drm_amdgpu_info request = {
312 .return_pointer = (uintptr_t)&accel_working,
313 .return_size = sizeof(accel_working),
314 .query = AMDGPU_INFO_ACCEL_WORKING
315 };
316
317 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
318 close(master_fd);
319 master_fd = -1;
320 }
321 }
322 }
323
324 device->master_fd = master_fd;
325 device->local_fd = fd;
326 device->ws->query_info(device->ws, &device->rad_info);
327
328 radv_handle_env_var_force_family(device);
329
330 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
331 if ((device->rad_info.chip_class < GFX8 ||
332 device->rad_info.chip_class > GFX9) && device->use_aco) {
333 fprintf(stderr, "WARNING: disabling ACO on unsupported GPUs.\n");
334 device->use_aco = false;
335 }
336
337 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name), device->use_aco);
338
339 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
340 device->ws->destroy(device->ws);
341 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
342 "cannot generate UUID");
343 goto fail;
344 }
345
346 /* These flags affect shader compilation. */
347 uint64_t shader_env_flags =
348 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
349 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0) |
350 (device->use_aco ? 0x4 : 0);
351
352 /* The gpu id is already embedded in the uuid so we just pass "radv"
353 * when creating the cache.
354 */
355 char buf[VK_UUID_SIZE * 2 + 1];
356 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
357 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
358
359 if (device->rad_info.chip_class < GFX8 ||
360 device->rad_info.chip_class > GFX9)
361 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
362
363 radv_get_driver_uuid(&device->driver_uuid);
364 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
365
366 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
373 (device->use_aco || device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
374
375 device->use_ngg_streamout = false;
376
377 /* Determine the number of threads per wave for all stages. */
378 device->cs_wave_size = 64;
379 device->ps_wave_size = 64;
380 device->ge_wave_size = 64;
381
382 if (device->rad_info.chip_class >= GFX10) {
383 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
384 device->cs_wave_size = 32;
385
386 /* For pixel shaders, wave64 is recommanded. */
387 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
388 device->ps_wave_size = 32;
389
390 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
391 device->ge_wave_size = 32;
392 }
393
394 radv_physical_device_init_mem_types(device);
395 radv_fill_device_extension_table(device, &device->supported_extensions);
396
397 device->bus_info = *drm_device->businfo.pci;
398
399 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
400 ac_print_gpu_info(&device->rad_info);
401
402 /* The WSI is structured as a layer on top of the driver, so this has
403 * to be the last part of initialization (at least until we get other
404 * semi-layers).
405 */
406 result = radv_init_wsi(device);
407 if (result != VK_SUCCESS) {
408 device->ws->destroy(device->ws);
409 vk_error(instance, result);
410 goto fail;
411 }
412
413 return VK_SUCCESS;
414
415 fail:
416 close(fd);
417 if (master_fd != -1)
418 close(master_fd);
419 return result;
420 }
421
422 static void
423 radv_physical_device_finish(struct radv_physical_device *device)
424 {
425 radv_finish_wsi(device);
426 device->ws->destroy(device->ws);
427 disk_cache_destroy(device->disk_cache);
428 close(device->local_fd);
429 if (device->master_fd != -1)
430 close(device->master_fd);
431 }
432
433 static void *
434 default_alloc_func(void *pUserData, size_t size, size_t align,
435 VkSystemAllocationScope allocationScope)
436 {
437 return malloc(size);
438 }
439
440 static void *
441 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
442 size_t align, VkSystemAllocationScope allocationScope)
443 {
444 return realloc(pOriginal, size);
445 }
446
447 static void
448 default_free_func(void *pUserData, void *pMemory)
449 {
450 free(pMemory);
451 }
452
453 static const VkAllocationCallbacks default_alloc = {
454 .pUserData = NULL,
455 .pfnAllocation = default_alloc_func,
456 .pfnReallocation = default_realloc_func,
457 .pfnFree = default_free_func,
458 };
459
460 static const struct debug_control radv_debug_options[] = {
461 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
462 {"nodcc", RADV_DEBUG_NO_DCC},
463 {"shaders", RADV_DEBUG_DUMP_SHADERS},
464 {"nocache", RADV_DEBUG_NO_CACHE},
465 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
466 {"nohiz", RADV_DEBUG_NO_HIZ},
467 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
468 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
469 {"allbos", RADV_DEBUG_ALL_BOS},
470 {"noibs", RADV_DEBUG_NO_IBS},
471 {"spirv", RADV_DEBUG_DUMP_SPIRV},
472 {"vmfaults", RADV_DEBUG_VM_FAULTS},
473 {"zerovram", RADV_DEBUG_ZERO_VRAM},
474 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
475 {"nosisched", RADV_DEBUG_NO_SISCHED},
476 {"preoptir", RADV_DEBUG_PREOPTIR},
477 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
478 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
479 {"info", RADV_DEBUG_INFO},
480 {"errors", RADV_DEBUG_ERRORS},
481 {"startup", RADV_DEBUG_STARTUP},
482 {"checkir", RADV_DEBUG_CHECKIR},
483 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
484 {"nobinning", RADV_DEBUG_NOBINNING},
485 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
486 {"nongg", RADV_DEBUG_NO_NGG},
487 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
488 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
489 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
490 {NULL, 0}
491 };
492
493 const char *
494 radv_get_debug_option_name(int id)
495 {
496 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
497 return radv_debug_options[id].string;
498 }
499
500 static const struct debug_control radv_perftest_options[] = {
501 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
502 {"sisched", RADV_PERFTEST_SISCHED},
503 {"localbos", RADV_PERFTEST_LOCAL_BOS},
504 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
505 {"bolist", RADV_PERFTEST_BO_LIST},
506 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
507 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
508 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
509 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
510 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
511 {"dfsm", RADV_PERFTEST_DFSM},
512 {"aco", RADV_PERFTEST_ACO},
513 {NULL, 0}
514 };
515
516 const char *
517 radv_get_perftest_option_name(int id)
518 {
519 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
520 return radv_perftest_options[id].string;
521 }
522
523 static void
524 radv_handle_per_app_options(struct radv_instance *instance,
525 const VkApplicationInfo *info)
526 {
527 const char *name = info ? info->pApplicationName : NULL;
528
529 if (!name)
530 return;
531
532 if (!strcmp(name, "Talos - Linux - 32bit") ||
533 !strcmp(name, "Talos - Linux - 64bit")) {
534 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
535 /* Force enable LLVM sisched for Talos because it looks
536 * safe and it gives few more FPS.
537 */
538 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
539 }
540 } else if (!strcmp(name, "DOOM_VFR")) {
541 /* Work around a Doom VFR game bug */
542 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
543 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
544 /* Workaround for a WaW hazard when LLVM moves/merges
545 * load/store memory operations.
546 * See https://reviews.llvm.org/D61313
547 */
548 if (LLVM_VERSION_MAJOR < 9)
549 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
550 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
551 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
552 /* Force enable VK_AMD_shader_ballot because it looks
553 * safe and it gives a nice boost (+20% on Vega 56 at
554 * this time).
555 */
556 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
557 }
558 } else if (!strcmp(name, "Fledge")) {
559 /*
560 * Zero VRAM for "The Surge 2"
561 *
562 * This avoid a hang when when rendering any level. Likely
563 * uninitialized data in an indirect draw.
564 */
565 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
566 }
567 }
568
569 static int radv_get_instance_extension_index(const char *name)
570 {
571 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
572 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
573 return i;
574 }
575 return -1;
576 }
577
578 static const char radv_dri_options_xml[] =
579 DRI_CONF_BEGIN
580 DRI_CONF_SECTION_PERFORMANCE
581 DRI_CONF_ADAPTIVE_SYNC("true")
582 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
583 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
584 DRI_CONF_SECTION_END
585 DRI_CONF_END;
586
587 static void radv_init_dri_options(struct radv_instance *instance)
588 {
589 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
590 driParseConfigFiles(&instance->dri_options,
591 &instance->available_dri_options,
592 0, "radv", NULL,
593 instance->engineName,
594 instance->engineVersion);
595 }
596
597 VkResult radv_CreateInstance(
598 const VkInstanceCreateInfo* pCreateInfo,
599 const VkAllocationCallbacks* pAllocator,
600 VkInstance* pInstance)
601 {
602 struct radv_instance *instance;
603 VkResult result;
604
605 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
606
607 uint32_t client_version;
608 if (pCreateInfo->pApplicationInfo &&
609 pCreateInfo->pApplicationInfo->apiVersion != 0) {
610 client_version = pCreateInfo->pApplicationInfo->apiVersion;
611 } else {
612 client_version = VK_API_VERSION_1_0;
613 }
614
615 const char *engine_name = NULL;
616 uint32_t engine_version = 0;
617 if (pCreateInfo->pApplicationInfo) {
618 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
619 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
620 }
621
622 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
623 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
624 if (!instance)
625 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
626
627 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
628
629 if (pAllocator)
630 instance->alloc = *pAllocator;
631 else
632 instance->alloc = default_alloc;
633
634 instance->apiVersion = client_version;
635 instance->physicalDeviceCount = -1;
636
637 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
638 radv_debug_options);
639
640 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
641 radv_perftest_options);
642
643 if (instance->perftest_flags & RADV_PERFTEST_ACO)
644 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
645
646 if (instance->debug_flags & RADV_DEBUG_STARTUP)
647 radv_logi("Created an instance");
648
649 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
650 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
651 int index = radv_get_instance_extension_index(ext_name);
652
653 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
654 vk_free2(&default_alloc, pAllocator, instance);
655 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
656 }
657
658 instance->enabled_extensions.extensions[index] = true;
659 }
660
661 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
662 if (result != VK_SUCCESS) {
663 vk_free2(&default_alloc, pAllocator, instance);
664 return vk_error(instance, result);
665 }
666
667 instance->engineName = vk_strdup(&instance->alloc, engine_name,
668 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
669 instance->engineVersion = engine_version;
670
671 _mesa_locale_init();
672 glsl_type_singleton_init_or_ref();
673
674 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
675
676 radv_init_dri_options(instance);
677 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
678
679 *pInstance = radv_instance_to_handle(instance);
680
681 return VK_SUCCESS;
682 }
683
684 void radv_DestroyInstance(
685 VkInstance _instance,
686 const VkAllocationCallbacks* pAllocator)
687 {
688 RADV_FROM_HANDLE(radv_instance, instance, _instance);
689
690 if (!instance)
691 return;
692
693 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
694 radv_physical_device_finish(instance->physicalDevices + i);
695 }
696
697 vk_free(&instance->alloc, instance->engineName);
698
699 VG(VALGRIND_DESTROY_MEMPOOL(instance));
700
701 glsl_type_singleton_decref();
702 _mesa_locale_fini();
703
704 driDestroyOptionCache(&instance->dri_options);
705 driDestroyOptionInfo(&instance->available_dri_options);
706
707 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
708
709 vk_free(&instance->alloc, instance);
710 }
711
712 static VkResult
713 radv_enumerate_devices(struct radv_instance *instance)
714 {
715 /* TODO: Check for more devices ? */
716 drmDevicePtr devices[8];
717 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
718 int max_devices;
719
720 instance->physicalDeviceCount = 0;
721
722 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
723
724 if (instance->debug_flags & RADV_DEBUG_STARTUP)
725 radv_logi("Found %d drm nodes", max_devices);
726
727 if (max_devices < 1)
728 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
729
730 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
731 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
732 devices[i]->bustype == DRM_BUS_PCI &&
733 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
734
735 result = radv_physical_device_init(instance->physicalDevices +
736 instance->physicalDeviceCount,
737 instance,
738 devices[i]);
739 if (result == VK_SUCCESS)
740 ++instance->physicalDeviceCount;
741 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
742 break;
743 }
744 }
745 drmFreeDevices(devices, max_devices);
746
747 return result;
748 }
749
750 VkResult radv_EnumeratePhysicalDevices(
751 VkInstance _instance,
752 uint32_t* pPhysicalDeviceCount,
753 VkPhysicalDevice* pPhysicalDevices)
754 {
755 RADV_FROM_HANDLE(radv_instance, instance, _instance);
756 VkResult result;
757
758 if (instance->physicalDeviceCount < 0) {
759 result = radv_enumerate_devices(instance);
760 if (result != VK_SUCCESS &&
761 result != VK_ERROR_INCOMPATIBLE_DRIVER)
762 return result;
763 }
764
765 if (!pPhysicalDevices) {
766 *pPhysicalDeviceCount = instance->physicalDeviceCount;
767 } else {
768 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
769 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
770 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
771 }
772
773 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
774 : VK_SUCCESS;
775 }
776
777 VkResult radv_EnumeratePhysicalDeviceGroups(
778 VkInstance _instance,
779 uint32_t* pPhysicalDeviceGroupCount,
780 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
781 {
782 RADV_FROM_HANDLE(radv_instance, instance, _instance);
783 VkResult result;
784
785 if (instance->physicalDeviceCount < 0) {
786 result = radv_enumerate_devices(instance);
787 if (result != VK_SUCCESS &&
788 result != VK_ERROR_INCOMPATIBLE_DRIVER)
789 return result;
790 }
791
792 if (!pPhysicalDeviceGroupProperties) {
793 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
794 } else {
795 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
796 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
797 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
798 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
799 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
800 }
801 }
802 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
803 : VK_SUCCESS;
804 }
805
806 void radv_GetPhysicalDeviceFeatures(
807 VkPhysicalDevice physicalDevice,
808 VkPhysicalDeviceFeatures* pFeatures)
809 {
810 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
811 memset(pFeatures, 0, sizeof(*pFeatures));
812
813 *pFeatures = (VkPhysicalDeviceFeatures) {
814 .robustBufferAccess = true,
815 .fullDrawIndexUint32 = true,
816 .imageCubeArray = true,
817 .independentBlend = true,
818 .geometryShader = true,
819 .tessellationShader = true,
820 .sampleRateShading = true,
821 .dualSrcBlend = true,
822 .logicOp = true,
823 .multiDrawIndirect = true,
824 .drawIndirectFirstInstance = true,
825 .depthClamp = true,
826 .depthBiasClamp = true,
827 .fillModeNonSolid = true,
828 .depthBounds = true,
829 .wideLines = true,
830 .largePoints = true,
831 .alphaToOne = true,
832 .multiViewport = true,
833 .samplerAnisotropy = true,
834 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
835 .textureCompressionASTC_LDR = false,
836 .textureCompressionBC = true,
837 .occlusionQueryPrecise = true,
838 .pipelineStatisticsQuery = true,
839 .vertexPipelineStoresAndAtomics = true,
840 .fragmentStoresAndAtomics = true,
841 .shaderTessellationAndGeometryPointSize = true,
842 .shaderImageGatherExtended = true,
843 .shaderStorageImageExtendedFormats = true,
844 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
845 .shaderUniformBufferArrayDynamicIndexing = true,
846 .shaderSampledImageArrayDynamicIndexing = true,
847 .shaderStorageBufferArrayDynamicIndexing = true,
848 .shaderStorageImageArrayDynamicIndexing = true,
849 .shaderStorageImageReadWithoutFormat = true,
850 .shaderStorageImageWriteWithoutFormat = true,
851 .shaderClipDistance = true,
852 .shaderCullDistance = true,
853 .shaderFloat64 = true,
854 .shaderInt64 = true,
855 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && !pdevice->use_aco,
856 .sparseBinding = true,
857 .variableMultisampleRate = true,
858 .inheritedQueries = true,
859 };
860 }
861
862 void radv_GetPhysicalDeviceFeatures2(
863 VkPhysicalDevice physicalDevice,
864 VkPhysicalDeviceFeatures2 *pFeatures)
865 {
866 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
867 vk_foreach_struct(ext, pFeatures->pNext) {
868 switch (ext->sType) {
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
870 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
871 features->variablePointersStorageBuffer = true;
872 features->variablePointers = true;
873 break;
874 }
875 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
876 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
877 features->multiview = true;
878 features->multiviewGeometryShader = true;
879 features->multiviewTessellationShader = true;
880 break;
881 }
882 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
883 VkPhysicalDeviceShaderDrawParametersFeatures *features =
884 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
885 features->shaderDrawParameters = true;
886 break;
887 }
888 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
889 VkPhysicalDeviceProtectedMemoryFeatures *features =
890 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
891 features->protectedMemory = false;
892 break;
893 }
894 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
895 VkPhysicalDevice16BitStorageFeatures *features =
896 (VkPhysicalDevice16BitStorageFeatures*)ext;
897 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
898 features->storageBuffer16BitAccess = enabled;
899 features->uniformAndStorageBuffer16BitAccess = enabled;
900 features->storagePushConstant16 = enabled;
901 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
905 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
906 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
907 features->samplerYcbcrConversion = true;
908 break;
909 }
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
911 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
912 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
913 features->shaderInputAttachmentArrayDynamicIndexing = true;
914 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
915 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
916 features->shaderUniformBufferArrayNonUniformIndexing = true;
917 features->shaderSampledImageArrayNonUniformIndexing = true;
918 features->shaderStorageBufferArrayNonUniformIndexing = true;
919 features->shaderStorageImageArrayNonUniformIndexing = true;
920 features->shaderInputAttachmentArrayNonUniformIndexing = true;
921 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
922 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
923 features->descriptorBindingUniformBufferUpdateAfterBind = true;
924 features->descriptorBindingSampledImageUpdateAfterBind = true;
925 features->descriptorBindingStorageImageUpdateAfterBind = true;
926 features->descriptorBindingStorageBufferUpdateAfterBind = true;
927 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
928 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
929 features->descriptorBindingUpdateUnusedWhilePending = true;
930 features->descriptorBindingPartiallyBound = true;
931 features->descriptorBindingVariableDescriptorCount = true;
932 features->runtimeDescriptorArray = true;
933 break;
934 }
935 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
936 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
937 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
938 features->conditionalRendering = true;
939 features->inheritedConditionalRendering = false;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
943 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
944 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
945 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
946 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
950 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
951 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
952 features->transformFeedback = true;
953 features->geometryStreams = !pdevice->use_ngg_streamout;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
957 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
958 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
959 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
960 break;
961 }
962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
963 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
964 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
965 features->memoryPriority = VK_TRUE;
966 break;
967 }
968 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
969 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
970 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
971 features->bufferDeviceAddress = true;
972 features->bufferDeviceAddressCaptureReplay = false;
973 features->bufferDeviceAddressMultiDevice = false;
974 break;
975 }
976 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
977 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
978 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
979 features->depthClipEnable = true;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
983 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
984 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
985 features->hostQueryReset = true;
986 break;
987 }
988 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
989 VkPhysicalDevice8BitStorageFeaturesKHR *features =
990 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
991 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
992 features->storageBuffer8BitAccess = enabled;
993 features->uniformAndStorageBuffer8BitAccess = enabled;
994 features->storagePushConstant8 = enabled;
995 break;
996 }
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
998 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
999 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
1000 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1001 features->shaderInt8 = !pdevice->use_aco;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
1005 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
1006 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
1007 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1008 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1012 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1013 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1014 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1015 break;
1016 }
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1018 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1019 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1020
1021 features->inlineUniformBlock = true;
1022 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1023 break;
1024 }
1025 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1026 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1027 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1028 features->computeDerivativeGroupQuads = false;
1029 features->computeDerivativeGroupLinear = true;
1030 break;
1031 }
1032 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1033 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1034 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1035 features->ycbcrImageArrays = true;
1036 break;
1037 }
1038 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1039 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1040 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1041 features->uniformBufferStandardLayout = true;
1042 break;
1043 }
1044 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1045 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1046 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1047 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1048 break;
1049 }
1050 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1051 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1052 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1053 features->imagelessFramebuffer = true;
1054 break;
1055 }
1056 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1057 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1058 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1059 features->pipelineExecutableInfo = true;
1060 break;
1061 }
1062 default:
1063 break;
1064 }
1065 }
1066 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1067 }
1068
1069 void radv_GetPhysicalDeviceProperties(
1070 VkPhysicalDevice physicalDevice,
1071 VkPhysicalDeviceProperties* pProperties)
1072 {
1073 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1074 VkSampleCountFlags sample_counts = 0xf;
1075
1076 /* make sure that the entire descriptor set is addressable with a signed
1077 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1078 * be at most 2 GiB. the combined image & samples object count as one of
1079 * both. This limit is for the pipeline layout, not for the set layout, but
1080 * there is no set limit, so we just set a pipeline limit. I don't think
1081 * any app is going to hit this soon. */
1082 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1083 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1084 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1085 32 /* sampler, largest when combined with image */ +
1086 64 /* sampled image */ +
1087 64 /* storage image */);
1088
1089 VkPhysicalDeviceLimits limits = {
1090 .maxImageDimension1D = (1 << 14),
1091 .maxImageDimension2D = (1 << 14),
1092 .maxImageDimension3D = (1 << 11),
1093 .maxImageDimensionCube = (1 << 14),
1094 .maxImageArrayLayers = (1 << 11),
1095 .maxTexelBufferElements = 128 * 1024 * 1024,
1096 .maxUniformBufferRange = UINT32_MAX,
1097 .maxStorageBufferRange = UINT32_MAX,
1098 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1099 .maxMemoryAllocationCount = UINT32_MAX,
1100 .maxSamplerAllocationCount = 64 * 1024,
1101 .bufferImageGranularity = 64, /* A cache line */
1102 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1103 .maxBoundDescriptorSets = MAX_SETS,
1104 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1105 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1106 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1107 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1108 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1109 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1110 .maxPerStageResources = max_descriptor_set_size,
1111 .maxDescriptorSetSamplers = max_descriptor_set_size,
1112 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1113 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1114 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1115 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1116 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1117 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1118 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1119 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1120 .maxVertexInputBindings = MAX_VBS,
1121 .maxVertexInputAttributeOffset = 2047,
1122 .maxVertexInputBindingStride = 2048,
1123 .maxVertexOutputComponents = 128,
1124 .maxTessellationGenerationLevel = 64,
1125 .maxTessellationPatchSize = 32,
1126 .maxTessellationControlPerVertexInputComponents = 128,
1127 .maxTessellationControlPerVertexOutputComponents = 128,
1128 .maxTessellationControlPerPatchOutputComponents = 120,
1129 .maxTessellationControlTotalOutputComponents = 4096,
1130 .maxTessellationEvaluationInputComponents = 128,
1131 .maxTessellationEvaluationOutputComponents = 128,
1132 .maxGeometryShaderInvocations = 127,
1133 .maxGeometryInputComponents = 64,
1134 .maxGeometryOutputComponents = 128,
1135 .maxGeometryOutputVertices = 256,
1136 .maxGeometryTotalOutputComponents = 1024,
1137 .maxFragmentInputComponents = 128,
1138 .maxFragmentOutputAttachments = 8,
1139 .maxFragmentDualSrcAttachments = 1,
1140 .maxFragmentCombinedOutputResources = 8,
1141 .maxComputeSharedMemorySize = 32768,
1142 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1143 .maxComputeWorkGroupInvocations = 2048,
1144 .maxComputeWorkGroupSize = {
1145 2048,
1146 2048,
1147 2048
1148 },
1149 .subPixelPrecisionBits = 8,
1150 .subTexelPrecisionBits = 8,
1151 .mipmapPrecisionBits = 8,
1152 .maxDrawIndexedIndexValue = UINT32_MAX,
1153 .maxDrawIndirectCount = UINT32_MAX,
1154 .maxSamplerLodBias = 16,
1155 .maxSamplerAnisotropy = 16,
1156 .maxViewports = MAX_VIEWPORTS,
1157 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1158 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1159 .viewportSubPixelBits = 8,
1160 .minMemoryMapAlignment = 4096, /* A page */
1161 .minTexelBufferOffsetAlignment = 1,
1162 .minUniformBufferOffsetAlignment = 4,
1163 .minStorageBufferOffsetAlignment = 4,
1164 .minTexelOffset = -32,
1165 .maxTexelOffset = 31,
1166 .minTexelGatherOffset = -32,
1167 .maxTexelGatherOffset = 31,
1168 .minInterpolationOffset = -2,
1169 .maxInterpolationOffset = 2,
1170 .subPixelInterpolationOffsetBits = 8,
1171 .maxFramebufferWidth = (1 << 14),
1172 .maxFramebufferHeight = (1 << 14),
1173 .maxFramebufferLayers = (1 << 10),
1174 .framebufferColorSampleCounts = sample_counts,
1175 .framebufferDepthSampleCounts = sample_counts,
1176 .framebufferStencilSampleCounts = sample_counts,
1177 .framebufferNoAttachmentsSampleCounts = sample_counts,
1178 .maxColorAttachments = MAX_RTS,
1179 .sampledImageColorSampleCounts = sample_counts,
1180 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1181 .sampledImageDepthSampleCounts = sample_counts,
1182 .sampledImageStencilSampleCounts = sample_counts,
1183 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1184 .maxSampleMaskWords = 1,
1185 .timestampComputeAndGraphics = true,
1186 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1187 .maxClipDistances = 8,
1188 .maxCullDistances = 8,
1189 .maxCombinedClipAndCullDistances = 8,
1190 .discreteQueuePriorities = 2,
1191 .pointSizeRange = { 0.0, 8192.0 },
1192 .lineWidthRange = { 0.0, 7.9921875 },
1193 .pointSizeGranularity = (1.0 / 8.0),
1194 .lineWidthGranularity = (1.0 / 128.0),
1195 .strictLines = false, /* FINISHME */
1196 .standardSampleLocations = true,
1197 .optimalBufferCopyOffsetAlignment = 128,
1198 .optimalBufferCopyRowPitchAlignment = 128,
1199 .nonCoherentAtomSize = 64,
1200 };
1201
1202 *pProperties = (VkPhysicalDeviceProperties) {
1203 .apiVersion = radv_physical_device_api_version(pdevice),
1204 .driverVersion = vk_get_driver_version(),
1205 .vendorID = ATI_VENDOR_ID,
1206 .deviceID = pdevice->rad_info.pci_id,
1207 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1208 .limits = limits,
1209 .sparseProperties = {0},
1210 };
1211
1212 strcpy(pProperties->deviceName, pdevice->name);
1213 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1214 }
1215
1216 void radv_GetPhysicalDeviceProperties2(
1217 VkPhysicalDevice physicalDevice,
1218 VkPhysicalDeviceProperties2 *pProperties)
1219 {
1220 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1221 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1222
1223 vk_foreach_struct(ext, pProperties->pNext) {
1224 switch (ext->sType) {
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1226 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1227 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1228 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1229 break;
1230 }
1231 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1232 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1233 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1234 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1235 properties->deviceLUIDValid = false;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1239 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1240 properties->maxMultiviewViewCount = MAX_VIEWS;
1241 properties->maxMultiviewInstanceIndex = INT_MAX;
1242 break;
1243 }
1244 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1245 VkPhysicalDevicePointClippingProperties *properties =
1246 (VkPhysicalDevicePointClippingProperties*)ext;
1247 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1248 break;
1249 }
1250 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1251 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1252 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1253 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1254 break;
1255 }
1256 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1257 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1258 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1259 properties->minImportedHostPointerAlignment = 4096;
1260 break;
1261 }
1262 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1263 VkPhysicalDeviceSubgroupProperties *properties =
1264 (VkPhysicalDeviceSubgroupProperties*)ext;
1265 properties->subgroupSize = 64;
1266 properties->supportedStages = VK_SHADER_STAGE_ALL;
1267 properties->supportedOperations =
1268 VK_SUBGROUP_FEATURE_BASIC_BIT |
1269 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1270 VK_SUBGROUP_FEATURE_QUAD_BIT |
1271 VK_SUBGROUP_FEATURE_VOTE_BIT;
1272 if (pdevice->rad_info.chip_class >= GFX8) {
1273 properties->supportedOperations |=
1274 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1275 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1276 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1277 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1278 }
1279 properties->quadOperationsInAllStages = true;
1280 break;
1281 }
1282 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1283 VkPhysicalDeviceMaintenance3Properties *properties =
1284 (VkPhysicalDeviceMaintenance3Properties*)ext;
1285 /* Make sure everything is addressable by a signed 32-bit int, and
1286 * our largest descriptors are 96 bytes. */
1287 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1288 /* Our buffer size fields allow only this much */
1289 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1290 break;
1291 }
1292 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1293 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1294 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1295 /* GFX6-8 only support single channel min/max filter. */
1296 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1297 properties->filterMinmaxSingleComponentFormats = true;
1298 break;
1299 }
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1301 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1302 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1303
1304 /* Shader engines. */
1305 properties->shaderEngineCount =
1306 pdevice->rad_info.max_se;
1307 properties->shaderArraysPerEngineCount =
1308 pdevice->rad_info.max_sh_per_se;
1309 properties->computeUnitsPerShaderArray =
1310 pdevice->rad_info.num_good_cu_per_sh;
1311 properties->simdPerComputeUnit = 4;
1312 properties->wavefrontsPerSimd =
1313 pdevice->rad_info.family == CHIP_TONGA ||
1314 pdevice->rad_info.family == CHIP_ICELAND ||
1315 pdevice->rad_info.family == CHIP_POLARIS10 ||
1316 pdevice->rad_info.family == CHIP_POLARIS11 ||
1317 pdevice->rad_info.family == CHIP_POLARIS12 ||
1318 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1319 properties->wavefrontSize = 64;
1320
1321 /* SGPR. */
1322 properties->sgprsPerSimd =
1323 pdevice->rad_info.num_physical_sgprs_per_simd;
1324 properties->minSgprAllocation =
1325 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1326 properties->maxSgprAllocation =
1327 pdevice->rad_info.family == CHIP_TONGA ||
1328 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1329 properties->sgprAllocationGranularity =
1330 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1331
1332 /* VGPR. */
1333 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1334 properties->minVgprAllocation = 4;
1335 properties->maxVgprAllocation = 256;
1336 properties->vgprAllocationGranularity = 4;
1337 break;
1338 }
1339 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1340 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1341 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1342
1343 properties->shaderCoreFeatures = 0;
1344 properties->activeComputeUnitCount =
1345 pdevice->rad_info.num_good_compute_units;
1346 break;
1347 }
1348 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1349 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1350 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1351 properties->maxVertexAttribDivisor = UINT32_MAX;
1352 break;
1353 }
1354 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1355 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1356 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1357 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1358 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1359 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1360 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1361 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1362 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1363 properties->robustBufferAccessUpdateAfterBind = false;
1364 properties->quadDivergentImplicitLod = false;
1365
1366 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1367 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1368 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1369 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1370 32 /* sampler, largest when combined with image */ +
1371 64 /* sampled image */ +
1372 64 /* storage image */);
1373 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1374 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1375 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1376 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1377 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1378 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1379 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1380 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1381 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1382 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1383 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1384 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1385 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1386 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1387 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1388 break;
1389 }
1390 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1391 VkPhysicalDeviceProtectedMemoryProperties *properties =
1392 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1393 properties->protectedNoFault = false;
1394 break;
1395 }
1396 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1397 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1398 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1399 properties->primitiveOverestimationSize = 0;
1400 properties->maxExtraPrimitiveOverestimationSize = 0;
1401 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1402 properties->primitiveUnderestimation = VK_FALSE;
1403 properties->conservativePointAndLineRasterization = VK_FALSE;
1404 properties->degenerateTrianglesRasterized = VK_FALSE;
1405 properties->degenerateLinesRasterized = VK_FALSE;
1406 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1407 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1408 break;
1409 }
1410 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1411 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1412 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1413 properties->pciDomain = pdevice->bus_info.domain;
1414 properties->pciBus = pdevice->bus_info.bus;
1415 properties->pciDevice = pdevice->bus_info.dev;
1416 properties->pciFunction = pdevice->bus_info.func;
1417 break;
1418 }
1419 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1420 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1421 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1422
1423 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1424 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1425 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1426 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1427 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1428
1429 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1430 .major = 1,
1431 .minor = 1,
1432 .subminor = 2,
1433 .patch = 0,
1434 };
1435 break;
1436 }
1437 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1438 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1439 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1440 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1441 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1442 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1443 properties->maxTransformFeedbackStreamDataSize = 512;
1444 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1445 properties->maxTransformFeedbackBufferDataStride = 512;
1446 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1447 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1448 properties->transformFeedbackRasterizationStreamSelect = false;
1449 properties->transformFeedbackDraw = true;
1450 break;
1451 }
1452 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1453 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1454 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1455
1456 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1457 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1458 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1459 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1460 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1461 break;
1462 }
1463 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1464 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1465 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1466 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1467 VK_SAMPLE_COUNT_4_BIT |
1468 VK_SAMPLE_COUNT_8_BIT;
1469 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1470 properties->sampleLocationCoordinateRange[0] = 0.0f;
1471 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1472 properties->sampleLocationSubPixelBits = 4;
1473 properties->variableSampleLocations = VK_FALSE;
1474 break;
1475 }
1476 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1477 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1478 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1479
1480 /* We support all of the depth resolve modes */
1481 properties->supportedDepthResolveModes =
1482 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1483 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1484 VK_RESOLVE_MODE_MIN_BIT_KHR |
1485 VK_RESOLVE_MODE_MAX_BIT_KHR;
1486
1487 /* Average doesn't make sense for stencil so we don't support that */
1488 properties->supportedStencilResolveModes =
1489 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1490 VK_RESOLVE_MODE_MIN_BIT_KHR |
1491 VK_RESOLVE_MODE_MAX_BIT_KHR;
1492
1493 properties->independentResolveNone = VK_TRUE;
1494 properties->independentResolve = VK_TRUE;
1495 break;
1496 }
1497 default:
1498 break;
1499 }
1500 }
1501 }
1502
1503 static void radv_get_physical_device_queue_family_properties(
1504 struct radv_physical_device* pdevice,
1505 uint32_t* pCount,
1506 VkQueueFamilyProperties** pQueueFamilyProperties)
1507 {
1508 int num_queue_families = 1;
1509 int idx;
1510 if (pdevice->rad_info.num_compute_rings > 0 &&
1511 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1512 num_queue_families++;
1513
1514 if (pQueueFamilyProperties == NULL) {
1515 *pCount = num_queue_families;
1516 return;
1517 }
1518
1519 if (!*pCount)
1520 return;
1521
1522 idx = 0;
1523 if (*pCount >= 1) {
1524 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1525 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1526 VK_QUEUE_COMPUTE_BIT |
1527 VK_QUEUE_TRANSFER_BIT |
1528 VK_QUEUE_SPARSE_BINDING_BIT,
1529 .queueCount = 1,
1530 .timestampValidBits = 64,
1531 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1532 };
1533 idx++;
1534 }
1535
1536 if (pdevice->rad_info.num_compute_rings > 0 &&
1537 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1538 if (*pCount > idx) {
1539 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1540 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1541 VK_QUEUE_TRANSFER_BIT |
1542 VK_QUEUE_SPARSE_BINDING_BIT,
1543 .queueCount = pdevice->rad_info.num_compute_rings,
1544 .timestampValidBits = 64,
1545 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1546 };
1547 idx++;
1548 }
1549 }
1550 *pCount = idx;
1551 }
1552
1553 void radv_GetPhysicalDeviceQueueFamilyProperties(
1554 VkPhysicalDevice physicalDevice,
1555 uint32_t* pCount,
1556 VkQueueFamilyProperties* pQueueFamilyProperties)
1557 {
1558 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1559 if (!pQueueFamilyProperties) {
1560 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1561 return;
1562 }
1563 VkQueueFamilyProperties *properties[] = {
1564 pQueueFamilyProperties + 0,
1565 pQueueFamilyProperties + 1,
1566 pQueueFamilyProperties + 2,
1567 };
1568 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1569 assert(*pCount <= 3);
1570 }
1571
1572 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1573 VkPhysicalDevice physicalDevice,
1574 uint32_t* pCount,
1575 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1576 {
1577 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1578 if (!pQueueFamilyProperties) {
1579 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1580 return;
1581 }
1582 VkQueueFamilyProperties *properties[] = {
1583 &pQueueFamilyProperties[0].queueFamilyProperties,
1584 &pQueueFamilyProperties[1].queueFamilyProperties,
1585 &pQueueFamilyProperties[2].queueFamilyProperties,
1586 };
1587 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1588 assert(*pCount <= 3);
1589 }
1590
1591 void radv_GetPhysicalDeviceMemoryProperties(
1592 VkPhysicalDevice physicalDevice,
1593 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1594 {
1595 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1596
1597 *pMemoryProperties = physical_device->memory_properties;
1598 }
1599
1600 static void
1601 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1602 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1603 {
1604 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1605 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1606 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1607 uint64_t vram_size = radv_get_vram_size(device);
1608 uint64_t gtt_size = device->rad_info.gart_size;
1609 uint64_t heap_budget, heap_usage;
1610
1611 /* For all memory heaps, the computation of budget is as follow:
1612 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1613 *
1614 * The Vulkan spec 1.1.97 says that the budget should include any
1615 * currently allocated device memory.
1616 *
1617 * Note that the application heap usages are not really accurate (eg.
1618 * in presence of shared buffers).
1619 */
1620 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1621 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1622
1623 switch (device->mem_type_indices[i]) {
1624 case RADV_MEM_TYPE_VRAM:
1625 heap_usage = device->ws->query_value(device->ws,
1626 RADEON_ALLOCATED_VRAM);
1627
1628 heap_budget = vram_size -
1629 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1630 heap_usage;
1631
1632 memoryBudget->heapBudget[heap_index] = heap_budget;
1633 memoryBudget->heapUsage[heap_index] = heap_usage;
1634 break;
1635 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1636 heap_usage = device->ws->query_value(device->ws,
1637 RADEON_ALLOCATED_VRAM_VIS);
1638
1639 heap_budget = visible_vram_size -
1640 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1641 heap_usage;
1642
1643 memoryBudget->heapBudget[heap_index] = heap_budget;
1644 memoryBudget->heapUsage[heap_index] = heap_usage;
1645 break;
1646 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1647 heap_usage = device->ws->query_value(device->ws,
1648 RADEON_ALLOCATED_GTT);
1649
1650 heap_budget = gtt_size -
1651 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1652 heap_usage;
1653
1654 memoryBudget->heapBudget[heap_index] = heap_budget;
1655 memoryBudget->heapUsage[heap_index] = heap_usage;
1656 break;
1657 default:
1658 break;
1659 }
1660 }
1661
1662 /* The heapBudget and heapUsage values must be zero for array elements
1663 * greater than or equal to
1664 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1665 */
1666 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1667 memoryBudget->heapBudget[i] = 0;
1668 memoryBudget->heapUsage[i] = 0;
1669 }
1670 }
1671
1672 void radv_GetPhysicalDeviceMemoryProperties2(
1673 VkPhysicalDevice physicalDevice,
1674 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1675 {
1676 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1677 &pMemoryProperties->memoryProperties);
1678
1679 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1680 vk_find_struct(pMemoryProperties->pNext,
1681 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1682 if (memory_budget)
1683 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1684 }
1685
1686 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1687 VkDevice _device,
1688 VkExternalMemoryHandleTypeFlagBits handleType,
1689 const void *pHostPointer,
1690 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1691 {
1692 RADV_FROM_HANDLE(radv_device, device, _device);
1693
1694 switch (handleType)
1695 {
1696 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1697 const struct radv_physical_device *physical_device = device->physical_device;
1698 uint32_t memoryTypeBits = 0;
1699 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1700 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1701 memoryTypeBits = (1 << i);
1702 break;
1703 }
1704 }
1705 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1706 return VK_SUCCESS;
1707 }
1708 default:
1709 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1710 }
1711 }
1712
1713 static enum radeon_ctx_priority
1714 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1715 {
1716 /* Default to MEDIUM when a specific global priority isn't requested */
1717 if (!pObj)
1718 return RADEON_CTX_PRIORITY_MEDIUM;
1719
1720 switch(pObj->globalPriority) {
1721 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1722 return RADEON_CTX_PRIORITY_REALTIME;
1723 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1724 return RADEON_CTX_PRIORITY_HIGH;
1725 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1726 return RADEON_CTX_PRIORITY_MEDIUM;
1727 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1728 return RADEON_CTX_PRIORITY_LOW;
1729 default:
1730 unreachable("Illegal global priority value");
1731 return RADEON_CTX_PRIORITY_INVALID;
1732 }
1733 }
1734
1735 static int
1736 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1737 uint32_t queue_family_index, int idx,
1738 VkDeviceQueueCreateFlags flags,
1739 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1740 {
1741 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1742 queue->device = device;
1743 queue->queue_family_index = queue_family_index;
1744 queue->queue_idx = idx;
1745 queue->priority = radv_get_queue_global_priority(global_priority);
1746 queue->flags = flags;
1747
1748 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1749 if (!queue->hw_ctx)
1750 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1751
1752 return VK_SUCCESS;
1753 }
1754
1755 static void
1756 radv_queue_finish(struct radv_queue *queue)
1757 {
1758 if (queue->hw_ctx)
1759 queue->device->ws->ctx_destroy(queue->hw_ctx);
1760
1761 if (queue->initial_full_flush_preamble_cs)
1762 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1763 if (queue->initial_preamble_cs)
1764 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1765 if (queue->continue_preamble_cs)
1766 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1767 if (queue->descriptor_bo)
1768 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1769 if (queue->scratch_bo)
1770 queue->device->ws->buffer_destroy(queue->scratch_bo);
1771 if (queue->esgs_ring_bo)
1772 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1773 if (queue->gsvs_ring_bo)
1774 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1775 if (queue->tess_rings_bo)
1776 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1777 if (queue->gds_bo)
1778 queue->device->ws->buffer_destroy(queue->gds_bo);
1779 if (queue->gds_oa_bo)
1780 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
1781 if (queue->compute_scratch_bo)
1782 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1783 }
1784
1785 static void
1786 radv_bo_list_init(struct radv_bo_list *bo_list)
1787 {
1788 pthread_mutex_init(&bo_list->mutex, NULL);
1789 bo_list->list.count = bo_list->capacity = 0;
1790 bo_list->list.bos = NULL;
1791 }
1792
1793 static void
1794 radv_bo_list_finish(struct radv_bo_list *bo_list)
1795 {
1796 free(bo_list->list.bos);
1797 pthread_mutex_destroy(&bo_list->mutex);
1798 }
1799
1800 static VkResult radv_bo_list_add(struct radv_device *device,
1801 struct radeon_winsys_bo *bo)
1802 {
1803 struct radv_bo_list *bo_list = &device->bo_list;
1804
1805 if (bo->is_local)
1806 return VK_SUCCESS;
1807
1808 if (unlikely(!device->use_global_bo_list))
1809 return VK_SUCCESS;
1810
1811 pthread_mutex_lock(&bo_list->mutex);
1812 if (bo_list->list.count == bo_list->capacity) {
1813 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1814 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1815
1816 if (!data) {
1817 pthread_mutex_unlock(&bo_list->mutex);
1818 return VK_ERROR_OUT_OF_HOST_MEMORY;
1819 }
1820
1821 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1822 bo_list->capacity = capacity;
1823 }
1824
1825 bo_list->list.bos[bo_list->list.count++] = bo;
1826 pthread_mutex_unlock(&bo_list->mutex);
1827 return VK_SUCCESS;
1828 }
1829
1830 static void radv_bo_list_remove(struct radv_device *device,
1831 struct radeon_winsys_bo *bo)
1832 {
1833 struct radv_bo_list *bo_list = &device->bo_list;
1834
1835 if (bo->is_local)
1836 return;
1837
1838 if (unlikely(!device->use_global_bo_list))
1839 return;
1840
1841 pthread_mutex_lock(&bo_list->mutex);
1842 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1843 if (bo_list->list.bos[i] == bo) {
1844 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1845 --bo_list->list.count;
1846 break;
1847 }
1848 }
1849 pthread_mutex_unlock(&bo_list->mutex);
1850 }
1851
1852 static void
1853 radv_device_init_gs_info(struct radv_device *device)
1854 {
1855 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1856 device->physical_device->rad_info.family);
1857 }
1858
1859 static int radv_get_device_extension_index(const char *name)
1860 {
1861 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1862 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1863 return i;
1864 }
1865 return -1;
1866 }
1867
1868 static int
1869 radv_get_int_debug_option(const char *name, int default_value)
1870 {
1871 const char *str;
1872 int result;
1873
1874 str = getenv(name);
1875 if (!str) {
1876 result = default_value;
1877 } else {
1878 char *endptr;
1879
1880 result = strtol(str, &endptr, 0);
1881 if (str == endptr) {
1882 /* No digits founs. */
1883 result = default_value;
1884 }
1885 }
1886
1887 return result;
1888 }
1889
1890 VkResult radv_CreateDevice(
1891 VkPhysicalDevice physicalDevice,
1892 const VkDeviceCreateInfo* pCreateInfo,
1893 const VkAllocationCallbacks* pAllocator,
1894 VkDevice* pDevice)
1895 {
1896 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1897 VkResult result;
1898 struct radv_device *device;
1899
1900 bool keep_shader_info = false;
1901
1902 /* Check enabled features */
1903 if (pCreateInfo->pEnabledFeatures) {
1904 VkPhysicalDeviceFeatures supported_features;
1905 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1906 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1907 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1908 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1909 for (uint32_t i = 0; i < num_features; i++) {
1910 if (enabled_feature[i] && !supported_feature[i])
1911 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1912 }
1913 }
1914
1915 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1916 sizeof(*device), 8,
1917 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1918 if (!device)
1919 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1920
1921 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1922 device->instance = physical_device->instance;
1923 device->physical_device = physical_device;
1924
1925 device->ws = physical_device->ws;
1926 if (pAllocator)
1927 device->alloc = *pAllocator;
1928 else
1929 device->alloc = physical_device->instance->alloc;
1930
1931 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1932 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1933 int index = radv_get_device_extension_index(ext_name);
1934 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1935 vk_free(&device->alloc, device);
1936 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1937 }
1938
1939 device->enabled_extensions.extensions[index] = true;
1940 }
1941
1942 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1943
1944 /* With update after bind we can't attach bo's to the command buffer
1945 * from the descriptor set anymore, so we have to use a global BO list.
1946 */
1947 device->use_global_bo_list =
1948 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1949 device->enabled_extensions.EXT_descriptor_indexing ||
1950 device->enabled_extensions.EXT_buffer_device_address;
1951
1952 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1953 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1954
1955 mtx_init(&device->shader_slab_mutex, mtx_plain);
1956 list_inithead(&device->shader_slabs);
1957
1958 radv_bo_list_init(&device->bo_list);
1959
1960 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1961 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1962 uint32_t qfi = queue_create->queueFamilyIndex;
1963 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1964 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1965
1966 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1967
1968 device->queues[qfi] = vk_alloc(&device->alloc,
1969 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1970 if (!device->queues[qfi]) {
1971 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1972 goto fail;
1973 }
1974
1975 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1976
1977 device->queue_count[qfi] = queue_create->queueCount;
1978
1979 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1980 result = radv_queue_init(device, &device->queues[qfi][q],
1981 qfi, q, queue_create->flags,
1982 global_priority);
1983 if (result != VK_SUCCESS)
1984 goto fail;
1985 }
1986 }
1987
1988 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1989 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1990
1991 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
1992 device->dfsm_allowed = device->pbb_allowed &&
1993 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
1994
1995 #ifdef ANDROID
1996 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1997 #endif
1998
1999 /* The maximum number of scratch waves. Scratch space isn't divided
2000 * evenly between CUs. The number is only a function of the number of CUs.
2001 * We can decrease the constant to decrease the scratch buffer size.
2002 *
2003 * sctx->scratch_waves must be >= the maximum possible size of
2004 * 1 threadgroup, so that the hw doesn't hang from being unable
2005 * to start any.
2006 *
2007 * The recommended value is 4 per CU at most. Higher numbers don't
2008 * bring much benefit, but they still occupy chip resources (think
2009 * async compute). I've seen ~2% performance difference between 4 and 32.
2010 */
2011 uint32_t max_threads_per_block = 2048;
2012 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2013 max_threads_per_block / 64);
2014
2015 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
2016 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
2017
2018 if (device->physical_device->rad_info.chip_class >= GFX7) {
2019 /* If the KMD allows it (there is a KMD hw register for it),
2020 * allow launching waves out-of-order.
2021 */
2022 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2023 }
2024
2025 radv_device_init_gs_info(device);
2026
2027 device->tess_offchip_block_dw_size =
2028 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2029
2030 if (getenv("RADV_TRACE_FILE")) {
2031 const char *filename = getenv("RADV_TRACE_FILE");
2032
2033 keep_shader_info = true;
2034
2035 if (!radv_init_trace(device))
2036 goto fail;
2037
2038 fprintf(stderr, "*****************************************************************************\n");
2039 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2040 fprintf(stderr, "*****************************************************************************\n");
2041
2042 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2043 radv_dump_enabled_options(device, stderr);
2044 }
2045
2046 device->keep_shader_info = keep_shader_info;
2047
2048 result = radv_device_init_meta(device);
2049 if (result != VK_SUCCESS)
2050 goto fail;
2051
2052 radv_device_init_msaa(device);
2053
2054 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2055 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2056 switch (family) {
2057 case RADV_QUEUE_GENERAL:
2058 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2059 if (device->physical_device->rad_info.drm_minor < 6) {
2060 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2061 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2062 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2063 }
2064 break;
2065 case RADV_QUEUE_COMPUTE:
2066 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2067 radeon_emit(device->empty_cs[family], 0);
2068 break;
2069 }
2070 device->ws->cs_finalize(device->empty_cs[family]);
2071 }
2072
2073 if (device->physical_device->rad_info.chip_class >= GFX7)
2074 cik_create_gfx_config(device);
2075
2076 VkPipelineCacheCreateInfo ci;
2077 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2078 ci.pNext = NULL;
2079 ci.flags = 0;
2080 ci.pInitialData = NULL;
2081 ci.initialDataSize = 0;
2082 VkPipelineCache pc;
2083 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2084 &ci, NULL, &pc);
2085 if (result != VK_SUCCESS)
2086 goto fail_meta;
2087
2088 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2089
2090 device->force_aniso =
2091 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2092 if (device->force_aniso >= 0) {
2093 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2094 1 << util_logbase2(device->force_aniso));
2095 }
2096
2097 *pDevice = radv_device_to_handle(device);
2098 return VK_SUCCESS;
2099
2100 fail_meta:
2101 radv_device_finish_meta(device);
2102 fail:
2103 radv_bo_list_finish(&device->bo_list);
2104
2105 if (device->trace_bo)
2106 device->ws->buffer_destroy(device->trace_bo);
2107
2108 if (device->gfx_init)
2109 device->ws->buffer_destroy(device->gfx_init);
2110
2111 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2112 for (unsigned q = 0; q < device->queue_count[i]; q++)
2113 radv_queue_finish(&device->queues[i][q]);
2114 if (device->queue_count[i])
2115 vk_free(&device->alloc, device->queues[i]);
2116 }
2117
2118 vk_free(&device->alloc, device);
2119 return result;
2120 }
2121
2122 void radv_DestroyDevice(
2123 VkDevice _device,
2124 const VkAllocationCallbacks* pAllocator)
2125 {
2126 RADV_FROM_HANDLE(radv_device, device, _device);
2127
2128 if (!device)
2129 return;
2130
2131 if (device->trace_bo)
2132 device->ws->buffer_destroy(device->trace_bo);
2133
2134 if (device->gfx_init)
2135 device->ws->buffer_destroy(device->gfx_init);
2136
2137 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2138 for (unsigned q = 0; q < device->queue_count[i]; q++)
2139 radv_queue_finish(&device->queues[i][q]);
2140 if (device->queue_count[i])
2141 vk_free(&device->alloc, device->queues[i]);
2142 if (device->empty_cs[i])
2143 device->ws->cs_destroy(device->empty_cs[i]);
2144 }
2145 radv_device_finish_meta(device);
2146
2147 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2148 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2149
2150 radv_destroy_shader_slabs(device);
2151
2152 radv_bo_list_finish(&device->bo_list);
2153 vk_free(&device->alloc, device);
2154 }
2155
2156 VkResult radv_EnumerateInstanceLayerProperties(
2157 uint32_t* pPropertyCount,
2158 VkLayerProperties* pProperties)
2159 {
2160 if (pProperties == NULL) {
2161 *pPropertyCount = 0;
2162 return VK_SUCCESS;
2163 }
2164
2165 /* None supported at this time */
2166 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2167 }
2168
2169 VkResult radv_EnumerateDeviceLayerProperties(
2170 VkPhysicalDevice physicalDevice,
2171 uint32_t* pPropertyCount,
2172 VkLayerProperties* pProperties)
2173 {
2174 if (pProperties == NULL) {
2175 *pPropertyCount = 0;
2176 return VK_SUCCESS;
2177 }
2178
2179 /* None supported at this time */
2180 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2181 }
2182
2183 void radv_GetDeviceQueue2(
2184 VkDevice _device,
2185 const VkDeviceQueueInfo2* pQueueInfo,
2186 VkQueue* pQueue)
2187 {
2188 RADV_FROM_HANDLE(radv_device, device, _device);
2189 struct radv_queue *queue;
2190
2191 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2192 if (pQueueInfo->flags != queue->flags) {
2193 /* From the Vulkan 1.1.70 spec:
2194 *
2195 * "The queue returned by vkGetDeviceQueue2 must have the same
2196 * flags value from this structure as that used at device
2197 * creation time in a VkDeviceQueueCreateInfo instance. If no
2198 * matching flags were specified at device creation time then
2199 * pQueue will return VK_NULL_HANDLE."
2200 */
2201 *pQueue = VK_NULL_HANDLE;
2202 return;
2203 }
2204
2205 *pQueue = radv_queue_to_handle(queue);
2206 }
2207
2208 void radv_GetDeviceQueue(
2209 VkDevice _device,
2210 uint32_t queueFamilyIndex,
2211 uint32_t queueIndex,
2212 VkQueue* pQueue)
2213 {
2214 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2215 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2216 .queueFamilyIndex = queueFamilyIndex,
2217 .queueIndex = queueIndex
2218 };
2219
2220 radv_GetDeviceQueue2(_device, &info, pQueue);
2221 }
2222
2223 static void
2224 fill_geom_tess_rings(struct radv_queue *queue,
2225 uint32_t *map,
2226 bool add_sample_positions,
2227 uint32_t esgs_ring_size,
2228 struct radeon_winsys_bo *esgs_ring_bo,
2229 uint32_t gsvs_ring_size,
2230 struct radeon_winsys_bo *gsvs_ring_bo,
2231 uint32_t tess_factor_ring_size,
2232 uint32_t tess_offchip_ring_offset,
2233 uint32_t tess_offchip_ring_size,
2234 struct radeon_winsys_bo *tess_rings_bo)
2235 {
2236 uint32_t *desc = &map[4];
2237
2238 if (esgs_ring_bo) {
2239 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2240
2241 /* stride 0, num records - size, add tid, swizzle, elsize4,
2242 index stride 64 */
2243 desc[0] = esgs_va;
2244 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2245 S_008F04_SWIZZLE_ENABLE(true);
2246 desc[2] = esgs_ring_size;
2247 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2248 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2249 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2250 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2251 S_008F0C_INDEX_STRIDE(3) |
2252 S_008F0C_ADD_TID_ENABLE(1);
2253
2254 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2255 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2256 S_008F0C_OOB_SELECT(2) |
2257 S_008F0C_RESOURCE_LEVEL(1);
2258 } else {
2259 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2260 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2261 S_008F0C_ELEMENT_SIZE(1);
2262 }
2263
2264 /* GS entry for ES->GS ring */
2265 /* stride 0, num records - size, elsize0,
2266 index stride 0 */
2267 desc[4] = esgs_va;
2268 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2269 desc[6] = esgs_ring_size;
2270 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2271 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2272 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2273 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2274
2275 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2276 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2277 S_008F0C_OOB_SELECT(2) |
2278 S_008F0C_RESOURCE_LEVEL(1);
2279 } else {
2280 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2281 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2282 }
2283 }
2284
2285 desc += 8;
2286
2287 if (gsvs_ring_bo) {
2288 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2289
2290 /* VS entry for GS->VS ring */
2291 /* stride 0, num records - size, elsize0,
2292 index stride 0 */
2293 desc[0] = gsvs_va;
2294 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2295 desc[2] = gsvs_ring_size;
2296 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2297 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2298 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2299 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2300
2301 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2302 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2303 S_008F0C_OOB_SELECT(2) |
2304 S_008F0C_RESOURCE_LEVEL(1);
2305 } else {
2306 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2307 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2308 }
2309
2310 /* stride gsvs_itemsize, num records 64
2311 elsize 4, index stride 16 */
2312 /* shader will patch stride and desc[2] */
2313 desc[4] = gsvs_va;
2314 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2315 S_008F04_SWIZZLE_ENABLE(1);
2316 desc[6] = 0;
2317 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2318 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2319 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2320 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2321 S_008F0C_INDEX_STRIDE(1) |
2322 S_008F0C_ADD_TID_ENABLE(true);
2323
2324 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2325 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2326 S_008F0C_OOB_SELECT(2) |
2327 S_008F0C_RESOURCE_LEVEL(1);
2328 } else {
2329 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2330 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2331 S_008F0C_ELEMENT_SIZE(1);
2332 }
2333
2334 }
2335
2336 desc += 8;
2337
2338 if (tess_rings_bo) {
2339 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2340 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2341
2342 desc[0] = tess_va;
2343 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2344 desc[2] = tess_factor_ring_size;
2345 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2346 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2347 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2348 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2349
2350 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2351 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2352 S_008F0C_OOB_SELECT(3) |
2353 S_008F0C_RESOURCE_LEVEL(1);
2354 } else {
2355 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2356 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2357 }
2358
2359 desc[4] = tess_offchip_va;
2360 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2361 desc[6] = tess_offchip_ring_size;
2362 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2363 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2364 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2365 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2366
2367 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2368 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2369 S_008F0C_OOB_SELECT(3) |
2370 S_008F0C_RESOURCE_LEVEL(1);
2371 } else {
2372 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2373 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2374 }
2375 }
2376
2377 desc += 8;
2378
2379 if (add_sample_positions) {
2380 /* add sample positions after all rings */
2381 memcpy(desc, queue->device->sample_locations_1x, 8);
2382 desc += 2;
2383 memcpy(desc, queue->device->sample_locations_2x, 16);
2384 desc += 4;
2385 memcpy(desc, queue->device->sample_locations_4x, 32);
2386 desc += 8;
2387 memcpy(desc, queue->device->sample_locations_8x, 64);
2388 }
2389 }
2390
2391 static unsigned
2392 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2393 {
2394 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2395 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2396 device->physical_device->rad_info.family != CHIP_STONEY;
2397 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2398 unsigned max_offchip_buffers;
2399 unsigned offchip_granularity;
2400 unsigned hs_offchip_param;
2401
2402 /*
2403 * Per RadeonSI:
2404 * This must be one less than the maximum number due to a hw limitation.
2405 * Various hardware bugs need thGFX7
2406 *
2407 * Per AMDVLK:
2408 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2409 * Gfx7 should limit max_offchip_buffers to 508
2410 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2411 *
2412 * Follow AMDVLK here.
2413 */
2414 if (device->physical_device->rad_info.chip_class >= GFX10) {
2415 max_offchip_buffers_per_se = 256;
2416 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2417 device->physical_device->rad_info.chip_class == GFX7 ||
2418 device->physical_device->rad_info.chip_class == GFX6)
2419 --max_offchip_buffers_per_se;
2420
2421 max_offchip_buffers = max_offchip_buffers_per_se *
2422 device->physical_device->rad_info.max_se;
2423
2424 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2425 * around by setting 4K granularity.
2426 */
2427 if (device->tess_offchip_block_dw_size == 4096) {
2428 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2429 offchip_granularity = V_03093C_X_4K_DWORDS;
2430 } else {
2431 assert(device->tess_offchip_block_dw_size == 8192);
2432 offchip_granularity = V_03093C_X_8K_DWORDS;
2433 }
2434
2435 switch (device->physical_device->rad_info.chip_class) {
2436 case GFX6:
2437 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2438 break;
2439 case GFX7:
2440 case GFX8:
2441 case GFX9:
2442 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2443 break;
2444 case GFX10:
2445 break;
2446 default:
2447 break;
2448 }
2449
2450 *max_offchip_buffers_p = max_offchip_buffers;
2451 if (device->physical_device->rad_info.chip_class >= GFX7) {
2452 if (device->physical_device->rad_info.chip_class >= GFX8)
2453 --max_offchip_buffers;
2454 hs_offchip_param =
2455 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2456 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2457 } else {
2458 hs_offchip_param =
2459 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2460 }
2461 return hs_offchip_param;
2462 }
2463
2464 static void
2465 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2466 struct radeon_winsys_bo *esgs_ring_bo,
2467 uint32_t esgs_ring_size,
2468 struct radeon_winsys_bo *gsvs_ring_bo,
2469 uint32_t gsvs_ring_size)
2470 {
2471 if (!esgs_ring_bo && !gsvs_ring_bo)
2472 return;
2473
2474 if (esgs_ring_bo)
2475 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2476
2477 if (gsvs_ring_bo)
2478 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2479
2480 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2481 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2482 radeon_emit(cs, esgs_ring_size >> 8);
2483 radeon_emit(cs, gsvs_ring_size >> 8);
2484 } else {
2485 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2486 radeon_emit(cs, esgs_ring_size >> 8);
2487 radeon_emit(cs, gsvs_ring_size >> 8);
2488 }
2489 }
2490
2491 static void
2492 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2493 unsigned hs_offchip_param, unsigned tf_ring_size,
2494 struct radeon_winsys_bo *tess_rings_bo)
2495 {
2496 uint64_t tf_va;
2497
2498 if (!tess_rings_bo)
2499 return;
2500
2501 tf_va = radv_buffer_get_va(tess_rings_bo);
2502
2503 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2504
2505 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2506 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2507 S_030938_SIZE(tf_ring_size / 4));
2508 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2509 tf_va >> 8);
2510
2511 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2512 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2513 S_030984_BASE_HI(tf_va >> 40));
2514 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2515 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2516 S_030944_BASE_HI(tf_va >> 40));
2517 }
2518 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2519 hs_offchip_param);
2520 } else {
2521 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2522 S_008988_SIZE(tf_ring_size / 4));
2523 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2524 tf_va >> 8);
2525 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2526 hs_offchip_param);
2527 }
2528 }
2529
2530 static void
2531 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2532 struct radeon_winsys_bo *compute_scratch_bo)
2533 {
2534 uint64_t scratch_va;
2535
2536 if (!compute_scratch_bo)
2537 return;
2538
2539 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2540
2541 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2542
2543 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2544 radeon_emit(cs, scratch_va);
2545 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2546 S_008F04_SWIZZLE_ENABLE(1));
2547 }
2548
2549 static void
2550 radv_emit_global_shader_pointers(struct radv_queue *queue,
2551 struct radeon_cmdbuf *cs,
2552 struct radeon_winsys_bo *descriptor_bo)
2553 {
2554 uint64_t va;
2555
2556 if (!descriptor_bo)
2557 return;
2558
2559 va = radv_buffer_get_va(descriptor_bo);
2560
2561 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2562
2563 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2564 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2565 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2566 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2567 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2568
2569 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2570 radv_emit_shader_pointer(queue->device, cs, regs[i],
2571 va, true);
2572 }
2573 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2574 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2575 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2576 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2577 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2578
2579 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2580 radv_emit_shader_pointer(queue->device, cs, regs[i],
2581 va, true);
2582 }
2583 } else {
2584 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2585 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2586 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2587 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2588 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2589 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2590
2591 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2592 radv_emit_shader_pointer(queue->device, cs, regs[i],
2593 va, true);
2594 }
2595 }
2596 }
2597
2598 static void
2599 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2600 {
2601 struct radv_device *device = queue->device;
2602
2603 if (device->gfx_init) {
2604 uint64_t va = radv_buffer_get_va(device->gfx_init);
2605
2606 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2607 radeon_emit(cs, va);
2608 radeon_emit(cs, va >> 32);
2609 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2610
2611 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2612 } else {
2613 struct radv_physical_device *physical_device = device->physical_device;
2614 si_emit_graphics(physical_device, cs);
2615 }
2616 }
2617
2618 static void
2619 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2620 {
2621 struct radv_physical_device *physical_device = queue->device->physical_device;
2622 si_emit_compute(physical_device, cs);
2623 }
2624
2625 static VkResult
2626 radv_get_preamble_cs(struct radv_queue *queue,
2627 uint32_t scratch_size,
2628 uint32_t compute_scratch_size,
2629 uint32_t esgs_ring_size,
2630 uint32_t gsvs_ring_size,
2631 bool needs_tess_rings,
2632 bool needs_gds,
2633 bool needs_sample_positions,
2634 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2635 struct radeon_cmdbuf **initial_preamble_cs,
2636 struct radeon_cmdbuf **continue_preamble_cs)
2637 {
2638 struct radeon_winsys_bo *scratch_bo = NULL;
2639 struct radeon_winsys_bo *descriptor_bo = NULL;
2640 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2641 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2642 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2643 struct radeon_winsys_bo *tess_rings_bo = NULL;
2644 struct radeon_winsys_bo *gds_bo = NULL;
2645 struct radeon_winsys_bo *gds_oa_bo = NULL;
2646 struct radeon_cmdbuf *dest_cs[3] = {0};
2647 bool add_tess_rings = false, add_gds = false, add_sample_positions = false;
2648 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2649 unsigned max_offchip_buffers;
2650 unsigned hs_offchip_param = 0;
2651 unsigned tess_offchip_ring_offset;
2652 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2653 if (!queue->has_tess_rings) {
2654 if (needs_tess_rings)
2655 add_tess_rings = true;
2656 }
2657 if (!queue->has_gds) {
2658 if (needs_gds)
2659 add_gds = true;
2660 }
2661 if (!queue->has_sample_positions) {
2662 if (needs_sample_positions)
2663 add_sample_positions = true;
2664 }
2665 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2666 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2667 &max_offchip_buffers);
2668 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2669 tess_offchip_ring_size = max_offchip_buffers *
2670 queue->device->tess_offchip_block_dw_size * 4;
2671
2672 if (scratch_size <= queue->scratch_size &&
2673 compute_scratch_size <= queue->compute_scratch_size &&
2674 esgs_ring_size <= queue->esgs_ring_size &&
2675 gsvs_ring_size <= queue->gsvs_ring_size &&
2676 !add_tess_rings && !add_gds && !add_sample_positions &&
2677 queue->initial_preamble_cs) {
2678 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2679 *initial_preamble_cs = queue->initial_preamble_cs;
2680 *continue_preamble_cs = queue->continue_preamble_cs;
2681 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2682 *continue_preamble_cs = NULL;
2683 return VK_SUCCESS;
2684 }
2685
2686 if (scratch_size > queue->scratch_size) {
2687 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2688 scratch_size,
2689 4096,
2690 RADEON_DOMAIN_VRAM,
2691 ring_bo_flags,
2692 RADV_BO_PRIORITY_SCRATCH);
2693 if (!scratch_bo)
2694 goto fail;
2695 } else
2696 scratch_bo = queue->scratch_bo;
2697
2698 if (compute_scratch_size > queue->compute_scratch_size) {
2699 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2700 compute_scratch_size,
2701 4096,
2702 RADEON_DOMAIN_VRAM,
2703 ring_bo_flags,
2704 RADV_BO_PRIORITY_SCRATCH);
2705 if (!compute_scratch_bo)
2706 goto fail;
2707
2708 } else
2709 compute_scratch_bo = queue->compute_scratch_bo;
2710
2711 if (esgs_ring_size > queue->esgs_ring_size) {
2712 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2713 esgs_ring_size,
2714 4096,
2715 RADEON_DOMAIN_VRAM,
2716 ring_bo_flags,
2717 RADV_BO_PRIORITY_SCRATCH);
2718 if (!esgs_ring_bo)
2719 goto fail;
2720 } else {
2721 esgs_ring_bo = queue->esgs_ring_bo;
2722 esgs_ring_size = queue->esgs_ring_size;
2723 }
2724
2725 if (gsvs_ring_size > queue->gsvs_ring_size) {
2726 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2727 gsvs_ring_size,
2728 4096,
2729 RADEON_DOMAIN_VRAM,
2730 ring_bo_flags,
2731 RADV_BO_PRIORITY_SCRATCH);
2732 if (!gsvs_ring_bo)
2733 goto fail;
2734 } else {
2735 gsvs_ring_bo = queue->gsvs_ring_bo;
2736 gsvs_ring_size = queue->gsvs_ring_size;
2737 }
2738
2739 if (add_tess_rings) {
2740 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2741 tess_offchip_ring_offset + tess_offchip_ring_size,
2742 256,
2743 RADEON_DOMAIN_VRAM,
2744 ring_bo_flags,
2745 RADV_BO_PRIORITY_SCRATCH);
2746 if (!tess_rings_bo)
2747 goto fail;
2748 } else {
2749 tess_rings_bo = queue->tess_rings_bo;
2750 }
2751
2752 if (add_gds) {
2753 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
2754
2755 /* 4 streamout GDS counters.
2756 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
2757 */
2758 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
2759 256, 4,
2760 RADEON_DOMAIN_GDS,
2761 ring_bo_flags,
2762 RADV_BO_PRIORITY_SCRATCH);
2763 if (!gds_bo)
2764 goto fail;
2765
2766 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
2767 4, 1,
2768 RADEON_DOMAIN_OA,
2769 ring_bo_flags,
2770 RADV_BO_PRIORITY_SCRATCH);
2771 if (!gds_oa_bo)
2772 goto fail;
2773 } else {
2774 gds_bo = queue->gds_bo;
2775 gds_oa_bo = queue->gds_oa_bo;
2776 }
2777
2778 if (scratch_bo != queue->scratch_bo ||
2779 esgs_ring_bo != queue->esgs_ring_bo ||
2780 gsvs_ring_bo != queue->gsvs_ring_bo ||
2781 tess_rings_bo != queue->tess_rings_bo ||
2782 add_sample_positions) {
2783 uint32_t size = 0;
2784 if (gsvs_ring_bo || esgs_ring_bo ||
2785 tess_rings_bo || add_sample_positions) {
2786 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2787 if (add_sample_positions)
2788 size += 128; /* 64+32+16+8 = 120 bytes */
2789 }
2790 else if (scratch_bo)
2791 size = 8; /* 2 dword */
2792
2793 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2794 size,
2795 4096,
2796 RADEON_DOMAIN_VRAM,
2797 RADEON_FLAG_CPU_ACCESS |
2798 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2799 RADEON_FLAG_READ_ONLY,
2800 RADV_BO_PRIORITY_DESCRIPTOR);
2801 if (!descriptor_bo)
2802 goto fail;
2803 } else
2804 descriptor_bo = queue->descriptor_bo;
2805
2806 if (descriptor_bo != queue->descriptor_bo) {
2807 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2808
2809 if (scratch_bo) {
2810 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2811 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2812 S_008F04_SWIZZLE_ENABLE(1);
2813 map[0] = scratch_va;
2814 map[1] = rsrc1;
2815 }
2816
2817 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2818 fill_geom_tess_rings(queue, map, add_sample_positions,
2819 esgs_ring_size, esgs_ring_bo,
2820 gsvs_ring_size, gsvs_ring_bo,
2821 tess_factor_ring_size,
2822 tess_offchip_ring_offset,
2823 tess_offchip_ring_size,
2824 tess_rings_bo);
2825
2826 queue->device->ws->buffer_unmap(descriptor_bo);
2827 }
2828
2829 for(int i = 0; i < 3; ++i) {
2830 struct radeon_cmdbuf *cs = NULL;
2831 cs = queue->device->ws->cs_create(queue->device->ws,
2832 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2833 if (!cs)
2834 goto fail;
2835
2836 dest_cs[i] = cs;
2837
2838 if (scratch_bo)
2839 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2840
2841 /* Emit initial configuration. */
2842 switch (queue->queue_family_index) {
2843 case RADV_QUEUE_GENERAL:
2844 radv_init_graphics_state(cs, queue);
2845 break;
2846 case RADV_QUEUE_COMPUTE:
2847 radv_init_compute_state(cs, queue);
2848 break;
2849 case RADV_QUEUE_TRANSFER:
2850 break;
2851 }
2852
2853 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2854 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2855 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2856
2857 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2858 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2859 }
2860
2861 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2862 gsvs_ring_bo, gsvs_ring_size);
2863 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2864 tess_factor_ring_size, tess_rings_bo);
2865 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2866 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2867
2868 if (gds_bo)
2869 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
2870 if (gds_oa_bo)
2871 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
2872
2873 if (i == 0) {
2874 si_cs_emit_cache_flush(cs,
2875 queue->device->physical_device->rad_info.chip_class,
2876 NULL, 0,
2877 queue->queue_family_index == RING_COMPUTE &&
2878 queue->device->physical_device->rad_info.chip_class >= GFX7,
2879 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2880 RADV_CMD_FLAG_INV_ICACHE |
2881 RADV_CMD_FLAG_INV_SCACHE |
2882 RADV_CMD_FLAG_INV_VCACHE |
2883 RADV_CMD_FLAG_INV_L2 |
2884 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2885 } else if (i == 1) {
2886 si_cs_emit_cache_flush(cs,
2887 queue->device->physical_device->rad_info.chip_class,
2888 NULL, 0,
2889 queue->queue_family_index == RING_COMPUTE &&
2890 queue->device->physical_device->rad_info.chip_class >= GFX7,
2891 RADV_CMD_FLAG_INV_ICACHE |
2892 RADV_CMD_FLAG_INV_SCACHE |
2893 RADV_CMD_FLAG_INV_VCACHE |
2894 RADV_CMD_FLAG_INV_L2 |
2895 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2896 }
2897
2898 if (!queue->device->ws->cs_finalize(cs))
2899 goto fail;
2900 }
2901
2902 if (queue->initial_full_flush_preamble_cs)
2903 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2904
2905 if (queue->initial_preamble_cs)
2906 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2907
2908 if (queue->continue_preamble_cs)
2909 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2910
2911 queue->initial_full_flush_preamble_cs = dest_cs[0];
2912 queue->initial_preamble_cs = dest_cs[1];
2913 queue->continue_preamble_cs = dest_cs[2];
2914
2915 if (scratch_bo != queue->scratch_bo) {
2916 if (queue->scratch_bo)
2917 queue->device->ws->buffer_destroy(queue->scratch_bo);
2918 queue->scratch_bo = scratch_bo;
2919 queue->scratch_size = scratch_size;
2920 }
2921
2922 if (compute_scratch_bo != queue->compute_scratch_bo) {
2923 if (queue->compute_scratch_bo)
2924 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2925 queue->compute_scratch_bo = compute_scratch_bo;
2926 queue->compute_scratch_size = compute_scratch_size;
2927 }
2928
2929 if (esgs_ring_bo != queue->esgs_ring_bo) {
2930 if (queue->esgs_ring_bo)
2931 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2932 queue->esgs_ring_bo = esgs_ring_bo;
2933 queue->esgs_ring_size = esgs_ring_size;
2934 }
2935
2936 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2937 if (queue->gsvs_ring_bo)
2938 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2939 queue->gsvs_ring_bo = gsvs_ring_bo;
2940 queue->gsvs_ring_size = gsvs_ring_size;
2941 }
2942
2943 if (tess_rings_bo != queue->tess_rings_bo) {
2944 queue->tess_rings_bo = tess_rings_bo;
2945 queue->has_tess_rings = true;
2946 }
2947
2948 if (gds_bo != queue->gds_bo) {
2949 queue->gds_bo = gds_bo;
2950 queue->has_gds = true;
2951 }
2952
2953 if (gds_oa_bo != queue->gds_oa_bo)
2954 queue->gds_oa_bo = gds_oa_bo;
2955
2956 if (descriptor_bo != queue->descriptor_bo) {
2957 if (queue->descriptor_bo)
2958 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2959
2960 queue->descriptor_bo = descriptor_bo;
2961 }
2962
2963 if (add_sample_positions)
2964 queue->has_sample_positions = true;
2965
2966 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2967 *initial_preamble_cs = queue->initial_preamble_cs;
2968 *continue_preamble_cs = queue->continue_preamble_cs;
2969 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2970 *continue_preamble_cs = NULL;
2971 return VK_SUCCESS;
2972 fail:
2973 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2974 if (dest_cs[i])
2975 queue->device->ws->cs_destroy(dest_cs[i]);
2976 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2977 queue->device->ws->buffer_destroy(descriptor_bo);
2978 if (scratch_bo && scratch_bo != queue->scratch_bo)
2979 queue->device->ws->buffer_destroy(scratch_bo);
2980 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2981 queue->device->ws->buffer_destroy(compute_scratch_bo);
2982 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2983 queue->device->ws->buffer_destroy(esgs_ring_bo);
2984 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2985 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2986 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2987 queue->device->ws->buffer_destroy(tess_rings_bo);
2988 if (gds_bo && gds_bo != queue->gds_bo)
2989 queue->device->ws->buffer_destroy(gds_bo);
2990 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
2991 queue->device->ws->buffer_destroy(gds_oa_bo);
2992
2993 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2994 }
2995
2996 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2997 struct radv_winsys_sem_counts *counts,
2998 int num_sems,
2999 const VkSemaphore *sems,
3000 VkFence _fence,
3001 bool reset_temp)
3002 {
3003 int syncobj_idx = 0, sem_idx = 0;
3004
3005 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3006 return VK_SUCCESS;
3007
3008 for (uint32_t i = 0; i < num_sems; i++) {
3009 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3010
3011 if (sem->temp_syncobj || sem->syncobj)
3012 counts->syncobj_count++;
3013 else
3014 counts->sem_count++;
3015 }
3016
3017 if (_fence != VK_NULL_HANDLE) {
3018 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3019 if (fence->temp_syncobj || fence->syncobj)
3020 counts->syncobj_count++;
3021 }
3022
3023 if (counts->syncobj_count) {
3024 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3025 if (!counts->syncobj)
3026 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3027 }
3028
3029 if (counts->sem_count) {
3030 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3031 if (!counts->sem) {
3032 free(counts->syncobj);
3033 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3034 }
3035 }
3036
3037 for (uint32_t i = 0; i < num_sems; i++) {
3038 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3039
3040 if (sem->temp_syncobj) {
3041 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
3042 }
3043 else if (sem->syncobj)
3044 counts->syncobj[syncobj_idx++] = sem->syncobj;
3045 else {
3046 assert(sem->sem);
3047 counts->sem[sem_idx++] = sem->sem;
3048 }
3049 }
3050
3051 if (_fence != VK_NULL_HANDLE) {
3052 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3053 if (fence->temp_syncobj)
3054 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
3055 else if (fence->syncobj)
3056 counts->syncobj[syncobj_idx++] = fence->syncobj;
3057 }
3058
3059 return VK_SUCCESS;
3060 }
3061
3062 static void
3063 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3064 {
3065 free(sem_info->wait.syncobj);
3066 free(sem_info->wait.sem);
3067 free(sem_info->signal.syncobj);
3068 free(sem_info->signal.sem);
3069 }
3070
3071
3072 static void radv_free_temp_syncobjs(struct radv_device *device,
3073 int num_sems,
3074 const VkSemaphore *sems)
3075 {
3076 for (uint32_t i = 0; i < num_sems; i++) {
3077 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3078
3079 if (sem->temp_syncobj) {
3080 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
3081 sem->temp_syncobj = 0;
3082 }
3083 }
3084 }
3085
3086 static VkResult
3087 radv_alloc_sem_info(struct radv_instance *instance,
3088 struct radv_winsys_sem_info *sem_info,
3089 int num_wait_sems,
3090 const VkSemaphore *wait_sems,
3091 int num_signal_sems,
3092 const VkSemaphore *signal_sems,
3093 VkFence fence)
3094 {
3095 VkResult ret;
3096 memset(sem_info, 0, sizeof(*sem_info));
3097
3098 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3099 if (ret)
3100 return ret;
3101 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3102 if (ret)
3103 radv_free_sem_info(sem_info);
3104
3105 /* caller can override these */
3106 sem_info->cs_emit_wait = true;
3107 sem_info->cs_emit_signal = true;
3108 return ret;
3109 }
3110
3111 /* Signals fence as soon as all the work currently put on queue is done. */
3112 static VkResult radv_signal_fence(struct radv_queue *queue,
3113 struct radv_fence *fence)
3114 {
3115 int ret;
3116 VkResult result;
3117 struct radv_winsys_sem_info sem_info;
3118
3119 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3120 radv_fence_to_handle(fence));
3121 if (result != VK_SUCCESS)
3122 return result;
3123
3124 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3125 &queue->device->empty_cs[queue->queue_family_index],
3126 1, NULL, NULL, &sem_info, NULL,
3127 false, fence->fence);
3128 radv_free_sem_info(&sem_info);
3129
3130 if (ret)
3131 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3132
3133 return VK_SUCCESS;
3134 }
3135
3136 VkResult radv_QueueSubmit(
3137 VkQueue _queue,
3138 uint32_t submitCount,
3139 const VkSubmitInfo* pSubmits,
3140 VkFence _fence)
3141 {
3142 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3143 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3144 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3145 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3146 int ret;
3147 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3148 uint32_t scratch_size = 0;
3149 uint32_t compute_scratch_size = 0;
3150 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3151 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3152 VkResult result;
3153 bool fence_emitted = false;
3154 bool tess_rings_needed = false;
3155 bool gds_needed = false;
3156 bool sample_positions_needed = false;
3157
3158 /* Do this first so failing to allocate scratch buffers can't result in
3159 * partially executed submissions. */
3160 for (uint32_t i = 0; i < submitCount; i++) {
3161 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3162 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3163 pSubmits[i].pCommandBuffers[j]);
3164
3165 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3166 compute_scratch_size = MAX2(compute_scratch_size,
3167 cmd_buffer->compute_scratch_size_needed);
3168 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3169 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3170 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3171 gds_needed |= cmd_buffer->gds_needed;
3172 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3173 }
3174 }
3175
3176 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3177 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3178 gds_needed, sample_positions_needed,
3179 &initial_flush_preamble_cs,
3180 &initial_preamble_cs, &continue_preamble_cs);
3181 if (result != VK_SUCCESS)
3182 return result;
3183
3184 for (uint32_t i = 0; i < submitCount; i++) {
3185 struct radeon_cmdbuf **cs_array;
3186 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3187 bool can_patch = true;
3188 uint32_t advance;
3189 struct radv_winsys_sem_info sem_info;
3190
3191 result = radv_alloc_sem_info(queue->device->instance,
3192 &sem_info,
3193 pSubmits[i].waitSemaphoreCount,
3194 pSubmits[i].pWaitSemaphores,
3195 pSubmits[i].signalSemaphoreCount,
3196 pSubmits[i].pSignalSemaphores,
3197 _fence);
3198 if (result != VK_SUCCESS)
3199 return result;
3200
3201 if (!pSubmits[i].commandBufferCount) {
3202 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3203 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3204 &queue->device->empty_cs[queue->queue_family_index],
3205 1, NULL, NULL,
3206 &sem_info, NULL,
3207 false, base_fence);
3208 if (ret) {
3209 radv_loge("failed to submit CS %d\n", i);
3210 abort();
3211 }
3212 fence_emitted = true;
3213 }
3214 radv_free_sem_info(&sem_info);
3215 continue;
3216 }
3217
3218 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3219 (pSubmits[i].commandBufferCount));
3220
3221 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3222 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3223 pSubmits[i].pCommandBuffers[j]);
3224 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3225
3226 cs_array[j] = cmd_buffer->cs;
3227 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3228 can_patch = false;
3229
3230 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3231 }
3232
3233 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3234 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3235 const struct radv_winsys_bo_list *bo_list = NULL;
3236
3237 advance = MIN2(max_cs_submission,
3238 pSubmits[i].commandBufferCount - j);
3239
3240 if (queue->device->trace_bo)
3241 *queue->device->trace_id_ptr = 0;
3242
3243 sem_info.cs_emit_wait = j == 0;
3244 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3245
3246 if (unlikely(queue->device->use_global_bo_list)) {
3247 pthread_mutex_lock(&queue->device->bo_list.mutex);
3248 bo_list = &queue->device->bo_list.list;
3249 }
3250
3251 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3252 advance, initial_preamble, continue_preamble_cs,
3253 &sem_info, bo_list,
3254 can_patch, base_fence);
3255
3256 if (unlikely(queue->device->use_global_bo_list))
3257 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3258
3259 if (ret) {
3260 radv_loge("failed to submit CS %d\n", i);
3261 abort();
3262 }
3263 fence_emitted = true;
3264 if (queue->device->trace_bo) {
3265 radv_check_gpu_hangs(queue, cs_array[j]);
3266 }
3267 }
3268
3269 radv_free_temp_syncobjs(queue->device,
3270 pSubmits[i].waitSemaphoreCount,
3271 pSubmits[i].pWaitSemaphores);
3272 radv_free_sem_info(&sem_info);
3273 free(cs_array);
3274 }
3275
3276 if (fence) {
3277 if (!fence_emitted) {
3278 result = radv_signal_fence(queue, fence);
3279 if (result != VK_SUCCESS)
3280 return result;
3281 }
3282 }
3283
3284 return VK_SUCCESS;
3285 }
3286
3287 VkResult radv_QueueWaitIdle(
3288 VkQueue _queue)
3289 {
3290 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3291
3292 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3293 radv_queue_family_to_ring(queue->queue_family_index),
3294 queue->queue_idx);
3295 return VK_SUCCESS;
3296 }
3297
3298 VkResult radv_DeviceWaitIdle(
3299 VkDevice _device)
3300 {
3301 RADV_FROM_HANDLE(radv_device, device, _device);
3302
3303 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3304 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3305 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3306 }
3307 }
3308 return VK_SUCCESS;
3309 }
3310
3311 VkResult radv_EnumerateInstanceExtensionProperties(
3312 const char* pLayerName,
3313 uint32_t* pPropertyCount,
3314 VkExtensionProperties* pProperties)
3315 {
3316 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3317
3318 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3319 if (radv_supported_instance_extensions.extensions[i]) {
3320 vk_outarray_append(&out, prop) {
3321 *prop = radv_instance_extensions[i];
3322 }
3323 }
3324 }
3325
3326 return vk_outarray_status(&out);
3327 }
3328
3329 VkResult radv_EnumerateDeviceExtensionProperties(
3330 VkPhysicalDevice physicalDevice,
3331 const char* pLayerName,
3332 uint32_t* pPropertyCount,
3333 VkExtensionProperties* pProperties)
3334 {
3335 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3336 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3337
3338 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3339 if (device->supported_extensions.extensions[i]) {
3340 vk_outarray_append(&out, prop) {
3341 *prop = radv_device_extensions[i];
3342 }
3343 }
3344 }
3345
3346 return vk_outarray_status(&out);
3347 }
3348
3349 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3350 VkInstance _instance,
3351 const char* pName)
3352 {
3353 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3354 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3355
3356 if (unchecked) {
3357 return radv_lookup_entrypoint_unchecked(pName);
3358 } else {
3359 return radv_lookup_entrypoint_checked(pName,
3360 instance ? instance->apiVersion : 0,
3361 instance ? &instance->enabled_extensions : NULL,
3362 NULL);
3363 }
3364 }
3365
3366 /* The loader wants us to expose a second GetInstanceProcAddr function
3367 * to work around certain LD_PRELOAD issues seen in apps.
3368 */
3369 PUBLIC
3370 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3371 VkInstance instance,
3372 const char* pName);
3373
3374 PUBLIC
3375 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3376 VkInstance instance,
3377 const char* pName)
3378 {
3379 return radv_GetInstanceProcAddr(instance, pName);
3380 }
3381
3382 PUBLIC
3383 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3384 VkInstance _instance,
3385 const char* pName);
3386
3387 PUBLIC
3388 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3389 VkInstance _instance,
3390 const char* pName)
3391 {
3392 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3393
3394 return radv_lookup_physical_device_entrypoint_checked(pName,
3395 instance ? instance->apiVersion : 0,
3396 instance ? &instance->enabled_extensions : NULL);
3397 }
3398
3399 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3400 VkDevice _device,
3401 const char* pName)
3402 {
3403 RADV_FROM_HANDLE(radv_device, device, _device);
3404 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3405
3406 if (unchecked) {
3407 return radv_lookup_entrypoint_unchecked(pName);
3408 } else {
3409 return radv_lookup_entrypoint_checked(pName,
3410 device->instance->apiVersion,
3411 &device->instance->enabled_extensions,
3412 &device->enabled_extensions);
3413 }
3414 }
3415
3416 bool radv_get_memory_fd(struct radv_device *device,
3417 struct radv_device_memory *memory,
3418 int *pFD)
3419 {
3420 struct radeon_bo_metadata metadata;
3421
3422 if (memory->image) {
3423 radv_init_metadata(device, memory->image, &metadata);
3424 device->ws->buffer_set_metadata(memory->bo, &metadata);
3425 }
3426
3427 return device->ws->buffer_get_fd(device->ws, memory->bo,
3428 pFD);
3429 }
3430
3431 static VkResult radv_alloc_memory(struct radv_device *device,
3432 const VkMemoryAllocateInfo* pAllocateInfo,
3433 const VkAllocationCallbacks* pAllocator,
3434 VkDeviceMemory* pMem)
3435 {
3436 struct radv_device_memory *mem;
3437 VkResult result;
3438 enum radeon_bo_domain domain;
3439 uint32_t flags = 0;
3440 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3441
3442 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3443
3444 if (pAllocateInfo->allocationSize == 0) {
3445 /* Apparently, this is allowed */
3446 *pMem = VK_NULL_HANDLE;
3447 return VK_SUCCESS;
3448 }
3449
3450 const VkImportMemoryFdInfoKHR *import_info =
3451 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3452 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3453 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3454 const VkExportMemoryAllocateInfo *export_info =
3455 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3456 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3457 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3458
3459 const struct wsi_memory_allocate_info *wsi_info =
3460 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3461
3462 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3463 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3464 if (mem == NULL)
3465 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3466
3467 if (wsi_info && wsi_info->implicit_sync)
3468 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3469
3470 if (dedicate_info) {
3471 mem->image = radv_image_from_handle(dedicate_info->image);
3472 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3473 } else {
3474 mem->image = NULL;
3475 mem->buffer = NULL;
3476 }
3477
3478 float priority_float = 0.5;
3479 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3480 vk_find_struct_const(pAllocateInfo->pNext,
3481 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3482 if (priority_ext)
3483 priority_float = priority_ext->priority;
3484
3485 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3486 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3487
3488 mem->user_ptr = NULL;
3489
3490 if (import_info) {
3491 assert(import_info->handleType ==
3492 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3493 import_info->handleType ==
3494 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3495 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3496 priority, NULL, NULL);
3497 if (!mem->bo) {
3498 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3499 goto fail;
3500 } else {
3501 close(import_info->fd);
3502 }
3503 } else if (host_ptr_info) {
3504 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3505 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3506 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3507 pAllocateInfo->allocationSize,
3508 priority);
3509 if (!mem->bo) {
3510 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3511 goto fail;
3512 } else {
3513 mem->user_ptr = host_ptr_info->pHostPointer;
3514 }
3515 } else {
3516 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3517 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3518 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3519 domain = RADEON_DOMAIN_GTT;
3520 else
3521 domain = RADEON_DOMAIN_VRAM;
3522
3523 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3524 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3525 else
3526 flags |= RADEON_FLAG_CPU_ACCESS;
3527
3528 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3529 flags |= RADEON_FLAG_GTT_WC;
3530
3531 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3532 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3533 if (device->use_global_bo_list) {
3534 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3535 }
3536 }
3537
3538 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3539 domain, flags, priority);
3540
3541 if (!mem->bo) {
3542 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3543 goto fail;
3544 }
3545 mem->type_index = mem_type_index;
3546 }
3547
3548 result = radv_bo_list_add(device, mem->bo);
3549 if (result != VK_SUCCESS)
3550 goto fail_bo;
3551
3552 *pMem = radv_device_memory_to_handle(mem);
3553
3554 return VK_SUCCESS;
3555
3556 fail_bo:
3557 device->ws->buffer_destroy(mem->bo);
3558 fail:
3559 vk_free2(&device->alloc, pAllocator, mem);
3560
3561 return result;
3562 }
3563
3564 VkResult radv_AllocateMemory(
3565 VkDevice _device,
3566 const VkMemoryAllocateInfo* pAllocateInfo,
3567 const VkAllocationCallbacks* pAllocator,
3568 VkDeviceMemory* pMem)
3569 {
3570 RADV_FROM_HANDLE(radv_device, device, _device);
3571 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3572 }
3573
3574 void radv_FreeMemory(
3575 VkDevice _device,
3576 VkDeviceMemory _mem,
3577 const VkAllocationCallbacks* pAllocator)
3578 {
3579 RADV_FROM_HANDLE(radv_device, device, _device);
3580 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3581
3582 if (mem == NULL)
3583 return;
3584
3585 radv_bo_list_remove(device, mem->bo);
3586 device->ws->buffer_destroy(mem->bo);
3587 mem->bo = NULL;
3588
3589 vk_free2(&device->alloc, pAllocator, mem);
3590 }
3591
3592 VkResult radv_MapMemory(
3593 VkDevice _device,
3594 VkDeviceMemory _memory,
3595 VkDeviceSize offset,
3596 VkDeviceSize size,
3597 VkMemoryMapFlags flags,
3598 void** ppData)
3599 {
3600 RADV_FROM_HANDLE(radv_device, device, _device);
3601 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3602
3603 if (mem == NULL) {
3604 *ppData = NULL;
3605 return VK_SUCCESS;
3606 }
3607
3608 if (mem->user_ptr)
3609 *ppData = mem->user_ptr;
3610 else
3611 *ppData = device->ws->buffer_map(mem->bo);
3612
3613 if (*ppData) {
3614 *ppData += offset;
3615 return VK_SUCCESS;
3616 }
3617
3618 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3619 }
3620
3621 void radv_UnmapMemory(
3622 VkDevice _device,
3623 VkDeviceMemory _memory)
3624 {
3625 RADV_FROM_HANDLE(radv_device, device, _device);
3626 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3627
3628 if (mem == NULL)
3629 return;
3630
3631 if (mem->user_ptr == NULL)
3632 device->ws->buffer_unmap(mem->bo);
3633 }
3634
3635 VkResult radv_FlushMappedMemoryRanges(
3636 VkDevice _device,
3637 uint32_t memoryRangeCount,
3638 const VkMappedMemoryRange* pMemoryRanges)
3639 {
3640 return VK_SUCCESS;
3641 }
3642
3643 VkResult radv_InvalidateMappedMemoryRanges(
3644 VkDevice _device,
3645 uint32_t memoryRangeCount,
3646 const VkMappedMemoryRange* pMemoryRanges)
3647 {
3648 return VK_SUCCESS;
3649 }
3650
3651 void radv_GetBufferMemoryRequirements(
3652 VkDevice _device,
3653 VkBuffer _buffer,
3654 VkMemoryRequirements* pMemoryRequirements)
3655 {
3656 RADV_FROM_HANDLE(radv_device, device, _device);
3657 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3658
3659 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3660
3661 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3662 pMemoryRequirements->alignment = 4096;
3663 else
3664 pMemoryRequirements->alignment = 16;
3665
3666 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3667 }
3668
3669 void radv_GetBufferMemoryRequirements2(
3670 VkDevice device,
3671 const VkBufferMemoryRequirementsInfo2 *pInfo,
3672 VkMemoryRequirements2 *pMemoryRequirements)
3673 {
3674 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3675 &pMemoryRequirements->memoryRequirements);
3676 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3677 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3678 switch (ext->sType) {
3679 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3680 VkMemoryDedicatedRequirements *req =
3681 (VkMemoryDedicatedRequirements *) ext;
3682 req->requiresDedicatedAllocation = buffer->shareable;
3683 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3684 break;
3685 }
3686 default:
3687 break;
3688 }
3689 }
3690 }
3691
3692 void radv_GetImageMemoryRequirements(
3693 VkDevice _device,
3694 VkImage _image,
3695 VkMemoryRequirements* pMemoryRequirements)
3696 {
3697 RADV_FROM_HANDLE(radv_device, device, _device);
3698 RADV_FROM_HANDLE(radv_image, image, _image);
3699
3700 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3701
3702 pMemoryRequirements->size = image->size;
3703 pMemoryRequirements->alignment = image->alignment;
3704 }
3705
3706 void radv_GetImageMemoryRequirements2(
3707 VkDevice device,
3708 const VkImageMemoryRequirementsInfo2 *pInfo,
3709 VkMemoryRequirements2 *pMemoryRequirements)
3710 {
3711 radv_GetImageMemoryRequirements(device, pInfo->image,
3712 &pMemoryRequirements->memoryRequirements);
3713
3714 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3715
3716 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3717 switch (ext->sType) {
3718 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3719 VkMemoryDedicatedRequirements *req =
3720 (VkMemoryDedicatedRequirements *) ext;
3721 req->requiresDedicatedAllocation = image->shareable;
3722 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3723 break;
3724 }
3725 default:
3726 break;
3727 }
3728 }
3729 }
3730
3731 void radv_GetImageSparseMemoryRequirements(
3732 VkDevice device,
3733 VkImage image,
3734 uint32_t* pSparseMemoryRequirementCount,
3735 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3736 {
3737 stub();
3738 }
3739
3740 void radv_GetImageSparseMemoryRequirements2(
3741 VkDevice device,
3742 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3743 uint32_t* pSparseMemoryRequirementCount,
3744 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3745 {
3746 stub();
3747 }
3748
3749 void radv_GetDeviceMemoryCommitment(
3750 VkDevice device,
3751 VkDeviceMemory memory,
3752 VkDeviceSize* pCommittedMemoryInBytes)
3753 {
3754 *pCommittedMemoryInBytes = 0;
3755 }
3756
3757 VkResult radv_BindBufferMemory2(VkDevice device,
3758 uint32_t bindInfoCount,
3759 const VkBindBufferMemoryInfo *pBindInfos)
3760 {
3761 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3762 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3763 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3764
3765 if (mem) {
3766 buffer->bo = mem->bo;
3767 buffer->offset = pBindInfos[i].memoryOffset;
3768 } else {
3769 buffer->bo = NULL;
3770 }
3771 }
3772 return VK_SUCCESS;
3773 }
3774
3775 VkResult radv_BindBufferMemory(
3776 VkDevice device,
3777 VkBuffer buffer,
3778 VkDeviceMemory memory,
3779 VkDeviceSize memoryOffset)
3780 {
3781 const VkBindBufferMemoryInfo info = {
3782 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3783 .buffer = buffer,
3784 .memory = memory,
3785 .memoryOffset = memoryOffset
3786 };
3787
3788 return radv_BindBufferMemory2(device, 1, &info);
3789 }
3790
3791 VkResult radv_BindImageMemory2(VkDevice device,
3792 uint32_t bindInfoCount,
3793 const VkBindImageMemoryInfo *pBindInfos)
3794 {
3795 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3796 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3797 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3798
3799 if (mem) {
3800 image->bo = mem->bo;
3801 image->offset = pBindInfos[i].memoryOffset;
3802 } else {
3803 image->bo = NULL;
3804 image->offset = 0;
3805 }
3806 }
3807 return VK_SUCCESS;
3808 }
3809
3810
3811 VkResult radv_BindImageMemory(
3812 VkDevice device,
3813 VkImage image,
3814 VkDeviceMemory memory,
3815 VkDeviceSize memoryOffset)
3816 {
3817 const VkBindImageMemoryInfo info = {
3818 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3819 .image = image,
3820 .memory = memory,
3821 .memoryOffset = memoryOffset
3822 };
3823
3824 return radv_BindImageMemory2(device, 1, &info);
3825 }
3826
3827
3828 static void
3829 radv_sparse_buffer_bind_memory(struct radv_device *device,
3830 const VkSparseBufferMemoryBindInfo *bind)
3831 {
3832 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3833
3834 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3835 struct radv_device_memory *mem = NULL;
3836
3837 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3838 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3839
3840 device->ws->buffer_virtual_bind(buffer->bo,
3841 bind->pBinds[i].resourceOffset,
3842 bind->pBinds[i].size,
3843 mem ? mem->bo : NULL,
3844 bind->pBinds[i].memoryOffset);
3845 }
3846 }
3847
3848 static void
3849 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3850 const VkSparseImageOpaqueMemoryBindInfo *bind)
3851 {
3852 RADV_FROM_HANDLE(radv_image, image, bind->image);
3853
3854 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3855 struct radv_device_memory *mem = NULL;
3856
3857 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3858 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3859
3860 device->ws->buffer_virtual_bind(image->bo,
3861 bind->pBinds[i].resourceOffset,
3862 bind->pBinds[i].size,
3863 mem ? mem->bo : NULL,
3864 bind->pBinds[i].memoryOffset);
3865 }
3866 }
3867
3868 VkResult radv_QueueBindSparse(
3869 VkQueue _queue,
3870 uint32_t bindInfoCount,
3871 const VkBindSparseInfo* pBindInfo,
3872 VkFence _fence)
3873 {
3874 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3875 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3876 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3877 bool fence_emitted = false;
3878 VkResult result;
3879 int ret;
3880
3881 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3882 struct radv_winsys_sem_info sem_info;
3883 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3884 radv_sparse_buffer_bind_memory(queue->device,
3885 pBindInfo[i].pBufferBinds + j);
3886 }
3887
3888 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3889 radv_sparse_image_opaque_bind_memory(queue->device,
3890 pBindInfo[i].pImageOpaqueBinds + j);
3891 }
3892
3893 VkResult result;
3894 result = radv_alloc_sem_info(queue->device->instance,
3895 &sem_info,
3896 pBindInfo[i].waitSemaphoreCount,
3897 pBindInfo[i].pWaitSemaphores,
3898 pBindInfo[i].signalSemaphoreCount,
3899 pBindInfo[i].pSignalSemaphores,
3900 _fence);
3901 if (result != VK_SUCCESS)
3902 return result;
3903
3904 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3905 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3906 &queue->device->empty_cs[queue->queue_family_index],
3907 1, NULL, NULL,
3908 &sem_info, NULL,
3909 false, base_fence);
3910 if (ret) {
3911 radv_loge("failed to submit CS %d\n", i);
3912 abort();
3913 }
3914
3915 fence_emitted = true;
3916 }
3917
3918 radv_free_sem_info(&sem_info);
3919
3920 }
3921
3922 if (fence) {
3923 if (!fence_emitted) {
3924 result = radv_signal_fence(queue, fence);
3925 if (result != VK_SUCCESS)
3926 return result;
3927 }
3928 }
3929
3930 return VK_SUCCESS;
3931 }
3932
3933 VkResult radv_CreateFence(
3934 VkDevice _device,
3935 const VkFenceCreateInfo* pCreateInfo,
3936 const VkAllocationCallbacks* pAllocator,
3937 VkFence* pFence)
3938 {
3939 RADV_FROM_HANDLE(radv_device, device, _device);
3940 const VkExportFenceCreateInfo *export =
3941 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3942 VkExternalFenceHandleTypeFlags handleTypes =
3943 export ? export->handleTypes : 0;
3944
3945 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3946 sizeof(*fence), 8,
3947 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3948
3949 if (!fence)
3950 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3951
3952 fence->fence_wsi = NULL;
3953 fence->temp_syncobj = 0;
3954 if (device->always_use_syncobj || handleTypes) {
3955 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3956 if (ret) {
3957 vk_free2(&device->alloc, pAllocator, fence);
3958 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3959 }
3960 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3961 device->ws->signal_syncobj(device->ws, fence->syncobj);
3962 }
3963 fence->fence = NULL;
3964 } else {
3965 fence->fence = device->ws->create_fence();
3966 if (!fence->fence) {
3967 vk_free2(&device->alloc, pAllocator, fence);
3968 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3969 }
3970 fence->syncobj = 0;
3971 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3972 device->ws->signal_fence(fence->fence);
3973 }
3974
3975 *pFence = radv_fence_to_handle(fence);
3976
3977 return VK_SUCCESS;
3978 }
3979
3980 void radv_DestroyFence(
3981 VkDevice _device,
3982 VkFence _fence,
3983 const VkAllocationCallbacks* pAllocator)
3984 {
3985 RADV_FROM_HANDLE(radv_device, device, _device);
3986 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3987
3988 if (!fence)
3989 return;
3990
3991 if (fence->temp_syncobj)
3992 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3993 if (fence->syncobj)
3994 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3995 if (fence->fence)
3996 device->ws->destroy_fence(fence->fence);
3997 if (fence->fence_wsi)
3998 fence->fence_wsi->destroy(fence->fence_wsi);
3999 vk_free2(&device->alloc, pAllocator, fence);
4000 }
4001
4002
4003 uint64_t radv_get_current_time(void)
4004 {
4005 struct timespec tv;
4006 clock_gettime(CLOCK_MONOTONIC, &tv);
4007 return tv.tv_nsec + tv.tv_sec*1000000000ull;
4008 }
4009
4010 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
4011 {
4012 uint64_t current_time = radv_get_current_time();
4013
4014 timeout = MIN2(UINT64_MAX - current_time, timeout);
4015
4016 return current_time + timeout;
4017 }
4018
4019
4020 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
4021 uint32_t fenceCount, const VkFence *pFences)
4022 {
4023 for (uint32_t i = 0; i < fenceCount; ++i) {
4024 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4025 if (fence->fence == NULL || fence->syncobj ||
4026 fence->temp_syncobj || fence->fence_wsi ||
4027 (!device->ws->is_fence_waitable(fence->fence)))
4028 return false;
4029 }
4030 return true;
4031 }
4032
4033 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
4034 {
4035 for (uint32_t i = 0; i < fenceCount; ++i) {
4036 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4037 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
4038 return false;
4039 }
4040 return true;
4041 }
4042
4043 VkResult radv_WaitForFences(
4044 VkDevice _device,
4045 uint32_t fenceCount,
4046 const VkFence* pFences,
4047 VkBool32 waitAll,
4048 uint64_t timeout)
4049 {
4050 RADV_FROM_HANDLE(radv_device, device, _device);
4051 timeout = radv_get_absolute_timeout(timeout);
4052
4053 if (device->always_use_syncobj &&
4054 radv_all_fences_syncobj(fenceCount, pFences))
4055 {
4056 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
4057 if (!handles)
4058 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4059
4060 for (uint32_t i = 0; i < fenceCount; ++i) {
4061 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4062 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
4063 }
4064
4065 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
4066
4067 free(handles);
4068 return success ? VK_SUCCESS : VK_TIMEOUT;
4069 }
4070
4071 if (!waitAll && fenceCount > 1) {
4072 /* Not doing this by default for waitAll, due to needing to allocate twice. */
4073 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
4074 uint32_t wait_count = 0;
4075 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
4076 if (!fences)
4077 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4078
4079 for (uint32_t i = 0; i < fenceCount; ++i) {
4080 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4081
4082 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
4083 free(fences);
4084 return VK_SUCCESS;
4085 }
4086
4087 fences[wait_count++] = fence->fence;
4088 }
4089
4090 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
4091 waitAll, timeout - radv_get_current_time());
4092
4093 free(fences);
4094 return success ? VK_SUCCESS : VK_TIMEOUT;
4095 }
4096
4097 while(radv_get_current_time() <= timeout) {
4098 for (uint32_t i = 0; i < fenceCount; ++i) {
4099 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
4100 return VK_SUCCESS;
4101 }
4102 }
4103 return VK_TIMEOUT;
4104 }
4105
4106 for (uint32_t i = 0; i < fenceCount; ++i) {
4107 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4108 bool expired = false;
4109
4110 if (fence->temp_syncobj) {
4111 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4112 return VK_TIMEOUT;
4113 continue;
4114 }
4115
4116 if (fence->syncobj) {
4117 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4118 return VK_TIMEOUT;
4119 continue;
4120 }
4121
4122 if (fence->fence) {
4123 if (!device->ws->is_fence_waitable(fence->fence)) {
4124 while(!device->ws->is_fence_waitable(fence->fence) &&
4125 radv_get_current_time() <= timeout)
4126 /* Do nothing */;
4127 }
4128
4129 expired = device->ws->fence_wait(device->ws,
4130 fence->fence,
4131 true, timeout);
4132 if (!expired)
4133 return VK_TIMEOUT;
4134 }
4135
4136 if (fence->fence_wsi) {
4137 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4138 if (result != VK_SUCCESS)
4139 return result;
4140 }
4141 }
4142
4143 return VK_SUCCESS;
4144 }
4145
4146 VkResult radv_ResetFences(VkDevice _device,
4147 uint32_t fenceCount,
4148 const VkFence *pFences)
4149 {
4150 RADV_FROM_HANDLE(radv_device, device, _device);
4151
4152 for (unsigned i = 0; i < fenceCount; ++i) {
4153 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4154 if (fence->fence)
4155 device->ws->reset_fence(fence->fence);
4156
4157 /* Per spec, we first restore the permanent payload, and then reset, so
4158 * having a temp syncobj should not skip resetting the permanent syncobj. */
4159 if (fence->temp_syncobj) {
4160 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4161 fence->temp_syncobj = 0;
4162 }
4163
4164 if (fence->syncobj) {
4165 device->ws->reset_syncobj(device->ws, fence->syncobj);
4166 }
4167 }
4168
4169 return VK_SUCCESS;
4170 }
4171
4172 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4173 {
4174 RADV_FROM_HANDLE(radv_device, device, _device);
4175 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4176
4177 if (fence->temp_syncobj) {
4178 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4179 return success ? VK_SUCCESS : VK_NOT_READY;
4180 }
4181
4182 if (fence->syncobj) {
4183 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4184 return success ? VK_SUCCESS : VK_NOT_READY;
4185 }
4186
4187 if (fence->fence) {
4188 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4189 return VK_NOT_READY;
4190 }
4191 if (fence->fence_wsi) {
4192 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4193
4194 if (result != VK_SUCCESS) {
4195 if (result == VK_TIMEOUT)
4196 return VK_NOT_READY;
4197 return result;
4198 }
4199 }
4200 return VK_SUCCESS;
4201 }
4202
4203
4204 // Queue semaphore functions
4205
4206 VkResult radv_CreateSemaphore(
4207 VkDevice _device,
4208 const VkSemaphoreCreateInfo* pCreateInfo,
4209 const VkAllocationCallbacks* pAllocator,
4210 VkSemaphore* pSemaphore)
4211 {
4212 RADV_FROM_HANDLE(radv_device, device, _device);
4213 const VkExportSemaphoreCreateInfo *export =
4214 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4215 VkExternalSemaphoreHandleTypeFlags handleTypes =
4216 export ? export->handleTypes : 0;
4217
4218 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4219 sizeof(*sem), 8,
4220 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4221 if (!sem)
4222 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4223
4224 sem->temp_syncobj = 0;
4225 /* create a syncobject if we are going to export this semaphore */
4226 if (device->always_use_syncobj || handleTypes) {
4227 assert (device->physical_device->rad_info.has_syncobj);
4228 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4229 if (ret) {
4230 vk_free2(&device->alloc, pAllocator, sem);
4231 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4232 }
4233 sem->sem = NULL;
4234 } else {
4235 sem->sem = device->ws->create_sem(device->ws);
4236 if (!sem->sem) {
4237 vk_free2(&device->alloc, pAllocator, sem);
4238 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4239 }
4240 sem->syncobj = 0;
4241 }
4242
4243 *pSemaphore = radv_semaphore_to_handle(sem);
4244 return VK_SUCCESS;
4245 }
4246
4247 void radv_DestroySemaphore(
4248 VkDevice _device,
4249 VkSemaphore _semaphore,
4250 const VkAllocationCallbacks* pAllocator)
4251 {
4252 RADV_FROM_HANDLE(radv_device, device, _device);
4253 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4254 if (!_semaphore)
4255 return;
4256
4257 if (sem->syncobj)
4258 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4259 else
4260 device->ws->destroy_sem(sem->sem);
4261 vk_free2(&device->alloc, pAllocator, sem);
4262 }
4263
4264 VkResult radv_CreateEvent(
4265 VkDevice _device,
4266 const VkEventCreateInfo* pCreateInfo,
4267 const VkAllocationCallbacks* pAllocator,
4268 VkEvent* pEvent)
4269 {
4270 RADV_FROM_HANDLE(radv_device, device, _device);
4271 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4272 sizeof(*event), 8,
4273 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4274
4275 if (!event)
4276 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4277
4278 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4279 RADEON_DOMAIN_GTT,
4280 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4281 RADV_BO_PRIORITY_FENCE);
4282 if (!event->bo) {
4283 vk_free2(&device->alloc, pAllocator, event);
4284 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4285 }
4286
4287 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4288
4289 *pEvent = radv_event_to_handle(event);
4290
4291 return VK_SUCCESS;
4292 }
4293
4294 void radv_DestroyEvent(
4295 VkDevice _device,
4296 VkEvent _event,
4297 const VkAllocationCallbacks* pAllocator)
4298 {
4299 RADV_FROM_HANDLE(radv_device, device, _device);
4300 RADV_FROM_HANDLE(radv_event, event, _event);
4301
4302 if (!event)
4303 return;
4304 device->ws->buffer_destroy(event->bo);
4305 vk_free2(&device->alloc, pAllocator, event);
4306 }
4307
4308 VkResult radv_GetEventStatus(
4309 VkDevice _device,
4310 VkEvent _event)
4311 {
4312 RADV_FROM_HANDLE(radv_event, event, _event);
4313
4314 if (*event->map == 1)
4315 return VK_EVENT_SET;
4316 return VK_EVENT_RESET;
4317 }
4318
4319 VkResult radv_SetEvent(
4320 VkDevice _device,
4321 VkEvent _event)
4322 {
4323 RADV_FROM_HANDLE(radv_event, event, _event);
4324 *event->map = 1;
4325
4326 return VK_SUCCESS;
4327 }
4328
4329 VkResult radv_ResetEvent(
4330 VkDevice _device,
4331 VkEvent _event)
4332 {
4333 RADV_FROM_HANDLE(radv_event, event, _event);
4334 *event->map = 0;
4335
4336 return VK_SUCCESS;
4337 }
4338
4339 VkResult radv_CreateBuffer(
4340 VkDevice _device,
4341 const VkBufferCreateInfo* pCreateInfo,
4342 const VkAllocationCallbacks* pAllocator,
4343 VkBuffer* pBuffer)
4344 {
4345 RADV_FROM_HANDLE(radv_device, device, _device);
4346 struct radv_buffer *buffer;
4347
4348 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4349
4350 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4351 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4352 if (buffer == NULL)
4353 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4354
4355 buffer->size = pCreateInfo->size;
4356 buffer->usage = pCreateInfo->usage;
4357 buffer->bo = NULL;
4358 buffer->offset = 0;
4359 buffer->flags = pCreateInfo->flags;
4360
4361 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4362 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4363
4364 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4365 buffer->bo = device->ws->buffer_create(device->ws,
4366 align64(buffer->size, 4096),
4367 4096, 0, RADEON_FLAG_VIRTUAL,
4368 RADV_BO_PRIORITY_VIRTUAL);
4369 if (!buffer->bo) {
4370 vk_free2(&device->alloc, pAllocator, buffer);
4371 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4372 }
4373 }
4374
4375 *pBuffer = radv_buffer_to_handle(buffer);
4376
4377 return VK_SUCCESS;
4378 }
4379
4380 void radv_DestroyBuffer(
4381 VkDevice _device,
4382 VkBuffer _buffer,
4383 const VkAllocationCallbacks* pAllocator)
4384 {
4385 RADV_FROM_HANDLE(radv_device, device, _device);
4386 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4387
4388 if (!buffer)
4389 return;
4390
4391 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4392 device->ws->buffer_destroy(buffer->bo);
4393
4394 vk_free2(&device->alloc, pAllocator, buffer);
4395 }
4396
4397 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4398 VkDevice device,
4399 const VkBufferDeviceAddressInfoEXT* pInfo)
4400 {
4401 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4402 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4403 }
4404
4405
4406 static inline unsigned
4407 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4408 {
4409 if (stencil)
4410 return plane->surface.u.legacy.stencil_tiling_index[level];
4411 else
4412 return plane->surface.u.legacy.tiling_index[level];
4413 }
4414
4415 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4416 {
4417 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4418 }
4419
4420 static uint32_t
4421 radv_init_dcc_control_reg(struct radv_device *device,
4422 struct radv_image_view *iview)
4423 {
4424 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4425 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4426 unsigned max_compressed_block_size;
4427 unsigned independent_128b_blocks;
4428 unsigned independent_64b_blocks;
4429
4430 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4431 return 0;
4432
4433 if (!device->physical_device->rad_info.has_dedicated_vram) {
4434 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4435 * dGPU and 64 for APU because all of our APUs to date use
4436 * DIMMs which have a request granularity size of 64B while all
4437 * other chips have a 32B request size.
4438 */
4439 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4440 }
4441
4442 if (device->physical_device->rad_info.chip_class >= GFX10) {
4443 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4444 independent_64b_blocks = 0;
4445 independent_128b_blocks = 1;
4446 } else {
4447 independent_128b_blocks = 0;
4448
4449 if (iview->image->info.samples > 1) {
4450 if (iview->image->planes[0].surface.bpe == 1)
4451 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4452 else if (iview->image->planes[0].surface.bpe == 2)
4453 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4454 }
4455
4456 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4457 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4458 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4459 /* If this DCC image is potentially going to be used in texture
4460 * fetches, we need some special settings.
4461 */
4462 independent_64b_blocks = 1;
4463 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4464 } else {
4465 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4466 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4467 * big as possible for better compression state.
4468 */
4469 independent_64b_blocks = 0;
4470 max_compressed_block_size = max_uncompressed_block_size;
4471 }
4472 }
4473
4474 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4475 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4476 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4477 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4478 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4479 }
4480
4481 void
4482 radv_initialise_color_surface(struct radv_device *device,
4483 struct radv_color_buffer_info *cb,
4484 struct radv_image_view *iview)
4485 {
4486 const struct vk_format_description *desc;
4487 unsigned ntype, format, swap, endian;
4488 unsigned blend_clamp = 0, blend_bypass = 0;
4489 uint64_t va;
4490 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4491 const struct radeon_surf *surf = &plane->surface;
4492
4493 desc = vk_format_description(iview->vk_format);
4494
4495 memset(cb, 0, sizeof(*cb));
4496
4497 /* Intensity is implemented as Red, so treat it that way. */
4498 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4499
4500 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4501
4502 cb->cb_color_base = va >> 8;
4503
4504 if (device->physical_device->rad_info.chip_class >= GFX9) {
4505 struct gfx9_surf_meta_flags meta;
4506 if (iview->image->dcc_offset)
4507 meta = surf->u.gfx9.dcc;
4508 else
4509 meta = surf->u.gfx9.cmask;
4510
4511 if (device->physical_device->rad_info.chip_class >= GFX10) {
4512 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4513 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4514 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4515 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4516 } else {
4517 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4518 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4519 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4520 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4521 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4522 }
4523
4524 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4525 cb->cb_color_base |= surf->tile_swizzle;
4526 } else {
4527 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4528 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4529
4530 cb->cb_color_base += level_info->offset >> 8;
4531 if (level_info->mode == RADEON_SURF_MODE_2D)
4532 cb->cb_color_base |= surf->tile_swizzle;
4533
4534 pitch_tile_max = level_info->nblk_x / 8 - 1;
4535 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4536 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4537
4538 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4539 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4540 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4541
4542 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4543
4544 if (radv_image_has_fmask(iview->image)) {
4545 if (device->physical_device->rad_info.chip_class >= GFX7)
4546 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4547 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4548 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4549 } else {
4550 /* This must be set for fast clear to work without FMASK. */
4551 if (device->physical_device->rad_info.chip_class >= GFX7)
4552 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4553 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4554 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4555 }
4556 }
4557
4558 /* CMASK variables */
4559 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4560 va += iview->image->cmask_offset;
4561 cb->cb_color_cmask = va >> 8;
4562
4563 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4564 va += iview->image->dcc_offset;
4565
4566 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4567 device->physical_device->rad_info.chip_class <= GFX8)
4568 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4569
4570 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4571 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4572
4573 cb->cb_dcc_base = va >> 8;
4574 cb->cb_dcc_base |= dcc_tile_swizzle;
4575
4576 /* GFX10 field has the same base shift as the GFX6 field. */
4577 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4578 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4579 S_028C6C_SLICE_MAX_GFX10(max_slice);
4580
4581 if (iview->image->info.samples > 1) {
4582 unsigned log_samples = util_logbase2(iview->image->info.samples);
4583
4584 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4585 S_028C74_NUM_FRAGMENTS(log_samples);
4586 }
4587
4588 if (radv_image_has_fmask(iview->image)) {
4589 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4590 cb->cb_color_fmask = va >> 8;
4591 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4592 } else {
4593 cb->cb_color_fmask = cb->cb_color_base;
4594 }
4595
4596 ntype = radv_translate_color_numformat(iview->vk_format,
4597 desc,
4598 vk_format_get_first_non_void_channel(iview->vk_format));
4599 format = radv_translate_colorformat(iview->vk_format);
4600 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4601 radv_finishme("Illegal color\n");
4602 swap = radv_translate_colorswap(iview->vk_format, false);
4603 endian = radv_colorformat_endian_swap(format);
4604
4605 /* blend clamp should be set for all NORM/SRGB types */
4606 if (ntype == V_028C70_NUMBER_UNORM ||
4607 ntype == V_028C70_NUMBER_SNORM ||
4608 ntype == V_028C70_NUMBER_SRGB)
4609 blend_clamp = 1;
4610
4611 /* set blend bypass according to docs if SINT/UINT or
4612 8/24 COLOR variants */
4613 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4614 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4615 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4616 blend_clamp = 0;
4617 blend_bypass = 1;
4618 }
4619 #if 0
4620 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4621 (format == V_028C70_COLOR_8 ||
4622 format == V_028C70_COLOR_8_8 ||
4623 format == V_028C70_COLOR_8_8_8_8))
4624 ->color_is_int8 = true;
4625 #endif
4626 cb->cb_color_info = S_028C70_FORMAT(format) |
4627 S_028C70_COMP_SWAP(swap) |
4628 S_028C70_BLEND_CLAMP(blend_clamp) |
4629 S_028C70_BLEND_BYPASS(blend_bypass) |
4630 S_028C70_SIMPLE_FLOAT(1) |
4631 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4632 ntype != V_028C70_NUMBER_SNORM &&
4633 ntype != V_028C70_NUMBER_SRGB &&
4634 format != V_028C70_COLOR_8_24 &&
4635 format != V_028C70_COLOR_24_8) |
4636 S_028C70_NUMBER_TYPE(ntype) |
4637 S_028C70_ENDIAN(endian);
4638 if (radv_image_has_fmask(iview->image)) {
4639 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4640 if (device->physical_device->rad_info.chip_class == GFX6) {
4641 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4642 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4643 }
4644
4645 if (radv_image_is_tc_compat_cmask(iview->image)) {
4646 /* Allow the texture block to read FMASK directly
4647 * without decompressing it. This bit must be cleared
4648 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4649 * otherwise the operation doesn't happen.
4650 */
4651 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4652
4653 /* Set CMASK into a tiling format that allows the
4654 * texture block to read it.
4655 */
4656 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4657 }
4658 }
4659
4660 if (radv_image_has_cmask(iview->image) &&
4661 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4662 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4663
4664 if (radv_dcc_enabled(iview->image, iview->base_mip))
4665 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4666
4667 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4668
4669 /* This must be set for fast clear to work without FMASK. */
4670 if (!radv_image_has_fmask(iview->image) &&
4671 device->physical_device->rad_info.chip_class == GFX6) {
4672 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4673 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4674 }
4675
4676 if (device->physical_device->rad_info.chip_class >= GFX9) {
4677 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4678
4679 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4680 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4681 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4682 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4683
4684 if (device->physical_device->rad_info.chip_class >= GFX10) {
4685 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4686
4687 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4688 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4689 S_028EE0_RESOURCE_LEVEL(1);
4690 } else {
4691 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4692 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4693 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4694 }
4695
4696 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4697 S_028C68_MIP0_HEIGHT(height - 1) |
4698 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4699 }
4700 }
4701
4702 static unsigned
4703 radv_calc_decompress_on_z_planes(struct radv_device *device,
4704 struct radv_image_view *iview)
4705 {
4706 unsigned max_zplanes = 0;
4707
4708 assert(radv_image_is_tc_compat_htile(iview->image));
4709
4710 if (device->physical_device->rad_info.chip_class >= GFX9) {
4711 /* Default value for 32-bit depth surfaces. */
4712 max_zplanes = 4;
4713
4714 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4715 iview->image->info.samples > 1)
4716 max_zplanes = 2;
4717
4718 max_zplanes = max_zplanes + 1;
4719 } else {
4720 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4721 /* Do not enable Z plane compression for 16-bit depth
4722 * surfaces because isn't supported on GFX8. Only
4723 * 32-bit depth surfaces are supported by the hardware.
4724 * This allows to maintain shader compatibility and to
4725 * reduce the number of depth decompressions.
4726 */
4727 max_zplanes = 1;
4728 } else {
4729 if (iview->image->info.samples <= 1)
4730 max_zplanes = 5;
4731 else if (iview->image->info.samples <= 4)
4732 max_zplanes = 3;
4733 else
4734 max_zplanes = 2;
4735 }
4736 }
4737
4738 return max_zplanes;
4739 }
4740
4741 void
4742 radv_initialise_ds_surface(struct radv_device *device,
4743 struct radv_ds_buffer_info *ds,
4744 struct radv_image_view *iview)
4745 {
4746 unsigned level = iview->base_mip;
4747 unsigned format, stencil_format;
4748 uint64_t va, s_offs, z_offs;
4749 bool stencil_only = false;
4750 const struct radv_image_plane *plane = &iview->image->planes[0];
4751 const struct radeon_surf *surf = &plane->surface;
4752
4753 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4754
4755 memset(ds, 0, sizeof(*ds));
4756 switch (iview->image->vk_format) {
4757 case VK_FORMAT_D24_UNORM_S8_UINT:
4758 case VK_FORMAT_X8_D24_UNORM_PACK32:
4759 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4760 ds->offset_scale = 2.0f;
4761 break;
4762 case VK_FORMAT_D16_UNORM:
4763 case VK_FORMAT_D16_UNORM_S8_UINT:
4764 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4765 ds->offset_scale = 4.0f;
4766 break;
4767 case VK_FORMAT_D32_SFLOAT:
4768 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4769 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4770 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4771 ds->offset_scale = 1.0f;
4772 break;
4773 case VK_FORMAT_S8_UINT:
4774 stencil_only = true;
4775 break;
4776 default:
4777 break;
4778 }
4779
4780 format = radv_translate_dbformat(iview->image->vk_format);
4781 stencil_format = surf->has_stencil ?
4782 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4783
4784 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4785 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4786 S_028008_SLICE_MAX(max_slice);
4787 if (device->physical_device->rad_info.chip_class >= GFX10) {
4788 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4789 S_028008_SLICE_MAX_HI(max_slice >> 11);
4790 }
4791
4792 ds->db_htile_data_base = 0;
4793 ds->db_htile_surface = 0;
4794
4795 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4796 s_offs = z_offs = va;
4797
4798 if (device->physical_device->rad_info.chip_class >= GFX9) {
4799 assert(surf->u.gfx9.surf_offset == 0);
4800 s_offs += surf->u.gfx9.stencil_offset;
4801
4802 ds->db_z_info = S_028038_FORMAT(format) |
4803 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4804 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4805 S_028038_MAXMIP(iview->image->info.levels - 1) |
4806 S_028038_ZRANGE_PRECISION(1);
4807 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4808 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4809
4810 if (device->physical_device->rad_info.chip_class == GFX9) {
4811 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4812 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4813 }
4814
4815 ds->db_depth_view |= S_028008_MIPID(level);
4816 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4817 S_02801C_Y_MAX(iview->image->info.height - 1);
4818
4819 if (radv_htile_enabled(iview->image, level)) {
4820 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4821
4822 if (radv_image_is_tc_compat_htile(iview->image)) {
4823 unsigned max_zplanes =
4824 radv_calc_decompress_on_z_planes(device, iview);
4825
4826 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4827
4828 if (device->physical_device->rad_info.chip_class >= GFX10) {
4829 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4830 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4831 } else {
4832 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4833 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4834 }
4835 }
4836
4837 if (!surf->has_stencil)
4838 /* Use all of the htile_buffer for depth if there's no stencil. */
4839 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4840 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4841 iview->image->htile_offset;
4842 ds->db_htile_data_base = va >> 8;
4843 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4844 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4845
4846 if (device->physical_device->rad_info.chip_class == GFX9) {
4847 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4848 }
4849 }
4850 } else {
4851 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4852
4853 if (stencil_only)
4854 level_info = &surf->u.legacy.stencil_level[level];
4855
4856 z_offs += surf->u.legacy.level[level].offset;
4857 s_offs += surf->u.legacy.stencil_level[level].offset;
4858
4859 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4860 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4861 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4862
4863 if (iview->image->info.samples > 1)
4864 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4865
4866 if (device->physical_device->rad_info.chip_class >= GFX7) {
4867 struct radeon_info *info = &device->physical_device->rad_info;
4868 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4869 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4870 unsigned macro_index = surf->u.legacy.macro_tile_index;
4871 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4872 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4873 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4874
4875 if (stencil_only)
4876 tile_mode = stencil_tile_mode;
4877
4878 ds->db_depth_info |=
4879 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4880 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4881 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4882 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4883 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4884 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4885 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4886 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4887 } else {
4888 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4889 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4890 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4891 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4892 if (stencil_only)
4893 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4894 }
4895
4896 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4897 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4898 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4899
4900 if (radv_htile_enabled(iview->image, level)) {
4901 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4902
4903 if (!surf->has_stencil &&
4904 !radv_image_is_tc_compat_htile(iview->image))
4905 /* Use all of the htile_buffer for depth if there's no stencil. */
4906 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4907
4908 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4909 iview->image->htile_offset;
4910 ds->db_htile_data_base = va >> 8;
4911 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4912
4913 if (radv_image_is_tc_compat_htile(iview->image)) {
4914 unsigned max_zplanes =
4915 radv_calc_decompress_on_z_planes(device, iview);
4916
4917 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4918 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4919 }
4920 }
4921 }
4922
4923 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4924 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4925 }
4926
4927 VkResult radv_CreateFramebuffer(
4928 VkDevice _device,
4929 const VkFramebufferCreateInfo* pCreateInfo,
4930 const VkAllocationCallbacks* pAllocator,
4931 VkFramebuffer* pFramebuffer)
4932 {
4933 RADV_FROM_HANDLE(radv_device, device, _device);
4934 struct radv_framebuffer *framebuffer;
4935 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4936 vk_find_struct_const(pCreateInfo->pNext,
4937 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4938
4939 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4940
4941 size_t size = sizeof(*framebuffer);
4942 if (!imageless_create_info)
4943 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4944 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4945 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4946 if (framebuffer == NULL)
4947 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4948
4949 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4950 framebuffer->width = pCreateInfo->width;
4951 framebuffer->height = pCreateInfo->height;
4952 framebuffer->layers = pCreateInfo->layers;
4953 if (imageless_create_info) {
4954 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4955 const VkFramebufferAttachmentImageInfoKHR *attachment =
4956 imageless_create_info->pAttachmentImageInfos + i;
4957 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4958 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4959 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4960 }
4961 } else {
4962 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4963 VkImageView _iview = pCreateInfo->pAttachments[i];
4964 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4965 framebuffer->attachments[i] = iview;
4966 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4967 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4968 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4969 }
4970 }
4971
4972 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4973 return VK_SUCCESS;
4974 }
4975
4976 void radv_DestroyFramebuffer(
4977 VkDevice _device,
4978 VkFramebuffer _fb,
4979 const VkAllocationCallbacks* pAllocator)
4980 {
4981 RADV_FROM_HANDLE(radv_device, device, _device);
4982 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4983
4984 if (!fb)
4985 return;
4986 vk_free2(&device->alloc, pAllocator, fb);
4987 }
4988
4989 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4990 {
4991 switch (address_mode) {
4992 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4993 return V_008F30_SQ_TEX_WRAP;
4994 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4995 return V_008F30_SQ_TEX_MIRROR;
4996 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4997 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4998 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4999 return V_008F30_SQ_TEX_CLAMP_BORDER;
5000 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
5001 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
5002 default:
5003 unreachable("illegal tex wrap mode");
5004 break;
5005 }
5006 }
5007
5008 static unsigned
5009 radv_tex_compare(VkCompareOp op)
5010 {
5011 switch (op) {
5012 case VK_COMPARE_OP_NEVER:
5013 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
5014 case VK_COMPARE_OP_LESS:
5015 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
5016 case VK_COMPARE_OP_EQUAL:
5017 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
5018 case VK_COMPARE_OP_LESS_OR_EQUAL:
5019 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
5020 case VK_COMPARE_OP_GREATER:
5021 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
5022 case VK_COMPARE_OP_NOT_EQUAL:
5023 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
5024 case VK_COMPARE_OP_GREATER_OR_EQUAL:
5025 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
5026 case VK_COMPARE_OP_ALWAYS:
5027 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
5028 default:
5029 unreachable("illegal compare mode");
5030 break;
5031 }
5032 }
5033
5034 static unsigned
5035 radv_tex_filter(VkFilter filter, unsigned max_ansio)
5036 {
5037 switch (filter) {
5038 case VK_FILTER_NEAREST:
5039 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
5040 V_008F38_SQ_TEX_XY_FILTER_POINT);
5041 case VK_FILTER_LINEAR:
5042 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
5043 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
5044 case VK_FILTER_CUBIC_IMG:
5045 default:
5046 fprintf(stderr, "illegal texture filter");
5047 return 0;
5048 }
5049 }
5050
5051 static unsigned
5052 radv_tex_mipfilter(VkSamplerMipmapMode mode)
5053 {
5054 switch (mode) {
5055 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
5056 return V_008F38_SQ_TEX_Z_FILTER_POINT;
5057 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
5058 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
5059 default:
5060 return V_008F38_SQ_TEX_Z_FILTER_NONE;
5061 }
5062 }
5063
5064 static unsigned
5065 radv_tex_bordercolor(VkBorderColor bcolor)
5066 {
5067 switch (bcolor) {
5068 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
5069 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
5070 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
5071 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
5072 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
5073 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
5074 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
5075 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
5076 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
5077 default:
5078 break;
5079 }
5080 return 0;
5081 }
5082
5083 static unsigned
5084 radv_tex_aniso_filter(unsigned filter)
5085 {
5086 if (filter < 2)
5087 return 0;
5088 if (filter < 4)
5089 return 1;
5090 if (filter < 8)
5091 return 2;
5092 if (filter < 16)
5093 return 3;
5094 return 4;
5095 }
5096
5097 static unsigned
5098 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
5099 {
5100 switch (mode) {
5101 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
5102 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5103 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5104 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5105 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5106 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5107 default:
5108 break;
5109 }
5110 return 0;
5111 }
5112
5113 static uint32_t
5114 radv_get_max_anisotropy(struct radv_device *device,
5115 const VkSamplerCreateInfo *pCreateInfo)
5116 {
5117 if (device->force_aniso >= 0)
5118 return device->force_aniso;
5119
5120 if (pCreateInfo->anisotropyEnable &&
5121 pCreateInfo->maxAnisotropy > 1.0f)
5122 return (uint32_t)pCreateInfo->maxAnisotropy;
5123
5124 return 0;
5125 }
5126
5127 static void
5128 radv_init_sampler(struct radv_device *device,
5129 struct radv_sampler *sampler,
5130 const VkSamplerCreateInfo *pCreateInfo)
5131 {
5132 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5133 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5134 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5135 device->physical_device->rad_info.chip_class == GFX9;
5136 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5137
5138 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5139 vk_find_struct_const(pCreateInfo->pNext,
5140 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5141 if (sampler_reduction)
5142 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5143
5144 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5145 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5146 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5147 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5148 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5149 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5150 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5151 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5152 S_008F30_DISABLE_CUBE_WRAP(0) |
5153 S_008F30_COMPAT_MODE(compat_mode) |
5154 S_008F30_FILTER_MODE(filter_mode));
5155 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5156 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5157 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5158 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5159 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5160 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5161 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5162 S_008F38_MIP_POINT_PRECLAMP(0));
5163 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5164 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5165
5166 if (device->physical_device->rad_info.chip_class >= GFX10) {
5167 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5168 } else {
5169 sampler->state[2] |=
5170 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5171 S_008F38_FILTER_PREC_FIX(1) |
5172 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5173 }
5174 }
5175
5176 VkResult radv_CreateSampler(
5177 VkDevice _device,
5178 const VkSamplerCreateInfo* pCreateInfo,
5179 const VkAllocationCallbacks* pAllocator,
5180 VkSampler* pSampler)
5181 {
5182 RADV_FROM_HANDLE(radv_device, device, _device);
5183 struct radv_sampler *sampler;
5184
5185 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5186 vk_find_struct_const(pCreateInfo->pNext,
5187 SAMPLER_YCBCR_CONVERSION_INFO);
5188
5189 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5190
5191 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5193 if (!sampler)
5194 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5195
5196 radv_init_sampler(device, sampler, pCreateInfo);
5197
5198 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5199 *pSampler = radv_sampler_to_handle(sampler);
5200
5201 return VK_SUCCESS;
5202 }
5203
5204 void radv_DestroySampler(
5205 VkDevice _device,
5206 VkSampler _sampler,
5207 const VkAllocationCallbacks* pAllocator)
5208 {
5209 RADV_FROM_HANDLE(radv_device, device, _device);
5210 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5211
5212 if (!sampler)
5213 return;
5214 vk_free2(&device->alloc, pAllocator, sampler);
5215 }
5216
5217 /* vk_icd.h does not declare this function, so we declare it here to
5218 * suppress Wmissing-prototypes.
5219 */
5220 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5221 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5222
5223 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5224 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5225 {
5226 /* For the full details on loader interface versioning, see
5227 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5228 * What follows is a condensed summary, to help you navigate the large and
5229 * confusing official doc.
5230 *
5231 * - Loader interface v0 is incompatible with later versions. We don't
5232 * support it.
5233 *
5234 * - In loader interface v1:
5235 * - The first ICD entrypoint called by the loader is
5236 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5237 * entrypoint.
5238 * - The ICD must statically expose no other Vulkan symbol unless it is
5239 * linked with -Bsymbolic.
5240 * - Each dispatchable Vulkan handle created by the ICD must be
5241 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5242 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5243 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5244 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5245 * such loader-managed surfaces.
5246 *
5247 * - Loader interface v2 differs from v1 in:
5248 * - The first ICD entrypoint called by the loader is
5249 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5250 * statically expose this entrypoint.
5251 *
5252 * - Loader interface v3 differs from v2 in:
5253 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5254 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5255 * because the loader no longer does so.
5256 */
5257 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5258 return VK_SUCCESS;
5259 }
5260
5261 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5262 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5263 int *pFD)
5264 {
5265 RADV_FROM_HANDLE(radv_device, device, _device);
5266 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5267
5268 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5269
5270 /* At the moment, we support only the below handle types. */
5271 assert(pGetFdInfo->handleType ==
5272 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5273 pGetFdInfo->handleType ==
5274 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5275
5276 bool ret = radv_get_memory_fd(device, memory, pFD);
5277 if (ret == false)
5278 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5279 return VK_SUCCESS;
5280 }
5281
5282 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5283 VkExternalMemoryHandleTypeFlagBits handleType,
5284 int fd,
5285 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5286 {
5287 RADV_FROM_HANDLE(radv_device, device, _device);
5288
5289 switch (handleType) {
5290 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5291 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5292 return VK_SUCCESS;
5293
5294 default:
5295 /* The valid usage section for this function says:
5296 *
5297 * "handleType must not be one of the handle types defined as
5298 * opaque."
5299 *
5300 * So opaque handle types fall into the default "unsupported" case.
5301 */
5302 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5303 }
5304 }
5305
5306 static VkResult radv_import_opaque_fd(struct radv_device *device,
5307 int fd,
5308 uint32_t *syncobj)
5309 {
5310 uint32_t syncobj_handle = 0;
5311 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5312 if (ret != 0)
5313 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5314
5315 if (*syncobj)
5316 device->ws->destroy_syncobj(device->ws, *syncobj);
5317
5318 *syncobj = syncobj_handle;
5319 close(fd);
5320
5321 return VK_SUCCESS;
5322 }
5323
5324 static VkResult radv_import_sync_fd(struct radv_device *device,
5325 int fd,
5326 uint32_t *syncobj)
5327 {
5328 /* If we create a syncobj we do it locally so that if we have an error, we don't
5329 * leave a syncobj in an undetermined state in the fence. */
5330 uint32_t syncobj_handle = *syncobj;
5331 if (!syncobj_handle) {
5332 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5333 if (ret) {
5334 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5335 }
5336 }
5337
5338 if (fd == -1) {
5339 device->ws->signal_syncobj(device->ws, syncobj_handle);
5340 } else {
5341 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5342 if (ret != 0)
5343 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5344 }
5345
5346 *syncobj = syncobj_handle;
5347 if (fd != -1)
5348 close(fd);
5349
5350 return VK_SUCCESS;
5351 }
5352
5353 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5354 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5355 {
5356 RADV_FROM_HANDLE(radv_device, device, _device);
5357 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5358 uint32_t *syncobj_dst = NULL;
5359
5360 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5361 syncobj_dst = &sem->temp_syncobj;
5362 } else {
5363 syncobj_dst = &sem->syncobj;
5364 }
5365
5366 switch(pImportSemaphoreFdInfo->handleType) {
5367 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5368 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5369 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5370 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5371 default:
5372 unreachable("Unhandled semaphore handle type");
5373 }
5374 }
5375
5376 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5377 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5378 int *pFd)
5379 {
5380 RADV_FROM_HANDLE(radv_device, device, _device);
5381 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5382 int ret;
5383 uint32_t syncobj_handle;
5384
5385 if (sem->temp_syncobj)
5386 syncobj_handle = sem->temp_syncobj;
5387 else
5388 syncobj_handle = sem->syncobj;
5389
5390 switch(pGetFdInfo->handleType) {
5391 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5392 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5393 break;
5394 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5395 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5396 if (!ret) {
5397 if (sem->temp_syncobj) {
5398 close (sem->temp_syncobj);
5399 sem->temp_syncobj = 0;
5400 } else {
5401 device->ws->reset_syncobj(device->ws, syncobj_handle);
5402 }
5403 }
5404 break;
5405 default:
5406 unreachable("Unhandled semaphore handle type");
5407 }
5408
5409 if (ret)
5410 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5411 return VK_SUCCESS;
5412 }
5413
5414 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5415 VkPhysicalDevice physicalDevice,
5416 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5417 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5418 {
5419 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5420
5421 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5422 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5423 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5424 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5425 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5426 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5427 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5428 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5429 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5430 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5431 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5432 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5433 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5434 } else {
5435 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5436 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5437 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5438 }
5439 }
5440
5441 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5442 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5443 {
5444 RADV_FROM_HANDLE(radv_device, device, _device);
5445 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5446 uint32_t *syncobj_dst = NULL;
5447
5448
5449 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5450 syncobj_dst = &fence->temp_syncobj;
5451 } else {
5452 syncobj_dst = &fence->syncobj;
5453 }
5454
5455 switch(pImportFenceFdInfo->handleType) {
5456 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5457 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5458 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5459 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5460 default:
5461 unreachable("Unhandled fence handle type");
5462 }
5463 }
5464
5465 VkResult radv_GetFenceFdKHR(VkDevice _device,
5466 const VkFenceGetFdInfoKHR *pGetFdInfo,
5467 int *pFd)
5468 {
5469 RADV_FROM_HANDLE(radv_device, device, _device);
5470 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5471 int ret;
5472 uint32_t syncobj_handle;
5473
5474 if (fence->temp_syncobj)
5475 syncobj_handle = fence->temp_syncobj;
5476 else
5477 syncobj_handle = fence->syncobj;
5478
5479 switch(pGetFdInfo->handleType) {
5480 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5481 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5482 break;
5483 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5484 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5485 if (!ret) {
5486 if (fence->temp_syncobj) {
5487 close (fence->temp_syncobj);
5488 fence->temp_syncobj = 0;
5489 } else {
5490 device->ws->reset_syncobj(device->ws, syncobj_handle);
5491 }
5492 }
5493 break;
5494 default:
5495 unreachable("Unhandled fence handle type");
5496 }
5497
5498 if (ret)
5499 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5500 return VK_SUCCESS;
5501 }
5502
5503 void radv_GetPhysicalDeviceExternalFenceProperties(
5504 VkPhysicalDevice physicalDevice,
5505 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5506 VkExternalFenceProperties *pExternalFenceProperties)
5507 {
5508 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5509
5510 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5511 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5512 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5513 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5514 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5515 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5516 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5517 } else {
5518 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5519 pExternalFenceProperties->compatibleHandleTypes = 0;
5520 pExternalFenceProperties->externalFenceFeatures = 0;
5521 }
5522 }
5523
5524 VkResult
5525 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5526 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5527 const VkAllocationCallbacks* pAllocator,
5528 VkDebugReportCallbackEXT* pCallback)
5529 {
5530 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5531 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5532 pCreateInfo, pAllocator, &instance->alloc,
5533 pCallback);
5534 }
5535
5536 void
5537 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5538 VkDebugReportCallbackEXT _callback,
5539 const VkAllocationCallbacks* pAllocator)
5540 {
5541 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5542 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5543 _callback, pAllocator, &instance->alloc);
5544 }
5545
5546 void
5547 radv_DebugReportMessageEXT(VkInstance _instance,
5548 VkDebugReportFlagsEXT flags,
5549 VkDebugReportObjectTypeEXT objectType,
5550 uint64_t object,
5551 size_t location,
5552 int32_t messageCode,
5553 const char* pLayerPrefix,
5554 const char* pMessage)
5555 {
5556 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5557 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5558 object, location, messageCode, pLayerPrefix, pMessage);
5559 }
5560
5561 void
5562 radv_GetDeviceGroupPeerMemoryFeatures(
5563 VkDevice device,
5564 uint32_t heapIndex,
5565 uint32_t localDeviceIndex,
5566 uint32_t remoteDeviceIndex,
5567 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5568 {
5569 assert(localDeviceIndex == remoteDeviceIndex);
5570
5571 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5572 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5573 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5574 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5575 }
5576
5577 static const VkTimeDomainEXT radv_time_domains[] = {
5578 VK_TIME_DOMAIN_DEVICE_EXT,
5579 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5580 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5581 };
5582
5583 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5584 VkPhysicalDevice physicalDevice,
5585 uint32_t *pTimeDomainCount,
5586 VkTimeDomainEXT *pTimeDomains)
5587 {
5588 int d;
5589 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5590
5591 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5592 vk_outarray_append(&out, i) {
5593 *i = radv_time_domains[d];
5594 }
5595 }
5596
5597 return vk_outarray_status(&out);
5598 }
5599
5600 static uint64_t
5601 radv_clock_gettime(clockid_t clock_id)
5602 {
5603 struct timespec current;
5604 int ret;
5605
5606 ret = clock_gettime(clock_id, &current);
5607 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5608 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5609 if (ret < 0)
5610 return 0;
5611
5612 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5613 }
5614
5615 VkResult radv_GetCalibratedTimestampsEXT(
5616 VkDevice _device,
5617 uint32_t timestampCount,
5618 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5619 uint64_t *pTimestamps,
5620 uint64_t *pMaxDeviation)
5621 {
5622 RADV_FROM_HANDLE(radv_device, device, _device);
5623 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5624 int d;
5625 uint64_t begin, end;
5626 uint64_t max_clock_period = 0;
5627
5628 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5629
5630 for (d = 0; d < timestampCount; d++) {
5631 switch (pTimestampInfos[d].timeDomain) {
5632 case VK_TIME_DOMAIN_DEVICE_EXT:
5633 pTimestamps[d] = device->ws->query_value(device->ws,
5634 RADEON_TIMESTAMP);
5635 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5636 max_clock_period = MAX2(max_clock_period, device_period);
5637 break;
5638 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5639 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5640 max_clock_period = MAX2(max_clock_period, 1);
5641 break;
5642
5643 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5644 pTimestamps[d] = begin;
5645 break;
5646 default:
5647 pTimestamps[d] = 0;
5648 break;
5649 }
5650 }
5651
5652 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5653
5654 /*
5655 * The maximum deviation is the sum of the interval over which we
5656 * perform the sampling and the maximum period of any sampled
5657 * clock. That's because the maximum skew between any two sampled
5658 * clock edges is when the sampled clock with the largest period is
5659 * sampled at the end of that period but right at the beginning of the
5660 * sampling interval and some other clock is sampled right at the
5661 * begining of its sampling period and right at the end of the
5662 * sampling interval. Let's assume the GPU has the longest clock
5663 * period and that the application is sampling GPU and monotonic:
5664 *
5665 * s e
5666 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5667 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5668 *
5669 * g
5670 * 0 1 2 3
5671 * GPU -----_____-----_____-----_____-----_____
5672 *
5673 * m
5674 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5675 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5676 *
5677 * Interval <----------------->
5678 * Deviation <-------------------------->
5679 *
5680 * s = read(raw) 2
5681 * g = read(GPU) 1
5682 * m = read(monotonic) 2
5683 * e = read(raw) b
5684 *
5685 * We round the sample interval up by one tick to cover sampling error
5686 * in the interval clock
5687 */
5688
5689 uint64_t sample_interval = end - begin + 1;
5690
5691 *pMaxDeviation = sample_interval + max_clock_period;
5692
5693 return VK_SUCCESS;
5694 }
5695
5696 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5697 VkPhysicalDevice physicalDevice,
5698 VkSampleCountFlagBits samples,
5699 VkMultisamplePropertiesEXT* pMultisampleProperties)
5700 {
5701 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5702 VK_SAMPLE_COUNT_4_BIT |
5703 VK_SAMPLE_COUNT_8_BIT)) {
5704 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5705 } else {
5706 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5707 }
5708 }