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radv: enable VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static bool
53 radv_get_build_id(void *ptr, struct mesa_sha1 *ctx)
54 {
55 uint32_t timestamp;
56
57 #ifdef HAVE_DL_ITERATE_PHDR
58 const struct build_id_note *note = NULL;
59 if ((note = build_id_find_nhdr_for_addr(ptr))) {
60 _mesa_sha1_update(ctx, build_id_data(note), build_id_length(note));
61 } else
62 #endif
63 if (disk_cache_get_function_timestamp(ptr, &timestamp)) {
64 if (!timestamp) {
65 fprintf(stderr, "radv: The provided filesystem timestamp for the cache is bogus!\n");
66 }
67
68 _mesa_sha1_update(ctx, &timestamp, sizeof(timestamp));
69 } else
70 return false;
71 return true;
72 }
73
74 static int
75 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
76 {
77 struct mesa_sha1 ctx;
78 unsigned char sha1[20];
79 unsigned ptr_size = sizeof(void*);
80 memset(uuid, 0, VK_UUID_SIZE);
81
82 if (!radv_get_build_id(radv_device_get_cache_uuid, &ctx) ||
83 !radv_get_build_id(LLVMInitializeAMDGPUTargetInfo, &ctx))
84 return -1;
85
86 _mesa_sha1_update(&ctx, &family, sizeof(family));
87 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
88 _mesa_sha1_final(&ctx, sha1);
89
90 memcpy(uuid, sha1, VK_UUID_SIZE);
91 return 0;
92 }
93
94 static void
95 radv_get_driver_uuid(void *uuid)
96 {
97 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
98 }
99
100 static void
101 radv_get_device_uuid(struct radeon_info *info, void *uuid)
102 {
103 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
104 }
105
106 static void
107 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
108 {
109 const char *chip_string;
110 char llvm_string[32] = {};
111
112 switch (family) {
113 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
114 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
115 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
116 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
117 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
118 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
119 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
120 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
121 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
122 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
123 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
124 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
125 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
126 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
127 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
128 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
129 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
130 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
131 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
132 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
133 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
134 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
135 default: chip_string = "AMD RADV unknown"; break;
136 }
137
138 snprintf(llvm_string, sizeof(llvm_string),
139 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
140 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
141 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
142 }
143
144 static void
145 radv_physical_device_init_mem_types(struct radv_physical_device *device)
146 {
147 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
148 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
149 device->rad_info.vram_vis_size);
150
151 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
152 device->memory_properties.memoryHeapCount = 0;
153 if (device->rad_info.vram_size - visible_vram_size > 0) {
154 vram_index = device->memory_properties.memoryHeapCount++;
155 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
156 .size = device->rad_info.vram_size - visible_vram_size,
157 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
158 };
159 }
160 if (visible_vram_size) {
161 visible_vram_index = device->memory_properties.memoryHeapCount++;
162 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
163 .size = visible_vram_size,
164 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
165 };
166 }
167 if (device->rad_info.gart_size > 0) {
168 gart_index = device->memory_properties.memoryHeapCount++;
169 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
170 .size = device->rad_info.gart_size,
171 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
172 };
173 }
174
175 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
176 unsigned type_count = 0;
177 if (vram_index >= 0) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
181 .heapIndex = vram_index,
182 };
183 }
184 if (gart_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
189 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
190 .heapIndex = gart_index,
191 };
192 }
193 if (visible_vram_index >= 0) {
194 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
195 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
196 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
197 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
199 .heapIndex = visible_vram_index,
200 };
201 }
202 if (gart_index >= 0) {
203 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
204 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
205 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
206 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
207 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
208 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
209 .heapIndex = gart_index,
210 };
211 }
212 device->memory_properties.memoryTypeCount = type_count;
213 }
214
215 static void
216 radv_handle_env_var_force_family(struct radv_physical_device *device)
217 {
218 const char *family = getenv("RADV_FORCE_FAMILY");
219 unsigned i;
220
221 if (!family)
222 return;
223
224 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
225 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
226 /* Override family and chip_class. */
227 device->rad_info.family = i;
228
229 if (i >= CHIP_VEGA10)
230 device->rad_info.chip_class = GFX9;
231 else if (i >= CHIP_TONGA)
232 device->rad_info.chip_class = VI;
233 else if (i >= CHIP_BONAIRE)
234 device->rad_info.chip_class = CIK;
235 else
236 device->rad_info.chip_class = SI;
237
238 return;
239 }
240 }
241
242 fprintf(stderr, "radv: Unknown family: %s\n", family);
243 exit(1);
244 }
245
246 static VkResult
247 radv_physical_device_init(struct radv_physical_device *device,
248 struct radv_instance *instance,
249 drmDevicePtr drm_device)
250 {
251 const char *path = drm_device->nodes[DRM_NODE_RENDER];
252 VkResult result;
253 drmVersionPtr version;
254 int fd;
255 int master_fd = -1;
256
257 fd = open(path, O_RDWR | O_CLOEXEC);
258 if (fd < 0) {
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not open device '%s'", path);
261
262 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
263 }
264
265 version = drmGetVersion(fd);
266 if (!version) {
267 close(fd);
268
269 if (instance->debug_flags & RADV_DEBUG_STARTUP)
270 radv_logi("Could not get the kernel driver version for device '%s'", path);
271
272 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
273 "failed to get version %s: %m", path);
274 }
275
276 if (strcmp(version->name, "amdgpu")) {
277 drmFreeVersion(version);
278 if (master_fd != -1)
279 close(master_fd);
280 close(fd);
281
282 if (instance->debug_flags & RADV_DEBUG_STARTUP)
283 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
284
285 return VK_ERROR_INCOMPATIBLE_DRIVER;
286 }
287 drmFreeVersion(version);
288
289 if (instance->debug_flags & RADV_DEBUG_STARTUP)
290 radv_logi("Found compatible device '%s'.", path);
291
292 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
293 device->instance = instance;
294 assert(strlen(path) < ARRAY_SIZE(device->path));
295 strncpy(device->path, path, ARRAY_SIZE(device->path));
296
297 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
298 instance->perftest_flags);
299 if (!device->ws) {
300 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
301 goto fail;
302 }
303
304 if (instance->enabled_extensions.KHR_display) {
305 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
306 if (master_fd >= 0) {
307 uint32_t accel_working = 0;
308 struct drm_amdgpu_info request = {
309 .return_pointer = (uintptr_t)&accel_working,
310 .return_size = sizeof(accel_working),
311 .query = AMDGPU_INFO_ACCEL_WORKING
312 };
313
314 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
315 close(master_fd);
316 master_fd = -1;
317 }
318 }
319 }
320
321 device->master_fd = master_fd;
322 device->local_fd = fd;
323 device->ws->query_info(device->ws, &device->rad_info);
324
325 radv_handle_env_var_force_family(device);
326
327 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
328
329 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
330 device->ws->destroy(device->ws);
331 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
332 "cannot generate UUID");
333 goto fail;
334 }
335
336 /* These flags affect shader compilation. */
337 uint64_t shader_env_flags =
338 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
339 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
340
341 /* The gpu id is already embedded in the uuid so we just pass "radv"
342 * when creating the cache.
343 */
344 char buf[VK_UUID_SIZE * 2 + 1];
345 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
346 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
347
348 if (device->rad_info.chip_class < VI ||
349 device->rad_info.chip_class > GFX9)
350 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
351
352 radv_get_driver_uuid(&device->device_uuid);
353 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
354
355 if (device->rad_info.family == CHIP_STONEY ||
356 device->rad_info.chip_class >= GFX9) {
357 device->has_rbplus = true;
358 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
359 device->rad_info.family == CHIP_VEGA12 ||
360 device->rad_info.family == CHIP_RAVEN;
361 }
362
363 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
364 * on SI.
365 */
366 device->has_clear_state = device->rad_info.chip_class >= CIK;
367
368 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
369
370 /* Vega10/Raven need a special workaround for a hardware bug. */
371 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
372 device->rad_info.family == CHIP_RAVEN;
373
374 /* Out-of-order primitive rasterization. */
375 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
376 device->rad_info.max_se >= 2;
377 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
378 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
379
380 device->dcc_msaa_allowed =
381 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
382
383 radv_physical_device_init_mem_types(device);
384 radv_fill_device_extension_table(device, &device->supported_extensions);
385
386 result = radv_init_wsi(device);
387 if (result != VK_SUCCESS) {
388 device->ws->destroy(device->ws);
389 vk_error(instance, result);
390 goto fail;
391 }
392
393 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
394 ac_print_gpu_info(&device->rad_info);
395
396 return VK_SUCCESS;
397
398 fail:
399 close(fd);
400 if (master_fd != -1)
401 close(master_fd);
402 return result;
403 }
404
405 static void
406 radv_physical_device_finish(struct radv_physical_device *device)
407 {
408 radv_finish_wsi(device);
409 device->ws->destroy(device->ws);
410 disk_cache_destroy(device->disk_cache);
411 close(device->local_fd);
412 if (device->master_fd != -1)
413 close(device->master_fd);
414 }
415
416 static void *
417 default_alloc_func(void *pUserData, size_t size, size_t align,
418 VkSystemAllocationScope allocationScope)
419 {
420 return malloc(size);
421 }
422
423 static void *
424 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
425 size_t align, VkSystemAllocationScope allocationScope)
426 {
427 return realloc(pOriginal, size);
428 }
429
430 static void
431 default_free_func(void *pUserData, void *pMemory)
432 {
433 free(pMemory);
434 }
435
436 static const VkAllocationCallbacks default_alloc = {
437 .pUserData = NULL,
438 .pfnAllocation = default_alloc_func,
439 .pfnReallocation = default_realloc_func,
440 .pfnFree = default_free_func,
441 };
442
443 static const struct debug_control radv_debug_options[] = {
444 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
445 {"nodcc", RADV_DEBUG_NO_DCC},
446 {"shaders", RADV_DEBUG_DUMP_SHADERS},
447 {"nocache", RADV_DEBUG_NO_CACHE},
448 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
449 {"nohiz", RADV_DEBUG_NO_HIZ},
450 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
451 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
452 {"allbos", RADV_DEBUG_ALL_BOS},
453 {"noibs", RADV_DEBUG_NO_IBS},
454 {"spirv", RADV_DEBUG_DUMP_SPIRV},
455 {"vmfaults", RADV_DEBUG_VM_FAULTS},
456 {"zerovram", RADV_DEBUG_ZERO_VRAM},
457 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
458 {"nosisched", RADV_DEBUG_NO_SISCHED},
459 {"preoptir", RADV_DEBUG_PREOPTIR},
460 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
461 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
462 {"info", RADV_DEBUG_INFO},
463 {"errors", RADV_DEBUG_ERRORS},
464 {"startup", RADV_DEBUG_STARTUP},
465 {"checkir", RADV_DEBUG_CHECKIR},
466 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
467 {NULL, 0}
468 };
469
470 const char *
471 radv_get_debug_option_name(int id)
472 {
473 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
474 return radv_debug_options[id].string;
475 }
476
477 static const struct debug_control radv_perftest_options[] = {
478 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
479 {"sisched", RADV_PERFTEST_SISCHED},
480 {"localbos", RADV_PERFTEST_LOCAL_BOS},
481 {"binning", RADV_PERFTEST_BINNING},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525
526 VkResult radv_CreateInstance(
527 const VkInstanceCreateInfo* pCreateInfo,
528 const VkAllocationCallbacks* pAllocator,
529 VkInstance* pInstance)
530 {
531 struct radv_instance *instance;
532 VkResult result;
533
534 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
535
536 uint32_t client_version;
537 if (pCreateInfo->pApplicationInfo &&
538 pCreateInfo->pApplicationInfo->apiVersion != 0) {
539 client_version = pCreateInfo->pApplicationInfo->apiVersion;
540 } else {
541 radv_EnumerateInstanceVersion(&client_version);
542 }
543
544 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
545 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
546 if (!instance)
547 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
550
551 if (pAllocator)
552 instance->alloc = *pAllocator;
553 else
554 instance->alloc = default_alloc;
555
556 instance->apiVersion = client_version;
557 instance->physicalDeviceCount = -1;
558
559 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
560 radv_debug_options);
561
562 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
563 radv_perftest_options);
564
565
566 if (instance->debug_flags & RADV_DEBUG_STARTUP)
567 radv_logi("Created an instance");
568
569 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
570 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
571 int index = radv_get_instance_extension_index(ext_name);
572
573 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
574 vk_free2(&default_alloc, pAllocator, instance);
575 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
576 }
577
578 instance->enabled_extensions.extensions[index] = true;
579 }
580
581 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
582 if (result != VK_SUCCESS) {
583 vk_free2(&default_alloc, pAllocator, instance);
584 return vk_error(instance, result);
585 }
586
587 _mesa_locale_init();
588
589 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
590
591 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
592
593 *pInstance = radv_instance_to_handle(instance);
594
595 return VK_SUCCESS;
596 }
597
598 void radv_DestroyInstance(
599 VkInstance _instance,
600 const VkAllocationCallbacks* pAllocator)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603
604 if (!instance)
605 return;
606
607 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
608 radv_physical_device_finish(instance->physicalDevices + i);
609 }
610
611 VG(VALGRIND_DESTROY_MEMPOOL(instance));
612
613 _mesa_locale_fini();
614
615 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
616
617 vk_free(&instance->alloc, instance);
618 }
619
620 static VkResult
621 radv_enumerate_devices(struct radv_instance *instance)
622 {
623 /* TODO: Check for more devices ? */
624 drmDevicePtr devices[8];
625 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
626 int max_devices;
627
628 instance->physicalDeviceCount = 0;
629
630 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
631
632 if (instance->debug_flags & RADV_DEBUG_STARTUP)
633 radv_logi("Found %d drm nodes", max_devices);
634
635 if (max_devices < 1)
636 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
637
638 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
639 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
640 devices[i]->bustype == DRM_BUS_PCI &&
641 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
642
643 result = radv_physical_device_init(instance->physicalDevices +
644 instance->physicalDeviceCount,
645 instance,
646 devices[i]);
647 if (result == VK_SUCCESS)
648 ++instance->physicalDeviceCount;
649 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
650 break;
651 }
652 }
653 drmFreeDevices(devices, max_devices);
654
655 return result;
656 }
657
658 VkResult radv_EnumeratePhysicalDevices(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceCount,
661 VkPhysicalDevice* pPhysicalDevices)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDevices) {
674 *pPhysicalDeviceCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
678 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
679 }
680
681 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
682 : VK_SUCCESS;
683 }
684
685 VkResult radv_EnumeratePhysicalDeviceGroups(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceGroupCount,
688 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDeviceGroupProperties) {
701 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
705 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
706 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
708 }
709 }
710 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
711 : VK_SUCCESS;
712 }
713
714 void radv_GetPhysicalDeviceFeatures(
715 VkPhysicalDevice physicalDevice,
716 VkPhysicalDeviceFeatures* pFeatures)
717 {
718 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
719 memset(pFeatures, 0, sizeof(*pFeatures));
720
721 *pFeatures = (VkPhysicalDeviceFeatures) {
722 .robustBufferAccess = true,
723 .fullDrawIndexUint32 = true,
724 .imageCubeArray = true,
725 .independentBlend = true,
726 .geometryShader = true,
727 .tessellationShader = true,
728 .sampleRateShading = true,
729 .dualSrcBlend = true,
730 .logicOp = true,
731 .multiDrawIndirect = true,
732 .drawIndirectFirstInstance = true,
733 .depthClamp = true,
734 .depthBiasClamp = true,
735 .fillModeNonSolid = true,
736 .depthBounds = true,
737 .wideLines = true,
738 .largePoints = true,
739 .alphaToOne = true,
740 .multiViewport = true,
741 .samplerAnisotropy = true,
742 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
743 pdevice->rad_info.family == CHIP_STONEY,
744 .textureCompressionASTC_LDR = false,
745 .textureCompressionBC = true,
746 .occlusionQueryPrecise = true,
747 .pipelineStatisticsQuery = true,
748 .vertexPipelineStoresAndAtomics = true,
749 .fragmentStoresAndAtomics = true,
750 .shaderTessellationAndGeometryPointSize = true,
751 .shaderImageGatherExtended = true,
752 .shaderStorageImageExtendedFormats = true,
753 .shaderStorageImageMultisample = false,
754 .shaderUniformBufferArrayDynamicIndexing = true,
755 .shaderSampledImageArrayDynamicIndexing = true,
756 .shaderStorageBufferArrayDynamicIndexing = true,
757 .shaderStorageImageArrayDynamicIndexing = true,
758 .shaderStorageImageReadWithoutFormat = true,
759 .shaderStorageImageWriteWithoutFormat = true,
760 .shaderClipDistance = true,
761 .shaderCullDistance = true,
762 .shaderFloat64 = true,
763 .shaderInt64 = true,
764 .shaderInt16 = true,
765 .sparseBinding = true,
766 .variableMultisampleRate = true,
767 .inheritedQueries = true,
768 };
769 }
770
771 void radv_GetPhysicalDeviceFeatures2(
772 VkPhysicalDevice physicalDevice,
773 VkPhysicalDeviceFeatures2KHR *pFeatures)
774 {
775 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
776 vk_foreach_struct(ext, pFeatures->pNext) {
777 switch (ext->sType) {
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
779 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
780 features->variablePointersStorageBuffer = true;
781 features->variablePointers = false;
782 break;
783 }
784 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
785 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
786 features->multiview = true;
787 features->multiviewGeometryShader = true;
788 features->multiviewTessellationShader = true;
789 break;
790 }
791 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
792 VkPhysicalDeviceShaderDrawParameterFeatures *features =
793 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
794 features->shaderDrawParameters = true;
795 break;
796 }
797 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
798 VkPhysicalDeviceProtectedMemoryFeatures *features =
799 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
800 features->protectedMemory = false;
801 break;
802 }
803 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
804 VkPhysicalDevice16BitStorageFeatures *features =
805 (VkPhysicalDevice16BitStorageFeatures*)ext;
806 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
807 features->storageBuffer16BitAccess = enabled;
808 features->uniformAndStorageBuffer16BitAccess = enabled;
809 features->storagePushConstant16 = enabled;
810 features->storageInputOutput16 = enabled;
811 break;
812 }
813 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
814 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
815 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
816 features->samplerYcbcrConversion = false;
817 break;
818 }
819 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
820 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
821 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
822 features->shaderInputAttachmentArrayDynamicIndexing = true;
823 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
824 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
825 features->shaderUniformBufferArrayNonUniformIndexing = false;
826 features->shaderSampledImageArrayNonUniformIndexing = false;
827 features->shaderStorageBufferArrayNonUniformIndexing = false;
828 features->shaderStorageImageArrayNonUniformIndexing = false;
829 features->shaderInputAttachmentArrayNonUniformIndexing = false;
830 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
831 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
832 features->descriptorBindingUniformBufferUpdateAfterBind = true;
833 features->descriptorBindingSampledImageUpdateAfterBind = true;
834 features->descriptorBindingStorageImageUpdateAfterBind = true;
835 features->descriptorBindingStorageBufferUpdateAfterBind = true;
836 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
837 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
838 features->descriptorBindingUpdateUnusedWhilePending = true;
839 features->descriptorBindingPartiallyBound = true;
840 features->descriptorBindingVariableDescriptorCount = true;
841 features->runtimeDescriptorArray = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
845 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
846 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
847 features->conditionalRendering = true;
848 features->inheritedConditionalRendering = false;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
852 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
853 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
854 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
855 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
856 break;
857 }
858 default:
859 break;
860 }
861 }
862 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
863 }
864
865 void radv_GetPhysicalDeviceProperties(
866 VkPhysicalDevice physicalDevice,
867 VkPhysicalDeviceProperties* pProperties)
868 {
869 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
870 VkSampleCountFlags sample_counts = 0xf;
871
872 /* make sure that the entire descriptor set is addressable with a signed
873 * 32-bit int. So the sum of all limits scaled by descriptor size has to
874 * be at most 2 GiB. the combined image & samples object count as one of
875 * both. This limit is for the pipeline layout, not for the set layout, but
876 * there is no set limit, so we just set a pipeline limit. I don't think
877 * any app is going to hit this soon. */
878 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
879 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
880 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
881 32 /* sampler, largest when combined with image */ +
882 64 /* sampled image */ +
883 64 /* storage image */);
884
885 VkPhysicalDeviceLimits limits = {
886 .maxImageDimension1D = (1 << 14),
887 .maxImageDimension2D = (1 << 14),
888 .maxImageDimension3D = (1 << 11),
889 .maxImageDimensionCube = (1 << 14),
890 .maxImageArrayLayers = (1 << 11),
891 .maxTexelBufferElements = 128 * 1024 * 1024,
892 .maxUniformBufferRange = UINT32_MAX,
893 .maxStorageBufferRange = UINT32_MAX,
894 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
895 .maxMemoryAllocationCount = UINT32_MAX,
896 .maxSamplerAllocationCount = 64 * 1024,
897 .bufferImageGranularity = 64, /* A cache line */
898 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
899 .maxBoundDescriptorSets = MAX_SETS,
900 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
901 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
902 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
903 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
904 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
905 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
906 .maxPerStageResources = max_descriptor_set_size,
907 .maxDescriptorSetSamplers = max_descriptor_set_size,
908 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
909 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
910 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
911 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
912 .maxDescriptorSetSampledImages = max_descriptor_set_size,
913 .maxDescriptorSetStorageImages = max_descriptor_set_size,
914 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
915 .maxVertexInputAttributes = 32,
916 .maxVertexInputBindings = 32,
917 .maxVertexInputAttributeOffset = 2047,
918 .maxVertexInputBindingStride = 2048,
919 .maxVertexOutputComponents = 128,
920 .maxTessellationGenerationLevel = 64,
921 .maxTessellationPatchSize = 32,
922 .maxTessellationControlPerVertexInputComponents = 128,
923 .maxTessellationControlPerVertexOutputComponents = 128,
924 .maxTessellationControlPerPatchOutputComponents = 120,
925 .maxTessellationControlTotalOutputComponents = 4096,
926 .maxTessellationEvaluationInputComponents = 128,
927 .maxTessellationEvaluationOutputComponents = 128,
928 .maxGeometryShaderInvocations = 127,
929 .maxGeometryInputComponents = 64,
930 .maxGeometryOutputComponents = 128,
931 .maxGeometryOutputVertices = 256,
932 .maxGeometryTotalOutputComponents = 1024,
933 .maxFragmentInputComponents = 128,
934 .maxFragmentOutputAttachments = 8,
935 .maxFragmentDualSrcAttachments = 1,
936 .maxFragmentCombinedOutputResources = 8,
937 .maxComputeSharedMemorySize = 32768,
938 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
939 .maxComputeWorkGroupInvocations = 2048,
940 .maxComputeWorkGroupSize = {
941 2048,
942 2048,
943 2048
944 },
945 .subPixelPrecisionBits = 4 /* FIXME */,
946 .subTexelPrecisionBits = 4 /* FIXME */,
947 .mipmapPrecisionBits = 4 /* FIXME */,
948 .maxDrawIndexedIndexValue = UINT32_MAX,
949 .maxDrawIndirectCount = UINT32_MAX,
950 .maxSamplerLodBias = 16,
951 .maxSamplerAnisotropy = 16,
952 .maxViewports = MAX_VIEWPORTS,
953 .maxViewportDimensions = { (1 << 14), (1 << 14) },
954 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
955 .viewportSubPixelBits = 8,
956 .minMemoryMapAlignment = 4096, /* A page */
957 .minTexelBufferOffsetAlignment = 1,
958 .minUniformBufferOffsetAlignment = 4,
959 .minStorageBufferOffsetAlignment = 4,
960 .minTexelOffset = -32,
961 .maxTexelOffset = 31,
962 .minTexelGatherOffset = -32,
963 .maxTexelGatherOffset = 31,
964 .minInterpolationOffset = -2,
965 .maxInterpolationOffset = 2,
966 .subPixelInterpolationOffsetBits = 8,
967 .maxFramebufferWidth = (1 << 14),
968 .maxFramebufferHeight = (1 << 14),
969 .maxFramebufferLayers = (1 << 10),
970 .framebufferColorSampleCounts = sample_counts,
971 .framebufferDepthSampleCounts = sample_counts,
972 .framebufferStencilSampleCounts = sample_counts,
973 .framebufferNoAttachmentsSampleCounts = sample_counts,
974 .maxColorAttachments = MAX_RTS,
975 .sampledImageColorSampleCounts = sample_counts,
976 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
977 .sampledImageDepthSampleCounts = sample_counts,
978 .sampledImageStencilSampleCounts = sample_counts,
979 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
980 .maxSampleMaskWords = 1,
981 .timestampComputeAndGraphics = true,
982 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
983 .maxClipDistances = 8,
984 .maxCullDistances = 8,
985 .maxCombinedClipAndCullDistances = 8,
986 .discreteQueuePriorities = 1,
987 .pointSizeRange = { 0.125, 255.875 },
988 .lineWidthRange = { 0.0, 7.9921875 },
989 .pointSizeGranularity = (1.0 / 8.0),
990 .lineWidthGranularity = (1.0 / 128.0),
991 .strictLines = false, /* FINISHME */
992 .standardSampleLocations = true,
993 .optimalBufferCopyOffsetAlignment = 128,
994 .optimalBufferCopyRowPitchAlignment = 128,
995 .nonCoherentAtomSize = 64,
996 };
997
998 *pProperties = (VkPhysicalDeviceProperties) {
999 .apiVersion = radv_physical_device_api_version(pdevice),
1000 .driverVersion = vk_get_driver_version(),
1001 .vendorID = ATI_VENDOR_ID,
1002 .deviceID = pdevice->rad_info.pci_id,
1003 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1004 .limits = limits,
1005 .sparseProperties = {0},
1006 };
1007
1008 strcpy(pProperties->deviceName, pdevice->name);
1009 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1010 }
1011
1012 void radv_GetPhysicalDeviceProperties2(
1013 VkPhysicalDevice physicalDevice,
1014 VkPhysicalDeviceProperties2KHR *pProperties)
1015 {
1016 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1017 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1018
1019 vk_foreach_struct(ext, pProperties->pNext) {
1020 switch (ext->sType) {
1021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1022 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1023 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1024 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1025 break;
1026 }
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1028 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1029 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1030 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1031 properties->deviceLUIDValid = false;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1035 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1036 properties->maxMultiviewViewCount = MAX_VIEWS;
1037 properties->maxMultiviewInstanceIndex = INT_MAX;
1038 break;
1039 }
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1041 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1042 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1043 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1044 break;
1045 }
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1047 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1048 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1049 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1050 break;
1051 }
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1053 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1054 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1055 properties->minImportedHostPointerAlignment = 4096;
1056 break;
1057 }
1058 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1059 VkPhysicalDeviceSubgroupProperties *properties =
1060 (VkPhysicalDeviceSubgroupProperties*)ext;
1061 properties->subgroupSize = 64;
1062 properties->supportedStages = VK_SHADER_STAGE_ALL;
1063 properties->supportedOperations =
1064 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1065 VK_SUBGROUP_FEATURE_BASIC_BIT |
1066 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1067 VK_SUBGROUP_FEATURE_QUAD_BIT |
1068 VK_SUBGROUP_FEATURE_VOTE_BIT;
1069 if (pdevice->rad_info.chip_class >= VI) {
1070 properties->supportedOperations |=
1071 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1072 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1073 }
1074 properties->quadOperationsInAllStages = true;
1075 break;
1076 }
1077 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1078 VkPhysicalDeviceMaintenance3Properties *properties =
1079 (VkPhysicalDeviceMaintenance3Properties*)ext;
1080 /* Make sure everything is addressable by a signed 32-bit int, and
1081 * our largest descriptors are 96 bytes. */
1082 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1083 /* Our buffer size fields allow only this much */
1084 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1085 break;
1086 }
1087 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1088 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1089 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1090 /* GFX6-8 only support single channel min/max filter. */
1091 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1092 properties->filterMinmaxSingleComponentFormats = true;
1093 break;
1094 }
1095 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1096 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1097 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1098
1099 /* Shader engines. */
1100 properties->shaderEngineCount =
1101 pdevice->rad_info.max_se;
1102 properties->shaderArraysPerEngineCount =
1103 pdevice->rad_info.max_sh_per_se;
1104 properties->computeUnitsPerShaderArray =
1105 pdevice->rad_info.num_good_compute_units /
1106 (pdevice->rad_info.max_se *
1107 pdevice->rad_info.max_sh_per_se);
1108 properties->simdPerComputeUnit = 4;
1109 properties->wavefrontsPerSimd =
1110 pdevice->rad_info.family == CHIP_TONGA ||
1111 pdevice->rad_info.family == CHIP_ICELAND ||
1112 pdevice->rad_info.family == CHIP_POLARIS10 ||
1113 pdevice->rad_info.family == CHIP_POLARIS11 ||
1114 pdevice->rad_info.family == CHIP_POLARIS12 ||
1115 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1116 properties->wavefrontSize = 64;
1117
1118 /* SGPR. */
1119 properties->sgprsPerSimd =
1120 radv_get_num_physical_sgprs(pdevice);
1121 properties->minSgprAllocation =
1122 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1123 properties->maxSgprAllocation =
1124 pdevice->rad_info.family == CHIP_TONGA ||
1125 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1126 properties->sgprAllocationGranularity =
1127 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1128
1129 /* VGPR. */
1130 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1131 properties->minVgprAllocation = 4;
1132 properties->maxVgprAllocation = 256;
1133 properties->vgprAllocationGranularity = 4;
1134 break;
1135 }
1136 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1137 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1138 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1139 properties->maxVertexAttribDivisor = UINT32_MAX;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1143 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1144 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1145 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1146 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1147 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1148 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1149 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1150 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1151 properties->robustBufferAccessUpdateAfterBind = false;
1152 properties->quadDivergentImplicitLod = false;
1153
1154 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1155 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1156 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1157 32 /* sampler, largest when combined with image */ +
1158 64 /* sampled image */ +
1159 64 /* storage image */);
1160 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1161 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1162 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1163 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1164 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1165 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1166 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1167 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1168 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1169 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1170 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1171 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1172 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1173 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1174 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1178 VkPhysicalDeviceProtectedMemoryProperties *properties =
1179 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1180 properties->protectedNoFault = false;
1181 break;
1182 }
1183 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1184 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1185 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1186 properties->primitiveOverestimationSize = 0;
1187 properties->maxExtraPrimitiveOverestimationSize = 0;
1188 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1189 properties->primitiveUnderestimation = VK_FALSE;
1190 properties->conservativePointAndLineRasterization = VK_FALSE;
1191 properties->degenerateTrianglesRasterized = VK_FALSE;
1192 properties->degenerateLinesRasterized = VK_FALSE;
1193 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1194 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1195 break;
1196 }
1197 default:
1198 break;
1199 }
1200 }
1201 }
1202
1203 static void radv_get_physical_device_queue_family_properties(
1204 struct radv_physical_device* pdevice,
1205 uint32_t* pCount,
1206 VkQueueFamilyProperties** pQueueFamilyProperties)
1207 {
1208 int num_queue_families = 1;
1209 int idx;
1210 if (pdevice->rad_info.num_compute_rings > 0 &&
1211 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1212 num_queue_families++;
1213
1214 if (pQueueFamilyProperties == NULL) {
1215 *pCount = num_queue_families;
1216 return;
1217 }
1218
1219 if (!*pCount)
1220 return;
1221
1222 idx = 0;
1223 if (*pCount >= 1) {
1224 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1225 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1226 VK_QUEUE_COMPUTE_BIT |
1227 VK_QUEUE_TRANSFER_BIT |
1228 VK_QUEUE_SPARSE_BINDING_BIT,
1229 .queueCount = 1,
1230 .timestampValidBits = 64,
1231 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1232 };
1233 idx++;
1234 }
1235
1236 if (pdevice->rad_info.num_compute_rings > 0 &&
1237 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1238 if (*pCount > idx) {
1239 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1240 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1241 VK_QUEUE_TRANSFER_BIT |
1242 VK_QUEUE_SPARSE_BINDING_BIT,
1243 .queueCount = pdevice->rad_info.num_compute_rings,
1244 .timestampValidBits = 64,
1245 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1246 };
1247 idx++;
1248 }
1249 }
1250 *pCount = idx;
1251 }
1252
1253 void radv_GetPhysicalDeviceQueueFamilyProperties(
1254 VkPhysicalDevice physicalDevice,
1255 uint32_t* pCount,
1256 VkQueueFamilyProperties* pQueueFamilyProperties)
1257 {
1258 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1259 if (!pQueueFamilyProperties) {
1260 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1261 return;
1262 }
1263 VkQueueFamilyProperties *properties[] = {
1264 pQueueFamilyProperties + 0,
1265 pQueueFamilyProperties + 1,
1266 pQueueFamilyProperties + 2,
1267 };
1268 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1269 assert(*pCount <= 3);
1270 }
1271
1272 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1273 VkPhysicalDevice physicalDevice,
1274 uint32_t* pCount,
1275 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1276 {
1277 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1278 if (!pQueueFamilyProperties) {
1279 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1280 return;
1281 }
1282 VkQueueFamilyProperties *properties[] = {
1283 &pQueueFamilyProperties[0].queueFamilyProperties,
1284 &pQueueFamilyProperties[1].queueFamilyProperties,
1285 &pQueueFamilyProperties[2].queueFamilyProperties,
1286 };
1287 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1288 assert(*pCount <= 3);
1289 }
1290
1291 void radv_GetPhysicalDeviceMemoryProperties(
1292 VkPhysicalDevice physicalDevice,
1293 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1294 {
1295 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1296
1297 *pMemoryProperties = physical_device->memory_properties;
1298 }
1299
1300 void radv_GetPhysicalDeviceMemoryProperties2(
1301 VkPhysicalDevice physicalDevice,
1302 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1303 {
1304 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1305 &pMemoryProperties->memoryProperties);
1306 }
1307
1308 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1309 VkDevice _device,
1310 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1311 const void *pHostPointer,
1312 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1313 {
1314 RADV_FROM_HANDLE(radv_device, device, _device);
1315
1316 switch (handleType)
1317 {
1318 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1319 const struct radv_physical_device *physical_device = device->physical_device;
1320 uint32_t memoryTypeBits = 0;
1321 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1322 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1323 memoryTypeBits = (1 << i);
1324 break;
1325 }
1326 }
1327 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1328 return VK_SUCCESS;
1329 }
1330 default:
1331 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1332 }
1333 }
1334
1335 static enum radeon_ctx_priority
1336 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1337 {
1338 /* Default to MEDIUM when a specific global priority isn't requested */
1339 if (!pObj)
1340 return RADEON_CTX_PRIORITY_MEDIUM;
1341
1342 switch(pObj->globalPriority) {
1343 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1344 return RADEON_CTX_PRIORITY_REALTIME;
1345 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1346 return RADEON_CTX_PRIORITY_HIGH;
1347 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1348 return RADEON_CTX_PRIORITY_MEDIUM;
1349 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1350 return RADEON_CTX_PRIORITY_LOW;
1351 default:
1352 unreachable("Illegal global priority value");
1353 return RADEON_CTX_PRIORITY_INVALID;
1354 }
1355 }
1356
1357 static int
1358 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1359 uint32_t queue_family_index, int idx,
1360 VkDeviceQueueCreateFlags flags,
1361 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1362 {
1363 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1364 queue->device = device;
1365 queue->queue_family_index = queue_family_index;
1366 queue->queue_idx = idx;
1367 queue->priority = radv_get_queue_global_priority(global_priority);
1368 queue->flags = flags;
1369
1370 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1371 if (!queue->hw_ctx)
1372 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1373
1374 return VK_SUCCESS;
1375 }
1376
1377 static void
1378 radv_queue_finish(struct radv_queue *queue)
1379 {
1380 if (queue->hw_ctx)
1381 queue->device->ws->ctx_destroy(queue->hw_ctx);
1382
1383 if (queue->initial_full_flush_preamble_cs)
1384 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1385 if (queue->initial_preamble_cs)
1386 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1387 if (queue->continue_preamble_cs)
1388 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1389 if (queue->descriptor_bo)
1390 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1391 if (queue->scratch_bo)
1392 queue->device->ws->buffer_destroy(queue->scratch_bo);
1393 if (queue->esgs_ring_bo)
1394 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1395 if (queue->gsvs_ring_bo)
1396 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1397 if (queue->tess_rings_bo)
1398 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1399 if (queue->compute_scratch_bo)
1400 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1401 }
1402
1403 static void
1404 radv_bo_list_init(struct radv_bo_list *bo_list)
1405 {
1406 pthread_mutex_init(&bo_list->mutex, NULL);
1407 bo_list->list.count = bo_list->capacity = 0;
1408 bo_list->list.bos = NULL;
1409 }
1410
1411 static void
1412 radv_bo_list_finish(struct radv_bo_list *bo_list)
1413 {
1414 free(bo_list->list.bos);
1415 pthread_mutex_destroy(&bo_list->mutex);
1416 }
1417
1418 static VkResult radv_bo_list_add(struct radv_device *device,
1419 struct radeon_winsys_bo *bo)
1420 {
1421 struct radv_bo_list *bo_list = &device->bo_list;
1422
1423 if (unlikely(!device->use_global_bo_list))
1424 return VK_SUCCESS;
1425
1426 pthread_mutex_lock(&bo_list->mutex);
1427 if (bo_list->list.count == bo_list->capacity) {
1428 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1429 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1430
1431 if (!data) {
1432 pthread_mutex_unlock(&bo_list->mutex);
1433 return VK_ERROR_OUT_OF_HOST_MEMORY;
1434 }
1435
1436 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1437 bo_list->capacity = capacity;
1438 }
1439
1440 bo_list->list.bos[bo_list->list.count++] = bo;
1441 pthread_mutex_unlock(&bo_list->mutex);
1442 return VK_SUCCESS;
1443 }
1444
1445 static void radv_bo_list_remove(struct radv_device *device,
1446 struct radeon_winsys_bo *bo)
1447 {
1448 struct radv_bo_list *bo_list = &device->bo_list;
1449
1450 if (unlikely(!device->use_global_bo_list))
1451 return;
1452
1453 pthread_mutex_lock(&bo_list->mutex);
1454 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1455 if (bo_list->list.bos[i] == bo) {
1456 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1457 --bo_list->list.count;
1458 break;
1459 }
1460 }
1461 pthread_mutex_unlock(&bo_list->mutex);
1462 }
1463
1464 static void
1465 radv_device_init_gs_info(struct radv_device *device)
1466 {
1467 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1468 device->physical_device->rad_info.family);
1469 }
1470
1471 static int radv_get_device_extension_index(const char *name)
1472 {
1473 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1474 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1475 return i;
1476 }
1477 return -1;
1478 }
1479
1480 static int
1481 radv_get_int_debug_option(const char *name, int default_value)
1482 {
1483 const char *str;
1484 int result;
1485
1486 str = getenv(name);
1487 if (!str) {
1488 result = default_value;
1489 } else {
1490 char *endptr;
1491
1492 result = strtol(str, &endptr, 0);
1493 if (str == endptr) {
1494 /* No digits founs. */
1495 result = default_value;
1496 }
1497 }
1498
1499 return result;
1500 }
1501
1502 VkResult radv_CreateDevice(
1503 VkPhysicalDevice physicalDevice,
1504 const VkDeviceCreateInfo* pCreateInfo,
1505 const VkAllocationCallbacks* pAllocator,
1506 VkDevice* pDevice)
1507 {
1508 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1509 VkResult result;
1510 struct radv_device *device;
1511
1512 bool keep_shader_info = false;
1513
1514 /* Check enabled features */
1515 if (pCreateInfo->pEnabledFeatures) {
1516 VkPhysicalDeviceFeatures supported_features;
1517 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1518 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1519 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1520 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1521 for (uint32_t i = 0; i < num_features; i++) {
1522 if (enabled_feature[i] && !supported_feature[i])
1523 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1524 }
1525 }
1526
1527 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1528 sizeof(*device), 8,
1529 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1530 if (!device)
1531 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1532
1533 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1534 device->instance = physical_device->instance;
1535 device->physical_device = physical_device;
1536
1537 device->ws = physical_device->ws;
1538 if (pAllocator)
1539 device->alloc = *pAllocator;
1540 else
1541 device->alloc = physical_device->instance->alloc;
1542
1543 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1544 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1545 int index = radv_get_device_extension_index(ext_name);
1546 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1547 vk_free(&device->alloc, device);
1548 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1549 }
1550
1551 device->enabled_extensions.extensions[index] = true;
1552 }
1553
1554 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1555
1556 /* With update after bind we can't attach bo's to the command buffer
1557 * from the descriptor set anymore, so we have to use a global BO list.
1558 */
1559 device->use_global_bo_list =
1560 device->enabled_extensions.EXT_descriptor_indexing;
1561
1562 mtx_init(&device->shader_slab_mutex, mtx_plain);
1563 list_inithead(&device->shader_slabs);
1564
1565 radv_bo_list_init(&device->bo_list);
1566
1567 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1568 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1569 uint32_t qfi = queue_create->queueFamilyIndex;
1570 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1571 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1572
1573 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1574
1575 device->queues[qfi] = vk_alloc(&device->alloc,
1576 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1577 if (!device->queues[qfi]) {
1578 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1579 goto fail;
1580 }
1581
1582 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1583
1584 device->queue_count[qfi] = queue_create->queueCount;
1585
1586 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1587 result = radv_queue_init(device, &device->queues[qfi][q],
1588 qfi, q, queue_create->flags,
1589 global_priority);
1590 if (result != VK_SUCCESS)
1591 goto fail;
1592 }
1593 }
1594
1595 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1596 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1597 device->physical_device->rad_info.family == CHIP_RAVEN);
1598
1599 /* Disabled and not implemented for now. */
1600 device->dfsm_allowed = device->pbb_allowed &&
1601 device->physical_device->rad_info.family == CHIP_RAVEN;
1602
1603 #ifdef ANDROID
1604 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1605 #endif
1606
1607 /* The maximum number of scratch waves. Scratch space isn't divided
1608 * evenly between CUs. The number is only a function of the number of CUs.
1609 * We can decrease the constant to decrease the scratch buffer size.
1610 *
1611 * sctx->scratch_waves must be >= the maximum possible size of
1612 * 1 threadgroup, so that the hw doesn't hang from being unable
1613 * to start any.
1614 *
1615 * The recommended value is 4 per CU at most. Higher numbers don't
1616 * bring much benefit, but they still occupy chip resources (think
1617 * async compute). I've seen ~2% performance difference between 4 and 32.
1618 */
1619 uint32_t max_threads_per_block = 2048;
1620 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1621 max_threads_per_block / 64);
1622
1623 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1624
1625 if (device->physical_device->rad_info.chip_class >= CIK) {
1626 /* If the KMD allows it (there is a KMD hw register for it),
1627 * allow launching waves out-of-order.
1628 */
1629 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1630 }
1631
1632 radv_device_init_gs_info(device);
1633
1634 device->tess_offchip_block_dw_size =
1635 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1636 device->has_distributed_tess =
1637 device->physical_device->rad_info.chip_class >= VI &&
1638 device->physical_device->rad_info.max_se >= 2;
1639
1640 if (getenv("RADV_TRACE_FILE")) {
1641 const char *filename = getenv("RADV_TRACE_FILE");
1642
1643 keep_shader_info = true;
1644
1645 if (!radv_init_trace(device))
1646 goto fail;
1647
1648 fprintf(stderr, "*****************************************************************************\n");
1649 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1650 fprintf(stderr, "*****************************************************************************\n");
1651
1652 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1653 radv_dump_enabled_options(device, stderr);
1654 }
1655
1656 device->keep_shader_info = keep_shader_info;
1657
1658 result = radv_device_init_meta(device);
1659 if (result != VK_SUCCESS)
1660 goto fail;
1661
1662 radv_device_init_msaa(device);
1663
1664 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1665 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1666 switch (family) {
1667 case RADV_QUEUE_GENERAL:
1668 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1669 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1670 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1671 break;
1672 case RADV_QUEUE_COMPUTE:
1673 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1674 radeon_emit(device->empty_cs[family], 0);
1675 break;
1676 }
1677 device->ws->cs_finalize(device->empty_cs[family]);
1678 }
1679
1680 if (device->physical_device->rad_info.chip_class >= CIK)
1681 cik_create_gfx_config(device);
1682
1683 VkPipelineCacheCreateInfo ci;
1684 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1685 ci.pNext = NULL;
1686 ci.flags = 0;
1687 ci.pInitialData = NULL;
1688 ci.initialDataSize = 0;
1689 VkPipelineCache pc;
1690 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1691 &ci, NULL, &pc);
1692 if (result != VK_SUCCESS)
1693 goto fail_meta;
1694
1695 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1696
1697 device->force_aniso =
1698 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1699 if (device->force_aniso >= 0) {
1700 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1701 1 << util_logbase2(device->force_aniso));
1702 }
1703
1704 *pDevice = radv_device_to_handle(device);
1705 return VK_SUCCESS;
1706
1707 fail_meta:
1708 radv_device_finish_meta(device);
1709 fail:
1710 radv_bo_list_finish(&device->bo_list);
1711
1712 if (device->trace_bo)
1713 device->ws->buffer_destroy(device->trace_bo);
1714
1715 if (device->gfx_init)
1716 device->ws->buffer_destroy(device->gfx_init);
1717
1718 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1719 for (unsigned q = 0; q < device->queue_count[i]; q++)
1720 radv_queue_finish(&device->queues[i][q]);
1721 if (device->queue_count[i])
1722 vk_free(&device->alloc, device->queues[i]);
1723 }
1724
1725 vk_free(&device->alloc, device);
1726 return result;
1727 }
1728
1729 void radv_DestroyDevice(
1730 VkDevice _device,
1731 const VkAllocationCallbacks* pAllocator)
1732 {
1733 RADV_FROM_HANDLE(radv_device, device, _device);
1734
1735 if (!device)
1736 return;
1737
1738 if (device->trace_bo)
1739 device->ws->buffer_destroy(device->trace_bo);
1740
1741 if (device->gfx_init)
1742 device->ws->buffer_destroy(device->gfx_init);
1743
1744 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1745 for (unsigned q = 0; q < device->queue_count[i]; q++)
1746 radv_queue_finish(&device->queues[i][q]);
1747 if (device->queue_count[i])
1748 vk_free(&device->alloc, device->queues[i]);
1749 if (device->empty_cs[i])
1750 device->ws->cs_destroy(device->empty_cs[i]);
1751 }
1752 radv_device_finish_meta(device);
1753
1754 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1755 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1756
1757 radv_destroy_shader_slabs(device);
1758
1759 radv_bo_list_finish(&device->bo_list);
1760 vk_free(&device->alloc, device);
1761 }
1762
1763 VkResult radv_EnumerateInstanceLayerProperties(
1764 uint32_t* pPropertyCount,
1765 VkLayerProperties* pProperties)
1766 {
1767 if (pProperties == NULL) {
1768 *pPropertyCount = 0;
1769 return VK_SUCCESS;
1770 }
1771
1772 /* None supported at this time */
1773 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1774 }
1775
1776 VkResult radv_EnumerateDeviceLayerProperties(
1777 VkPhysicalDevice physicalDevice,
1778 uint32_t* pPropertyCount,
1779 VkLayerProperties* pProperties)
1780 {
1781 if (pProperties == NULL) {
1782 *pPropertyCount = 0;
1783 return VK_SUCCESS;
1784 }
1785
1786 /* None supported at this time */
1787 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1788 }
1789
1790 void radv_GetDeviceQueue2(
1791 VkDevice _device,
1792 const VkDeviceQueueInfo2* pQueueInfo,
1793 VkQueue* pQueue)
1794 {
1795 RADV_FROM_HANDLE(radv_device, device, _device);
1796 struct radv_queue *queue;
1797
1798 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1799 if (pQueueInfo->flags != queue->flags) {
1800 /* From the Vulkan 1.1.70 spec:
1801 *
1802 * "The queue returned by vkGetDeviceQueue2 must have the same
1803 * flags value from this structure as that used at device
1804 * creation time in a VkDeviceQueueCreateInfo instance. If no
1805 * matching flags were specified at device creation time then
1806 * pQueue will return VK_NULL_HANDLE."
1807 */
1808 *pQueue = VK_NULL_HANDLE;
1809 return;
1810 }
1811
1812 *pQueue = radv_queue_to_handle(queue);
1813 }
1814
1815 void radv_GetDeviceQueue(
1816 VkDevice _device,
1817 uint32_t queueFamilyIndex,
1818 uint32_t queueIndex,
1819 VkQueue* pQueue)
1820 {
1821 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1822 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1823 .queueFamilyIndex = queueFamilyIndex,
1824 .queueIndex = queueIndex
1825 };
1826
1827 radv_GetDeviceQueue2(_device, &info, pQueue);
1828 }
1829
1830 static void
1831 fill_geom_tess_rings(struct radv_queue *queue,
1832 uint32_t *map,
1833 bool add_sample_positions,
1834 uint32_t esgs_ring_size,
1835 struct radeon_winsys_bo *esgs_ring_bo,
1836 uint32_t gsvs_ring_size,
1837 struct radeon_winsys_bo *gsvs_ring_bo,
1838 uint32_t tess_factor_ring_size,
1839 uint32_t tess_offchip_ring_offset,
1840 uint32_t tess_offchip_ring_size,
1841 struct radeon_winsys_bo *tess_rings_bo)
1842 {
1843 uint64_t esgs_va = 0, gsvs_va = 0;
1844 uint64_t tess_va = 0, tess_offchip_va = 0;
1845 uint32_t *desc = &map[4];
1846
1847 if (esgs_ring_bo)
1848 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1849 if (gsvs_ring_bo)
1850 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1851 if (tess_rings_bo) {
1852 tess_va = radv_buffer_get_va(tess_rings_bo);
1853 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1854 }
1855
1856 /* stride 0, num records - size, add tid, swizzle, elsize4,
1857 index stride 64 */
1858 desc[0] = esgs_va;
1859 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1860 S_008F04_STRIDE(0) |
1861 S_008F04_SWIZZLE_ENABLE(true);
1862 desc[2] = esgs_ring_size;
1863 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1864 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1865 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1866 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1867 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1868 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1869 S_008F0C_ELEMENT_SIZE(1) |
1870 S_008F0C_INDEX_STRIDE(3) |
1871 S_008F0C_ADD_TID_ENABLE(true);
1872
1873 desc += 4;
1874 /* GS entry for ES->GS ring */
1875 /* stride 0, num records - size, elsize0,
1876 index stride 0 */
1877 desc[0] = esgs_va;
1878 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1879 S_008F04_STRIDE(0) |
1880 S_008F04_SWIZZLE_ENABLE(false);
1881 desc[2] = esgs_ring_size;
1882 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1883 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1884 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1885 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1886 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1887 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1888 S_008F0C_ELEMENT_SIZE(0) |
1889 S_008F0C_INDEX_STRIDE(0) |
1890 S_008F0C_ADD_TID_ENABLE(false);
1891
1892 desc += 4;
1893 /* VS entry for GS->VS ring */
1894 /* stride 0, num records - size, elsize0,
1895 index stride 0 */
1896 desc[0] = gsvs_va;
1897 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1898 S_008F04_STRIDE(0) |
1899 S_008F04_SWIZZLE_ENABLE(false);
1900 desc[2] = gsvs_ring_size;
1901 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1902 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1903 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1904 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1905 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1906 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1907 S_008F0C_ELEMENT_SIZE(0) |
1908 S_008F0C_INDEX_STRIDE(0) |
1909 S_008F0C_ADD_TID_ENABLE(false);
1910 desc += 4;
1911
1912 /* stride gsvs_itemsize, num records 64
1913 elsize 4, index stride 16 */
1914 /* shader will patch stride and desc[2] */
1915 desc[0] = gsvs_va;
1916 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1917 S_008F04_STRIDE(0) |
1918 S_008F04_SWIZZLE_ENABLE(true);
1919 desc[2] = 0;
1920 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1921 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1922 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1923 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1924 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1925 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1926 S_008F0C_ELEMENT_SIZE(1) |
1927 S_008F0C_INDEX_STRIDE(1) |
1928 S_008F0C_ADD_TID_ENABLE(true);
1929 desc += 4;
1930
1931 desc[0] = tess_va;
1932 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1933 S_008F04_STRIDE(0) |
1934 S_008F04_SWIZZLE_ENABLE(false);
1935 desc[2] = tess_factor_ring_size;
1936 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1937 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1938 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1939 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1940 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1941 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1942 S_008F0C_ELEMENT_SIZE(0) |
1943 S_008F0C_INDEX_STRIDE(0) |
1944 S_008F0C_ADD_TID_ENABLE(false);
1945 desc += 4;
1946
1947 desc[0] = tess_offchip_va;
1948 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1949 S_008F04_STRIDE(0) |
1950 S_008F04_SWIZZLE_ENABLE(false);
1951 desc[2] = tess_offchip_ring_size;
1952 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1953 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1954 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1955 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1956 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1957 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1958 S_008F0C_ELEMENT_SIZE(0) |
1959 S_008F0C_INDEX_STRIDE(0) |
1960 S_008F0C_ADD_TID_ENABLE(false);
1961 desc += 4;
1962
1963 /* add sample positions after all rings */
1964 memcpy(desc, queue->device->sample_locations_1x, 8);
1965 desc += 2;
1966 memcpy(desc, queue->device->sample_locations_2x, 16);
1967 desc += 4;
1968 memcpy(desc, queue->device->sample_locations_4x, 32);
1969 desc += 8;
1970 memcpy(desc, queue->device->sample_locations_8x, 64);
1971 desc += 16;
1972 memcpy(desc, queue->device->sample_locations_16x, 128);
1973 }
1974
1975 static unsigned
1976 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1977 {
1978 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1979 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1980 device->physical_device->rad_info.family != CHIP_STONEY;
1981 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1982 unsigned max_offchip_buffers;
1983 unsigned offchip_granularity;
1984 unsigned hs_offchip_param;
1985
1986 /*
1987 * Per RadeonSI:
1988 * This must be one less than the maximum number due to a hw limitation.
1989 * Various hardware bugs in SI, CIK, and GFX9 need this.
1990 *
1991 * Per AMDVLK:
1992 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1993 * Gfx7 should limit max_offchip_buffers to 508
1994 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
1995 *
1996 * Follow AMDVLK here.
1997 */
1998 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
1999 device->physical_device->rad_info.chip_class == CIK ||
2000 device->physical_device->rad_info.chip_class == SI)
2001 --max_offchip_buffers_per_se;
2002
2003 max_offchip_buffers = max_offchip_buffers_per_se *
2004 device->physical_device->rad_info.max_se;
2005
2006 switch (device->tess_offchip_block_dw_size) {
2007 default:
2008 assert(0);
2009 /* fall through */
2010 case 8192:
2011 offchip_granularity = V_03093C_X_8K_DWORDS;
2012 break;
2013 case 4096:
2014 offchip_granularity = V_03093C_X_4K_DWORDS;
2015 break;
2016 }
2017
2018 switch (device->physical_device->rad_info.chip_class) {
2019 case SI:
2020 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2021 break;
2022 case CIK:
2023 case VI:
2024 case GFX9:
2025 default:
2026 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2027 break;
2028 }
2029
2030 *max_offchip_buffers_p = max_offchip_buffers;
2031 if (device->physical_device->rad_info.chip_class >= CIK) {
2032 if (device->physical_device->rad_info.chip_class >= VI)
2033 --max_offchip_buffers;
2034 hs_offchip_param =
2035 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2036 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2037 } else {
2038 hs_offchip_param =
2039 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2040 }
2041 return hs_offchip_param;
2042 }
2043
2044 static void
2045 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2046 struct radeon_winsys_bo *esgs_ring_bo,
2047 uint32_t esgs_ring_size,
2048 struct radeon_winsys_bo *gsvs_ring_bo,
2049 uint32_t gsvs_ring_size)
2050 {
2051 if (!esgs_ring_bo && !gsvs_ring_bo)
2052 return;
2053
2054 if (esgs_ring_bo)
2055 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2056
2057 if (gsvs_ring_bo)
2058 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2059
2060 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2061 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2062 radeon_emit(cs, esgs_ring_size >> 8);
2063 radeon_emit(cs, gsvs_ring_size >> 8);
2064 } else {
2065 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2066 radeon_emit(cs, esgs_ring_size >> 8);
2067 radeon_emit(cs, gsvs_ring_size >> 8);
2068 }
2069 }
2070
2071 static void
2072 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2073 unsigned hs_offchip_param, unsigned tf_ring_size,
2074 struct radeon_winsys_bo *tess_rings_bo)
2075 {
2076 uint64_t tf_va;
2077
2078 if (!tess_rings_bo)
2079 return;
2080
2081 tf_va = radv_buffer_get_va(tess_rings_bo);
2082
2083 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2084
2085 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2086 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2087 S_030938_SIZE(tf_ring_size / 4));
2088 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2089 tf_va >> 8);
2090 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2091 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2092 S_030944_BASE_HI(tf_va >> 40));
2093 }
2094 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2095 hs_offchip_param);
2096 } else {
2097 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2098 S_008988_SIZE(tf_ring_size / 4));
2099 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2100 tf_va >> 8);
2101 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2102 hs_offchip_param);
2103 }
2104 }
2105
2106 static void
2107 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2108 struct radeon_winsys_bo *compute_scratch_bo)
2109 {
2110 uint64_t scratch_va;
2111
2112 if (!compute_scratch_bo)
2113 return;
2114
2115 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2116
2117 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2118
2119 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2120 radeon_emit(cs, scratch_va);
2121 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2122 S_008F04_SWIZZLE_ENABLE(1));
2123 }
2124
2125 static void
2126 radv_emit_global_shader_pointers(struct radv_queue *queue,
2127 struct radeon_cmdbuf *cs,
2128 struct radeon_winsys_bo *descriptor_bo)
2129 {
2130 uint64_t va;
2131
2132 if (!descriptor_bo)
2133 return;
2134
2135 va = radv_buffer_get_va(descriptor_bo);
2136
2137 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2138
2139 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2140 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2141 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2142 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2143 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2144
2145 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2146 radv_emit_shader_pointer(queue->device, cs, regs[i],
2147 va, true);
2148 }
2149 } else {
2150 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2151 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2152 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2153 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2154 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2155 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2156
2157 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2158 radv_emit_shader_pointer(queue->device, cs, regs[i],
2159 va, true);
2160 }
2161 }
2162 }
2163
2164 static void
2165 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2166 {
2167 struct radv_device *device = queue->device;
2168
2169 if (device->gfx_init) {
2170 uint64_t va = radv_buffer_get_va(device->gfx_init);
2171
2172 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2173 radeon_emit(cs, va);
2174 radeon_emit(cs, va >> 32);
2175 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2176
2177 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2178 } else {
2179 struct radv_physical_device *physical_device = device->physical_device;
2180 si_emit_graphics(physical_device, cs);
2181 }
2182 }
2183
2184 static void
2185 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2186 {
2187 struct radv_physical_device *physical_device = queue->device->physical_device;
2188 si_emit_compute(physical_device, cs);
2189 }
2190
2191 static VkResult
2192 radv_get_preamble_cs(struct radv_queue *queue,
2193 uint32_t scratch_size,
2194 uint32_t compute_scratch_size,
2195 uint32_t esgs_ring_size,
2196 uint32_t gsvs_ring_size,
2197 bool needs_tess_rings,
2198 bool needs_sample_positions,
2199 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2200 struct radeon_cmdbuf **initial_preamble_cs,
2201 struct radeon_cmdbuf **continue_preamble_cs)
2202 {
2203 struct radeon_winsys_bo *scratch_bo = NULL;
2204 struct radeon_winsys_bo *descriptor_bo = NULL;
2205 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2206 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2207 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2208 struct radeon_winsys_bo *tess_rings_bo = NULL;
2209 struct radeon_cmdbuf *dest_cs[3] = {0};
2210 bool add_tess_rings = false, add_sample_positions = false;
2211 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2212 unsigned max_offchip_buffers;
2213 unsigned hs_offchip_param = 0;
2214 unsigned tess_offchip_ring_offset;
2215 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2216 if (!queue->has_tess_rings) {
2217 if (needs_tess_rings)
2218 add_tess_rings = true;
2219 }
2220 if (!queue->has_sample_positions) {
2221 if (needs_sample_positions)
2222 add_sample_positions = true;
2223 }
2224 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2225 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2226 &max_offchip_buffers);
2227 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2228 tess_offchip_ring_size = max_offchip_buffers *
2229 queue->device->tess_offchip_block_dw_size * 4;
2230
2231 if (scratch_size <= queue->scratch_size &&
2232 compute_scratch_size <= queue->compute_scratch_size &&
2233 esgs_ring_size <= queue->esgs_ring_size &&
2234 gsvs_ring_size <= queue->gsvs_ring_size &&
2235 !add_tess_rings && !add_sample_positions &&
2236 queue->initial_preamble_cs) {
2237 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2238 *initial_preamble_cs = queue->initial_preamble_cs;
2239 *continue_preamble_cs = queue->continue_preamble_cs;
2240 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2241 *continue_preamble_cs = NULL;
2242 return VK_SUCCESS;
2243 }
2244
2245 if (scratch_size > queue->scratch_size) {
2246 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2247 scratch_size,
2248 4096,
2249 RADEON_DOMAIN_VRAM,
2250 ring_bo_flags);
2251 if (!scratch_bo)
2252 goto fail;
2253 } else
2254 scratch_bo = queue->scratch_bo;
2255
2256 if (compute_scratch_size > queue->compute_scratch_size) {
2257 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2258 compute_scratch_size,
2259 4096,
2260 RADEON_DOMAIN_VRAM,
2261 ring_bo_flags);
2262 if (!compute_scratch_bo)
2263 goto fail;
2264
2265 } else
2266 compute_scratch_bo = queue->compute_scratch_bo;
2267
2268 if (esgs_ring_size > queue->esgs_ring_size) {
2269 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2270 esgs_ring_size,
2271 4096,
2272 RADEON_DOMAIN_VRAM,
2273 ring_bo_flags);
2274 if (!esgs_ring_bo)
2275 goto fail;
2276 } else {
2277 esgs_ring_bo = queue->esgs_ring_bo;
2278 esgs_ring_size = queue->esgs_ring_size;
2279 }
2280
2281 if (gsvs_ring_size > queue->gsvs_ring_size) {
2282 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2283 gsvs_ring_size,
2284 4096,
2285 RADEON_DOMAIN_VRAM,
2286 ring_bo_flags);
2287 if (!gsvs_ring_bo)
2288 goto fail;
2289 } else {
2290 gsvs_ring_bo = queue->gsvs_ring_bo;
2291 gsvs_ring_size = queue->gsvs_ring_size;
2292 }
2293
2294 if (add_tess_rings) {
2295 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2296 tess_offchip_ring_offset + tess_offchip_ring_size,
2297 256,
2298 RADEON_DOMAIN_VRAM,
2299 ring_bo_flags);
2300 if (!tess_rings_bo)
2301 goto fail;
2302 } else {
2303 tess_rings_bo = queue->tess_rings_bo;
2304 }
2305
2306 if (scratch_bo != queue->scratch_bo ||
2307 esgs_ring_bo != queue->esgs_ring_bo ||
2308 gsvs_ring_bo != queue->gsvs_ring_bo ||
2309 tess_rings_bo != queue->tess_rings_bo ||
2310 add_sample_positions) {
2311 uint32_t size = 0;
2312 if (gsvs_ring_bo || esgs_ring_bo ||
2313 tess_rings_bo || add_sample_positions) {
2314 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2315 if (add_sample_positions)
2316 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2317 }
2318 else if (scratch_bo)
2319 size = 8; /* 2 dword */
2320
2321 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2322 size,
2323 4096,
2324 RADEON_DOMAIN_VRAM,
2325 RADEON_FLAG_CPU_ACCESS |
2326 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2327 RADEON_FLAG_READ_ONLY);
2328 if (!descriptor_bo)
2329 goto fail;
2330 } else
2331 descriptor_bo = queue->descriptor_bo;
2332
2333 for(int i = 0; i < 3; ++i) {
2334 struct radeon_cmdbuf *cs = NULL;
2335 cs = queue->device->ws->cs_create(queue->device->ws,
2336 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2337 if (!cs)
2338 goto fail;
2339
2340 dest_cs[i] = cs;
2341
2342 if (scratch_bo)
2343 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2344
2345 /* Emit initial configuration. */
2346 switch (queue->queue_family_index) {
2347 case RADV_QUEUE_GENERAL:
2348 radv_init_graphics_state(cs, queue);
2349 break;
2350 case RADV_QUEUE_COMPUTE:
2351 radv_init_compute_state(cs, queue);
2352 break;
2353 case RADV_QUEUE_TRANSFER:
2354 break;
2355 }
2356
2357 if (descriptor_bo != queue->descriptor_bo) {
2358 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2359
2360 if (scratch_bo) {
2361 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2362 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2363 S_008F04_SWIZZLE_ENABLE(1);
2364 map[0] = scratch_va;
2365 map[1] = rsrc1;
2366 }
2367
2368 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2369 add_sample_positions)
2370 fill_geom_tess_rings(queue, map, add_sample_positions,
2371 esgs_ring_size, esgs_ring_bo,
2372 gsvs_ring_size, gsvs_ring_bo,
2373 tess_factor_ring_size,
2374 tess_offchip_ring_offset,
2375 tess_offchip_ring_size,
2376 tess_rings_bo);
2377
2378 queue->device->ws->buffer_unmap(descriptor_bo);
2379 }
2380
2381 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2382 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2383 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2384 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2385 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2386 }
2387
2388 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2389 gsvs_ring_bo, gsvs_ring_size);
2390 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2391 tess_factor_ring_size, tess_rings_bo);
2392 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2393 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2394
2395 if (i == 0) {
2396 si_cs_emit_cache_flush(cs,
2397 queue->device->physical_device->rad_info.chip_class,
2398 NULL, 0,
2399 queue->queue_family_index == RING_COMPUTE &&
2400 queue->device->physical_device->rad_info.chip_class >= CIK,
2401 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2402 RADV_CMD_FLAG_INV_ICACHE |
2403 RADV_CMD_FLAG_INV_SMEM_L1 |
2404 RADV_CMD_FLAG_INV_VMEM_L1 |
2405 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2406 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2407 } else if (i == 1) {
2408 si_cs_emit_cache_flush(cs,
2409 queue->device->physical_device->rad_info.chip_class,
2410 NULL, 0,
2411 queue->queue_family_index == RING_COMPUTE &&
2412 queue->device->physical_device->rad_info.chip_class >= CIK,
2413 RADV_CMD_FLAG_INV_ICACHE |
2414 RADV_CMD_FLAG_INV_SMEM_L1 |
2415 RADV_CMD_FLAG_INV_VMEM_L1 |
2416 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2417 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2418 }
2419
2420 if (!queue->device->ws->cs_finalize(cs))
2421 goto fail;
2422 }
2423
2424 if (queue->initial_full_flush_preamble_cs)
2425 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2426
2427 if (queue->initial_preamble_cs)
2428 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2429
2430 if (queue->continue_preamble_cs)
2431 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2432
2433 queue->initial_full_flush_preamble_cs = dest_cs[0];
2434 queue->initial_preamble_cs = dest_cs[1];
2435 queue->continue_preamble_cs = dest_cs[2];
2436
2437 if (scratch_bo != queue->scratch_bo) {
2438 if (queue->scratch_bo)
2439 queue->device->ws->buffer_destroy(queue->scratch_bo);
2440 queue->scratch_bo = scratch_bo;
2441 queue->scratch_size = scratch_size;
2442 }
2443
2444 if (compute_scratch_bo != queue->compute_scratch_bo) {
2445 if (queue->compute_scratch_bo)
2446 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2447 queue->compute_scratch_bo = compute_scratch_bo;
2448 queue->compute_scratch_size = compute_scratch_size;
2449 }
2450
2451 if (esgs_ring_bo != queue->esgs_ring_bo) {
2452 if (queue->esgs_ring_bo)
2453 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2454 queue->esgs_ring_bo = esgs_ring_bo;
2455 queue->esgs_ring_size = esgs_ring_size;
2456 }
2457
2458 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2459 if (queue->gsvs_ring_bo)
2460 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2461 queue->gsvs_ring_bo = gsvs_ring_bo;
2462 queue->gsvs_ring_size = gsvs_ring_size;
2463 }
2464
2465 if (tess_rings_bo != queue->tess_rings_bo) {
2466 queue->tess_rings_bo = tess_rings_bo;
2467 queue->has_tess_rings = true;
2468 }
2469
2470 if (descriptor_bo != queue->descriptor_bo) {
2471 if (queue->descriptor_bo)
2472 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2473
2474 queue->descriptor_bo = descriptor_bo;
2475 }
2476
2477 if (add_sample_positions)
2478 queue->has_sample_positions = true;
2479
2480 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2481 *initial_preamble_cs = queue->initial_preamble_cs;
2482 *continue_preamble_cs = queue->continue_preamble_cs;
2483 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2484 *continue_preamble_cs = NULL;
2485 return VK_SUCCESS;
2486 fail:
2487 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2488 if (dest_cs[i])
2489 queue->device->ws->cs_destroy(dest_cs[i]);
2490 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2491 queue->device->ws->buffer_destroy(descriptor_bo);
2492 if (scratch_bo && scratch_bo != queue->scratch_bo)
2493 queue->device->ws->buffer_destroy(scratch_bo);
2494 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2495 queue->device->ws->buffer_destroy(compute_scratch_bo);
2496 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2497 queue->device->ws->buffer_destroy(esgs_ring_bo);
2498 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2499 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2500 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2501 queue->device->ws->buffer_destroy(tess_rings_bo);
2502 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2503 }
2504
2505 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2506 struct radv_winsys_sem_counts *counts,
2507 int num_sems,
2508 const VkSemaphore *sems,
2509 VkFence _fence,
2510 bool reset_temp)
2511 {
2512 int syncobj_idx = 0, sem_idx = 0;
2513
2514 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2515 return VK_SUCCESS;
2516
2517 for (uint32_t i = 0; i < num_sems; i++) {
2518 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2519
2520 if (sem->temp_syncobj || sem->syncobj)
2521 counts->syncobj_count++;
2522 else
2523 counts->sem_count++;
2524 }
2525
2526 if (_fence != VK_NULL_HANDLE) {
2527 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2528 if (fence->temp_syncobj || fence->syncobj)
2529 counts->syncobj_count++;
2530 }
2531
2532 if (counts->syncobj_count) {
2533 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2534 if (!counts->syncobj)
2535 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2536 }
2537
2538 if (counts->sem_count) {
2539 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2540 if (!counts->sem) {
2541 free(counts->syncobj);
2542 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2543 }
2544 }
2545
2546 for (uint32_t i = 0; i < num_sems; i++) {
2547 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2548
2549 if (sem->temp_syncobj) {
2550 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2551 }
2552 else if (sem->syncobj)
2553 counts->syncobj[syncobj_idx++] = sem->syncobj;
2554 else {
2555 assert(sem->sem);
2556 counts->sem[sem_idx++] = sem->sem;
2557 }
2558 }
2559
2560 if (_fence != VK_NULL_HANDLE) {
2561 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2562 if (fence->temp_syncobj)
2563 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2564 else if (fence->syncobj)
2565 counts->syncobj[syncobj_idx++] = fence->syncobj;
2566 }
2567
2568 return VK_SUCCESS;
2569 }
2570
2571 static void
2572 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2573 {
2574 free(sem_info->wait.syncobj);
2575 free(sem_info->wait.sem);
2576 free(sem_info->signal.syncobj);
2577 free(sem_info->signal.sem);
2578 }
2579
2580
2581 static void radv_free_temp_syncobjs(struct radv_device *device,
2582 int num_sems,
2583 const VkSemaphore *sems)
2584 {
2585 for (uint32_t i = 0; i < num_sems; i++) {
2586 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2587
2588 if (sem->temp_syncobj) {
2589 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2590 sem->temp_syncobj = 0;
2591 }
2592 }
2593 }
2594
2595 static VkResult
2596 radv_alloc_sem_info(struct radv_instance *instance,
2597 struct radv_winsys_sem_info *sem_info,
2598 int num_wait_sems,
2599 const VkSemaphore *wait_sems,
2600 int num_signal_sems,
2601 const VkSemaphore *signal_sems,
2602 VkFence fence)
2603 {
2604 VkResult ret;
2605 memset(sem_info, 0, sizeof(*sem_info));
2606
2607 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2608 if (ret)
2609 return ret;
2610 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2611 if (ret)
2612 radv_free_sem_info(sem_info);
2613
2614 /* caller can override these */
2615 sem_info->cs_emit_wait = true;
2616 sem_info->cs_emit_signal = true;
2617 return ret;
2618 }
2619
2620 /* Signals fence as soon as all the work currently put on queue is done. */
2621 static VkResult radv_signal_fence(struct radv_queue *queue,
2622 struct radv_fence *fence)
2623 {
2624 int ret;
2625 VkResult result;
2626 struct radv_winsys_sem_info sem_info;
2627
2628 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2629 radv_fence_to_handle(fence));
2630 if (result != VK_SUCCESS)
2631 return result;
2632
2633 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2634 &queue->device->empty_cs[queue->queue_family_index],
2635 1, NULL, NULL, &sem_info, NULL,
2636 false, fence->fence);
2637 radv_free_sem_info(&sem_info);
2638
2639 if (ret)
2640 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2641
2642 return VK_SUCCESS;
2643 }
2644
2645 VkResult radv_QueueSubmit(
2646 VkQueue _queue,
2647 uint32_t submitCount,
2648 const VkSubmitInfo* pSubmits,
2649 VkFence _fence)
2650 {
2651 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2652 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2653 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2654 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2655 int ret;
2656 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2657 uint32_t scratch_size = 0;
2658 uint32_t compute_scratch_size = 0;
2659 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2660 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2661 VkResult result;
2662 bool fence_emitted = false;
2663 bool tess_rings_needed = false;
2664 bool sample_positions_needed = false;
2665
2666 /* Do this first so failing to allocate scratch buffers can't result in
2667 * partially executed submissions. */
2668 for (uint32_t i = 0; i < submitCount; i++) {
2669 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2670 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2671 pSubmits[i].pCommandBuffers[j]);
2672
2673 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2674 compute_scratch_size = MAX2(compute_scratch_size,
2675 cmd_buffer->compute_scratch_size_needed);
2676 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2677 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2678 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2679 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2680 }
2681 }
2682
2683 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2684 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2685 sample_positions_needed, &initial_flush_preamble_cs,
2686 &initial_preamble_cs, &continue_preamble_cs);
2687 if (result != VK_SUCCESS)
2688 return result;
2689
2690 for (uint32_t i = 0; i < submitCount; i++) {
2691 struct radeon_cmdbuf **cs_array;
2692 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2693 bool can_patch = true;
2694 uint32_t advance;
2695 struct radv_winsys_sem_info sem_info;
2696
2697 result = radv_alloc_sem_info(queue->device->instance,
2698 &sem_info,
2699 pSubmits[i].waitSemaphoreCount,
2700 pSubmits[i].pWaitSemaphores,
2701 pSubmits[i].signalSemaphoreCount,
2702 pSubmits[i].pSignalSemaphores,
2703 _fence);
2704 if (result != VK_SUCCESS)
2705 return result;
2706
2707 if (!pSubmits[i].commandBufferCount) {
2708 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2709 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2710 &queue->device->empty_cs[queue->queue_family_index],
2711 1, NULL, NULL,
2712 &sem_info, NULL,
2713 false, base_fence);
2714 if (ret) {
2715 radv_loge("failed to submit CS %d\n", i);
2716 abort();
2717 }
2718 fence_emitted = true;
2719 }
2720 radv_free_sem_info(&sem_info);
2721 continue;
2722 }
2723
2724 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2725 (pSubmits[i].commandBufferCount));
2726
2727 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2728 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2729 pSubmits[i].pCommandBuffers[j]);
2730 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2731
2732 cs_array[j] = cmd_buffer->cs;
2733 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2734 can_patch = false;
2735
2736 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2737 }
2738
2739 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2740 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2741 const struct radv_winsys_bo_list *bo_list = NULL;
2742
2743 advance = MIN2(max_cs_submission,
2744 pSubmits[i].commandBufferCount - j);
2745
2746 if (queue->device->trace_bo)
2747 *queue->device->trace_id_ptr = 0;
2748
2749 sem_info.cs_emit_wait = j == 0;
2750 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2751
2752 if (unlikely(queue->device->use_global_bo_list)) {
2753 pthread_mutex_lock(&queue->device->bo_list.mutex);
2754 bo_list = &queue->device->bo_list.list;
2755 }
2756
2757 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2758 advance, initial_preamble, continue_preamble_cs,
2759 &sem_info, bo_list,
2760 can_patch, base_fence);
2761
2762 if (unlikely(queue->device->use_global_bo_list))
2763 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2764
2765 if (ret) {
2766 radv_loge("failed to submit CS %d\n", i);
2767 abort();
2768 }
2769 fence_emitted = true;
2770 if (queue->device->trace_bo) {
2771 radv_check_gpu_hangs(queue, cs_array[j]);
2772 }
2773 }
2774
2775 radv_free_temp_syncobjs(queue->device,
2776 pSubmits[i].waitSemaphoreCount,
2777 pSubmits[i].pWaitSemaphores);
2778 radv_free_sem_info(&sem_info);
2779 free(cs_array);
2780 }
2781
2782 if (fence) {
2783 if (!fence_emitted) {
2784 result = radv_signal_fence(queue, fence);
2785 if (result != VK_SUCCESS)
2786 return result;
2787 }
2788 fence->submitted = true;
2789 }
2790
2791 return VK_SUCCESS;
2792 }
2793
2794 VkResult radv_QueueWaitIdle(
2795 VkQueue _queue)
2796 {
2797 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2798
2799 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2800 radv_queue_family_to_ring(queue->queue_family_index),
2801 queue->queue_idx);
2802 return VK_SUCCESS;
2803 }
2804
2805 VkResult radv_DeviceWaitIdle(
2806 VkDevice _device)
2807 {
2808 RADV_FROM_HANDLE(radv_device, device, _device);
2809
2810 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2811 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2812 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2813 }
2814 }
2815 return VK_SUCCESS;
2816 }
2817
2818 VkResult radv_EnumerateInstanceExtensionProperties(
2819 const char* pLayerName,
2820 uint32_t* pPropertyCount,
2821 VkExtensionProperties* pProperties)
2822 {
2823 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2824
2825 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2826 if (radv_supported_instance_extensions.extensions[i]) {
2827 vk_outarray_append(&out, prop) {
2828 *prop = radv_instance_extensions[i];
2829 }
2830 }
2831 }
2832
2833 return vk_outarray_status(&out);
2834 }
2835
2836 VkResult radv_EnumerateDeviceExtensionProperties(
2837 VkPhysicalDevice physicalDevice,
2838 const char* pLayerName,
2839 uint32_t* pPropertyCount,
2840 VkExtensionProperties* pProperties)
2841 {
2842 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2843 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2844
2845 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2846 if (device->supported_extensions.extensions[i]) {
2847 vk_outarray_append(&out, prop) {
2848 *prop = radv_device_extensions[i];
2849 }
2850 }
2851 }
2852
2853 return vk_outarray_status(&out);
2854 }
2855
2856 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2857 VkInstance _instance,
2858 const char* pName)
2859 {
2860 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2861
2862 return radv_lookup_entrypoint_checked(pName,
2863 instance ? instance->apiVersion : 0,
2864 instance ? &instance->enabled_extensions : NULL,
2865 NULL);
2866 }
2867
2868 /* The loader wants us to expose a second GetInstanceProcAddr function
2869 * to work around certain LD_PRELOAD issues seen in apps.
2870 */
2871 PUBLIC
2872 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2873 VkInstance instance,
2874 const char* pName);
2875
2876 PUBLIC
2877 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2878 VkInstance instance,
2879 const char* pName)
2880 {
2881 return radv_GetInstanceProcAddr(instance, pName);
2882 }
2883
2884 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2885 VkDevice _device,
2886 const char* pName)
2887 {
2888 RADV_FROM_HANDLE(radv_device, device, _device);
2889
2890 return radv_lookup_entrypoint_checked(pName,
2891 device->instance->apiVersion,
2892 &device->instance->enabled_extensions,
2893 &device->enabled_extensions);
2894 }
2895
2896 bool radv_get_memory_fd(struct radv_device *device,
2897 struct radv_device_memory *memory,
2898 int *pFD)
2899 {
2900 struct radeon_bo_metadata metadata;
2901
2902 if (memory->image) {
2903 radv_init_metadata(device, memory->image, &metadata);
2904 device->ws->buffer_set_metadata(memory->bo, &metadata);
2905 }
2906
2907 return device->ws->buffer_get_fd(device->ws, memory->bo,
2908 pFD);
2909 }
2910
2911 static VkResult radv_alloc_memory(struct radv_device *device,
2912 const VkMemoryAllocateInfo* pAllocateInfo,
2913 const VkAllocationCallbacks* pAllocator,
2914 VkDeviceMemory* pMem)
2915 {
2916 struct radv_device_memory *mem;
2917 VkResult result;
2918 enum radeon_bo_domain domain;
2919 uint32_t flags = 0;
2920 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2921
2922 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2923
2924 if (pAllocateInfo->allocationSize == 0) {
2925 /* Apparently, this is allowed */
2926 *pMem = VK_NULL_HANDLE;
2927 return VK_SUCCESS;
2928 }
2929
2930 const VkImportMemoryFdInfoKHR *import_info =
2931 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2932 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2933 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2934 const VkExportMemoryAllocateInfoKHR *export_info =
2935 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2936 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2937 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2938
2939 const struct wsi_memory_allocate_info *wsi_info =
2940 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2941
2942 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2943 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2944 if (mem == NULL)
2945 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2946
2947 if (wsi_info && wsi_info->implicit_sync)
2948 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2949
2950 if (dedicate_info) {
2951 mem->image = radv_image_from_handle(dedicate_info->image);
2952 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2953 } else {
2954 mem->image = NULL;
2955 mem->buffer = NULL;
2956 }
2957
2958 mem->user_ptr = NULL;
2959
2960 if (import_info) {
2961 assert(import_info->handleType ==
2962 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2963 import_info->handleType ==
2964 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2965 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2966 NULL, NULL);
2967 if (!mem->bo) {
2968 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2969 goto fail;
2970 } else {
2971 close(import_info->fd);
2972 }
2973 } else if (host_ptr_info) {
2974 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2975 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2976 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2977 pAllocateInfo->allocationSize);
2978 if (!mem->bo) {
2979 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2980 goto fail;
2981 } else {
2982 mem->user_ptr = host_ptr_info->pHostPointer;
2983 }
2984 } else {
2985 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2986 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2987 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2988 domain = RADEON_DOMAIN_GTT;
2989 else
2990 domain = RADEON_DOMAIN_VRAM;
2991
2992 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2993 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2994 else
2995 flags |= RADEON_FLAG_CPU_ACCESS;
2996
2997 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2998 flags |= RADEON_FLAG_GTT_WC;
2999
3000 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3001 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3002
3003 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3004 domain, flags);
3005
3006 if (!mem->bo) {
3007 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3008 goto fail;
3009 }
3010 mem->type_index = mem_type_index;
3011 }
3012
3013 result = radv_bo_list_add(device, mem->bo);
3014 if (result != VK_SUCCESS)
3015 goto fail_bo;
3016
3017 *pMem = radv_device_memory_to_handle(mem);
3018
3019 return VK_SUCCESS;
3020
3021 fail_bo:
3022 device->ws->buffer_destroy(mem->bo);
3023 fail:
3024 vk_free2(&device->alloc, pAllocator, mem);
3025
3026 return result;
3027 }
3028
3029 VkResult radv_AllocateMemory(
3030 VkDevice _device,
3031 const VkMemoryAllocateInfo* pAllocateInfo,
3032 const VkAllocationCallbacks* pAllocator,
3033 VkDeviceMemory* pMem)
3034 {
3035 RADV_FROM_HANDLE(radv_device, device, _device);
3036 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3037 }
3038
3039 void radv_FreeMemory(
3040 VkDevice _device,
3041 VkDeviceMemory _mem,
3042 const VkAllocationCallbacks* pAllocator)
3043 {
3044 RADV_FROM_HANDLE(radv_device, device, _device);
3045 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3046
3047 if (mem == NULL)
3048 return;
3049
3050 radv_bo_list_remove(device, mem->bo);
3051 device->ws->buffer_destroy(mem->bo);
3052 mem->bo = NULL;
3053
3054 vk_free2(&device->alloc, pAllocator, mem);
3055 }
3056
3057 VkResult radv_MapMemory(
3058 VkDevice _device,
3059 VkDeviceMemory _memory,
3060 VkDeviceSize offset,
3061 VkDeviceSize size,
3062 VkMemoryMapFlags flags,
3063 void** ppData)
3064 {
3065 RADV_FROM_HANDLE(radv_device, device, _device);
3066 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3067
3068 if (mem == NULL) {
3069 *ppData = NULL;
3070 return VK_SUCCESS;
3071 }
3072
3073 if (mem->user_ptr)
3074 *ppData = mem->user_ptr;
3075 else
3076 *ppData = device->ws->buffer_map(mem->bo);
3077
3078 if (*ppData) {
3079 *ppData += offset;
3080 return VK_SUCCESS;
3081 }
3082
3083 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3084 }
3085
3086 void radv_UnmapMemory(
3087 VkDevice _device,
3088 VkDeviceMemory _memory)
3089 {
3090 RADV_FROM_HANDLE(radv_device, device, _device);
3091 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3092
3093 if (mem == NULL)
3094 return;
3095
3096 if (mem->user_ptr == NULL)
3097 device->ws->buffer_unmap(mem->bo);
3098 }
3099
3100 VkResult radv_FlushMappedMemoryRanges(
3101 VkDevice _device,
3102 uint32_t memoryRangeCount,
3103 const VkMappedMemoryRange* pMemoryRanges)
3104 {
3105 return VK_SUCCESS;
3106 }
3107
3108 VkResult radv_InvalidateMappedMemoryRanges(
3109 VkDevice _device,
3110 uint32_t memoryRangeCount,
3111 const VkMappedMemoryRange* pMemoryRanges)
3112 {
3113 return VK_SUCCESS;
3114 }
3115
3116 void radv_GetBufferMemoryRequirements(
3117 VkDevice _device,
3118 VkBuffer _buffer,
3119 VkMemoryRequirements* pMemoryRequirements)
3120 {
3121 RADV_FROM_HANDLE(radv_device, device, _device);
3122 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3123
3124 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3125
3126 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3127 pMemoryRequirements->alignment = 4096;
3128 else
3129 pMemoryRequirements->alignment = 16;
3130
3131 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3132 }
3133
3134 void radv_GetBufferMemoryRequirements2(
3135 VkDevice device,
3136 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3137 VkMemoryRequirements2KHR* pMemoryRequirements)
3138 {
3139 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3140 &pMemoryRequirements->memoryRequirements);
3141 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3142 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3143 switch (ext->sType) {
3144 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3145 VkMemoryDedicatedRequirementsKHR *req =
3146 (VkMemoryDedicatedRequirementsKHR *) ext;
3147 req->requiresDedicatedAllocation = buffer->shareable;
3148 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3149 break;
3150 }
3151 default:
3152 break;
3153 }
3154 }
3155 }
3156
3157 void radv_GetImageMemoryRequirements(
3158 VkDevice _device,
3159 VkImage _image,
3160 VkMemoryRequirements* pMemoryRequirements)
3161 {
3162 RADV_FROM_HANDLE(radv_device, device, _device);
3163 RADV_FROM_HANDLE(radv_image, image, _image);
3164
3165 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3166
3167 pMemoryRequirements->size = image->size;
3168 pMemoryRequirements->alignment = image->alignment;
3169 }
3170
3171 void radv_GetImageMemoryRequirements2(
3172 VkDevice device,
3173 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3174 VkMemoryRequirements2KHR* pMemoryRequirements)
3175 {
3176 radv_GetImageMemoryRequirements(device, pInfo->image,
3177 &pMemoryRequirements->memoryRequirements);
3178
3179 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3180
3181 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3182 switch (ext->sType) {
3183 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3184 VkMemoryDedicatedRequirementsKHR *req =
3185 (VkMemoryDedicatedRequirementsKHR *) ext;
3186 req->requiresDedicatedAllocation = image->shareable;
3187 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3188 break;
3189 }
3190 default:
3191 break;
3192 }
3193 }
3194 }
3195
3196 void radv_GetImageSparseMemoryRequirements(
3197 VkDevice device,
3198 VkImage image,
3199 uint32_t* pSparseMemoryRequirementCount,
3200 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3201 {
3202 stub();
3203 }
3204
3205 void radv_GetImageSparseMemoryRequirements2(
3206 VkDevice device,
3207 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3208 uint32_t* pSparseMemoryRequirementCount,
3209 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3210 {
3211 stub();
3212 }
3213
3214 void radv_GetDeviceMemoryCommitment(
3215 VkDevice device,
3216 VkDeviceMemory memory,
3217 VkDeviceSize* pCommittedMemoryInBytes)
3218 {
3219 *pCommittedMemoryInBytes = 0;
3220 }
3221
3222 VkResult radv_BindBufferMemory2(VkDevice device,
3223 uint32_t bindInfoCount,
3224 const VkBindBufferMemoryInfoKHR *pBindInfos)
3225 {
3226 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3227 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3228 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3229
3230 if (mem) {
3231 buffer->bo = mem->bo;
3232 buffer->offset = pBindInfos[i].memoryOffset;
3233 } else {
3234 buffer->bo = NULL;
3235 }
3236 }
3237 return VK_SUCCESS;
3238 }
3239
3240 VkResult radv_BindBufferMemory(
3241 VkDevice device,
3242 VkBuffer buffer,
3243 VkDeviceMemory memory,
3244 VkDeviceSize memoryOffset)
3245 {
3246 const VkBindBufferMemoryInfoKHR info = {
3247 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3248 .buffer = buffer,
3249 .memory = memory,
3250 .memoryOffset = memoryOffset
3251 };
3252
3253 return radv_BindBufferMemory2(device, 1, &info);
3254 }
3255
3256 VkResult radv_BindImageMemory2(VkDevice device,
3257 uint32_t bindInfoCount,
3258 const VkBindImageMemoryInfoKHR *pBindInfos)
3259 {
3260 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3261 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3262 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3263
3264 if (mem) {
3265 image->bo = mem->bo;
3266 image->offset = pBindInfos[i].memoryOffset;
3267 } else {
3268 image->bo = NULL;
3269 image->offset = 0;
3270 }
3271 }
3272 return VK_SUCCESS;
3273 }
3274
3275
3276 VkResult radv_BindImageMemory(
3277 VkDevice device,
3278 VkImage image,
3279 VkDeviceMemory memory,
3280 VkDeviceSize memoryOffset)
3281 {
3282 const VkBindImageMemoryInfoKHR info = {
3283 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3284 .image = image,
3285 .memory = memory,
3286 .memoryOffset = memoryOffset
3287 };
3288
3289 return radv_BindImageMemory2(device, 1, &info);
3290 }
3291
3292
3293 static void
3294 radv_sparse_buffer_bind_memory(struct radv_device *device,
3295 const VkSparseBufferMemoryBindInfo *bind)
3296 {
3297 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3298
3299 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3300 struct radv_device_memory *mem = NULL;
3301
3302 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3303 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3304
3305 device->ws->buffer_virtual_bind(buffer->bo,
3306 bind->pBinds[i].resourceOffset,
3307 bind->pBinds[i].size,
3308 mem ? mem->bo : NULL,
3309 bind->pBinds[i].memoryOffset);
3310 }
3311 }
3312
3313 static void
3314 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3315 const VkSparseImageOpaqueMemoryBindInfo *bind)
3316 {
3317 RADV_FROM_HANDLE(radv_image, image, bind->image);
3318
3319 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3320 struct radv_device_memory *mem = NULL;
3321
3322 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3323 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3324
3325 device->ws->buffer_virtual_bind(image->bo,
3326 bind->pBinds[i].resourceOffset,
3327 bind->pBinds[i].size,
3328 mem ? mem->bo : NULL,
3329 bind->pBinds[i].memoryOffset);
3330 }
3331 }
3332
3333 VkResult radv_QueueBindSparse(
3334 VkQueue _queue,
3335 uint32_t bindInfoCount,
3336 const VkBindSparseInfo* pBindInfo,
3337 VkFence _fence)
3338 {
3339 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3340 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3341 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3342 bool fence_emitted = false;
3343 VkResult result;
3344 int ret;
3345
3346 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3347 struct radv_winsys_sem_info sem_info;
3348 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3349 radv_sparse_buffer_bind_memory(queue->device,
3350 pBindInfo[i].pBufferBinds + j);
3351 }
3352
3353 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3354 radv_sparse_image_opaque_bind_memory(queue->device,
3355 pBindInfo[i].pImageOpaqueBinds + j);
3356 }
3357
3358 VkResult result;
3359 result = radv_alloc_sem_info(queue->device->instance,
3360 &sem_info,
3361 pBindInfo[i].waitSemaphoreCount,
3362 pBindInfo[i].pWaitSemaphores,
3363 pBindInfo[i].signalSemaphoreCount,
3364 pBindInfo[i].pSignalSemaphores,
3365 _fence);
3366 if (result != VK_SUCCESS)
3367 return result;
3368
3369 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3370 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3371 &queue->device->empty_cs[queue->queue_family_index],
3372 1, NULL, NULL,
3373 &sem_info, NULL,
3374 false, base_fence);
3375 if (ret) {
3376 radv_loge("failed to submit CS %d\n", i);
3377 abort();
3378 }
3379
3380 fence_emitted = true;
3381 if (fence)
3382 fence->submitted = true;
3383 }
3384
3385 radv_free_sem_info(&sem_info);
3386
3387 }
3388
3389 if (fence) {
3390 if (!fence_emitted) {
3391 result = radv_signal_fence(queue, fence);
3392 if (result != VK_SUCCESS)
3393 return result;
3394 }
3395 fence->submitted = true;
3396 }
3397
3398 return VK_SUCCESS;
3399 }
3400
3401 VkResult radv_CreateFence(
3402 VkDevice _device,
3403 const VkFenceCreateInfo* pCreateInfo,
3404 const VkAllocationCallbacks* pAllocator,
3405 VkFence* pFence)
3406 {
3407 RADV_FROM_HANDLE(radv_device, device, _device);
3408 const VkExportFenceCreateInfoKHR *export =
3409 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3410 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3411 export ? export->handleTypes : 0;
3412
3413 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3414 sizeof(*fence), 8,
3415 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3416
3417 if (!fence)
3418 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3419
3420 fence->fence_wsi = NULL;
3421 fence->submitted = false;
3422 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3423 fence->temp_syncobj = 0;
3424 if (device->always_use_syncobj || handleTypes) {
3425 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3426 if (ret) {
3427 vk_free2(&device->alloc, pAllocator, fence);
3428 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3429 }
3430 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3431 device->ws->signal_syncobj(device->ws, fence->syncobj);
3432 }
3433 fence->fence = NULL;
3434 } else {
3435 fence->fence = device->ws->create_fence();
3436 if (!fence->fence) {
3437 vk_free2(&device->alloc, pAllocator, fence);
3438 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3439 }
3440 fence->syncobj = 0;
3441 }
3442
3443 *pFence = radv_fence_to_handle(fence);
3444
3445 return VK_SUCCESS;
3446 }
3447
3448 void radv_DestroyFence(
3449 VkDevice _device,
3450 VkFence _fence,
3451 const VkAllocationCallbacks* pAllocator)
3452 {
3453 RADV_FROM_HANDLE(radv_device, device, _device);
3454 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3455
3456 if (!fence)
3457 return;
3458
3459 if (fence->temp_syncobj)
3460 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3461 if (fence->syncobj)
3462 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3463 if (fence->fence)
3464 device->ws->destroy_fence(fence->fence);
3465 if (fence->fence_wsi)
3466 fence->fence_wsi->destroy(fence->fence_wsi);
3467 vk_free2(&device->alloc, pAllocator, fence);
3468 }
3469
3470
3471 static uint64_t radv_get_current_time()
3472 {
3473 struct timespec tv;
3474 clock_gettime(CLOCK_MONOTONIC, &tv);
3475 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3476 }
3477
3478 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3479 {
3480 uint64_t current_time = radv_get_current_time();
3481
3482 timeout = MIN2(UINT64_MAX - current_time, timeout);
3483
3484 return current_time + timeout;
3485 }
3486
3487
3488 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3489 {
3490 for (uint32_t i = 0; i < fenceCount; ++i) {
3491 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3492 if (fence->fence == NULL || fence->syncobj ||
3493 fence->temp_syncobj ||
3494 (!fence->signalled && !fence->submitted))
3495 return false;
3496 }
3497 return true;
3498 }
3499
3500 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3501 {
3502 for (uint32_t i = 0; i < fenceCount; ++i) {
3503 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3504 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3505 return false;
3506 }
3507 return true;
3508 }
3509
3510 VkResult radv_WaitForFences(
3511 VkDevice _device,
3512 uint32_t fenceCount,
3513 const VkFence* pFences,
3514 VkBool32 waitAll,
3515 uint64_t timeout)
3516 {
3517 RADV_FROM_HANDLE(radv_device, device, _device);
3518 timeout = radv_get_absolute_timeout(timeout);
3519
3520 if (device->always_use_syncobj &&
3521 radv_all_fences_syncobj(fenceCount, pFences))
3522 {
3523 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3524 if (!handles)
3525 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3526
3527 for (uint32_t i = 0; i < fenceCount; ++i) {
3528 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3529 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3530 }
3531
3532 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3533
3534 free(handles);
3535 return success ? VK_SUCCESS : VK_TIMEOUT;
3536 }
3537
3538 if (!waitAll && fenceCount > 1) {
3539 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3540 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3541 uint32_t wait_count = 0;
3542 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3543 if (!fences)
3544 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3545
3546 for (uint32_t i = 0; i < fenceCount; ++i) {
3547 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3548
3549 if (fence->signalled) {
3550 free(fences);
3551 return VK_SUCCESS;
3552 }
3553
3554 fences[wait_count++] = fence->fence;
3555 }
3556
3557 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3558 waitAll, timeout - radv_get_current_time());
3559
3560 free(fences);
3561 return success ? VK_SUCCESS : VK_TIMEOUT;
3562 }
3563
3564 while(radv_get_current_time() <= timeout) {
3565 for (uint32_t i = 0; i < fenceCount; ++i) {
3566 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3567 return VK_SUCCESS;
3568 }
3569 }
3570 return VK_TIMEOUT;
3571 }
3572
3573 for (uint32_t i = 0; i < fenceCount; ++i) {
3574 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3575 bool expired = false;
3576
3577 if (fence->temp_syncobj) {
3578 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3579 return VK_TIMEOUT;
3580 continue;
3581 }
3582
3583 if (fence->syncobj) {
3584 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3585 return VK_TIMEOUT;
3586 continue;
3587 }
3588
3589 if (fence->signalled)
3590 continue;
3591
3592 if (fence->fence) {
3593 if (!fence->submitted) {
3594 while(radv_get_current_time() <= timeout &&
3595 !fence->submitted)
3596 /* Do nothing */;
3597
3598 if (!fence->submitted)
3599 return VK_TIMEOUT;
3600
3601 /* Recheck as it may have been set by
3602 * submitting operations. */
3603
3604 if (fence->signalled)
3605 continue;
3606 }
3607
3608 expired = device->ws->fence_wait(device->ws,
3609 fence->fence,
3610 true, timeout);
3611 if (!expired)
3612 return VK_TIMEOUT;
3613 }
3614
3615 if (fence->fence_wsi) {
3616 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3617 if (result != VK_SUCCESS)
3618 return result;
3619 }
3620
3621 fence->signalled = true;
3622 }
3623
3624 return VK_SUCCESS;
3625 }
3626
3627 VkResult radv_ResetFences(VkDevice _device,
3628 uint32_t fenceCount,
3629 const VkFence *pFences)
3630 {
3631 RADV_FROM_HANDLE(radv_device, device, _device);
3632
3633 for (unsigned i = 0; i < fenceCount; ++i) {
3634 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3635 fence->submitted = fence->signalled = false;
3636
3637 /* Per spec, we first restore the permanent payload, and then reset, so
3638 * having a temp syncobj should not skip resetting the permanent syncobj. */
3639 if (fence->temp_syncobj) {
3640 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3641 fence->temp_syncobj = 0;
3642 }
3643
3644 if (fence->syncobj) {
3645 device->ws->reset_syncobj(device->ws, fence->syncobj);
3646 }
3647 }
3648
3649 return VK_SUCCESS;
3650 }
3651
3652 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3653 {
3654 RADV_FROM_HANDLE(radv_device, device, _device);
3655 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3656
3657 if (fence->temp_syncobj) {
3658 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3659 return success ? VK_SUCCESS : VK_NOT_READY;
3660 }
3661
3662 if (fence->syncobj) {
3663 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3664 return success ? VK_SUCCESS : VK_NOT_READY;
3665 }
3666
3667 if (fence->signalled)
3668 return VK_SUCCESS;
3669 if (!fence->submitted)
3670 return VK_NOT_READY;
3671 if (fence->fence) {
3672 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3673 return VK_NOT_READY;
3674 }
3675 if (fence->fence_wsi) {
3676 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3677
3678 if (result != VK_SUCCESS) {
3679 if (result == VK_TIMEOUT)
3680 return VK_NOT_READY;
3681 return result;
3682 }
3683 }
3684 return VK_SUCCESS;
3685 }
3686
3687
3688 // Queue semaphore functions
3689
3690 VkResult radv_CreateSemaphore(
3691 VkDevice _device,
3692 const VkSemaphoreCreateInfo* pCreateInfo,
3693 const VkAllocationCallbacks* pAllocator,
3694 VkSemaphore* pSemaphore)
3695 {
3696 RADV_FROM_HANDLE(radv_device, device, _device);
3697 const VkExportSemaphoreCreateInfoKHR *export =
3698 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3699 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3700 export ? export->handleTypes : 0;
3701
3702 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3703 sizeof(*sem), 8,
3704 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3705 if (!sem)
3706 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3707
3708 sem->temp_syncobj = 0;
3709 /* create a syncobject if we are going to export this semaphore */
3710 if (device->always_use_syncobj || handleTypes) {
3711 assert (device->physical_device->rad_info.has_syncobj);
3712 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3713 if (ret) {
3714 vk_free2(&device->alloc, pAllocator, sem);
3715 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3716 }
3717 sem->sem = NULL;
3718 } else {
3719 sem->sem = device->ws->create_sem(device->ws);
3720 if (!sem->sem) {
3721 vk_free2(&device->alloc, pAllocator, sem);
3722 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3723 }
3724 sem->syncobj = 0;
3725 }
3726
3727 *pSemaphore = radv_semaphore_to_handle(sem);
3728 return VK_SUCCESS;
3729 }
3730
3731 void radv_DestroySemaphore(
3732 VkDevice _device,
3733 VkSemaphore _semaphore,
3734 const VkAllocationCallbacks* pAllocator)
3735 {
3736 RADV_FROM_HANDLE(radv_device, device, _device);
3737 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3738 if (!_semaphore)
3739 return;
3740
3741 if (sem->syncobj)
3742 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3743 else
3744 device->ws->destroy_sem(sem->sem);
3745 vk_free2(&device->alloc, pAllocator, sem);
3746 }
3747
3748 VkResult radv_CreateEvent(
3749 VkDevice _device,
3750 const VkEventCreateInfo* pCreateInfo,
3751 const VkAllocationCallbacks* pAllocator,
3752 VkEvent* pEvent)
3753 {
3754 RADV_FROM_HANDLE(radv_device, device, _device);
3755 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3756 sizeof(*event), 8,
3757 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3758
3759 if (!event)
3760 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3761
3762 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3763 RADEON_DOMAIN_GTT,
3764 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3765 if (!event->bo) {
3766 vk_free2(&device->alloc, pAllocator, event);
3767 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3768 }
3769
3770 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3771
3772 *pEvent = radv_event_to_handle(event);
3773
3774 return VK_SUCCESS;
3775 }
3776
3777 void radv_DestroyEvent(
3778 VkDevice _device,
3779 VkEvent _event,
3780 const VkAllocationCallbacks* pAllocator)
3781 {
3782 RADV_FROM_HANDLE(radv_device, device, _device);
3783 RADV_FROM_HANDLE(radv_event, event, _event);
3784
3785 if (!event)
3786 return;
3787 device->ws->buffer_destroy(event->bo);
3788 vk_free2(&device->alloc, pAllocator, event);
3789 }
3790
3791 VkResult radv_GetEventStatus(
3792 VkDevice _device,
3793 VkEvent _event)
3794 {
3795 RADV_FROM_HANDLE(radv_event, event, _event);
3796
3797 if (*event->map == 1)
3798 return VK_EVENT_SET;
3799 return VK_EVENT_RESET;
3800 }
3801
3802 VkResult radv_SetEvent(
3803 VkDevice _device,
3804 VkEvent _event)
3805 {
3806 RADV_FROM_HANDLE(radv_event, event, _event);
3807 *event->map = 1;
3808
3809 return VK_SUCCESS;
3810 }
3811
3812 VkResult radv_ResetEvent(
3813 VkDevice _device,
3814 VkEvent _event)
3815 {
3816 RADV_FROM_HANDLE(radv_event, event, _event);
3817 *event->map = 0;
3818
3819 return VK_SUCCESS;
3820 }
3821
3822 VkResult radv_CreateBuffer(
3823 VkDevice _device,
3824 const VkBufferCreateInfo* pCreateInfo,
3825 const VkAllocationCallbacks* pAllocator,
3826 VkBuffer* pBuffer)
3827 {
3828 RADV_FROM_HANDLE(radv_device, device, _device);
3829 struct radv_buffer *buffer;
3830
3831 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3832
3833 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3834 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3835 if (buffer == NULL)
3836 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3837
3838 buffer->size = pCreateInfo->size;
3839 buffer->usage = pCreateInfo->usage;
3840 buffer->bo = NULL;
3841 buffer->offset = 0;
3842 buffer->flags = pCreateInfo->flags;
3843
3844 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3845 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3846
3847 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3848 buffer->bo = device->ws->buffer_create(device->ws,
3849 align64(buffer->size, 4096),
3850 4096, 0, RADEON_FLAG_VIRTUAL);
3851 if (!buffer->bo) {
3852 vk_free2(&device->alloc, pAllocator, buffer);
3853 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3854 }
3855 }
3856
3857 *pBuffer = radv_buffer_to_handle(buffer);
3858
3859 return VK_SUCCESS;
3860 }
3861
3862 void radv_DestroyBuffer(
3863 VkDevice _device,
3864 VkBuffer _buffer,
3865 const VkAllocationCallbacks* pAllocator)
3866 {
3867 RADV_FROM_HANDLE(radv_device, device, _device);
3868 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3869
3870 if (!buffer)
3871 return;
3872
3873 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3874 device->ws->buffer_destroy(buffer->bo);
3875
3876 vk_free2(&device->alloc, pAllocator, buffer);
3877 }
3878
3879 static inline unsigned
3880 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3881 {
3882 if (stencil)
3883 return image->surface.u.legacy.stencil_tiling_index[level];
3884 else
3885 return image->surface.u.legacy.tiling_index[level];
3886 }
3887
3888 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3889 {
3890 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3891 }
3892
3893 static uint32_t
3894 radv_init_dcc_control_reg(struct radv_device *device,
3895 struct radv_image_view *iview)
3896 {
3897 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3898 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3899 unsigned max_compressed_block_size;
3900 unsigned independent_64b_blocks;
3901
3902 if (device->physical_device->rad_info.chip_class < VI)
3903 return 0;
3904
3905 if (iview->image->info.samples > 1) {
3906 if (iview->image->surface.bpe == 1)
3907 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3908 else if (iview->image->surface.bpe == 2)
3909 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3910 }
3911
3912 if (!device->physical_device->rad_info.has_dedicated_vram) {
3913 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3914 * dGPU and 64 for APU because all of our APUs to date use
3915 * DIMMs which have a request granularity size of 64B while all
3916 * other chips have a 32B request size.
3917 */
3918 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3919 }
3920
3921 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3922 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3923 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3924 /* If this DCC image is potentially going to be used in texture
3925 * fetches, we need some special settings.
3926 */
3927 independent_64b_blocks = 1;
3928 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3929 } else {
3930 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3931 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3932 * big as possible for better compression state.
3933 */
3934 independent_64b_blocks = 0;
3935 max_compressed_block_size = max_uncompressed_block_size;
3936 }
3937
3938 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3939 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3940 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3941 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3942 }
3943
3944 static void
3945 radv_initialise_color_surface(struct radv_device *device,
3946 struct radv_color_buffer_info *cb,
3947 struct radv_image_view *iview)
3948 {
3949 const struct vk_format_description *desc;
3950 unsigned ntype, format, swap, endian;
3951 unsigned blend_clamp = 0, blend_bypass = 0;
3952 uint64_t va;
3953 const struct radeon_surf *surf = &iview->image->surface;
3954
3955 desc = vk_format_description(iview->vk_format);
3956
3957 memset(cb, 0, sizeof(*cb));
3958
3959 /* Intensity is implemented as Red, so treat it that way. */
3960 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3961
3962 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3963
3964 cb->cb_color_base = va >> 8;
3965
3966 if (device->physical_device->rad_info.chip_class >= GFX9) {
3967 struct gfx9_surf_meta_flags meta;
3968 if (iview->image->dcc_offset)
3969 meta = iview->image->surface.u.gfx9.dcc;
3970 else
3971 meta = iview->image->surface.u.gfx9.cmask;
3972
3973 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3974 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3975 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3976 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3977
3978 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3979 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3980 } else {
3981 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3982 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3983
3984 cb->cb_color_base += level_info->offset >> 8;
3985 if (level_info->mode == RADEON_SURF_MODE_2D)
3986 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3987
3988 pitch_tile_max = level_info->nblk_x / 8 - 1;
3989 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3990 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3991
3992 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3993 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3994 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3995
3996 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3997
3998 if (radv_image_has_fmask(iview->image)) {
3999 if (device->physical_device->rad_info.chip_class >= CIK)
4000 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4001 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4002 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4003 } else {
4004 /* This must be set for fast clear to work without FMASK. */
4005 if (device->physical_device->rad_info.chip_class >= CIK)
4006 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4007 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4008 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4009 }
4010 }
4011
4012 /* CMASK variables */
4013 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4014 va += iview->image->cmask.offset;
4015 cb->cb_color_cmask = va >> 8;
4016
4017 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4018 va += iview->image->dcc_offset;
4019 cb->cb_dcc_base = va >> 8;
4020 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4021
4022 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4023 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4024 S_028C6C_SLICE_MAX(max_slice);
4025
4026 if (iview->image->info.samples > 1) {
4027 unsigned log_samples = util_logbase2(iview->image->info.samples);
4028
4029 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4030 S_028C74_NUM_FRAGMENTS(log_samples);
4031 }
4032
4033 if (radv_image_has_fmask(iview->image)) {
4034 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4035 cb->cb_color_fmask = va >> 8;
4036 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4037 } else {
4038 cb->cb_color_fmask = cb->cb_color_base;
4039 }
4040
4041 ntype = radv_translate_color_numformat(iview->vk_format,
4042 desc,
4043 vk_format_get_first_non_void_channel(iview->vk_format));
4044 format = radv_translate_colorformat(iview->vk_format);
4045 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4046 radv_finishme("Illegal color\n");
4047 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4048 endian = radv_colorformat_endian_swap(format);
4049
4050 /* blend clamp should be set for all NORM/SRGB types */
4051 if (ntype == V_028C70_NUMBER_UNORM ||
4052 ntype == V_028C70_NUMBER_SNORM ||
4053 ntype == V_028C70_NUMBER_SRGB)
4054 blend_clamp = 1;
4055
4056 /* set blend bypass according to docs if SINT/UINT or
4057 8/24 COLOR variants */
4058 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4059 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4060 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4061 blend_clamp = 0;
4062 blend_bypass = 1;
4063 }
4064 #if 0
4065 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4066 (format == V_028C70_COLOR_8 ||
4067 format == V_028C70_COLOR_8_8 ||
4068 format == V_028C70_COLOR_8_8_8_8))
4069 ->color_is_int8 = true;
4070 #endif
4071 cb->cb_color_info = S_028C70_FORMAT(format) |
4072 S_028C70_COMP_SWAP(swap) |
4073 S_028C70_BLEND_CLAMP(blend_clamp) |
4074 S_028C70_BLEND_BYPASS(blend_bypass) |
4075 S_028C70_SIMPLE_FLOAT(1) |
4076 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4077 ntype != V_028C70_NUMBER_SNORM &&
4078 ntype != V_028C70_NUMBER_SRGB &&
4079 format != V_028C70_COLOR_8_24 &&
4080 format != V_028C70_COLOR_24_8) |
4081 S_028C70_NUMBER_TYPE(ntype) |
4082 S_028C70_ENDIAN(endian);
4083 if (radv_image_has_fmask(iview->image)) {
4084 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4085 if (device->physical_device->rad_info.chip_class == SI) {
4086 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4087 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4088 }
4089 }
4090
4091 if (radv_image_has_cmask(iview->image) &&
4092 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4093 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4094
4095 if (radv_dcc_enabled(iview->image, iview->base_mip))
4096 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4097
4098 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4099
4100 /* This must be set for fast clear to work without FMASK. */
4101 if (!radv_image_has_fmask(iview->image) &&
4102 device->physical_device->rad_info.chip_class == SI) {
4103 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4104 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4105 }
4106
4107 if (device->physical_device->rad_info.chip_class >= GFX9) {
4108 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4109 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4110
4111 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4112 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4113 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4114 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4115 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4116 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4117 }
4118 }
4119
4120 static unsigned
4121 radv_calc_decompress_on_z_planes(struct radv_device *device,
4122 struct radv_image_view *iview)
4123 {
4124 unsigned max_zplanes = 0;
4125
4126 assert(radv_image_is_tc_compat_htile(iview->image));
4127
4128 if (device->physical_device->rad_info.chip_class >= GFX9) {
4129 /* Default value for 32-bit depth surfaces. */
4130 max_zplanes = 4;
4131
4132 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4133 iview->image->info.samples > 1)
4134 max_zplanes = 2;
4135
4136 max_zplanes = max_zplanes + 1;
4137 } else {
4138 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4139 /* Do not enable Z plane compression for 16-bit depth
4140 * surfaces because isn't supported on GFX8. Only
4141 * 32-bit depth surfaces are supported by the hardware.
4142 * This allows to maintain shader compatibility and to
4143 * reduce the number of depth decompressions.
4144 */
4145 max_zplanes = 1;
4146 } else {
4147 if (iview->image->info.samples <= 1)
4148 max_zplanes = 5;
4149 else if (iview->image->info.samples <= 4)
4150 max_zplanes = 3;
4151 else
4152 max_zplanes = 2;
4153 }
4154 }
4155
4156 return max_zplanes;
4157 }
4158
4159 static void
4160 radv_initialise_ds_surface(struct radv_device *device,
4161 struct radv_ds_buffer_info *ds,
4162 struct radv_image_view *iview)
4163 {
4164 unsigned level = iview->base_mip;
4165 unsigned format, stencil_format;
4166 uint64_t va, s_offs, z_offs;
4167 bool stencil_only = false;
4168 memset(ds, 0, sizeof(*ds));
4169 switch (iview->image->vk_format) {
4170 case VK_FORMAT_D24_UNORM_S8_UINT:
4171 case VK_FORMAT_X8_D24_UNORM_PACK32:
4172 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4173 ds->offset_scale = 2.0f;
4174 break;
4175 case VK_FORMAT_D16_UNORM:
4176 case VK_FORMAT_D16_UNORM_S8_UINT:
4177 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4178 ds->offset_scale = 4.0f;
4179 break;
4180 case VK_FORMAT_D32_SFLOAT:
4181 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4182 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4183 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4184 ds->offset_scale = 1.0f;
4185 break;
4186 case VK_FORMAT_S8_UINT:
4187 stencil_only = true;
4188 break;
4189 default:
4190 break;
4191 }
4192
4193 format = radv_translate_dbformat(iview->image->vk_format);
4194 stencil_format = iview->image->surface.has_stencil ?
4195 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4196
4197 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4198 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4199 S_028008_SLICE_MAX(max_slice);
4200
4201 ds->db_htile_data_base = 0;
4202 ds->db_htile_surface = 0;
4203
4204 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4205 s_offs = z_offs = va;
4206
4207 if (device->physical_device->rad_info.chip_class >= GFX9) {
4208 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4209 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4210
4211 ds->db_z_info = S_028038_FORMAT(format) |
4212 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4213 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4214 S_028038_MAXMIP(iview->image->info.levels - 1) |
4215 S_028038_ZRANGE_PRECISION(1);
4216 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4217 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4218
4219 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4220 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4221 ds->db_depth_view |= S_028008_MIPID(level);
4222
4223 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4224 S_02801C_Y_MAX(iview->image->info.height - 1);
4225
4226 if (radv_htile_enabled(iview->image, level)) {
4227 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4228
4229 if (radv_image_is_tc_compat_htile(iview->image)) {
4230 unsigned max_zplanes =
4231 radv_calc_decompress_on_z_planes(device, iview);
4232
4233 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4234 S_028038_ITERATE_FLUSH(1);
4235 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4236 }
4237
4238 if (!iview->image->surface.has_stencil)
4239 /* Use all of the htile_buffer for depth if there's no stencil. */
4240 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4241 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4242 iview->image->htile_offset;
4243 ds->db_htile_data_base = va >> 8;
4244 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4245 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4246 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4247 }
4248 } else {
4249 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4250
4251 if (stencil_only)
4252 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4253
4254 z_offs += iview->image->surface.u.legacy.level[level].offset;
4255 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4256
4257 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4258 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4259 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4260
4261 if (iview->image->info.samples > 1)
4262 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4263
4264 if (device->physical_device->rad_info.chip_class >= CIK) {
4265 struct radeon_info *info = &device->physical_device->rad_info;
4266 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4267 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4268 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4269 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4270 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4271 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4272
4273 if (stencil_only)
4274 tile_mode = stencil_tile_mode;
4275
4276 ds->db_depth_info |=
4277 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4278 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4279 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4280 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4281 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4282 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4283 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4284 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4285 } else {
4286 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4287 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4288 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4289 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4290 if (stencil_only)
4291 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4292 }
4293
4294 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4295 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4296 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4297
4298 if (radv_htile_enabled(iview->image, level)) {
4299 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4300
4301 if (!iview->image->surface.has_stencil &&
4302 !radv_image_is_tc_compat_htile(iview->image))
4303 /* Use all of the htile_buffer for depth if there's no stencil. */
4304 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4305
4306 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4307 iview->image->htile_offset;
4308 ds->db_htile_data_base = va >> 8;
4309 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4310
4311 if (radv_image_is_tc_compat_htile(iview->image)) {
4312 unsigned max_zplanes =
4313 radv_calc_decompress_on_z_planes(device, iview);
4314
4315 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4316 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4317 }
4318 }
4319 }
4320
4321 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4322 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4323 }
4324
4325 VkResult radv_CreateFramebuffer(
4326 VkDevice _device,
4327 const VkFramebufferCreateInfo* pCreateInfo,
4328 const VkAllocationCallbacks* pAllocator,
4329 VkFramebuffer* pFramebuffer)
4330 {
4331 RADV_FROM_HANDLE(radv_device, device, _device);
4332 struct radv_framebuffer *framebuffer;
4333
4334 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4335
4336 size_t size = sizeof(*framebuffer) +
4337 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4338 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4339 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4340 if (framebuffer == NULL)
4341 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4342
4343 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4344 framebuffer->width = pCreateInfo->width;
4345 framebuffer->height = pCreateInfo->height;
4346 framebuffer->layers = pCreateInfo->layers;
4347 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4348 VkImageView _iview = pCreateInfo->pAttachments[i];
4349 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4350 framebuffer->attachments[i].attachment = iview;
4351 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4352 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4353 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4354 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4355 }
4356 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4357 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4358 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4359 }
4360
4361 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4362 return VK_SUCCESS;
4363 }
4364
4365 void radv_DestroyFramebuffer(
4366 VkDevice _device,
4367 VkFramebuffer _fb,
4368 const VkAllocationCallbacks* pAllocator)
4369 {
4370 RADV_FROM_HANDLE(radv_device, device, _device);
4371 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4372
4373 if (!fb)
4374 return;
4375 vk_free2(&device->alloc, pAllocator, fb);
4376 }
4377
4378 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4379 {
4380 switch (address_mode) {
4381 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4382 return V_008F30_SQ_TEX_WRAP;
4383 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4384 return V_008F30_SQ_TEX_MIRROR;
4385 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4386 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4387 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4388 return V_008F30_SQ_TEX_CLAMP_BORDER;
4389 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4390 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4391 default:
4392 unreachable("illegal tex wrap mode");
4393 break;
4394 }
4395 }
4396
4397 static unsigned
4398 radv_tex_compare(VkCompareOp op)
4399 {
4400 switch (op) {
4401 case VK_COMPARE_OP_NEVER:
4402 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4403 case VK_COMPARE_OP_LESS:
4404 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4405 case VK_COMPARE_OP_EQUAL:
4406 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4407 case VK_COMPARE_OP_LESS_OR_EQUAL:
4408 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4409 case VK_COMPARE_OP_GREATER:
4410 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4411 case VK_COMPARE_OP_NOT_EQUAL:
4412 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4413 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4414 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4415 case VK_COMPARE_OP_ALWAYS:
4416 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4417 default:
4418 unreachable("illegal compare mode");
4419 break;
4420 }
4421 }
4422
4423 static unsigned
4424 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4425 {
4426 switch (filter) {
4427 case VK_FILTER_NEAREST:
4428 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4429 V_008F38_SQ_TEX_XY_FILTER_POINT);
4430 case VK_FILTER_LINEAR:
4431 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4432 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4433 case VK_FILTER_CUBIC_IMG:
4434 default:
4435 fprintf(stderr, "illegal texture filter");
4436 return 0;
4437 }
4438 }
4439
4440 static unsigned
4441 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4442 {
4443 switch (mode) {
4444 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4445 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4446 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4447 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4448 default:
4449 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4450 }
4451 }
4452
4453 static unsigned
4454 radv_tex_bordercolor(VkBorderColor bcolor)
4455 {
4456 switch (bcolor) {
4457 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4458 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4459 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4460 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4461 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4462 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4463 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4464 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4465 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4466 default:
4467 break;
4468 }
4469 return 0;
4470 }
4471
4472 static unsigned
4473 radv_tex_aniso_filter(unsigned filter)
4474 {
4475 if (filter < 2)
4476 return 0;
4477 if (filter < 4)
4478 return 1;
4479 if (filter < 8)
4480 return 2;
4481 if (filter < 16)
4482 return 3;
4483 return 4;
4484 }
4485
4486 static unsigned
4487 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4488 {
4489 switch (mode) {
4490 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4491 return SQ_IMG_FILTER_MODE_BLEND;
4492 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4493 return SQ_IMG_FILTER_MODE_MIN;
4494 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4495 return SQ_IMG_FILTER_MODE_MAX;
4496 default:
4497 break;
4498 }
4499 return 0;
4500 }
4501
4502 static uint32_t
4503 radv_get_max_anisotropy(struct radv_device *device,
4504 const VkSamplerCreateInfo *pCreateInfo)
4505 {
4506 if (device->force_aniso >= 0)
4507 return device->force_aniso;
4508
4509 if (pCreateInfo->anisotropyEnable &&
4510 pCreateInfo->maxAnisotropy > 1.0f)
4511 return (uint32_t)pCreateInfo->maxAnisotropy;
4512
4513 return 0;
4514 }
4515
4516 static void
4517 radv_init_sampler(struct radv_device *device,
4518 struct radv_sampler *sampler,
4519 const VkSamplerCreateInfo *pCreateInfo)
4520 {
4521 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4522 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4523 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4524 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4525
4526 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4527 vk_find_struct_const(pCreateInfo->pNext,
4528 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4529 if (sampler_reduction)
4530 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4531
4532 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4533 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4534 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4535 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4536 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4537 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4538 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4539 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4540 S_008F30_DISABLE_CUBE_WRAP(0) |
4541 S_008F30_COMPAT_MODE(is_vi) |
4542 S_008F30_FILTER_MODE(filter_mode));
4543 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4544 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4545 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4546 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4547 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4548 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4549 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4550 S_008F38_MIP_POINT_PRECLAMP(0) |
4551 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4552 S_008F38_FILTER_PREC_FIX(1) |
4553 S_008F38_ANISO_OVERRIDE(is_vi));
4554 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4555 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4556 }
4557
4558 VkResult radv_CreateSampler(
4559 VkDevice _device,
4560 const VkSamplerCreateInfo* pCreateInfo,
4561 const VkAllocationCallbacks* pAllocator,
4562 VkSampler* pSampler)
4563 {
4564 RADV_FROM_HANDLE(radv_device, device, _device);
4565 struct radv_sampler *sampler;
4566
4567 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4568
4569 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4570 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4571 if (!sampler)
4572 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4573
4574 radv_init_sampler(device, sampler, pCreateInfo);
4575 *pSampler = radv_sampler_to_handle(sampler);
4576
4577 return VK_SUCCESS;
4578 }
4579
4580 void radv_DestroySampler(
4581 VkDevice _device,
4582 VkSampler _sampler,
4583 const VkAllocationCallbacks* pAllocator)
4584 {
4585 RADV_FROM_HANDLE(radv_device, device, _device);
4586 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4587
4588 if (!sampler)
4589 return;
4590 vk_free2(&device->alloc, pAllocator, sampler);
4591 }
4592
4593 /* vk_icd.h does not declare this function, so we declare it here to
4594 * suppress Wmissing-prototypes.
4595 */
4596 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4597 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4598
4599 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4600 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4601 {
4602 /* For the full details on loader interface versioning, see
4603 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4604 * What follows is a condensed summary, to help you navigate the large and
4605 * confusing official doc.
4606 *
4607 * - Loader interface v0 is incompatible with later versions. We don't
4608 * support it.
4609 *
4610 * - In loader interface v1:
4611 * - The first ICD entrypoint called by the loader is
4612 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4613 * entrypoint.
4614 * - The ICD must statically expose no other Vulkan symbol unless it is
4615 * linked with -Bsymbolic.
4616 * - Each dispatchable Vulkan handle created by the ICD must be
4617 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4618 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4619 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4620 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4621 * such loader-managed surfaces.
4622 *
4623 * - Loader interface v2 differs from v1 in:
4624 * - The first ICD entrypoint called by the loader is
4625 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4626 * statically expose this entrypoint.
4627 *
4628 * - Loader interface v3 differs from v2 in:
4629 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4630 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4631 * because the loader no longer does so.
4632 */
4633 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4634 return VK_SUCCESS;
4635 }
4636
4637 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4638 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4639 int *pFD)
4640 {
4641 RADV_FROM_HANDLE(radv_device, device, _device);
4642 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4643
4644 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4645
4646 /* At the moment, we support only the below handle types. */
4647 assert(pGetFdInfo->handleType ==
4648 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4649 pGetFdInfo->handleType ==
4650 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4651
4652 bool ret = radv_get_memory_fd(device, memory, pFD);
4653 if (ret == false)
4654 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4655 return VK_SUCCESS;
4656 }
4657
4658 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4659 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4660 int fd,
4661 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4662 {
4663 RADV_FROM_HANDLE(radv_device, device, _device);
4664
4665 switch (handleType) {
4666 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4667 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4668 return VK_SUCCESS;
4669
4670 default:
4671 /* The valid usage section for this function says:
4672 *
4673 * "handleType must not be one of the handle types defined as
4674 * opaque."
4675 *
4676 * So opaque handle types fall into the default "unsupported" case.
4677 */
4678 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4679 }
4680 }
4681
4682 static VkResult radv_import_opaque_fd(struct radv_device *device,
4683 int fd,
4684 uint32_t *syncobj)
4685 {
4686 uint32_t syncobj_handle = 0;
4687 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4688 if (ret != 0)
4689 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4690
4691 if (*syncobj)
4692 device->ws->destroy_syncobj(device->ws, *syncobj);
4693
4694 *syncobj = syncobj_handle;
4695 close(fd);
4696
4697 return VK_SUCCESS;
4698 }
4699
4700 static VkResult radv_import_sync_fd(struct radv_device *device,
4701 int fd,
4702 uint32_t *syncobj)
4703 {
4704 /* If we create a syncobj we do it locally so that if we have an error, we don't
4705 * leave a syncobj in an undetermined state in the fence. */
4706 uint32_t syncobj_handle = *syncobj;
4707 if (!syncobj_handle) {
4708 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4709 if (ret) {
4710 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4711 }
4712 }
4713
4714 if (fd == -1) {
4715 device->ws->signal_syncobj(device->ws, syncobj_handle);
4716 } else {
4717 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4718 if (ret != 0)
4719 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4720 }
4721
4722 *syncobj = syncobj_handle;
4723 if (fd != -1)
4724 close(fd);
4725
4726 return VK_SUCCESS;
4727 }
4728
4729 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4730 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4731 {
4732 RADV_FROM_HANDLE(radv_device, device, _device);
4733 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4734 uint32_t *syncobj_dst = NULL;
4735
4736 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4737 syncobj_dst = &sem->temp_syncobj;
4738 } else {
4739 syncobj_dst = &sem->syncobj;
4740 }
4741
4742 switch(pImportSemaphoreFdInfo->handleType) {
4743 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4744 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4745 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4746 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4747 default:
4748 unreachable("Unhandled semaphore handle type");
4749 }
4750 }
4751
4752 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4753 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4754 int *pFd)
4755 {
4756 RADV_FROM_HANDLE(radv_device, device, _device);
4757 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4758 int ret;
4759 uint32_t syncobj_handle;
4760
4761 if (sem->temp_syncobj)
4762 syncobj_handle = sem->temp_syncobj;
4763 else
4764 syncobj_handle = sem->syncobj;
4765
4766 switch(pGetFdInfo->handleType) {
4767 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4768 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4769 break;
4770 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4771 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4772 if (!ret) {
4773 if (sem->temp_syncobj) {
4774 close (sem->temp_syncobj);
4775 sem->temp_syncobj = 0;
4776 } else {
4777 device->ws->reset_syncobj(device->ws, syncobj_handle);
4778 }
4779 }
4780 break;
4781 default:
4782 unreachable("Unhandled semaphore handle type");
4783 }
4784
4785 if (ret)
4786 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4787 return VK_SUCCESS;
4788 }
4789
4790 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4791 VkPhysicalDevice physicalDevice,
4792 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4793 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4794 {
4795 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4796
4797 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4798 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4799 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4800 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4801 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4802 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4803 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4804 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4805 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4806 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4807 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4808 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4809 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4810 } else {
4811 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4812 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4813 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4814 }
4815 }
4816
4817 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4818 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4819 {
4820 RADV_FROM_HANDLE(radv_device, device, _device);
4821 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4822 uint32_t *syncobj_dst = NULL;
4823
4824
4825 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4826 syncobj_dst = &fence->temp_syncobj;
4827 } else {
4828 syncobj_dst = &fence->syncobj;
4829 }
4830
4831 switch(pImportFenceFdInfo->handleType) {
4832 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4833 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4834 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4835 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4836 default:
4837 unreachable("Unhandled fence handle type");
4838 }
4839 }
4840
4841 VkResult radv_GetFenceFdKHR(VkDevice _device,
4842 const VkFenceGetFdInfoKHR *pGetFdInfo,
4843 int *pFd)
4844 {
4845 RADV_FROM_HANDLE(radv_device, device, _device);
4846 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4847 int ret;
4848 uint32_t syncobj_handle;
4849
4850 if (fence->temp_syncobj)
4851 syncobj_handle = fence->temp_syncobj;
4852 else
4853 syncobj_handle = fence->syncobj;
4854
4855 switch(pGetFdInfo->handleType) {
4856 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4857 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4858 break;
4859 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4860 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4861 if (!ret) {
4862 if (fence->temp_syncobj) {
4863 close (fence->temp_syncobj);
4864 fence->temp_syncobj = 0;
4865 } else {
4866 device->ws->reset_syncobj(device->ws, syncobj_handle);
4867 }
4868 }
4869 break;
4870 default:
4871 unreachable("Unhandled fence handle type");
4872 }
4873
4874 if (ret)
4875 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4876 return VK_SUCCESS;
4877 }
4878
4879 void radv_GetPhysicalDeviceExternalFenceProperties(
4880 VkPhysicalDevice physicalDevice,
4881 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4882 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4883 {
4884 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4885
4886 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4887 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4888 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4889 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4890 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4891 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4892 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4893 } else {
4894 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4895 pExternalFenceProperties->compatibleHandleTypes = 0;
4896 pExternalFenceProperties->externalFenceFeatures = 0;
4897 }
4898 }
4899
4900 VkResult
4901 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4902 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4903 const VkAllocationCallbacks* pAllocator,
4904 VkDebugReportCallbackEXT* pCallback)
4905 {
4906 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4907 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4908 pCreateInfo, pAllocator, &instance->alloc,
4909 pCallback);
4910 }
4911
4912 void
4913 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4914 VkDebugReportCallbackEXT _callback,
4915 const VkAllocationCallbacks* pAllocator)
4916 {
4917 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4918 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4919 _callback, pAllocator, &instance->alloc);
4920 }
4921
4922 void
4923 radv_DebugReportMessageEXT(VkInstance _instance,
4924 VkDebugReportFlagsEXT flags,
4925 VkDebugReportObjectTypeEXT objectType,
4926 uint64_t object,
4927 size_t location,
4928 int32_t messageCode,
4929 const char* pLayerPrefix,
4930 const char* pMessage)
4931 {
4932 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4933 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4934 object, location, messageCode, pLayerPrefix, pMessage);
4935 }
4936
4937 void
4938 radv_GetDeviceGroupPeerMemoryFeatures(
4939 VkDevice device,
4940 uint32_t heapIndex,
4941 uint32_t localDeviceIndex,
4942 uint32_t remoteDeviceIndex,
4943 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4944 {
4945 assert(localDeviceIndex == remoteDeviceIndex);
4946
4947 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4948 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4949 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4950 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4951 }