projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: Add support for ETC2 textures.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 }
484 }
485
486 static int radv_get_instance_extension_index(const char *name)
487 {
488 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
489 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
490 return i;
491 }
492 return -1;
493 }
494
495
496 VkResult radv_CreateInstance(
497 const VkInstanceCreateInfo* pCreateInfo,
498 const VkAllocationCallbacks* pAllocator,
499 VkInstance* pInstance)
500 {
501 struct radv_instance *instance;
502 VkResult result;
503
504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
505
506 uint32_t client_version;
507 if (pCreateInfo->pApplicationInfo &&
508 pCreateInfo->pApplicationInfo->apiVersion != 0) {
509 client_version = pCreateInfo->pApplicationInfo->apiVersion;
510 } else {
511 radv_EnumerateInstanceVersion(&client_version);
512 }
513
514 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
515 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
516 if (!instance)
517 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
518
519 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
520
521 if (pAllocator)
522 instance->alloc = *pAllocator;
523 else
524 instance->alloc = default_alloc;
525
526 instance->apiVersion = client_version;
527 instance->physicalDeviceCount = -1;
528
529 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
530 radv_debug_options);
531
532 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
533 radv_perftest_options);
534
535
536 if (instance->debug_flags & RADV_DEBUG_STARTUP)
537 radv_logi("Created an instance");
538
539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
541 int index = radv_get_instance_extension_index(ext_name);
542
543 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
544 vk_free2(&default_alloc, pAllocator, instance);
545 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
546 }
547
548 instance->enabled_extensions.extensions[index] = true;
549 }
550
551 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
552 if (result != VK_SUCCESS) {
553 vk_free2(&default_alloc, pAllocator, instance);
554 return vk_error(instance, result);
555 }
556
557 _mesa_locale_init();
558
559 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
560
561 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
562
563 *pInstance = radv_instance_to_handle(instance);
564
565 return VK_SUCCESS;
566 }
567
568 void radv_DestroyInstance(
569 VkInstance _instance,
570 const VkAllocationCallbacks* pAllocator)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573
574 if (!instance)
575 return;
576
577 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
578 radv_physical_device_finish(instance->physicalDevices + i);
579 }
580
581 VG(VALGRIND_DESTROY_MEMPOOL(instance));
582
583 _mesa_locale_fini();
584
585 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
586
587 vk_free(&instance->alloc, instance);
588 }
589
590 static VkResult
591 radv_enumerate_devices(struct radv_instance *instance)
592 {
593 /* TODO: Check for more devices ? */
594 drmDevicePtr devices[8];
595 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
596 int max_devices;
597
598 instance->physicalDeviceCount = 0;
599
600 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Found %d drm nodes", max_devices);
604
605 if (max_devices < 1)
606 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
607
608 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
609 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
610 devices[i]->bustype == DRM_BUS_PCI &&
611 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
612
613 result = radv_physical_device_init(instance->physicalDevices +
614 instance->physicalDeviceCount,
615 instance,
616 devices[i]);
617 if (result == VK_SUCCESS)
618 ++instance->physicalDeviceCount;
619 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 break;
621 }
622 }
623 drmFreeDevices(devices, max_devices);
624
625 return result;
626 }
627
628 VkResult radv_EnumeratePhysicalDevices(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceCount,
631 VkPhysicalDevice* pPhysicalDevices)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDevices) {
644 *pPhysicalDeviceCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
648 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
649 }
650
651 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
652 : VK_SUCCESS;
653 }
654
655 VkResult radv_EnumeratePhysicalDeviceGroups(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceGroupCount,
658 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDeviceGroupProperties) {
671 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
675 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
676 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
678 }
679 }
680 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
681 : VK_SUCCESS;
682 }
683
684 void radv_GetPhysicalDeviceFeatures(
685 VkPhysicalDevice physicalDevice,
686 VkPhysicalDeviceFeatures* pFeatures)
687 {
688 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
689 memset(pFeatures, 0, sizeof(*pFeatures));
690
691 *pFeatures = (VkPhysicalDeviceFeatures) {
692 .robustBufferAccess = true,
693 .fullDrawIndexUint32 = true,
694 .imageCubeArray = true,
695 .independentBlend = true,
696 .geometryShader = true,
697 .tessellationShader = true,
698 .sampleRateShading = true,
699 .dualSrcBlend = true,
700 .logicOp = true,
701 .multiDrawIndirect = true,
702 .drawIndirectFirstInstance = true,
703 .depthClamp = true,
704 .depthBiasClamp = true,
705 .fillModeNonSolid = true,
706 .depthBounds = true,
707 .wideLines = true,
708 .largePoints = true,
709 .alphaToOne = true,
710 .multiViewport = true,
711 .samplerAnisotropy = true,
712 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
713 pdevice->rad_info.family == CHIP_STONEY,
714 .textureCompressionASTC_LDR = false,
715 .textureCompressionBC = true,
716 .occlusionQueryPrecise = true,
717 .pipelineStatisticsQuery = true,
718 .vertexPipelineStoresAndAtomics = true,
719 .fragmentStoresAndAtomics = true,
720 .shaderTessellationAndGeometryPointSize = true,
721 .shaderImageGatherExtended = true,
722 .shaderStorageImageExtendedFormats = true,
723 .shaderStorageImageMultisample = false,
724 .shaderUniformBufferArrayDynamicIndexing = true,
725 .shaderSampledImageArrayDynamicIndexing = true,
726 .shaderStorageBufferArrayDynamicIndexing = true,
727 .shaderStorageImageArrayDynamicIndexing = true,
728 .shaderStorageImageReadWithoutFormat = true,
729 .shaderStorageImageWriteWithoutFormat = true,
730 .shaderClipDistance = true,
731 .shaderCullDistance = true,
732 .shaderFloat64 = true,
733 .shaderInt64 = true,
734 .shaderInt16 = false,
735 .sparseBinding = true,
736 .variableMultisampleRate = true,
737 .inheritedQueries = true,
738 };
739 }
740
741 void radv_GetPhysicalDeviceFeatures2(
742 VkPhysicalDevice physicalDevice,
743 VkPhysicalDeviceFeatures2KHR *pFeatures)
744 {
745 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
746 vk_foreach_struct(ext, pFeatures->pNext) {
747 switch (ext->sType) {
748 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
749 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
750 features->variablePointersStorageBuffer = true;
751 features->variablePointers = false;
752 break;
753 }
754 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
755 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
756 features->multiview = true;
757 features->multiviewGeometryShader = true;
758 features->multiviewTessellationShader = true;
759 break;
760 }
761 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
762 VkPhysicalDeviceShaderDrawParameterFeatures *features =
763 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
764 features->shaderDrawParameters = true;
765 break;
766 }
767 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
768 VkPhysicalDeviceProtectedMemoryFeatures *features =
769 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
770 features->protectedMemory = false;
771 break;
772 }
773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
774 VkPhysicalDevice16BitStorageFeatures *features =
775 (VkPhysicalDevice16BitStorageFeatures*)ext;
776 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
777 features->storageBuffer16BitAccess = enabled;
778 features->uniformAndStorageBuffer16BitAccess = enabled;
779 features->storagePushConstant16 = enabled;
780 features->storageInputOutput16 = enabled;
781 break;
782 }
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
784 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
785 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
786 features->samplerYcbcrConversion = false;
787 break;
788 }
789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
790 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
791 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
792 features->shaderInputAttachmentArrayDynamicIndexing = true;
793 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
794 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
795 features->shaderUniformBufferArrayNonUniformIndexing = false;
796 features->shaderSampledImageArrayNonUniformIndexing = false;
797 features->shaderStorageBufferArrayNonUniformIndexing = false;
798 features->shaderStorageImageArrayNonUniformIndexing = false;
799 features->shaderInputAttachmentArrayNonUniformIndexing = false;
800 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
801 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
802 features->descriptorBindingUniformBufferUpdateAfterBind = true;
803 features->descriptorBindingSampledImageUpdateAfterBind = true;
804 features->descriptorBindingStorageImageUpdateAfterBind = true;
805 features->descriptorBindingStorageBufferUpdateAfterBind = true;
806 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
807 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
808 features->descriptorBindingUpdateUnusedWhilePending = true;
809 features->descriptorBindingPartiallyBound = true;
810 features->descriptorBindingVariableDescriptorCount = true;
811 features->runtimeDescriptorArray = true;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
815 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
816 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
817 features->conditionalRendering = true;
818 features->inheritedConditionalRendering = false;
819 break;
820 }
821 default:
822 break;
823 }
824 }
825 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
826 }
827
828 void radv_GetPhysicalDeviceProperties(
829 VkPhysicalDevice physicalDevice,
830 VkPhysicalDeviceProperties* pProperties)
831 {
832 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
833 VkSampleCountFlags sample_counts = 0xf;
834
835 /* make sure that the entire descriptor set is addressable with a signed
836 * 32-bit int. So the sum of all limits scaled by descriptor size has to
837 * be at most 2 GiB. the combined image & samples object count as one of
838 * both. This limit is for the pipeline layout, not for the set layout, but
839 * there is no set limit, so we just set a pipeline limit. I don't think
840 * any app is going to hit this soon. */
841 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
842 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
843 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
844 32 /* sampler, largest when combined with image */ +
845 64 /* sampled image */ +
846 64 /* storage image */);
847
848 VkPhysicalDeviceLimits limits = {
849 .maxImageDimension1D = (1 << 14),
850 .maxImageDimension2D = (1 << 14),
851 .maxImageDimension3D = (1 << 11),
852 .maxImageDimensionCube = (1 << 14),
853 .maxImageArrayLayers = (1 << 11),
854 .maxTexelBufferElements = 128 * 1024 * 1024,
855 .maxUniformBufferRange = UINT32_MAX,
856 .maxStorageBufferRange = UINT32_MAX,
857 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
858 .maxMemoryAllocationCount = UINT32_MAX,
859 .maxSamplerAllocationCount = 64 * 1024,
860 .bufferImageGranularity = 64, /* A cache line */
861 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
862 .maxBoundDescriptorSets = MAX_SETS,
863 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
864 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
865 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
866 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
867 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
868 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
869 .maxPerStageResources = max_descriptor_set_size,
870 .maxDescriptorSetSamplers = max_descriptor_set_size,
871 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
872 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
873 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
874 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
875 .maxDescriptorSetSampledImages = max_descriptor_set_size,
876 .maxDescriptorSetStorageImages = max_descriptor_set_size,
877 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
878 .maxVertexInputAttributes = 32,
879 .maxVertexInputBindings = 32,
880 .maxVertexInputAttributeOffset = 2047,
881 .maxVertexInputBindingStride = 2048,
882 .maxVertexOutputComponents = 128,
883 .maxTessellationGenerationLevel = 64,
884 .maxTessellationPatchSize = 32,
885 .maxTessellationControlPerVertexInputComponents = 128,
886 .maxTessellationControlPerVertexOutputComponents = 128,
887 .maxTessellationControlPerPatchOutputComponents = 120,
888 .maxTessellationControlTotalOutputComponents = 4096,
889 .maxTessellationEvaluationInputComponents = 128,
890 .maxTessellationEvaluationOutputComponents = 128,
891 .maxGeometryShaderInvocations = 127,
892 .maxGeometryInputComponents = 64,
893 .maxGeometryOutputComponents = 128,
894 .maxGeometryOutputVertices = 256,
895 .maxGeometryTotalOutputComponents = 1024,
896 .maxFragmentInputComponents = 128,
897 .maxFragmentOutputAttachments = 8,
898 .maxFragmentDualSrcAttachments = 1,
899 .maxFragmentCombinedOutputResources = 8,
900 .maxComputeSharedMemorySize = 32768,
901 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
902 .maxComputeWorkGroupInvocations = 2048,
903 .maxComputeWorkGroupSize = {
904 2048,
905 2048,
906 2048
907 },
908 .subPixelPrecisionBits = 4 /* FIXME */,
909 .subTexelPrecisionBits = 4 /* FIXME */,
910 .mipmapPrecisionBits = 4 /* FIXME */,
911 .maxDrawIndexedIndexValue = UINT32_MAX,
912 .maxDrawIndirectCount = UINT32_MAX,
913 .maxSamplerLodBias = 16,
914 .maxSamplerAnisotropy = 16,
915 .maxViewports = MAX_VIEWPORTS,
916 .maxViewportDimensions = { (1 << 14), (1 << 14) },
917 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
918 .viewportSubPixelBits = 8,
919 .minMemoryMapAlignment = 4096, /* A page */
920 .minTexelBufferOffsetAlignment = 1,
921 .minUniformBufferOffsetAlignment = 4,
922 .minStorageBufferOffsetAlignment = 4,
923 .minTexelOffset = -32,
924 .maxTexelOffset = 31,
925 .minTexelGatherOffset = -32,
926 .maxTexelGatherOffset = 31,
927 .minInterpolationOffset = -2,
928 .maxInterpolationOffset = 2,
929 .subPixelInterpolationOffsetBits = 8,
930 .maxFramebufferWidth = (1 << 14),
931 .maxFramebufferHeight = (1 << 14),
932 .maxFramebufferLayers = (1 << 10),
933 .framebufferColorSampleCounts = sample_counts,
934 .framebufferDepthSampleCounts = sample_counts,
935 .framebufferStencilSampleCounts = sample_counts,
936 .framebufferNoAttachmentsSampleCounts = sample_counts,
937 .maxColorAttachments = MAX_RTS,
938 .sampledImageColorSampleCounts = sample_counts,
939 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
940 .sampledImageDepthSampleCounts = sample_counts,
941 .sampledImageStencilSampleCounts = sample_counts,
942 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
943 .maxSampleMaskWords = 1,
944 .timestampComputeAndGraphics = true,
945 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
946 .maxClipDistances = 8,
947 .maxCullDistances = 8,
948 .maxCombinedClipAndCullDistances = 8,
949 .discreteQueuePriorities = 1,
950 .pointSizeRange = { 0.125, 255.875 },
951 .lineWidthRange = { 0.0, 7.9921875 },
952 .pointSizeGranularity = (1.0 / 8.0),
953 .lineWidthGranularity = (1.0 / 128.0),
954 .strictLines = false, /* FINISHME */
955 .standardSampleLocations = true,
956 .optimalBufferCopyOffsetAlignment = 128,
957 .optimalBufferCopyRowPitchAlignment = 128,
958 .nonCoherentAtomSize = 64,
959 };
960
961 *pProperties = (VkPhysicalDeviceProperties) {
962 .apiVersion = radv_physical_device_api_version(pdevice),
963 .driverVersion = vk_get_driver_version(),
964 .vendorID = ATI_VENDOR_ID,
965 .deviceID = pdevice->rad_info.pci_id,
966 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
967 .limits = limits,
968 .sparseProperties = {0},
969 };
970
971 strcpy(pProperties->deviceName, pdevice->name);
972 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
973 }
974
975 void radv_GetPhysicalDeviceProperties2(
976 VkPhysicalDevice physicalDevice,
977 VkPhysicalDeviceProperties2KHR *pProperties)
978 {
979 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
980 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
981
982 vk_foreach_struct(ext, pProperties->pNext) {
983 switch (ext->sType) {
984 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
985 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
986 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
987 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
988 break;
989 }
990 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
991 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
992 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
993 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
994 properties->deviceLUIDValid = false;
995 break;
996 }
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
998 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
999 properties->maxMultiviewViewCount = MAX_VIEWS;
1000 properties->maxMultiviewInstanceIndex = INT_MAX;
1001 break;
1002 }
1003 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1004 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1005 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1006 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1007 break;
1008 }
1009 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1010 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1011 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1012 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1013 break;
1014 }
1015 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1016 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1017 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1018 properties->minImportedHostPointerAlignment = 4096;
1019 break;
1020 }
1021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1022 VkPhysicalDeviceSubgroupProperties *properties =
1023 (VkPhysicalDeviceSubgroupProperties*)ext;
1024 properties->subgroupSize = 64;
1025 properties->supportedStages = VK_SHADER_STAGE_ALL;
1026 properties->supportedOperations =
1027 VK_SUBGROUP_FEATURE_BASIC_BIT |
1028 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1029 VK_SUBGROUP_FEATURE_QUAD_BIT |
1030 VK_SUBGROUP_FEATURE_VOTE_BIT;
1031 if (pdevice->rad_info.chip_class >= VI) {
1032 properties->supportedOperations |=
1033 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1034 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1035 }
1036 properties->quadOperationsInAllStages = true;
1037 break;
1038 }
1039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1040 VkPhysicalDeviceMaintenance3Properties *properties =
1041 (VkPhysicalDeviceMaintenance3Properties*)ext;
1042 /* Make sure everything is addressable by a signed 32-bit int, and
1043 * our largest descriptors are 96 bytes. */
1044 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1045 /* Our buffer size fields allow only this much */
1046 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1050 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1051 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1052 /* GFX6-8 only support single channel min/max filter. */
1053 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1054 properties->filterMinmaxSingleComponentFormats = true;
1055 break;
1056 }
1057 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1058 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1059 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1060
1061 /* Shader engines. */
1062 properties->shaderEngineCount =
1063 pdevice->rad_info.max_se;
1064 properties->shaderArraysPerEngineCount =
1065 pdevice->rad_info.max_sh_per_se;
1066 properties->computeUnitsPerShaderArray =
1067 pdevice->rad_info.num_good_compute_units /
1068 (pdevice->rad_info.max_se *
1069 pdevice->rad_info.max_sh_per_se);
1070 properties->simdPerComputeUnit = 4;
1071 properties->wavefrontsPerSimd =
1072 pdevice->rad_info.family == CHIP_TONGA ||
1073 pdevice->rad_info.family == CHIP_ICELAND ||
1074 pdevice->rad_info.family == CHIP_POLARIS10 ||
1075 pdevice->rad_info.family == CHIP_POLARIS11 ||
1076 pdevice->rad_info.family == CHIP_POLARIS12 ||
1077 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1078 properties->wavefrontSize = 64;
1079
1080 /* SGPR. */
1081 properties->sgprsPerSimd =
1082 radv_get_num_physical_sgprs(pdevice);
1083 properties->minSgprAllocation =
1084 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1085 properties->maxSgprAllocation =
1086 pdevice->rad_info.family == CHIP_TONGA ||
1087 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1088 properties->sgprAllocationGranularity =
1089 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1090
1091 /* VGPR. */
1092 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1093 properties->minVgprAllocation = 4;
1094 properties->maxVgprAllocation = 256;
1095 properties->vgprAllocationGranularity = 4;
1096 break;
1097 }
1098 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1099 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1100 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1101 properties->maxVertexAttribDivisor = UINT32_MAX;
1102 break;
1103 }
1104 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1105 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1106 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1107 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1108 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1109 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1110 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1111 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1112 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1113 properties->robustBufferAccessUpdateAfterBind = false;
1114 properties->quadDivergentImplicitLod = false;
1115
1116 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1117 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1118 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1119 32 /* sampler, largest when combined with image */ +
1120 64 /* sampled image */ +
1121 64 /* storage image */);
1122 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1123 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1124 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1125 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1126 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1127 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1128 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1129 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1130 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1131 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1132 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1133 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1134 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1135 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1136 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1137 break;
1138 }
1139 default:
1140 break;
1141 }
1142 }
1143 }
1144
1145 static void radv_get_physical_device_queue_family_properties(
1146 struct radv_physical_device* pdevice,
1147 uint32_t* pCount,
1148 VkQueueFamilyProperties** pQueueFamilyProperties)
1149 {
1150 int num_queue_families = 1;
1151 int idx;
1152 if (pdevice->rad_info.num_compute_rings > 0 &&
1153 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1154 num_queue_families++;
1155
1156 if (pQueueFamilyProperties == NULL) {
1157 *pCount = num_queue_families;
1158 return;
1159 }
1160
1161 if (!*pCount)
1162 return;
1163
1164 idx = 0;
1165 if (*pCount >= 1) {
1166 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1167 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1168 VK_QUEUE_COMPUTE_BIT |
1169 VK_QUEUE_TRANSFER_BIT |
1170 VK_QUEUE_SPARSE_BINDING_BIT,
1171 .queueCount = 1,
1172 .timestampValidBits = 64,
1173 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1174 };
1175 idx++;
1176 }
1177
1178 if (pdevice->rad_info.num_compute_rings > 0 &&
1179 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1180 if (*pCount > idx) {
1181 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1182 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1183 VK_QUEUE_TRANSFER_BIT |
1184 VK_QUEUE_SPARSE_BINDING_BIT,
1185 .queueCount = pdevice->rad_info.num_compute_rings,
1186 .timestampValidBits = 64,
1187 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1188 };
1189 idx++;
1190 }
1191 }
1192 *pCount = idx;
1193 }
1194
1195 void radv_GetPhysicalDeviceQueueFamilyProperties(
1196 VkPhysicalDevice physicalDevice,
1197 uint32_t* pCount,
1198 VkQueueFamilyProperties* pQueueFamilyProperties)
1199 {
1200 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1201 if (!pQueueFamilyProperties) {
1202 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1203 return;
1204 }
1205 VkQueueFamilyProperties *properties[] = {
1206 pQueueFamilyProperties + 0,
1207 pQueueFamilyProperties + 1,
1208 pQueueFamilyProperties + 2,
1209 };
1210 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1211 assert(*pCount <= 3);
1212 }
1213
1214 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1215 VkPhysicalDevice physicalDevice,
1216 uint32_t* pCount,
1217 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1218 {
1219 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1220 if (!pQueueFamilyProperties) {
1221 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1222 return;
1223 }
1224 VkQueueFamilyProperties *properties[] = {
1225 &pQueueFamilyProperties[0].queueFamilyProperties,
1226 &pQueueFamilyProperties[1].queueFamilyProperties,
1227 &pQueueFamilyProperties[2].queueFamilyProperties,
1228 };
1229 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1230 assert(*pCount <= 3);
1231 }
1232
1233 void radv_GetPhysicalDeviceMemoryProperties(
1234 VkPhysicalDevice physicalDevice,
1235 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1236 {
1237 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1238
1239 *pMemoryProperties = physical_device->memory_properties;
1240 }
1241
1242 void radv_GetPhysicalDeviceMemoryProperties2(
1243 VkPhysicalDevice physicalDevice,
1244 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1245 {
1246 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1247 &pMemoryProperties->memoryProperties);
1248 }
1249
1250 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1251 VkDevice _device,
1252 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1253 const void *pHostPointer,
1254 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1255 {
1256 RADV_FROM_HANDLE(radv_device, device, _device);
1257
1258 switch (handleType)
1259 {
1260 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1261 const struct radv_physical_device *physical_device = device->physical_device;
1262 uint32_t memoryTypeBits = 0;
1263 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1264 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1265 memoryTypeBits = (1 << i);
1266 break;
1267 }
1268 }
1269 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1270 return VK_SUCCESS;
1271 }
1272 default:
1273 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1274 }
1275 }
1276
1277 static enum radeon_ctx_priority
1278 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1279 {
1280 /* Default to MEDIUM when a specific global priority isn't requested */
1281 if (!pObj)
1282 return RADEON_CTX_PRIORITY_MEDIUM;
1283
1284 switch(pObj->globalPriority) {
1285 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1286 return RADEON_CTX_PRIORITY_REALTIME;
1287 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1288 return RADEON_CTX_PRIORITY_HIGH;
1289 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1290 return RADEON_CTX_PRIORITY_MEDIUM;
1291 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1292 return RADEON_CTX_PRIORITY_LOW;
1293 default:
1294 unreachable("Illegal global priority value");
1295 return RADEON_CTX_PRIORITY_INVALID;
1296 }
1297 }
1298
1299 static int
1300 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1301 uint32_t queue_family_index, int idx,
1302 VkDeviceQueueCreateFlags flags,
1303 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1304 {
1305 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1306 queue->device = device;
1307 queue->queue_family_index = queue_family_index;
1308 queue->queue_idx = idx;
1309 queue->priority = radv_get_queue_global_priority(global_priority);
1310 queue->flags = flags;
1311
1312 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1313 if (!queue->hw_ctx)
1314 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1315
1316 return VK_SUCCESS;
1317 }
1318
1319 static void
1320 radv_queue_finish(struct radv_queue *queue)
1321 {
1322 if (queue->hw_ctx)
1323 queue->device->ws->ctx_destroy(queue->hw_ctx);
1324
1325 if (queue->initial_full_flush_preamble_cs)
1326 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1327 if (queue->initial_preamble_cs)
1328 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1329 if (queue->continue_preamble_cs)
1330 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1331 if (queue->descriptor_bo)
1332 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1333 if (queue->scratch_bo)
1334 queue->device->ws->buffer_destroy(queue->scratch_bo);
1335 if (queue->esgs_ring_bo)
1336 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1337 if (queue->gsvs_ring_bo)
1338 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1339 if (queue->tess_rings_bo)
1340 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1341 if (queue->compute_scratch_bo)
1342 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1343 }
1344
1345 static void
1346 radv_bo_list_init(struct radv_bo_list *bo_list)
1347 {
1348 pthread_mutex_init(&bo_list->mutex, NULL);
1349 bo_list->list.count = bo_list->capacity = 0;
1350 bo_list->list.bos = NULL;
1351 }
1352
1353 static void
1354 radv_bo_list_finish(struct radv_bo_list *bo_list)
1355 {
1356 free(bo_list->list.bos);
1357 pthread_mutex_destroy(&bo_list->mutex);
1358 }
1359
1360 static VkResult radv_bo_list_add(struct radv_device *device,
1361 struct radeon_winsys_bo *bo)
1362 {
1363 struct radv_bo_list *bo_list = &device->bo_list;
1364
1365 if (unlikely(!device->use_global_bo_list))
1366 return VK_SUCCESS;
1367
1368 pthread_mutex_lock(&bo_list->mutex);
1369 if (bo_list->list.count == bo_list->capacity) {
1370 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1371 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1372
1373 if (!data) {
1374 pthread_mutex_unlock(&bo_list->mutex);
1375 return VK_ERROR_OUT_OF_HOST_MEMORY;
1376 }
1377
1378 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1379 bo_list->capacity = capacity;
1380 }
1381
1382 bo_list->list.bos[bo_list->list.count++] = bo;
1383 pthread_mutex_unlock(&bo_list->mutex);
1384 return VK_SUCCESS;
1385 }
1386
1387 static void radv_bo_list_remove(struct radv_device *device,
1388 struct radeon_winsys_bo *bo)
1389 {
1390 struct radv_bo_list *bo_list = &device->bo_list;
1391
1392 if (unlikely(!device->use_global_bo_list))
1393 return;
1394
1395 pthread_mutex_lock(&bo_list->mutex);
1396 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1397 if (bo_list->list.bos[i] == bo) {
1398 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1399 --bo_list->list.count;
1400 break;
1401 }
1402 }
1403 pthread_mutex_unlock(&bo_list->mutex);
1404 }
1405
1406 static void
1407 radv_device_init_gs_info(struct radv_device *device)
1408 {
1409 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1410 device->physical_device->rad_info.family);
1411 }
1412
1413 static int radv_get_device_extension_index(const char *name)
1414 {
1415 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1416 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1417 return i;
1418 }
1419 return -1;
1420 }
1421
1422 VkResult radv_CreateDevice(
1423 VkPhysicalDevice physicalDevice,
1424 const VkDeviceCreateInfo* pCreateInfo,
1425 const VkAllocationCallbacks* pAllocator,
1426 VkDevice* pDevice)
1427 {
1428 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1429 VkResult result;
1430 struct radv_device *device;
1431
1432 bool keep_shader_info = false;
1433
1434 /* Check enabled features */
1435 if (pCreateInfo->pEnabledFeatures) {
1436 VkPhysicalDeviceFeatures supported_features;
1437 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1438 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1439 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1440 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1441 for (uint32_t i = 0; i < num_features; i++) {
1442 if (enabled_feature[i] && !supported_feature[i])
1443 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1444 }
1445 }
1446
1447 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1448 sizeof(*device), 8,
1449 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1450 if (!device)
1451 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1452
1453 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1454 device->instance = physical_device->instance;
1455 device->physical_device = physical_device;
1456
1457 device->ws = physical_device->ws;
1458 if (pAllocator)
1459 device->alloc = *pAllocator;
1460 else
1461 device->alloc = physical_device->instance->alloc;
1462
1463 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1464 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1465 int index = radv_get_device_extension_index(ext_name);
1466 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1467 vk_free(&device->alloc, device);
1468 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1469 }
1470
1471 device->enabled_extensions.extensions[index] = true;
1472 }
1473
1474 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1475
1476 /* With update after bind we can't attach bo's to the command buffer
1477 * from the descriptor set anymore, so we have to use a global BO list.
1478 */
1479 device->use_global_bo_list =
1480 device->enabled_extensions.EXT_descriptor_indexing;
1481
1482 mtx_init(&device->shader_slab_mutex, mtx_plain);
1483 list_inithead(&device->shader_slabs);
1484
1485 radv_bo_list_init(&device->bo_list);
1486
1487 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1488 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1489 uint32_t qfi = queue_create->queueFamilyIndex;
1490 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1491 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1492
1493 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1494
1495 device->queues[qfi] = vk_alloc(&device->alloc,
1496 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1497 if (!device->queues[qfi]) {
1498 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1499 goto fail;
1500 }
1501
1502 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1503
1504 device->queue_count[qfi] = queue_create->queueCount;
1505
1506 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1507 result = radv_queue_init(device, &device->queues[qfi][q],
1508 qfi, q, queue_create->flags,
1509 global_priority);
1510 if (result != VK_SUCCESS)
1511 goto fail;
1512 }
1513 }
1514
1515 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1516 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1517 device->physical_device->rad_info.family == CHIP_RAVEN);
1518
1519 /* Disabled and not implemented for now. */
1520 device->dfsm_allowed = device->pbb_allowed &&
1521 device->physical_device->rad_info.family == CHIP_RAVEN;
1522
1523 #ifdef ANDROID
1524 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1525 #endif
1526
1527 /* The maximum number of scratch waves. Scratch space isn't divided
1528 * evenly between CUs. The number is only a function of the number of CUs.
1529 * We can decrease the constant to decrease the scratch buffer size.
1530 *
1531 * sctx->scratch_waves must be >= the maximum possible size of
1532 * 1 threadgroup, so that the hw doesn't hang from being unable
1533 * to start any.
1534 *
1535 * The recommended value is 4 per CU at most. Higher numbers don't
1536 * bring much benefit, but they still occupy chip resources (think
1537 * async compute). I've seen ~2% performance difference between 4 and 32.
1538 */
1539 uint32_t max_threads_per_block = 2048;
1540 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1541 max_threads_per_block / 64);
1542
1543 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1544
1545 if (device->physical_device->rad_info.chip_class >= CIK) {
1546 /* If the KMD allows it (there is a KMD hw register for it),
1547 * allow launching waves out-of-order.
1548 */
1549 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1550 }
1551
1552 radv_device_init_gs_info(device);
1553
1554 device->tess_offchip_block_dw_size =
1555 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1556 device->has_distributed_tess =
1557 device->physical_device->rad_info.chip_class >= VI &&
1558 device->physical_device->rad_info.max_se >= 2;
1559
1560 if (getenv("RADV_TRACE_FILE")) {
1561 const char *filename = getenv("RADV_TRACE_FILE");
1562
1563 keep_shader_info = true;
1564
1565 if (!radv_init_trace(device))
1566 goto fail;
1567
1568 fprintf(stderr, "*****************************************************************************\n");
1569 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1570 fprintf(stderr, "*****************************************************************************\n");
1571
1572 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1573 radv_dump_enabled_options(device, stderr);
1574 }
1575
1576 device->keep_shader_info = keep_shader_info;
1577
1578 result = radv_device_init_meta(device);
1579 if (result != VK_SUCCESS)
1580 goto fail;
1581
1582 radv_device_init_msaa(device);
1583
1584 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1585 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1586 switch (family) {
1587 case RADV_QUEUE_GENERAL:
1588 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1589 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1590 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1591 break;
1592 case RADV_QUEUE_COMPUTE:
1593 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1594 radeon_emit(device->empty_cs[family], 0);
1595 break;
1596 }
1597 device->ws->cs_finalize(device->empty_cs[family]);
1598 }
1599
1600 if (device->physical_device->rad_info.chip_class >= CIK)
1601 cik_create_gfx_config(device);
1602
1603 VkPipelineCacheCreateInfo ci;
1604 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1605 ci.pNext = NULL;
1606 ci.flags = 0;
1607 ci.pInitialData = NULL;
1608 ci.initialDataSize = 0;
1609 VkPipelineCache pc;
1610 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1611 &ci, NULL, &pc);
1612 if (result != VK_SUCCESS)
1613 goto fail_meta;
1614
1615 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1616
1617 *pDevice = radv_device_to_handle(device);
1618 return VK_SUCCESS;
1619
1620 fail_meta:
1621 radv_device_finish_meta(device);
1622 fail:
1623 radv_bo_list_finish(&device->bo_list);
1624
1625 if (device->trace_bo)
1626 device->ws->buffer_destroy(device->trace_bo);
1627
1628 if (device->gfx_init)
1629 device->ws->buffer_destroy(device->gfx_init);
1630
1631 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1632 for (unsigned q = 0; q < device->queue_count[i]; q++)
1633 radv_queue_finish(&device->queues[i][q]);
1634 if (device->queue_count[i])
1635 vk_free(&device->alloc, device->queues[i]);
1636 }
1637
1638 vk_free(&device->alloc, device);
1639 return result;
1640 }
1641
1642 void radv_DestroyDevice(
1643 VkDevice _device,
1644 const VkAllocationCallbacks* pAllocator)
1645 {
1646 RADV_FROM_HANDLE(radv_device, device, _device);
1647
1648 if (!device)
1649 return;
1650
1651 if (device->trace_bo)
1652 device->ws->buffer_destroy(device->trace_bo);
1653
1654 if (device->gfx_init)
1655 device->ws->buffer_destroy(device->gfx_init);
1656
1657 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1658 for (unsigned q = 0; q < device->queue_count[i]; q++)
1659 radv_queue_finish(&device->queues[i][q]);
1660 if (device->queue_count[i])
1661 vk_free(&device->alloc, device->queues[i]);
1662 if (device->empty_cs[i])
1663 device->ws->cs_destroy(device->empty_cs[i]);
1664 }
1665 radv_device_finish_meta(device);
1666
1667 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1668 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1669
1670 radv_destroy_shader_slabs(device);
1671
1672 radv_bo_list_finish(&device->bo_list);
1673 vk_free(&device->alloc, device);
1674 }
1675
1676 VkResult radv_EnumerateInstanceLayerProperties(
1677 uint32_t* pPropertyCount,
1678 VkLayerProperties* pProperties)
1679 {
1680 if (pProperties == NULL) {
1681 *pPropertyCount = 0;
1682 return VK_SUCCESS;
1683 }
1684
1685 /* None supported at this time */
1686 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1687 }
1688
1689 VkResult radv_EnumerateDeviceLayerProperties(
1690 VkPhysicalDevice physicalDevice,
1691 uint32_t* pPropertyCount,
1692 VkLayerProperties* pProperties)
1693 {
1694 if (pProperties == NULL) {
1695 *pPropertyCount = 0;
1696 return VK_SUCCESS;
1697 }
1698
1699 /* None supported at this time */
1700 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1701 }
1702
1703 void radv_GetDeviceQueue2(
1704 VkDevice _device,
1705 const VkDeviceQueueInfo2* pQueueInfo,
1706 VkQueue* pQueue)
1707 {
1708 RADV_FROM_HANDLE(radv_device, device, _device);
1709 struct radv_queue *queue;
1710
1711 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1712 if (pQueueInfo->flags != queue->flags) {
1713 /* From the Vulkan 1.1.70 spec:
1714 *
1715 * "The queue returned by vkGetDeviceQueue2 must have the same
1716 * flags value from this structure as that used at device
1717 * creation time in a VkDeviceQueueCreateInfo instance. If no
1718 * matching flags were specified at device creation time then
1719 * pQueue will return VK_NULL_HANDLE."
1720 */
1721 *pQueue = VK_NULL_HANDLE;
1722 return;
1723 }
1724
1725 *pQueue = radv_queue_to_handle(queue);
1726 }
1727
1728 void radv_GetDeviceQueue(
1729 VkDevice _device,
1730 uint32_t queueFamilyIndex,
1731 uint32_t queueIndex,
1732 VkQueue* pQueue)
1733 {
1734 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1735 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1736 .queueFamilyIndex = queueFamilyIndex,
1737 .queueIndex = queueIndex
1738 };
1739
1740 radv_GetDeviceQueue2(_device, &info, pQueue);
1741 }
1742
1743 static void
1744 fill_geom_tess_rings(struct radv_queue *queue,
1745 uint32_t *map,
1746 bool add_sample_positions,
1747 uint32_t esgs_ring_size,
1748 struct radeon_winsys_bo *esgs_ring_bo,
1749 uint32_t gsvs_ring_size,
1750 struct radeon_winsys_bo *gsvs_ring_bo,
1751 uint32_t tess_factor_ring_size,
1752 uint32_t tess_offchip_ring_offset,
1753 uint32_t tess_offchip_ring_size,
1754 struct radeon_winsys_bo *tess_rings_bo)
1755 {
1756 uint64_t esgs_va = 0, gsvs_va = 0;
1757 uint64_t tess_va = 0, tess_offchip_va = 0;
1758 uint32_t *desc = &map[4];
1759
1760 if (esgs_ring_bo)
1761 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1762 if (gsvs_ring_bo)
1763 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1764 if (tess_rings_bo) {
1765 tess_va = radv_buffer_get_va(tess_rings_bo);
1766 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1767 }
1768
1769 /* stride 0, num records - size, add tid, swizzle, elsize4,
1770 index stride 64 */
1771 desc[0] = esgs_va;
1772 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1773 S_008F04_STRIDE(0) |
1774 S_008F04_SWIZZLE_ENABLE(true);
1775 desc[2] = esgs_ring_size;
1776 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1777 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1778 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1779 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1780 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1781 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1782 S_008F0C_ELEMENT_SIZE(1) |
1783 S_008F0C_INDEX_STRIDE(3) |
1784 S_008F0C_ADD_TID_ENABLE(true);
1785
1786 desc += 4;
1787 /* GS entry for ES->GS ring */
1788 /* stride 0, num records - size, elsize0,
1789 index stride 0 */
1790 desc[0] = esgs_va;
1791 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1792 S_008F04_STRIDE(0) |
1793 S_008F04_SWIZZLE_ENABLE(false);
1794 desc[2] = esgs_ring_size;
1795 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1796 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1797 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1798 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1799 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1800 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1801 S_008F0C_ELEMENT_SIZE(0) |
1802 S_008F0C_INDEX_STRIDE(0) |
1803 S_008F0C_ADD_TID_ENABLE(false);
1804
1805 desc += 4;
1806 /* VS entry for GS->VS ring */
1807 /* stride 0, num records - size, elsize0,
1808 index stride 0 */
1809 desc[0] = gsvs_va;
1810 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1811 S_008F04_STRIDE(0) |
1812 S_008F04_SWIZZLE_ENABLE(false);
1813 desc[2] = gsvs_ring_size;
1814 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1815 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1816 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1817 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1818 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1819 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1820 S_008F0C_ELEMENT_SIZE(0) |
1821 S_008F0C_INDEX_STRIDE(0) |
1822 S_008F0C_ADD_TID_ENABLE(false);
1823 desc += 4;
1824
1825 /* stride gsvs_itemsize, num records 64
1826 elsize 4, index stride 16 */
1827 /* shader will patch stride and desc[2] */
1828 desc[0] = gsvs_va;
1829 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1830 S_008F04_STRIDE(0) |
1831 S_008F04_SWIZZLE_ENABLE(true);
1832 desc[2] = 0;
1833 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1834 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1835 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1836 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1837 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1838 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1839 S_008F0C_ELEMENT_SIZE(1) |
1840 S_008F0C_INDEX_STRIDE(1) |
1841 S_008F0C_ADD_TID_ENABLE(true);
1842 desc += 4;
1843
1844 desc[0] = tess_va;
1845 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1846 S_008F04_STRIDE(0) |
1847 S_008F04_SWIZZLE_ENABLE(false);
1848 desc[2] = tess_factor_ring_size;
1849 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1850 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1851 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1852 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1853 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1854 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1855 S_008F0C_ELEMENT_SIZE(0) |
1856 S_008F0C_INDEX_STRIDE(0) |
1857 S_008F0C_ADD_TID_ENABLE(false);
1858 desc += 4;
1859
1860 desc[0] = tess_offchip_va;
1861 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1862 S_008F04_STRIDE(0) |
1863 S_008F04_SWIZZLE_ENABLE(false);
1864 desc[2] = tess_offchip_ring_size;
1865 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1866 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1867 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1868 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1869 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1870 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1871 S_008F0C_ELEMENT_SIZE(0) |
1872 S_008F0C_INDEX_STRIDE(0) |
1873 S_008F0C_ADD_TID_ENABLE(false);
1874 desc += 4;
1875
1876 /* add sample positions after all rings */
1877 memcpy(desc, queue->device->sample_locations_1x, 8);
1878 desc += 2;
1879 memcpy(desc, queue->device->sample_locations_2x, 16);
1880 desc += 4;
1881 memcpy(desc, queue->device->sample_locations_4x, 32);
1882 desc += 8;
1883 memcpy(desc, queue->device->sample_locations_8x, 64);
1884 desc += 16;
1885 memcpy(desc, queue->device->sample_locations_16x, 128);
1886 }
1887
1888 static unsigned
1889 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1890 {
1891 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1892 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1893 device->physical_device->rad_info.family != CHIP_STONEY;
1894 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1895 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1896 device->physical_device->rad_info.max_se;
1897 unsigned offchip_granularity;
1898 unsigned hs_offchip_param;
1899 switch (device->tess_offchip_block_dw_size) {
1900 default:
1901 assert(0);
1902 /* fall through */
1903 case 8192:
1904 offchip_granularity = V_03093C_X_8K_DWORDS;
1905 break;
1906 case 4096:
1907 offchip_granularity = V_03093C_X_4K_DWORDS;
1908 break;
1909 }
1910
1911 switch (device->physical_device->rad_info.chip_class) {
1912 case SI:
1913 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1914 break;
1915 case CIK:
1916 case VI:
1917 case GFX9:
1918 default:
1919 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1920 break;
1921 }
1922
1923 *max_offchip_buffers_p = max_offchip_buffers;
1924 if (device->physical_device->rad_info.chip_class >= CIK) {
1925 if (device->physical_device->rad_info.chip_class >= VI)
1926 --max_offchip_buffers;
1927 hs_offchip_param =
1928 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1929 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1930 } else {
1931 hs_offchip_param =
1932 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1933 }
1934 return hs_offchip_param;
1935 }
1936
1937 static void
1938 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1939 struct radeon_winsys_bo *esgs_ring_bo,
1940 uint32_t esgs_ring_size,
1941 struct radeon_winsys_bo *gsvs_ring_bo,
1942 uint32_t gsvs_ring_size)
1943 {
1944 if (!esgs_ring_bo && !gsvs_ring_bo)
1945 return;
1946
1947 if (esgs_ring_bo)
1948 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1949
1950 if (gsvs_ring_bo)
1951 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1952
1953 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1954 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1955 radeon_emit(cs, esgs_ring_size >> 8);
1956 radeon_emit(cs, gsvs_ring_size >> 8);
1957 } else {
1958 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1959 radeon_emit(cs, esgs_ring_size >> 8);
1960 radeon_emit(cs, gsvs_ring_size >> 8);
1961 }
1962 }
1963
1964 static void
1965 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1966 unsigned hs_offchip_param, unsigned tf_ring_size,
1967 struct radeon_winsys_bo *tess_rings_bo)
1968 {
1969 uint64_t tf_va;
1970
1971 if (!tess_rings_bo)
1972 return;
1973
1974 tf_va = radv_buffer_get_va(tess_rings_bo);
1975
1976 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
1977
1978 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1979 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1980 S_030938_SIZE(tf_ring_size / 4));
1981 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1982 tf_va >> 8);
1983 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1984 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1985 S_030944_BASE_HI(tf_va >> 40));
1986 }
1987 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1988 hs_offchip_param);
1989 } else {
1990 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1991 S_008988_SIZE(tf_ring_size / 4));
1992 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1993 tf_va >> 8);
1994 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1995 hs_offchip_param);
1996 }
1997 }
1998
1999 static void
2000 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2001 struct radeon_winsys_bo *compute_scratch_bo)
2002 {
2003 uint64_t scratch_va;
2004
2005 if (!compute_scratch_bo)
2006 return;
2007
2008 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2009
2010 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2011
2012 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2013 radeon_emit(cs, scratch_va);
2014 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2015 S_008F04_SWIZZLE_ENABLE(1));
2016 }
2017
2018 static void
2019 radv_emit_global_shader_pointers(struct radv_queue *queue,
2020 struct radeon_cmdbuf *cs,
2021 struct radeon_winsys_bo *descriptor_bo)
2022 {
2023 uint64_t va;
2024
2025 if (!descriptor_bo)
2026 return;
2027
2028 va = radv_buffer_get_va(descriptor_bo);
2029
2030 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2031
2032 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2033 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2034 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2035 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2036 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2037
2038 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2039 radv_emit_shader_pointer(queue->device, cs, regs[i],
2040 va, true);
2041 }
2042 } else {
2043 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2044 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2045 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2046 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2047 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2048 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2049
2050 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2051 radv_emit_shader_pointer(queue->device, cs, regs[i],
2052 va, true);
2053 }
2054 }
2055 }
2056
2057 static VkResult
2058 radv_get_preamble_cs(struct radv_queue *queue,
2059 uint32_t scratch_size,
2060 uint32_t compute_scratch_size,
2061 uint32_t esgs_ring_size,
2062 uint32_t gsvs_ring_size,
2063 bool needs_tess_rings,
2064 bool needs_sample_positions,
2065 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2066 struct radeon_cmdbuf **initial_preamble_cs,
2067 struct radeon_cmdbuf **continue_preamble_cs)
2068 {
2069 struct radeon_winsys_bo *scratch_bo = NULL;
2070 struct radeon_winsys_bo *descriptor_bo = NULL;
2071 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2072 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2073 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2074 struct radeon_winsys_bo *tess_rings_bo = NULL;
2075 struct radeon_cmdbuf *dest_cs[3] = {0};
2076 bool add_tess_rings = false, add_sample_positions = false;
2077 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2078 unsigned max_offchip_buffers;
2079 unsigned hs_offchip_param = 0;
2080 unsigned tess_offchip_ring_offset;
2081 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2082 if (!queue->has_tess_rings) {
2083 if (needs_tess_rings)
2084 add_tess_rings = true;
2085 }
2086 if (!queue->has_sample_positions) {
2087 if (needs_sample_positions)
2088 add_sample_positions = true;
2089 }
2090 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2091 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2092 &max_offchip_buffers);
2093 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2094 tess_offchip_ring_size = max_offchip_buffers *
2095 queue->device->tess_offchip_block_dw_size * 4;
2096
2097 if (scratch_size <= queue->scratch_size &&
2098 compute_scratch_size <= queue->compute_scratch_size &&
2099 esgs_ring_size <= queue->esgs_ring_size &&
2100 gsvs_ring_size <= queue->gsvs_ring_size &&
2101 !add_tess_rings && !add_sample_positions &&
2102 queue->initial_preamble_cs) {
2103 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2104 *initial_preamble_cs = queue->initial_preamble_cs;
2105 *continue_preamble_cs = queue->continue_preamble_cs;
2106 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2107 *continue_preamble_cs = NULL;
2108 return VK_SUCCESS;
2109 }
2110
2111 if (scratch_size > queue->scratch_size) {
2112 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2113 scratch_size,
2114 4096,
2115 RADEON_DOMAIN_VRAM,
2116 ring_bo_flags);
2117 if (!scratch_bo)
2118 goto fail;
2119 } else
2120 scratch_bo = queue->scratch_bo;
2121
2122 if (compute_scratch_size > queue->compute_scratch_size) {
2123 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2124 compute_scratch_size,
2125 4096,
2126 RADEON_DOMAIN_VRAM,
2127 ring_bo_flags);
2128 if (!compute_scratch_bo)
2129 goto fail;
2130
2131 } else
2132 compute_scratch_bo = queue->compute_scratch_bo;
2133
2134 if (esgs_ring_size > queue->esgs_ring_size) {
2135 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2136 esgs_ring_size,
2137 4096,
2138 RADEON_DOMAIN_VRAM,
2139 ring_bo_flags);
2140 if (!esgs_ring_bo)
2141 goto fail;
2142 } else {
2143 esgs_ring_bo = queue->esgs_ring_bo;
2144 esgs_ring_size = queue->esgs_ring_size;
2145 }
2146
2147 if (gsvs_ring_size > queue->gsvs_ring_size) {
2148 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2149 gsvs_ring_size,
2150 4096,
2151 RADEON_DOMAIN_VRAM,
2152 ring_bo_flags);
2153 if (!gsvs_ring_bo)
2154 goto fail;
2155 } else {
2156 gsvs_ring_bo = queue->gsvs_ring_bo;
2157 gsvs_ring_size = queue->gsvs_ring_size;
2158 }
2159
2160 if (add_tess_rings) {
2161 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2162 tess_offchip_ring_offset + tess_offchip_ring_size,
2163 256,
2164 RADEON_DOMAIN_VRAM,
2165 ring_bo_flags);
2166 if (!tess_rings_bo)
2167 goto fail;
2168 } else {
2169 tess_rings_bo = queue->tess_rings_bo;
2170 }
2171
2172 if (scratch_bo != queue->scratch_bo ||
2173 esgs_ring_bo != queue->esgs_ring_bo ||
2174 gsvs_ring_bo != queue->gsvs_ring_bo ||
2175 tess_rings_bo != queue->tess_rings_bo ||
2176 add_sample_positions) {
2177 uint32_t size = 0;
2178 if (gsvs_ring_bo || esgs_ring_bo ||
2179 tess_rings_bo || add_sample_positions) {
2180 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2181 if (add_sample_positions)
2182 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2183 }
2184 else if (scratch_bo)
2185 size = 8; /* 2 dword */
2186
2187 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2188 size,
2189 4096,
2190 RADEON_DOMAIN_VRAM,
2191 RADEON_FLAG_CPU_ACCESS |
2192 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2193 RADEON_FLAG_READ_ONLY);
2194 if (!descriptor_bo)
2195 goto fail;
2196 } else
2197 descriptor_bo = queue->descriptor_bo;
2198
2199 for(int i = 0; i < 3; ++i) {
2200 struct radeon_cmdbuf *cs = NULL;
2201 cs = queue->device->ws->cs_create(queue->device->ws,
2202 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2203 if (!cs)
2204 goto fail;
2205
2206 dest_cs[i] = cs;
2207
2208 if (scratch_bo)
2209 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2210
2211 if (descriptor_bo != queue->descriptor_bo) {
2212 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2213
2214 if (scratch_bo) {
2215 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2216 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2217 S_008F04_SWIZZLE_ENABLE(1);
2218 map[0] = scratch_va;
2219 map[1] = rsrc1;
2220 }
2221
2222 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2223 add_sample_positions)
2224 fill_geom_tess_rings(queue, map, add_sample_positions,
2225 esgs_ring_size, esgs_ring_bo,
2226 gsvs_ring_size, gsvs_ring_bo,
2227 tess_factor_ring_size,
2228 tess_offchip_ring_offset,
2229 tess_offchip_ring_size,
2230 tess_rings_bo);
2231
2232 queue->device->ws->buffer_unmap(descriptor_bo);
2233 }
2234
2235 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2236 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2237 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2238 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2239 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2240 }
2241
2242 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2243 gsvs_ring_bo, gsvs_ring_size);
2244 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2245 tess_factor_ring_size, tess_rings_bo);
2246 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2247 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2248
2249 if (i == 0) {
2250 si_cs_emit_cache_flush(cs,
2251 queue->device->physical_device->rad_info.chip_class,
2252 NULL, 0,
2253 queue->queue_family_index == RING_COMPUTE &&
2254 queue->device->physical_device->rad_info.chip_class >= CIK,
2255 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2256 RADV_CMD_FLAG_INV_ICACHE |
2257 RADV_CMD_FLAG_INV_SMEM_L1 |
2258 RADV_CMD_FLAG_INV_VMEM_L1 |
2259 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2260 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2261 } else if (i == 1) {
2262 si_cs_emit_cache_flush(cs,
2263 queue->device->physical_device->rad_info.chip_class,
2264 NULL, 0,
2265 queue->queue_family_index == RING_COMPUTE &&
2266 queue->device->physical_device->rad_info.chip_class >= CIK,
2267 RADV_CMD_FLAG_INV_ICACHE |
2268 RADV_CMD_FLAG_INV_SMEM_L1 |
2269 RADV_CMD_FLAG_INV_VMEM_L1 |
2270 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2271 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2272 }
2273
2274 if (!queue->device->ws->cs_finalize(cs))
2275 goto fail;
2276 }
2277
2278 if (queue->initial_full_flush_preamble_cs)
2279 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2280
2281 if (queue->initial_preamble_cs)
2282 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2283
2284 if (queue->continue_preamble_cs)
2285 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2286
2287 queue->initial_full_flush_preamble_cs = dest_cs[0];
2288 queue->initial_preamble_cs = dest_cs[1];
2289 queue->continue_preamble_cs = dest_cs[2];
2290
2291 if (scratch_bo != queue->scratch_bo) {
2292 if (queue->scratch_bo)
2293 queue->device->ws->buffer_destroy(queue->scratch_bo);
2294 queue->scratch_bo = scratch_bo;
2295 queue->scratch_size = scratch_size;
2296 }
2297
2298 if (compute_scratch_bo != queue->compute_scratch_bo) {
2299 if (queue->compute_scratch_bo)
2300 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2301 queue->compute_scratch_bo = compute_scratch_bo;
2302 queue->compute_scratch_size = compute_scratch_size;
2303 }
2304
2305 if (esgs_ring_bo != queue->esgs_ring_bo) {
2306 if (queue->esgs_ring_bo)
2307 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2308 queue->esgs_ring_bo = esgs_ring_bo;
2309 queue->esgs_ring_size = esgs_ring_size;
2310 }
2311
2312 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2313 if (queue->gsvs_ring_bo)
2314 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2315 queue->gsvs_ring_bo = gsvs_ring_bo;
2316 queue->gsvs_ring_size = gsvs_ring_size;
2317 }
2318
2319 if (tess_rings_bo != queue->tess_rings_bo) {
2320 queue->tess_rings_bo = tess_rings_bo;
2321 queue->has_tess_rings = true;
2322 }
2323
2324 if (descriptor_bo != queue->descriptor_bo) {
2325 if (queue->descriptor_bo)
2326 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2327
2328 queue->descriptor_bo = descriptor_bo;
2329 }
2330
2331 if (add_sample_positions)
2332 queue->has_sample_positions = true;
2333
2334 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2335 *initial_preamble_cs = queue->initial_preamble_cs;
2336 *continue_preamble_cs = queue->continue_preamble_cs;
2337 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2338 *continue_preamble_cs = NULL;
2339 return VK_SUCCESS;
2340 fail:
2341 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2342 if (dest_cs[i])
2343 queue->device->ws->cs_destroy(dest_cs[i]);
2344 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2345 queue->device->ws->buffer_destroy(descriptor_bo);
2346 if (scratch_bo && scratch_bo != queue->scratch_bo)
2347 queue->device->ws->buffer_destroy(scratch_bo);
2348 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2349 queue->device->ws->buffer_destroy(compute_scratch_bo);
2350 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2351 queue->device->ws->buffer_destroy(esgs_ring_bo);
2352 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2353 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2354 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2355 queue->device->ws->buffer_destroy(tess_rings_bo);
2356 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2357 }
2358
2359 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2360 struct radv_winsys_sem_counts *counts,
2361 int num_sems,
2362 const VkSemaphore *sems,
2363 VkFence _fence,
2364 bool reset_temp)
2365 {
2366 int syncobj_idx = 0, sem_idx = 0;
2367
2368 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2369 return VK_SUCCESS;
2370
2371 for (uint32_t i = 0; i < num_sems; i++) {
2372 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2373
2374 if (sem->temp_syncobj || sem->syncobj)
2375 counts->syncobj_count++;
2376 else
2377 counts->sem_count++;
2378 }
2379
2380 if (_fence != VK_NULL_HANDLE) {
2381 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2382 if (fence->temp_syncobj || fence->syncobj)
2383 counts->syncobj_count++;
2384 }
2385
2386 if (counts->syncobj_count) {
2387 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2388 if (!counts->syncobj)
2389 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2390 }
2391
2392 if (counts->sem_count) {
2393 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2394 if (!counts->sem) {
2395 free(counts->syncobj);
2396 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2397 }
2398 }
2399
2400 for (uint32_t i = 0; i < num_sems; i++) {
2401 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2402
2403 if (sem->temp_syncobj) {
2404 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2405 }
2406 else if (sem->syncobj)
2407 counts->syncobj[syncobj_idx++] = sem->syncobj;
2408 else {
2409 assert(sem->sem);
2410 counts->sem[sem_idx++] = sem->sem;
2411 }
2412 }
2413
2414 if (_fence != VK_NULL_HANDLE) {
2415 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2416 if (fence->temp_syncobj)
2417 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2418 else if (fence->syncobj)
2419 counts->syncobj[syncobj_idx++] = fence->syncobj;
2420 }
2421
2422 return VK_SUCCESS;
2423 }
2424
2425 static void
2426 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2427 {
2428 free(sem_info->wait.syncobj);
2429 free(sem_info->wait.sem);
2430 free(sem_info->signal.syncobj);
2431 free(sem_info->signal.sem);
2432 }
2433
2434
2435 static void radv_free_temp_syncobjs(struct radv_device *device,
2436 int num_sems,
2437 const VkSemaphore *sems)
2438 {
2439 for (uint32_t i = 0; i < num_sems; i++) {
2440 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2441
2442 if (sem->temp_syncobj) {
2443 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2444 sem->temp_syncobj = 0;
2445 }
2446 }
2447 }
2448
2449 static VkResult
2450 radv_alloc_sem_info(struct radv_instance *instance,
2451 struct radv_winsys_sem_info *sem_info,
2452 int num_wait_sems,
2453 const VkSemaphore *wait_sems,
2454 int num_signal_sems,
2455 const VkSemaphore *signal_sems,
2456 VkFence fence)
2457 {
2458 VkResult ret;
2459 memset(sem_info, 0, sizeof(*sem_info));
2460
2461 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2462 if (ret)
2463 return ret;
2464 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2465 if (ret)
2466 radv_free_sem_info(sem_info);
2467
2468 /* caller can override these */
2469 sem_info->cs_emit_wait = true;
2470 sem_info->cs_emit_signal = true;
2471 return ret;
2472 }
2473
2474 /* Signals fence as soon as all the work currently put on queue is done. */
2475 static VkResult radv_signal_fence(struct radv_queue *queue,
2476 struct radv_fence *fence)
2477 {
2478 int ret;
2479 VkResult result;
2480 struct radv_winsys_sem_info sem_info;
2481
2482 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2483 radv_fence_to_handle(fence));
2484 if (result != VK_SUCCESS)
2485 return result;
2486
2487 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2488 &queue->device->empty_cs[queue->queue_family_index],
2489 1, NULL, NULL, &sem_info, NULL,
2490 false, fence->fence);
2491 radv_free_sem_info(&sem_info);
2492
2493 if (ret)
2494 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2495
2496 return VK_SUCCESS;
2497 }
2498
2499 VkResult radv_QueueSubmit(
2500 VkQueue _queue,
2501 uint32_t submitCount,
2502 const VkSubmitInfo* pSubmits,
2503 VkFence _fence)
2504 {
2505 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2506 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2507 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2508 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2509 int ret;
2510 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2511 uint32_t scratch_size = 0;
2512 uint32_t compute_scratch_size = 0;
2513 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2514 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2515 VkResult result;
2516 bool fence_emitted = false;
2517 bool tess_rings_needed = false;
2518 bool sample_positions_needed = false;
2519
2520 /* Do this first so failing to allocate scratch buffers can't result in
2521 * partially executed submissions. */
2522 for (uint32_t i = 0; i < submitCount; i++) {
2523 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2524 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2525 pSubmits[i].pCommandBuffers[j]);
2526
2527 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2528 compute_scratch_size = MAX2(compute_scratch_size,
2529 cmd_buffer->compute_scratch_size_needed);
2530 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2531 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2532 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2533 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2534 }
2535 }
2536
2537 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2538 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2539 sample_positions_needed, &initial_flush_preamble_cs,
2540 &initial_preamble_cs, &continue_preamble_cs);
2541 if (result != VK_SUCCESS)
2542 return result;
2543
2544 for (uint32_t i = 0; i < submitCount; i++) {
2545 struct radeon_cmdbuf **cs_array;
2546 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2547 bool can_patch = true;
2548 uint32_t advance;
2549 struct radv_winsys_sem_info sem_info;
2550
2551 result = radv_alloc_sem_info(queue->device->instance,
2552 &sem_info,
2553 pSubmits[i].waitSemaphoreCount,
2554 pSubmits[i].pWaitSemaphores,
2555 pSubmits[i].signalSemaphoreCount,
2556 pSubmits[i].pSignalSemaphores,
2557 _fence);
2558 if (result != VK_SUCCESS)
2559 return result;
2560
2561 if (!pSubmits[i].commandBufferCount) {
2562 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2563 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2564 &queue->device->empty_cs[queue->queue_family_index],
2565 1, NULL, NULL,
2566 &sem_info, NULL,
2567 false, base_fence);
2568 if (ret) {
2569 radv_loge("failed to submit CS %d\n", i);
2570 abort();
2571 }
2572 fence_emitted = true;
2573 }
2574 radv_free_sem_info(&sem_info);
2575 continue;
2576 }
2577
2578 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2579 (pSubmits[i].commandBufferCount));
2580
2581 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2582 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2583 pSubmits[i].pCommandBuffers[j]);
2584 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2585
2586 cs_array[j] = cmd_buffer->cs;
2587 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2588 can_patch = false;
2589
2590 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2591 }
2592
2593 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2594 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2595 const struct radv_winsys_bo_list *bo_list = NULL;
2596
2597 advance = MIN2(max_cs_submission,
2598 pSubmits[i].commandBufferCount - j);
2599
2600 if (queue->device->trace_bo)
2601 *queue->device->trace_id_ptr = 0;
2602
2603 sem_info.cs_emit_wait = j == 0;
2604 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2605
2606 if (unlikely(queue->device->use_global_bo_list)) {
2607 pthread_mutex_lock(&queue->device->bo_list.mutex);
2608 bo_list = &queue->device->bo_list.list;
2609 }
2610
2611 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2612 advance, initial_preamble, continue_preamble_cs,
2613 &sem_info, bo_list,
2614 can_patch, base_fence);
2615
2616 if (unlikely(queue->device->use_global_bo_list))
2617 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2618
2619 if (ret) {
2620 radv_loge("failed to submit CS %d\n", i);
2621 abort();
2622 }
2623 fence_emitted = true;
2624 if (queue->device->trace_bo) {
2625 radv_check_gpu_hangs(queue, cs_array[j]);
2626 }
2627 }
2628
2629 radv_free_temp_syncobjs(queue->device,
2630 pSubmits[i].waitSemaphoreCount,
2631 pSubmits[i].pWaitSemaphores);
2632 radv_free_sem_info(&sem_info);
2633 free(cs_array);
2634 }
2635
2636 if (fence) {
2637 if (!fence_emitted) {
2638 result = radv_signal_fence(queue, fence);
2639 if (result != VK_SUCCESS)
2640 return result;
2641 }
2642 fence->submitted = true;
2643 }
2644
2645 return VK_SUCCESS;
2646 }
2647
2648 VkResult radv_QueueWaitIdle(
2649 VkQueue _queue)
2650 {
2651 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2652
2653 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2654 radv_queue_family_to_ring(queue->queue_family_index),
2655 queue->queue_idx);
2656 return VK_SUCCESS;
2657 }
2658
2659 VkResult radv_DeviceWaitIdle(
2660 VkDevice _device)
2661 {
2662 RADV_FROM_HANDLE(radv_device, device, _device);
2663
2664 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2665 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2666 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2667 }
2668 }
2669 return VK_SUCCESS;
2670 }
2671
2672 VkResult radv_EnumerateInstanceExtensionProperties(
2673 const char* pLayerName,
2674 uint32_t* pPropertyCount,
2675 VkExtensionProperties* pProperties)
2676 {
2677 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2678
2679 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2680 if (radv_supported_instance_extensions.extensions[i]) {
2681 vk_outarray_append(&out, prop) {
2682 *prop = radv_instance_extensions[i];
2683 }
2684 }
2685 }
2686
2687 return vk_outarray_status(&out);
2688 }
2689
2690 VkResult radv_EnumerateDeviceExtensionProperties(
2691 VkPhysicalDevice physicalDevice,
2692 const char* pLayerName,
2693 uint32_t* pPropertyCount,
2694 VkExtensionProperties* pProperties)
2695 {
2696 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2697 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2698
2699 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2700 if (device->supported_extensions.extensions[i]) {
2701 vk_outarray_append(&out, prop) {
2702 *prop = radv_device_extensions[i];
2703 }
2704 }
2705 }
2706
2707 return vk_outarray_status(&out);
2708 }
2709
2710 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2711 VkInstance _instance,
2712 const char* pName)
2713 {
2714 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2715
2716 return radv_lookup_entrypoint_checked(pName,
2717 instance ? instance->apiVersion : 0,
2718 instance ? &instance->enabled_extensions : NULL,
2719 NULL);
2720 }
2721
2722 /* The loader wants us to expose a second GetInstanceProcAddr function
2723 * to work around certain LD_PRELOAD issues seen in apps.
2724 */
2725 PUBLIC
2726 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2727 VkInstance instance,
2728 const char* pName);
2729
2730 PUBLIC
2731 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2732 VkInstance instance,
2733 const char* pName)
2734 {
2735 return radv_GetInstanceProcAddr(instance, pName);
2736 }
2737
2738 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2739 VkDevice _device,
2740 const char* pName)
2741 {
2742 RADV_FROM_HANDLE(radv_device, device, _device);
2743
2744 return radv_lookup_entrypoint_checked(pName,
2745 device->instance->apiVersion,
2746 &device->instance->enabled_extensions,
2747 &device->enabled_extensions);
2748 }
2749
2750 bool radv_get_memory_fd(struct radv_device *device,
2751 struct radv_device_memory *memory,
2752 int *pFD)
2753 {
2754 struct radeon_bo_metadata metadata;
2755
2756 if (memory->image) {
2757 radv_init_metadata(device, memory->image, &metadata);
2758 device->ws->buffer_set_metadata(memory->bo, &metadata);
2759 }
2760
2761 return device->ws->buffer_get_fd(device->ws, memory->bo,
2762 pFD);
2763 }
2764
2765 static VkResult radv_alloc_memory(struct radv_device *device,
2766 const VkMemoryAllocateInfo* pAllocateInfo,
2767 const VkAllocationCallbacks* pAllocator,
2768 VkDeviceMemory* pMem)
2769 {
2770 struct radv_device_memory *mem;
2771 VkResult result;
2772 enum radeon_bo_domain domain;
2773 uint32_t flags = 0;
2774 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2775
2776 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2777
2778 if (pAllocateInfo->allocationSize == 0) {
2779 /* Apparently, this is allowed */
2780 *pMem = VK_NULL_HANDLE;
2781 return VK_SUCCESS;
2782 }
2783
2784 const VkImportMemoryFdInfoKHR *import_info =
2785 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2786 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2787 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2788 const VkExportMemoryAllocateInfoKHR *export_info =
2789 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2790 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2791 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2792
2793 const struct wsi_memory_allocate_info *wsi_info =
2794 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2795
2796 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2797 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2798 if (mem == NULL)
2799 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2800
2801 if (wsi_info && wsi_info->implicit_sync)
2802 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2803
2804 if (dedicate_info) {
2805 mem->image = radv_image_from_handle(dedicate_info->image);
2806 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2807 } else {
2808 mem->image = NULL;
2809 mem->buffer = NULL;
2810 }
2811
2812 mem->user_ptr = NULL;
2813
2814 if (import_info) {
2815 assert(import_info->handleType ==
2816 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2817 import_info->handleType ==
2818 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2819 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2820 NULL, NULL);
2821 if (!mem->bo) {
2822 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2823 goto fail;
2824 } else {
2825 close(import_info->fd);
2826 }
2827 } else if (host_ptr_info) {
2828 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2829 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2830 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2831 pAllocateInfo->allocationSize);
2832 if (!mem->bo) {
2833 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2834 goto fail;
2835 } else {
2836 mem->user_ptr = host_ptr_info->pHostPointer;
2837 }
2838 } else {
2839 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2840 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2841 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2842 domain = RADEON_DOMAIN_GTT;
2843 else
2844 domain = RADEON_DOMAIN_VRAM;
2845
2846 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2847 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2848 else
2849 flags |= RADEON_FLAG_CPU_ACCESS;
2850
2851 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2852 flags |= RADEON_FLAG_GTT_WC;
2853
2854 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2855 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2856
2857 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2858 domain, flags);
2859
2860 if (!mem->bo) {
2861 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2862 goto fail;
2863 }
2864 mem->type_index = mem_type_index;
2865 }
2866
2867 result = radv_bo_list_add(device, mem->bo);
2868 if (result != VK_SUCCESS)
2869 goto fail_bo;
2870
2871 *pMem = radv_device_memory_to_handle(mem);
2872
2873 return VK_SUCCESS;
2874
2875 fail_bo:
2876 device->ws->buffer_destroy(mem->bo);
2877 fail:
2878 vk_free2(&device->alloc, pAllocator, mem);
2879
2880 return result;
2881 }
2882
2883 VkResult radv_AllocateMemory(
2884 VkDevice _device,
2885 const VkMemoryAllocateInfo* pAllocateInfo,
2886 const VkAllocationCallbacks* pAllocator,
2887 VkDeviceMemory* pMem)
2888 {
2889 RADV_FROM_HANDLE(radv_device, device, _device);
2890 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2891 }
2892
2893 void radv_FreeMemory(
2894 VkDevice _device,
2895 VkDeviceMemory _mem,
2896 const VkAllocationCallbacks* pAllocator)
2897 {
2898 RADV_FROM_HANDLE(radv_device, device, _device);
2899 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2900
2901 if (mem == NULL)
2902 return;
2903
2904 radv_bo_list_remove(device, mem->bo);
2905 device->ws->buffer_destroy(mem->bo);
2906 mem->bo = NULL;
2907
2908 vk_free2(&device->alloc, pAllocator, mem);
2909 }
2910
2911 VkResult radv_MapMemory(
2912 VkDevice _device,
2913 VkDeviceMemory _memory,
2914 VkDeviceSize offset,
2915 VkDeviceSize size,
2916 VkMemoryMapFlags flags,
2917 void** ppData)
2918 {
2919 RADV_FROM_HANDLE(radv_device, device, _device);
2920 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2921
2922 if (mem == NULL) {
2923 *ppData = NULL;
2924 return VK_SUCCESS;
2925 }
2926
2927 if (mem->user_ptr)
2928 *ppData = mem->user_ptr;
2929 else
2930 *ppData = device->ws->buffer_map(mem->bo);
2931
2932 if (*ppData) {
2933 *ppData += offset;
2934 return VK_SUCCESS;
2935 }
2936
2937 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2938 }
2939
2940 void radv_UnmapMemory(
2941 VkDevice _device,
2942 VkDeviceMemory _memory)
2943 {
2944 RADV_FROM_HANDLE(radv_device, device, _device);
2945 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2946
2947 if (mem == NULL)
2948 return;
2949
2950 if (mem->user_ptr == NULL)
2951 device->ws->buffer_unmap(mem->bo);
2952 }
2953
2954 VkResult radv_FlushMappedMemoryRanges(
2955 VkDevice _device,
2956 uint32_t memoryRangeCount,
2957 const VkMappedMemoryRange* pMemoryRanges)
2958 {
2959 return VK_SUCCESS;
2960 }
2961
2962 VkResult radv_InvalidateMappedMemoryRanges(
2963 VkDevice _device,
2964 uint32_t memoryRangeCount,
2965 const VkMappedMemoryRange* pMemoryRanges)
2966 {
2967 return VK_SUCCESS;
2968 }
2969
2970 void radv_GetBufferMemoryRequirements(
2971 VkDevice _device,
2972 VkBuffer _buffer,
2973 VkMemoryRequirements* pMemoryRequirements)
2974 {
2975 RADV_FROM_HANDLE(radv_device, device, _device);
2976 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2977
2978 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2979
2980 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2981 pMemoryRequirements->alignment = 4096;
2982 else
2983 pMemoryRequirements->alignment = 16;
2984
2985 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2986 }
2987
2988 void radv_GetBufferMemoryRequirements2(
2989 VkDevice device,
2990 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2991 VkMemoryRequirements2KHR* pMemoryRequirements)
2992 {
2993 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2994 &pMemoryRequirements->memoryRequirements);
2995 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2996 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2997 switch (ext->sType) {
2998 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2999 VkMemoryDedicatedRequirementsKHR *req =
3000 (VkMemoryDedicatedRequirementsKHR *) ext;
3001 req->requiresDedicatedAllocation = buffer->shareable;
3002 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3003 break;
3004 }
3005 default:
3006 break;
3007 }
3008 }
3009 }
3010
3011 void radv_GetImageMemoryRequirements(
3012 VkDevice _device,
3013 VkImage _image,
3014 VkMemoryRequirements* pMemoryRequirements)
3015 {
3016 RADV_FROM_HANDLE(radv_device, device, _device);
3017 RADV_FROM_HANDLE(radv_image, image, _image);
3018
3019 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3020
3021 pMemoryRequirements->size = image->size;
3022 pMemoryRequirements->alignment = image->alignment;
3023 }
3024
3025 void radv_GetImageMemoryRequirements2(
3026 VkDevice device,
3027 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3028 VkMemoryRequirements2KHR* pMemoryRequirements)
3029 {
3030 radv_GetImageMemoryRequirements(device, pInfo->image,
3031 &pMemoryRequirements->memoryRequirements);
3032
3033 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3034
3035 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3036 switch (ext->sType) {
3037 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3038 VkMemoryDedicatedRequirementsKHR *req =
3039 (VkMemoryDedicatedRequirementsKHR *) ext;
3040 req->requiresDedicatedAllocation = image->shareable;
3041 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3042 break;
3043 }
3044 default:
3045 break;
3046 }
3047 }
3048 }
3049
3050 void radv_GetImageSparseMemoryRequirements(
3051 VkDevice device,
3052 VkImage image,
3053 uint32_t* pSparseMemoryRequirementCount,
3054 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3055 {
3056 stub();
3057 }
3058
3059 void radv_GetImageSparseMemoryRequirements2(
3060 VkDevice device,
3061 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3062 uint32_t* pSparseMemoryRequirementCount,
3063 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3064 {
3065 stub();
3066 }
3067
3068 void radv_GetDeviceMemoryCommitment(
3069 VkDevice device,
3070 VkDeviceMemory memory,
3071 VkDeviceSize* pCommittedMemoryInBytes)
3072 {
3073 *pCommittedMemoryInBytes = 0;
3074 }
3075
3076 VkResult radv_BindBufferMemory2(VkDevice device,
3077 uint32_t bindInfoCount,
3078 const VkBindBufferMemoryInfoKHR *pBindInfos)
3079 {
3080 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3081 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3082 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3083
3084 if (mem) {
3085 buffer->bo = mem->bo;
3086 buffer->offset = pBindInfos[i].memoryOffset;
3087 } else {
3088 buffer->bo = NULL;
3089 }
3090 }
3091 return VK_SUCCESS;
3092 }
3093
3094 VkResult radv_BindBufferMemory(
3095 VkDevice device,
3096 VkBuffer buffer,
3097 VkDeviceMemory memory,
3098 VkDeviceSize memoryOffset)
3099 {
3100 const VkBindBufferMemoryInfoKHR info = {
3101 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3102 .buffer = buffer,
3103 .memory = memory,
3104 .memoryOffset = memoryOffset
3105 };
3106
3107 return radv_BindBufferMemory2(device, 1, &info);
3108 }
3109
3110 VkResult radv_BindImageMemory2(VkDevice device,
3111 uint32_t bindInfoCount,
3112 const VkBindImageMemoryInfoKHR *pBindInfos)
3113 {
3114 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3115 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3116 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3117
3118 if (mem) {
3119 image->bo = mem->bo;
3120 image->offset = pBindInfos[i].memoryOffset;
3121 } else {
3122 image->bo = NULL;
3123 image->offset = 0;
3124 }
3125 }
3126 return VK_SUCCESS;
3127 }
3128
3129
3130 VkResult radv_BindImageMemory(
3131 VkDevice device,
3132 VkImage image,
3133 VkDeviceMemory memory,
3134 VkDeviceSize memoryOffset)
3135 {
3136 const VkBindImageMemoryInfoKHR info = {
3137 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3138 .image = image,
3139 .memory = memory,
3140 .memoryOffset = memoryOffset
3141 };
3142
3143 return radv_BindImageMemory2(device, 1, &info);
3144 }
3145
3146
3147 static void
3148 radv_sparse_buffer_bind_memory(struct radv_device *device,
3149 const VkSparseBufferMemoryBindInfo *bind)
3150 {
3151 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3152
3153 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3154 struct radv_device_memory *mem = NULL;
3155
3156 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3157 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3158
3159 device->ws->buffer_virtual_bind(buffer->bo,
3160 bind->pBinds[i].resourceOffset,
3161 bind->pBinds[i].size,
3162 mem ? mem->bo : NULL,
3163 bind->pBinds[i].memoryOffset);
3164 }
3165 }
3166
3167 static void
3168 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3169 const VkSparseImageOpaqueMemoryBindInfo *bind)
3170 {
3171 RADV_FROM_HANDLE(radv_image, image, bind->image);
3172
3173 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3174 struct radv_device_memory *mem = NULL;
3175
3176 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3177 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3178
3179 device->ws->buffer_virtual_bind(image->bo,
3180 bind->pBinds[i].resourceOffset,
3181 bind->pBinds[i].size,
3182 mem ? mem->bo : NULL,
3183 bind->pBinds[i].memoryOffset);
3184 }
3185 }
3186
3187 VkResult radv_QueueBindSparse(
3188 VkQueue _queue,
3189 uint32_t bindInfoCount,
3190 const VkBindSparseInfo* pBindInfo,
3191 VkFence _fence)
3192 {
3193 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3194 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3195 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3196 bool fence_emitted = false;
3197 VkResult result;
3198 int ret;
3199
3200 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3201 struct radv_winsys_sem_info sem_info;
3202 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3203 radv_sparse_buffer_bind_memory(queue->device,
3204 pBindInfo[i].pBufferBinds + j);
3205 }
3206
3207 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3208 radv_sparse_image_opaque_bind_memory(queue->device,
3209 pBindInfo[i].pImageOpaqueBinds + j);
3210 }
3211
3212 VkResult result;
3213 result = radv_alloc_sem_info(queue->device->instance,
3214 &sem_info,
3215 pBindInfo[i].waitSemaphoreCount,
3216 pBindInfo[i].pWaitSemaphores,
3217 pBindInfo[i].signalSemaphoreCount,
3218 pBindInfo[i].pSignalSemaphores,
3219 _fence);
3220 if (result != VK_SUCCESS)
3221 return result;
3222
3223 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3224 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3225 &queue->device->empty_cs[queue->queue_family_index],
3226 1, NULL, NULL,
3227 &sem_info, NULL,
3228 false, base_fence);
3229 if (ret) {
3230 radv_loge("failed to submit CS %d\n", i);
3231 abort();
3232 }
3233
3234 fence_emitted = true;
3235 if (fence)
3236 fence->submitted = true;
3237 }
3238
3239 radv_free_sem_info(&sem_info);
3240
3241 }
3242
3243 if (fence) {
3244 if (!fence_emitted) {
3245 result = radv_signal_fence(queue, fence);
3246 if (result != VK_SUCCESS)
3247 return result;
3248 }
3249 fence->submitted = true;
3250 }
3251
3252 return VK_SUCCESS;
3253 }
3254
3255 VkResult radv_CreateFence(
3256 VkDevice _device,
3257 const VkFenceCreateInfo* pCreateInfo,
3258 const VkAllocationCallbacks* pAllocator,
3259 VkFence* pFence)
3260 {
3261 RADV_FROM_HANDLE(radv_device, device, _device);
3262 const VkExportFenceCreateInfoKHR *export =
3263 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3264 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3265 export ? export->handleTypes : 0;
3266
3267 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3268 sizeof(*fence), 8,
3269 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3270
3271 if (!fence)
3272 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3273
3274 fence->fence_wsi = NULL;
3275 fence->submitted = false;
3276 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3277 fence->temp_syncobj = 0;
3278 if (device->always_use_syncobj || handleTypes) {
3279 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3280 if (ret) {
3281 vk_free2(&device->alloc, pAllocator, fence);
3282 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3283 }
3284 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3285 device->ws->signal_syncobj(device->ws, fence->syncobj);
3286 }
3287 fence->fence = NULL;
3288 } else {
3289 fence->fence = device->ws->create_fence();
3290 if (!fence->fence) {
3291 vk_free2(&device->alloc, pAllocator, fence);
3292 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3293 }
3294 fence->syncobj = 0;
3295 }
3296
3297 *pFence = radv_fence_to_handle(fence);
3298
3299 return VK_SUCCESS;
3300 }
3301
3302 void radv_DestroyFence(
3303 VkDevice _device,
3304 VkFence _fence,
3305 const VkAllocationCallbacks* pAllocator)
3306 {
3307 RADV_FROM_HANDLE(radv_device, device, _device);
3308 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3309
3310 if (!fence)
3311 return;
3312
3313 if (fence->temp_syncobj)
3314 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3315 if (fence->syncobj)
3316 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3317 if (fence->fence)
3318 device->ws->destroy_fence(fence->fence);
3319 if (fence->fence_wsi)
3320 fence->fence_wsi->destroy(fence->fence_wsi);
3321 vk_free2(&device->alloc, pAllocator, fence);
3322 }
3323
3324
3325 static uint64_t radv_get_current_time()
3326 {
3327 struct timespec tv;
3328 clock_gettime(CLOCK_MONOTONIC, &tv);
3329 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3330 }
3331
3332 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3333 {
3334 uint64_t current_time = radv_get_current_time();
3335
3336 timeout = MIN2(UINT64_MAX - current_time, timeout);
3337
3338 return current_time + timeout;
3339 }
3340
3341
3342 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3343 {
3344 for (uint32_t i = 0; i < fenceCount; ++i) {
3345 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3346 if (fence->fence == NULL || fence->syncobj ||
3347 fence->temp_syncobj ||
3348 (!fence->signalled && !fence->submitted))
3349 return false;
3350 }
3351 return true;
3352 }
3353
3354 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3355 {
3356 for (uint32_t i = 0; i < fenceCount; ++i) {
3357 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3358 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3359 return false;
3360 }
3361 return true;
3362 }
3363
3364 VkResult radv_WaitForFences(
3365 VkDevice _device,
3366 uint32_t fenceCount,
3367 const VkFence* pFences,
3368 VkBool32 waitAll,
3369 uint64_t timeout)
3370 {
3371 RADV_FROM_HANDLE(radv_device, device, _device);
3372 timeout = radv_get_absolute_timeout(timeout);
3373
3374 if (device->always_use_syncobj &&
3375 radv_all_fences_syncobj(fenceCount, pFences))
3376 {
3377 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3378 if (!handles)
3379 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3380
3381 for (uint32_t i = 0; i < fenceCount; ++i) {
3382 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3383 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3384 }
3385
3386 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3387
3388 free(handles);
3389 return success ? VK_SUCCESS : VK_TIMEOUT;
3390 }
3391
3392 if (!waitAll && fenceCount > 1) {
3393 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3394 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3395 uint32_t wait_count = 0;
3396 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3397 if (!fences)
3398 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3399
3400 for (uint32_t i = 0; i < fenceCount; ++i) {
3401 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3402
3403 if (fence->signalled) {
3404 free(fences);
3405 return VK_SUCCESS;
3406 }
3407
3408 fences[wait_count++] = fence->fence;
3409 }
3410
3411 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3412 waitAll, timeout - radv_get_current_time());
3413
3414 free(fences);
3415 return success ? VK_SUCCESS : VK_TIMEOUT;
3416 }
3417
3418 while(radv_get_current_time() <= timeout) {
3419 for (uint32_t i = 0; i < fenceCount; ++i) {
3420 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3421 return VK_SUCCESS;
3422 }
3423 }
3424 return VK_TIMEOUT;
3425 }
3426
3427 for (uint32_t i = 0; i < fenceCount; ++i) {
3428 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3429 bool expired = false;
3430
3431 if (fence->temp_syncobj) {
3432 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3433 return VK_TIMEOUT;
3434 continue;
3435 }
3436
3437 if (fence->syncobj) {
3438 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3439 return VK_TIMEOUT;
3440 continue;
3441 }
3442
3443 if (fence->signalled)
3444 continue;
3445
3446 if (fence->fence) {
3447 if (!fence->submitted) {
3448 while(radv_get_current_time() <= timeout &&
3449 !fence->submitted)
3450 /* Do nothing */;
3451
3452 if (!fence->submitted)
3453 return VK_TIMEOUT;
3454
3455 /* Recheck as it may have been set by
3456 * submitting operations. */
3457
3458 if (fence->signalled)
3459 continue;
3460 }
3461
3462 expired = device->ws->fence_wait(device->ws,
3463 fence->fence,
3464 true, timeout);
3465 if (!expired)
3466 return VK_TIMEOUT;
3467 }
3468
3469 if (fence->fence_wsi) {
3470 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3471 if (result != VK_SUCCESS)
3472 return result;
3473 }
3474
3475 fence->signalled = true;
3476 }
3477
3478 return VK_SUCCESS;
3479 }
3480
3481 VkResult radv_ResetFences(VkDevice _device,
3482 uint32_t fenceCount,
3483 const VkFence *pFences)
3484 {
3485 RADV_FROM_HANDLE(radv_device, device, _device);
3486
3487 for (unsigned i = 0; i < fenceCount; ++i) {
3488 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3489 fence->submitted = fence->signalled = false;
3490
3491 /* Per spec, we first restore the permanent payload, and then reset, so
3492 * having a temp syncobj should not skip resetting the permanent syncobj. */
3493 if (fence->temp_syncobj) {
3494 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3495 fence->temp_syncobj = 0;
3496 }
3497
3498 if (fence->syncobj) {
3499 device->ws->reset_syncobj(device->ws, fence->syncobj);
3500 }
3501 }
3502
3503 return VK_SUCCESS;
3504 }
3505
3506 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3507 {
3508 RADV_FROM_HANDLE(radv_device, device, _device);
3509 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3510
3511 if (fence->temp_syncobj) {
3512 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3513 return success ? VK_SUCCESS : VK_NOT_READY;
3514 }
3515
3516 if (fence->syncobj) {
3517 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3518 return success ? VK_SUCCESS : VK_NOT_READY;
3519 }
3520
3521 if (fence->signalled)
3522 return VK_SUCCESS;
3523 if (!fence->submitted)
3524 return VK_NOT_READY;
3525 if (fence->fence) {
3526 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3527 return VK_NOT_READY;
3528 }
3529 if (fence->fence_wsi) {
3530 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3531
3532 if (result != VK_SUCCESS) {
3533 if (result == VK_TIMEOUT)
3534 return VK_NOT_READY;
3535 return result;
3536 }
3537 }
3538 return VK_SUCCESS;
3539 }
3540
3541
3542 // Queue semaphore functions
3543
3544 VkResult radv_CreateSemaphore(
3545 VkDevice _device,
3546 const VkSemaphoreCreateInfo* pCreateInfo,
3547 const VkAllocationCallbacks* pAllocator,
3548 VkSemaphore* pSemaphore)
3549 {
3550 RADV_FROM_HANDLE(radv_device, device, _device);
3551 const VkExportSemaphoreCreateInfoKHR *export =
3552 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3553 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3554 export ? export->handleTypes : 0;
3555
3556 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3557 sizeof(*sem), 8,
3558 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3559 if (!sem)
3560 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3561
3562 sem->temp_syncobj = 0;
3563 /* create a syncobject if we are going to export this semaphore */
3564 if (device->always_use_syncobj || handleTypes) {
3565 assert (device->physical_device->rad_info.has_syncobj);
3566 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3567 if (ret) {
3568 vk_free2(&device->alloc, pAllocator, sem);
3569 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3570 }
3571 sem->sem = NULL;
3572 } else {
3573 sem->sem = device->ws->create_sem(device->ws);
3574 if (!sem->sem) {
3575 vk_free2(&device->alloc, pAllocator, sem);
3576 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3577 }
3578 sem->syncobj = 0;
3579 }
3580
3581 *pSemaphore = radv_semaphore_to_handle(sem);
3582 return VK_SUCCESS;
3583 }
3584
3585 void radv_DestroySemaphore(
3586 VkDevice _device,
3587 VkSemaphore _semaphore,
3588 const VkAllocationCallbacks* pAllocator)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3592 if (!_semaphore)
3593 return;
3594
3595 if (sem->syncobj)
3596 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3597 else
3598 device->ws->destroy_sem(sem->sem);
3599 vk_free2(&device->alloc, pAllocator, sem);
3600 }
3601
3602 VkResult radv_CreateEvent(
3603 VkDevice _device,
3604 const VkEventCreateInfo* pCreateInfo,
3605 const VkAllocationCallbacks* pAllocator,
3606 VkEvent* pEvent)
3607 {
3608 RADV_FROM_HANDLE(radv_device, device, _device);
3609 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3610 sizeof(*event), 8,
3611 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3612
3613 if (!event)
3614 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3615
3616 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3617 RADEON_DOMAIN_GTT,
3618 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3619 if (!event->bo) {
3620 vk_free2(&device->alloc, pAllocator, event);
3621 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3622 }
3623
3624 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3625
3626 *pEvent = radv_event_to_handle(event);
3627
3628 return VK_SUCCESS;
3629 }
3630
3631 void radv_DestroyEvent(
3632 VkDevice _device,
3633 VkEvent _event,
3634 const VkAllocationCallbacks* pAllocator)
3635 {
3636 RADV_FROM_HANDLE(radv_device, device, _device);
3637 RADV_FROM_HANDLE(radv_event, event, _event);
3638
3639 if (!event)
3640 return;
3641 device->ws->buffer_destroy(event->bo);
3642 vk_free2(&device->alloc, pAllocator, event);
3643 }
3644
3645 VkResult radv_GetEventStatus(
3646 VkDevice _device,
3647 VkEvent _event)
3648 {
3649 RADV_FROM_HANDLE(radv_event, event, _event);
3650
3651 if (*event->map == 1)
3652 return VK_EVENT_SET;
3653 return VK_EVENT_RESET;
3654 }
3655
3656 VkResult radv_SetEvent(
3657 VkDevice _device,
3658 VkEvent _event)
3659 {
3660 RADV_FROM_HANDLE(radv_event, event, _event);
3661 *event->map = 1;
3662
3663 return VK_SUCCESS;
3664 }
3665
3666 VkResult radv_ResetEvent(
3667 VkDevice _device,
3668 VkEvent _event)
3669 {
3670 RADV_FROM_HANDLE(radv_event, event, _event);
3671 *event->map = 0;
3672
3673 return VK_SUCCESS;
3674 }
3675
3676 VkResult radv_CreateBuffer(
3677 VkDevice _device,
3678 const VkBufferCreateInfo* pCreateInfo,
3679 const VkAllocationCallbacks* pAllocator,
3680 VkBuffer* pBuffer)
3681 {
3682 RADV_FROM_HANDLE(radv_device, device, _device);
3683 struct radv_buffer *buffer;
3684
3685 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3686
3687 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3688 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3689 if (buffer == NULL)
3690 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3691
3692 buffer->size = pCreateInfo->size;
3693 buffer->usage = pCreateInfo->usage;
3694 buffer->bo = NULL;
3695 buffer->offset = 0;
3696 buffer->flags = pCreateInfo->flags;
3697
3698 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3699 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3700
3701 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3702 buffer->bo = device->ws->buffer_create(device->ws,
3703 align64(buffer->size, 4096),
3704 4096, 0, RADEON_FLAG_VIRTUAL);
3705 if (!buffer->bo) {
3706 vk_free2(&device->alloc, pAllocator, buffer);
3707 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3708 }
3709 }
3710
3711 *pBuffer = radv_buffer_to_handle(buffer);
3712
3713 return VK_SUCCESS;
3714 }
3715
3716 void radv_DestroyBuffer(
3717 VkDevice _device,
3718 VkBuffer _buffer,
3719 const VkAllocationCallbacks* pAllocator)
3720 {
3721 RADV_FROM_HANDLE(radv_device, device, _device);
3722 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3723
3724 if (!buffer)
3725 return;
3726
3727 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3728 device->ws->buffer_destroy(buffer->bo);
3729
3730 vk_free2(&device->alloc, pAllocator, buffer);
3731 }
3732
3733 static inline unsigned
3734 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3735 {
3736 if (stencil)
3737 return image->surface.u.legacy.stencil_tiling_index[level];
3738 else
3739 return image->surface.u.legacy.tiling_index[level];
3740 }
3741
3742 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3743 {
3744 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3745 }
3746
3747 static uint32_t
3748 radv_init_dcc_control_reg(struct radv_device *device,
3749 struct radv_image_view *iview)
3750 {
3751 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3752 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3753 unsigned max_compressed_block_size;
3754 unsigned independent_64b_blocks;
3755
3756 if (device->physical_device->rad_info.chip_class < VI)
3757 return 0;
3758
3759 if (iview->image->info.samples > 1) {
3760 if (iview->image->surface.bpe == 1)
3761 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3762 else if (iview->image->surface.bpe == 2)
3763 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3764 }
3765
3766 if (!device->physical_device->rad_info.has_dedicated_vram) {
3767 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3768 * dGPU and 64 for APU because all of our APUs to date use
3769 * DIMMs which have a request granularity size of 64B while all
3770 * other chips have a 32B request size.
3771 */
3772 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3773 }
3774
3775 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3776 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3777 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3778 /* If this DCC image is potentially going to be used in texture
3779 * fetches, we need some special settings.
3780 */
3781 independent_64b_blocks = 1;
3782 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3783 } else {
3784 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3785 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3786 * big as possible for better compression state.
3787 */
3788 independent_64b_blocks = 0;
3789 max_compressed_block_size = max_uncompressed_block_size;
3790 }
3791
3792 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3793 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3794 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3795 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3796 }
3797
3798 static void
3799 radv_initialise_color_surface(struct radv_device *device,
3800 struct radv_color_buffer_info *cb,
3801 struct radv_image_view *iview)
3802 {
3803 const struct vk_format_description *desc;
3804 unsigned ntype, format, swap, endian;
3805 unsigned blend_clamp = 0, blend_bypass = 0;
3806 uint64_t va;
3807 const struct radeon_surf *surf = &iview->image->surface;
3808
3809 desc = vk_format_description(iview->vk_format);
3810
3811 memset(cb, 0, sizeof(*cb));
3812
3813 /* Intensity is implemented as Red, so treat it that way. */
3814 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3815
3816 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3817
3818 cb->cb_color_base = va >> 8;
3819
3820 if (device->physical_device->rad_info.chip_class >= GFX9) {
3821 struct gfx9_surf_meta_flags meta;
3822 if (iview->image->dcc_offset)
3823 meta = iview->image->surface.u.gfx9.dcc;
3824 else
3825 meta = iview->image->surface.u.gfx9.cmask;
3826
3827 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3828 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3829 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3830 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3831
3832 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3833 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3834 } else {
3835 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3836 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3837
3838 cb->cb_color_base += level_info->offset >> 8;
3839 if (level_info->mode == RADEON_SURF_MODE_2D)
3840 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3841
3842 pitch_tile_max = level_info->nblk_x / 8 - 1;
3843 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3844 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3845
3846 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3847 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3848 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3849
3850 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3851
3852 if (radv_image_has_fmask(iview->image)) {
3853 if (device->physical_device->rad_info.chip_class >= CIK)
3854 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3855 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3856 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3857 } else {
3858 /* This must be set for fast clear to work without FMASK. */
3859 if (device->physical_device->rad_info.chip_class >= CIK)
3860 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3861 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3862 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3863 }
3864 }
3865
3866 /* CMASK variables */
3867 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3868 va += iview->image->cmask.offset;
3869 cb->cb_color_cmask = va >> 8;
3870
3871 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3872 va += iview->image->dcc_offset;
3873 cb->cb_dcc_base = va >> 8;
3874 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3875
3876 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3877 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3878 S_028C6C_SLICE_MAX(max_slice);
3879
3880 if (iview->image->info.samples > 1) {
3881 unsigned log_samples = util_logbase2(iview->image->info.samples);
3882
3883 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3884 S_028C74_NUM_FRAGMENTS(log_samples);
3885 }
3886
3887 if (radv_image_has_fmask(iview->image)) {
3888 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3889 cb->cb_color_fmask = va >> 8;
3890 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3891 } else {
3892 cb->cb_color_fmask = cb->cb_color_base;
3893 }
3894
3895 ntype = radv_translate_color_numformat(iview->vk_format,
3896 desc,
3897 vk_format_get_first_non_void_channel(iview->vk_format));
3898 format = radv_translate_colorformat(iview->vk_format);
3899 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3900 radv_finishme("Illegal color\n");
3901 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3902 endian = radv_colorformat_endian_swap(format);
3903
3904 /* blend clamp should be set for all NORM/SRGB types */
3905 if (ntype == V_028C70_NUMBER_UNORM ||
3906 ntype == V_028C70_NUMBER_SNORM ||
3907 ntype == V_028C70_NUMBER_SRGB)
3908 blend_clamp = 1;
3909
3910 /* set blend bypass according to docs if SINT/UINT or
3911 8/24 COLOR variants */
3912 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3913 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3914 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3915 blend_clamp = 0;
3916 blend_bypass = 1;
3917 }
3918 #if 0
3919 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3920 (format == V_028C70_COLOR_8 ||
3921 format == V_028C70_COLOR_8_8 ||
3922 format == V_028C70_COLOR_8_8_8_8))
3923 ->color_is_int8 = true;
3924 #endif
3925 cb->cb_color_info = S_028C70_FORMAT(format) |
3926 S_028C70_COMP_SWAP(swap) |
3927 S_028C70_BLEND_CLAMP(blend_clamp) |
3928 S_028C70_BLEND_BYPASS(blend_bypass) |
3929 S_028C70_SIMPLE_FLOAT(1) |
3930 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3931 ntype != V_028C70_NUMBER_SNORM &&
3932 ntype != V_028C70_NUMBER_SRGB &&
3933 format != V_028C70_COLOR_8_24 &&
3934 format != V_028C70_COLOR_24_8) |
3935 S_028C70_NUMBER_TYPE(ntype) |
3936 S_028C70_ENDIAN(endian);
3937 if (radv_image_has_fmask(iview->image)) {
3938 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3939 if (device->physical_device->rad_info.chip_class == SI) {
3940 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3941 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3942 }
3943 }
3944
3945 if (radv_image_has_cmask(iview->image) &&
3946 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3947 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3948
3949 if (radv_dcc_enabled(iview->image, iview->base_mip))
3950 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3951
3952 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3953
3954 /* This must be set for fast clear to work without FMASK. */
3955 if (!radv_image_has_fmask(iview->image) &&
3956 device->physical_device->rad_info.chip_class == SI) {
3957 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3958 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3959 }
3960
3961 if (device->physical_device->rad_info.chip_class >= GFX9) {
3962 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3963 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3964
3965 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3966 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3967 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3968 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3969 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3970 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3971 }
3972 }
3973
3974 static unsigned
3975 radv_calc_decompress_on_z_planes(struct radv_device *device,
3976 struct radv_image_view *iview)
3977 {
3978 unsigned max_zplanes = 0;
3979
3980 assert(radv_image_is_tc_compat_htile(iview->image));
3981
3982 if (device->physical_device->rad_info.chip_class >= GFX9) {
3983 /* Default value for 32-bit depth surfaces. */
3984 max_zplanes = 4;
3985
3986 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3987 iview->image->info.samples > 1)
3988 max_zplanes = 2;
3989
3990 max_zplanes = max_zplanes + 1;
3991 } else {
3992 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3993 /* Do not enable Z plane compression for 16-bit depth
3994 * surfaces because isn't supported on GFX8. Only
3995 * 32-bit depth surfaces are supported by the hardware.
3996 * This allows to maintain shader compatibility and to
3997 * reduce the number of depth decompressions.
3998 */
3999 max_zplanes = 1;
4000 } else {
4001 if (iview->image->info.samples <= 1)
4002 max_zplanes = 5;
4003 else if (iview->image->info.samples <= 4)
4004 max_zplanes = 3;
4005 else
4006 max_zplanes = 2;
4007 }
4008 }
4009
4010 return max_zplanes;
4011 }
4012
4013 static void
4014 radv_initialise_ds_surface(struct radv_device *device,
4015 struct radv_ds_buffer_info *ds,
4016 struct radv_image_view *iview)
4017 {
4018 unsigned level = iview->base_mip;
4019 unsigned format, stencil_format;
4020 uint64_t va, s_offs, z_offs;
4021 bool stencil_only = false;
4022 memset(ds, 0, sizeof(*ds));
4023 switch (iview->image->vk_format) {
4024 case VK_FORMAT_D24_UNORM_S8_UINT:
4025 case VK_FORMAT_X8_D24_UNORM_PACK32:
4026 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4027 ds->offset_scale = 2.0f;
4028 break;
4029 case VK_FORMAT_D16_UNORM:
4030 case VK_FORMAT_D16_UNORM_S8_UINT:
4031 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4032 ds->offset_scale = 4.0f;
4033 break;
4034 case VK_FORMAT_D32_SFLOAT:
4035 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4036 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4037 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4038 ds->offset_scale = 1.0f;
4039 break;
4040 case VK_FORMAT_S8_UINT:
4041 stencil_only = true;
4042 break;
4043 default:
4044 break;
4045 }
4046
4047 format = radv_translate_dbformat(iview->image->vk_format);
4048 stencil_format = iview->image->surface.has_stencil ?
4049 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4050
4051 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4052 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4053 S_028008_SLICE_MAX(max_slice);
4054
4055 ds->db_htile_data_base = 0;
4056 ds->db_htile_surface = 0;
4057
4058 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4059 s_offs = z_offs = va;
4060
4061 if (device->physical_device->rad_info.chip_class >= GFX9) {
4062 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4063 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4064
4065 ds->db_z_info = S_028038_FORMAT(format) |
4066 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4067 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4068 S_028038_MAXMIP(iview->image->info.levels - 1) |
4069 S_028038_ZRANGE_PRECISION(1);
4070 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4071 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4072
4073 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4074 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4075 ds->db_depth_view |= S_028008_MIPID(level);
4076
4077 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4078 S_02801C_Y_MAX(iview->image->info.height - 1);
4079
4080 if (radv_htile_enabled(iview->image, level)) {
4081 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4082
4083 if (radv_image_is_tc_compat_htile(iview->image)) {
4084 unsigned max_zplanes =
4085 radv_calc_decompress_on_z_planes(device, iview);
4086
4087 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4088 S_028038_ITERATE_FLUSH(1);
4089 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4090 }
4091
4092 if (!iview->image->surface.has_stencil)
4093 /* Use all of the htile_buffer for depth if there's no stencil. */
4094 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4095 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4096 iview->image->htile_offset;
4097 ds->db_htile_data_base = va >> 8;
4098 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4099 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4100 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4101 }
4102 } else {
4103 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4104
4105 if (stencil_only)
4106 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4107
4108 z_offs += iview->image->surface.u.legacy.level[level].offset;
4109 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4110
4111 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4112 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4113 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4114
4115 if (iview->image->info.samples > 1)
4116 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4117
4118 if (device->physical_device->rad_info.chip_class >= CIK) {
4119 struct radeon_info *info = &device->physical_device->rad_info;
4120 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4121 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4122 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4123 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4124 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4125 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4126
4127 if (stencil_only)
4128 tile_mode = stencil_tile_mode;
4129
4130 ds->db_depth_info |=
4131 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4132 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4133 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4134 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4135 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4136 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4137 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4138 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4139 } else {
4140 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4141 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4142 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4143 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4144 if (stencil_only)
4145 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4146 }
4147
4148 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4149 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4150 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4151
4152 if (radv_htile_enabled(iview->image, level)) {
4153 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4154
4155 if (!iview->image->surface.has_stencil &&
4156 !radv_image_is_tc_compat_htile(iview->image))
4157 /* Use all of the htile_buffer for depth if there's no stencil. */
4158 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4159
4160 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4161 iview->image->htile_offset;
4162 ds->db_htile_data_base = va >> 8;
4163 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4164
4165 if (radv_image_is_tc_compat_htile(iview->image)) {
4166 unsigned max_zplanes =
4167 radv_calc_decompress_on_z_planes(device, iview);
4168
4169 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4170 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4171 }
4172 }
4173 }
4174
4175 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4176 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4177 }
4178
4179 VkResult radv_CreateFramebuffer(
4180 VkDevice _device,
4181 const VkFramebufferCreateInfo* pCreateInfo,
4182 const VkAllocationCallbacks* pAllocator,
4183 VkFramebuffer* pFramebuffer)
4184 {
4185 RADV_FROM_HANDLE(radv_device, device, _device);
4186 struct radv_framebuffer *framebuffer;
4187
4188 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4189
4190 size_t size = sizeof(*framebuffer) +
4191 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4192 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4193 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4194 if (framebuffer == NULL)
4195 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4196
4197 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4198 framebuffer->width = pCreateInfo->width;
4199 framebuffer->height = pCreateInfo->height;
4200 framebuffer->layers = pCreateInfo->layers;
4201 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4202 VkImageView _iview = pCreateInfo->pAttachments[i];
4203 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4204 framebuffer->attachments[i].attachment = iview;
4205 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4206 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4207 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4208 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4209 }
4210 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4211 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4212 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4213 }
4214
4215 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4216 return VK_SUCCESS;
4217 }
4218
4219 void radv_DestroyFramebuffer(
4220 VkDevice _device,
4221 VkFramebuffer _fb,
4222 const VkAllocationCallbacks* pAllocator)
4223 {
4224 RADV_FROM_HANDLE(radv_device, device, _device);
4225 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4226
4227 if (!fb)
4228 return;
4229 vk_free2(&device->alloc, pAllocator, fb);
4230 }
4231
4232 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4233 {
4234 switch (address_mode) {
4235 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4236 return V_008F30_SQ_TEX_WRAP;
4237 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4238 return V_008F30_SQ_TEX_MIRROR;
4239 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4240 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4241 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4242 return V_008F30_SQ_TEX_CLAMP_BORDER;
4243 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4244 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4245 default:
4246 unreachable("illegal tex wrap mode");
4247 break;
4248 }
4249 }
4250
4251 static unsigned
4252 radv_tex_compare(VkCompareOp op)
4253 {
4254 switch (op) {
4255 case VK_COMPARE_OP_NEVER:
4256 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4257 case VK_COMPARE_OP_LESS:
4258 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4259 case VK_COMPARE_OP_EQUAL:
4260 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4261 case VK_COMPARE_OP_LESS_OR_EQUAL:
4262 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4263 case VK_COMPARE_OP_GREATER:
4264 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4265 case VK_COMPARE_OP_NOT_EQUAL:
4266 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4267 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4268 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4269 case VK_COMPARE_OP_ALWAYS:
4270 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4271 default:
4272 unreachable("illegal compare mode");
4273 break;
4274 }
4275 }
4276
4277 static unsigned
4278 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4279 {
4280 switch (filter) {
4281 case VK_FILTER_NEAREST:
4282 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4283 V_008F38_SQ_TEX_XY_FILTER_POINT);
4284 case VK_FILTER_LINEAR:
4285 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4286 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4287 case VK_FILTER_CUBIC_IMG:
4288 default:
4289 fprintf(stderr, "illegal texture filter");
4290 return 0;
4291 }
4292 }
4293
4294 static unsigned
4295 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4296 {
4297 switch (mode) {
4298 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4299 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4300 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4301 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4302 default:
4303 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4304 }
4305 }
4306
4307 static unsigned
4308 radv_tex_bordercolor(VkBorderColor bcolor)
4309 {
4310 switch (bcolor) {
4311 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4312 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4313 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4314 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4315 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4316 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4317 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4318 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4319 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4320 default:
4321 break;
4322 }
4323 return 0;
4324 }
4325
4326 static unsigned
4327 radv_tex_aniso_filter(unsigned filter)
4328 {
4329 if (filter < 2)
4330 return 0;
4331 if (filter < 4)
4332 return 1;
4333 if (filter < 8)
4334 return 2;
4335 if (filter < 16)
4336 return 3;
4337 return 4;
4338 }
4339
4340 static unsigned
4341 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4342 {
4343 switch (mode) {
4344 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4345 return SQ_IMG_FILTER_MODE_BLEND;
4346 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4347 return SQ_IMG_FILTER_MODE_MIN;
4348 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4349 return SQ_IMG_FILTER_MODE_MAX;
4350 default:
4351 break;
4352 }
4353 return 0;
4354 }
4355
4356 static void
4357 radv_init_sampler(struct radv_device *device,
4358 struct radv_sampler *sampler,
4359 const VkSamplerCreateInfo *pCreateInfo)
4360 {
4361 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4362 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4363 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4364 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4365 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4366
4367 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4368 vk_find_struct_const(pCreateInfo->pNext,
4369 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4370 if (sampler_reduction)
4371 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4372
4373 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4374 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4375 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4376 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4377 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4378 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4379 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4380 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4381 S_008F30_DISABLE_CUBE_WRAP(0) |
4382 S_008F30_COMPAT_MODE(is_vi) |
4383 S_008F30_FILTER_MODE(filter_mode));
4384 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4385 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4386 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4387 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4388 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4389 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4390 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4391 S_008F38_MIP_POINT_PRECLAMP(0) |
4392 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4393 S_008F38_FILTER_PREC_FIX(1) |
4394 S_008F38_ANISO_OVERRIDE(is_vi));
4395 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4396 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4397 }
4398
4399 VkResult radv_CreateSampler(
4400 VkDevice _device,
4401 const VkSamplerCreateInfo* pCreateInfo,
4402 const VkAllocationCallbacks* pAllocator,
4403 VkSampler* pSampler)
4404 {
4405 RADV_FROM_HANDLE(radv_device, device, _device);
4406 struct radv_sampler *sampler;
4407
4408 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4409
4410 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4411 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4412 if (!sampler)
4413 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4414
4415 radv_init_sampler(device, sampler, pCreateInfo);
4416 *pSampler = radv_sampler_to_handle(sampler);
4417
4418 return VK_SUCCESS;
4419 }
4420
4421 void radv_DestroySampler(
4422 VkDevice _device,
4423 VkSampler _sampler,
4424 const VkAllocationCallbacks* pAllocator)
4425 {
4426 RADV_FROM_HANDLE(radv_device, device, _device);
4427 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4428
4429 if (!sampler)
4430 return;
4431 vk_free2(&device->alloc, pAllocator, sampler);
4432 }
4433
4434 /* vk_icd.h does not declare this function, so we declare it here to
4435 * suppress Wmissing-prototypes.
4436 */
4437 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4438 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4439
4440 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4441 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4442 {
4443 /* For the full details on loader interface versioning, see
4444 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4445 * What follows is a condensed summary, to help you navigate the large and
4446 * confusing official doc.
4447 *
4448 * - Loader interface v0 is incompatible with later versions. We don't
4449 * support it.
4450 *
4451 * - In loader interface v1:
4452 * - The first ICD entrypoint called by the loader is
4453 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4454 * entrypoint.
4455 * - The ICD must statically expose no other Vulkan symbol unless it is
4456 * linked with -Bsymbolic.
4457 * - Each dispatchable Vulkan handle created by the ICD must be
4458 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4459 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4460 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4461 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4462 * such loader-managed surfaces.
4463 *
4464 * - Loader interface v2 differs from v1 in:
4465 * - The first ICD entrypoint called by the loader is
4466 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4467 * statically expose this entrypoint.
4468 *
4469 * - Loader interface v3 differs from v2 in:
4470 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4471 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4472 * because the loader no longer does so.
4473 */
4474 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4475 return VK_SUCCESS;
4476 }
4477
4478 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4479 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4480 int *pFD)
4481 {
4482 RADV_FROM_HANDLE(radv_device, device, _device);
4483 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4484
4485 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4486
4487 /* At the moment, we support only the below handle types. */
4488 assert(pGetFdInfo->handleType ==
4489 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4490 pGetFdInfo->handleType ==
4491 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4492
4493 bool ret = radv_get_memory_fd(device, memory, pFD);
4494 if (ret == false)
4495 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4496 return VK_SUCCESS;
4497 }
4498
4499 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4500 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4501 int fd,
4502 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4503 {
4504 RADV_FROM_HANDLE(radv_device, device, _device);
4505
4506 switch (handleType) {
4507 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4508 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4509 return VK_SUCCESS;
4510
4511 default:
4512 /* The valid usage section for this function says:
4513 *
4514 * "handleType must not be one of the handle types defined as
4515 * opaque."
4516 *
4517 * So opaque handle types fall into the default "unsupported" case.
4518 */
4519 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4520 }
4521 }
4522
4523 static VkResult radv_import_opaque_fd(struct radv_device *device,
4524 int fd,
4525 uint32_t *syncobj)
4526 {
4527 uint32_t syncobj_handle = 0;
4528 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4529 if (ret != 0)
4530 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4531
4532 if (*syncobj)
4533 device->ws->destroy_syncobj(device->ws, *syncobj);
4534
4535 *syncobj = syncobj_handle;
4536 close(fd);
4537
4538 return VK_SUCCESS;
4539 }
4540
4541 static VkResult radv_import_sync_fd(struct radv_device *device,
4542 int fd,
4543 uint32_t *syncobj)
4544 {
4545 /* If we create a syncobj we do it locally so that if we have an error, we don't
4546 * leave a syncobj in an undetermined state in the fence. */
4547 uint32_t syncobj_handle = *syncobj;
4548 if (!syncobj_handle) {
4549 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4550 if (ret) {
4551 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4552 }
4553 }
4554
4555 if (fd == -1) {
4556 device->ws->signal_syncobj(device->ws, syncobj_handle);
4557 } else {
4558 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4559 if (ret != 0)
4560 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4561 }
4562
4563 *syncobj = syncobj_handle;
4564 if (fd != -1)
4565 close(fd);
4566
4567 return VK_SUCCESS;
4568 }
4569
4570 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4571 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4572 {
4573 RADV_FROM_HANDLE(radv_device, device, _device);
4574 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4575 uint32_t *syncobj_dst = NULL;
4576
4577 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4578 syncobj_dst = &sem->temp_syncobj;
4579 } else {
4580 syncobj_dst = &sem->syncobj;
4581 }
4582
4583 switch(pImportSemaphoreFdInfo->handleType) {
4584 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4585 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4586 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4587 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4588 default:
4589 unreachable("Unhandled semaphore handle type");
4590 }
4591 }
4592
4593 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4594 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4595 int *pFd)
4596 {
4597 RADV_FROM_HANDLE(radv_device, device, _device);
4598 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4599 int ret;
4600 uint32_t syncobj_handle;
4601
4602 if (sem->temp_syncobj)
4603 syncobj_handle = sem->temp_syncobj;
4604 else
4605 syncobj_handle = sem->syncobj;
4606
4607 switch(pGetFdInfo->handleType) {
4608 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4609 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4610 break;
4611 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4612 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4613 if (!ret) {
4614 if (sem->temp_syncobj) {
4615 close (sem->temp_syncobj);
4616 sem->temp_syncobj = 0;
4617 } else {
4618 device->ws->reset_syncobj(device->ws, syncobj_handle);
4619 }
4620 }
4621 break;
4622 default:
4623 unreachable("Unhandled semaphore handle type");
4624 }
4625
4626 if (ret)
4627 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4628 return VK_SUCCESS;
4629 }
4630
4631 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4632 VkPhysicalDevice physicalDevice,
4633 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4634 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4635 {
4636 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4637
4638 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4639 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4640 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4641 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4642 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4643 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4644 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4645 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4646 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4647 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4648 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4649 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4650 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4651 } else {
4652 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4653 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4654 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4655 }
4656 }
4657
4658 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4659 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4660 {
4661 RADV_FROM_HANDLE(radv_device, device, _device);
4662 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4663 uint32_t *syncobj_dst = NULL;
4664
4665
4666 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4667 syncobj_dst = &fence->temp_syncobj;
4668 } else {
4669 syncobj_dst = &fence->syncobj;
4670 }
4671
4672 switch(pImportFenceFdInfo->handleType) {
4673 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4674 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4675 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4676 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4677 default:
4678 unreachable("Unhandled fence handle type");
4679 }
4680 }
4681
4682 VkResult radv_GetFenceFdKHR(VkDevice _device,
4683 const VkFenceGetFdInfoKHR *pGetFdInfo,
4684 int *pFd)
4685 {
4686 RADV_FROM_HANDLE(radv_device, device, _device);
4687 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4688 int ret;
4689 uint32_t syncobj_handle;
4690
4691 if (fence->temp_syncobj)
4692 syncobj_handle = fence->temp_syncobj;
4693 else
4694 syncobj_handle = fence->syncobj;
4695
4696 switch(pGetFdInfo->handleType) {
4697 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4698 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4699 break;
4700 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4701 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4702 if (!ret) {
4703 if (fence->temp_syncobj) {
4704 close (fence->temp_syncobj);
4705 fence->temp_syncobj = 0;
4706 } else {
4707 device->ws->reset_syncobj(device->ws, syncobj_handle);
4708 }
4709 }
4710 break;
4711 default:
4712 unreachable("Unhandled fence handle type");
4713 }
4714
4715 if (ret)
4716 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4717 return VK_SUCCESS;
4718 }
4719
4720 void radv_GetPhysicalDeviceExternalFenceProperties(
4721 VkPhysicalDevice physicalDevice,
4722 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4723 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4724 {
4725 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4726
4727 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4728 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4729 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4730 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4731 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4732 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4733 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4734 } else {
4735 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4736 pExternalFenceProperties->compatibleHandleTypes = 0;
4737 pExternalFenceProperties->externalFenceFeatures = 0;
4738 }
4739 }
4740
4741 VkResult
4742 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4743 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4744 const VkAllocationCallbacks* pAllocator,
4745 VkDebugReportCallbackEXT* pCallback)
4746 {
4747 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4748 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4749 pCreateInfo, pAllocator, &instance->alloc,
4750 pCallback);
4751 }
4752
4753 void
4754 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4755 VkDebugReportCallbackEXT _callback,
4756 const VkAllocationCallbacks* pAllocator)
4757 {
4758 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4759 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4760 _callback, pAllocator, &instance->alloc);
4761 }
4762
4763 void
4764 radv_DebugReportMessageEXT(VkInstance _instance,
4765 VkDebugReportFlagsEXT flags,
4766 VkDebugReportObjectTypeEXT objectType,
4767 uint64_t object,
4768 size_t location,
4769 int32_t messageCode,
4770 const char* pLayerPrefix,
4771 const char* pMessage)
4772 {
4773 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4774 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4775 object, location, messageCode, pLayerPrefix, pMessage);
4776 }
4777
4778 void
4779 radv_GetDeviceGroupPeerMemoryFeatures(
4780 VkDevice device,
4781 uint32_t heapIndex,
4782 uint32_t localDeviceIndex,
4783 uint32_t remoteDeviceIndex,
4784 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4785 {
4786 assert(localDeviceIndex == remoteDeviceIndex);
4787
4788 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4789 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4790 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4791 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4792 }