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ac: add has_dcc_constant_encode to ac_gpu_info
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
181 .heapIndex = gart_index,
182 };
183 }
184 if (visible_vram_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
188 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
189 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
190 .heapIndex = visible_vram_index,
191 };
192 }
193 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
194 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
195 * as they have identical property flags, and according to the
196 * spec, for types with identical flags, the one with greater
197 * performance must be given a lower index. */
198 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
199 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
200 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
201 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
202 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
203 .heapIndex = gart_index,
204 };
205 }
206 if (gart_index >= 0) {
207 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
208 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
209 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
210 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
211 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
212 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
213 .heapIndex = gart_index,
214 };
215 }
216 device->memory_properties.memoryTypeCount = type_count;
217 }
218
219 static void
220 radv_handle_env_var_force_family(struct radv_physical_device *device)
221 {
222 const char *family = getenv("RADV_FORCE_FAMILY");
223 unsigned i;
224
225 if (!family)
226 return;
227
228 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
229 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
230 /* Override family and chip_class. */
231 device->rad_info.family = i;
232
233 if (i >= CHIP_NAVI10)
234 device->rad_info.chip_class = GFX10;
235 else if (i >= CHIP_VEGA10)
236 device->rad_info.chip_class = GFX9;
237 else if (i >= CHIP_TONGA)
238 device->rad_info.chip_class = GFX8;
239 else if (i >= CHIP_BONAIRE)
240 device->rad_info.chip_class = GFX7;
241 else
242 device->rad_info.chip_class = GFX6;
243
244 return;
245 }
246 }
247
248 fprintf(stderr, "radv: Unknown family: %s\n", family);
249 exit(1);
250 }
251
252 static VkResult
253 radv_physical_device_init(struct radv_physical_device *device,
254 struct radv_instance *instance,
255 drmDevicePtr drm_device)
256 {
257 const char *path = drm_device->nodes[DRM_NODE_RENDER];
258 VkResult result;
259 drmVersionPtr version;
260 int fd;
261 int master_fd = -1;
262
263 fd = open(path, O_RDWR | O_CLOEXEC);
264 if (fd < 0) {
265 if (instance->debug_flags & RADV_DEBUG_STARTUP)
266 radv_logi("Could not open device '%s'", path);
267
268 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
269 }
270
271 version = drmGetVersion(fd);
272 if (!version) {
273 close(fd);
274
275 if (instance->debug_flags & RADV_DEBUG_STARTUP)
276 radv_logi("Could not get the kernel driver version for device '%s'", path);
277
278 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
279 "failed to get version %s: %m", path);
280 }
281
282 if (strcmp(version->name, "amdgpu")) {
283 drmFreeVersion(version);
284 close(fd);
285
286 if (instance->debug_flags & RADV_DEBUG_STARTUP)
287 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
288
289 return VK_ERROR_INCOMPATIBLE_DRIVER;
290 }
291 drmFreeVersion(version);
292
293 if (instance->debug_flags & RADV_DEBUG_STARTUP)
294 radv_logi("Found compatible device '%s'.", path);
295
296 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
297 device->instance = instance;
298
299 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
300 instance->perftest_flags);
301 if (!device->ws) {
302 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
303 goto fail;
304 }
305
306 if (instance->enabled_extensions.KHR_display) {
307 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
308 if (master_fd >= 0) {
309 uint32_t accel_working = 0;
310 struct drm_amdgpu_info request = {
311 .return_pointer = (uintptr_t)&accel_working,
312 .return_size = sizeof(accel_working),
313 .query = AMDGPU_INFO_ACCEL_WORKING
314 };
315
316 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
317 close(master_fd);
318 master_fd = -1;
319 }
320 }
321 }
322
323 device->master_fd = master_fd;
324 device->local_fd = fd;
325 device->ws->query_info(device->ws, &device->rad_info);
326
327 radv_handle_env_var_force_family(device);
328
329 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
330
331 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
332 device->ws->destroy(device->ws);
333 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
334 "cannot generate UUID");
335 goto fail;
336 }
337
338 /* These flags affect shader compilation. */
339 uint64_t shader_env_flags =
340 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
341 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
342
343 /* The gpu id is already embedded in the uuid so we just pass "radv"
344 * when creating the cache.
345 */
346 char buf[VK_UUID_SIZE * 2 + 1];
347 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
348 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
349
350 if (device->rad_info.chip_class < GFX8 ||
351 device->rad_info.chip_class > GFX9)
352 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
353
354 radv_get_driver_uuid(&device->driver_uuid);
355 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
356
357 if (device->rad_info.family == CHIP_STONEY ||
358 device->rad_info.chip_class >= GFX9) {
359 device->has_rbplus = true;
360 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
361 device->rad_info.family == CHIP_VEGA12 ||
362 device->rad_info.family == CHIP_RAVEN ||
363 device->rad_info.family == CHIP_RAVEN2 ||
364 device->rad_info.family == CHIP_RENOIR;
365 }
366
367 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
368
369 /* Vega10/Raven need a special workaround for a hardware bug. */
370 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
371 device->rad_info.family == CHIP_RAVEN;
372
373 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
374
375 /* Out-of-order primitive rasterization. */
376 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
377 device->rad_info.max_se >= 2;
378 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
379 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
380
381 device->dcc_msaa_allowed =
382 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
383
384 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
385 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
386 (device->rad_info.chip_class >= GFX8 &&
387 device->rad_info.me_fw_feature >= 41);
388
389 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
390 device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
391
392 /* Determine the number of threads per wave for all stages. */
393 device->cs_wave_size = 64;
394 device->ps_wave_size = 64;
395 device->ge_wave_size = 64;
396
397 if (device->rad_info.chip_class >= GFX10) {
398 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
399 device->cs_wave_size = 32;
400
401 /* For pixel shaders, wave64 is recommanded. */
402 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
403 device->ps_wave_size = 32;
404
405 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
406 device->ge_wave_size = 32;
407 }
408
409 radv_physical_device_init_mem_types(device);
410 radv_fill_device_extension_table(device, &device->supported_extensions);
411
412 device->bus_info = *drm_device->businfo.pci;
413
414 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
415 ac_print_gpu_info(&device->rad_info);
416
417 /* The WSI is structured as a layer on top of the driver, so this has
418 * to be the last part of initialization (at least until we get other
419 * semi-layers).
420 */
421 result = radv_init_wsi(device);
422 if (result != VK_SUCCESS) {
423 device->ws->destroy(device->ws);
424 vk_error(instance, result);
425 goto fail;
426 }
427
428 return VK_SUCCESS;
429
430 fail:
431 close(fd);
432 if (master_fd != -1)
433 close(master_fd);
434 return result;
435 }
436
437 static void
438 radv_physical_device_finish(struct radv_physical_device *device)
439 {
440 radv_finish_wsi(device);
441 device->ws->destroy(device->ws);
442 disk_cache_destroy(device->disk_cache);
443 close(device->local_fd);
444 if (device->master_fd != -1)
445 close(device->master_fd);
446 }
447
448 static void *
449 default_alloc_func(void *pUserData, size_t size, size_t align,
450 VkSystemAllocationScope allocationScope)
451 {
452 return malloc(size);
453 }
454
455 static void *
456 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
457 size_t align, VkSystemAllocationScope allocationScope)
458 {
459 return realloc(pOriginal, size);
460 }
461
462 static void
463 default_free_func(void *pUserData, void *pMemory)
464 {
465 free(pMemory);
466 }
467
468 static const VkAllocationCallbacks default_alloc = {
469 .pUserData = NULL,
470 .pfnAllocation = default_alloc_func,
471 .pfnReallocation = default_realloc_func,
472 .pfnFree = default_free_func,
473 };
474
475 static const struct debug_control radv_debug_options[] = {
476 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
477 {"nodcc", RADV_DEBUG_NO_DCC},
478 {"shaders", RADV_DEBUG_DUMP_SHADERS},
479 {"nocache", RADV_DEBUG_NO_CACHE},
480 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
481 {"nohiz", RADV_DEBUG_NO_HIZ},
482 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
483 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
484 {"allbos", RADV_DEBUG_ALL_BOS},
485 {"noibs", RADV_DEBUG_NO_IBS},
486 {"spirv", RADV_DEBUG_DUMP_SPIRV},
487 {"vmfaults", RADV_DEBUG_VM_FAULTS},
488 {"zerovram", RADV_DEBUG_ZERO_VRAM},
489 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
490 {"nosisched", RADV_DEBUG_NO_SISCHED},
491 {"preoptir", RADV_DEBUG_PREOPTIR},
492 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
493 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
494 {"info", RADV_DEBUG_INFO},
495 {"errors", RADV_DEBUG_ERRORS},
496 {"startup", RADV_DEBUG_STARTUP},
497 {"checkir", RADV_DEBUG_CHECKIR},
498 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
499 {"nobinning", RADV_DEBUG_NOBINNING},
500 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
501 {"nongg", RADV_DEBUG_NO_NGG},
502 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
503 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
504 {NULL, 0}
505 };
506
507 const char *
508 radv_get_debug_option_name(int id)
509 {
510 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
511 return radv_debug_options[id].string;
512 }
513
514 static const struct debug_control radv_perftest_options[] = {
515 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
516 {"sisched", RADV_PERFTEST_SISCHED},
517 {"localbos", RADV_PERFTEST_LOCAL_BOS},
518 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
519 {"bolist", RADV_PERFTEST_BO_LIST},
520 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
521 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
522 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
523 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
524 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
525 {NULL, 0}
526 };
527
528 const char *
529 radv_get_perftest_option_name(int id)
530 {
531 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
532 return radv_perftest_options[id].string;
533 }
534
535 static void
536 radv_handle_per_app_options(struct radv_instance *instance,
537 const VkApplicationInfo *info)
538 {
539 const char *name = info ? info->pApplicationName : NULL;
540
541 if (!name)
542 return;
543
544 if (!strcmp(name, "Talos - Linux - 32bit") ||
545 !strcmp(name, "Talos - Linux - 64bit")) {
546 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
547 /* Force enable LLVM sisched for Talos because it looks
548 * safe and it gives few more FPS.
549 */
550 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
551 }
552 } else if (!strcmp(name, "DOOM_VFR")) {
553 /* Work around a Doom VFR game bug */
554 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
555 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
556 /* Workaround for a WaW hazard when LLVM moves/merges
557 * load/store memory operations.
558 * See https://reviews.llvm.org/D61313
559 */
560 if (HAVE_LLVM < 0x900)
561 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
562 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
563 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
564 /* Force enable VK_AMD_shader_ballot because it looks
565 * safe and it gives a nice boost (+20% on Vega 56 at
566 * this time).
567 */
568 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
569 }
570 }
571 }
572
573 static int radv_get_instance_extension_index(const char *name)
574 {
575 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
576 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
577 return i;
578 }
579 return -1;
580 }
581
582 static const char radv_dri_options_xml[] =
583 DRI_CONF_BEGIN
584 DRI_CONF_SECTION_QUALITY
585 DRI_CONF_ADAPTIVE_SYNC("true")
586 DRI_CONF_SECTION_END
587 DRI_CONF_END;
588
589 static void radv_init_dri_options(struct radv_instance *instance)
590 {
591 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
592 driParseConfigFiles(&instance->dri_options,
593 &instance->available_dri_options,
594 0, "radv", NULL);
595 }
596
597 VkResult radv_CreateInstance(
598 const VkInstanceCreateInfo* pCreateInfo,
599 const VkAllocationCallbacks* pAllocator,
600 VkInstance* pInstance)
601 {
602 struct radv_instance *instance;
603 VkResult result;
604
605 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
606
607 uint32_t client_version;
608 if (pCreateInfo->pApplicationInfo &&
609 pCreateInfo->pApplicationInfo->apiVersion != 0) {
610 client_version = pCreateInfo->pApplicationInfo->apiVersion;
611 } else {
612 client_version = VK_API_VERSION_1_0;
613 }
614
615 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
616 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
617 if (!instance)
618 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
619
620 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
621
622 if (pAllocator)
623 instance->alloc = *pAllocator;
624 else
625 instance->alloc = default_alloc;
626
627 instance->apiVersion = client_version;
628 instance->physicalDeviceCount = -1;
629
630 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
631 radv_debug_options);
632
633 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
634 radv_perftest_options);
635
636
637 if (instance->debug_flags & RADV_DEBUG_STARTUP)
638 radv_logi("Created an instance");
639
640 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
641 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
642 int index = radv_get_instance_extension_index(ext_name);
643
644 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
645 vk_free2(&default_alloc, pAllocator, instance);
646 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
647 }
648
649 instance->enabled_extensions.extensions[index] = true;
650 }
651
652 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
653 if (result != VK_SUCCESS) {
654 vk_free2(&default_alloc, pAllocator, instance);
655 return vk_error(instance, result);
656 }
657
658 _mesa_locale_init();
659 glsl_type_singleton_init_or_ref();
660
661 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
662
663 radv_init_dri_options(instance);
664 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
665
666 *pInstance = radv_instance_to_handle(instance);
667
668 return VK_SUCCESS;
669 }
670
671 void radv_DestroyInstance(
672 VkInstance _instance,
673 const VkAllocationCallbacks* pAllocator)
674 {
675 RADV_FROM_HANDLE(radv_instance, instance, _instance);
676
677 if (!instance)
678 return;
679
680 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
681 radv_physical_device_finish(instance->physicalDevices + i);
682 }
683
684 VG(VALGRIND_DESTROY_MEMPOOL(instance));
685
686 glsl_type_singleton_decref();
687 _mesa_locale_fini();
688
689 driDestroyOptionCache(&instance->dri_options);
690 driDestroyOptionInfo(&instance->available_dri_options);
691
692 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
693
694 vk_free(&instance->alloc, instance);
695 }
696
697 static VkResult
698 radv_enumerate_devices(struct radv_instance *instance)
699 {
700 /* TODO: Check for more devices ? */
701 drmDevicePtr devices[8];
702 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
703 int max_devices;
704
705 instance->physicalDeviceCount = 0;
706
707 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
708
709 if (instance->debug_flags & RADV_DEBUG_STARTUP)
710 radv_logi("Found %d drm nodes", max_devices);
711
712 if (max_devices < 1)
713 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
714
715 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
716 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
717 devices[i]->bustype == DRM_BUS_PCI &&
718 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
719
720 result = radv_physical_device_init(instance->physicalDevices +
721 instance->physicalDeviceCount,
722 instance,
723 devices[i]);
724 if (result == VK_SUCCESS)
725 ++instance->physicalDeviceCount;
726 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
727 break;
728 }
729 }
730 drmFreeDevices(devices, max_devices);
731
732 return result;
733 }
734
735 VkResult radv_EnumeratePhysicalDevices(
736 VkInstance _instance,
737 uint32_t* pPhysicalDeviceCount,
738 VkPhysicalDevice* pPhysicalDevices)
739 {
740 RADV_FROM_HANDLE(radv_instance, instance, _instance);
741 VkResult result;
742
743 if (instance->physicalDeviceCount < 0) {
744 result = radv_enumerate_devices(instance);
745 if (result != VK_SUCCESS &&
746 result != VK_ERROR_INCOMPATIBLE_DRIVER)
747 return result;
748 }
749
750 if (!pPhysicalDevices) {
751 *pPhysicalDeviceCount = instance->physicalDeviceCount;
752 } else {
753 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
754 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
755 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
756 }
757
758 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
759 : VK_SUCCESS;
760 }
761
762 VkResult radv_EnumeratePhysicalDeviceGroups(
763 VkInstance _instance,
764 uint32_t* pPhysicalDeviceGroupCount,
765 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
766 {
767 RADV_FROM_HANDLE(radv_instance, instance, _instance);
768 VkResult result;
769
770 if (instance->physicalDeviceCount < 0) {
771 result = radv_enumerate_devices(instance);
772 if (result != VK_SUCCESS &&
773 result != VK_ERROR_INCOMPATIBLE_DRIVER)
774 return result;
775 }
776
777 if (!pPhysicalDeviceGroupProperties) {
778 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
779 } else {
780 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
781 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
782 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
783 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
784 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
785 }
786 }
787 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
788 : VK_SUCCESS;
789 }
790
791 void radv_GetPhysicalDeviceFeatures(
792 VkPhysicalDevice physicalDevice,
793 VkPhysicalDeviceFeatures* pFeatures)
794 {
795 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
796 memset(pFeatures, 0, sizeof(*pFeatures));
797
798 *pFeatures = (VkPhysicalDeviceFeatures) {
799 .robustBufferAccess = true,
800 .fullDrawIndexUint32 = true,
801 .imageCubeArray = true,
802 .independentBlend = true,
803 .geometryShader = true,
804 .tessellationShader = true,
805 .sampleRateShading = true,
806 .dualSrcBlend = true,
807 .logicOp = true,
808 .multiDrawIndirect = true,
809 .drawIndirectFirstInstance = true,
810 .depthClamp = true,
811 .depthBiasClamp = true,
812 .fillModeNonSolid = true,
813 .depthBounds = true,
814 .wideLines = true,
815 .largePoints = true,
816 .alphaToOne = true,
817 .multiViewport = true,
818 .samplerAnisotropy = true,
819 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
820 .textureCompressionASTC_LDR = false,
821 .textureCompressionBC = true,
822 .occlusionQueryPrecise = true,
823 .pipelineStatisticsQuery = true,
824 .vertexPipelineStoresAndAtomics = true,
825 .fragmentStoresAndAtomics = true,
826 .shaderTessellationAndGeometryPointSize = true,
827 .shaderImageGatherExtended = true,
828 .shaderStorageImageExtendedFormats = true,
829 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
830 .shaderUniformBufferArrayDynamicIndexing = true,
831 .shaderSampledImageArrayDynamicIndexing = true,
832 .shaderStorageBufferArrayDynamicIndexing = true,
833 .shaderStorageImageArrayDynamicIndexing = true,
834 .shaderStorageImageReadWithoutFormat = true,
835 .shaderStorageImageWriteWithoutFormat = true,
836 .shaderClipDistance = true,
837 .shaderCullDistance = true,
838 .shaderFloat64 = true,
839 .shaderInt64 = true,
840 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
841 .sparseBinding = true,
842 .variableMultisampleRate = true,
843 .inheritedQueries = true,
844 };
845 }
846
847 void radv_GetPhysicalDeviceFeatures2(
848 VkPhysicalDevice physicalDevice,
849 VkPhysicalDeviceFeatures2 *pFeatures)
850 {
851 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
852 vk_foreach_struct(ext, pFeatures->pNext) {
853 switch (ext->sType) {
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
855 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
856 features->variablePointersStorageBuffer = true;
857 features->variablePointers = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
861 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
862 features->multiview = true;
863 features->multiviewGeometryShader = true;
864 features->multiviewTessellationShader = true;
865 break;
866 }
867 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
868 VkPhysicalDeviceShaderDrawParametersFeatures *features =
869 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
870 features->shaderDrawParameters = true;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
874 VkPhysicalDeviceProtectedMemoryFeatures *features =
875 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
876 features->protectedMemory = false;
877 break;
878 }
879 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
880 VkPhysicalDevice16BitStorageFeatures *features =
881 (VkPhysicalDevice16BitStorageFeatures*)ext;
882 bool enabled = pdevice->rad_info.chip_class >= GFX8;
883 features->storageBuffer16BitAccess = enabled;
884 features->uniformAndStorageBuffer16BitAccess = enabled;
885 features->storagePushConstant16 = enabled;
886 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
887 break;
888 }
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
890 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
891 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
892 features->samplerYcbcrConversion = true;
893 break;
894 }
895 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
896 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
897 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
898 features->shaderInputAttachmentArrayDynamicIndexing = true;
899 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
900 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
901 features->shaderUniformBufferArrayNonUniformIndexing = true;
902 features->shaderSampledImageArrayNonUniformIndexing = true;
903 features->shaderStorageBufferArrayNonUniformIndexing = true;
904 features->shaderStorageImageArrayNonUniformIndexing = true;
905 features->shaderInputAttachmentArrayNonUniformIndexing = true;
906 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
907 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
908 features->descriptorBindingUniformBufferUpdateAfterBind = true;
909 features->descriptorBindingSampledImageUpdateAfterBind = true;
910 features->descriptorBindingStorageImageUpdateAfterBind = true;
911 features->descriptorBindingStorageBufferUpdateAfterBind = true;
912 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
913 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
914 features->descriptorBindingUpdateUnusedWhilePending = true;
915 features->descriptorBindingPartiallyBound = true;
916 features->descriptorBindingVariableDescriptorCount = true;
917 features->runtimeDescriptorArray = true;
918 break;
919 }
920 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
921 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
922 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
923 features->conditionalRendering = true;
924 features->inheritedConditionalRendering = false;
925 break;
926 }
927 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
928 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
929 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
930 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
931 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
932 break;
933 }
934 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
935 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
936 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
937 features->transformFeedback = true;
938 features->geometryStreams = true;
939 break;
940 }
941 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
942 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
943 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
944 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
945 break;
946 }
947 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
948 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
949 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
950 features->memoryPriority = VK_TRUE;
951 break;
952 }
953 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
954 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
955 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
956 features->bufferDeviceAddress = true;
957 features->bufferDeviceAddressCaptureReplay = false;
958 features->bufferDeviceAddressMultiDevice = false;
959 break;
960 }
961 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
962 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
963 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
964 features->depthClipEnable = true;
965 break;
966 }
967 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
968 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
969 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
970 features->hostQueryReset = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
974 VkPhysicalDevice8BitStorageFeaturesKHR *features =
975 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
976 bool enabled = pdevice->rad_info.chip_class >= GFX8;
977 features->storageBuffer8BitAccess = enabled;
978 features->uniformAndStorageBuffer8BitAccess = enabled;
979 features->storagePushConstant8 = enabled;
980 break;
981 }
982 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
983 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
984 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
985 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8;
986 features->shaderInt8 = true;
987 break;
988 }
989 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
990 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
991 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
992 features->shaderBufferInt64Atomics = HAVE_LLVM >= 0x0900;
993 features->shaderSharedInt64Atomics = HAVE_LLVM >= 0x0900;
994 break;
995 }
996 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
997 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
998 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
999
1000 features->inlineUniformBlock = true;
1001 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1005 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1006 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1007 features->computeDerivativeGroupQuads = false;
1008 features->computeDerivativeGroupLinear = true;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1012 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1013 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1014 features->ycbcrImageArrays = true;
1015 break;
1016 }
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1018 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1019 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1020 features->uniformBufferStandardLayout = true;
1021 break;
1022 }
1023 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1024 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1025 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1026 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1027 break;
1028 }
1029 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1030 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1031 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1032 features->imagelessFramebuffer = true;
1033 break;
1034 }
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1036 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1037 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1038 features->pipelineExecutableInfo = true;
1039 break;
1040 }
1041 default:
1042 break;
1043 }
1044 }
1045 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1046 }
1047
1048 void radv_GetPhysicalDeviceProperties(
1049 VkPhysicalDevice physicalDevice,
1050 VkPhysicalDeviceProperties* pProperties)
1051 {
1052 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1053 VkSampleCountFlags sample_counts = 0xf;
1054
1055 /* make sure that the entire descriptor set is addressable with a signed
1056 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1057 * be at most 2 GiB. the combined image & samples object count as one of
1058 * both. This limit is for the pipeline layout, not for the set layout, but
1059 * there is no set limit, so we just set a pipeline limit. I don't think
1060 * any app is going to hit this soon. */
1061 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1062 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1063 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1064 32 /* sampler, largest when combined with image */ +
1065 64 /* sampled image */ +
1066 64 /* storage image */);
1067
1068 VkPhysicalDeviceLimits limits = {
1069 .maxImageDimension1D = (1 << 14),
1070 .maxImageDimension2D = (1 << 14),
1071 .maxImageDimension3D = (1 << 11),
1072 .maxImageDimensionCube = (1 << 14),
1073 .maxImageArrayLayers = (1 << 11),
1074 .maxTexelBufferElements = 128 * 1024 * 1024,
1075 .maxUniformBufferRange = UINT32_MAX,
1076 .maxStorageBufferRange = UINT32_MAX,
1077 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1078 .maxMemoryAllocationCount = UINT32_MAX,
1079 .maxSamplerAllocationCount = 64 * 1024,
1080 .bufferImageGranularity = 64, /* A cache line */
1081 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1082 .maxBoundDescriptorSets = MAX_SETS,
1083 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1084 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1085 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1086 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1087 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1088 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1089 .maxPerStageResources = max_descriptor_set_size,
1090 .maxDescriptorSetSamplers = max_descriptor_set_size,
1091 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1092 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1093 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1094 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1095 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1096 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1097 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1098 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1099 .maxVertexInputBindings = MAX_VBS,
1100 .maxVertexInputAttributeOffset = 2047,
1101 .maxVertexInputBindingStride = 2048,
1102 .maxVertexOutputComponents = 128,
1103 .maxTessellationGenerationLevel = 64,
1104 .maxTessellationPatchSize = 32,
1105 .maxTessellationControlPerVertexInputComponents = 128,
1106 .maxTessellationControlPerVertexOutputComponents = 128,
1107 .maxTessellationControlPerPatchOutputComponents = 120,
1108 .maxTessellationControlTotalOutputComponents = 4096,
1109 .maxTessellationEvaluationInputComponents = 128,
1110 .maxTessellationEvaluationOutputComponents = 128,
1111 .maxGeometryShaderInvocations = 127,
1112 .maxGeometryInputComponents = 64,
1113 .maxGeometryOutputComponents = 128,
1114 .maxGeometryOutputVertices = 256,
1115 .maxGeometryTotalOutputComponents = 1024,
1116 .maxFragmentInputComponents = 128,
1117 .maxFragmentOutputAttachments = 8,
1118 .maxFragmentDualSrcAttachments = 1,
1119 .maxFragmentCombinedOutputResources = 8,
1120 .maxComputeSharedMemorySize = 32768,
1121 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1122 .maxComputeWorkGroupInvocations = 2048,
1123 .maxComputeWorkGroupSize = {
1124 2048,
1125 2048,
1126 2048
1127 },
1128 .subPixelPrecisionBits = 8,
1129 .subTexelPrecisionBits = 8,
1130 .mipmapPrecisionBits = 8,
1131 .maxDrawIndexedIndexValue = UINT32_MAX,
1132 .maxDrawIndirectCount = UINT32_MAX,
1133 .maxSamplerLodBias = 16,
1134 .maxSamplerAnisotropy = 16,
1135 .maxViewports = MAX_VIEWPORTS,
1136 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1137 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1138 .viewportSubPixelBits = 8,
1139 .minMemoryMapAlignment = 4096, /* A page */
1140 .minTexelBufferOffsetAlignment = 1,
1141 .minUniformBufferOffsetAlignment = 4,
1142 .minStorageBufferOffsetAlignment = 4,
1143 .minTexelOffset = -32,
1144 .maxTexelOffset = 31,
1145 .minTexelGatherOffset = -32,
1146 .maxTexelGatherOffset = 31,
1147 .minInterpolationOffset = -2,
1148 .maxInterpolationOffset = 2,
1149 .subPixelInterpolationOffsetBits = 8,
1150 .maxFramebufferWidth = (1 << 14),
1151 .maxFramebufferHeight = (1 << 14),
1152 .maxFramebufferLayers = (1 << 10),
1153 .framebufferColorSampleCounts = sample_counts,
1154 .framebufferDepthSampleCounts = sample_counts,
1155 .framebufferStencilSampleCounts = sample_counts,
1156 .framebufferNoAttachmentsSampleCounts = sample_counts,
1157 .maxColorAttachments = MAX_RTS,
1158 .sampledImageColorSampleCounts = sample_counts,
1159 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1160 .sampledImageDepthSampleCounts = sample_counts,
1161 .sampledImageStencilSampleCounts = sample_counts,
1162 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1163 .maxSampleMaskWords = 1,
1164 .timestampComputeAndGraphics = true,
1165 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1166 .maxClipDistances = 8,
1167 .maxCullDistances = 8,
1168 .maxCombinedClipAndCullDistances = 8,
1169 .discreteQueuePriorities = 2,
1170 .pointSizeRange = { 0.0, 8192.0 },
1171 .lineWidthRange = { 0.0, 7.9921875 },
1172 .pointSizeGranularity = (1.0 / 8.0),
1173 .lineWidthGranularity = (1.0 / 128.0),
1174 .strictLines = false, /* FINISHME */
1175 .standardSampleLocations = true,
1176 .optimalBufferCopyOffsetAlignment = 128,
1177 .optimalBufferCopyRowPitchAlignment = 128,
1178 .nonCoherentAtomSize = 64,
1179 };
1180
1181 *pProperties = (VkPhysicalDeviceProperties) {
1182 .apiVersion = radv_physical_device_api_version(pdevice),
1183 .driverVersion = vk_get_driver_version(),
1184 .vendorID = ATI_VENDOR_ID,
1185 .deviceID = pdevice->rad_info.pci_id,
1186 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1187 .limits = limits,
1188 .sparseProperties = {0},
1189 };
1190
1191 strcpy(pProperties->deviceName, pdevice->name);
1192 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1193 }
1194
1195 void radv_GetPhysicalDeviceProperties2(
1196 VkPhysicalDevice physicalDevice,
1197 VkPhysicalDeviceProperties2 *pProperties)
1198 {
1199 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1200 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1201
1202 vk_foreach_struct(ext, pProperties->pNext) {
1203 switch (ext->sType) {
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1205 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1206 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1207 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1211 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1212 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1213 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1214 properties->deviceLUIDValid = false;
1215 break;
1216 }
1217 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1218 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1219 properties->maxMultiviewViewCount = MAX_VIEWS;
1220 properties->maxMultiviewInstanceIndex = INT_MAX;
1221 break;
1222 }
1223 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1224 VkPhysicalDevicePointClippingProperties *properties =
1225 (VkPhysicalDevicePointClippingProperties*)ext;
1226 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1227 break;
1228 }
1229 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1230 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1231 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1232 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1236 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1237 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1238 properties->minImportedHostPointerAlignment = 4096;
1239 break;
1240 }
1241 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1242 VkPhysicalDeviceSubgroupProperties *properties =
1243 (VkPhysicalDeviceSubgroupProperties*)ext;
1244 properties->subgroupSize = 64;
1245 properties->supportedStages = VK_SHADER_STAGE_ALL;
1246 properties->supportedOperations =
1247 VK_SUBGROUP_FEATURE_BASIC_BIT |
1248 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1249 VK_SUBGROUP_FEATURE_QUAD_BIT |
1250 VK_SUBGROUP_FEATURE_VOTE_BIT;
1251 if (pdevice->rad_info.chip_class >= GFX8) {
1252 properties->supportedOperations |=
1253 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1254 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1255 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1256 }
1257 properties->quadOperationsInAllStages = true;
1258 break;
1259 }
1260 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1261 VkPhysicalDeviceMaintenance3Properties *properties =
1262 (VkPhysicalDeviceMaintenance3Properties*)ext;
1263 /* Make sure everything is addressable by a signed 32-bit int, and
1264 * our largest descriptors are 96 bytes. */
1265 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1266 /* Our buffer size fields allow only this much */
1267 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1268 break;
1269 }
1270 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1271 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1272 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1273 /* GFX6-8 only support single channel min/max filter. */
1274 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1275 properties->filterMinmaxSingleComponentFormats = true;
1276 break;
1277 }
1278 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1279 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1280 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1281
1282 /* Shader engines. */
1283 properties->shaderEngineCount =
1284 pdevice->rad_info.max_se;
1285 properties->shaderArraysPerEngineCount =
1286 pdevice->rad_info.max_sh_per_se;
1287 properties->computeUnitsPerShaderArray =
1288 pdevice->rad_info.num_good_cu_per_sh;
1289 properties->simdPerComputeUnit = 4;
1290 properties->wavefrontsPerSimd =
1291 pdevice->rad_info.family == CHIP_TONGA ||
1292 pdevice->rad_info.family == CHIP_ICELAND ||
1293 pdevice->rad_info.family == CHIP_POLARIS10 ||
1294 pdevice->rad_info.family == CHIP_POLARIS11 ||
1295 pdevice->rad_info.family == CHIP_POLARIS12 ||
1296 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1297 properties->wavefrontSize = 64;
1298
1299 /* SGPR. */
1300 properties->sgprsPerSimd =
1301 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1302 properties->minSgprAllocation =
1303 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1304 properties->maxSgprAllocation =
1305 pdevice->rad_info.family == CHIP_TONGA ||
1306 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1307 properties->sgprAllocationGranularity =
1308 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1309
1310 /* VGPR. */
1311 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1312 properties->minVgprAllocation = 4;
1313 properties->maxVgprAllocation = 256;
1314 properties->vgprAllocationGranularity = 4;
1315 break;
1316 }
1317 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1318 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1319 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1320
1321 properties->shaderCoreFeatures = 0;
1322 properties->activeComputeUnitCount =
1323 pdevice->rad_info.num_good_compute_units;
1324 break;
1325 }
1326 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1327 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1328 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1329 properties->maxVertexAttribDivisor = UINT32_MAX;
1330 break;
1331 }
1332 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1333 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1334 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1335 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1336 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1337 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1338 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1339 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1340 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1341 properties->robustBufferAccessUpdateAfterBind = false;
1342 properties->quadDivergentImplicitLod = false;
1343
1344 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1345 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1346 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1347 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1348 32 /* sampler, largest when combined with image */ +
1349 64 /* sampled image */ +
1350 64 /* storage image */);
1351 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1352 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1353 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1354 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1355 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1356 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1357 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1358 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1359 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1360 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1361 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1362 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1363 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1364 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1365 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1366 break;
1367 }
1368 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1369 VkPhysicalDeviceProtectedMemoryProperties *properties =
1370 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1371 properties->protectedNoFault = false;
1372 break;
1373 }
1374 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1375 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1376 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1377 properties->primitiveOverestimationSize = 0;
1378 properties->maxExtraPrimitiveOverestimationSize = 0;
1379 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1380 properties->primitiveUnderestimation = VK_FALSE;
1381 properties->conservativePointAndLineRasterization = VK_FALSE;
1382 properties->degenerateTrianglesRasterized = VK_FALSE;
1383 properties->degenerateLinesRasterized = VK_FALSE;
1384 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1385 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1386 break;
1387 }
1388 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1389 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1390 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1391 properties->pciDomain = pdevice->bus_info.domain;
1392 properties->pciBus = pdevice->bus_info.bus;
1393 properties->pciDevice = pdevice->bus_info.dev;
1394 properties->pciFunction = pdevice->bus_info.func;
1395 break;
1396 }
1397 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1398 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1399 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1400
1401 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1402 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1403 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1404 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1405 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1406
1407 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1408 .major = 1,
1409 .minor = 1,
1410 .subminor = 2,
1411 .patch = 0,
1412 };
1413 break;
1414 }
1415 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1416 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1417 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1418 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1419 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1420 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1421 properties->maxTransformFeedbackStreamDataSize = 512;
1422 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1423 properties->maxTransformFeedbackBufferDataStride = 512;
1424 properties->transformFeedbackQueries = true;
1425 properties->transformFeedbackStreamsLinesTriangles = true;
1426 properties->transformFeedbackRasterizationStreamSelect = false;
1427 properties->transformFeedbackDraw = true;
1428 break;
1429 }
1430 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1431 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1432 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1433
1434 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1435 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1436 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1437 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1438 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1439 break;
1440 }
1441 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1442 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1443 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1444 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1445 VK_SAMPLE_COUNT_4_BIT |
1446 VK_SAMPLE_COUNT_8_BIT;
1447 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1448 properties->sampleLocationCoordinateRange[0] = 0.0f;
1449 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1450 properties->sampleLocationSubPixelBits = 4;
1451 properties->variableSampleLocations = VK_FALSE;
1452 break;
1453 }
1454 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1455 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1456 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1457
1458 /* We support all of the depth resolve modes */
1459 properties->supportedDepthResolveModes =
1460 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1461 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1462 VK_RESOLVE_MODE_MIN_BIT_KHR |
1463 VK_RESOLVE_MODE_MAX_BIT_KHR;
1464
1465 /* Average doesn't make sense for stencil so we don't support that */
1466 properties->supportedStencilResolveModes =
1467 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1468 VK_RESOLVE_MODE_MIN_BIT_KHR |
1469 VK_RESOLVE_MODE_MAX_BIT_KHR;
1470
1471 properties->independentResolveNone = VK_TRUE;
1472 properties->independentResolve = VK_TRUE;
1473 break;
1474 }
1475 default:
1476 break;
1477 }
1478 }
1479 }
1480
1481 static void radv_get_physical_device_queue_family_properties(
1482 struct radv_physical_device* pdevice,
1483 uint32_t* pCount,
1484 VkQueueFamilyProperties** pQueueFamilyProperties)
1485 {
1486 int num_queue_families = 1;
1487 int idx;
1488 if (pdevice->rad_info.num_compute_rings > 0 &&
1489 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1490 num_queue_families++;
1491
1492 if (pQueueFamilyProperties == NULL) {
1493 *pCount = num_queue_families;
1494 return;
1495 }
1496
1497 if (!*pCount)
1498 return;
1499
1500 idx = 0;
1501 if (*pCount >= 1) {
1502 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1503 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1504 VK_QUEUE_COMPUTE_BIT |
1505 VK_QUEUE_TRANSFER_BIT |
1506 VK_QUEUE_SPARSE_BINDING_BIT,
1507 .queueCount = 1,
1508 .timestampValidBits = 64,
1509 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1510 };
1511 idx++;
1512 }
1513
1514 if (pdevice->rad_info.num_compute_rings > 0 &&
1515 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1516 if (*pCount > idx) {
1517 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1518 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1519 VK_QUEUE_TRANSFER_BIT |
1520 VK_QUEUE_SPARSE_BINDING_BIT,
1521 .queueCount = pdevice->rad_info.num_compute_rings,
1522 .timestampValidBits = 64,
1523 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1524 };
1525 idx++;
1526 }
1527 }
1528 *pCount = idx;
1529 }
1530
1531 void radv_GetPhysicalDeviceQueueFamilyProperties(
1532 VkPhysicalDevice physicalDevice,
1533 uint32_t* pCount,
1534 VkQueueFamilyProperties* pQueueFamilyProperties)
1535 {
1536 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1537 if (!pQueueFamilyProperties) {
1538 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1539 return;
1540 }
1541 VkQueueFamilyProperties *properties[] = {
1542 pQueueFamilyProperties + 0,
1543 pQueueFamilyProperties + 1,
1544 pQueueFamilyProperties + 2,
1545 };
1546 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1547 assert(*pCount <= 3);
1548 }
1549
1550 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1551 VkPhysicalDevice physicalDevice,
1552 uint32_t* pCount,
1553 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1554 {
1555 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1556 if (!pQueueFamilyProperties) {
1557 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1558 return;
1559 }
1560 VkQueueFamilyProperties *properties[] = {
1561 &pQueueFamilyProperties[0].queueFamilyProperties,
1562 &pQueueFamilyProperties[1].queueFamilyProperties,
1563 &pQueueFamilyProperties[2].queueFamilyProperties,
1564 };
1565 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1566 assert(*pCount <= 3);
1567 }
1568
1569 void radv_GetPhysicalDeviceMemoryProperties(
1570 VkPhysicalDevice physicalDevice,
1571 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1572 {
1573 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1574
1575 *pMemoryProperties = physical_device->memory_properties;
1576 }
1577
1578 static void
1579 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1580 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1581 {
1582 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1583 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1584 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1585 uint64_t vram_size = radv_get_vram_size(device);
1586 uint64_t gtt_size = device->rad_info.gart_size;
1587 uint64_t heap_budget, heap_usage;
1588
1589 /* For all memory heaps, the computation of budget is as follow:
1590 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1591 *
1592 * The Vulkan spec 1.1.97 says that the budget should include any
1593 * currently allocated device memory.
1594 *
1595 * Note that the application heap usages are not really accurate (eg.
1596 * in presence of shared buffers).
1597 */
1598 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1599 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1600
1601 switch (device->mem_type_indices[i]) {
1602 case RADV_MEM_TYPE_VRAM:
1603 heap_usage = device->ws->query_value(device->ws,
1604 RADEON_ALLOCATED_VRAM);
1605
1606 heap_budget = vram_size -
1607 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1608 heap_usage;
1609
1610 memoryBudget->heapBudget[heap_index] = heap_budget;
1611 memoryBudget->heapUsage[heap_index] = heap_usage;
1612 break;
1613 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1614 heap_usage = device->ws->query_value(device->ws,
1615 RADEON_ALLOCATED_VRAM_VIS);
1616
1617 heap_budget = visible_vram_size -
1618 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1619 heap_usage;
1620
1621 memoryBudget->heapBudget[heap_index] = heap_budget;
1622 memoryBudget->heapUsage[heap_index] = heap_usage;
1623 break;
1624 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1625 heap_usage = device->ws->query_value(device->ws,
1626 RADEON_ALLOCATED_GTT);
1627
1628 heap_budget = gtt_size -
1629 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1630 heap_usage;
1631
1632 memoryBudget->heapBudget[heap_index] = heap_budget;
1633 memoryBudget->heapUsage[heap_index] = heap_usage;
1634 break;
1635 default:
1636 break;
1637 }
1638 }
1639
1640 /* The heapBudget and heapUsage values must be zero for array elements
1641 * greater than or equal to
1642 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1643 */
1644 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1645 memoryBudget->heapBudget[i] = 0;
1646 memoryBudget->heapUsage[i] = 0;
1647 }
1648 }
1649
1650 void radv_GetPhysicalDeviceMemoryProperties2(
1651 VkPhysicalDevice physicalDevice,
1652 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1653 {
1654 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1655 &pMemoryProperties->memoryProperties);
1656
1657 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1658 vk_find_struct(pMemoryProperties->pNext,
1659 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1660 if (memory_budget)
1661 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1662 }
1663
1664 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1665 VkDevice _device,
1666 VkExternalMemoryHandleTypeFlagBits handleType,
1667 const void *pHostPointer,
1668 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1669 {
1670 RADV_FROM_HANDLE(radv_device, device, _device);
1671
1672 switch (handleType)
1673 {
1674 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1675 const struct radv_physical_device *physical_device = device->physical_device;
1676 uint32_t memoryTypeBits = 0;
1677 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1678 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1679 memoryTypeBits = (1 << i);
1680 break;
1681 }
1682 }
1683 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1684 return VK_SUCCESS;
1685 }
1686 default:
1687 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1688 }
1689 }
1690
1691 static enum radeon_ctx_priority
1692 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1693 {
1694 /* Default to MEDIUM when a specific global priority isn't requested */
1695 if (!pObj)
1696 return RADEON_CTX_PRIORITY_MEDIUM;
1697
1698 switch(pObj->globalPriority) {
1699 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1700 return RADEON_CTX_PRIORITY_REALTIME;
1701 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1702 return RADEON_CTX_PRIORITY_HIGH;
1703 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1704 return RADEON_CTX_PRIORITY_MEDIUM;
1705 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1706 return RADEON_CTX_PRIORITY_LOW;
1707 default:
1708 unreachable("Illegal global priority value");
1709 return RADEON_CTX_PRIORITY_INVALID;
1710 }
1711 }
1712
1713 static int
1714 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1715 uint32_t queue_family_index, int idx,
1716 VkDeviceQueueCreateFlags flags,
1717 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1718 {
1719 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1720 queue->device = device;
1721 queue->queue_family_index = queue_family_index;
1722 queue->queue_idx = idx;
1723 queue->priority = radv_get_queue_global_priority(global_priority);
1724 queue->flags = flags;
1725
1726 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1727 if (!queue->hw_ctx)
1728 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1729
1730 return VK_SUCCESS;
1731 }
1732
1733 static void
1734 radv_queue_finish(struct radv_queue *queue)
1735 {
1736 if (queue->hw_ctx)
1737 queue->device->ws->ctx_destroy(queue->hw_ctx);
1738
1739 if (queue->initial_full_flush_preamble_cs)
1740 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1741 if (queue->initial_preamble_cs)
1742 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1743 if (queue->continue_preamble_cs)
1744 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1745 if (queue->descriptor_bo)
1746 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1747 if (queue->scratch_bo)
1748 queue->device->ws->buffer_destroy(queue->scratch_bo);
1749 if (queue->esgs_ring_bo)
1750 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1751 if (queue->gsvs_ring_bo)
1752 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1753 if (queue->tess_rings_bo)
1754 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1755 if (queue->compute_scratch_bo)
1756 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1757 }
1758
1759 static void
1760 radv_bo_list_init(struct radv_bo_list *bo_list)
1761 {
1762 pthread_mutex_init(&bo_list->mutex, NULL);
1763 bo_list->list.count = bo_list->capacity = 0;
1764 bo_list->list.bos = NULL;
1765 }
1766
1767 static void
1768 radv_bo_list_finish(struct radv_bo_list *bo_list)
1769 {
1770 free(bo_list->list.bos);
1771 pthread_mutex_destroy(&bo_list->mutex);
1772 }
1773
1774 static VkResult radv_bo_list_add(struct radv_device *device,
1775 struct radeon_winsys_bo *bo)
1776 {
1777 struct radv_bo_list *bo_list = &device->bo_list;
1778
1779 if (bo->is_local)
1780 return VK_SUCCESS;
1781
1782 if (unlikely(!device->use_global_bo_list))
1783 return VK_SUCCESS;
1784
1785 pthread_mutex_lock(&bo_list->mutex);
1786 if (bo_list->list.count == bo_list->capacity) {
1787 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1788 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1789
1790 if (!data) {
1791 pthread_mutex_unlock(&bo_list->mutex);
1792 return VK_ERROR_OUT_OF_HOST_MEMORY;
1793 }
1794
1795 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1796 bo_list->capacity = capacity;
1797 }
1798
1799 bo_list->list.bos[bo_list->list.count++] = bo;
1800 pthread_mutex_unlock(&bo_list->mutex);
1801 return VK_SUCCESS;
1802 }
1803
1804 static void radv_bo_list_remove(struct radv_device *device,
1805 struct radeon_winsys_bo *bo)
1806 {
1807 struct radv_bo_list *bo_list = &device->bo_list;
1808
1809 if (bo->is_local)
1810 return;
1811
1812 if (unlikely(!device->use_global_bo_list))
1813 return;
1814
1815 pthread_mutex_lock(&bo_list->mutex);
1816 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1817 if (bo_list->list.bos[i] == bo) {
1818 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1819 --bo_list->list.count;
1820 break;
1821 }
1822 }
1823 pthread_mutex_unlock(&bo_list->mutex);
1824 }
1825
1826 static void
1827 radv_device_init_gs_info(struct radv_device *device)
1828 {
1829 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1830 device->physical_device->rad_info.family);
1831 }
1832
1833 static int radv_get_device_extension_index(const char *name)
1834 {
1835 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1836 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1837 return i;
1838 }
1839 return -1;
1840 }
1841
1842 static int
1843 radv_get_int_debug_option(const char *name, int default_value)
1844 {
1845 const char *str;
1846 int result;
1847
1848 str = getenv(name);
1849 if (!str) {
1850 result = default_value;
1851 } else {
1852 char *endptr;
1853
1854 result = strtol(str, &endptr, 0);
1855 if (str == endptr) {
1856 /* No digits founs. */
1857 result = default_value;
1858 }
1859 }
1860
1861 return result;
1862 }
1863
1864 VkResult radv_CreateDevice(
1865 VkPhysicalDevice physicalDevice,
1866 const VkDeviceCreateInfo* pCreateInfo,
1867 const VkAllocationCallbacks* pAllocator,
1868 VkDevice* pDevice)
1869 {
1870 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1871 VkResult result;
1872 struct radv_device *device;
1873
1874 bool keep_shader_info = false;
1875
1876 /* Check enabled features */
1877 if (pCreateInfo->pEnabledFeatures) {
1878 VkPhysicalDeviceFeatures supported_features;
1879 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1880 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1881 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1882 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1883 for (uint32_t i = 0; i < num_features; i++) {
1884 if (enabled_feature[i] && !supported_feature[i])
1885 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1886 }
1887 }
1888
1889 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1890 sizeof(*device), 8,
1891 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1892 if (!device)
1893 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1894
1895 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1896 device->instance = physical_device->instance;
1897 device->physical_device = physical_device;
1898
1899 device->ws = physical_device->ws;
1900 if (pAllocator)
1901 device->alloc = *pAllocator;
1902 else
1903 device->alloc = physical_device->instance->alloc;
1904
1905 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1906 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1907 int index = radv_get_device_extension_index(ext_name);
1908 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1909 vk_free(&device->alloc, device);
1910 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1911 }
1912
1913 device->enabled_extensions.extensions[index] = true;
1914 }
1915
1916 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1917
1918 /* With update after bind we can't attach bo's to the command buffer
1919 * from the descriptor set anymore, so we have to use a global BO list.
1920 */
1921 device->use_global_bo_list =
1922 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1923 device->enabled_extensions.EXT_descriptor_indexing ||
1924 device->enabled_extensions.EXT_buffer_device_address;
1925
1926 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1927 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1928
1929 mtx_init(&device->shader_slab_mutex, mtx_plain);
1930 list_inithead(&device->shader_slabs);
1931
1932 radv_bo_list_init(&device->bo_list);
1933
1934 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1935 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1936 uint32_t qfi = queue_create->queueFamilyIndex;
1937 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1938 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1939
1940 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1941
1942 device->queues[qfi] = vk_alloc(&device->alloc,
1943 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1944 if (!device->queues[qfi]) {
1945 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1946 goto fail;
1947 }
1948
1949 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1950
1951 device->queue_count[qfi] = queue_create->queueCount;
1952
1953 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1954 result = radv_queue_init(device, &device->queues[qfi][q],
1955 qfi, q, queue_create->flags,
1956 global_priority);
1957 if (result != VK_SUCCESS)
1958 goto fail;
1959 }
1960 }
1961
1962 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1963 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1964
1965 device->dfsm_allowed = device->pbb_allowed &&
1966 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1967 device->physical_device->rad_info.family == CHIP_RAVEN2 ||
1968 device->physical_device->rad_info.family == CHIP_RENOIR);
1969
1970 #ifdef ANDROID
1971 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1972 #endif
1973
1974 /* The maximum number of scratch waves. Scratch space isn't divided
1975 * evenly between CUs. The number is only a function of the number of CUs.
1976 * We can decrease the constant to decrease the scratch buffer size.
1977 *
1978 * sctx->scratch_waves must be >= the maximum possible size of
1979 * 1 threadgroup, so that the hw doesn't hang from being unable
1980 * to start any.
1981 *
1982 * The recommended value is 4 per CU at most. Higher numbers don't
1983 * bring much benefit, but they still occupy chip resources (think
1984 * async compute). I've seen ~2% performance difference between 4 and 32.
1985 */
1986 uint32_t max_threads_per_block = 2048;
1987 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1988 max_threads_per_block / 64);
1989
1990 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1991 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1992
1993 if (device->physical_device->rad_info.chip_class >= GFX7) {
1994 /* If the KMD allows it (there is a KMD hw register for it),
1995 * allow launching waves out-of-order.
1996 */
1997 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1998 }
1999
2000 radv_device_init_gs_info(device);
2001
2002 device->tess_offchip_block_dw_size =
2003 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2004
2005 if (getenv("RADV_TRACE_FILE")) {
2006 const char *filename = getenv("RADV_TRACE_FILE");
2007
2008 keep_shader_info = true;
2009
2010 if (!radv_init_trace(device))
2011 goto fail;
2012
2013 fprintf(stderr, "*****************************************************************************\n");
2014 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2015 fprintf(stderr, "*****************************************************************************\n");
2016
2017 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2018 radv_dump_enabled_options(device, stderr);
2019 }
2020
2021 device->keep_shader_info = keep_shader_info;
2022
2023 result = radv_device_init_meta(device);
2024 if (result != VK_SUCCESS)
2025 goto fail;
2026
2027 radv_device_init_msaa(device);
2028
2029 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2030 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2031 switch (family) {
2032 case RADV_QUEUE_GENERAL:
2033 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2034 if (device->physical_device->rad_info.drm_minor < 6) {
2035 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2036 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2037 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2038 }
2039 break;
2040 case RADV_QUEUE_COMPUTE:
2041 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2042 radeon_emit(device->empty_cs[family], 0);
2043 break;
2044 }
2045 device->ws->cs_finalize(device->empty_cs[family]);
2046 }
2047
2048 if (device->physical_device->rad_info.chip_class >= GFX7)
2049 cik_create_gfx_config(device);
2050
2051 VkPipelineCacheCreateInfo ci;
2052 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2053 ci.pNext = NULL;
2054 ci.flags = 0;
2055 ci.pInitialData = NULL;
2056 ci.initialDataSize = 0;
2057 VkPipelineCache pc;
2058 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2059 &ci, NULL, &pc);
2060 if (result != VK_SUCCESS)
2061 goto fail_meta;
2062
2063 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2064
2065 device->force_aniso =
2066 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2067 if (device->force_aniso >= 0) {
2068 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2069 1 << util_logbase2(device->force_aniso));
2070 }
2071
2072 *pDevice = radv_device_to_handle(device);
2073 return VK_SUCCESS;
2074
2075 fail_meta:
2076 radv_device_finish_meta(device);
2077 fail:
2078 radv_bo_list_finish(&device->bo_list);
2079
2080 if (device->trace_bo)
2081 device->ws->buffer_destroy(device->trace_bo);
2082
2083 if (device->gfx_init)
2084 device->ws->buffer_destroy(device->gfx_init);
2085
2086 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2087 for (unsigned q = 0; q < device->queue_count[i]; q++)
2088 radv_queue_finish(&device->queues[i][q]);
2089 if (device->queue_count[i])
2090 vk_free(&device->alloc, device->queues[i]);
2091 }
2092
2093 vk_free(&device->alloc, device);
2094 return result;
2095 }
2096
2097 void radv_DestroyDevice(
2098 VkDevice _device,
2099 const VkAllocationCallbacks* pAllocator)
2100 {
2101 RADV_FROM_HANDLE(radv_device, device, _device);
2102
2103 if (!device)
2104 return;
2105
2106 if (device->trace_bo)
2107 device->ws->buffer_destroy(device->trace_bo);
2108
2109 if (device->gfx_init)
2110 device->ws->buffer_destroy(device->gfx_init);
2111
2112 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2113 for (unsigned q = 0; q < device->queue_count[i]; q++)
2114 radv_queue_finish(&device->queues[i][q]);
2115 if (device->queue_count[i])
2116 vk_free(&device->alloc, device->queues[i]);
2117 if (device->empty_cs[i])
2118 device->ws->cs_destroy(device->empty_cs[i]);
2119 }
2120 radv_device_finish_meta(device);
2121
2122 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2123 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2124
2125 radv_destroy_shader_slabs(device);
2126
2127 radv_bo_list_finish(&device->bo_list);
2128 vk_free(&device->alloc, device);
2129 }
2130
2131 VkResult radv_EnumerateInstanceLayerProperties(
2132 uint32_t* pPropertyCount,
2133 VkLayerProperties* pProperties)
2134 {
2135 if (pProperties == NULL) {
2136 *pPropertyCount = 0;
2137 return VK_SUCCESS;
2138 }
2139
2140 /* None supported at this time */
2141 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2142 }
2143
2144 VkResult radv_EnumerateDeviceLayerProperties(
2145 VkPhysicalDevice physicalDevice,
2146 uint32_t* pPropertyCount,
2147 VkLayerProperties* pProperties)
2148 {
2149 if (pProperties == NULL) {
2150 *pPropertyCount = 0;
2151 return VK_SUCCESS;
2152 }
2153
2154 /* None supported at this time */
2155 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2156 }
2157
2158 void radv_GetDeviceQueue2(
2159 VkDevice _device,
2160 const VkDeviceQueueInfo2* pQueueInfo,
2161 VkQueue* pQueue)
2162 {
2163 RADV_FROM_HANDLE(radv_device, device, _device);
2164 struct radv_queue *queue;
2165
2166 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2167 if (pQueueInfo->flags != queue->flags) {
2168 /* From the Vulkan 1.1.70 spec:
2169 *
2170 * "The queue returned by vkGetDeviceQueue2 must have the same
2171 * flags value from this structure as that used at device
2172 * creation time in a VkDeviceQueueCreateInfo instance. If no
2173 * matching flags were specified at device creation time then
2174 * pQueue will return VK_NULL_HANDLE."
2175 */
2176 *pQueue = VK_NULL_HANDLE;
2177 return;
2178 }
2179
2180 *pQueue = radv_queue_to_handle(queue);
2181 }
2182
2183 void radv_GetDeviceQueue(
2184 VkDevice _device,
2185 uint32_t queueFamilyIndex,
2186 uint32_t queueIndex,
2187 VkQueue* pQueue)
2188 {
2189 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2190 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2191 .queueFamilyIndex = queueFamilyIndex,
2192 .queueIndex = queueIndex
2193 };
2194
2195 radv_GetDeviceQueue2(_device, &info, pQueue);
2196 }
2197
2198 static void
2199 fill_geom_tess_rings(struct radv_queue *queue,
2200 uint32_t *map,
2201 bool add_sample_positions,
2202 uint32_t esgs_ring_size,
2203 struct radeon_winsys_bo *esgs_ring_bo,
2204 uint32_t gsvs_ring_size,
2205 struct radeon_winsys_bo *gsvs_ring_bo,
2206 uint32_t tess_factor_ring_size,
2207 uint32_t tess_offchip_ring_offset,
2208 uint32_t tess_offchip_ring_size,
2209 struct radeon_winsys_bo *tess_rings_bo)
2210 {
2211 uint32_t *desc = &map[4];
2212
2213 if (esgs_ring_bo) {
2214 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2215
2216 /* stride 0, num records - size, add tid, swizzle, elsize4,
2217 index stride 64 */
2218 desc[0] = esgs_va;
2219 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2220 S_008F04_SWIZZLE_ENABLE(true);
2221 desc[2] = esgs_ring_size;
2222 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2223 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2224 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2225 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2226 S_008F0C_INDEX_STRIDE(3) |
2227 S_008F0C_ADD_TID_ENABLE(1);
2228
2229 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2230 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2231 S_008F0C_OOB_SELECT(2) |
2232 S_008F0C_RESOURCE_LEVEL(1);
2233 } else {
2234 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2235 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2236 S_008F0C_ELEMENT_SIZE(1);
2237 }
2238
2239 /* GS entry for ES->GS ring */
2240 /* stride 0, num records - size, elsize0,
2241 index stride 0 */
2242 desc[4] = esgs_va;
2243 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2244 desc[6] = esgs_ring_size;
2245 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2246 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2247 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2248 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2249
2250 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2251 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2252 S_008F0C_OOB_SELECT(2) |
2253 S_008F0C_RESOURCE_LEVEL(1);
2254 } else {
2255 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2256 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2257 }
2258 }
2259
2260 desc += 8;
2261
2262 if (gsvs_ring_bo) {
2263 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2264
2265 /* VS entry for GS->VS ring */
2266 /* stride 0, num records - size, elsize0,
2267 index stride 0 */
2268 desc[0] = gsvs_va;
2269 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2270 desc[2] = gsvs_ring_size;
2271 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2272 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2273 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2274 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2275
2276 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2277 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2278 S_008F0C_OOB_SELECT(2) |
2279 S_008F0C_RESOURCE_LEVEL(1);
2280 } else {
2281 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2282 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2283 }
2284
2285 /* stride gsvs_itemsize, num records 64
2286 elsize 4, index stride 16 */
2287 /* shader will patch stride and desc[2] */
2288 desc[4] = gsvs_va;
2289 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2290 S_008F04_SWIZZLE_ENABLE(1);
2291 desc[6] = 0;
2292 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2293 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2294 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2295 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2296 S_008F0C_INDEX_STRIDE(1) |
2297 S_008F0C_ADD_TID_ENABLE(true);
2298
2299 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2300 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2301 S_008F0C_OOB_SELECT(2) |
2302 S_008F0C_RESOURCE_LEVEL(1);
2303 } else {
2304 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2305 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2306 S_008F0C_ELEMENT_SIZE(1);
2307 }
2308
2309 }
2310
2311 desc += 8;
2312
2313 if (tess_rings_bo) {
2314 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2315 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2316
2317 desc[0] = tess_va;
2318 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2319 desc[2] = tess_factor_ring_size;
2320 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2321 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2322 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2323 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2324
2325 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2326 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2327 S_008F0C_OOB_SELECT(3) |
2328 S_008F0C_RESOURCE_LEVEL(1);
2329 } else {
2330 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2331 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2332 }
2333
2334 desc[4] = tess_offchip_va;
2335 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2336 desc[6] = tess_offchip_ring_size;
2337 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2338 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2339 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2340 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2341
2342 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2343 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2344 S_008F0C_OOB_SELECT(3) |
2345 S_008F0C_RESOURCE_LEVEL(1);
2346 } else {
2347 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2348 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2349 }
2350 }
2351
2352 desc += 8;
2353
2354 if (add_sample_positions) {
2355 /* add sample positions after all rings */
2356 memcpy(desc, queue->device->sample_locations_1x, 8);
2357 desc += 2;
2358 memcpy(desc, queue->device->sample_locations_2x, 16);
2359 desc += 4;
2360 memcpy(desc, queue->device->sample_locations_4x, 32);
2361 desc += 8;
2362 memcpy(desc, queue->device->sample_locations_8x, 64);
2363 }
2364 }
2365
2366 static unsigned
2367 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2368 {
2369 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2370 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2371 device->physical_device->rad_info.family != CHIP_STONEY;
2372 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2373 unsigned max_offchip_buffers;
2374 unsigned offchip_granularity;
2375 unsigned hs_offchip_param;
2376
2377 /*
2378 * Per RadeonSI:
2379 * This must be one less than the maximum number due to a hw limitation.
2380 * Various hardware bugs need thGFX7
2381 *
2382 * Per AMDVLK:
2383 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2384 * Gfx7 should limit max_offchip_buffers to 508
2385 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2386 *
2387 * Follow AMDVLK here.
2388 */
2389 if (device->physical_device->rad_info.chip_class >= GFX10) {
2390 max_offchip_buffers_per_se = 256;
2391 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2392 device->physical_device->rad_info.chip_class == GFX7 ||
2393 device->physical_device->rad_info.chip_class == GFX6)
2394 --max_offchip_buffers_per_se;
2395
2396 max_offchip_buffers = max_offchip_buffers_per_se *
2397 device->physical_device->rad_info.max_se;
2398
2399 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2400 * around by setting 4K granularity.
2401 */
2402 if (device->tess_offchip_block_dw_size == 4096) {
2403 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2404 offchip_granularity = V_03093C_X_4K_DWORDS;
2405 } else {
2406 assert(device->tess_offchip_block_dw_size == 8192);
2407 offchip_granularity = V_03093C_X_8K_DWORDS;
2408 }
2409
2410 switch (device->physical_device->rad_info.chip_class) {
2411 case GFX6:
2412 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2413 break;
2414 case GFX7:
2415 case GFX8:
2416 case GFX9:
2417 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2418 break;
2419 case GFX10:
2420 break;
2421 default:
2422 break;
2423 }
2424
2425 *max_offchip_buffers_p = max_offchip_buffers;
2426 if (device->physical_device->rad_info.chip_class >= GFX7) {
2427 if (device->physical_device->rad_info.chip_class >= GFX8)
2428 --max_offchip_buffers;
2429 hs_offchip_param =
2430 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2431 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2432 } else {
2433 hs_offchip_param =
2434 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2435 }
2436 return hs_offchip_param;
2437 }
2438
2439 static void
2440 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2441 struct radeon_winsys_bo *esgs_ring_bo,
2442 uint32_t esgs_ring_size,
2443 struct radeon_winsys_bo *gsvs_ring_bo,
2444 uint32_t gsvs_ring_size)
2445 {
2446 if (!esgs_ring_bo && !gsvs_ring_bo)
2447 return;
2448
2449 if (esgs_ring_bo)
2450 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2451
2452 if (gsvs_ring_bo)
2453 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2454
2455 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2456 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2457 radeon_emit(cs, esgs_ring_size >> 8);
2458 radeon_emit(cs, gsvs_ring_size >> 8);
2459 } else {
2460 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2461 radeon_emit(cs, esgs_ring_size >> 8);
2462 radeon_emit(cs, gsvs_ring_size >> 8);
2463 }
2464 }
2465
2466 static void
2467 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2468 unsigned hs_offchip_param, unsigned tf_ring_size,
2469 struct radeon_winsys_bo *tess_rings_bo)
2470 {
2471 uint64_t tf_va;
2472
2473 if (!tess_rings_bo)
2474 return;
2475
2476 tf_va = radv_buffer_get_va(tess_rings_bo);
2477
2478 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2479
2480 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2481 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2482 S_030938_SIZE(tf_ring_size / 4));
2483 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2484 tf_va >> 8);
2485
2486 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2487 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2488 S_030984_BASE_HI(tf_va >> 40));
2489 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2490 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2491 S_030944_BASE_HI(tf_va >> 40));
2492 }
2493 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2494 hs_offchip_param);
2495 } else {
2496 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2497 S_008988_SIZE(tf_ring_size / 4));
2498 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2499 tf_va >> 8);
2500 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2501 hs_offchip_param);
2502 }
2503 }
2504
2505 static void
2506 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2507 struct radeon_winsys_bo *compute_scratch_bo)
2508 {
2509 uint64_t scratch_va;
2510
2511 if (!compute_scratch_bo)
2512 return;
2513
2514 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2515
2516 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2517
2518 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2519 radeon_emit(cs, scratch_va);
2520 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2521 S_008F04_SWIZZLE_ENABLE(1));
2522 }
2523
2524 static void
2525 radv_emit_global_shader_pointers(struct radv_queue *queue,
2526 struct radeon_cmdbuf *cs,
2527 struct radeon_winsys_bo *descriptor_bo)
2528 {
2529 uint64_t va;
2530
2531 if (!descriptor_bo)
2532 return;
2533
2534 va = radv_buffer_get_va(descriptor_bo);
2535
2536 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2537
2538 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2539 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2540 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2541 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2542 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2543
2544 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2545 radv_emit_shader_pointer(queue->device, cs, regs[i],
2546 va, true);
2547 }
2548 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2549 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2550 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2551 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2552 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2553
2554 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2555 radv_emit_shader_pointer(queue->device, cs, regs[i],
2556 va, true);
2557 }
2558 } else {
2559 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2560 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2561 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2562 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2563 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2564 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2565
2566 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2567 radv_emit_shader_pointer(queue->device, cs, regs[i],
2568 va, true);
2569 }
2570 }
2571 }
2572
2573 static void
2574 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2575 {
2576 struct radv_device *device = queue->device;
2577
2578 if (device->gfx_init) {
2579 uint64_t va = radv_buffer_get_va(device->gfx_init);
2580
2581 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2582 radeon_emit(cs, va);
2583 radeon_emit(cs, va >> 32);
2584 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2585
2586 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2587 } else {
2588 struct radv_physical_device *physical_device = device->physical_device;
2589 si_emit_graphics(physical_device, cs);
2590 }
2591 }
2592
2593 static void
2594 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2595 {
2596 struct radv_physical_device *physical_device = queue->device->physical_device;
2597 si_emit_compute(physical_device, cs);
2598 }
2599
2600 static VkResult
2601 radv_get_preamble_cs(struct radv_queue *queue,
2602 uint32_t scratch_size,
2603 uint32_t compute_scratch_size,
2604 uint32_t esgs_ring_size,
2605 uint32_t gsvs_ring_size,
2606 bool needs_tess_rings,
2607 bool needs_sample_positions,
2608 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2609 struct radeon_cmdbuf **initial_preamble_cs,
2610 struct radeon_cmdbuf **continue_preamble_cs)
2611 {
2612 struct radeon_winsys_bo *scratch_bo = NULL;
2613 struct radeon_winsys_bo *descriptor_bo = NULL;
2614 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2615 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2616 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2617 struct radeon_winsys_bo *tess_rings_bo = NULL;
2618 struct radeon_cmdbuf *dest_cs[3] = {0};
2619 bool add_tess_rings = false, add_sample_positions = false;
2620 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2621 unsigned max_offchip_buffers;
2622 unsigned hs_offchip_param = 0;
2623 unsigned tess_offchip_ring_offset;
2624 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2625 if (!queue->has_tess_rings) {
2626 if (needs_tess_rings)
2627 add_tess_rings = true;
2628 }
2629 if (!queue->has_sample_positions) {
2630 if (needs_sample_positions)
2631 add_sample_positions = true;
2632 }
2633 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2634 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2635 &max_offchip_buffers);
2636 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2637 tess_offchip_ring_size = max_offchip_buffers *
2638 queue->device->tess_offchip_block_dw_size * 4;
2639
2640 if (scratch_size <= queue->scratch_size &&
2641 compute_scratch_size <= queue->compute_scratch_size &&
2642 esgs_ring_size <= queue->esgs_ring_size &&
2643 gsvs_ring_size <= queue->gsvs_ring_size &&
2644 !add_tess_rings && !add_sample_positions &&
2645 queue->initial_preamble_cs) {
2646 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2647 *initial_preamble_cs = queue->initial_preamble_cs;
2648 *continue_preamble_cs = queue->continue_preamble_cs;
2649 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2650 *continue_preamble_cs = NULL;
2651 return VK_SUCCESS;
2652 }
2653
2654 if (scratch_size > queue->scratch_size) {
2655 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2656 scratch_size,
2657 4096,
2658 RADEON_DOMAIN_VRAM,
2659 ring_bo_flags,
2660 RADV_BO_PRIORITY_SCRATCH);
2661 if (!scratch_bo)
2662 goto fail;
2663 } else
2664 scratch_bo = queue->scratch_bo;
2665
2666 if (compute_scratch_size > queue->compute_scratch_size) {
2667 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2668 compute_scratch_size,
2669 4096,
2670 RADEON_DOMAIN_VRAM,
2671 ring_bo_flags,
2672 RADV_BO_PRIORITY_SCRATCH);
2673 if (!compute_scratch_bo)
2674 goto fail;
2675
2676 } else
2677 compute_scratch_bo = queue->compute_scratch_bo;
2678
2679 if (esgs_ring_size > queue->esgs_ring_size) {
2680 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2681 esgs_ring_size,
2682 4096,
2683 RADEON_DOMAIN_VRAM,
2684 ring_bo_flags,
2685 RADV_BO_PRIORITY_SCRATCH);
2686 if (!esgs_ring_bo)
2687 goto fail;
2688 } else {
2689 esgs_ring_bo = queue->esgs_ring_bo;
2690 esgs_ring_size = queue->esgs_ring_size;
2691 }
2692
2693 if (gsvs_ring_size > queue->gsvs_ring_size) {
2694 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2695 gsvs_ring_size,
2696 4096,
2697 RADEON_DOMAIN_VRAM,
2698 ring_bo_flags,
2699 RADV_BO_PRIORITY_SCRATCH);
2700 if (!gsvs_ring_bo)
2701 goto fail;
2702 } else {
2703 gsvs_ring_bo = queue->gsvs_ring_bo;
2704 gsvs_ring_size = queue->gsvs_ring_size;
2705 }
2706
2707 if (add_tess_rings) {
2708 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2709 tess_offchip_ring_offset + tess_offchip_ring_size,
2710 256,
2711 RADEON_DOMAIN_VRAM,
2712 ring_bo_flags,
2713 RADV_BO_PRIORITY_SCRATCH);
2714 if (!tess_rings_bo)
2715 goto fail;
2716 } else {
2717 tess_rings_bo = queue->tess_rings_bo;
2718 }
2719
2720 if (scratch_bo != queue->scratch_bo ||
2721 esgs_ring_bo != queue->esgs_ring_bo ||
2722 gsvs_ring_bo != queue->gsvs_ring_bo ||
2723 tess_rings_bo != queue->tess_rings_bo ||
2724 add_sample_positions) {
2725 uint32_t size = 0;
2726 if (gsvs_ring_bo || esgs_ring_bo ||
2727 tess_rings_bo || add_sample_positions) {
2728 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2729 if (add_sample_positions)
2730 size += 128; /* 64+32+16+8 = 120 bytes */
2731 }
2732 else if (scratch_bo)
2733 size = 8; /* 2 dword */
2734
2735 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2736 size,
2737 4096,
2738 RADEON_DOMAIN_VRAM,
2739 RADEON_FLAG_CPU_ACCESS |
2740 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2741 RADEON_FLAG_READ_ONLY,
2742 RADV_BO_PRIORITY_DESCRIPTOR);
2743 if (!descriptor_bo)
2744 goto fail;
2745 } else
2746 descriptor_bo = queue->descriptor_bo;
2747
2748 if (descriptor_bo != queue->descriptor_bo) {
2749 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2750
2751 if (scratch_bo) {
2752 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2753 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2754 S_008F04_SWIZZLE_ENABLE(1);
2755 map[0] = scratch_va;
2756 map[1] = rsrc1;
2757 }
2758
2759 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2760 fill_geom_tess_rings(queue, map, add_sample_positions,
2761 esgs_ring_size, esgs_ring_bo,
2762 gsvs_ring_size, gsvs_ring_bo,
2763 tess_factor_ring_size,
2764 tess_offchip_ring_offset,
2765 tess_offchip_ring_size,
2766 tess_rings_bo);
2767
2768 queue->device->ws->buffer_unmap(descriptor_bo);
2769 }
2770
2771 for(int i = 0; i < 3; ++i) {
2772 struct radeon_cmdbuf *cs = NULL;
2773 cs = queue->device->ws->cs_create(queue->device->ws,
2774 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2775 if (!cs)
2776 goto fail;
2777
2778 dest_cs[i] = cs;
2779
2780 if (scratch_bo)
2781 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2782
2783 /* Emit initial configuration. */
2784 switch (queue->queue_family_index) {
2785 case RADV_QUEUE_GENERAL:
2786 radv_init_graphics_state(cs, queue);
2787 break;
2788 case RADV_QUEUE_COMPUTE:
2789 radv_init_compute_state(cs, queue);
2790 break;
2791 case RADV_QUEUE_TRANSFER:
2792 break;
2793 }
2794
2795 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2796 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2797 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2798
2799 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2800 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2801 }
2802
2803 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2804 gsvs_ring_bo, gsvs_ring_size);
2805 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2806 tess_factor_ring_size, tess_rings_bo);
2807 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2808 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2809
2810 if (i == 0) {
2811 si_cs_emit_cache_flush(cs,
2812 queue->device->physical_device->rad_info.chip_class,
2813 NULL, 0,
2814 queue->queue_family_index == RING_COMPUTE &&
2815 queue->device->physical_device->rad_info.chip_class >= GFX7,
2816 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2817 RADV_CMD_FLAG_INV_ICACHE |
2818 RADV_CMD_FLAG_INV_SCACHE |
2819 RADV_CMD_FLAG_INV_VCACHE |
2820 RADV_CMD_FLAG_INV_L2 |
2821 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2822 } else if (i == 1) {
2823 si_cs_emit_cache_flush(cs,
2824 queue->device->physical_device->rad_info.chip_class,
2825 NULL, 0,
2826 queue->queue_family_index == RING_COMPUTE &&
2827 queue->device->physical_device->rad_info.chip_class >= GFX7,
2828 RADV_CMD_FLAG_INV_ICACHE |
2829 RADV_CMD_FLAG_INV_SCACHE |
2830 RADV_CMD_FLAG_INV_VCACHE |
2831 RADV_CMD_FLAG_INV_L2 |
2832 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2833 }
2834
2835 if (!queue->device->ws->cs_finalize(cs))
2836 goto fail;
2837 }
2838
2839 if (queue->initial_full_flush_preamble_cs)
2840 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2841
2842 if (queue->initial_preamble_cs)
2843 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2844
2845 if (queue->continue_preamble_cs)
2846 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2847
2848 queue->initial_full_flush_preamble_cs = dest_cs[0];
2849 queue->initial_preamble_cs = dest_cs[1];
2850 queue->continue_preamble_cs = dest_cs[2];
2851
2852 if (scratch_bo != queue->scratch_bo) {
2853 if (queue->scratch_bo)
2854 queue->device->ws->buffer_destroy(queue->scratch_bo);
2855 queue->scratch_bo = scratch_bo;
2856 queue->scratch_size = scratch_size;
2857 }
2858
2859 if (compute_scratch_bo != queue->compute_scratch_bo) {
2860 if (queue->compute_scratch_bo)
2861 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2862 queue->compute_scratch_bo = compute_scratch_bo;
2863 queue->compute_scratch_size = compute_scratch_size;
2864 }
2865
2866 if (esgs_ring_bo != queue->esgs_ring_bo) {
2867 if (queue->esgs_ring_bo)
2868 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2869 queue->esgs_ring_bo = esgs_ring_bo;
2870 queue->esgs_ring_size = esgs_ring_size;
2871 }
2872
2873 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2874 if (queue->gsvs_ring_bo)
2875 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2876 queue->gsvs_ring_bo = gsvs_ring_bo;
2877 queue->gsvs_ring_size = gsvs_ring_size;
2878 }
2879
2880 if (tess_rings_bo != queue->tess_rings_bo) {
2881 queue->tess_rings_bo = tess_rings_bo;
2882 queue->has_tess_rings = true;
2883 }
2884
2885 if (descriptor_bo != queue->descriptor_bo) {
2886 if (queue->descriptor_bo)
2887 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2888
2889 queue->descriptor_bo = descriptor_bo;
2890 }
2891
2892 if (add_sample_positions)
2893 queue->has_sample_positions = true;
2894
2895 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2896 *initial_preamble_cs = queue->initial_preamble_cs;
2897 *continue_preamble_cs = queue->continue_preamble_cs;
2898 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2899 *continue_preamble_cs = NULL;
2900 return VK_SUCCESS;
2901 fail:
2902 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2903 if (dest_cs[i])
2904 queue->device->ws->cs_destroy(dest_cs[i]);
2905 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2906 queue->device->ws->buffer_destroy(descriptor_bo);
2907 if (scratch_bo && scratch_bo != queue->scratch_bo)
2908 queue->device->ws->buffer_destroy(scratch_bo);
2909 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2910 queue->device->ws->buffer_destroy(compute_scratch_bo);
2911 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2912 queue->device->ws->buffer_destroy(esgs_ring_bo);
2913 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2914 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2915 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2916 queue->device->ws->buffer_destroy(tess_rings_bo);
2917 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2918 }
2919
2920 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2921 struct radv_winsys_sem_counts *counts,
2922 int num_sems,
2923 const VkSemaphore *sems,
2924 VkFence _fence,
2925 bool reset_temp)
2926 {
2927 int syncobj_idx = 0, sem_idx = 0;
2928
2929 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2930 return VK_SUCCESS;
2931
2932 for (uint32_t i = 0; i < num_sems; i++) {
2933 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2934
2935 if (sem->temp_syncobj || sem->syncobj)
2936 counts->syncobj_count++;
2937 else
2938 counts->sem_count++;
2939 }
2940
2941 if (_fence != VK_NULL_HANDLE) {
2942 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2943 if (fence->temp_syncobj || fence->syncobj)
2944 counts->syncobj_count++;
2945 }
2946
2947 if (counts->syncobj_count) {
2948 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2949 if (!counts->syncobj)
2950 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2951 }
2952
2953 if (counts->sem_count) {
2954 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2955 if (!counts->sem) {
2956 free(counts->syncobj);
2957 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2958 }
2959 }
2960
2961 for (uint32_t i = 0; i < num_sems; i++) {
2962 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2963
2964 if (sem->temp_syncobj) {
2965 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2966 }
2967 else if (sem->syncobj)
2968 counts->syncobj[syncobj_idx++] = sem->syncobj;
2969 else {
2970 assert(sem->sem);
2971 counts->sem[sem_idx++] = sem->sem;
2972 }
2973 }
2974
2975 if (_fence != VK_NULL_HANDLE) {
2976 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2977 if (fence->temp_syncobj)
2978 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2979 else if (fence->syncobj)
2980 counts->syncobj[syncobj_idx++] = fence->syncobj;
2981 }
2982
2983 return VK_SUCCESS;
2984 }
2985
2986 static void
2987 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2988 {
2989 free(sem_info->wait.syncobj);
2990 free(sem_info->wait.sem);
2991 free(sem_info->signal.syncobj);
2992 free(sem_info->signal.sem);
2993 }
2994
2995
2996 static void radv_free_temp_syncobjs(struct radv_device *device,
2997 int num_sems,
2998 const VkSemaphore *sems)
2999 {
3000 for (uint32_t i = 0; i < num_sems; i++) {
3001 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
3002
3003 if (sem->temp_syncobj) {
3004 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
3005 sem->temp_syncobj = 0;
3006 }
3007 }
3008 }
3009
3010 static VkResult
3011 radv_alloc_sem_info(struct radv_instance *instance,
3012 struct radv_winsys_sem_info *sem_info,
3013 int num_wait_sems,
3014 const VkSemaphore *wait_sems,
3015 int num_signal_sems,
3016 const VkSemaphore *signal_sems,
3017 VkFence fence)
3018 {
3019 VkResult ret;
3020 memset(sem_info, 0, sizeof(*sem_info));
3021
3022 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
3023 if (ret)
3024 return ret;
3025 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3026 if (ret)
3027 radv_free_sem_info(sem_info);
3028
3029 /* caller can override these */
3030 sem_info->cs_emit_wait = true;
3031 sem_info->cs_emit_signal = true;
3032 return ret;
3033 }
3034
3035 /* Signals fence as soon as all the work currently put on queue is done. */
3036 static VkResult radv_signal_fence(struct radv_queue *queue,
3037 struct radv_fence *fence)
3038 {
3039 int ret;
3040 VkResult result;
3041 struct radv_winsys_sem_info sem_info;
3042
3043 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3044 radv_fence_to_handle(fence));
3045 if (result != VK_SUCCESS)
3046 return result;
3047
3048 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3049 &queue->device->empty_cs[queue->queue_family_index],
3050 1, NULL, NULL, &sem_info, NULL,
3051 false, fence->fence);
3052 radv_free_sem_info(&sem_info);
3053
3054 if (ret)
3055 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3056
3057 return VK_SUCCESS;
3058 }
3059
3060 VkResult radv_QueueSubmit(
3061 VkQueue _queue,
3062 uint32_t submitCount,
3063 const VkSubmitInfo* pSubmits,
3064 VkFence _fence)
3065 {
3066 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3067 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3068 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3069 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3070 int ret;
3071 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3072 uint32_t scratch_size = 0;
3073 uint32_t compute_scratch_size = 0;
3074 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3075 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3076 VkResult result;
3077 bool fence_emitted = false;
3078 bool tess_rings_needed = false;
3079 bool sample_positions_needed = false;
3080
3081 /* Do this first so failing to allocate scratch buffers can't result in
3082 * partially executed submissions. */
3083 for (uint32_t i = 0; i < submitCount; i++) {
3084 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3085 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3086 pSubmits[i].pCommandBuffers[j]);
3087
3088 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3089 compute_scratch_size = MAX2(compute_scratch_size,
3090 cmd_buffer->compute_scratch_size_needed);
3091 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3092 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3093 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3094 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3095 }
3096 }
3097
3098 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3099 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3100 sample_positions_needed, &initial_flush_preamble_cs,
3101 &initial_preamble_cs, &continue_preamble_cs);
3102 if (result != VK_SUCCESS)
3103 return result;
3104
3105 for (uint32_t i = 0; i < submitCount; i++) {
3106 struct radeon_cmdbuf **cs_array;
3107 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3108 bool can_patch = true;
3109 uint32_t advance;
3110 struct radv_winsys_sem_info sem_info;
3111
3112 result = radv_alloc_sem_info(queue->device->instance,
3113 &sem_info,
3114 pSubmits[i].waitSemaphoreCount,
3115 pSubmits[i].pWaitSemaphores,
3116 pSubmits[i].signalSemaphoreCount,
3117 pSubmits[i].pSignalSemaphores,
3118 _fence);
3119 if (result != VK_SUCCESS)
3120 return result;
3121
3122 if (!pSubmits[i].commandBufferCount) {
3123 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3124 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3125 &queue->device->empty_cs[queue->queue_family_index],
3126 1, NULL, NULL,
3127 &sem_info, NULL,
3128 false, base_fence);
3129 if (ret) {
3130 radv_loge("failed to submit CS %d\n", i);
3131 abort();
3132 }
3133 fence_emitted = true;
3134 }
3135 radv_free_sem_info(&sem_info);
3136 continue;
3137 }
3138
3139 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3140 (pSubmits[i].commandBufferCount));
3141
3142 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3143 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3144 pSubmits[i].pCommandBuffers[j]);
3145 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3146
3147 cs_array[j] = cmd_buffer->cs;
3148 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3149 can_patch = false;
3150
3151 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3152 }
3153
3154 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3155 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3156 const struct radv_winsys_bo_list *bo_list = NULL;
3157
3158 advance = MIN2(max_cs_submission,
3159 pSubmits[i].commandBufferCount - j);
3160
3161 if (queue->device->trace_bo)
3162 *queue->device->trace_id_ptr = 0;
3163
3164 sem_info.cs_emit_wait = j == 0;
3165 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3166
3167 if (unlikely(queue->device->use_global_bo_list)) {
3168 pthread_mutex_lock(&queue->device->bo_list.mutex);
3169 bo_list = &queue->device->bo_list.list;
3170 }
3171
3172 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3173 advance, initial_preamble, continue_preamble_cs,
3174 &sem_info, bo_list,
3175 can_patch, base_fence);
3176
3177 if (unlikely(queue->device->use_global_bo_list))
3178 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3179
3180 if (ret) {
3181 radv_loge("failed to submit CS %d\n", i);
3182 abort();
3183 }
3184 fence_emitted = true;
3185 if (queue->device->trace_bo) {
3186 radv_check_gpu_hangs(queue, cs_array[j]);
3187 }
3188 }
3189
3190 radv_free_temp_syncobjs(queue->device,
3191 pSubmits[i].waitSemaphoreCount,
3192 pSubmits[i].pWaitSemaphores);
3193 radv_free_sem_info(&sem_info);
3194 free(cs_array);
3195 }
3196
3197 if (fence) {
3198 if (!fence_emitted) {
3199 result = radv_signal_fence(queue, fence);
3200 if (result != VK_SUCCESS)
3201 return result;
3202 }
3203 }
3204
3205 return VK_SUCCESS;
3206 }
3207
3208 VkResult radv_QueueWaitIdle(
3209 VkQueue _queue)
3210 {
3211 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3212
3213 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3214 radv_queue_family_to_ring(queue->queue_family_index),
3215 queue->queue_idx);
3216 return VK_SUCCESS;
3217 }
3218
3219 VkResult radv_DeviceWaitIdle(
3220 VkDevice _device)
3221 {
3222 RADV_FROM_HANDLE(radv_device, device, _device);
3223
3224 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3225 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3226 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3227 }
3228 }
3229 return VK_SUCCESS;
3230 }
3231
3232 VkResult radv_EnumerateInstanceExtensionProperties(
3233 const char* pLayerName,
3234 uint32_t* pPropertyCount,
3235 VkExtensionProperties* pProperties)
3236 {
3237 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3238
3239 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3240 if (radv_supported_instance_extensions.extensions[i]) {
3241 vk_outarray_append(&out, prop) {
3242 *prop = radv_instance_extensions[i];
3243 }
3244 }
3245 }
3246
3247 return vk_outarray_status(&out);
3248 }
3249
3250 VkResult radv_EnumerateDeviceExtensionProperties(
3251 VkPhysicalDevice physicalDevice,
3252 const char* pLayerName,
3253 uint32_t* pPropertyCount,
3254 VkExtensionProperties* pProperties)
3255 {
3256 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3257 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3258
3259 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3260 if (device->supported_extensions.extensions[i]) {
3261 vk_outarray_append(&out, prop) {
3262 *prop = radv_device_extensions[i];
3263 }
3264 }
3265 }
3266
3267 return vk_outarray_status(&out);
3268 }
3269
3270 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3271 VkInstance _instance,
3272 const char* pName)
3273 {
3274 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3275 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3276
3277 if (unchecked) {
3278 return radv_lookup_entrypoint_unchecked(pName);
3279 } else {
3280 return radv_lookup_entrypoint_checked(pName,
3281 instance ? instance->apiVersion : 0,
3282 instance ? &instance->enabled_extensions : NULL,
3283 NULL);
3284 }
3285 }
3286
3287 /* The loader wants us to expose a second GetInstanceProcAddr function
3288 * to work around certain LD_PRELOAD issues seen in apps.
3289 */
3290 PUBLIC
3291 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3292 VkInstance instance,
3293 const char* pName);
3294
3295 PUBLIC
3296 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3297 VkInstance instance,
3298 const char* pName)
3299 {
3300 return radv_GetInstanceProcAddr(instance, pName);
3301 }
3302
3303 PUBLIC
3304 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3305 VkInstance _instance,
3306 const char* pName);
3307
3308 PUBLIC
3309 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3310 VkInstance _instance,
3311 const char* pName)
3312 {
3313 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3314
3315 return radv_lookup_physical_device_entrypoint_checked(pName,
3316 instance ? instance->apiVersion : 0,
3317 instance ? &instance->enabled_extensions : NULL);
3318 }
3319
3320 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3321 VkDevice _device,
3322 const char* pName)
3323 {
3324 RADV_FROM_HANDLE(radv_device, device, _device);
3325 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3326
3327 if (unchecked) {
3328 return radv_lookup_entrypoint_unchecked(pName);
3329 } else {
3330 return radv_lookup_entrypoint_checked(pName,
3331 device->instance->apiVersion,
3332 &device->instance->enabled_extensions,
3333 &device->enabled_extensions);
3334 }
3335 }
3336
3337 bool radv_get_memory_fd(struct radv_device *device,
3338 struct radv_device_memory *memory,
3339 int *pFD)
3340 {
3341 struct radeon_bo_metadata metadata;
3342
3343 if (memory->image) {
3344 radv_init_metadata(device, memory->image, &metadata);
3345 device->ws->buffer_set_metadata(memory->bo, &metadata);
3346 }
3347
3348 return device->ws->buffer_get_fd(device->ws, memory->bo,
3349 pFD);
3350 }
3351
3352 static VkResult radv_alloc_memory(struct radv_device *device,
3353 const VkMemoryAllocateInfo* pAllocateInfo,
3354 const VkAllocationCallbacks* pAllocator,
3355 VkDeviceMemory* pMem)
3356 {
3357 struct radv_device_memory *mem;
3358 VkResult result;
3359 enum radeon_bo_domain domain;
3360 uint32_t flags = 0;
3361 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3362
3363 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3364
3365 if (pAllocateInfo->allocationSize == 0) {
3366 /* Apparently, this is allowed */
3367 *pMem = VK_NULL_HANDLE;
3368 return VK_SUCCESS;
3369 }
3370
3371 const VkImportMemoryFdInfoKHR *import_info =
3372 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3373 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3374 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3375 const VkExportMemoryAllocateInfo *export_info =
3376 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3377 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3378 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3379
3380 const struct wsi_memory_allocate_info *wsi_info =
3381 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3382
3383 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3384 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3385 if (mem == NULL)
3386 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3387
3388 if (wsi_info && wsi_info->implicit_sync)
3389 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3390
3391 if (dedicate_info) {
3392 mem->image = radv_image_from_handle(dedicate_info->image);
3393 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3394 } else {
3395 mem->image = NULL;
3396 mem->buffer = NULL;
3397 }
3398
3399 float priority_float = 0.5;
3400 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3401 vk_find_struct_const(pAllocateInfo->pNext,
3402 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3403 if (priority_ext)
3404 priority_float = priority_ext->priority;
3405
3406 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3407 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3408
3409 mem->user_ptr = NULL;
3410
3411 if (import_info) {
3412 assert(import_info->handleType ==
3413 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3414 import_info->handleType ==
3415 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3416 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3417 priority, NULL, NULL);
3418 if (!mem->bo) {
3419 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3420 goto fail;
3421 } else {
3422 close(import_info->fd);
3423 }
3424 } else if (host_ptr_info) {
3425 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3426 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3427 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3428 pAllocateInfo->allocationSize,
3429 priority);
3430 if (!mem->bo) {
3431 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3432 goto fail;
3433 } else {
3434 mem->user_ptr = host_ptr_info->pHostPointer;
3435 }
3436 } else {
3437 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3438 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3439 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3440 domain = RADEON_DOMAIN_GTT;
3441 else
3442 domain = RADEON_DOMAIN_VRAM;
3443
3444 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3445 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3446 else
3447 flags |= RADEON_FLAG_CPU_ACCESS;
3448
3449 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3450 flags |= RADEON_FLAG_GTT_WC;
3451
3452 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3453 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3454 if (device->use_global_bo_list) {
3455 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3456 }
3457 }
3458
3459 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3460 domain, flags, priority);
3461
3462 if (!mem->bo) {
3463 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3464 goto fail;
3465 }
3466 mem->type_index = mem_type_index;
3467 }
3468
3469 result = radv_bo_list_add(device, mem->bo);
3470 if (result != VK_SUCCESS)
3471 goto fail_bo;
3472
3473 *pMem = radv_device_memory_to_handle(mem);
3474
3475 return VK_SUCCESS;
3476
3477 fail_bo:
3478 device->ws->buffer_destroy(mem->bo);
3479 fail:
3480 vk_free2(&device->alloc, pAllocator, mem);
3481
3482 return result;
3483 }
3484
3485 VkResult radv_AllocateMemory(
3486 VkDevice _device,
3487 const VkMemoryAllocateInfo* pAllocateInfo,
3488 const VkAllocationCallbacks* pAllocator,
3489 VkDeviceMemory* pMem)
3490 {
3491 RADV_FROM_HANDLE(radv_device, device, _device);
3492 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3493 }
3494
3495 void radv_FreeMemory(
3496 VkDevice _device,
3497 VkDeviceMemory _mem,
3498 const VkAllocationCallbacks* pAllocator)
3499 {
3500 RADV_FROM_HANDLE(radv_device, device, _device);
3501 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3502
3503 if (mem == NULL)
3504 return;
3505
3506 radv_bo_list_remove(device, mem->bo);
3507 device->ws->buffer_destroy(mem->bo);
3508 mem->bo = NULL;
3509
3510 vk_free2(&device->alloc, pAllocator, mem);
3511 }
3512
3513 VkResult radv_MapMemory(
3514 VkDevice _device,
3515 VkDeviceMemory _memory,
3516 VkDeviceSize offset,
3517 VkDeviceSize size,
3518 VkMemoryMapFlags flags,
3519 void** ppData)
3520 {
3521 RADV_FROM_HANDLE(radv_device, device, _device);
3522 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3523
3524 if (mem == NULL) {
3525 *ppData = NULL;
3526 return VK_SUCCESS;
3527 }
3528
3529 if (mem->user_ptr)
3530 *ppData = mem->user_ptr;
3531 else
3532 *ppData = device->ws->buffer_map(mem->bo);
3533
3534 if (*ppData) {
3535 *ppData += offset;
3536 return VK_SUCCESS;
3537 }
3538
3539 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3540 }
3541
3542 void radv_UnmapMemory(
3543 VkDevice _device,
3544 VkDeviceMemory _memory)
3545 {
3546 RADV_FROM_HANDLE(radv_device, device, _device);
3547 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3548
3549 if (mem == NULL)
3550 return;
3551
3552 if (mem->user_ptr == NULL)
3553 device->ws->buffer_unmap(mem->bo);
3554 }
3555
3556 VkResult radv_FlushMappedMemoryRanges(
3557 VkDevice _device,
3558 uint32_t memoryRangeCount,
3559 const VkMappedMemoryRange* pMemoryRanges)
3560 {
3561 return VK_SUCCESS;
3562 }
3563
3564 VkResult radv_InvalidateMappedMemoryRanges(
3565 VkDevice _device,
3566 uint32_t memoryRangeCount,
3567 const VkMappedMemoryRange* pMemoryRanges)
3568 {
3569 return VK_SUCCESS;
3570 }
3571
3572 void radv_GetBufferMemoryRequirements(
3573 VkDevice _device,
3574 VkBuffer _buffer,
3575 VkMemoryRequirements* pMemoryRequirements)
3576 {
3577 RADV_FROM_HANDLE(radv_device, device, _device);
3578 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3579
3580 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3581
3582 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3583 pMemoryRequirements->alignment = 4096;
3584 else
3585 pMemoryRequirements->alignment = 16;
3586
3587 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3588 }
3589
3590 void radv_GetBufferMemoryRequirements2(
3591 VkDevice device,
3592 const VkBufferMemoryRequirementsInfo2 *pInfo,
3593 VkMemoryRequirements2 *pMemoryRequirements)
3594 {
3595 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3596 &pMemoryRequirements->memoryRequirements);
3597 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3598 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3599 switch (ext->sType) {
3600 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3601 VkMemoryDedicatedRequirements *req =
3602 (VkMemoryDedicatedRequirements *) ext;
3603 req->requiresDedicatedAllocation = buffer->shareable;
3604 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3605 break;
3606 }
3607 default:
3608 break;
3609 }
3610 }
3611 }
3612
3613 void radv_GetImageMemoryRequirements(
3614 VkDevice _device,
3615 VkImage _image,
3616 VkMemoryRequirements* pMemoryRequirements)
3617 {
3618 RADV_FROM_HANDLE(radv_device, device, _device);
3619 RADV_FROM_HANDLE(radv_image, image, _image);
3620
3621 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3622
3623 pMemoryRequirements->size = image->size;
3624 pMemoryRequirements->alignment = image->alignment;
3625 }
3626
3627 void radv_GetImageMemoryRequirements2(
3628 VkDevice device,
3629 const VkImageMemoryRequirementsInfo2 *pInfo,
3630 VkMemoryRequirements2 *pMemoryRequirements)
3631 {
3632 radv_GetImageMemoryRequirements(device, pInfo->image,
3633 &pMemoryRequirements->memoryRequirements);
3634
3635 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3636
3637 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3638 switch (ext->sType) {
3639 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3640 VkMemoryDedicatedRequirements *req =
3641 (VkMemoryDedicatedRequirements *) ext;
3642 req->requiresDedicatedAllocation = image->shareable;
3643 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3644 break;
3645 }
3646 default:
3647 break;
3648 }
3649 }
3650 }
3651
3652 void radv_GetImageSparseMemoryRequirements(
3653 VkDevice device,
3654 VkImage image,
3655 uint32_t* pSparseMemoryRequirementCount,
3656 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3657 {
3658 stub();
3659 }
3660
3661 void radv_GetImageSparseMemoryRequirements2(
3662 VkDevice device,
3663 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3664 uint32_t* pSparseMemoryRequirementCount,
3665 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3666 {
3667 stub();
3668 }
3669
3670 void radv_GetDeviceMemoryCommitment(
3671 VkDevice device,
3672 VkDeviceMemory memory,
3673 VkDeviceSize* pCommittedMemoryInBytes)
3674 {
3675 *pCommittedMemoryInBytes = 0;
3676 }
3677
3678 VkResult radv_BindBufferMemory2(VkDevice device,
3679 uint32_t bindInfoCount,
3680 const VkBindBufferMemoryInfo *pBindInfos)
3681 {
3682 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3683 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3684 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3685
3686 if (mem) {
3687 buffer->bo = mem->bo;
3688 buffer->offset = pBindInfos[i].memoryOffset;
3689 } else {
3690 buffer->bo = NULL;
3691 }
3692 }
3693 return VK_SUCCESS;
3694 }
3695
3696 VkResult radv_BindBufferMemory(
3697 VkDevice device,
3698 VkBuffer buffer,
3699 VkDeviceMemory memory,
3700 VkDeviceSize memoryOffset)
3701 {
3702 const VkBindBufferMemoryInfo info = {
3703 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3704 .buffer = buffer,
3705 .memory = memory,
3706 .memoryOffset = memoryOffset
3707 };
3708
3709 return radv_BindBufferMemory2(device, 1, &info);
3710 }
3711
3712 VkResult radv_BindImageMemory2(VkDevice device,
3713 uint32_t bindInfoCount,
3714 const VkBindImageMemoryInfo *pBindInfos)
3715 {
3716 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3717 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3718 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3719
3720 if (mem) {
3721 image->bo = mem->bo;
3722 image->offset = pBindInfos[i].memoryOffset;
3723 } else {
3724 image->bo = NULL;
3725 image->offset = 0;
3726 }
3727 }
3728 return VK_SUCCESS;
3729 }
3730
3731
3732 VkResult radv_BindImageMemory(
3733 VkDevice device,
3734 VkImage image,
3735 VkDeviceMemory memory,
3736 VkDeviceSize memoryOffset)
3737 {
3738 const VkBindImageMemoryInfo info = {
3739 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3740 .image = image,
3741 .memory = memory,
3742 .memoryOffset = memoryOffset
3743 };
3744
3745 return radv_BindImageMemory2(device, 1, &info);
3746 }
3747
3748
3749 static void
3750 radv_sparse_buffer_bind_memory(struct radv_device *device,
3751 const VkSparseBufferMemoryBindInfo *bind)
3752 {
3753 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3754
3755 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3756 struct radv_device_memory *mem = NULL;
3757
3758 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3759 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3760
3761 device->ws->buffer_virtual_bind(buffer->bo,
3762 bind->pBinds[i].resourceOffset,
3763 bind->pBinds[i].size,
3764 mem ? mem->bo : NULL,
3765 bind->pBinds[i].memoryOffset);
3766 }
3767 }
3768
3769 static void
3770 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3771 const VkSparseImageOpaqueMemoryBindInfo *bind)
3772 {
3773 RADV_FROM_HANDLE(radv_image, image, bind->image);
3774
3775 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3776 struct radv_device_memory *mem = NULL;
3777
3778 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3779 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3780
3781 device->ws->buffer_virtual_bind(image->bo,
3782 bind->pBinds[i].resourceOffset,
3783 bind->pBinds[i].size,
3784 mem ? mem->bo : NULL,
3785 bind->pBinds[i].memoryOffset);
3786 }
3787 }
3788
3789 VkResult radv_QueueBindSparse(
3790 VkQueue _queue,
3791 uint32_t bindInfoCount,
3792 const VkBindSparseInfo* pBindInfo,
3793 VkFence _fence)
3794 {
3795 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3796 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3797 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3798 bool fence_emitted = false;
3799 VkResult result;
3800 int ret;
3801
3802 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3803 struct radv_winsys_sem_info sem_info;
3804 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3805 radv_sparse_buffer_bind_memory(queue->device,
3806 pBindInfo[i].pBufferBinds + j);
3807 }
3808
3809 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3810 radv_sparse_image_opaque_bind_memory(queue->device,
3811 pBindInfo[i].pImageOpaqueBinds + j);
3812 }
3813
3814 VkResult result;
3815 result = radv_alloc_sem_info(queue->device->instance,
3816 &sem_info,
3817 pBindInfo[i].waitSemaphoreCount,
3818 pBindInfo[i].pWaitSemaphores,
3819 pBindInfo[i].signalSemaphoreCount,
3820 pBindInfo[i].pSignalSemaphores,
3821 _fence);
3822 if (result != VK_SUCCESS)
3823 return result;
3824
3825 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3826 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3827 &queue->device->empty_cs[queue->queue_family_index],
3828 1, NULL, NULL,
3829 &sem_info, NULL,
3830 false, base_fence);
3831 if (ret) {
3832 radv_loge("failed to submit CS %d\n", i);
3833 abort();
3834 }
3835
3836 fence_emitted = true;
3837 }
3838
3839 radv_free_sem_info(&sem_info);
3840
3841 }
3842
3843 if (fence) {
3844 if (!fence_emitted) {
3845 result = radv_signal_fence(queue, fence);
3846 if (result != VK_SUCCESS)
3847 return result;
3848 }
3849 }
3850
3851 return VK_SUCCESS;
3852 }
3853
3854 VkResult radv_CreateFence(
3855 VkDevice _device,
3856 const VkFenceCreateInfo* pCreateInfo,
3857 const VkAllocationCallbacks* pAllocator,
3858 VkFence* pFence)
3859 {
3860 RADV_FROM_HANDLE(radv_device, device, _device);
3861 const VkExportFenceCreateInfo *export =
3862 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3863 VkExternalFenceHandleTypeFlags handleTypes =
3864 export ? export->handleTypes : 0;
3865
3866 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3867 sizeof(*fence), 8,
3868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3869
3870 if (!fence)
3871 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3872
3873 fence->fence_wsi = NULL;
3874 fence->temp_syncobj = 0;
3875 if (device->always_use_syncobj || handleTypes) {
3876 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3877 if (ret) {
3878 vk_free2(&device->alloc, pAllocator, fence);
3879 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3880 }
3881 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3882 device->ws->signal_syncobj(device->ws, fence->syncobj);
3883 }
3884 fence->fence = NULL;
3885 } else {
3886 fence->fence = device->ws->create_fence();
3887 if (!fence->fence) {
3888 vk_free2(&device->alloc, pAllocator, fence);
3889 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3890 }
3891 fence->syncobj = 0;
3892 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3893 device->ws->signal_fence(fence->fence);
3894 }
3895
3896 *pFence = radv_fence_to_handle(fence);
3897
3898 return VK_SUCCESS;
3899 }
3900
3901 void radv_DestroyFence(
3902 VkDevice _device,
3903 VkFence _fence,
3904 const VkAllocationCallbacks* pAllocator)
3905 {
3906 RADV_FROM_HANDLE(radv_device, device, _device);
3907 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3908
3909 if (!fence)
3910 return;
3911
3912 if (fence->temp_syncobj)
3913 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3914 if (fence->syncobj)
3915 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3916 if (fence->fence)
3917 device->ws->destroy_fence(fence->fence);
3918 if (fence->fence_wsi)
3919 fence->fence_wsi->destroy(fence->fence_wsi);
3920 vk_free2(&device->alloc, pAllocator, fence);
3921 }
3922
3923
3924 uint64_t radv_get_current_time(void)
3925 {
3926 struct timespec tv;
3927 clock_gettime(CLOCK_MONOTONIC, &tv);
3928 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3929 }
3930
3931 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3932 {
3933 uint64_t current_time = radv_get_current_time();
3934
3935 timeout = MIN2(UINT64_MAX - current_time, timeout);
3936
3937 return current_time + timeout;
3938 }
3939
3940
3941 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3942 uint32_t fenceCount, const VkFence *pFences)
3943 {
3944 for (uint32_t i = 0; i < fenceCount; ++i) {
3945 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3946 if (fence->fence == NULL || fence->syncobj ||
3947 fence->temp_syncobj || fence->fence_wsi ||
3948 (!device->ws->is_fence_waitable(fence->fence)))
3949 return false;
3950 }
3951 return true;
3952 }
3953
3954 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3955 {
3956 for (uint32_t i = 0; i < fenceCount; ++i) {
3957 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3958 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3959 return false;
3960 }
3961 return true;
3962 }
3963
3964 VkResult radv_WaitForFences(
3965 VkDevice _device,
3966 uint32_t fenceCount,
3967 const VkFence* pFences,
3968 VkBool32 waitAll,
3969 uint64_t timeout)
3970 {
3971 RADV_FROM_HANDLE(radv_device, device, _device);
3972 timeout = radv_get_absolute_timeout(timeout);
3973
3974 if (device->always_use_syncobj &&
3975 radv_all_fences_syncobj(fenceCount, pFences))
3976 {
3977 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3978 if (!handles)
3979 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3980
3981 for (uint32_t i = 0; i < fenceCount; ++i) {
3982 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3983 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3984 }
3985
3986 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3987
3988 free(handles);
3989 return success ? VK_SUCCESS : VK_TIMEOUT;
3990 }
3991
3992 if (!waitAll && fenceCount > 1) {
3993 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3994 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3995 uint32_t wait_count = 0;
3996 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3997 if (!fences)
3998 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3999
4000 for (uint32_t i = 0; i < fenceCount; ++i) {
4001 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4002
4003 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
4004 free(fences);
4005 return VK_SUCCESS;
4006 }
4007
4008 fences[wait_count++] = fence->fence;
4009 }
4010
4011 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
4012 waitAll, timeout - radv_get_current_time());
4013
4014 free(fences);
4015 return success ? VK_SUCCESS : VK_TIMEOUT;
4016 }
4017
4018 while(radv_get_current_time() <= timeout) {
4019 for (uint32_t i = 0; i < fenceCount; ++i) {
4020 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
4021 return VK_SUCCESS;
4022 }
4023 }
4024 return VK_TIMEOUT;
4025 }
4026
4027 for (uint32_t i = 0; i < fenceCount; ++i) {
4028 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4029 bool expired = false;
4030
4031 if (fence->temp_syncobj) {
4032 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4033 return VK_TIMEOUT;
4034 continue;
4035 }
4036
4037 if (fence->syncobj) {
4038 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4039 return VK_TIMEOUT;
4040 continue;
4041 }
4042
4043 if (fence->fence) {
4044 if (!device->ws->is_fence_waitable(fence->fence)) {
4045 while(!device->ws->is_fence_waitable(fence->fence) &&
4046 radv_get_current_time() <= timeout)
4047 /* Do nothing */;
4048 }
4049
4050 expired = device->ws->fence_wait(device->ws,
4051 fence->fence,
4052 true, timeout);
4053 if (!expired)
4054 return VK_TIMEOUT;
4055 }
4056
4057 if (fence->fence_wsi) {
4058 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4059 if (result != VK_SUCCESS)
4060 return result;
4061 }
4062 }
4063
4064 return VK_SUCCESS;
4065 }
4066
4067 VkResult radv_ResetFences(VkDevice _device,
4068 uint32_t fenceCount,
4069 const VkFence *pFences)
4070 {
4071 RADV_FROM_HANDLE(radv_device, device, _device);
4072
4073 for (unsigned i = 0; i < fenceCount; ++i) {
4074 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4075 if (fence->fence)
4076 device->ws->reset_fence(fence->fence);
4077
4078 /* Per spec, we first restore the permanent payload, and then reset, so
4079 * having a temp syncobj should not skip resetting the permanent syncobj. */
4080 if (fence->temp_syncobj) {
4081 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4082 fence->temp_syncobj = 0;
4083 }
4084
4085 if (fence->syncobj) {
4086 device->ws->reset_syncobj(device->ws, fence->syncobj);
4087 }
4088 }
4089
4090 return VK_SUCCESS;
4091 }
4092
4093 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4094 {
4095 RADV_FROM_HANDLE(radv_device, device, _device);
4096 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4097
4098 if (fence->temp_syncobj) {
4099 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4100 return success ? VK_SUCCESS : VK_NOT_READY;
4101 }
4102
4103 if (fence->syncobj) {
4104 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4105 return success ? VK_SUCCESS : VK_NOT_READY;
4106 }
4107
4108 if (fence->fence) {
4109 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4110 return VK_NOT_READY;
4111 }
4112 if (fence->fence_wsi) {
4113 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4114
4115 if (result != VK_SUCCESS) {
4116 if (result == VK_TIMEOUT)
4117 return VK_NOT_READY;
4118 return result;
4119 }
4120 }
4121 return VK_SUCCESS;
4122 }
4123
4124
4125 // Queue semaphore functions
4126
4127 VkResult radv_CreateSemaphore(
4128 VkDevice _device,
4129 const VkSemaphoreCreateInfo* pCreateInfo,
4130 const VkAllocationCallbacks* pAllocator,
4131 VkSemaphore* pSemaphore)
4132 {
4133 RADV_FROM_HANDLE(radv_device, device, _device);
4134 const VkExportSemaphoreCreateInfo *export =
4135 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4136 VkExternalSemaphoreHandleTypeFlags handleTypes =
4137 export ? export->handleTypes : 0;
4138
4139 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4140 sizeof(*sem), 8,
4141 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4142 if (!sem)
4143 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4144
4145 sem->temp_syncobj = 0;
4146 /* create a syncobject if we are going to export this semaphore */
4147 if (device->always_use_syncobj || handleTypes) {
4148 assert (device->physical_device->rad_info.has_syncobj);
4149 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4150 if (ret) {
4151 vk_free2(&device->alloc, pAllocator, sem);
4152 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4153 }
4154 sem->sem = NULL;
4155 } else {
4156 sem->sem = device->ws->create_sem(device->ws);
4157 if (!sem->sem) {
4158 vk_free2(&device->alloc, pAllocator, sem);
4159 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4160 }
4161 sem->syncobj = 0;
4162 }
4163
4164 *pSemaphore = radv_semaphore_to_handle(sem);
4165 return VK_SUCCESS;
4166 }
4167
4168 void radv_DestroySemaphore(
4169 VkDevice _device,
4170 VkSemaphore _semaphore,
4171 const VkAllocationCallbacks* pAllocator)
4172 {
4173 RADV_FROM_HANDLE(radv_device, device, _device);
4174 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4175 if (!_semaphore)
4176 return;
4177
4178 if (sem->syncobj)
4179 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4180 else
4181 device->ws->destroy_sem(sem->sem);
4182 vk_free2(&device->alloc, pAllocator, sem);
4183 }
4184
4185 VkResult radv_CreateEvent(
4186 VkDevice _device,
4187 const VkEventCreateInfo* pCreateInfo,
4188 const VkAllocationCallbacks* pAllocator,
4189 VkEvent* pEvent)
4190 {
4191 RADV_FROM_HANDLE(radv_device, device, _device);
4192 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4193 sizeof(*event), 8,
4194 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4195
4196 if (!event)
4197 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4198
4199 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4200 RADEON_DOMAIN_GTT,
4201 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4202 RADV_BO_PRIORITY_FENCE);
4203 if (!event->bo) {
4204 vk_free2(&device->alloc, pAllocator, event);
4205 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4206 }
4207
4208 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4209
4210 *pEvent = radv_event_to_handle(event);
4211
4212 return VK_SUCCESS;
4213 }
4214
4215 void radv_DestroyEvent(
4216 VkDevice _device,
4217 VkEvent _event,
4218 const VkAllocationCallbacks* pAllocator)
4219 {
4220 RADV_FROM_HANDLE(radv_device, device, _device);
4221 RADV_FROM_HANDLE(radv_event, event, _event);
4222
4223 if (!event)
4224 return;
4225 device->ws->buffer_destroy(event->bo);
4226 vk_free2(&device->alloc, pAllocator, event);
4227 }
4228
4229 VkResult radv_GetEventStatus(
4230 VkDevice _device,
4231 VkEvent _event)
4232 {
4233 RADV_FROM_HANDLE(radv_event, event, _event);
4234
4235 if (*event->map == 1)
4236 return VK_EVENT_SET;
4237 return VK_EVENT_RESET;
4238 }
4239
4240 VkResult radv_SetEvent(
4241 VkDevice _device,
4242 VkEvent _event)
4243 {
4244 RADV_FROM_HANDLE(radv_event, event, _event);
4245 *event->map = 1;
4246
4247 return VK_SUCCESS;
4248 }
4249
4250 VkResult radv_ResetEvent(
4251 VkDevice _device,
4252 VkEvent _event)
4253 {
4254 RADV_FROM_HANDLE(radv_event, event, _event);
4255 *event->map = 0;
4256
4257 return VK_SUCCESS;
4258 }
4259
4260 VkResult radv_CreateBuffer(
4261 VkDevice _device,
4262 const VkBufferCreateInfo* pCreateInfo,
4263 const VkAllocationCallbacks* pAllocator,
4264 VkBuffer* pBuffer)
4265 {
4266 RADV_FROM_HANDLE(radv_device, device, _device);
4267 struct radv_buffer *buffer;
4268
4269 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4270
4271 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4272 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4273 if (buffer == NULL)
4274 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4275
4276 buffer->size = pCreateInfo->size;
4277 buffer->usage = pCreateInfo->usage;
4278 buffer->bo = NULL;
4279 buffer->offset = 0;
4280 buffer->flags = pCreateInfo->flags;
4281
4282 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4283 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4284
4285 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4286 buffer->bo = device->ws->buffer_create(device->ws,
4287 align64(buffer->size, 4096),
4288 4096, 0, RADEON_FLAG_VIRTUAL,
4289 RADV_BO_PRIORITY_VIRTUAL);
4290 if (!buffer->bo) {
4291 vk_free2(&device->alloc, pAllocator, buffer);
4292 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4293 }
4294 }
4295
4296 *pBuffer = radv_buffer_to_handle(buffer);
4297
4298 return VK_SUCCESS;
4299 }
4300
4301 void radv_DestroyBuffer(
4302 VkDevice _device,
4303 VkBuffer _buffer,
4304 const VkAllocationCallbacks* pAllocator)
4305 {
4306 RADV_FROM_HANDLE(radv_device, device, _device);
4307 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4308
4309 if (!buffer)
4310 return;
4311
4312 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4313 device->ws->buffer_destroy(buffer->bo);
4314
4315 vk_free2(&device->alloc, pAllocator, buffer);
4316 }
4317
4318 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4319 VkDevice device,
4320 const VkBufferDeviceAddressInfoEXT* pInfo)
4321 {
4322 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4323 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4324 }
4325
4326
4327 static inline unsigned
4328 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4329 {
4330 if (stencil)
4331 return plane->surface.u.legacy.stencil_tiling_index[level];
4332 else
4333 return plane->surface.u.legacy.tiling_index[level];
4334 }
4335
4336 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4337 {
4338 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4339 }
4340
4341 static uint32_t
4342 radv_init_dcc_control_reg(struct radv_device *device,
4343 struct radv_image_view *iview)
4344 {
4345 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4346 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4347 unsigned max_compressed_block_size;
4348 unsigned independent_128b_blocks;
4349 unsigned independent_64b_blocks;
4350
4351 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4352 return 0;
4353
4354 if (!device->physical_device->rad_info.has_dedicated_vram) {
4355 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4356 * dGPU and 64 for APU because all of our APUs to date use
4357 * DIMMs which have a request granularity size of 64B while all
4358 * other chips have a 32B request size.
4359 */
4360 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4361 }
4362
4363 if (device->physical_device->rad_info.chip_class >= GFX10) {
4364 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4365 independent_64b_blocks = 0;
4366 independent_128b_blocks = 1;
4367 } else {
4368 independent_128b_blocks = 0;
4369
4370 if (iview->image->info.samples > 1) {
4371 if (iview->image->planes[0].surface.bpe == 1)
4372 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4373 else if (iview->image->planes[0].surface.bpe == 2)
4374 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4375 }
4376
4377 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4378 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4379 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4380 /* If this DCC image is potentially going to be used in texture
4381 * fetches, we need some special settings.
4382 */
4383 independent_64b_blocks = 1;
4384 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4385 } else {
4386 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4387 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4388 * big as possible for better compression state.
4389 */
4390 independent_64b_blocks = 0;
4391 max_compressed_block_size = max_uncompressed_block_size;
4392 }
4393 }
4394
4395 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4396 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4397 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4398 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4399 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4400 }
4401
4402 void
4403 radv_initialise_color_surface(struct radv_device *device,
4404 struct radv_color_buffer_info *cb,
4405 struct radv_image_view *iview)
4406 {
4407 const struct vk_format_description *desc;
4408 unsigned ntype, format, swap, endian;
4409 unsigned blend_clamp = 0, blend_bypass = 0;
4410 uint64_t va;
4411 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4412 const struct radeon_surf *surf = &plane->surface;
4413
4414 desc = vk_format_description(iview->vk_format);
4415
4416 memset(cb, 0, sizeof(*cb));
4417
4418 /* Intensity is implemented as Red, so treat it that way. */
4419 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4420
4421 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4422
4423 cb->cb_color_base = va >> 8;
4424
4425 if (device->physical_device->rad_info.chip_class >= GFX9) {
4426 struct gfx9_surf_meta_flags meta;
4427 if (iview->image->dcc_offset)
4428 meta = surf->u.gfx9.dcc;
4429 else
4430 meta = surf->u.gfx9.cmask;
4431
4432 if (device->physical_device->rad_info.chip_class >= GFX10) {
4433 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4434 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4435 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4436 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4437 } else {
4438 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4439 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4440 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4441 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4442 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4443 }
4444
4445 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4446 cb->cb_color_base |= surf->tile_swizzle;
4447 } else {
4448 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4449 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4450
4451 cb->cb_color_base += level_info->offset >> 8;
4452 if (level_info->mode == RADEON_SURF_MODE_2D)
4453 cb->cb_color_base |= surf->tile_swizzle;
4454
4455 pitch_tile_max = level_info->nblk_x / 8 - 1;
4456 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4457 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4458
4459 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4460 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4461 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4462
4463 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4464
4465 if (radv_image_has_fmask(iview->image)) {
4466 if (device->physical_device->rad_info.chip_class >= GFX7)
4467 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4468 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4469 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4470 } else {
4471 /* This must be set for fast clear to work without FMASK. */
4472 if (device->physical_device->rad_info.chip_class >= GFX7)
4473 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4474 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4475 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4476 }
4477 }
4478
4479 /* CMASK variables */
4480 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4481 va += iview->image->cmask_offset;
4482 cb->cb_color_cmask = va >> 8;
4483
4484 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4485 va += iview->image->dcc_offset;
4486
4487 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4488 device->physical_device->rad_info.chip_class <= GFX8)
4489 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4490
4491 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4492 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4493
4494 cb->cb_dcc_base = va >> 8;
4495 cb->cb_dcc_base |= dcc_tile_swizzle;
4496
4497 /* GFX10 field has the same base shift as the GFX6 field. */
4498 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4499 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4500 S_028C6C_SLICE_MAX_GFX10(max_slice);
4501
4502 if (iview->image->info.samples > 1) {
4503 unsigned log_samples = util_logbase2(iview->image->info.samples);
4504
4505 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4506 S_028C74_NUM_FRAGMENTS(log_samples);
4507 }
4508
4509 if (radv_image_has_fmask(iview->image)) {
4510 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4511 cb->cb_color_fmask = va >> 8;
4512 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4513 } else {
4514 cb->cb_color_fmask = cb->cb_color_base;
4515 }
4516
4517 ntype = radv_translate_color_numformat(iview->vk_format,
4518 desc,
4519 vk_format_get_first_non_void_channel(iview->vk_format));
4520 format = radv_translate_colorformat(iview->vk_format);
4521 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4522 radv_finishme("Illegal color\n");
4523 swap = radv_translate_colorswap(iview->vk_format, false);
4524 endian = radv_colorformat_endian_swap(format);
4525
4526 /* blend clamp should be set for all NORM/SRGB types */
4527 if (ntype == V_028C70_NUMBER_UNORM ||
4528 ntype == V_028C70_NUMBER_SNORM ||
4529 ntype == V_028C70_NUMBER_SRGB)
4530 blend_clamp = 1;
4531
4532 /* set blend bypass according to docs if SINT/UINT or
4533 8/24 COLOR variants */
4534 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4535 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4536 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4537 blend_clamp = 0;
4538 blend_bypass = 1;
4539 }
4540 #if 0
4541 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4542 (format == V_028C70_COLOR_8 ||
4543 format == V_028C70_COLOR_8_8 ||
4544 format == V_028C70_COLOR_8_8_8_8))
4545 ->color_is_int8 = true;
4546 #endif
4547 cb->cb_color_info = S_028C70_FORMAT(format) |
4548 S_028C70_COMP_SWAP(swap) |
4549 S_028C70_BLEND_CLAMP(blend_clamp) |
4550 S_028C70_BLEND_BYPASS(blend_bypass) |
4551 S_028C70_SIMPLE_FLOAT(1) |
4552 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4553 ntype != V_028C70_NUMBER_SNORM &&
4554 ntype != V_028C70_NUMBER_SRGB &&
4555 format != V_028C70_COLOR_8_24 &&
4556 format != V_028C70_COLOR_24_8) |
4557 S_028C70_NUMBER_TYPE(ntype) |
4558 S_028C70_ENDIAN(endian);
4559 if (radv_image_has_fmask(iview->image)) {
4560 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4561 if (device->physical_device->rad_info.chip_class == GFX6) {
4562 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4563 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4564 }
4565
4566 if (radv_image_is_tc_compat_cmask(iview->image)) {
4567 /* Allow the texture block to read FMASK directly
4568 * without decompressing it. This bit must be cleared
4569 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4570 * otherwise the operation doesn't happen.
4571 */
4572 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4573
4574 /* Set CMASK into a tiling format that allows the
4575 * texture block to read it.
4576 */
4577 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4578 }
4579 }
4580
4581 if (radv_image_has_cmask(iview->image) &&
4582 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4583 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4584
4585 if (radv_dcc_enabled(iview->image, iview->base_mip))
4586 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4587
4588 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4589
4590 /* This must be set for fast clear to work without FMASK. */
4591 if (!radv_image_has_fmask(iview->image) &&
4592 device->physical_device->rad_info.chip_class == GFX6) {
4593 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4594 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4595 }
4596
4597 if (device->physical_device->rad_info.chip_class >= GFX9) {
4598 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4599
4600 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4601 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4602 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4603 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4604
4605 if (device->physical_device->rad_info.chip_class >= GFX10) {
4606 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4607
4608 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4609 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4610 S_028EE0_RESOURCE_LEVEL(1);
4611 } else {
4612 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4613 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4614 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4615 }
4616
4617 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4618 S_028C68_MIP0_HEIGHT(height - 1) |
4619 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4620 }
4621 }
4622
4623 static unsigned
4624 radv_calc_decompress_on_z_planes(struct radv_device *device,
4625 struct radv_image_view *iview)
4626 {
4627 unsigned max_zplanes = 0;
4628
4629 assert(radv_image_is_tc_compat_htile(iview->image));
4630
4631 if (device->physical_device->rad_info.chip_class >= GFX9) {
4632 /* Default value for 32-bit depth surfaces. */
4633 max_zplanes = 4;
4634
4635 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4636 iview->image->info.samples > 1)
4637 max_zplanes = 2;
4638
4639 max_zplanes = max_zplanes + 1;
4640 } else {
4641 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4642 /* Do not enable Z plane compression for 16-bit depth
4643 * surfaces because isn't supported on GFX8. Only
4644 * 32-bit depth surfaces are supported by the hardware.
4645 * This allows to maintain shader compatibility and to
4646 * reduce the number of depth decompressions.
4647 */
4648 max_zplanes = 1;
4649 } else {
4650 if (iview->image->info.samples <= 1)
4651 max_zplanes = 5;
4652 else if (iview->image->info.samples <= 4)
4653 max_zplanes = 3;
4654 else
4655 max_zplanes = 2;
4656 }
4657 }
4658
4659 return max_zplanes;
4660 }
4661
4662 void
4663 radv_initialise_ds_surface(struct radv_device *device,
4664 struct radv_ds_buffer_info *ds,
4665 struct radv_image_view *iview)
4666 {
4667 unsigned level = iview->base_mip;
4668 unsigned format, stencil_format;
4669 uint64_t va, s_offs, z_offs;
4670 bool stencil_only = false;
4671 const struct radv_image_plane *plane = &iview->image->planes[0];
4672 const struct radeon_surf *surf = &plane->surface;
4673
4674 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4675
4676 memset(ds, 0, sizeof(*ds));
4677 switch (iview->image->vk_format) {
4678 case VK_FORMAT_D24_UNORM_S8_UINT:
4679 case VK_FORMAT_X8_D24_UNORM_PACK32:
4680 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4681 ds->offset_scale = 2.0f;
4682 break;
4683 case VK_FORMAT_D16_UNORM:
4684 case VK_FORMAT_D16_UNORM_S8_UINT:
4685 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4686 ds->offset_scale = 4.0f;
4687 break;
4688 case VK_FORMAT_D32_SFLOAT:
4689 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4690 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4691 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4692 ds->offset_scale = 1.0f;
4693 break;
4694 case VK_FORMAT_S8_UINT:
4695 stencil_only = true;
4696 break;
4697 default:
4698 break;
4699 }
4700
4701 format = radv_translate_dbformat(iview->image->vk_format);
4702 stencil_format = surf->has_stencil ?
4703 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4704
4705 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4706 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4707 S_028008_SLICE_MAX(max_slice);
4708 if (device->physical_device->rad_info.chip_class >= GFX10) {
4709 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4710 S_028008_SLICE_MAX_HI(max_slice >> 11);
4711 }
4712
4713 ds->db_htile_data_base = 0;
4714 ds->db_htile_surface = 0;
4715
4716 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4717 s_offs = z_offs = va;
4718
4719 if (device->physical_device->rad_info.chip_class >= GFX9) {
4720 assert(surf->u.gfx9.surf_offset == 0);
4721 s_offs += surf->u.gfx9.stencil_offset;
4722
4723 ds->db_z_info = S_028038_FORMAT(format) |
4724 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4725 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4726 S_028038_MAXMIP(iview->image->info.levels - 1) |
4727 S_028038_ZRANGE_PRECISION(1);
4728 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4729 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4730
4731 if (device->physical_device->rad_info.chip_class == GFX9) {
4732 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4733 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4734 }
4735
4736 ds->db_depth_view |= S_028008_MIPID(level);
4737 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4738 S_02801C_Y_MAX(iview->image->info.height - 1);
4739
4740 if (radv_htile_enabled(iview->image, level)) {
4741 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4742
4743 if (radv_image_is_tc_compat_htile(iview->image)) {
4744 unsigned max_zplanes =
4745 radv_calc_decompress_on_z_planes(device, iview);
4746
4747 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4748
4749 if (device->physical_device->rad_info.chip_class >= GFX10) {
4750 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4751 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4752 } else {
4753 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4754 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4755 }
4756 }
4757
4758 if (!surf->has_stencil)
4759 /* Use all of the htile_buffer for depth if there's no stencil. */
4760 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4761 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4762 iview->image->htile_offset;
4763 ds->db_htile_data_base = va >> 8;
4764 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4765 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4766
4767 if (device->physical_device->rad_info.chip_class == GFX9) {
4768 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4769 }
4770 }
4771 } else {
4772 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4773
4774 if (stencil_only)
4775 level_info = &surf->u.legacy.stencil_level[level];
4776
4777 z_offs += surf->u.legacy.level[level].offset;
4778 s_offs += surf->u.legacy.stencil_level[level].offset;
4779
4780 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4781 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4782 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4783
4784 if (iview->image->info.samples > 1)
4785 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4786
4787 if (device->physical_device->rad_info.chip_class >= GFX7) {
4788 struct radeon_info *info = &device->physical_device->rad_info;
4789 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4790 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4791 unsigned macro_index = surf->u.legacy.macro_tile_index;
4792 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4793 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4794 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4795
4796 if (stencil_only)
4797 tile_mode = stencil_tile_mode;
4798
4799 ds->db_depth_info |=
4800 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4801 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4802 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4803 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4804 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4805 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4806 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4807 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4808 } else {
4809 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4810 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4811 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4812 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4813 if (stencil_only)
4814 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4815 }
4816
4817 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4818 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4819 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4820
4821 if (radv_htile_enabled(iview->image, level)) {
4822 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4823
4824 if (!surf->has_stencil &&
4825 !radv_image_is_tc_compat_htile(iview->image))
4826 /* Use all of the htile_buffer for depth if there's no stencil. */
4827 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4828
4829 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4830 iview->image->htile_offset;
4831 ds->db_htile_data_base = va >> 8;
4832 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4833
4834 if (radv_image_is_tc_compat_htile(iview->image)) {
4835 unsigned max_zplanes =
4836 radv_calc_decompress_on_z_planes(device, iview);
4837
4838 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4839 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4840 }
4841 }
4842 }
4843
4844 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4845 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4846 }
4847
4848 VkResult radv_CreateFramebuffer(
4849 VkDevice _device,
4850 const VkFramebufferCreateInfo* pCreateInfo,
4851 const VkAllocationCallbacks* pAllocator,
4852 VkFramebuffer* pFramebuffer)
4853 {
4854 RADV_FROM_HANDLE(radv_device, device, _device);
4855 struct radv_framebuffer *framebuffer;
4856 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4857 vk_find_struct_const(pCreateInfo->pNext,
4858 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4859
4860 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4861
4862 size_t size = sizeof(*framebuffer);
4863 if (!imageless_create_info)
4864 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4865 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4866 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4867 if (framebuffer == NULL)
4868 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4869
4870 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4871 framebuffer->width = pCreateInfo->width;
4872 framebuffer->height = pCreateInfo->height;
4873 framebuffer->layers = pCreateInfo->layers;
4874 if (imageless_create_info) {
4875 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4876 const VkFramebufferAttachmentImageInfoKHR *attachment =
4877 imageless_create_info->pAttachmentImageInfos + i;
4878 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4879 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4880 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4881 }
4882 } else {
4883 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4884 VkImageView _iview = pCreateInfo->pAttachments[i];
4885 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4886 framebuffer->attachments[i] = iview;
4887 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4888 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4889 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4890 }
4891 }
4892
4893 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4894 return VK_SUCCESS;
4895 }
4896
4897 void radv_DestroyFramebuffer(
4898 VkDevice _device,
4899 VkFramebuffer _fb,
4900 const VkAllocationCallbacks* pAllocator)
4901 {
4902 RADV_FROM_HANDLE(radv_device, device, _device);
4903 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4904
4905 if (!fb)
4906 return;
4907 vk_free2(&device->alloc, pAllocator, fb);
4908 }
4909
4910 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4911 {
4912 switch (address_mode) {
4913 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4914 return V_008F30_SQ_TEX_WRAP;
4915 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4916 return V_008F30_SQ_TEX_MIRROR;
4917 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4918 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4919 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4920 return V_008F30_SQ_TEX_CLAMP_BORDER;
4921 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4922 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4923 default:
4924 unreachable("illegal tex wrap mode");
4925 break;
4926 }
4927 }
4928
4929 static unsigned
4930 radv_tex_compare(VkCompareOp op)
4931 {
4932 switch (op) {
4933 case VK_COMPARE_OP_NEVER:
4934 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4935 case VK_COMPARE_OP_LESS:
4936 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4937 case VK_COMPARE_OP_EQUAL:
4938 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4939 case VK_COMPARE_OP_LESS_OR_EQUAL:
4940 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4941 case VK_COMPARE_OP_GREATER:
4942 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4943 case VK_COMPARE_OP_NOT_EQUAL:
4944 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4945 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4946 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4947 case VK_COMPARE_OP_ALWAYS:
4948 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4949 default:
4950 unreachable("illegal compare mode");
4951 break;
4952 }
4953 }
4954
4955 static unsigned
4956 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4957 {
4958 switch (filter) {
4959 case VK_FILTER_NEAREST:
4960 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4961 V_008F38_SQ_TEX_XY_FILTER_POINT);
4962 case VK_FILTER_LINEAR:
4963 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4964 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4965 case VK_FILTER_CUBIC_IMG:
4966 default:
4967 fprintf(stderr, "illegal texture filter");
4968 return 0;
4969 }
4970 }
4971
4972 static unsigned
4973 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4974 {
4975 switch (mode) {
4976 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4977 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4978 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4979 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4980 default:
4981 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4982 }
4983 }
4984
4985 static unsigned
4986 radv_tex_bordercolor(VkBorderColor bcolor)
4987 {
4988 switch (bcolor) {
4989 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4990 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4991 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4992 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4993 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4994 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4995 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4996 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4997 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4998 default:
4999 break;
5000 }
5001 return 0;
5002 }
5003
5004 static unsigned
5005 radv_tex_aniso_filter(unsigned filter)
5006 {
5007 if (filter < 2)
5008 return 0;
5009 if (filter < 4)
5010 return 1;
5011 if (filter < 8)
5012 return 2;
5013 if (filter < 16)
5014 return 3;
5015 return 4;
5016 }
5017
5018 static unsigned
5019 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
5020 {
5021 switch (mode) {
5022 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
5023 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5024 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5025 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5026 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5027 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5028 default:
5029 break;
5030 }
5031 return 0;
5032 }
5033
5034 static uint32_t
5035 radv_get_max_anisotropy(struct radv_device *device,
5036 const VkSamplerCreateInfo *pCreateInfo)
5037 {
5038 if (device->force_aniso >= 0)
5039 return device->force_aniso;
5040
5041 if (pCreateInfo->anisotropyEnable &&
5042 pCreateInfo->maxAnisotropy > 1.0f)
5043 return (uint32_t)pCreateInfo->maxAnisotropy;
5044
5045 return 0;
5046 }
5047
5048 static void
5049 radv_init_sampler(struct radv_device *device,
5050 struct radv_sampler *sampler,
5051 const VkSamplerCreateInfo *pCreateInfo)
5052 {
5053 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5054 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5055 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5056 device->physical_device->rad_info.chip_class == GFX9;
5057 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5058
5059 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5060 vk_find_struct_const(pCreateInfo->pNext,
5061 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5062 if (sampler_reduction)
5063 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5064
5065 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5066 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5067 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5068 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5069 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5070 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5071 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5072 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5073 S_008F30_DISABLE_CUBE_WRAP(0) |
5074 S_008F30_COMPAT_MODE(compat_mode) |
5075 S_008F30_FILTER_MODE(filter_mode));
5076 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5077 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5078 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5079 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5080 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5081 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5082 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5083 S_008F38_MIP_POINT_PRECLAMP(0));
5084 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5085 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5086
5087 if (device->physical_device->rad_info.chip_class >= GFX10) {
5088 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5089 } else {
5090 sampler->state[2] |=
5091 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5092 S_008F38_FILTER_PREC_FIX(1) |
5093 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5094 }
5095 }
5096
5097 VkResult radv_CreateSampler(
5098 VkDevice _device,
5099 const VkSamplerCreateInfo* pCreateInfo,
5100 const VkAllocationCallbacks* pAllocator,
5101 VkSampler* pSampler)
5102 {
5103 RADV_FROM_HANDLE(radv_device, device, _device);
5104 struct radv_sampler *sampler;
5105
5106 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5107 vk_find_struct_const(pCreateInfo->pNext,
5108 SAMPLER_YCBCR_CONVERSION_INFO);
5109
5110 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5111
5112 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5113 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5114 if (!sampler)
5115 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5116
5117 radv_init_sampler(device, sampler, pCreateInfo);
5118
5119 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5120 *pSampler = radv_sampler_to_handle(sampler);
5121
5122 return VK_SUCCESS;
5123 }
5124
5125 void radv_DestroySampler(
5126 VkDevice _device,
5127 VkSampler _sampler,
5128 const VkAllocationCallbacks* pAllocator)
5129 {
5130 RADV_FROM_HANDLE(radv_device, device, _device);
5131 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5132
5133 if (!sampler)
5134 return;
5135 vk_free2(&device->alloc, pAllocator, sampler);
5136 }
5137
5138 /* vk_icd.h does not declare this function, so we declare it here to
5139 * suppress Wmissing-prototypes.
5140 */
5141 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5142 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5143
5144 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5145 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5146 {
5147 /* For the full details on loader interface versioning, see
5148 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5149 * What follows is a condensed summary, to help you navigate the large and
5150 * confusing official doc.
5151 *
5152 * - Loader interface v0 is incompatible with later versions. We don't
5153 * support it.
5154 *
5155 * - In loader interface v1:
5156 * - The first ICD entrypoint called by the loader is
5157 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5158 * entrypoint.
5159 * - The ICD must statically expose no other Vulkan symbol unless it is
5160 * linked with -Bsymbolic.
5161 * - Each dispatchable Vulkan handle created by the ICD must be
5162 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5163 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5164 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5165 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5166 * such loader-managed surfaces.
5167 *
5168 * - Loader interface v2 differs from v1 in:
5169 * - The first ICD entrypoint called by the loader is
5170 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5171 * statically expose this entrypoint.
5172 *
5173 * - Loader interface v3 differs from v2 in:
5174 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5175 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5176 * because the loader no longer does so.
5177 */
5178 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5179 return VK_SUCCESS;
5180 }
5181
5182 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5183 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5184 int *pFD)
5185 {
5186 RADV_FROM_HANDLE(radv_device, device, _device);
5187 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5188
5189 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5190
5191 /* At the moment, we support only the below handle types. */
5192 assert(pGetFdInfo->handleType ==
5193 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5194 pGetFdInfo->handleType ==
5195 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5196
5197 bool ret = radv_get_memory_fd(device, memory, pFD);
5198 if (ret == false)
5199 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5200 return VK_SUCCESS;
5201 }
5202
5203 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5204 VkExternalMemoryHandleTypeFlagBits handleType,
5205 int fd,
5206 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5207 {
5208 RADV_FROM_HANDLE(radv_device, device, _device);
5209
5210 switch (handleType) {
5211 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5212 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5213 return VK_SUCCESS;
5214
5215 default:
5216 /* The valid usage section for this function says:
5217 *
5218 * "handleType must not be one of the handle types defined as
5219 * opaque."
5220 *
5221 * So opaque handle types fall into the default "unsupported" case.
5222 */
5223 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5224 }
5225 }
5226
5227 static VkResult radv_import_opaque_fd(struct radv_device *device,
5228 int fd,
5229 uint32_t *syncobj)
5230 {
5231 uint32_t syncobj_handle = 0;
5232 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5233 if (ret != 0)
5234 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5235
5236 if (*syncobj)
5237 device->ws->destroy_syncobj(device->ws, *syncobj);
5238
5239 *syncobj = syncobj_handle;
5240 close(fd);
5241
5242 return VK_SUCCESS;
5243 }
5244
5245 static VkResult radv_import_sync_fd(struct radv_device *device,
5246 int fd,
5247 uint32_t *syncobj)
5248 {
5249 /* If we create a syncobj we do it locally so that if we have an error, we don't
5250 * leave a syncobj in an undetermined state in the fence. */
5251 uint32_t syncobj_handle = *syncobj;
5252 if (!syncobj_handle) {
5253 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5254 if (ret) {
5255 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5256 }
5257 }
5258
5259 if (fd == -1) {
5260 device->ws->signal_syncobj(device->ws, syncobj_handle);
5261 } else {
5262 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5263 if (ret != 0)
5264 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5265 }
5266
5267 *syncobj = syncobj_handle;
5268 if (fd != -1)
5269 close(fd);
5270
5271 return VK_SUCCESS;
5272 }
5273
5274 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5275 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5276 {
5277 RADV_FROM_HANDLE(radv_device, device, _device);
5278 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5279 uint32_t *syncobj_dst = NULL;
5280
5281 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5282 syncobj_dst = &sem->temp_syncobj;
5283 } else {
5284 syncobj_dst = &sem->syncobj;
5285 }
5286
5287 switch(pImportSemaphoreFdInfo->handleType) {
5288 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5289 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5290 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5291 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5292 default:
5293 unreachable("Unhandled semaphore handle type");
5294 }
5295 }
5296
5297 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5298 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5299 int *pFd)
5300 {
5301 RADV_FROM_HANDLE(radv_device, device, _device);
5302 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5303 int ret;
5304 uint32_t syncobj_handle;
5305
5306 if (sem->temp_syncobj)
5307 syncobj_handle = sem->temp_syncobj;
5308 else
5309 syncobj_handle = sem->syncobj;
5310
5311 switch(pGetFdInfo->handleType) {
5312 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5313 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5314 break;
5315 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5316 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5317 if (!ret) {
5318 if (sem->temp_syncobj) {
5319 close (sem->temp_syncobj);
5320 sem->temp_syncobj = 0;
5321 } else {
5322 device->ws->reset_syncobj(device->ws, syncobj_handle);
5323 }
5324 }
5325 break;
5326 default:
5327 unreachable("Unhandled semaphore handle type");
5328 }
5329
5330 if (ret)
5331 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5332 return VK_SUCCESS;
5333 }
5334
5335 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5336 VkPhysicalDevice physicalDevice,
5337 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5338 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5339 {
5340 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5341
5342 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5343 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5344 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5345 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5346 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5347 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5348 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5349 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5350 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5351 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5352 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5353 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5354 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5355 } else {
5356 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5357 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5358 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5359 }
5360 }
5361
5362 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5363 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5364 {
5365 RADV_FROM_HANDLE(radv_device, device, _device);
5366 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5367 uint32_t *syncobj_dst = NULL;
5368
5369
5370 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5371 syncobj_dst = &fence->temp_syncobj;
5372 } else {
5373 syncobj_dst = &fence->syncobj;
5374 }
5375
5376 switch(pImportFenceFdInfo->handleType) {
5377 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5378 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5379 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5380 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5381 default:
5382 unreachable("Unhandled fence handle type");
5383 }
5384 }
5385
5386 VkResult radv_GetFenceFdKHR(VkDevice _device,
5387 const VkFenceGetFdInfoKHR *pGetFdInfo,
5388 int *pFd)
5389 {
5390 RADV_FROM_HANDLE(radv_device, device, _device);
5391 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5392 int ret;
5393 uint32_t syncobj_handle;
5394
5395 if (fence->temp_syncobj)
5396 syncobj_handle = fence->temp_syncobj;
5397 else
5398 syncobj_handle = fence->syncobj;
5399
5400 switch(pGetFdInfo->handleType) {
5401 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5402 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5403 break;
5404 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5405 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5406 if (!ret) {
5407 if (fence->temp_syncobj) {
5408 close (fence->temp_syncobj);
5409 fence->temp_syncobj = 0;
5410 } else {
5411 device->ws->reset_syncobj(device->ws, syncobj_handle);
5412 }
5413 }
5414 break;
5415 default:
5416 unreachable("Unhandled fence handle type");
5417 }
5418
5419 if (ret)
5420 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5421 return VK_SUCCESS;
5422 }
5423
5424 void radv_GetPhysicalDeviceExternalFenceProperties(
5425 VkPhysicalDevice physicalDevice,
5426 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5427 VkExternalFenceProperties *pExternalFenceProperties)
5428 {
5429 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5430
5431 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5432 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5433 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5434 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5435 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5436 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5437 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5438 } else {
5439 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5440 pExternalFenceProperties->compatibleHandleTypes = 0;
5441 pExternalFenceProperties->externalFenceFeatures = 0;
5442 }
5443 }
5444
5445 VkResult
5446 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5447 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5448 const VkAllocationCallbacks* pAllocator,
5449 VkDebugReportCallbackEXT* pCallback)
5450 {
5451 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5452 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5453 pCreateInfo, pAllocator, &instance->alloc,
5454 pCallback);
5455 }
5456
5457 void
5458 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5459 VkDebugReportCallbackEXT _callback,
5460 const VkAllocationCallbacks* pAllocator)
5461 {
5462 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5463 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5464 _callback, pAllocator, &instance->alloc);
5465 }
5466
5467 void
5468 radv_DebugReportMessageEXT(VkInstance _instance,
5469 VkDebugReportFlagsEXT flags,
5470 VkDebugReportObjectTypeEXT objectType,
5471 uint64_t object,
5472 size_t location,
5473 int32_t messageCode,
5474 const char* pLayerPrefix,
5475 const char* pMessage)
5476 {
5477 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5478 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5479 object, location, messageCode, pLayerPrefix, pMessage);
5480 }
5481
5482 void
5483 radv_GetDeviceGroupPeerMemoryFeatures(
5484 VkDevice device,
5485 uint32_t heapIndex,
5486 uint32_t localDeviceIndex,
5487 uint32_t remoteDeviceIndex,
5488 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5489 {
5490 assert(localDeviceIndex == remoteDeviceIndex);
5491
5492 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5493 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5494 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5495 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5496 }
5497
5498 static const VkTimeDomainEXT radv_time_domains[] = {
5499 VK_TIME_DOMAIN_DEVICE_EXT,
5500 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5501 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5502 };
5503
5504 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5505 VkPhysicalDevice physicalDevice,
5506 uint32_t *pTimeDomainCount,
5507 VkTimeDomainEXT *pTimeDomains)
5508 {
5509 int d;
5510 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5511
5512 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5513 vk_outarray_append(&out, i) {
5514 *i = radv_time_domains[d];
5515 }
5516 }
5517
5518 return vk_outarray_status(&out);
5519 }
5520
5521 static uint64_t
5522 radv_clock_gettime(clockid_t clock_id)
5523 {
5524 struct timespec current;
5525 int ret;
5526
5527 ret = clock_gettime(clock_id, &current);
5528 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5529 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5530 if (ret < 0)
5531 return 0;
5532
5533 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5534 }
5535
5536 VkResult radv_GetCalibratedTimestampsEXT(
5537 VkDevice _device,
5538 uint32_t timestampCount,
5539 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5540 uint64_t *pTimestamps,
5541 uint64_t *pMaxDeviation)
5542 {
5543 RADV_FROM_HANDLE(radv_device, device, _device);
5544 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5545 int d;
5546 uint64_t begin, end;
5547 uint64_t max_clock_period = 0;
5548
5549 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5550
5551 for (d = 0; d < timestampCount; d++) {
5552 switch (pTimestampInfos[d].timeDomain) {
5553 case VK_TIME_DOMAIN_DEVICE_EXT:
5554 pTimestamps[d] = device->ws->query_value(device->ws,
5555 RADEON_TIMESTAMP);
5556 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5557 max_clock_period = MAX2(max_clock_period, device_period);
5558 break;
5559 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5560 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5561 max_clock_period = MAX2(max_clock_period, 1);
5562 break;
5563
5564 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5565 pTimestamps[d] = begin;
5566 break;
5567 default:
5568 pTimestamps[d] = 0;
5569 break;
5570 }
5571 }
5572
5573 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5574
5575 /*
5576 * The maximum deviation is the sum of the interval over which we
5577 * perform the sampling and the maximum period of any sampled
5578 * clock. That's because the maximum skew between any two sampled
5579 * clock edges is when the sampled clock with the largest period is
5580 * sampled at the end of that period but right at the beginning of the
5581 * sampling interval and some other clock is sampled right at the
5582 * begining of its sampling period and right at the end of the
5583 * sampling interval. Let's assume the GPU has the longest clock
5584 * period and that the application is sampling GPU and monotonic:
5585 *
5586 * s e
5587 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5588 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5589 *
5590 * g
5591 * 0 1 2 3
5592 * GPU -----_____-----_____-----_____-----_____
5593 *
5594 * m
5595 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5596 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5597 *
5598 * Interval <----------------->
5599 * Deviation <-------------------------->
5600 *
5601 * s = read(raw) 2
5602 * g = read(GPU) 1
5603 * m = read(monotonic) 2
5604 * e = read(raw) b
5605 *
5606 * We round the sample interval up by one tick to cover sampling error
5607 * in the interval clock
5608 */
5609
5610 uint64_t sample_interval = end - begin + 1;
5611
5612 *pMaxDeviation = sample_interval + max_clock_period;
5613
5614 return VK_SUCCESS;
5615 }
5616
5617 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5618 VkPhysicalDevice physicalDevice,
5619 VkSampleCountFlagBits samples,
5620 VkMultisamplePropertiesEXT* pMultisampleProperties)
5621 {
5622 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5623 VK_SAMPLE_COUNT_4_BIT |
5624 VK_SAMPLE_COUNT_8_BIT)) {
5625 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5626 } else {
5627 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5628 }
5629 }