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amd: move adaptive sync to performance section, as it is defined in xmlpool
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include <llvm/Config/llvm-config.h>
33 #include "radv_debug.h"
34 #include "radv_private.h"
35 #include "radv_shader.h"
36 #include "radv_cs.h"
37 #include "util/disk_cache.h"
38 #include "util/strtod.h"
39 #include "vk_util.h"
40 #include <xf86drm.h>
41 #include <amdgpu.h>
42 #include <amdgpu_drm.h>
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "git_sha1.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
118 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
119 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
120 default: chip_string = "AMD RADV unknown"; break;
121 }
122
123 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
124 }
125
126 static uint64_t
127 radv_get_visible_vram_size(struct radv_physical_device *device)
128 {
129 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
130 }
131
132 static uint64_t
133 radv_get_vram_size(struct radv_physical_device *device)
134 {
135 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
136 }
137
138 static void
139 radv_physical_device_init_mem_types(struct radv_physical_device *device)
140 {
141 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
142 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
143 uint64_t vram_size = radv_get_vram_size(device);
144 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
145 device->memory_properties.memoryHeapCount = 0;
146 if (vram_size > 0) {
147 vram_index = device->memory_properties.memoryHeapCount++;
148 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
149 .size = vram_size,
150 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
151 };
152 }
153 if (visible_vram_size) {
154 visible_vram_index = device->memory_properties.memoryHeapCount++;
155 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
156 .size = visible_vram_size,
157 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
158 };
159 }
160 if (device->rad_info.gart_size > 0) {
161 gart_index = device->memory_properties.memoryHeapCount++;
162 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
163 .size = device->rad_info.gart_size,
164 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
165 };
166 }
167
168 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
169 unsigned type_count = 0;
170 if (vram_index >= 0) {
171 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
172 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
173 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
174 .heapIndex = vram_index,
175 };
176 }
177 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
178 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
179 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
180 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
181 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
195 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
196 * as they have identical property flags, and according to the
197 * spec, for types with identical flags, the one with greater
198 * performance must be given a lower index. */
199 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
200 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
201 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
202 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
203 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
204 .heapIndex = gart_index,
205 };
206 }
207 if (gart_index >= 0) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
212 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
213 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
214 .heapIndex = gart_index,
215 };
216 }
217 device->memory_properties.memoryTypeCount = type_count;
218 }
219
220 static void
221 radv_handle_env_var_force_family(struct radv_physical_device *device)
222 {
223 const char *family = getenv("RADV_FORCE_FAMILY");
224 unsigned i;
225
226 if (!family)
227 return;
228
229 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
230 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
231 /* Override family and chip_class. */
232 device->rad_info.family = i;
233
234 if (i >= CHIP_NAVI10)
235 device->rad_info.chip_class = GFX10;
236 else if (i >= CHIP_VEGA10)
237 device->rad_info.chip_class = GFX9;
238 else if (i >= CHIP_TONGA)
239 device->rad_info.chip_class = GFX8;
240 else if (i >= CHIP_BONAIRE)
241 device->rad_info.chip_class = GFX7;
242 else
243 device->rad_info.chip_class = GFX6;
244
245 return;
246 }
247 }
248
249 fprintf(stderr, "radv: Unknown family: %s\n", family);
250 exit(1);
251 }
252
253 static VkResult
254 radv_physical_device_init(struct radv_physical_device *device,
255 struct radv_instance *instance,
256 drmDevicePtr drm_device)
257 {
258 const char *path = drm_device->nodes[DRM_NODE_RENDER];
259 VkResult result;
260 drmVersionPtr version;
261 int fd;
262 int master_fd = -1;
263
264 fd = open(path, O_RDWR | O_CLOEXEC);
265 if (fd < 0) {
266 if (instance->debug_flags & RADV_DEBUG_STARTUP)
267 radv_logi("Could not open device '%s'", path);
268
269 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
270 }
271
272 version = drmGetVersion(fd);
273 if (!version) {
274 close(fd);
275
276 if (instance->debug_flags & RADV_DEBUG_STARTUP)
277 radv_logi("Could not get the kernel driver version for device '%s'", path);
278
279 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
280 "failed to get version %s: %m", path);
281 }
282
283 if (strcmp(version->name, "amdgpu")) {
284 drmFreeVersion(version);
285 close(fd);
286
287 if (instance->debug_flags & RADV_DEBUG_STARTUP)
288 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
289
290 return VK_ERROR_INCOMPATIBLE_DRIVER;
291 }
292 drmFreeVersion(version);
293
294 if (instance->debug_flags & RADV_DEBUG_STARTUP)
295 radv_logi("Found compatible device '%s'.", path);
296
297 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
298 device->instance = instance;
299
300 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
301 instance->perftest_flags);
302 if (!device->ws) {
303 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
304 goto fail;
305 }
306
307 if (instance->enabled_extensions.KHR_display) {
308 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
309 if (master_fd >= 0) {
310 uint32_t accel_working = 0;
311 struct drm_amdgpu_info request = {
312 .return_pointer = (uintptr_t)&accel_working,
313 .return_size = sizeof(accel_working),
314 .query = AMDGPU_INFO_ACCEL_WORKING
315 };
316
317 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
318 close(master_fd);
319 master_fd = -1;
320 }
321 }
322 }
323
324 device->master_fd = master_fd;
325 device->local_fd = fd;
326 device->ws->query_info(device->ws, &device->rad_info);
327
328 radv_handle_env_var_force_family(device);
329
330 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
331
332 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
333 device->ws->destroy(device->ws);
334 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
335 "cannot generate UUID");
336 goto fail;
337 }
338
339 /* These flags affect shader compilation. */
340 uint64_t shader_env_flags =
341 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
342 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
343
344 /* The gpu id is already embedded in the uuid so we just pass "radv"
345 * when creating the cache.
346 */
347 char buf[VK_UUID_SIZE * 2 + 1];
348 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
349 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
350
351 if (device->rad_info.chip_class < GFX8 ||
352 device->rad_info.chip_class > GFX9)
353 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
354
355 radv_get_driver_uuid(&device->driver_uuid);
356 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
357
358 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
359 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
360
361 device->dcc_msaa_allowed =
362 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
363
364 device->use_shader_ballot = device->rad_info.chip_class >= GFX8 &&
365 device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
366
367 /* Determine the number of threads per wave for all stages. */
368 device->cs_wave_size = 64;
369 device->ps_wave_size = 64;
370 device->ge_wave_size = 64;
371
372 if (device->rad_info.chip_class >= GFX10) {
373 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
374 device->cs_wave_size = 32;
375
376 /* For pixel shaders, wave64 is recommanded. */
377 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
378 device->ps_wave_size = 32;
379
380 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
381 device->ge_wave_size = 32;
382 }
383
384 radv_physical_device_init_mem_types(device);
385 radv_fill_device_extension_table(device, &device->supported_extensions);
386
387 device->bus_info = *drm_device->businfo.pci;
388
389 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
390 ac_print_gpu_info(&device->rad_info);
391
392 /* The WSI is structured as a layer on top of the driver, so this has
393 * to be the last part of initialization (at least until we get other
394 * semi-layers).
395 */
396 result = radv_init_wsi(device);
397 if (result != VK_SUCCESS) {
398 device->ws->destroy(device->ws);
399 vk_error(instance, result);
400 goto fail;
401 }
402
403 return VK_SUCCESS;
404
405 fail:
406 close(fd);
407 if (master_fd != -1)
408 close(master_fd);
409 return result;
410 }
411
412 static void
413 radv_physical_device_finish(struct radv_physical_device *device)
414 {
415 radv_finish_wsi(device);
416 device->ws->destroy(device->ws);
417 disk_cache_destroy(device->disk_cache);
418 close(device->local_fd);
419 if (device->master_fd != -1)
420 close(device->master_fd);
421 }
422
423 static void *
424 default_alloc_func(void *pUserData, size_t size, size_t align,
425 VkSystemAllocationScope allocationScope)
426 {
427 return malloc(size);
428 }
429
430 static void *
431 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
432 size_t align, VkSystemAllocationScope allocationScope)
433 {
434 return realloc(pOriginal, size);
435 }
436
437 static void
438 default_free_func(void *pUserData, void *pMemory)
439 {
440 free(pMemory);
441 }
442
443 static const VkAllocationCallbacks default_alloc = {
444 .pUserData = NULL,
445 .pfnAllocation = default_alloc_func,
446 .pfnReallocation = default_realloc_func,
447 .pfnFree = default_free_func,
448 };
449
450 static const struct debug_control radv_debug_options[] = {
451 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
452 {"nodcc", RADV_DEBUG_NO_DCC},
453 {"shaders", RADV_DEBUG_DUMP_SHADERS},
454 {"nocache", RADV_DEBUG_NO_CACHE},
455 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
456 {"nohiz", RADV_DEBUG_NO_HIZ},
457 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
458 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
459 {"allbos", RADV_DEBUG_ALL_BOS},
460 {"noibs", RADV_DEBUG_NO_IBS},
461 {"spirv", RADV_DEBUG_DUMP_SPIRV},
462 {"vmfaults", RADV_DEBUG_VM_FAULTS},
463 {"zerovram", RADV_DEBUG_ZERO_VRAM},
464 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
465 {"nosisched", RADV_DEBUG_NO_SISCHED},
466 {"preoptir", RADV_DEBUG_PREOPTIR},
467 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
468 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
469 {"info", RADV_DEBUG_INFO},
470 {"errors", RADV_DEBUG_ERRORS},
471 {"startup", RADV_DEBUG_STARTUP},
472 {"checkir", RADV_DEBUG_CHECKIR},
473 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
474 {"nobinning", RADV_DEBUG_NOBINNING},
475 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
476 {"nongg", RADV_DEBUG_NO_NGG},
477 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
478 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
479 {NULL, 0}
480 };
481
482 const char *
483 radv_get_debug_option_name(int id)
484 {
485 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
486 return radv_debug_options[id].string;
487 }
488
489 static const struct debug_control radv_perftest_options[] = {
490 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
491 {"sisched", RADV_PERFTEST_SISCHED},
492 {"localbos", RADV_PERFTEST_LOCAL_BOS},
493 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
494 {"bolist", RADV_PERFTEST_BO_LIST},
495 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
496 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
497 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
498 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
499 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
500 {NULL, 0}
501 };
502
503 const char *
504 radv_get_perftest_option_name(int id)
505 {
506 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
507 return radv_perftest_options[id].string;
508 }
509
510 static void
511 radv_handle_per_app_options(struct radv_instance *instance,
512 const VkApplicationInfo *info)
513 {
514 const char *name = info ? info->pApplicationName : NULL;
515
516 if (!name)
517 return;
518
519 if (!strcmp(name, "Talos - Linux - 32bit") ||
520 !strcmp(name, "Talos - Linux - 64bit")) {
521 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
522 /* Force enable LLVM sisched for Talos because it looks
523 * safe and it gives few more FPS.
524 */
525 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
526 }
527 } else if (!strcmp(name, "DOOM_VFR")) {
528 /* Work around a Doom VFR game bug */
529 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
530 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
531 /* Workaround for a WaW hazard when LLVM moves/merges
532 * load/store memory operations.
533 * See https://reviews.llvm.org/D61313
534 */
535 if (LLVM_VERSION_MAJOR < 9)
536 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
537 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
538 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT)) {
539 /* Force enable VK_AMD_shader_ballot because it looks
540 * safe and it gives a nice boost (+20% on Vega 56 at
541 * this time).
542 */
543 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
544 }
545 }
546 }
547
548 static int radv_get_instance_extension_index(const char *name)
549 {
550 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
551 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
552 return i;
553 }
554 return -1;
555 }
556
557 static const char radv_dri_options_xml[] =
558 DRI_CONF_BEGIN
559 DRI_CONF_SECTION_PERFORMANCE
560 DRI_CONF_ADAPTIVE_SYNC("true")
561 DRI_CONF_SECTION_END
562 DRI_CONF_END;
563
564 static void radv_init_dri_options(struct radv_instance *instance)
565 {
566 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
567 driParseConfigFiles(&instance->dri_options,
568 &instance->available_dri_options,
569 0, "radv", NULL);
570 }
571
572 VkResult radv_CreateInstance(
573 const VkInstanceCreateInfo* pCreateInfo,
574 const VkAllocationCallbacks* pAllocator,
575 VkInstance* pInstance)
576 {
577 struct radv_instance *instance;
578 VkResult result;
579
580 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
581
582 uint32_t client_version;
583 if (pCreateInfo->pApplicationInfo &&
584 pCreateInfo->pApplicationInfo->apiVersion != 0) {
585 client_version = pCreateInfo->pApplicationInfo->apiVersion;
586 } else {
587 client_version = VK_API_VERSION_1_0;
588 }
589
590 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
591 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
592 if (!instance)
593 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
594
595 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
596
597 if (pAllocator)
598 instance->alloc = *pAllocator;
599 else
600 instance->alloc = default_alloc;
601
602 instance->apiVersion = client_version;
603 instance->physicalDeviceCount = -1;
604
605 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
606 radv_debug_options);
607
608 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
609 radv_perftest_options);
610
611
612 if (instance->debug_flags & RADV_DEBUG_STARTUP)
613 radv_logi("Created an instance");
614
615 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
616 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
617 int index = radv_get_instance_extension_index(ext_name);
618
619 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
620 vk_free2(&default_alloc, pAllocator, instance);
621 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
622 }
623
624 instance->enabled_extensions.extensions[index] = true;
625 }
626
627 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
628 if (result != VK_SUCCESS) {
629 vk_free2(&default_alloc, pAllocator, instance);
630 return vk_error(instance, result);
631 }
632
633 _mesa_locale_init();
634 glsl_type_singleton_init_or_ref();
635
636 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
637
638 radv_init_dri_options(instance);
639 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
640
641 *pInstance = radv_instance_to_handle(instance);
642
643 return VK_SUCCESS;
644 }
645
646 void radv_DestroyInstance(
647 VkInstance _instance,
648 const VkAllocationCallbacks* pAllocator)
649 {
650 RADV_FROM_HANDLE(radv_instance, instance, _instance);
651
652 if (!instance)
653 return;
654
655 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
656 radv_physical_device_finish(instance->physicalDevices + i);
657 }
658
659 VG(VALGRIND_DESTROY_MEMPOOL(instance));
660
661 glsl_type_singleton_decref();
662 _mesa_locale_fini();
663
664 driDestroyOptionCache(&instance->dri_options);
665 driDestroyOptionInfo(&instance->available_dri_options);
666
667 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
668
669 vk_free(&instance->alloc, instance);
670 }
671
672 static VkResult
673 radv_enumerate_devices(struct radv_instance *instance)
674 {
675 /* TODO: Check for more devices ? */
676 drmDevicePtr devices[8];
677 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
678 int max_devices;
679
680 instance->physicalDeviceCount = 0;
681
682 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
683
684 if (instance->debug_flags & RADV_DEBUG_STARTUP)
685 radv_logi("Found %d drm nodes", max_devices);
686
687 if (max_devices < 1)
688 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
689
690 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
691 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
692 devices[i]->bustype == DRM_BUS_PCI &&
693 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
694
695 result = radv_physical_device_init(instance->physicalDevices +
696 instance->physicalDeviceCount,
697 instance,
698 devices[i]);
699 if (result == VK_SUCCESS)
700 ++instance->physicalDeviceCount;
701 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
702 break;
703 }
704 }
705 drmFreeDevices(devices, max_devices);
706
707 return result;
708 }
709
710 VkResult radv_EnumeratePhysicalDevices(
711 VkInstance _instance,
712 uint32_t* pPhysicalDeviceCount,
713 VkPhysicalDevice* pPhysicalDevices)
714 {
715 RADV_FROM_HANDLE(radv_instance, instance, _instance);
716 VkResult result;
717
718 if (instance->physicalDeviceCount < 0) {
719 result = radv_enumerate_devices(instance);
720 if (result != VK_SUCCESS &&
721 result != VK_ERROR_INCOMPATIBLE_DRIVER)
722 return result;
723 }
724
725 if (!pPhysicalDevices) {
726 *pPhysicalDeviceCount = instance->physicalDeviceCount;
727 } else {
728 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
729 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
730 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
731 }
732
733 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
734 : VK_SUCCESS;
735 }
736
737 VkResult radv_EnumeratePhysicalDeviceGroups(
738 VkInstance _instance,
739 uint32_t* pPhysicalDeviceGroupCount,
740 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
741 {
742 RADV_FROM_HANDLE(radv_instance, instance, _instance);
743 VkResult result;
744
745 if (instance->physicalDeviceCount < 0) {
746 result = radv_enumerate_devices(instance);
747 if (result != VK_SUCCESS &&
748 result != VK_ERROR_INCOMPATIBLE_DRIVER)
749 return result;
750 }
751
752 if (!pPhysicalDeviceGroupProperties) {
753 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
754 } else {
755 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
756 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
757 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
758 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
759 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
760 }
761 }
762 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
763 : VK_SUCCESS;
764 }
765
766 void radv_GetPhysicalDeviceFeatures(
767 VkPhysicalDevice physicalDevice,
768 VkPhysicalDeviceFeatures* pFeatures)
769 {
770 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
771 memset(pFeatures, 0, sizeof(*pFeatures));
772
773 *pFeatures = (VkPhysicalDeviceFeatures) {
774 .robustBufferAccess = true,
775 .fullDrawIndexUint32 = true,
776 .imageCubeArray = true,
777 .independentBlend = true,
778 .geometryShader = true,
779 .tessellationShader = true,
780 .sampleRateShading = true,
781 .dualSrcBlend = true,
782 .logicOp = true,
783 .multiDrawIndirect = true,
784 .drawIndirectFirstInstance = true,
785 .depthClamp = true,
786 .depthBiasClamp = true,
787 .fillModeNonSolid = true,
788 .depthBounds = true,
789 .wideLines = true,
790 .largePoints = true,
791 .alphaToOne = true,
792 .multiViewport = true,
793 .samplerAnisotropy = true,
794 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
795 .textureCompressionASTC_LDR = false,
796 .textureCompressionBC = true,
797 .occlusionQueryPrecise = true,
798 .pipelineStatisticsQuery = true,
799 .vertexPipelineStoresAndAtomics = true,
800 .fragmentStoresAndAtomics = true,
801 .shaderTessellationAndGeometryPointSize = true,
802 .shaderImageGatherExtended = true,
803 .shaderStorageImageExtendedFormats = true,
804 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
805 .shaderUniformBufferArrayDynamicIndexing = true,
806 .shaderSampledImageArrayDynamicIndexing = true,
807 .shaderStorageBufferArrayDynamicIndexing = true,
808 .shaderStorageImageArrayDynamicIndexing = true,
809 .shaderStorageImageReadWithoutFormat = true,
810 .shaderStorageImageWriteWithoutFormat = true,
811 .shaderClipDistance = true,
812 .shaderCullDistance = true,
813 .shaderFloat64 = true,
814 .shaderInt64 = true,
815 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
816 .sparseBinding = true,
817 .variableMultisampleRate = true,
818 .inheritedQueries = true,
819 };
820 }
821
822 void radv_GetPhysicalDeviceFeatures2(
823 VkPhysicalDevice physicalDevice,
824 VkPhysicalDeviceFeatures2 *pFeatures)
825 {
826 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
827 vk_foreach_struct(ext, pFeatures->pNext) {
828 switch (ext->sType) {
829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
830 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
831 features->variablePointersStorageBuffer = true;
832 features->variablePointers = true;
833 break;
834 }
835 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
836 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
837 features->multiview = true;
838 features->multiviewGeometryShader = true;
839 features->multiviewTessellationShader = true;
840 break;
841 }
842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
843 VkPhysicalDeviceShaderDrawParametersFeatures *features =
844 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
845 features->shaderDrawParameters = true;
846 break;
847 }
848 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
849 VkPhysicalDeviceProtectedMemoryFeatures *features =
850 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
851 features->protectedMemory = false;
852 break;
853 }
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
855 VkPhysicalDevice16BitStorageFeatures *features =
856 (VkPhysicalDevice16BitStorageFeatures*)ext;
857 bool enabled = pdevice->rad_info.chip_class >= GFX8;
858 features->storageBuffer16BitAccess = enabled;
859 features->uniformAndStorageBuffer16BitAccess = enabled;
860 features->storagePushConstant16 = enabled;
861 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
862 break;
863 }
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
865 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
866 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
867 features->samplerYcbcrConversion = true;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
871 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
872 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
873 features->shaderInputAttachmentArrayDynamicIndexing = true;
874 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
875 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
876 features->shaderUniformBufferArrayNonUniformIndexing = true;
877 features->shaderSampledImageArrayNonUniformIndexing = true;
878 features->shaderStorageBufferArrayNonUniformIndexing = true;
879 features->shaderStorageImageArrayNonUniformIndexing = true;
880 features->shaderInputAttachmentArrayNonUniformIndexing = true;
881 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
882 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
883 features->descriptorBindingUniformBufferUpdateAfterBind = true;
884 features->descriptorBindingSampledImageUpdateAfterBind = true;
885 features->descriptorBindingStorageImageUpdateAfterBind = true;
886 features->descriptorBindingStorageBufferUpdateAfterBind = true;
887 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
888 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
889 features->descriptorBindingUpdateUnusedWhilePending = true;
890 features->descriptorBindingPartiallyBound = true;
891 features->descriptorBindingVariableDescriptorCount = true;
892 features->runtimeDescriptorArray = true;
893 break;
894 }
895 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
896 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
897 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
898 features->conditionalRendering = true;
899 features->inheritedConditionalRendering = false;
900 break;
901 }
902 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
903 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
904 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
905 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
906 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
910 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
911 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
912 features->transformFeedback = true;
913 features->geometryStreams = true;
914 break;
915 }
916 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
917 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
918 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
919 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
920 break;
921 }
922 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
923 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
924 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
925 features->memoryPriority = VK_TRUE;
926 break;
927 }
928 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
929 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
930 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
931 features->bufferDeviceAddress = true;
932 features->bufferDeviceAddressCaptureReplay = false;
933 features->bufferDeviceAddressMultiDevice = false;
934 break;
935 }
936 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
937 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
938 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
939 features->depthClipEnable = true;
940 break;
941 }
942 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
943 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
944 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
945 features->hostQueryReset = true;
946 break;
947 }
948 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
949 VkPhysicalDevice8BitStorageFeaturesKHR *features =
950 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
951 bool enabled = pdevice->rad_info.chip_class >= GFX8;
952 features->storageBuffer8BitAccess = enabled;
953 features->uniformAndStorageBuffer8BitAccess = enabled;
954 features->storagePushConstant8 = enabled;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
958 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
959 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
960 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8;
961 features->shaderInt8 = true;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
965 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
966 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
967 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
968 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
972 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
973 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
974
975 features->inlineUniformBlock = true;
976 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
977 break;
978 }
979 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
980 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
981 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
982 features->computeDerivativeGroupQuads = false;
983 features->computeDerivativeGroupLinear = true;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
987 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
988 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
989 features->ycbcrImageArrays = true;
990 break;
991 }
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
993 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
994 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
995 features->uniformBufferStandardLayout = true;
996 break;
997 }
998 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
999 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1000 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1001 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1005 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1006 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1007 features->imagelessFramebuffer = true;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1011 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1012 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1013 features->pipelineExecutableInfo = true;
1014 break;
1015 }
1016 default:
1017 break;
1018 }
1019 }
1020 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1021 }
1022
1023 void radv_GetPhysicalDeviceProperties(
1024 VkPhysicalDevice physicalDevice,
1025 VkPhysicalDeviceProperties* pProperties)
1026 {
1027 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1028 VkSampleCountFlags sample_counts = 0xf;
1029
1030 /* make sure that the entire descriptor set is addressable with a signed
1031 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1032 * be at most 2 GiB. the combined image & samples object count as one of
1033 * both. This limit is for the pipeline layout, not for the set layout, but
1034 * there is no set limit, so we just set a pipeline limit. I don't think
1035 * any app is going to hit this soon. */
1036 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1037 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1038 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1039 32 /* sampler, largest when combined with image */ +
1040 64 /* sampled image */ +
1041 64 /* storage image */);
1042
1043 VkPhysicalDeviceLimits limits = {
1044 .maxImageDimension1D = (1 << 14),
1045 .maxImageDimension2D = (1 << 14),
1046 .maxImageDimension3D = (1 << 11),
1047 .maxImageDimensionCube = (1 << 14),
1048 .maxImageArrayLayers = (1 << 11),
1049 .maxTexelBufferElements = 128 * 1024 * 1024,
1050 .maxUniformBufferRange = UINT32_MAX,
1051 .maxStorageBufferRange = UINT32_MAX,
1052 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1053 .maxMemoryAllocationCount = UINT32_MAX,
1054 .maxSamplerAllocationCount = 64 * 1024,
1055 .bufferImageGranularity = 64, /* A cache line */
1056 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1057 .maxBoundDescriptorSets = MAX_SETS,
1058 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1059 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1060 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1061 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1062 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1063 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1064 .maxPerStageResources = max_descriptor_set_size,
1065 .maxDescriptorSetSamplers = max_descriptor_set_size,
1066 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1067 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1068 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1069 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1070 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1071 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1072 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1073 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1074 .maxVertexInputBindings = MAX_VBS,
1075 .maxVertexInputAttributeOffset = 2047,
1076 .maxVertexInputBindingStride = 2048,
1077 .maxVertexOutputComponents = 128,
1078 .maxTessellationGenerationLevel = 64,
1079 .maxTessellationPatchSize = 32,
1080 .maxTessellationControlPerVertexInputComponents = 128,
1081 .maxTessellationControlPerVertexOutputComponents = 128,
1082 .maxTessellationControlPerPatchOutputComponents = 120,
1083 .maxTessellationControlTotalOutputComponents = 4096,
1084 .maxTessellationEvaluationInputComponents = 128,
1085 .maxTessellationEvaluationOutputComponents = 128,
1086 .maxGeometryShaderInvocations = 127,
1087 .maxGeometryInputComponents = 64,
1088 .maxGeometryOutputComponents = 128,
1089 .maxGeometryOutputVertices = 256,
1090 .maxGeometryTotalOutputComponents = 1024,
1091 .maxFragmentInputComponents = 128,
1092 .maxFragmentOutputAttachments = 8,
1093 .maxFragmentDualSrcAttachments = 1,
1094 .maxFragmentCombinedOutputResources = 8,
1095 .maxComputeSharedMemorySize = 32768,
1096 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1097 .maxComputeWorkGroupInvocations = 2048,
1098 .maxComputeWorkGroupSize = {
1099 2048,
1100 2048,
1101 2048
1102 },
1103 .subPixelPrecisionBits = 8,
1104 .subTexelPrecisionBits = 8,
1105 .mipmapPrecisionBits = 8,
1106 .maxDrawIndexedIndexValue = UINT32_MAX,
1107 .maxDrawIndirectCount = UINT32_MAX,
1108 .maxSamplerLodBias = 16,
1109 .maxSamplerAnisotropy = 16,
1110 .maxViewports = MAX_VIEWPORTS,
1111 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1112 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1113 .viewportSubPixelBits = 8,
1114 .minMemoryMapAlignment = 4096, /* A page */
1115 .minTexelBufferOffsetAlignment = 1,
1116 .minUniformBufferOffsetAlignment = 4,
1117 .minStorageBufferOffsetAlignment = 4,
1118 .minTexelOffset = -32,
1119 .maxTexelOffset = 31,
1120 .minTexelGatherOffset = -32,
1121 .maxTexelGatherOffset = 31,
1122 .minInterpolationOffset = -2,
1123 .maxInterpolationOffset = 2,
1124 .subPixelInterpolationOffsetBits = 8,
1125 .maxFramebufferWidth = (1 << 14),
1126 .maxFramebufferHeight = (1 << 14),
1127 .maxFramebufferLayers = (1 << 10),
1128 .framebufferColorSampleCounts = sample_counts,
1129 .framebufferDepthSampleCounts = sample_counts,
1130 .framebufferStencilSampleCounts = sample_counts,
1131 .framebufferNoAttachmentsSampleCounts = sample_counts,
1132 .maxColorAttachments = MAX_RTS,
1133 .sampledImageColorSampleCounts = sample_counts,
1134 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1135 .sampledImageDepthSampleCounts = sample_counts,
1136 .sampledImageStencilSampleCounts = sample_counts,
1137 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1138 .maxSampleMaskWords = 1,
1139 .timestampComputeAndGraphics = true,
1140 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1141 .maxClipDistances = 8,
1142 .maxCullDistances = 8,
1143 .maxCombinedClipAndCullDistances = 8,
1144 .discreteQueuePriorities = 2,
1145 .pointSizeRange = { 0.0, 8192.0 },
1146 .lineWidthRange = { 0.0, 7.9921875 },
1147 .pointSizeGranularity = (1.0 / 8.0),
1148 .lineWidthGranularity = (1.0 / 128.0),
1149 .strictLines = false, /* FINISHME */
1150 .standardSampleLocations = true,
1151 .optimalBufferCopyOffsetAlignment = 128,
1152 .optimalBufferCopyRowPitchAlignment = 128,
1153 .nonCoherentAtomSize = 64,
1154 };
1155
1156 *pProperties = (VkPhysicalDeviceProperties) {
1157 .apiVersion = radv_physical_device_api_version(pdevice),
1158 .driverVersion = vk_get_driver_version(),
1159 .vendorID = ATI_VENDOR_ID,
1160 .deviceID = pdevice->rad_info.pci_id,
1161 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1162 .limits = limits,
1163 .sparseProperties = {0},
1164 };
1165
1166 strcpy(pProperties->deviceName, pdevice->name);
1167 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1168 }
1169
1170 void radv_GetPhysicalDeviceProperties2(
1171 VkPhysicalDevice physicalDevice,
1172 VkPhysicalDeviceProperties2 *pProperties)
1173 {
1174 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1175 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1176
1177 vk_foreach_struct(ext, pProperties->pNext) {
1178 switch (ext->sType) {
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1180 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1181 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1182 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1186 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1187 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1188 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1189 properties->deviceLUIDValid = false;
1190 break;
1191 }
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1193 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1194 properties->maxMultiviewViewCount = MAX_VIEWS;
1195 properties->maxMultiviewInstanceIndex = INT_MAX;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1199 VkPhysicalDevicePointClippingProperties *properties =
1200 (VkPhysicalDevicePointClippingProperties*)ext;
1201 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1205 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1206 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1207 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1211 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1212 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1213 properties->minImportedHostPointerAlignment = 4096;
1214 break;
1215 }
1216 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1217 VkPhysicalDeviceSubgroupProperties *properties =
1218 (VkPhysicalDeviceSubgroupProperties*)ext;
1219 properties->subgroupSize = 64;
1220 properties->supportedStages = VK_SHADER_STAGE_ALL;
1221 properties->supportedOperations =
1222 VK_SUBGROUP_FEATURE_BASIC_BIT |
1223 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1224 VK_SUBGROUP_FEATURE_QUAD_BIT |
1225 VK_SUBGROUP_FEATURE_VOTE_BIT;
1226 if (pdevice->rad_info.chip_class >= GFX8) {
1227 properties->supportedOperations |=
1228 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1229 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1230 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1231 }
1232 properties->quadOperationsInAllStages = true;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1236 VkPhysicalDeviceMaintenance3Properties *properties =
1237 (VkPhysicalDeviceMaintenance3Properties*)ext;
1238 /* Make sure everything is addressable by a signed 32-bit int, and
1239 * our largest descriptors are 96 bytes. */
1240 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1241 /* Our buffer size fields allow only this much */
1242 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1246 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1247 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1248 /* GFX6-8 only support single channel min/max filter. */
1249 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1250 properties->filterMinmaxSingleComponentFormats = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1254 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1255 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1256
1257 /* Shader engines. */
1258 properties->shaderEngineCount =
1259 pdevice->rad_info.max_se;
1260 properties->shaderArraysPerEngineCount =
1261 pdevice->rad_info.max_sh_per_se;
1262 properties->computeUnitsPerShaderArray =
1263 pdevice->rad_info.num_good_cu_per_sh;
1264 properties->simdPerComputeUnit = 4;
1265 properties->wavefrontsPerSimd =
1266 pdevice->rad_info.family == CHIP_TONGA ||
1267 pdevice->rad_info.family == CHIP_ICELAND ||
1268 pdevice->rad_info.family == CHIP_POLARIS10 ||
1269 pdevice->rad_info.family == CHIP_POLARIS11 ||
1270 pdevice->rad_info.family == CHIP_POLARIS12 ||
1271 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1272 properties->wavefrontSize = 64;
1273
1274 /* SGPR. */
1275 properties->sgprsPerSimd =
1276 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1277 properties->minSgprAllocation =
1278 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1279 properties->maxSgprAllocation =
1280 pdevice->rad_info.family == CHIP_TONGA ||
1281 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1282 properties->sgprAllocationGranularity =
1283 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1284
1285 /* VGPR. */
1286 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1287 properties->minVgprAllocation = 4;
1288 properties->maxVgprAllocation = 256;
1289 properties->vgprAllocationGranularity = 4;
1290 break;
1291 }
1292 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1293 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1294 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1295
1296 properties->shaderCoreFeatures = 0;
1297 properties->activeComputeUnitCount =
1298 pdevice->rad_info.num_good_compute_units;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1302 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1303 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1304 properties->maxVertexAttribDivisor = UINT32_MAX;
1305 break;
1306 }
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1308 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1309 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1310 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1311 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1312 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1313 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1314 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1315 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1316 properties->robustBufferAccessUpdateAfterBind = false;
1317 properties->quadDivergentImplicitLod = false;
1318
1319 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1320 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1321 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1322 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1323 32 /* sampler, largest when combined with image */ +
1324 64 /* sampled image */ +
1325 64 /* storage image */);
1326 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1327 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1328 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1329 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1330 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1331 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1332 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1333 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1334 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1335 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1336 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1337 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1338 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1339 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1340 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1341 break;
1342 }
1343 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1344 VkPhysicalDeviceProtectedMemoryProperties *properties =
1345 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1346 properties->protectedNoFault = false;
1347 break;
1348 }
1349 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1350 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1351 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1352 properties->primitiveOverestimationSize = 0;
1353 properties->maxExtraPrimitiveOverestimationSize = 0;
1354 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1355 properties->primitiveUnderestimation = VK_FALSE;
1356 properties->conservativePointAndLineRasterization = VK_FALSE;
1357 properties->degenerateTrianglesRasterized = VK_FALSE;
1358 properties->degenerateLinesRasterized = VK_FALSE;
1359 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1360 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1364 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1365 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1366 properties->pciDomain = pdevice->bus_info.domain;
1367 properties->pciBus = pdevice->bus_info.bus;
1368 properties->pciDevice = pdevice->bus_info.dev;
1369 properties->pciFunction = pdevice->bus_info.func;
1370 break;
1371 }
1372 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1373 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1374 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1375
1376 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1377 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1378 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1379 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1380 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1381
1382 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1383 .major = 1,
1384 .minor = 1,
1385 .subminor = 2,
1386 .patch = 0,
1387 };
1388 break;
1389 }
1390 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1391 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1392 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1393 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1394 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1395 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1396 properties->maxTransformFeedbackStreamDataSize = 512;
1397 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1398 properties->maxTransformFeedbackBufferDataStride = 512;
1399 properties->transformFeedbackQueries = true;
1400 properties->transformFeedbackStreamsLinesTriangles = true;
1401 properties->transformFeedbackRasterizationStreamSelect = false;
1402 properties->transformFeedbackDraw = true;
1403 break;
1404 }
1405 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1406 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1407 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1408
1409 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1410 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1411 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1412 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1413 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1414 break;
1415 }
1416 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1417 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1418 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1419 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1420 VK_SAMPLE_COUNT_4_BIT |
1421 VK_SAMPLE_COUNT_8_BIT;
1422 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1423 properties->sampleLocationCoordinateRange[0] = 0.0f;
1424 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1425 properties->sampleLocationSubPixelBits = 4;
1426 properties->variableSampleLocations = VK_FALSE;
1427 break;
1428 }
1429 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1430 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1431 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1432
1433 /* We support all of the depth resolve modes */
1434 properties->supportedDepthResolveModes =
1435 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1436 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1437 VK_RESOLVE_MODE_MIN_BIT_KHR |
1438 VK_RESOLVE_MODE_MAX_BIT_KHR;
1439
1440 /* Average doesn't make sense for stencil so we don't support that */
1441 properties->supportedStencilResolveModes =
1442 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1443 VK_RESOLVE_MODE_MIN_BIT_KHR |
1444 VK_RESOLVE_MODE_MAX_BIT_KHR;
1445
1446 properties->independentResolveNone = VK_TRUE;
1447 properties->independentResolve = VK_TRUE;
1448 break;
1449 }
1450 default:
1451 break;
1452 }
1453 }
1454 }
1455
1456 static void radv_get_physical_device_queue_family_properties(
1457 struct radv_physical_device* pdevice,
1458 uint32_t* pCount,
1459 VkQueueFamilyProperties** pQueueFamilyProperties)
1460 {
1461 int num_queue_families = 1;
1462 int idx;
1463 if (pdevice->rad_info.num_compute_rings > 0 &&
1464 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1465 num_queue_families++;
1466
1467 if (pQueueFamilyProperties == NULL) {
1468 *pCount = num_queue_families;
1469 return;
1470 }
1471
1472 if (!*pCount)
1473 return;
1474
1475 idx = 0;
1476 if (*pCount >= 1) {
1477 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1478 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1479 VK_QUEUE_COMPUTE_BIT |
1480 VK_QUEUE_TRANSFER_BIT |
1481 VK_QUEUE_SPARSE_BINDING_BIT,
1482 .queueCount = 1,
1483 .timestampValidBits = 64,
1484 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1485 };
1486 idx++;
1487 }
1488
1489 if (pdevice->rad_info.num_compute_rings > 0 &&
1490 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1491 if (*pCount > idx) {
1492 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1493 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1494 VK_QUEUE_TRANSFER_BIT |
1495 VK_QUEUE_SPARSE_BINDING_BIT,
1496 .queueCount = pdevice->rad_info.num_compute_rings,
1497 .timestampValidBits = 64,
1498 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1499 };
1500 idx++;
1501 }
1502 }
1503 *pCount = idx;
1504 }
1505
1506 void radv_GetPhysicalDeviceQueueFamilyProperties(
1507 VkPhysicalDevice physicalDevice,
1508 uint32_t* pCount,
1509 VkQueueFamilyProperties* pQueueFamilyProperties)
1510 {
1511 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1512 if (!pQueueFamilyProperties) {
1513 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1514 return;
1515 }
1516 VkQueueFamilyProperties *properties[] = {
1517 pQueueFamilyProperties + 0,
1518 pQueueFamilyProperties + 1,
1519 pQueueFamilyProperties + 2,
1520 };
1521 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1522 assert(*pCount <= 3);
1523 }
1524
1525 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1526 VkPhysicalDevice physicalDevice,
1527 uint32_t* pCount,
1528 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1529 {
1530 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1531 if (!pQueueFamilyProperties) {
1532 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1533 return;
1534 }
1535 VkQueueFamilyProperties *properties[] = {
1536 &pQueueFamilyProperties[0].queueFamilyProperties,
1537 &pQueueFamilyProperties[1].queueFamilyProperties,
1538 &pQueueFamilyProperties[2].queueFamilyProperties,
1539 };
1540 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1541 assert(*pCount <= 3);
1542 }
1543
1544 void radv_GetPhysicalDeviceMemoryProperties(
1545 VkPhysicalDevice physicalDevice,
1546 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1547 {
1548 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1549
1550 *pMemoryProperties = physical_device->memory_properties;
1551 }
1552
1553 static void
1554 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1555 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1556 {
1557 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1558 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1559 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1560 uint64_t vram_size = radv_get_vram_size(device);
1561 uint64_t gtt_size = device->rad_info.gart_size;
1562 uint64_t heap_budget, heap_usage;
1563
1564 /* For all memory heaps, the computation of budget is as follow:
1565 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1566 *
1567 * The Vulkan spec 1.1.97 says that the budget should include any
1568 * currently allocated device memory.
1569 *
1570 * Note that the application heap usages are not really accurate (eg.
1571 * in presence of shared buffers).
1572 */
1573 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1574 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1575
1576 switch (device->mem_type_indices[i]) {
1577 case RADV_MEM_TYPE_VRAM:
1578 heap_usage = device->ws->query_value(device->ws,
1579 RADEON_ALLOCATED_VRAM);
1580
1581 heap_budget = vram_size -
1582 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1583 heap_usage;
1584
1585 memoryBudget->heapBudget[heap_index] = heap_budget;
1586 memoryBudget->heapUsage[heap_index] = heap_usage;
1587 break;
1588 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1589 heap_usage = device->ws->query_value(device->ws,
1590 RADEON_ALLOCATED_VRAM_VIS);
1591
1592 heap_budget = visible_vram_size -
1593 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1594 heap_usage;
1595
1596 memoryBudget->heapBudget[heap_index] = heap_budget;
1597 memoryBudget->heapUsage[heap_index] = heap_usage;
1598 break;
1599 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1600 heap_usage = device->ws->query_value(device->ws,
1601 RADEON_ALLOCATED_GTT);
1602
1603 heap_budget = gtt_size -
1604 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1605 heap_usage;
1606
1607 memoryBudget->heapBudget[heap_index] = heap_budget;
1608 memoryBudget->heapUsage[heap_index] = heap_usage;
1609 break;
1610 default:
1611 break;
1612 }
1613 }
1614
1615 /* The heapBudget and heapUsage values must be zero for array elements
1616 * greater than or equal to
1617 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1618 */
1619 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1620 memoryBudget->heapBudget[i] = 0;
1621 memoryBudget->heapUsage[i] = 0;
1622 }
1623 }
1624
1625 void radv_GetPhysicalDeviceMemoryProperties2(
1626 VkPhysicalDevice physicalDevice,
1627 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1628 {
1629 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1630 &pMemoryProperties->memoryProperties);
1631
1632 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1633 vk_find_struct(pMemoryProperties->pNext,
1634 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1635 if (memory_budget)
1636 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1637 }
1638
1639 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1640 VkDevice _device,
1641 VkExternalMemoryHandleTypeFlagBits handleType,
1642 const void *pHostPointer,
1643 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1644 {
1645 RADV_FROM_HANDLE(radv_device, device, _device);
1646
1647 switch (handleType)
1648 {
1649 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1650 const struct radv_physical_device *physical_device = device->physical_device;
1651 uint32_t memoryTypeBits = 0;
1652 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1653 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1654 memoryTypeBits = (1 << i);
1655 break;
1656 }
1657 }
1658 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1659 return VK_SUCCESS;
1660 }
1661 default:
1662 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1663 }
1664 }
1665
1666 static enum radeon_ctx_priority
1667 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1668 {
1669 /* Default to MEDIUM when a specific global priority isn't requested */
1670 if (!pObj)
1671 return RADEON_CTX_PRIORITY_MEDIUM;
1672
1673 switch(pObj->globalPriority) {
1674 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1675 return RADEON_CTX_PRIORITY_REALTIME;
1676 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1677 return RADEON_CTX_PRIORITY_HIGH;
1678 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1679 return RADEON_CTX_PRIORITY_MEDIUM;
1680 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1681 return RADEON_CTX_PRIORITY_LOW;
1682 default:
1683 unreachable("Illegal global priority value");
1684 return RADEON_CTX_PRIORITY_INVALID;
1685 }
1686 }
1687
1688 static int
1689 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1690 uint32_t queue_family_index, int idx,
1691 VkDeviceQueueCreateFlags flags,
1692 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1693 {
1694 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1695 queue->device = device;
1696 queue->queue_family_index = queue_family_index;
1697 queue->queue_idx = idx;
1698 queue->priority = radv_get_queue_global_priority(global_priority);
1699 queue->flags = flags;
1700
1701 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1702 if (!queue->hw_ctx)
1703 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1704
1705 return VK_SUCCESS;
1706 }
1707
1708 static void
1709 radv_queue_finish(struct radv_queue *queue)
1710 {
1711 if (queue->hw_ctx)
1712 queue->device->ws->ctx_destroy(queue->hw_ctx);
1713
1714 if (queue->initial_full_flush_preamble_cs)
1715 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1716 if (queue->initial_preamble_cs)
1717 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1718 if (queue->continue_preamble_cs)
1719 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1720 if (queue->descriptor_bo)
1721 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1722 if (queue->scratch_bo)
1723 queue->device->ws->buffer_destroy(queue->scratch_bo);
1724 if (queue->esgs_ring_bo)
1725 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1726 if (queue->gsvs_ring_bo)
1727 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1728 if (queue->tess_rings_bo)
1729 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1730 if (queue->compute_scratch_bo)
1731 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1732 }
1733
1734 static void
1735 radv_bo_list_init(struct radv_bo_list *bo_list)
1736 {
1737 pthread_mutex_init(&bo_list->mutex, NULL);
1738 bo_list->list.count = bo_list->capacity = 0;
1739 bo_list->list.bos = NULL;
1740 }
1741
1742 static void
1743 radv_bo_list_finish(struct radv_bo_list *bo_list)
1744 {
1745 free(bo_list->list.bos);
1746 pthread_mutex_destroy(&bo_list->mutex);
1747 }
1748
1749 static VkResult radv_bo_list_add(struct radv_device *device,
1750 struct radeon_winsys_bo *bo)
1751 {
1752 struct radv_bo_list *bo_list = &device->bo_list;
1753
1754 if (bo->is_local)
1755 return VK_SUCCESS;
1756
1757 if (unlikely(!device->use_global_bo_list))
1758 return VK_SUCCESS;
1759
1760 pthread_mutex_lock(&bo_list->mutex);
1761 if (bo_list->list.count == bo_list->capacity) {
1762 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1763 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1764
1765 if (!data) {
1766 pthread_mutex_unlock(&bo_list->mutex);
1767 return VK_ERROR_OUT_OF_HOST_MEMORY;
1768 }
1769
1770 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1771 bo_list->capacity = capacity;
1772 }
1773
1774 bo_list->list.bos[bo_list->list.count++] = bo;
1775 pthread_mutex_unlock(&bo_list->mutex);
1776 return VK_SUCCESS;
1777 }
1778
1779 static void radv_bo_list_remove(struct radv_device *device,
1780 struct radeon_winsys_bo *bo)
1781 {
1782 struct radv_bo_list *bo_list = &device->bo_list;
1783
1784 if (bo->is_local)
1785 return;
1786
1787 if (unlikely(!device->use_global_bo_list))
1788 return;
1789
1790 pthread_mutex_lock(&bo_list->mutex);
1791 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1792 if (bo_list->list.bos[i] == bo) {
1793 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1794 --bo_list->list.count;
1795 break;
1796 }
1797 }
1798 pthread_mutex_unlock(&bo_list->mutex);
1799 }
1800
1801 static void
1802 radv_device_init_gs_info(struct radv_device *device)
1803 {
1804 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1805 device->physical_device->rad_info.family);
1806 }
1807
1808 static int radv_get_device_extension_index(const char *name)
1809 {
1810 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1811 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1812 return i;
1813 }
1814 return -1;
1815 }
1816
1817 static int
1818 radv_get_int_debug_option(const char *name, int default_value)
1819 {
1820 const char *str;
1821 int result;
1822
1823 str = getenv(name);
1824 if (!str) {
1825 result = default_value;
1826 } else {
1827 char *endptr;
1828
1829 result = strtol(str, &endptr, 0);
1830 if (str == endptr) {
1831 /* No digits founs. */
1832 result = default_value;
1833 }
1834 }
1835
1836 return result;
1837 }
1838
1839 VkResult radv_CreateDevice(
1840 VkPhysicalDevice physicalDevice,
1841 const VkDeviceCreateInfo* pCreateInfo,
1842 const VkAllocationCallbacks* pAllocator,
1843 VkDevice* pDevice)
1844 {
1845 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1846 VkResult result;
1847 struct radv_device *device;
1848
1849 bool keep_shader_info = false;
1850
1851 /* Check enabled features */
1852 if (pCreateInfo->pEnabledFeatures) {
1853 VkPhysicalDeviceFeatures supported_features;
1854 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1855 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1856 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1857 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1858 for (uint32_t i = 0; i < num_features; i++) {
1859 if (enabled_feature[i] && !supported_feature[i])
1860 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1861 }
1862 }
1863
1864 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1865 sizeof(*device), 8,
1866 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1867 if (!device)
1868 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1869
1870 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1871 device->instance = physical_device->instance;
1872 device->physical_device = physical_device;
1873
1874 device->ws = physical_device->ws;
1875 if (pAllocator)
1876 device->alloc = *pAllocator;
1877 else
1878 device->alloc = physical_device->instance->alloc;
1879
1880 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1881 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1882 int index = radv_get_device_extension_index(ext_name);
1883 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1884 vk_free(&device->alloc, device);
1885 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1886 }
1887
1888 device->enabled_extensions.extensions[index] = true;
1889 }
1890
1891 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1892
1893 /* With update after bind we can't attach bo's to the command buffer
1894 * from the descriptor set anymore, so we have to use a global BO list.
1895 */
1896 device->use_global_bo_list =
1897 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1898 device->enabled_extensions.EXT_descriptor_indexing ||
1899 device->enabled_extensions.EXT_buffer_device_address;
1900
1901 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
1902 pCreateInfo->pEnabledFeatures->robustBufferAccess;
1903
1904 mtx_init(&device->shader_slab_mutex, mtx_plain);
1905 list_inithead(&device->shader_slabs);
1906
1907 radv_bo_list_init(&device->bo_list);
1908
1909 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1910 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1911 uint32_t qfi = queue_create->queueFamilyIndex;
1912 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1913 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1914
1915 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1916
1917 device->queues[qfi] = vk_alloc(&device->alloc,
1918 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1919 if (!device->queues[qfi]) {
1920 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1921 goto fail;
1922 }
1923
1924 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1925
1926 device->queue_count[qfi] = queue_create->queueCount;
1927
1928 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1929 result = radv_queue_init(device, &device->queues[qfi][q],
1930 qfi, q, queue_create->flags,
1931 global_priority);
1932 if (result != VK_SUCCESS)
1933 goto fail;
1934 }
1935 }
1936
1937 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1938 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1939
1940 device->dfsm_allowed = device->pbb_allowed &&
1941 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1942 device->physical_device->rad_info.family == CHIP_RAVEN2 ||
1943 device->physical_device->rad_info.family == CHIP_RENOIR);
1944
1945 #ifdef ANDROID
1946 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1947 #endif
1948
1949 /* The maximum number of scratch waves. Scratch space isn't divided
1950 * evenly between CUs. The number is only a function of the number of CUs.
1951 * We can decrease the constant to decrease the scratch buffer size.
1952 *
1953 * sctx->scratch_waves must be >= the maximum possible size of
1954 * 1 threadgroup, so that the hw doesn't hang from being unable
1955 * to start any.
1956 *
1957 * The recommended value is 4 per CU at most. Higher numbers don't
1958 * bring much benefit, but they still occupy chip resources (think
1959 * async compute). I've seen ~2% performance difference between 4 and 32.
1960 */
1961 uint32_t max_threads_per_block = 2048;
1962 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1963 max_threads_per_block / 64);
1964
1965 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1966 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1967
1968 if (device->physical_device->rad_info.chip_class >= GFX7) {
1969 /* If the KMD allows it (there is a KMD hw register for it),
1970 * allow launching waves out-of-order.
1971 */
1972 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1973 }
1974
1975 radv_device_init_gs_info(device);
1976
1977 device->tess_offchip_block_dw_size =
1978 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1979
1980 if (getenv("RADV_TRACE_FILE")) {
1981 const char *filename = getenv("RADV_TRACE_FILE");
1982
1983 keep_shader_info = true;
1984
1985 if (!radv_init_trace(device))
1986 goto fail;
1987
1988 fprintf(stderr, "*****************************************************************************\n");
1989 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1990 fprintf(stderr, "*****************************************************************************\n");
1991
1992 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1993 radv_dump_enabled_options(device, stderr);
1994 }
1995
1996 device->keep_shader_info = keep_shader_info;
1997
1998 result = radv_device_init_meta(device);
1999 if (result != VK_SUCCESS)
2000 goto fail;
2001
2002 radv_device_init_msaa(device);
2003
2004 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2005 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2006 switch (family) {
2007 case RADV_QUEUE_GENERAL:
2008 /* Since amdgpu version 3.6.0, CONTEXT_CONTROL is emitted by the kernel */
2009 if (device->physical_device->rad_info.drm_minor < 6) {
2010 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2011 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2012 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2013 }
2014 break;
2015 case RADV_QUEUE_COMPUTE:
2016 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2017 radeon_emit(device->empty_cs[family], 0);
2018 break;
2019 }
2020 device->ws->cs_finalize(device->empty_cs[family]);
2021 }
2022
2023 if (device->physical_device->rad_info.chip_class >= GFX7)
2024 cik_create_gfx_config(device);
2025
2026 VkPipelineCacheCreateInfo ci;
2027 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2028 ci.pNext = NULL;
2029 ci.flags = 0;
2030 ci.pInitialData = NULL;
2031 ci.initialDataSize = 0;
2032 VkPipelineCache pc;
2033 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2034 &ci, NULL, &pc);
2035 if (result != VK_SUCCESS)
2036 goto fail_meta;
2037
2038 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2039
2040 device->force_aniso =
2041 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2042 if (device->force_aniso >= 0) {
2043 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2044 1 << util_logbase2(device->force_aniso));
2045 }
2046
2047 *pDevice = radv_device_to_handle(device);
2048 return VK_SUCCESS;
2049
2050 fail_meta:
2051 radv_device_finish_meta(device);
2052 fail:
2053 radv_bo_list_finish(&device->bo_list);
2054
2055 if (device->trace_bo)
2056 device->ws->buffer_destroy(device->trace_bo);
2057
2058 if (device->gfx_init)
2059 device->ws->buffer_destroy(device->gfx_init);
2060
2061 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2062 for (unsigned q = 0; q < device->queue_count[i]; q++)
2063 radv_queue_finish(&device->queues[i][q]);
2064 if (device->queue_count[i])
2065 vk_free(&device->alloc, device->queues[i]);
2066 }
2067
2068 vk_free(&device->alloc, device);
2069 return result;
2070 }
2071
2072 void radv_DestroyDevice(
2073 VkDevice _device,
2074 const VkAllocationCallbacks* pAllocator)
2075 {
2076 RADV_FROM_HANDLE(radv_device, device, _device);
2077
2078 if (!device)
2079 return;
2080
2081 if (device->trace_bo)
2082 device->ws->buffer_destroy(device->trace_bo);
2083
2084 if (device->gfx_init)
2085 device->ws->buffer_destroy(device->gfx_init);
2086
2087 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2088 for (unsigned q = 0; q < device->queue_count[i]; q++)
2089 radv_queue_finish(&device->queues[i][q]);
2090 if (device->queue_count[i])
2091 vk_free(&device->alloc, device->queues[i]);
2092 if (device->empty_cs[i])
2093 device->ws->cs_destroy(device->empty_cs[i]);
2094 }
2095 radv_device_finish_meta(device);
2096
2097 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2098 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2099
2100 radv_destroy_shader_slabs(device);
2101
2102 radv_bo_list_finish(&device->bo_list);
2103 vk_free(&device->alloc, device);
2104 }
2105
2106 VkResult radv_EnumerateInstanceLayerProperties(
2107 uint32_t* pPropertyCount,
2108 VkLayerProperties* pProperties)
2109 {
2110 if (pProperties == NULL) {
2111 *pPropertyCount = 0;
2112 return VK_SUCCESS;
2113 }
2114
2115 /* None supported at this time */
2116 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2117 }
2118
2119 VkResult radv_EnumerateDeviceLayerProperties(
2120 VkPhysicalDevice physicalDevice,
2121 uint32_t* pPropertyCount,
2122 VkLayerProperties* pProperties)
2123 {
2124 if (pProperties == NULL) {
2125 *pPropertyCount = 0;
2126 return VK_SUCCESS;
2127 }
2128
2129 /* None supported at this time */
2130 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2131 }
2132
2133 void radv_GetDeviceQueue2(
2134 VkDevice _device,
2135 const VkDeviceQueueInfo2* pQueueInfo,
2136 VkQueue* pQueue)
2137 {
2138 RADV_FROM_HANDLE(radv_device, device, _device);
2139 struct radv_queue *queue;
2140
2141 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2142 if (pQueueInfo->flags != queue->flags) {
2143 /* From the Vulkan 1.1.70 spec:
2144 *
2145 * "The queue returned by vkGetDeviceQueue2 must have the same
2146 * flags value from this structure as that used at device
2147 * creation time in a VkDeviceQueueCreateInfo instance. If no
2148 * matching flags were specified at device creation time then
2149 * pQueue will return VK_NULL_HANDLE."
2150 */
2151 *pQueue = VK_NULL_HANDLE;
2152 return;
2153 }
2154
2155 *pQueue = radv_queue_to_handle(queue);
2156 }
2157
2158 void radv_GetDeviceQueue(
2159 VkDevice _device,
2160 uint32_t queueFamilyIndex,
2161 uint32_t queueIndex,
2162 VkQueue* pQueue)
2163 {
2164 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2165 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2166 .queueFamilyIndex = queueFamilyIndex,
2167 .queueIndex = queueIndex
2168 };
2169
2170 radv_GetDeviceQueue2(_device, &info, pQueue);
2171 }
2172
2173 static void
2174 fill_geom_tess_rings(struct radv_queue *queue,
2175 uint32_t *map,
2176 bool add_sample_positions,
2177 uint32_t esgs_ring_size,
2178 struct radeon_winsys_bo *esgs_ring_bo,
2179 uint32_t gsvs_ring_size,
2180 struct radeon_winsys_bo *gsvs_ring_bo,
2181 uint32_t tess_factor_ring_size,
2182 uint32_t tess_offchip_ring_offset,
2183 uint32_t tess_offchip_ring_size,
2184 struct radeon_winsys_bo *tess_rings_bo)
2185 {
2186 uint32_t *desc = &map[4];
2187
2188 if (esgs_ring_bo) {
2189 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2190
2191 /* stride 0, num records - size, add tid, swizzle, elsize4,
2192 index stride 64 */
2193 desc[0] = esgs_va;
2194 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2195 S_008F04_SWIZZLE_ENABLE(true);
2196 desc[2] = esgs_ring_size;
2197 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2198 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2199 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2200 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2201 S_008F0C_INDEX_STRIDE(3) |
2202 S_008F0C_ADD_TID_ENABLE(1);
2203
2204 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2205 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2206 S_008F0C_OOB_SELECT(2) |
2207 S_008F0C_RESOURCE_LEVEL(1);
2208 } else {
2209 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2210 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2211 S_008F0C_ELEMENT_SIZE(1);
2212 }
2213
2214 /* GS entry for ES->GS ring */
2215 /* stride 0, num records - size, elsize0,
2216 index stride 0 */
2217 desc[4] = esgs_va;
2218 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2219 desc[6] = esgs_ring_size;
2220 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2221 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2222 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2223 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2224
2225 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2226 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2227 S_008F0C_OOB_SELECT(2) |
2228 S_008F0C_RESOURCE_LEVEL(1);
2229 } else {
2230 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2231 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2232 }
2233 }
2234
2235 desc += 8;
2236
2237 if (gsvs_ring_bo) {
2238 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2239
2240 /* VS entry for GS->VS ring */
2241 /* stride 0, num records - size, elsize0,
2242 index stride 0 */
2243 desc[0] = gsvs_va;
2244 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2245 desc[2] = gsvs_ring_size;
2246 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2247 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2248 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2249 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2250
2251 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2252 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2253 S_008F0C_OOB_SELECT(2) |
2254 S_008F0C_RESOURCE_LEVEL(1);
2255 } else {
2256 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2257 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2258 }
2259
2260 /* stride gsvs_itemsize, num records 64
2261 elsize 4, index stride 16 */
2262 /* shader will patch stride and desc[2] */
2263 desc[4] = gsvs_va;
2264 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2265 S_008F04_SWIZZLE_ENABLE(1);
2266 desc[6] = 0;
2267 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2268 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2269 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2270 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2271 S_008F0C_INDEX_STRIDE(1) |
2272 S_008F0C_ADD_TID_ENABLE(true);
2273
2274 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2275 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2276 S_008F0C_OOB_SELECT(2) |
2277 S_008F0C_RESOURCE_LEVEL(1);
2278 } else {
2279 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2280 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2281 S_008F0C_ELEMENT_SIZE(1);
2282 }
2283
2284 }
2285
2286 desc += 8;
2287
2288 if (tess_rings_bo) {
2289 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2290 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2291
2292 desc[0] = tess_va;
2293 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2294 desc[2] = tess_factor_ring_size;
2295 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2296 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2297 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2298 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2299
2300 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2301 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2302 S_008F0C_OOB_SELECT(3) |
2303 S_008F0C_RESOURCE_LEVEL(1);
2304 } else {
2305 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2306 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2307 }
2308
2309 desc[4] = tess_offchip_va;
2310 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2311 desc[6] = tess_offchip_ring_size;
2312 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2313 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2314 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2315 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2316
2317 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2318 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2319 S_008F0C_OOB_SELECT(3) |
2320 S_008F0C_RESOURCE_LEVEL(1);
2321 } else {
2322 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2323 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2324 }
2325 }
2326
2327 desc += 8;
2328
2329 if (add_sample_positions) {
2330 /* add sample positions after all rings */
2331 memcpy(desc, queue->device->sample_locations_1x, 8);
2332 desc += 2;
2333 memcpy(desc, queue->device->sample_locations_2x, 16);
2334 desc += 4;
2335 memcpy(desc, queue->device->sample_locations_4x, 32);
2336 desc += 8;
2337 memcpy(desc, queue->device->sample_locations_8x, 64);
2338 }
2339 }
2340
2341 static unsigned
2342 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2343 {
2344 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2345 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2346 device->physical_device->rad_info.family != CHIP_STONEY;
2347 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2348 unsigned max_offchip_buffers;
2349 unsigned offchip_granularity;
2350 unsigned hs_offchip_param;
2351
2352 /*
2353 * Per RadeonSI:
2354 * This must be one less than the maximum number due to a hw limitation.
2355 * Various hardware bugs need thGFX7
2356 *
2357 * Per AMDVLK:
2358 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2359 * Gfx7 should limit max_offchip_buffers to 508
2360 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2361 *
2362 * Follow AMDVLK here.
2363 */
2364 if (device->physical_device->rad_info.chip_class >= GFX10) {
2365 max_offchip_buffers_per_se = 256;
2366 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2367 device->physical_device->rad_info.chip_class == GFX7 ||
2368 device->physical_device->rad_info.chip_class == GFX6)
2369 --max_offchip_buffers_per_se;
2370
2371 max_offchip_buffers = max_offchip_buffers_per_se *
2372 device->physical_device->rad_info.max_se;
2373
2374 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2375 * around by setting 4K granularity.
2376 */
2377 if (device->tess_offchip_block_dw_size == 4096) {
2378 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2379 offchip_granularity = V_03093C_X_4K_DWORDS;
2380 } else {
2381 assert(device->tess_offchip_block_dw_size == 8192);
2382 offchip_granularity = V_03093C_X_8K_DWORDS;
2383 }
2384
2385 switch (device->physical_device->rad_info.chip_class) {
2386 case GFX6:
2387 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2388 break;
2389 case GFX7:
2390 case GFX8:
2391 case GFX9:
2392 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2393 break;
2394 case GFX10:
2395 break;
2396 default:
2397 break;
2398 }
2399
2400 *max_offchip_buffers_p = max_offchip_buffers;
2401 if (device->physical_device->rad_info.chip_class >= GFX7) {
2402 if (device->physical_device->rad_info.chip_class >= GFX8)
2403 --max_offchip_buffers;
2404 hs_offchip_param =
2405 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2406 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2407 } else {
2408 hs_offchip_param =
2409 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2410 }
2411 return hs_offchip_param;
2412 }
2413
2414 static void
2415 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2416 struct radeon_winsys_bo *esgs_ring_bo,
2417 uint32_t esgs_ring_size,
2418 struct radeon_winsys_bo *gsvs_ring_bo,
2419 uint32_t gsvs_ring_size)
2420 {
2421 if (!esgs_ring_bo && !gsvs_ring_bo)
2422 return;
2423
2424 if (esgs_ring_bo)
2425 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2426
2427 if (gsvs_ring_bo)
2428 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2429
2430 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2431 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2432 radeon_emit(cs, esgs_ring_size >> 8);
2433 radeon_emit(cs, gsvs_ring_size >> 8);
2434 } else {
2435 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2436 radeon_emit(cs, esgs_ring_size >> 8);
2437 radeon_emit(cs, gsvs_ring_size >> 8);
2438 }
2439 }
2440
2441 static void
2442 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2443 unsigned hs_offchip_param, unsigned tf_ring_size,
2444 struct radeon_winsys_bo *tess_rings_bo)
2445 {
2446 uint64_t tf_va;
2447
2448 if (!tess_rings_bo)
2449 return;
2450
2451 tf_va = radv_buffer_get_va(tess_rings_bo);
2452
2453 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2454
2455 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2456 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2457 S_030938_SIZE(tf_ring_size / 4));
2458 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2459 tf_va >> 8);
2460
2461 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2462 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2463 S_030984_BASE_HI(tf_va >> 40));
2464 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2465 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2466 S_030944_BASE_HI(tf_va >> 40));
2467 }
2468 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2469 hs_offchip_param);
2470 } else {
2471 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2472 S_008988_SIZE(tf_ring_size / 4));
2473 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2474 tf_va >> 8);
2475 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2476 hs_offchip_param);
2477 }
2478 }
2479
2480 static void
2481 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2482 struct radeon_winsys_bo *compute_scratch_bo)
2483 {
2484 uint64_t scratch_va;
2485
2486 if (!compute_scratch_bo)
2487 return;
2488
2489 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2490
2491 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2492
2493 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2494 radeon_emit(cs, scratch_va);
2495 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2496 S_008F04_SWIZZLE_ENABLE(1));
2497 }
2498
2499 static void
2500 radv_emit_global_shader_pointers(struct radv_queue *queue,
2501 struct radeon_cmdbuf *cs,
2502 struct radeon_winsys_bo *descriptor_bo)
2503 {
2504 uint64_t va;
2505
2506 if (!descriptor_bo)
2507 return;
2508
2509 va = radv_buffer_get_va(descriptor_bo);
2510
2511 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2512
2513 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2514 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2515 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2516 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2517 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2518
2519 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2520 radv_emit_shader_pointer(queue->device, cs, regs[i],
2521 va, true);
2522 }
2523 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2524 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2525 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2526 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2527 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2528
2529 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2530 radv_emit_shader_pointer(queue->device, cs, regs[i],
2531 va, true);
2532 }
2533 } else {
2534 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2535 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2536 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2537 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2538 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2539 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2540
2541 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2542 radv_emit_shader_pointer(queue->device, cs, regs[i],
2543 va, true);
2544 }
2545 }
2546 }
2547
2548 static void
2549 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2550 {
2551 struct radv_device *device = queue->device;
2552
2553 if (device->gfx_init) {
2554 uint64_t va = radv_buffer_get_va(device->gfx_init);
2555
2556 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2557 radeon_emit(cs, va);
2558 radeon_emit(cs, va >> 32);
2559 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2560
2561 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2562 } else {
2563 struct radv_physical_device *physical_device = device->physical_device;
2564 si_emit_graphics(physical_device, cs);
2565 }
2566 }
2567
2568 static void
2569 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2570 {
2571 struct radv_physical_device *physical_device = queue->device->physical_device;
2572 si_emit_compute(physical_device, cs);
2573 }
2574
2575 static VkResult
2576 radv_get_preamble_cs(struct radv_queue *queue,
2577 uint32_t scratch_size,
2578 uint32_t compute_scratch_size,
2579 uint32_t esgs_ring_size,
2580 uint32_t gsvs_ring_size,
2581 bool needs_tess_rings,
2582 bool needs_sample_positions,
2583 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2584 struct radeon_cmdbuf **initial_preamble_cs,
2585 struct radeon_cmdbuf **continue_preamble_cs)
2586 {
2587 struct radeon_winsys_bo *scratch_bo = NULL;
2588 struct radeon_winsys_bo *descriptor_bo = NULL;
2589 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2590 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2591 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2592 struct radeon_winsys_bo *tess_rings_bo = NULL;
2593 struct radeon_cmdbuf *dest_cs[3] = {0};
2594 bool add_tess_rings = false, add_sample_positions = false;
2595 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2596 unsigned max_offchip_buffers;
2597 unsigned hs_offchip_param = 0;
2598 unsigned tess_offchip_ring_offset;
2599 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2600 if (!queue->has_tess_rings) {
2601 if (needs_tess_rings)
2602 add_tess_rings = true;
2603 }
2604 if (!queue->has_sample_positions) {
2605 if (needs_sample_positions)
2606 add_sample_positions = true;
2607 }
2608 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2609 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2610 &max_offchip_buffers);
2611 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2612 tess_offchip_ring_size = max_offchip_buffers *
2613 queue->device->tess_offchip_block_dw_size * 4;
2614
2615 if (scratch_size <= queue->scratch_size &&
2616 compute_scratch_size <= queue->compute_scratch_size &&
2617 esgs_ring_size <= queue->esgs_ring_size &&
2618 gsvs_ring_size <= queue->gsvs_ring_size &&
2619 !add_tess_rings && !add_sample_positions &&
2620 queue->initial_preamble_cs) {
2621 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2622 *initial_preamble_cs = queue->initial_preamble_cs;
2623 *continue_preamble_cs = queue->continue_preamble_cs;
2624 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2625 *continue_preamble_cs = NULL;
2626 return VK_SUCCESS;
2627 }
2628
2629 if (scratch_size > queue->scratch_size) {
2630 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2631 scratch_size,
2632 4096,
2633 RADEON_DOMAIN_VRAM,
2634 ring_bo_flags,
2635 RADV_BO_PRIORITY_SCRATCH);
2636 if (!scratch_bo)
2637 goto fail;
2638 } else
2639 scratch_bo = queue->scratch_bo;
2640
2641 if (compute_scratch_size > queue->compute_scratch_size) {
2642 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2643 compute_scratch_size,
2644 4096,
2645 RADEON_DOMAIN_VRAM,
2646 ring_bo_flags,
2647 RADV_BO_PRIORITY_SCRATCH);
2648 if (!compute_scratch_bo)
2649 goto fail;
2650
2651 } else
2652 compute_scratch_bo = queue->compute_scratch_bo;
2653
2654 if (esgs_ring_size > queue->esgs_ring_size) {
2655 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2656 esgs_ring_size,
2657 4096,
2658 RADEON_DOMAIN_VRAM,
2659 ring_bo_flags,
2660 RADV_BO_PRIORITY_SCRATCH);
2661 if (!esgs_ring_bo)
2662 goto fail;
2663 } else {
2664 esgs_ring_bo = queue->esgs_ring_bo;
2665 esgs_ring_size = queue->esgs_ring_size;
2666 }
2667
2668 if (gsvs_ring_size > queue->gsvs_ring_size) {
2669 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2670 gsvs_ring_size,
2671 4096,
2672 RADEON_DOMAIN_VRAM,
2673 ring_bo_flags,
2674 RADV_BO_PRIORITY_SCRATCH);
2675 if (!gsvs_ring_bo)
2676 goto fail;
2677 } else {
2678 gsvs_ring_bo = queue->gsvs_ring_bo;
2679 gsvs_ring_size = queue->gsvs_ring_size;
2680 }
2681
2682 if (add_tess_rings) {
2683 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2684 tess_offchip_ring_offset + tess_offchip_ring_size,
2685 256,
2686 RADEON_DOMAIN_VRAM,
2687 ring_bo_flags,
2688 RADV_BO_PRIORITY_SCRATCH);
2689 if (!tess_rings_bo)
2690 goto fail;
2691 } else {
2692 tess_rings_bo = queue->tess_rings_bo;
2693 }
2694
2695 if (scratch_bo != queue->scratch_bo ||
2696 esgs_ring_bo != queue->esgs_ring_bo ||
2697 gsvs_ring_bo != queue->gsvs_ring_bo ||
2698 tess_rings_bo != queue->tess_rings_bo ||
2699 add_sample_positions) {
2700 uint32_t size = 0;
2701 if (gsvs_ring_bo || esgs_ring_bo ||
2702 tess_rings_bo || add_sample_positions) {
2703 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2704 if (add_sample_positions)
2705 size += 128; /* 64+32+16+8 = 120 bytes */
2706 }
2707 else if (scratch_bo)
2708 size = 8; /* 2 dword */
2709
2710 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2711 size,
2712 4096,
2713 RADEON_DOMAIN_VRAM,
2714 RADEON_FLAG_CPU_ACCESS |
2715 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2716 RADEON_FLAG_READ_ONLY,
2717 RADV_BO_PRIORITY_DESCRIPTOR);
2718 if (!descriptor_bo)
2719 goto fail;
2720 } else
2721 descriptor_bo = queue->descriptor_bo;
2722
2723 if (descriptor_bo != queue->descriptor_bo) {
2724 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2725
2726 if (scratch_bo) {
2727 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2728 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2729 S_008F04_SWIZZLE_ENABLE(1);
2730 map[0] = scratch_va;
2731 map[1] = rsrc1;
2732 }
2733
2734 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2735 fill_geom_tess_rings(queue, map, add_sample_positions,
2736 esgs_ring_size, esgs_ring_bo,
2737 gsvs_ring_size, gsvs_ring_bo,
2738 tess_factor_ring_size,
2739 tess_offchip_ring_offset,
2740 tess_offchip_ring_size,
2741 tess_rings_bo);
2742
2743 queue->device->ws->buffer_unmap(descriptor_bo);
2744 }
2745
2746 for(int i = 0; i < 3; ++i) {
2747 struct radeon_cmdbuf *cs = NULL;
2748 cs = queue->device->ws->cs_create(queue->device->ws,
2749 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2750 if (!cs)
2751 goto fail;
2752
2753 dest_cs[i] = cs;
2754
2755 if (scratch_bo)
2756 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2757
2758 /* Emit initial configuration. */
2759 switch (queue->queue_family_index) {
2760 case RADV_QUEUE_GENERAL:
2761 radv_init_graphics_state(cs, queue);
2762 break;
2763 case RADV_QUEUE_COMPUTE:
2764 radv_init_compute_state(cs, queue);
2765 break;
2766 case RADV_QUEUE_TRANSFER:
2767 break;
2768 }
2769
2770 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2771 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2772 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2773
2774 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2775 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2776 }
2777
2778 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2779 gsvs_ring_bo, gsvs_ring_size);
2780 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2781 tess_factor_ring_size, tess_rings_bo);
2782 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2783 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2784
2785 if (i == 0) {
2786 si_cs_emit_cache_flush(cs,
2787 queue->device->physical_device->rad_info.chip_class,
2788 NULL, 0,
2789 queue->queue_family_index == RING_COMPUTE &&
2790 queue->device->physical_device->rad_info.chip_class >= GFX7,
2791 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2792 RADV_CMD_FLAG_INV_ICACHE |
2793 RADV_CMD_FLAG_INV_SCACHE |
2794 RADV_CMD_FLAG_INV_VCACHE |
2795 RADV_CMD_FLAG_INV_L2 |
2796 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2797 } else if (i == 1) {
2798 si_cs_emit_cache_flush(cs,
2799 queue->device->physical_device->rad_info.chip_class,
2800 NULL, 0,
2801 queue->queue_family_index == RING_COMPUTE &&
2802 queue->device->physical_device->rad_info.chip_class >= GFX7,
2803 RADV_CMD_FLAG_INV_ICACHE |
2804 RADV_CMD_FLAG_INV_SCACHE |
2805 RADV_CMD_FLAG_INV_VCACHE |
2806 RADV_CMD_FLAG_INV_L2 |
2807 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2808 }
2809
2810 if (!queue->device->ws->cs_finalize(cs))
2811 goto fail;
2812 }
2813
2814 if (queue->initial_full_flush_preamble_cs)
2815 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2816
2817 if (queue->initial_preamble_cs)
2818 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2819
2820 if (queue->continue_preamble_cs)
2821 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2822
2823 queue->initial_full_flush_preamble_cs = dest_cs[0];
2824 queue->initial_preamble_cs = dest_cs[1];
2825 queue->continue_preamble_cs = dest_cs[2];
2826
2827 if (scratch_bo != queue->scratch_bo) {
2828 if (queue->scratch_bo)
2829 queue->device->ws->buffer_destroy(queue->scratch_bo);
2830 queue->scratch_bo = scratch_bo;
2831 queue->scratch_size = scratch_size;
2832 }
2833
2834 if (compute_scratch_bo != queue->compute_scratch_bo) {
2835 if (queue->compute_scratch_bo)
2836 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2837 queue->compute_scratch_bo = compute_scratch_bo;
2838 queue->compute_scratch_size = compute_scratch_size;
2839 }
2840
2841 if (esgs_ring_bo != queue->esgs_ring_bo) {
2842 if (queue->esgs_ring_bo)
2843 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2844 queue->esgs_ring_bo = esgs_ring_bo;
2845 queue->esgs_ring_size = esgs_ring_size;
2846 }
2847
2848 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2849 if (queue->gsvs_ring_bo)
2850 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2851 queue->gsvs_ring_bo = gsvs_ring_bo;
2852 queue->gsvs_ring_size = gsvs_ring_size;
2853 }
2854
2855 if (tess_rings_bo != queue->tess_rings_bo) {
2856 queue->tess_rings_bo = tess_rings_bo;
2857 queue->has_tess_rings = true;
2858 }
2859
2860 if (descriptor_bo != queue->descriptor_bo) {
2861 if (queue->descriptor_bo)
2862 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2863
2864 queue->descriptor_bo = descriptor_bo;
2865 }
2866
2867 if (add_sample_positions)
2868 queue->has_sample_positions = true;
2869
2870 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2871 *initial_preamble_cs = queue->initial_preamble_cs;
2872 *continue_preamble_cs = queue->continue_preamble_cs;
2873 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2874 *continue_preamble_cs = NULL;
2875 return VK_SUCCESS;
2876 fail:
2877 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2878 if (dest_cs[i])
2879 queue->device->ws->cs_destroy(dest_cs[i]);
2880 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2881 queue->device->ws->buffer_destroy(descriptor_bo);
2882 if (scratch_bo && scratch_bo != queue->scratch_bo)
2883 queue->device->ws->buffer_destroy(scratch_bo);
2884 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2885 queue->device->ws->buffer_destroy(compute_scratch_bo);
2886 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2887 queue->device->ws->buffer_destroy(esgs_ring_bo);
2888 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2889 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2890 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2891 queue->device->ws->buffer_destroy(tess_rings_bo);
2892 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2893 }
2894
2895 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2896 struct radv_winsys_sem_counts *counts,
2897 int num_sems,
2898 const VkSemaphore *sems,
2899 VkFence _fence,
2900 bool reset_temp)
2901 {
2902 int syncobj_idx = 0, sem_idx = 0;
2903
2904 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2905 return VK_SUCCESS;
2906
2907 for (uint32_t i = 0; i < num_sems; i++) {
2908 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2909
2910 if (sem->temp_syncobj || sem->syncobj)
2911 counts->syncobj_count++;
2912 else
2913 counts->sem_count++;
2914 }
2915
2916 if (_fence != VK_NULL_HANDLE) {
2917 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2918 if (fence->temp_syncobj || fence->syncobj)
2919 counts->syncobj_count++;
2920 }
2921
2922 if (counts->syncobj_count) {
2923 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2924 if (!counts->syncobj)
2925 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2926 }
2927
2928 if (counts->sem_count) {
2929 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2930 if (!counts->sem) {
2931 free(counts->syncobj);
2932 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2933 }
2934 }
2935
2936 for (uint32_t i = 0; i < num_sems; i++) {
2937 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2938
2939 if (sem->temp_syncobj) {
2940 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2941 }
2942 else if (sem->syncobj)
2943 counts->syncobj[syncobj_idx++] = sem->syncobj;
2944 else {
2945 assert(sem->sem);
2946 counts->sem[sem_idx++] = sem->sem;
2947 }
2948 }
2949
2950 if (_fence != VK_NULL_HANDLE) {
2951 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2952 if (fence->temp_syncobj)
2953 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2954 else if (fence->syncobj)
2955 counts->syncobj[syncobj_idx++] = fence->syncobj;
2956 }
2957
2958 return VK_SUCCESS;
2959 }
2960
2961 static void
2962 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2963 {
2964 free(sem_info->wait.syncobj);
2965 free(sem_info->wait.sem);
2966 free(sem_info->signal.syncobj);
2967 free(sem_info->signal.sem);
2968 }
2969
2970
2971 static void radv_free_temp_syncobjs(struct radv_device *device,
2972 int num_sems,
2973 const VkSemaphore *sems)
2974 {
2975 for (uint32_t i = 0; i < num_sems; i++) {
2976 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2977
2978 if (sem->temp_syncobj) {
2979 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2980 sem->temp_syncobj = 0;
2981 }
2982 }
2983 }
2984
2985 static VkResult
2986 radv_alloc_sem_info(struct radv_instance *instance,
2987 struct radv_winsys_sem_info *sem_info,
2988 int num_wait_sems,
2989 const VkSemaphore *wait_sems,
2990 int num_signal_sems,
2991 const VkSemaphore *signal_sems,
2992 VkFence fence)
2993 {
2994 VkResult ret;
2995 memset(sem_info, 0, sizeof(*sem_info));
2996
2997 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2998 if (ret)
2999 return ret;
3000 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
3001 if (ret)
3002 radv_free_sem_info(sem_info);
3003
3004 /* caller can override these */
3005 sem_info->cs_emit_wait = true;
3006 sem_info->cs_emit_signal = true;
3007 return ret;
3008 }
3009
3010 /* Signals fence as soon as all the work currently put on queue is done. */
3011 static VkResult radv_signal_fence(struct radv_queue *queue,
3012 struct radv_fence *fence)
3013 {
3014 int ret;
3015 VkResult result;
3016 struct radv_winsys_sem_info sem_info;
3017
3018 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3019 radv_fence_to_handle(fence));
3020 if (result != VK_SUCCESS)
3021 return result;
3022
3023 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3024 &queue->device->empty_cs[queue->queue_family_index],
3025 1, NULL, NULL, &sem_info, NULL,
3026 false, fence->fence);
3027 radv_free_sem_info(&sem_info);
3028
3029 if (ret)
3030 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3031
3032 return VK_SUCCESS;
3033 }
3034
3035 VkResult radv_QueueSubmit(
3036 VkQueue _queue,
3037 uint32_t submitCount,
3038 const VkSubmitInfo* pSubmits,
3039 VkFence _fence)
3040 {
3041 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3042 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3043 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3044 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3045 int ret;
3046 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3047 uint32_t scratch_size = 0;
3048 uint32_t compute_scratch_size = 0;
3049 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3050 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3051 VkResult result;
3052 bool fence_emitted = false;
3053 bool tess_rings_needed = false;
3054 bool sample_positions_needed = false;
3055
3056 /* Do this first so failing to allocate scratch buffers can't result in
3057 * partially executed submissions. */
3058 for (uint32_t i = 0; i < submitCount; i++) {
3059 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3060 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3061 pSubmits[i].pCommandBuffers[j]);
3062
3063 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3064 compute_scratch_size = MAX2(compute_scratch_size,
3065 cmd_buffer->compute_scratch_size_needed);
3066 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3067 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3068 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3069 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3070 }
3071 }
3072
3073 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3074 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3075 sample_positions_needed, &initial_flush_preamble_cs,
3076 &initial_preamble_cs, &continue_preamble_cs);
3077 if (result != VK_SUCCESS)
3078 return result;
3079
3080 for (uint32_t i = 0; i < submitCount; i++) {
3081 struct radeon_cmdbuf **cs_array;
3082 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3083 bool can_patch = true;
3084 uint32_t advance;
3085 struct radv_winsys_sem_info sem_info;
3086
3087 result = radv_alloc_sem_info(queue->device->instance,
3088 &sem_info,
3089 pSubmits[i].waitSemaphoreCount,
3090 pSubmits[i].pWaitSemaphores,
3091 pSubmits[i].signalSemaphoreCount,
3092 pSubmits[i].pSignalSemaphores,
3093 _fence);
3094 if (result != VK_SUCCESS)
3095 return result;
3096
3097 if (!pSubmits[i].commandBufferCount) {
3098 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3099 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3100 &queue->device->empty_cs[queue->queue_family_index],
3101 1, NULL, NULL,
3102 &sem_info, NULL,
3103 false, base_fence);
3104 if (ret) {
3105 radv_loge("failed to submit CS %d\n", i);
3106 abort();
3107 }
3108 fence_emitted = true;
3109 }
3110 radv_free_sem_info(&sem_info);
3111 continue;
3112 }
3113
3114 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3115 (pSubmits[i].commandBufferCount));
3116
3117 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3118 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3119 pSubmits[i].pCommandBuffers[j]);
3120 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3121
3122 cs_array[j] = cmd_buffer->cs;
3123 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3124 can_patch = false;
3125
3126 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3127 }
3128
3129 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3130 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3131 const struct radv_winsys_bo_list *bo_list = NULL;
3132
3133 advance = MIN2(max_cs_submission,
3134 pSubmits[i].commandBufferCount - j);
3135
3136 if (queue->device->trace_bo)
3137 *queue->device->trace_id_ptr = 0;
3138
3139 sem_info.cs_emit_wait = j == 0;
3140 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3141
3142 if (unlikely(queue->device->use_global_bo_list)) {
3143 pthread_mutex_lock(&queue->device->bo_list.mutex);
3144 bo_list = &queue->device->bo_list.list;
3145 }
3146
3147 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3148 advance, initial_preamble, continue_preamble_cs,
3149 &sem_info, bo_list,
3150 can_patch, base_fence);
3151
3152 if (unlikely(queue->device->use_global_bo_list))
3153 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3154
3155 if (ret) {
3156 radv_loge("failed to submit CS %d\n", i);
3157 abort();
3158 }
3159 fence_emitted = true;
3160 if (queue->device->trace_bo) {
3161 radv_check_gpu_hangs(queue, cs_array[j]);
3162 }
3163 }
3164
3165 radv_free_temp_syncobjs(queue->device,
3166 pSubmits[i].waitSemaphoreCount,
3167 pSubmits[i].pWaitSemaphores);
3168 radv_free_sem_info(&sem_info);
3169 free(cs_array);
3170 }
3171
3172 if (fence) {
3173 if (!fence_emitted) {
3174 result = radv_signal_fence(queue, fence);
3175 if (result != VK_SUCCESS)
3176 return result;
3177 }
3178 }
3179
3180 return VK_SUCCESS;
3181 }
3182
3183 VkResult radv_QueueWaitIdle(
3184 VkQueue _queue)
3185 {
3186 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3187
3188 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3189 radv_queue_family_to_ring(queue->queue_family_index),
3190 queue->queue_idx);
3191 return VK_SUCCESS;
3192 }
3193
3194 VkResult radv_DeviceWaitIdle(
3195 VkDevice _device)
3196 {
3197 RADV_FROM_HANDLE(radv_device, device, _device);
3198
3199 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3200 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3201 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3202 }
3203 }
3204 return VK_SUCCESS;
3205 }
3206
3207 VkResult radv_EnumerateInstanceExtensionProperties(
3208 const char* pLayerName,
3209 uint32_t* pPropertyCount,
3210 VkExtensionProperties* pProperties)
3211 {
3212 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3213
3214 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3215 if (radv_supported_instance_extensions.extensions[i]) {
3216 vk_outarray_append(&out, prop) {
3217 *prop = radv_instance_extensions[i];
3218 }
3219 }
3220 }
3221
3222 return vk_outarray_status(&out);
3223 }
3224
3225 VkResult radv_EnumerateDeviceExtensionProperties(
3226 VkPhysicalDevice physicalDevice,
3227 const char* pLayerName,
3228 uint32_t* pPropertyCount,
3229 VkExtensionProperties* pProperties)
3230 {
3231 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3232 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3233
3234 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3235 if (device->supported_extensions.extensions[i]) {
3236 vk_outarray_append(&out, prop) {
3237 *prop = radv_device_extensions[i];
3238 }
3239 }
3240 }
3241
3242 return vk_outarray_status(&out);
3243 }
3244
3245 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3246 VkInstance _instance,
3247 const char* pName)
3248 {
3249 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3250 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3251
3252 if (unchecked) {
3253 return radv_lookup_entrypoint_unchecked(pName);
3254 } else {
3255 return radv_lookup_entrypoint_checked(pName,
3256 instance ? instance->apiVersion : 0,
3257 instance ? &instance->enabled_extensions : NULL,
3258 NULL);
3259 }
3260 }
3261
3262 /* The loader wants us to expose a second GetInstanceProcAddr function
3263 * to work around certain LD_PRELOAD issues seen in apps.
3264 */
3265 PUBLIC
3266 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3267 VkInstance instance,
3268 const char* pName);
3269
3270 PUBLIC
3271 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3272 VkInstance instance,
3273 const char* pName)
3274 {
3275 return radv_GetInstanceProcAddr(instance, pName);
3276 }
3277
3278 PUBLIC
3279 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3280 VkInstance _instance,
3281 const char* pName);
3282
3283 PUBLIC
3284 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3285 VkInstance _instance,
3286 const char* pName)
3287 {
3288 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3289
3290 return radv_lookup_physical_device_entrypoint_checked(pName,
3291 instance ? instance->apiVersion : 0,
3292 instance ? &instance->enabled_extensions : NULL);
3293 }
3294
3295 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3296 VkDevice _device,
3297 const char* pName)
3298 {
3299 RADV_FROM_HANDLE(radv_device, device, _device);
3300 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
3301
3302 if (unchecked) {
3303 return radv_lookup_entrypoint_unchecked(pName);
3304 } else {
3305 return radv_lookup_entrypoint_checked(pName,
3306 device->instance->apiVersion,
3307 &device->instance->enabled_extensions,
3308 &device->enabled_extensions);
3309 }
3310 }
3311
3312 bool radv_get_memory_fd(struct radv_device *device,
3313 struct radv_device_memory *memory,
3314 int *pFD)
3315 {
3316 struct radeon_bo_metadata metadata;
3317
3318 if (memory->image) {
3319 radv_init_metadata(device, memory->image, &metadata);
3320 device->ws->buffer_set_metadata(memory->bo, &metadata);
3321 }
3322
3323 return device->ws->buffer_get_fd(device->ws, memory->bo,
3324 pFD);
3325 }
3326
3327 static VkResult radv_alloc_memory(struct radv_device *device,
3328 const VkMemoryAllocateInfo* pAllocateInfo,
3329 const VkAllocationCallbacks* pAllocator,
3330 VkDeviceMemory* pMem)
3331 {
3332 struct radv_device_memory *mem;
3333 VkResult result;
3334 enum radeon_bo_domain domain;
3335 uint32_t flags = 0;
3336 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3337
3338 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3339
3340 if (pAllocateInfo->allocationSize == 0) {
3341 /* Apparently, this is allowed */
3342 *pMem = VK_NULL_HANDLE;
3343 return VK_SUCCESS;
3344 }
3345
3346 const VkImportMemoryFdInfoKHR *import_info =
3347 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3348 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3349 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3350 const VkExportMemoryAllocateInfo *export_info =
3351 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3352 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3353 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3354
3355 const struct wsi_memory_allocate_info *wsi_info =
3356 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3357
3358 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3359 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3360 if (mem == NULL)
3361 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3362
3363 if (wsi_info && wsi_info->implicit_sync)
3364 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3365
3366 if (dedicate_info) {
3367 mem->image = radv_image_from_handle(dedicate_info->image);
3368 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3369 } else {
3370 mem->image = NULL;
3371 mem->buffer = NULL;
3372 }
3373
3374 float priority_float = 0.5;
3375 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3376 vk_find_struct_const(pAllocateInfo->pNext,
3377 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3378 if (priority_ext)
3379 priority_float = priority_ext->priority;
3380
3381 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3382 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3383
3384 mem->user_ptr = NULL;
3385
3386 if (import_info) {
3387 assert(import_info->handleType ==
3388 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3389 import_info->handleType ==
3390 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3391 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3392 priority, NULL, NULL);
3393 if (!mem->bo) {
3394 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3395 goto fail;
3396 } else {
3397 close(import_info->fd);
3398 }
3399 } else if (host_ptr_info) {
3400 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3401 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3402 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3403 pAllocateInfo->allocationSize,
3404 priority);
3405 if (!mem->bo) {
3406 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3407 goto fail;
3408 } else {
3409 mem->user_ptr = host_ptr_info->pHostPointer;
3410 }
3411 } else {
3412 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3413 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3414 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3415 domain = RADEON_DOMAIN_GTT;
3416 else
3417 domain = RADEON_DOMAIN_VRAM;
3418
3419 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3420 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3421 else
3422 flags |= RADEON_FLAG_CPU_ACCESS;
3423
3424 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3425 flags |= RADEON_FLAG_GTT_WC;
3426
3427 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3428 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3429 if (device->use_global_bo_list) {
3430 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3431 }
3432 }
3433
3434 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3435 domain, flags, priority);
3436
3437 if (!mem->bo) {
3438 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3439 goto fail;
3440 }
3441 mem->type_index = mem_type_index;
3442 }
3443
3444 result = radv_bo_list_add(device, mem->bo);
3445 if (result != VK_SUCCESS)
3446 goto fail_bo;
3447
3448 *pMem = radv_device_memory_to_handle(mem);
3449
3450 return VK_SUCCESS;
3451
3452 fail_bo:
3453 device->ws->buffer_destroy(mem->bo);
3454 fail:
3455 vk_free2(&device->alloc, pAllocator, mem);
3456
3457 return result;
3458 }
3459
3460 VkResult radv_AllocateMemory(
3461 VkDevice _device,
3462 const VkMemoryAllocateInfo* pAllocateInfo,
3463 const VkAllocationCallbacks* pAllocator,
3464 VkDeviceMemory* pMem)
3465 {
3466 RADV_FROM_HANDLE(radv_device, device, _device);
3467 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3468 }
3469
3470 void radv_FreeMemory(
3471 VkDevice _device,
3472 VkDeviceMemory _mem,
3473 const VkAllocationCallbacks* pAllocator)
3474 {
3475 RADV_FROM_HANDLE(radv_device, device, _device);
3476 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3477
3478 if (mem == NULL)
3479 return;
3480
3481 radv_bo_list_remove(device, mem->bo);
3482 device->ws->buffer_destroy(mem->bo);
3483 mem->bo = NULL;
3484
3485 vk_free2(&device->alloc, pAllocator, mem);
3486 }
3487
3488 VkResult radv_MapMemory(
3489 VkDevice _device,
3490 VkDeviceMemory _memory,
3491 VkDeviceSize offset,
3492 VkDeviceSize size,
3493 VkMemoryMapFlags flags,
3494 void** ppData)
3495 {
3496 RADV_FROM_HANDLE(radv_device, device, _device);
3497 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3498
3499 if (mem == NULL) {
3500 *ppData = NULL;
3501 return VK_SUCCESS;
3502 }
3503
3504 if (mem->user_ptr)
3505 *ppData = mem->user_ptr;
3506 else
3507 *ppData = device->ws->buffer_map(mem->bo);
3508
3509 if (*ppData) {
3510 *ppData += offset;
3511 return VK_SUCCESS;
3512 }
3513
3514 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3515 }
3516
3517 void radv_UnmapMemory(
3518 VkDevice _device,
3519 VkDeviceMemory _memory)
3520 {
3521 RADV_FROM_HANDLE(radv_device, device, _device);
3522 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3523
3524 if (mem == NULL)
3525 return;
3526
3527 if (mem->user_ptr == NULL)
3528 device->ws->buffer_unmap(mem->bo);
3529 }
3530
3531 VkResult radv_FlushMappedMemoryRanges(
3532 VkDevice _device,
3533 uint32_t memoryRangeCount,
3534 const VkMappedMemoryRange* pMemoryRanges)
3535 {
3536 return VK_SUCCESS;
3537 }
3538
3539 VkResult radv_InvalidateMappedMemoryRanges(
3540 VkDevice _device,
3541 uint32_t memoryRangeCount,
3542 const VkMappedMemoryRange* pMemoryRanges)
3543 {
3544 return VK_SUCCESS;
3545 }
3546
3547 void radv_GetBufferMemoryRequirements(
3548 VkDevice _device,
3549 VkBuffer _buffer,
3550 VkMemoryRequirements* pMemoryRequirements)
3551 {
3552 RADV_FROM_HANDLE(radv_device, device, _device);
3553 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3554
3555 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3556
3557 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3558 pMemoryRequirements->alignment = 4096;
3559 else
3560 pMemoryRequirements->alignment = 16;
3561
3562 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3563 }
3564
3565 void radv_GetBufferMemoryRequirements2(
3566 VkDevice device,
3567 const VkBufferMemoryRequirementsInfo2 *pInfo,
3568 VkMemoryRequirements2 *pMemoryRequirements)
3569 {
3570 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3571 &pMemoryRequirements->memoryRequirements);
3572 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3573 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3574 switch (ext->sType) {
3575 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3576 VkMemoryDedicatedRequirements *req =
3577 (VkMemoryDedicatedRequirements *) ext;
3578 req->requiresDedicatedAllocation = buffer->shareable;
3579 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3580 break;
3581 }
3582 default:
3583 break;
3584 }
3585 }
3586 }
3587
3588 void radv_GetImageMemoryRequirements(
3589 VkDevice _device,
3590 VkImage _image,
3591 VkMemoryRequirements* pMemoryRequirements)
3592 {
3593 RADV_FROM_HANDLE(radv_device, device, _device);
3594 RADV_FROM_HANDLE(radv_image, image, _image);
3595
3596 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3597
3598 pMemoryRequirements->size = image->size;
3599 pMemoryRequirements->alignment = image->alignment;
3600 }
3601
3602 void radv_GetImageMemoryRequirements2(
3603 VkDevice device,
3604 const VkImageMemoryRequirementsInfo2 *pInfo,
3605 VkMemoryRequirements2 *pMemoryRequirements)
3606 {
3607 radv_GetImageMemoryRequirements(device, pInfo->image,
3608 &pMemoryRequirements->memoryRequirements);
3609
3610 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3611
3612 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3613 switch (ext->sType) {
3614 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3615 VkMemoryDedicatedRequirements *req =
3616 (VkMemoryDedicatedRequirements *) ext;
3617 req->requiresDedicatedAllocation = image->shareable;
3618 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3619 break;
3620 }
3621 default:
3622 break;
3623 }
3624 }
3625 }
3626
3627 void radv_GetImageSparseMemoryRequirements(
3628 VkDevice device,
3629 VkImage image,
3630 uint32_t* pSparseMemoryRequirementCount,
3631 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3632 {
3633 stub();
3634 }
3635
3636 void radv_GetImageSparseMemoryRequirements2(
3637 VkDevice device,
3638 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3639 uint32_t* pSparseMemoryRequirementCount,
3640 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3641 {
3642 stub();
3643 }
3644
3645 void radv_GetDeviceMemoryCommitment(
3646 VkDevice device,
3647 VkDeviceMemory memory,
3648 VkDeviceSize* pCommittedMemoryInBytes)
3649 {
3650 *pCommittedMemoryInBytes = 0;
3651 }
3652
3653 VkResult radv_BindBufferMemory2(VkDevice device,
3654 uint32_t bindInfoCount,
3655 const VkBindBufferMemoryInfo *pBindInfos)
3656 {
3657 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3658 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3659 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3660
3661 if (mem) {
3662 buffer->bo = mem->bo;
3663 buffer->offset = pBindInfos[i].memoryOffset;
3664 } else {
3665 buffer->bo = NULL;
3666 }
3667 }
3668 return VK_SUCCESS;
3669 }
3670
3671 VkResult radv_BindBufferMemory(
3672 VkDevice device,
3673 VkBuffer buffer,
3674 VkDeviceMemory memory,
3675 VkDeviceSize memoryOffset)
3676 {
3677 const VkBindBufferMemoryInfo info = {
3678 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3679 .buffer = buffer,
3680 .memory = memory,
3681 .memoryOffset = memoryOffset
3682 };
3683
3684 return radv_BindBufferMemory2(device, 1, &info);
3685 }
3686
3687 VkResult radv_BindImageMemory2(VkDevice device,
3688 uint32_t bindInfoCount,
3689 const VkBindImageMemoryInfo *pBindInfos)
3690 {
3691 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3692 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3693 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3694
3695 if (mem) {
3696 image->bo = mem->bo;
3697 image->offset = pBindInfos[i].memoryOffset;
3698 } else {
3699 image->bo = NULL;
3700 image->offset = 0;
3701 }
3702 }
3703 return VK_SUCCESS;
3704 }
3705
3706
3707 VkResult radv_BindImageMemory(
3708 VkDevice device,
3709 VkImage image,
3710 VkDeviceMemory memory,
3711 VkDeviceSize memoryOffset)
3712 {
3713 const VkBindImageMemoryInfo info = {
3714 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3715 .image = image,
3716 .memory = memory,
3717 .memoryOffset = memoryOffset
3718 };
3719
3720 return radv_BindImageMemory2(device, 1, &info);
3721 }
3722
3723
3724 static void
3725 radv_sparse_buffer_bind_memory(struct radv_device *device,
3726 const VkSparseBufferMemoryBindInfo *bind)
3727 {
3728 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3729
3730 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3731 struct radv_device_memory *mem = NULL;
3732
3733 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3734 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3735
3736 device->ws->buffer_virtual_bind(buffer->bo,
3737 bind->pBinds[i].resourceOffset,
3738 bind->pBinds[i].size,
3739 mem ? mem->bo : NULL,
3740 bind->pBinds[i].memoryOffset);
3741 }
3742 }
3743
3744 static void
3745 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3746 const VkSparseImageOpaqueMemoryBindInfo *bind)
3747 {
3748 RADV_FROM_HANDLE(radv_image, image, bind->image);
3749
3750 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3751 struct radv_device_memory *mem = NULL;
3752
3753 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3754 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3755
3756 device->ws->buffer_virtual_bind(image->bo,
3757 bind->pBinds[i].resourceOffset,
3758 bind->pBinds[i].size,
3759 mem ? mem->bo : NULL,
3760 bind->pBinds[i].memoryOffset);
3761 }
3762 }
3763
3764 VkResult radv_QueueBindSparse(
3765 VkQueue _queue,
3766 uint32_t bindInfoCount,
3767 const VkBindSparseInfo* pBindInfo,
3768 VkFence _fence)
3769 {
3770 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3771 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3772 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3773 bool fence_emitted = false;
3774 VkResult result;
3775 int ret;
3776
3777 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3778 struct radv_winsys_sem_info sem_info;
3779 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3780 radv_sparse_buffer_bind_memory(queue->device,
3781 pBindInfo[i].pBufferBinds + j);
3782 }
3783
3784 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3785 radv_sparse_image_opaque_bind_memory(queue->device,
3786 pBindInfo[i].pImageOpaqueBinds + j);
3787 }
3788
3789 VkResult result;
3790 result = radv_alloc_sem_info(queue->device->instance,
3791 &sem_info,
3792 pBindInfo[i].waitSemaphoreCount,
3793 pBindInfo[i].pWaitSemaphores,
3794 pBindInfo[i].signalSemaphoreCount,
3795 pBindInfo[i].pSignalSemaphores,
3796 _fence);
3797 if (result != VK_SUCCESS)
3798 return result;
3799
3800 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3801 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3802 &queue->device->empty_cs[queue->queue_family_index],
3803 1, NULL, NULL,
3804 &sem_info, NULL,
3805 false, base_fence);
3806 if (ret) {
3807 radv_loge("failed to submit CS %d\n", i);
3808 abort();
3809 }
3810
3811 fence_emitted = true;
3812 }
3813
3814 radv_free_sem_info(&sem_info);
3815
3816 }
3817
3818 if (fence) {
3819 if (!fence_emitted) {
3820 result = radv_signal_fence(queue, fence);
3821 if (result != VK_SUCCESS)
3822 return result;
3823 }
3824 }
3825
3826 return VK_SUCCESS;
3827 }
3828
3829 VkResult radv_CreateFence(
3830 VkDevice _device,
3831 const VkFenceCreateInfo* pCreateInfo,
3832 const VkAllocationCallbacks* pAllocator,
3833 VkFence* pFence)
3834 {
3835 RADV_FROM_HANDLE(radv_device, device, _device);
3836 const VkExportFenceCreateInfo *export =
3837 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3838 VkExternalFenceHandleTypeFlags handleTypes =
3839 export ? export->handleTypes : 0;
3840
3841 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3842 sizeof(*fence), 8,
3843 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3844
3845 if (!fence)
3846 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3847
3848 fence->fence_wsi = NULL;
3849 fence->temp_syncobj = 0;
3850 if (device->always_use_syncobj || handleTypes) {
3851 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3852 if (ret) {
3853 vk_free2(&device->alloc, pAllocator, fence);
3854 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3855 }
3856 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3857 device->ws->signal_syncobj(device->ws, fence->syncobj);
3858 }
3859 fence->fence = NULL;
3860 } else {
3861 fence->fence = device->ws->create_fence();
3862 if (!fence->fence) {
3863 vk_free2(&device->alloc, pAllocator, fence);
3864 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3865 }
3866 fence->syncobj = 0;
3867 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3868 device->ws->signal_fence(fence->fence);
3869 }
3870
3871 *pFence = radv_fence_to_handle(fence);
3872
3873 return VK_SUCCESS;
3874 }
3875
3876 void radv_DestroyFence(
3877 VkDevice _device,
3878 VkFence _fence,
3879 const VkAllocationCallbacks* pAllocator)
3880 {
3881 RADV_FROM_HANDLE(radv_device, device, _device);
3882 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3883
3884 if (!fence)
3885 return;
3886
3887 if (fence->temp_syncobj)
3888 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3889 if (fence->syncobj)
3890 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3891 if (fence->fence)
3892 device->ws->destroy_fence(fence->fence);
3893 if (fence->fence_wsi)
3894 fence->fence_wsi->destroy(fence->fence_wsi);
3895 vk_free2(&device->alloc, pAllocator, fence);
3896 }
3897
3898
3899 uint64_t radv_get_current_time(void)
3900 {
3901 struct timespec tv;
3902 clock_gettime(CLOCK_MONOTONIC, &tv);
3903 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3904 }
3905
3906 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3907 {
3908 uint64_t current_time = radv_get_current_time();
3909
3910 timeout = MIN2(UINT64_MAX - current_time, timeout);
3911
3912 return current_time + timeout;
3913 }
3914
3915
3916 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3917 uint32_t fenceCount, const VkFence *pFences)
3918 {
3919 for (uint32_t i = 0; i < fenceCount; ++i) {
3920 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3921 if (fence->fence == NULL || fence->syncobj ||
3922 fence->temp_syncobj || fence->fence_wsi ||
3923 (!device->ws->is_fence_waitable(fence->fence)))
3924 return false;
3925 }
3926 return true;
3927 }
3928
3929 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3930 {
3931 for (uint32_t i = 0; i < fenceCount; ++i) {
3932 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3933 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3934 return false;
3935 }
3936 return true;
3937 }
3938
3939 VkResult radv_WaitForFences(
3940 VkDevice _device,
3941 uint32_t fenceCount,
3942 const VkFence* pFences,
3943 VkBool32 waitAll,
3944 uint64_t timeout)
3945 {
3946 RADV_FROM_HANDLE(radv_device, device, _device);
3947 timeout = radv_get_absolute_timeout(timeout);
3948
3949 if (device->always_use_syncobj &&
3950 radv_all_fences_syncobj(fenceCount, pFences))
3951 {
3952 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3953 if (!handles)
3954 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3955
3956 for (uint32_t i = 0; i < fenceCount; ++i) {
3957 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3958 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3959 }
3960
3961 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3962
3963 free(handles);
3964 return success ? VK_SUCCESS : VK_TIMEOUT;
3965 }
3966
3967 if (!waitAll && fenceCount > 1) {
3968 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3969 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3970 uint32_t wait_count = 0;
3971 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3972 if (!fences)
3973 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3974
3975 for (uint32_t i = 0; i < fenceCount; ++i) {
3976 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3977
3978 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3979 free(fences);
3980 return VK_SUCCESS;
3981 }
3982
3983 fences[wait_count++] = fence->fence;
3984 }
3985
3986 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3987 waitAll, timeout - radv_get_current_time());
3988
3989 free(fences);
3990 return success ? VK_SUCCESS : VK_TIMEOUT;
3991 }
3992
3993 while(radv_get_current_time() <= timeout) {
3994 for (uint32_t i = 0; i < fenceCount; ++i) {
3995 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3996 return VK_SUCCESS;
3997 }
3998 }
3999 return VK_TIMEOUT;
4000 }
4001
4002 for (uint32_t i = 0; i < fenceCount; ++i) {
4003 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4004 bool expired = false;
4005
4006 if (fence->temp_syncobj) {
4007 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
4008 return VK_TIMEOUT;
4009 continue;
4010 }
4011
4012 if (fence->syncobj) {
4013 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
4014 return VK_TIMEOUT;
4015 continue;
4016 }
4017
4018 if (fence->fence) {
4019 if (!device->ws->is_fence_waitable(fence->fence)) {
4020 while(!device->ws->is_fence_waitable(fence->fence) &&
4021 radv_get_current_time() <= timeout)
4022 /* Do nothing */;
4023 }
4024
4025 expired = device->ws->fence_wait(device->ws,
4026 fence->fence,
4027 true, timeout);
4028 if (!expired)
4029 return VK_TIMEOUT;
4030 }
4031
4032 if (fence->fence_wsi) {
4033 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4034 if (result != VK_SUCCESS)
4035 return result;
4036 }
4037 }
4038
4039 return VK_SUCCESS;
4040 }
4041
4042 VkResult radv_ResetFences(VkDevice _device,
4043 uint32_t fenceCount,
4044 const VkFence *pFences)
4045 {
4046 RADV_FROM_HANDLE(radv_device, device, _device);
4047
4048 for (unsigned i = 0; i < fenceCount; ++i) {
4049 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4050 if (fence->fence)
4051 device->ws->reset_fence(fence->fence);
4052
4053 /* Per spec, we first restore the permanent payload, and then reset, so
4054 * having a temp syncobj should not skip resetting the permanent syncobj. */
4055 if (fence->temp_syncobj) {
4056 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4057 fence->temp_syncobj = 0;
4058 }
4059
4060 if (fence->syncobj) {
4061 device->ws->reset_syncobj(device->ws, fence->syncobj);
4062 }
4063 }
4064
4065 return VK_SUCCESS;
4066 }
4067
4068 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4069 {
4070 RADV_FROM_HANDLE(radv_device, device, _device);
4071 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4072
4073 if (fence->temp_syncobj) {
4074 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4075 return success ? VK_SUCCESS : VK_NOT_READY;
4076 }
4077
4078 if (fence->syncobj) {
4079 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4080 return success ? VK_SUCCESS : VK_NOT_READY;
4081 }
4082
4083 if (fence->fence) {
4084 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4085 return VK_NOT_READY;
4086 }
4087 if (fence->fence_wsi) {
4088 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4089
4090 if (result != VK_SUCCESS) {
4091 if (result == VK_TIMEOUT)
4092 return VK_NOT_READY;
4093 return result;
4094 }
4095 }
4096 return VK_SUCCESS;
4097 }
4098
4099
4100 // Queue semaphore functions
4101
4102 VkResult radv_CreateSemaphore(
4103 VkDevice _device,
4104 const VkSemaphoreCreateInfo* pCreateInfo,
4105 const VkAllocationCallbacks* pAllocator,
4106 VkSemaphore* pSemaphore)
4107 {
4108 RADV_FROM_HANDLE(radv_device, device, _device);
4109 const VkExportSemaphoreCreateInfo *export =
4110 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4111 VkExternalSemaphoreHandleTypeFlags handleTypes =
4112 export ? export->handleTypes : 0;
4113
4114 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4115 sizeof(*sem), 8,
4116 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4117 if (!sem)
4118 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4119
4120 sem->temp_syncobj = 0;
4121 /* create a syncobject if we are going to export this semaphore */
4122 if (device->always_use_syncobj || handleTypes) {
4123 assert (device->physical_device->rad_info.has_syncobj);
4124 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4125 if (ret) {
4126 vk_free2(&device->alloc, pAllocator, sem);
4127 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4128 }
4129 sem->sem = NULL;
4130 } else {
4131 sem->sem = device->ws->create_sem(device->ws);
4132 if (!sem->sem) {
4133 vk_free2(&device->alloc, pAllocator, sem);
4134 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4135 }
4136 sem->syncobj = 0;
4137 }
4138
4139 *pSemaphore = radv_semaphore_to_handle(sem);
4140 return VK_SUCCESS;
4141 }
4142
4143 void radv_DestroySemaphore(
4144 VkDevice _device,
4145 VkSemaphore _semaphore,
4146 const VkAllocationCallbacks* pAllocator)
4147 {
4148 RADV_FROM_HANDLE(radv_device, device, _device);
4149 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4150 if (!_semaphore)
4151 return;
4152
4153 if (sem->syncobj)
4154 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4155 else
4156 device->ws->destroy_sem(sem->sem);
4157 vk_free2(&device->alloc, pAllocator, sem);
4158 }
4159
4160 VkResult radv_CreateEvent(
4161 VkDevice _device,
4162 const VkEventCreateInfo* pCreateInfo,
4163 const VkAllocationCallbacks* pAllocator,
4164 VkEvent* pEvent)
4165 {
4166 RADV_FROM_HANDLE(radv_device, device, _device);
4167 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4168 sizeof(*event), 8,
4169 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4170
4171 if (!event)
4172 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4173
4174 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4175 RADEON_DOMAIN_GTT,
4176 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4177 RADV_BO_PRIORITY_FENCE);
4178 if (!event->bo) {
4179 vk_free2(&device->alloc, pAllocator, event);
4180 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4181 }
4182
4183 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4184
4185 *pEvent = radv_event_to_handle(event);
4186
4187 return VK_SUCCESS;
4188 }
4189
4190 void radv_DestroyEvent(
4191 VkDevice _device,
4192 VkEvent _event,
4193 const VkAllocationCallbacks* pAllocator)
4194 {
4195 RADV_FROM_HANDLE(radv_device, device, _device);
4196 RADV_FROM_HANDLE(radv_event, event, _event);
4197
4198 if (!event)
4199 return;
4200 device->ws->buffer_destroy(event->bo);
4201 vk_free2(&device->alloc, pAllocator, event);
4202 }
4203
4204 VkResult radv_GetEventStatus(
4205 VkDevice _device,
4206 VkEvent _event)
4207 {
4208 RADV_FROM_HANDLE(radv_event, event, _event);
4209
4210 if (*event->map == 1)
4211 return VK_EVENT_SET;
4212 return VK_EVENT_RESET;
4213 }
4214
4215 VkResult radv_SetEvent(
4216 VkDevice _device,
4217 VkEvent _event)
4218 {
4219 RADV_FROM_HANDLE(radv_event, event, _event);
4220 *event->map = 1;
4221
4222 return VK_SUCCESS;
4223 }
4224
4225 VkResult radv_ResetEvent(
4226 VkDevice _device,
4227 VkEvent _event)
4228 {
4229 RADV_FROM_HANDLE(radv_event, event, _event);
4230 *event->map = 0;
4231
4232 return VK_SUCCESS;
4233 }
4234
4235 VkResult radv_CreateBuffer(
4236 VkDevice _device,
4237 const VkBufferCreateInfo* pCreateInfo,
4238 const VkAllocationCallbacks* pAllocator,
4239 VkBuffer* pBuffer)
4240 {
4241 RADV_FROM_HANDLE(radv_device, device, _device);
4242 struct radv_buffer *buffer;
4243
4244 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4245
4246 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4247 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4248 if (buffer == NULL)
4249 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4250
4251 buffer->size = pCreateInfo->size;
4252 buffer->usage = pCreateInfo->usage;
4253 buffer->bo = NULL;
4254 buffer->offset = 0;
4255 buffer->flags = pCreateInfo->flags;
4256
4257 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4258 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4259
4260 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4261 buffer->bo = device->ws->buffer_create(device->ws,
4262 align64(buffer->size, 4096),
4263 4096, 0, RADEON_FLAG_VIRTUAL,
4264 RADV_BO_PRIORITY_VIRTUAL);
4265 if (!buffer->bo) {
4266 vk_free2(&device->alloc, pAllocator, buffer);
4267 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4268 }
4269 }
4270
4271 *pBuffer = radv_buffer_to_handle(buffer);
4272
4273 return VK_SUCCESS;
4274 }
4275
4276 void radv_DestroyBuffer(
4277 VkDevice _device,
4278 VkBuffer _buffer,
4279 const VkAllocationCallbacks* pAllocator)
4280 {
4281 RADV_FROM_HANDLE(radv_device, device, _device);
4282 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4283
4284 if (!buffer)
4285 return;
4286
4287 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4288 device->ws->buffer_destroy(buffer->bo);
4289
4290 vk_free2(&device->alloc, pAllocator, buffer);
4291 }
4292
4293 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4294 VkDevice device,
4295 const VkBufferDeviceAddressInfoEXT* pInfo)
4296 {
4297 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4298 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4299 }
4300
4301
4302 static inline unsigned
4303 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4304 {
4305 if (stencil)
4306 return plane->surface.u.legacy.stencil_tiling_index[level];
4307 else
4308 return plane->surface.u.legacy.tiling_index[level];
4309 }
4310
4311 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4312 {
4313 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4314 }
4315
4316 static uint32_t
4317 radv_init_dcc_control_reg(struct radv_device *device,
4318 struct radv_image_view *iview)
4319 {
4320 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4321 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4322 unsigned max_compressed_block_size;
4323 unsigned independent_128b_blocks;
4324 unsigned independent_64b_blocks;
4325
4326 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4327 return 0;
4328
4329 if (!device->physical_device->rad_info.has_dedicated_vram) {
4330 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4331 * dGPU and 64 for APU because all of our APUs to date use
4332 * DIMMs which have a request granularity size of 64B while all
4333 * other chips have a 32B request size.
4334 */
4335 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4336 }
4337
4338 if (device->physical_device->rad_info.chip_class >= GFX10) {
4339 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4340 independent_64b_blocks = 0;
4341 independent_128b_blocks = 1;
4342 } else {
4343 independent_128b_blocks = 0;
4344
4345 if (iview->image->info.samples > 1) {
4346 if (iview->image->planes[0].surface.bpe == 1)
4347 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4348 else if (iview->image->planes[0].surface.bpe == 2)
4349 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4350 }
4351
4352 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4353 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4354 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4355 /* If this DCC image is potentially going to be used in texture
4356 * fetches, we need some special settings.
4357 */
4358 independent_64b_blocks = 1;
4359 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4360 } else {
4361 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4362 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4363 * big as possible for better compression state.
4364 */
4365 independent_64b_blocks = 0;
4366 max_compressed_block_size = max_uncompressed_block_size;
4367 }
4368 }
4369
4370 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4371 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4372 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4373 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4374 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4375 }
4376
4377 void
4378 radv_initialise_color_surface(struct radv_device *device,
4379 struct radv_color_buffer_info *cb,
4380 struct radv_image_view *iview)
4381 {
4382 const struct vk_format_description *desc;
4383 unsigned ntype, format, swap, endian;
4384 unsigned blend_clamp = 0, blend_bypass = 0;
4385 uint64_t va;
4386 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4387 const struct radeon_surf *surf = &plane->surface;
4388
4389 desc = vk_format_description(iview->vk_format);
4390
4391 memset(cb, 0, sizeof(*cb));
4392
4393 /* Intensity is implemented as Red, so treat it that way. */
4394 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4395
4396 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4397
4398 cb->cb_color_base = va >> 8;
4399
4400 if (device->physical_device->rad_info.chip_class >= GFX9) {
4401 struct gfx9_surf_meta_flags meta;
4402 if (iview->image->dcc_offset)
4403 meta = surf->u.gfx9.dcc;
4404 else
4405 meta = surf->u.gfx9.cmask;
4406
4407 if (device->physical_device->rad_info.chip_class >= GFX10) {
4408 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4409 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4410 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4411 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4412 } else {
4413 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4414 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4415 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4416 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4417 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4418 }
4419
4420 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4421 cb->cb_color_base |= surf->tile_swizzle;
4422 } else {
4423 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4424 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4425
4426 cb->cb_color_base += level_info->offset >> 8;
4427 if (level_info->mode == RADEON_SURF_MODE_2D)
4428 cb->cb_color_base |= surf->tile_swizzle;
4429
4430 pitch_tile_max = level_info->nblk_x / 8 - 1;
4431 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4432 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4433
4434 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4435 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4436 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
4437
4438 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4439
4440 if (radv_image_has_fmask(iview->image)) {
4441 if (device->physical_device->rad_info.chip_class >= GFX7)
4442 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
4443 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
4444 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
4445 } else {
4446 /* This must be set for fast clear to work without FMASK. */
4447 if (device->physical_device->rad_info.chip_class >= GFX7)
4448 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4449 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4450 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4451 }
4452 }
4453
4454 /* CMASK variables */
4455 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4456 va += iview->image->cmask_offset;
4457 cb->cb_color_cmask = va >> 8;
4458
4459 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4460 va += iview->image->dcc_offset;
4461
4462 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4463 device->physical_device->rad_info.chip_class <= GFX8)
4464 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4465
4466 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4467 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4468
4469 cb->cb_dcc_base = va >> 8;
4470 cb->cb_dcc_base |= dcc_tile_swizzle;
4471
4472 /* GFX10 field has the same base shift as the GFX6 field. */
4473 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4474 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4475 S_028C6C_SLICE_MAX_GFX10(max_slice);
4476
4477 if (iview->image->info.samples > 1) {
4478 unsigned log_samples = util_logbase2(iview->image->info.samples);
4479
4480 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4481 S_028C74_NUM_FRAGMENTS(log_samples);
4482 }
4483
4484 if (radv_image_has_fmask(iview->image)) {
4485 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
4486 cb->cb_color_fmask = va >> 8;
4487 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
4488 } else {
4489 cb->cb_color_fmask = cb->cb_color_base;
4490 }
4491
4492 ntype = radv_translate_color_numformat(iview->vk_format,
4493 desc,
4494 vk_format_get_first_non_void_channel(iview->vk_format));
4495 format = radv_translate_colorformat(iview->vk_format);
4496 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4497 radv_finishme("Illegal color\n");
4498 swap = radv_translate_colorswap(iview->vk_format, false);
4499 endian = radv_colorformat_endian_swap(format);
4500
4501 /* blend clamp should be set for all NORM/SRGB types */
4502 if (ntype == V_028C70_NUMBER_UNORM ||
4503 ntype == V_028C70_NUMBER_SNORM ||
4504 ntype == V_028C70_NUMBER_SRGB)
4505 blend_clamp = 1;
4506
4507 /* set blend bypass according to docs if SINT/UINT or
4508 8/24 COLOR variants */
4509 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4510 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4511 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4512 blend_clamp = 0;
4513 blend_bypass = 1;
4514 }
4515 #if 0
4516 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4517 (format == V_028C70_COLOR_8 ||
4518 format == V_028C70_COLOR_8_8 ||
4519 format == V_028C70_COLOR_8_8_8_8))
4520 ->color_is_int8 = true;
4521 #endif
4522 cb->cb_color_info = S_028C70_FORMAT(format) |
4523 S_028C70_COMP_SWAP(swap) |
4524 S_028C70_BLEND_CLAMP(blend_clamp) |
4525 S_028C70_BLEND_BYPASS(blend_bypass) |
4526 S_028C70_SIMPLE_FLOAT(1) |
4527 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4528 ntype != V_028C70_NUMBER_SNORM &&
4529 ntype != V_028C70_NUMBER_SRGB &&
4530 format != V_028C70_COLOR_8_24 &&
4531 format != V_028C70_COLOR_24_8) |
4532 S_028C70_NUMBER_TYPE(ntype) |
4533 S_028C70_ENDIAN(endian);
4534 if (radv_image_has_fmask(iview->image)) {
4535 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4536 if (device->physical_device->rad_info.chip_class == GFX6) {
4537 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
4538 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4539 }
4540
4541 if (radv_image_is_tc_compat_cmask(iview->image)) {
4542 /* Allow the texture block to read FMASK directly
4543 * without decompressing it. This bit must be cleared
4544 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4545 * otherwise the operation doesn't happen.
4546 */
4547 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4548
4549 /* Set CMASK into a tiling format that allows the
4550 * texture block to read it.
4551 */
4552 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4553 }
4554 }
4555
4556 if (radv_image_has_cmask(iview->image) &&
4557 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4558 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4559
4560 if (radv_dcc_enabled(iview->image, iview->base_mip))
4561 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4562
4563 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4564
4565 /* This must be set for fast clear to work without FMASK. */
4566 if (!radv_image_has_fmask(iview->image) &&
4567 device->physical_device->rad_info.chip_class == GFX6) {
4568 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4569 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4570 }
4571
4572 if (device->physical_device->rad_info.chip_class >= GFX9) {
4573 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4574
4575 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4576 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4577 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4578 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4579
4580 if (device->physical_device->rad_info.chip_class >= GFX10) {
4581 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4582
4583 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4584 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4585 S_028EE0_RESOURCE_LEVEL(1);
4586 } else {
4587 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4588 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4589 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4590 }
4591
4592 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4593 S_028C68_MIP0_HEIGHT(height - 1) |
4594 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4595 }
4596 }
4597
4598 static unsigned
4599 radv_calc_decompress_on_z_planes(struct radv_device *device,
4600 struct radv_image_view *iview)
4601 {
4602 unsigned max_zplanes = 0;
4603
4604 assert(radv_image_is_tc_compat_htile(iview->image));
4605
4606 if (device->physical_device->rad_info.chip_class >= GFX9) {
4607 /* Default value for 32-bit depth surfaces. */
4608 max_zplanes = 4;
4609
4610 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4611 iview->image->info.samples > 1)
4612 max_zplanes = 2;
4613
4614 max_zplanes = max_zplanes + 1;
4615 } else {
4616 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4617 /* Do not enable Z plane compression for 16-bit depth
4618 * surfaces because isn't supported on GFX8. Only
4619 * 32-bit depth surfaces are supported by the hardware.
4620 * This allows to maintain shader compatibility and to
4621 * reduce the number of depth decompressions.
4622 */
4623 max_zplanes = 1;
4624 } else {
4625 if (iview->image->info.samples <= 1)
4626 max_zplanes = 5;
4627 else if (iview->image->info.samples <= 4)
4628 max_zplanes = 3;
4629 else
4630 max_zplanes = 2;
4631 }
4632 }
4633
4634 return max_zplanes;
4635 }
4636
4637 void
4638 radv_initialise_ds_surface(struct radv_device *device,
4639 struct radv_ds_buffer_info *ds,
4640 struct radv_image_view *iview)
4641 {
4642 unsigned level = iview->base_mip;
4643 unsigned format, stencil_format;
4644 uint64_t va, s_offs, z_offs;
4645 bool stencil_only = false;
4646 const struct radv_image_plane *plane = &iview->image->planes[0];
4647 const struct radeon_surf *surf = &plane->surface;
4648
4649 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4650
4651 memset(ds, 0, sizeof(*ds));
4652 switch (iview->image->vk_format) {
4653 case VK_FORMAT_D24_UNORM_S8_UINT:
4654 case VK_FORMAT_X8_D24_UNORM_PACK32:
4655 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4656 ds->offset_scale = 2.0f;
4657 break;
4658 case VK_FORMAT_D16_UNORM:
4659 case VK_FORMAT_D16_UNORM_S8_UINT:
4660 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4661 ds->offset_scale = 4.0f;
4662 break;
4663 case VK_FORMAT_D32_SFLOAT:
4664 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4665 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4666 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4667 ds->offset_scale = 1.0f;
4668 break;
4669 case VK_FORMAT_S8_UINT:
4670 stencil_only = true;
4671 break;
4672 default:
4673 break;
4674 }
4675
4676 format = radv_translate_dbformat(iview->image->vk_format);
4677 stencil_format = surf->has_stencil ?
4678 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4679
4680 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4681 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4682 S_028008_SLICE_MAX(max_slice);
4683 if (device->physical_device->rad_info.chip_class >= GFX10) {
4684 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4685 S_028008_SLICE_MAX_HI(max_slice >> 11);
4686 }
4687
4688 ds->db_htile_data_base = 0;
4689 ds->db_htile_surface = 0;
4690
4691 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4692 s_offs = z_offs = va;
4693
4694 if (device->physical_device->rad_info.chip_class >= GFX9) {
4695 assert(surf->u.gfx9.surf_offset == 0);
4696 s_offs += surf->u.gfx9.stencil_offset;
4697
4698 ds->db_z_info = S_028038_FORMAT(format) |
4699 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4700 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4701 S_028038_MAXMIP(iview->image->info.levels - 1) |
4702 S_028038_ZRANGE_PRECISION(1);
4703 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4704 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4705
4706 if (device->physical_device->rad_info.chip_class == GFX9) {
4707 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4708 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4709 }
4710
4711 ds->db_depth_view |= S_028008_MIPID(level);
4712 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4713 S_02801C_Y_MAX(iview->image->info.height - 1);
4714
4715 if (radv_htile_enabled(iview->image, level)) {
4716 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4717
4718 if (radv_image_is_tc_compat_htile(iview->image)) {
4719 unsigned max_zplanes =
4720 radv_calc_decompress_on_z_planes(device, iview);
4721
4722 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4723
4724 if (device->physical_device->rad_info.chip_class >= GFX10) {
4725 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4726 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4727 } else {
4728 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4729 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4730 }
4731 }
4732
4733 if (!surf->has_stencil)
4734 /* Use all of the htile_buffer for depth if there's no stencil. */
4735 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4736 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4737 iview->image->htile_offset;
4738 ds->db_htile_data_base = va >> 8;
4739 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4740 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4741
4742 if (device->physical_device->rad_info.chip_class == GFX9) {
4743 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4744 }
4745 }
4746 } else {
4747 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4748
4749 if (stencil_only)
4750 level_info = &surf->u.legacy.stencil_level[level];
4751
4752 z_offs += surf->u.legacy.level[level].offset;
4753 s_offs += surf->u.legacy.stencil_level[level].offset;
4754
4755 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4756 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4757 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4758
4759 if (iview->image->info.samples > 1)
4760 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4761
4762 if (device->physical_device->rad_info.chip_class >= GFX7) {
4763 struct radeon_info *info = &device->physical_device->rad_info;
4764 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4765 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4766 unsigned macro_index = surf->u.legacy.macro_tile_index;
4767 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4768 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4769 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4770
4771 if (stencil_only)
4772 tile_mode = stencil_tile_mode;
4773
4774 ds->db_depth_info |=
4775 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4776 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4777 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4778 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4779 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4780 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4781 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4782 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4783 } else {
4784 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4785 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4786 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4787 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4788 if (stencil_only)
4789 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4790 }
4791
4792 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4793 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4794 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4795
4796 if (radv_htile_enabled(iview->image, level)) {
4797 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4798
4799 if (!surf->has_stencil &&
4800 !radv_image_is_tc_compat_htile(iview->image))
4801 /* Use all of the htile_buffer for depth if there's no stencil. */
4802 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4803
4804 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4805 iview->image->htile_offset;
4806 ds->db_htile_data_base = va >> 8;
4807 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4808
4809 if (radv_image_is_tc_compat_htile(iview->image)) {
4810 unsigned max_zplanes =
4811 radv_calc_decompress_on_z_planes(device, iview);
4812
4813 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4814 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4815 }
4816 }
4817 }
4818
4819 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4820 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4821 }
4822
4823 VkResult radv_CreateFramebuffer(
4824 VkDevice _device,
4825 const VkFramebufferCreateInfo* pCreateInfo,
4826 const VkAllocationCallbacks* pAllocator,
4827 VkFramebuffer* pFramebuffer)
4828 {
4829 RADV_FROM_HANDLE(radv_device, device, _device);
4830 struct radv_framebuffer *framebuffer;
4831 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
4832 vk_find_struct_const(pCreateInfo->pNext,
4833 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
4834
4835 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4836
4837 size_t size = sizeof(*framebuffer);
4838 if (!imageless_create_info)
4839 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
4840 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4841 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4842 if (framebuffer == NULL)
4843 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4844
4845 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4846 framebuffer->width = pCreateInfo->width;
4847 framebuffer->height = pCreateInfo->height;
4848 framebuffer->layers = pCreateInfo->layers;
4849 if (imageless_create_info) {
4850 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
4851 const VkFramebufferAttachmentImageInfoKHR *attachment =
4852 imageless_create_info->pAttachmentImageInfos + i;
4853 framebuffer->width = MIN2(framebuffer->width, attachment->width);
4854 framebuffer->height = MIN2(framebuffer->height, attachment->height);
4855 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
4856 }
4857 } else {
4858 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4859 VkImageView _iview = pCreateInfo->pAttachments[i];
4860 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4861 framebuffer->attachments[i] = iview;
4862 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4863 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4864 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4865 }
4866 }
4867
4868 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4869 return VK_SUCCESS;
4870 }
4871
4872 void radv_DestroyFramebuffer(
4873 VkDevice _device,
4874 VkFramebuffer _fb,
4875 const VkAllocationCallbacks* pAllocator)
4876 {
4877 RADV_FROM_HANDLE(radv_device, device, _device);
4878 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4879
4880 if (!fb)
4881 return;
4882 vk_free2(&device->alloc, pAllocator, fb);
4883 }
4884
4885 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4886 {
4887 switch (address_mode) {
4888 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4889 return V_008F30_SQ_TEX_WRAP;
4890 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4891 return V_008F30_SQ_TEX_MIRROR;
4892 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4893 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4894 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4895 return V_008F30_SQ_TEX_CLAMP_BORDER;
4896 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4897 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4898 default:
4899 unreachable("illegal tex wrap mode");
4900 break;
4901 }
4902 }
4903
4904 static unsigned
4905 radv_tex_compare(VkCompareOp op)
4906 {
4907 switch (op) {
4908 case VK_COMPARE_OP_NEVER:
4909 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4910 case VK_COMPARE_OP_LESS:
4911 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4912 case VK_COMPARE_OP_EQUAL:
4913 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4914 case VK_COMPARE_OP_LESS_OR_EQUAL:
4915 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4916 case VK_COMPARE_OP_GREATER:
4917 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4918 case VK_COMPARE_OP_NOT_EQUAL:
4919 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4920 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4921 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4922 case VK_COMPARE_OP_ALWAYS:
4923 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4924 default:
4925 unreachable("illegal compare mode");
4926 break;
4927 }
4928 }
4929
4930 static unsigned
4931 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4932 {
4933 switch (filter) {
4934 case VK_FILTER_NEAREST:
4935 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4936 V_008F38_SQ_TEX_XY_FILTER_POINT);
4937 case VK_FILTER_LINEAR:
4938 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4939 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4940 case VK_FILTER_CUBIC_IMG:
4941 default:
4942 fprintf(stderr, "illegal texture filter");
4943 return 0;
4944 }
4945 }
4946
4947 static unsigned
4948 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4949 {
4950 switch (mode) {
4951 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4952 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4953 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4954 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4955 default:
4956 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4957 }
4958 }
4959
4960 static unsigned
4961 radv_tex_bordercolor(VkBorderColor bcolor)
4962 {
4963 switch (bcolor) {
4964 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4965 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4966 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4967 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4968 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4969 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4970 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4971 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4972 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4973 default:
4974 break;
4975 }
4976 return 0;
4977 }
4978
4979 static unsigned
4980 radv_tex_aniso_filter(unsigned filter)
4981 {
4982 if (filter < 2)
4983 return 0;
4984 if (filter < 4)
4985 return 1;
4986 if (filter < 8)
4987 return 2;
4988 if (filter < 16)
4989 return 3;
4990 return 4;
4991 }
4992
4993 static unsigned
4994 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4995 {
4996 switch (mode) {
4997 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4998 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4999 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
5000 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
5001 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
5002 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
5003 default:
5004 break;
5005 }
5006 return 0;
5007 }
5008
5009 static uint32_t
5010 radv_get_max_anisotropy(struct radv_device *device,
5011 const VkSamplerCreateInfo *pCreateInfo)
5012 {
5013 if (device->force_aniso >= 0)
5014 return device->force_aniso;
5015
5016 if (pCreateInfo->anisotropyEnable &&
5017 pCreateInfo->maxAnisotropy > 1.0f)
5018 return (uint32_t)pCreateInfo->maxAnisotropy;
5019
5020 return 0;
5021 }
5022
5023 static void
5024 radv_init_sampler(struct radv_device *device,
5025 struct radv_sampler *sampler,
5026 const VkSamplerCreateInfo *pCreateInfo)
5027 {
5028 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
5029 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
5030 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5031 device->physical_device->rad_info.chip_class == GFX9;
5032 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5033
5034 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5035 vk_find_struct_const(pCreateInfo->pNext,
5036 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5037 if (sampler_reduction)
5038 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5039
5040 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5041 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5042 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5043 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5044 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5045 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5046 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5047 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5048 S_008F30_DISABLE_CUBE_WRAP(0) |
5049 S_008F30_COMPAT_MODE(compat_mode) |
5050 S_008F30_FILTER_MODE(filter_mode));
5051 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5052 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5053 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5054 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5055 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5056 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5057 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5058 S_008F38_MIP_POINT_PRECLAMP(0));
5059 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5060 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5061
5062 if (device->physical_device->rad_info.chip_class >= GFX10) {
5063 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5064 } else {
5065 sampler->state[2] |=
5066 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5067 S_008F38_FILTER_PREC_FIX(1) |
5068 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5069 }
5070 }
5071
5072 VkResult radv_CreateSampler(
5073 VkDevice _device,
5074 const VkSamplerCreateInfo* pCreateInfo,
5075 const VkAllocationCallbacks* pAllocator,
5076 VkSampler* pSampler)
5077 {
5078 RADV_FROM_HANDLE(radv_device, device, _device);
5079 struct radv_sampler *sampler;
5080
5081 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5082 vk_find_struct_const(pCreateInfo->pNext,
5083 SAMPLER_YCBCR_CONVERSION_INFO);
5084
5085 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5086
5087 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5089 if (!sampler)
5090 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5091
5092 radv_init_sampler(device, sampler, pCreateInfo);
5093
5094 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5095 *pSampler = radv_sampler_to_handle(sampler);
5096
5097 return VK_SUCCESS;
5098 }
5099
5100 void radv_DestroySampler(
5101 VkDevice _device,
5102 VkSampler _sampler,
5103 const VkAllocationCallbacks* pAllocator)
5104 {
5105 RADV_FROM_HANDLE(radv_device, device, _device);
5106 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5107
5108 if (!sampler)
5109 return;
5110 vk_free2(&device->alloc, pAllocator, sampler);
5111 }
5112
5113 /* vk_icd.h does not declare this function, so we declare it here to
5114 * suppress Wmissing-prototypes.
5115 */
5116 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5117 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5118
5119 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5120 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5121 {
5122 /* For the full details on loader interface versioning, see
5123 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5124 * What follows is a condensed summary, to help you navigate the large and
5125 * confusing official doc.
5126 *
5127 * - Loader interface v0 is incompatible with later versions. We don't
5128 * support it.
5129 *
5130 * - In loader interface v1:
5131 * - The first ICD entrypoint called by the loader is
5132 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5133 * entrypoint.
5134 * - The ICD must statically expose no other Vulkan symbol unless it is
5135 * linked with -Bsymbolic.
5136 * - Each dispatchable Vulkan handle created by the ICD must be
5137 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5138 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5139 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5140 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5141 * such loader-managed surfaces.
5142 *
5143 * - Loader interface v2 differs from v1 in:
5144 * - The first ICD entrypoint called by the loader is
5145 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5146 * statically expose this entrypoint.
5147 *
5148 * - Loader interface v3 differs from v2 in:
5149 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5150 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5151 * because the loader no longer does so.
5152 */
5153 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5154 return VK_SUCCESS;
5155 }
5156
5157 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5158 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5159 int *pFD)
5160 {
5161 RADV_FROM_HANDLE(radv_device, device, _device);
5162 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5163
5164 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5165
5166 /* At the moment, we support only the below handle types. */
5167 assert(pGetFdInfo->handleType ==
5168 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5169 pGetFdInfo->handleType ==
5170 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5171
5172 bool ret = radv_get_memory_fd(device, memory, pFD);
5173 if (ret == false)
5174 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5175 return VK_SUCCESS;
5176 }
5177
5178 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5179 VkExternalMemoryHandleTypeFlagBits handleType,
5180 int fd,
5181 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5182 {
5183 RADV_FROM_HANDLE(radv_device, device, _device);
5184
5185 switch (handleType) {
5186 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5187 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5188 return VK_SUCCESS;
5189
5190 default:
5191 /* The valid usage section for this function says:
5192 *
5193 * "handleType must not be one of the handle types defined as
5194 * opaque."
5195 *
5196 * So opaque handle types fall into the default "unsupported" case.
5197 */
5198 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5199 }
5200 }
5201
5202 static VkResult radv_import_opaque_fd(struct radv_device *device,
5203 int fd,
5204 uint32_t *syncobj)
5205 {
5206 uint32_t syncobj_handle = 0;
5207 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5208 if (ret != 0)
5209 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5210
5211 if (*syncobj)
5212 device->ws->destroy_syncobj(device->ws, *syncobj);
5213
5214 *syncobj = syncobj_handle;
5215 close(fd);
5216
5217 return VK_SUCCESS;
5218 }
5219
5220 static VkResult radv_import_sync_fd(struct radv_device *device,
5221 int fd,
5222 uint32_t *syncobj)
5223 {
5224 /* If we create a syncobj we do it locally so that if we have an error, we don't
5225 * leave a syncobj in an undetermined state in the fence. */
5226 uint32_t syncobj_handle = *syncobj;
5227 if (!syncobj_handle) {
5228 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5229 if (ret) {
5230 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5231 }
5232 }
5233
5234 if (fd == -1) {
5235 device->ws->signal_syncobj(device->ws, syncobj_handle);
5236 } else {
5237 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5238 if (ret != 0)
5239 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5240 }
5241
5242 *syncobj = syncobj_handle;
5243 if (fd != -1)
5244 close(fd);
5245
5246 return VK_SUCCESS;
5247 }
5248
5249 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5250 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5251 {
5252 RADV_FROM_HANDLE(radv_device, device, _device);
5253 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5254 uint32_t *syncobj_dst = NULL;
5255
5256 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5257 syncobj_dst = &sem->temp_syncobj;
5258 } else {
5259 syncobj_dst = &sem->syncobj;
5260 }
5261
5262 switch(pImportSemaphoreFdInfo->handleType) {
5263 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5264 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5265 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5266 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5267 default:
5268 unreachable("Unhandled semaphore handle type");
5269 }
5270 }
5271
5272 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5273 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5274 int *pFd)
5275 {
5276 RADV_FROM_HANDLE(radv_device, device, _device);
5277 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5278 int ret;
5279 uint32_t syncobj_handle;
5280
5281 if (sem->temp_syncobj)
5282 syncobj_handle = sem->temp_syncobj;
5283 else
5284 syncobj_handle = sem->syncobj;
5285
5286 switch(pGetFdInfo->handleType) {
5287 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5288 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5289 break;
5290 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5291 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5292 if (!ret) {
5293 if (sem->temp_syncobj) {
5294 close (sem->temp_syncobj);
5295 sem->temp_syncobj = 0;
5296 } else {
5297 device->ws->reset_syncobj(device->ws, syncobj_handle);
5298 }
5299 }
5300 break;
5301 default:
5302 unreachable("Unhandled semaphore handle type");
5303 }
5304
5305 if (ret)
5306 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5307 return VK_SUCCESS;
5308 }
5309
5310 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5311 VkPhysicalDevice physicalDevice,
5312 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5313 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5314 {
5315 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5316
5317 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5318 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5319 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5320 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5321 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5322 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5323 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5324 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5325 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5326 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5327 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5328 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5329 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5330 } else {
5331 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5332 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5333 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5334 }
5335 }
5336
5337 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5338 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5339 {
5340 RADV_FROM_HANDLE(radv_device, device, _device);
5341 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5342 uint32_t *syncobj_dst = NULL;
5343
5344
5345 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5346 syncobj_dst = &fence->temp_syncobj;
5347 } else {
5348 syncobj_dst = &fence->syncobj;
5349 }
5350
5351 switch(pImportFenceFdInfo->handleType) {
5352 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5353 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5354 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5355 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5356 default:
5357 unreachable("Unhandled fence handle type");
5358 }
5359 }
5360
5361 VkResult radv_GetFenceFdKHR(VkDevice _device,
5362 const VkFenceGetFdInfoKHR *pGetFdInfo,
5363 int *pFd)
5364 {
5365 RADV_FROM_HANDLE(radv_device, device, _device);
5366 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5367 int ret;
5368 uint32_t syncobj_handle;
5369
5370 if (fence->temp_syncobj)
5371 syncobj_handle = fence->temp_syncobj;
5372 else
5373 syncobj_handle = fence->syncobj;
5374
5375 switch(pGetFdInfo->handleType) {
5376 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5377 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5378 break;
5379 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5380 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5381 if (!ret) {
5382 if (fence->temp_syncobj) {
5383 close (fence->temp_syncobj);
5384 fence->temp_syncobj = 0;
5385 } else {
5386 device->ws->reset_syncobj(device->ws, syncobj_handle);
5387 }
5388 }
5389 break;
5390 default:
5391 unreachable("Unhandled fence handle type");
5392 }
5393
5394 if (ret)
5395 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5396 return VK_SUCCESS;
5397 }
5398
5399 void radv_GetPhysicalDeviceExternalFenceProperties(
5400 VkPhysicalDevice physicalDevice,
5401 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5402 VkExternalFenceProperties *pExternalFenceProperties)
5403 {
5404 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5405
5406 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5407 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5408 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5409 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5410 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5411 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5412 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5413 } else {
5414 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5415 pExternalFenceProperties->compatibleHandleTypes = 0;
5416 pExternalFenceProperties->externalFenceFeatures = 0;
5417 }
5418 }
5419
5420 VkResult
5421 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5422 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5423 const VkAllocationCallbacks* pAllocator,
5424 VkDebugReportCallbackEXT* pCallback)
5425 {
5426 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5427 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5428 pCreateInfo, pAllocator, &instance->alloc,
5429 pCallback);
5430 }
5431
5432 void
5433 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5434 VkDebugReportCallbackEXT _callback,
5435 const VkAllocationCallbacks* pAllocator)
5436 {
5437 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5438 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5439 _callback, pAllocator, &instance->alloc);
5440 }
5441
5442 void
5443 radv_DebugReportMessageEXT(VkInstance _instance,
5444 VkDebugReportFlagsEXT flags,
5445 VkDebugReportObjectTypeEXT objectType,
5446 uint64_t object,
5447 size_t location,
5448 int32_t messageCode,
5449 const char* pLayerPrefix,
5450 const char* pMessage)
5451 {
5452 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5453 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5454 object, location, messageCode, pLayerPrefix, pMessage);
5455 }
5456
5457 void
5458 radv_GetDeviceGroupPeerMemoryFeatures(
5459 VkDevice device,
5460 uint32_t heapIndex,
5461 uint32_t localDeviceIndex,
5462 uint32_t remoteDeviceIndex,
5463 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5464 {
5465 assert(localDeviceIndex == remoteDeviceIndex);
5466
5467 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5468 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5469 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5470 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5471 }
5472
5473 static const VkTimeDomainEXT radv_time_domains[] = {
5474 VK_TIME_DOMAIN_DEVICE_EXT,
5475 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5476 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5477 };
5478
5479 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5480 VkPhysicalDevice physicalDevice,
5481 uint32_t *pTimeDomainCount,
5482 VkTimeDomainEXT *pTimeDomains)
5483 {
5484 int d;
5485 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5486
5487 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5488 vk_outarray_append(&out, i) {
5489 *i = radv_time_domains[d];
5490 }
5491 }
5492
5493 return vk_outarray_status(&out);
5494 }
5495
5496 static uint64_t
5497 radv_clock_gettime(clockid_t clock_id)
5498 {
5499 struct timespec current;
5500 int ret;
5501
5502 ret = clock_gettime(clock_id, &current);
5503 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5504 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5505 if (ret < 0)
5506 return 0;
5507
5508 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5509 }
5510
5511 VkResult radv_GetCalibratedTimestampsEXT(
5512 VkDevice _device,
5513 uint32_t timestampCount,
5514 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5515 uint64_t *pTimestamps,
5516 uint64_t *pMaxDeviation)
5517 {
5518 RADV_FROM_HANDLE(radv_device, device, _device);
5519 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5520 int d;
5521 uint64_t begin, end;
5522 uint64_t max_clock_period = 0;
5523
5524 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5525
5526 for (d = 0; d < timestampCount; d++) {
5527 switch (pTimestampInfos[d].timeDomain) {
5528 case VK_TIME_DOMAIN_DEVICE_EXT:
5529 pTimestamps[d] = device->ws->query_value(device->ws,
5530 RADEON_TIMESTAMP);
5531 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5532 max_clock_period = MAX2(max_clock_period, device_period);
5533 break;
5534 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5535 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5536 max_clock_period = MAX2(max_clock_period, 1);
5537 break;
5538
5539 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5540 pTimestamps[d] = begin;
5541 break;
5542 default:
5543 pTimestamps[d] = 0;
5544 break;
5545 }
5546 }
5547
5548 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5549
5550 /*
5551 * The maximum deviation is the sum of the interval over which we
5552 * perform the sampling and the maximum period of any sampled
5553 * clock. That's because the maximum skew between any two sampled
5554 * clock edges is when the sampled clock with the largest period is
5555 * sampled at the end of that period but right at the beginning of the
5556 * sampling interval and some other clock is sampled right at the
5557 * begining of its sampling period and right at the end of the
5558 * sampling interval. Let's assume the GPU has the longest clock
5559 * period and that the application is sampling GPU and monotonic:
5560 *
5561 * s e
5562 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5563 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5564 *
5565 * g
5566 * 0 1 2 3
5567 * GPU -----_____-----_____-----_____-----_____
5568 *
5569 * m
5570 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5571 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5572 *
5573 * Interval <----------------->
5574 * Deviation <-------------------------->
5575 *
5576 * s = read(raw) 2
5577 * g = read(GPU) 1
5578 * m = read(monotonic) 2
5579 * e = read(raw) b
5580 *
5581 * We round the sample interval up by one tick to cover sampling error
5582 * in the interval clock
5583 */
5584
5585 uint64_t sample_interval = end - begin + 1;
5586
5587 *pMaxDeviation = sample_interval + max_clock_period;
5588
5589 return VK_SUCCESS;
5590 }
5591
5592 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5593 VkPhysicalDevice physicalDevice,
5594 VkSampleCountFlagBits samples,
5595 VkMultisamplePropertiesEXT* pMultisampleProperties)
5596 {
5597 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5598 VK_SAMPLE_COUNT_4_BIT |
5599 VK_SAMPLE_COUNT_8_BIT)) {
5600 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5601 } else {
5602 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5603 }
5604 }