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radv: export KHR_relaxed_block_layout
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 {
174 .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_BIND_MEMORY_2_EXTENSION_NAME,
179 .specVersion = 1,
180 },
181 {
182 .extensionName = VK_KHR_MAINTENANCE2_EXTENSION_NAME,
183 .specVersion = 1,
184 },
185 {
186 .extensionName = VK_KHR_RELAXED_BLOCK_LAYOUT_EXTENSION_NAME,
187 .specVersion = 1,
188 },
189 };
190
191 static const VkExtensionProperties rasterization_order_extension[] ={
192 {
193 .extensionName = VK_AMD_RASTERIZATION_ORDER_EXTENSION_NAME,
194 .specVersion = 1,
195 },
196 };
197
198 static const VkExtensionProperties ext_sema_device_extensions[] = {
199 {
200 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
201 .specVersion = 1,
202 },
203 {
204 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
205 .specVersion = 1,
206 },
207 {
208 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
209 .specVersion = 1,
210 },
211 };
212
213 static VkResult
214 radv_extensions_register(struct radv_instance *instance,
215 struct radv_extensions *extensions,
216 const VkExtensionProperties *new_ext,
217 uint32_t num_ext)
218 {
219 size_t new_size;
220 VkExtensionProperties *new_ptr;
221
222 assert(new_ext && num_ext > 0);
223
224 if (!new_ext)
225 return VK_ERROR_INITIALIZATION_FAILED;
226
227 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
228 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
229 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
230
231 /* Old array continues to be valid, update nothing */
232 if (!new_ptr)
233 return VK_ERROR_OUT_OF_HOST_MEMORY;
234
235 memcpy(&new_ptr[extensions->num_ext], new_ext,
236 num_ext * sizeof(VkExtensionProperties));
237 extensions->ext_array = new_ptr;
238 extensions->num_ext += num_ext;
239
240 return VK_SUCCESS;
241 }
242
243 static void
244 radv_extensions_finish(struct radv_instance *instance,
245 struct radv_extensions *extensions)
246 {
247 assert(extensions);
248
249 if (!extensions)
250 radv_loge("Attemted to free invalid extension struct\n");
251
252 if (extensions->ext_array)
253 vk_free(&instance->alloc, extensions->ext_array);
254 }
255
256 static bool
257 is_extension_enabled(const VkExtensionProperties *extensions,
258 size_t num_ext,
259 const char *name)
260 {
261 assert(extensions && name);
262
263 for (uint32_t i = 0; i < num_ext; i++) {
264 if (strcmp(name, extensions[i].extensionName) == 0)
265 return true;
266 }
267
268 return false;
269 }
270
271 static const char *
272 get_chip_name(enum radeon_family family)
273 {
274 switch (family) {
275 case CHIP_TAHITI: return "AMD RADV TAHITI";
276 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
277 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
278 case CHIP_OLAND: return "AMD RADV OLAND";
279 case CHIP_HAINAN: return "AMD RADV HAINAN";
280 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
281 case CHIP_KAVERI: return "AMD RADV KAVERI";
282 case CHIP_KABINI: return "AMD RADV KABINI";
283 case CHIP_HAWAII: return "AMD RADV HAWAII";
284 case CHIP_MULLINS: return "AMD RADV MULLINS";
285 case CHIP_TONGA: return "AMD RADV TONGA";
286 case CHIP_ICELAND: return "AMD RADV ICELAND";
287 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
288 case CHIP_FIJI: return "AMD RADV FIJI";
289 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
290 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
291 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
292 case CHIP_STONEY: return "AMD RADV STONEY";
293 case CHIP_VEGA10: return "AMD RADV VEGA";
294 case CHIP_RAVEN: return "AMD RADV RAVEN";
295 default: return "AMD RADV unknown";
296 }
297 }
298
299 static VkResult
300 radv_physical_device_init(struct radv_physical_device *device,
301 struct radv_instance *instance,
302 drmDevicePtr drm_device)
303 {
304 const char *path = drm_device->nodes[DRM_NODE_RENDER];
305 VkResult result;
306 drmVersionPtr version;
307 int fd;
308
309 fd = open(path, O_RDWR | O_CLOEXEC);
310 if (fd < 0)
311 return VK_ERROR_INCOMPATIBLE_DRIVER;
312
313 version = drmGetVersion(fd);
314 if (!version) {
315 close(fd);
316 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
317 "failed to get version %s: %m", path);
318 }
319
320 if (strcmp(version->name, "amdgpu")) {
321 drmFreeVersion(version);
322 close(fd);
323 return VK_ERROR_INCOMPATIBLE_DRIVER;
324 }
325 drmFreeVersion(version);
326
327 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
328 device->instance = instance;
329 assert(strlen(path) < ARRAY_SIZE(device->path));
330 strncpy(device->path, path, ARRAY_SIZE(device->path));
331
332 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
333 instance->perftest_flags);
334 if (!device->ws) {
335 result = VK_ERROR_INCOMPATIBLE_DRIVER;
336 goto fail;
337 }
338
339 device->local_fd = fd;
340 device->ws->query_info(device->ws, &device->rad_info);
341 result = radv_init_wsi(device);
342 if (result != VK_SUCCESS) {
343 device->ws->destroy(device->ws);
344 goto fail;
345 }
346
347 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
348 radv_finish_wsi(device);
349 device->ws->destroy(device->ws);
350 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
351 "cannot generate UUID");
352 goto fail;
353 }
354
355 result = radv_extensions_register(instance,
356 &device->extensions,
357 common_device_extensions,
358 ARRAY_SIZE(common_device_extensions));
359 if (result != VK_SUCCESS)
360 goto fail;
361
362 if (device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2) {
363 result = radv_extensions_register(instance,
364 &device->extensions,
365 rasterization_order_extension,
366 ARRAY_SIZE(rasterization_order_extension));
367 if (result != VK_SUCCESS)
368 goto fail;
369 }
370
371 if (device->rad_info.has_syncobj) {
372 result = radv_extensions_register(instance,
373 &device->extensions,
374 ext_sema_device_extensions,
375 ARRAY_SIZE(ext_sema_device_extensions));
376 if (result != VK_SUCCESS)
377 goto fail;
378 }
379
380 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
381 device->name = get_chip_name(device->rad_info.family);
382
383 radv_get_driver_uuid(&device->device_uuid);
384 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
385
386 if (device->rad_info.family == CHIP_STONEY ||
387 device->rad_info.chip_class >= GFX9) {
388 device->has_rbplus = true;
389 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
390 }
391
392 return VK_SUCCESS;
393
394 fail:
395 close(fd);
396 return result;
397 }
398
399 static void
400 radv_physical_device_finish(struct radv_physical_device *device)
401 {
402 radv_extensions_finish(device->instance, &device->extensions);
403 radv_finish_wsi(device);
404 device->ws->destroy(device->ws);
405 close(device->local_fd);
406 }
407
408 static void *
409 default_alloc_func(void *pUserData, size_t size, size_t align,
410 VkSystemAllocationScope allocationScope)
411 {
412 return malloc(size);
413 }
414
415 static void *
416 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
417 size_t align, VkSystemAllocationScope allocationScope)
418 {
419 return realloc(pOriginal, size);
420 }
421
422 static void
423 default_free_func(void *pUserData, void *pMemory)
424 {
425 free(pMemory);
426 }
427
428 static const VkAllocationCallbacks default_alloc = {
429 .pUserData = NULL,
430 .pfnAllocation = default_alloc_func,
431 .pfnReallocation = default_realloc_func,
432 .pfnFree = default_free_func,
433 };
434
435 static const struct debug_control radv_debug_options[] = {
436 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
437 {"nodcc", RADV_DEBUG_NO_DCC},
438 {"shaders", RADV_DEBUG_DUMP_SHADERS},
439 {"nocache", RADV_DEBUG_NO_CACHE},
440 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
441 {"nohiz", RADV_DEBUG_NO_HIZ},
442 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
443 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
444 {"allbos", RADV_DEBUG_ALL_BOS},
445 {"noibs", RADV_DEBUG_NO_IBS},
446 {"spirv", RADV_DEBUG_DUMP_SPIRV},
447 {"vmfaults", RADV_DEBUG_VM_FAULTS},
448 {"zerovram", RADV_DEBUG_ZERO_VRAM},
449 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
450 {NULL, 0}
451 };
452
453 const char *
454 radv_get_debug_option_name(int id)
455 {
456 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
457 return radv_debug_options[id].string;
458 }
459
460 static const struct debug_control radv_perftest_options[] = {
461 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
462 {"sisched", RADV_PERFTEST_SISCHED},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_perftest_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_perftest_options[id].string;
471 }
472
473 VkResult radv_CreateInstance(
474 const VkInstanceCreateInfo* pCreateInfo,
475 const VkAllocationCallbacks* pAllocator,
476 VkInstance* pInstance)
477 {
478 struct radv_instance *instance;
479
480 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
481
482 uint32_t client_version;
483 if (pCreateInfo->pApplicationInfo &&
484 pCreateInfo->pApplicationInfo->apiVersion != 0) {
485 client_version = pCreateInfo->pApplicationInfo->apiVersion;
486 } else {
487 client_version = VK_MAKE_VERSION(1, 0, 0);
488 }
489
490 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
491 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
492 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
493 "Client requested version %d.%d.%d",
494 VK_VERSION_MAJOR(client_version),
495 VK_VERSION_MINOR(client_version),
496 VK_VERSION_PATCH(client_version));
497 }
498
499 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
500 if (!is_extension_enabled(instance_extensions,
501 ARRAY_SIZE(instance_extensions),
502 pCreateInfo->ppEnabledExtensionNames[i]))
503 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
504 }
505
506 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
507 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
508 if (!instance)
509 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
510
511 memset(instance, 0, sizeof(*instance));
512
513 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
514
515 if (pAllocator)
516 instance->alloc = *pAllocator;
517 else
518 instance->alloc = default_alloc;
519
520 instance->apiVersion = client_version;
521 instance->physicalDeviceCount = -1;
522
523 _mesa_locale_init();
524
525 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
526
527 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
528 radv_debug_options);
529
530 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
531 radv_perftest_options);
532
533 *pInstance = radv_instance_to_handle(instance);
534
535 return VK_SUCCESS;
536 }
537
538 void radv_DestroyInstance(
539 VkInstance _instance,
540 const VkAllocationCallbacks* pAllocator)
541 {
542 RADV_FROM_HANDLE(radv_instance, instance, _instance);
543
544 if (!instance)
545 return;
546
547 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
548 radv_physical_device_finish(instance->physicalDevices + i);
549 }
550
551 VG(VALGRIND_DESTROY_MEMPOOL(instance));
552
553 _mesa_locale_fini();
554
555 vk_free(&instance->alloc, instance);
556 }
557
558 static VkResult
559 radv_enumerate_devices(struct radv_instance *instance)
560 {
561 /* TODO: Check for more devices ? */
562 drmDevicePtr devices[8];
563 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
564 int max_devices;
565
566 instance->physicalDeviceCount = 0;
567
568 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
569 if (max_devices < 1)
570 return VK_ERROR_INCOMPATIBLE_DRIVER;
571
572 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
573 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
574 devices[i]->bustype == DRM_BUS_PCI &&
575 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
576
577 result = radv_physical_device_init(instance->physicalDevices +
578 instance->physicalDeviceCount,
579 instance,
580 devices[i]);
581 if (result == VK_SUCCESS)
582 ++instance->physicalDeviceCount;
583 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
584 break;
585 }
586 }
587 drmFreeDevices(devices, max_devices);
588
589 return result;
590 }
591
592 VkResult radv_EnumeratePhysicalDevices(
593 VkInstance _instance,
594 uint32_t* pPhysicalDeviceCount,
595 VkPhysicalDevice* pPhysicalDevices)
596 {
597 RADV_FROM_HANDLE(radv_instance, instance, _instance);
598 VkResult result;
599
600 if (instance->physicalDeviceCount < 0) {
601 result = radv_enumerate_devices(instance);
602 if (result != VK_SUCCESS &&
603 result != VK_ERROR_INCOMPATIBLE_DRIVER)
604 return result;
605 }
606
607 if (!pPhysicalDevices) {
608 *pPhysicalDeviceCount = instance->physicalDeviceCount;
609 } else {
610 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
611 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
612 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
613 }
614
615 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
616 : VK_SUCCESS;
617 }
618
619 void radv_GetPhysicalDeviceFeatures(
620 VkPhysicalDevice physicalDevice,
621 VkPhysicalDeviceFeatures* pFeatures)
622 {
623 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
624 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
625 memset(pFeatures, 0, sizeof(*pFeatures));
626
627 *pFeatures = (VkPhysicalDeviceFeatures) {
628 .robustBufferAccess = true,
629 .fullDrawIndexUint32 = true,
630 .imageCubeArray = true,
631 .independentBlend = true,
632 .geometryShader = !is_gfx9,
633 .tessellationShader = !is_gfx9,
634 .sampleRateShading = true,
635 .dualSrcBlend = true,
636 .logicOp = true,
637 .multiDrawIndirect = true,
638 .drawIndirectFirstInstance = true,
639 .depthClamp = true,
640 .depthBiasClamp = true,
641 .fillModeNonSolid = true,
642 .depthBounds = true,
643 .wideLines = true,
644 .largePoints = true,
645 .alphaToOne = true,
646 .multiViewport = true,
647 .samplerAnisotropy = true,
648 .textureCompressionETC2 = false,
649 .textureCompressionASTC_LDR = false,
650 .textureCompressionBC = true,
651 .occlusionQueryPrecise = true,
652 .pipelineStatisticsQuery = true,
653 .vertexPipelineStoresAndAtomics = true,
654 .fragmentStoresAndAtomics = true,
655 .shaderTessellationAndGeometryPointSize = true,
656 .shaderImageGatherExtended = true,
657 .shaderStorageImageExtendedFormats = true,
658 .shaderStorageImageMultisample = false,
659 .shaderUniformBufferArrayDynamicIndexing = true,
660 .shaderSampledImageArrayDynamicIndexing = true,
661 .shaderStorageBufferArrayDynamicIndexing = true,
662 .shaderStorageImageArrayDynamicIndexing = true,
663 .shaderStorageImageReadWithoutFormat = true,
664 .shaderStorageImageWriteWithoutFormat = true,
665 .shaderClipDistance = true,
666 .shaderCullDistance = true,
667 .shaderFloat64 = true,
668 .shaderInt64 = true,
669 .shaderInt16 = false,
670 .sparseBinding = true,
671 .variableMultisampleRate = true,
672 .inheritedQueries = true,
673 };
674 }
675
676 void radv_GetPhysicalDeviceFeatures2KHR(
677 VkPhysicalDevice physicalDevice,
678 VkPhysicalDeviceFeatures2KHR *pFeatures)
679 {
680 vk_foreach_struct(ext, pFeatures->pNext) {
681 switch (ext->sType) {
682 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
683 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
684 features->variablePointersStorageBuffer = true;
685 features->variablePointers = false;
686 break;
687 }
688 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
689 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
690 features->multiview = true;
691 features->multiviewGeometryShader = true;
692 features->multiviewTessellationShader = true;
693 break;
694 }
695 default:
696 break;
697 }
698 }
699 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
700 }
701
702 void radv_GetPhysicalDeviceProperties(
703 VkPhysicalDevice physicalDevice,
704 VkPhysicalDeviceProperties* pProperties)
705 {
706 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
707 VkSampleCountFlags sample_counts = 0xf;
708
709 /* make sure that the entire descriptor set is addressable with a signed
710 * 32-bit int. So the sum of all limits scaled by descriptor size has to
711 * be at most 2 GiB. the combined image & samples object count as one of
712 * both. This limit is for the pipeline layout, not for the set layout, but
713 * there is no set limit, so we just set a pipeline limit. I don't think
714 * any app is going to hit this soon. */
715 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
716 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
717 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
718 32 /* sampler, largest when combined with image */ +
719 64 /* sampled image */ +
720 64 /* storage image */);
721
722 VkPhysicalDeviceLimits limits = {
723 .maxImageDimension1D = (1 << 14),
724 .maxImageDimension2D = (1 << 14),
725 .maxImageDimension3D = (1 << 11),
726 .maxImageDimensionCube = (1 << 14),
727 .maxImageArrayLayers = (1 << 11),
728 .maxTexelBufferElements = 128 * 1024 * 1024,
729 .maxUniformBufferRange = UINT32_MAX,
730 .maxStorageBufferRange = UINT32_MAX,
731 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
732 .maxMemoryAllocationCount = UINT32_MAX,
733 .maxSamplerAllocationCount = 64 * 1024,
734 .bufferImageGranularity = 64, /* A cache line */
735 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
736 .maxBoundDescriptorSets = MAX_SETS,
737 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
738 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
739 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
740 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
741 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
742 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
743 .maxPerStageResources = max_descriptor_set_size,
744 .maxDescriptorSetSamplers = max_descriptor_set_size,
745 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
746 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
747 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
748 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
749 .maxDescriptorSetSampledImages = max_descriptor_set_size,
750 .maxDescriptorSetStorageImages = max_descriptor_set_size,
751 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
752 .maxVertexInputAttributes = 32,
753 .maxVertexInputBindings = 32,
754 .maxVertexInputAttributeOffset = 2047,
755 .maxVertexInputBindingStride = 2048,
756 .maxVertexOutputComponents = 128,
757 .maxTessellationGenerationLevel = 64,
758 .maxTessellationPatchSize = 32,
759 .maxTessellationControlPerVertexInputComponents = 128,
760 .maxTessellationControlPerVertexOutputComponents = 128,
761 .maxTessellationControlPerPatchOutputComponents = 120,
762 .maxTessellationControlTotalOutputComponents = 4096,
763 .maxTessellationEvaluationInputComponents = 128,
764 .maxTessellationEvaluationOutputComponents = 128,
765 .maxGeometryShaderInvocations = 127,
766 .maxGeometryInputComponents = 64,
767 .maxGeometryOutputComponents = 128,
768 .maxGeometryOutputVertices = 256,
769 .maxGeometryTotalOutputComponents = 1024,
770 .maxFragmentInputComponents = 128,
771 .maxFragmentOutputAttachments = 8,
772 .maxFragmentDualSrcAttachments = 1,
773 .maxFragmentCombinedOutputResources = 8,
774 .maxComputeSharedMemorySize = 32768,
775 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
776 .maxComputeWorkGroupInvocations = 2048,
777 .maxComputeWorkGroupSize = {
778 2048,
779 2048,
780 2048
781 },
782 .subPixelPrecisionBits = 4 /* FIXME */,
783 .subTexelPrecisionBits = 4 /* FIXME */,
784 .mipmapPrecisionBits = 4 /* FIXME */,
785 .maxDrawIndexedIndexValue = UINT32_MAX,
786 .maxDrawIndirectCount = UINT32_MAX,
787 .maxSamplerLodBias = 16,
788 .maxSamplerAnisotropy = 16,
789 .maxViewports = MAX_VIEWPORTS,
790 .maxViewportDimensions = { (1 << 14), (1 << 14) },
791 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
792 .viewportSubPixelBits = 13, /* We take a float? */
793 .minMemoryMapAlignment = 4096, /* A page */
794 .minTexelBufferOffsetAlignment = 1,
795 .minUniformBufferOffsetAlignment = 4,
796 .minStorageBufferOffsetAlignment = 4,
797 .minTexelOffset = -32,
798 .maxTexelOffset = 31,
799 .minTexelGatherOffset = -32,
800 .maxTexelGatherOffset = 31,
801 .minInterpolationOffset = -2,
802 .maxInterpolationOffset = 2,
803 .subPixelInterpolationOffsetBits = 8,
804 .maxFramebufferWidth = (1 << 14),
805 .maxFramebufferHeight = (1 << 14),
806 .maxFramebufferLayers = (1 << 10),
807 .framebufferColorSampleCounts = sample_counts,
808 .framebufferDepthSampleCounts = sample_counts,
809 .framebufferStencilSampleCounts = sample_counts,
810 .framebufferNoAttachmentsSampleCounts = sample_counts,
811 .maxColorAttachments = MAX_RTS,
812 .sampledImageColorSampleCounts = sample_counts,
813 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
814 .sampledImageDepthSampleCounts = sample_counts,
815 .sampledImageStencilSampleCounts = sample_counts,
816 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
817 .maxSampleMaskWords = 1,
818 .timestampComputeAndGraphics = true,
819 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
820 .maxClipDistances = 8,
821 .maxCullDistances = 8,
822 .maxCombinedClipAndCullDistances = 8,
823 .discreteQueuePriorities = 1,
824 .pointSizeRange = { 0.125, 255.875 },
825 .lineWidthRange = { 0.0, 7.9921875 },
826 .pointSizeGranularity = (1.0 / 8.0),
827 .lineWidthGranularity = (1.0 / 128.0),
828 .strictLines = false, /* FINISHME */
829 .standardSampleLocations = true,
830 .optimalBufferCopyOffsetAlignment = 128,
831 .optimalBufferCopyRowPitchAlignment = 128,
832 .nonCoherentAtomSize = 64,
833 };
834
835 *pProperties = (VkPhysicalDeviceProperties) {
836 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
837 .driverVersion = vk_get_driver_version(),
838 .vendorID = ATI_VENDOR_ID,
839 .deviceID = pdevice->rad_info.pci_id,
840 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
841 .limits = limits,
842 .sparseProperties = {0},
843 };
844
845 strcpy(pProperties->deviceName, pdevice->name);
846 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
847 }
848
849 void radv_GetPhysicalDeviceProperties2KHR(
850 VkPhysicalDevice physicalDevice,
851 VkPhysicalDeviceProperties2KHR *pProperties)
852 {
853 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
854 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
855
856 vk_foreach_struct(ext, pProperties->pNext) {
857 switch (ext->sType) {
858 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
859 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
860 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
861 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
862 break;
863 }
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
865 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
866 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
867 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
868 properties->deviceLUIDValid = false;
869 break;
870 }
871 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
872 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
873 properties->maxMultiviewViewCount = MAX_VIEWS;
874 properties->maxMultiviewInstanceIndex = INT_MAX;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
878 VkPhysicalDevicePointClippingPropertiesKHR *properties =
879 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
880 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
881 break;
882 }
883 default:
884 break;
885 }
886 }
887 }
888
889 static void radv_get_physical_device_queue_family_properties(
890 struct radv_physical_device* pdevice,
891 uint32_t* pCount,
892 VkQueueFamilyProperties** pQueueFamilyProperties)
893 {
894 int num_queue_families = 1;
895 int idx;
896 if (pdevice->rad_info.num_compute_rings > 0 &&
897 pdevice->rad_info.chip_class >= CIK &&
898 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
899 num_queue_families++;
900
901 if (pQueueFamilyProperties == NULL) {
902 *pCount = num_queue_families;
903 return;
904 }
905
906 if (!*pCount)
907 return;
908
909 idx = 0;
910 if (*pCount >= 1) {
911 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
912 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
913 VK_QUEUE_COMPUTE_BIT |
914 VK_QUEUE_TRANSFER_BIT |
915 VK_QUEUE_SPARSE_BINDING_BIT,
916 .queueCount = 1,
917 .timestampValidBits = 64,
918 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
919 };
920 idx++;
921 }
922
923 if (pdevice->rad_info.num_compute_rings > 0 &&
924 pdevice->rad_info.chip_class >= CIK &&
925 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
926 if (*pCount > idx) {
927 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
928 .queueFlags = VK_QUEUE_COMPUTE_BIT |
929 VK_QUEUE_TRANSFER_BIT |
930 VK_QUEUE_SPARSE_BINDING_BIT,
931 .queueCount = pdevice->rad_info.num_compute_rings,
932 .timestampValidBits = 64,
933 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
934 };
935 idx++;
936 }
937 }
938 *pCount = idx;
939 }
940
941 void radv_GetPhysicalDeviceQueueFamilyProperties(
942 VkPhysicalDevice physicalDevice,
943 uint32_t* pCount,
944 VkQueueFamilyProperties* pQueueFamilyProperties)
945 {
946 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
947 if (!pQueueFamilyProperties) {
948 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
949 return;
950 }
951 VkQueueFamilyProperties *properties[] = {
952 pQueueFamilyProperties + 0,
953 pQueueFamilyProperties + 1,
954 pQueueFamilyProperties + 2,
955 };
956 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
957 assert(*pCount <= 3);
958 }
959
960 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
961 VkPhysicalDevice physicalDevice,
962 uint32_t* pCount,
963 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
964 {
965 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
966 if (!pQueueFamilyProperties) {
967 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
968 return;
969 }
970 VkQueueFamilyProperties *properties[] = {
971 &pQueueFamilyProperties[0].queueFamilyProperties,
972 &pQueueFamilyProperties[1].queueFamilyProperties,
973 &pQueueFamilyProperties[2].queueFamilyProperties,
974 };
975 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
976 assert(*pCount <= 3);
977 }
978
979 void radv_GetPhysicalDeviceMemoryProperties(
980 VkPhysicalDevice physicalDevice,
981 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
982 {
983 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
984
985 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
986
987 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
988 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
989 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
990 .heapIndex = RADV_MEM_HEAP_VRAM,
991 };
992 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
993 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
994 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
995 .heapIndex = RADV_MEM_HEAP_GTT,
996 };
997 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
998 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
999 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
1000 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
1001 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
1002 };
1003 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
1004 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
1005 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
1006 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
1007 .heapIndex = RADV_MEM_HEAP_GTT,
1008 };
1009
1010 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
1011 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
1012 physical_device->rad_info.vram_vis_size);
1013
1014 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
1015 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
1016 .size = physical_device->rad_info.vram_size -
1017 visible_vram_size,
1018 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1019 };
1020 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
1021 .size = visible_vram_size,
1022 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1023 };
1024 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
1025 .size = physical_device->rad_info.gart_size,
1026 .flags = 0,
1027 };
1028 }
1029
1030 void radv_GetPhysicalDeviceMemoryProperties2KHR(
1031 VkPhysicalDevice physicalDevice,
1032 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1033 {
1034 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1035 &pMemoryProperties->memoryProperties);
1036 }
1037
1038 static int
1039 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1040 int queue_family_index, int idx)
1041 {
1042 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1043 queue->device = device;
1044 queue->queue_family_index = queue_family_index;
1045 queue->queue_idx = idx;
1046
1047 queue->hw_ctx = device->ws->ctx_create(device->ws);
1048 if (!queue->hw_ctx)
1049 return VK_ERROR_OUT_OF_HOST_MEMORY;
1050
1051 return VK_SUCCESS;
1052 }
1053
1054 static void
1055 radv_queue_finish(struct radv_queue *queue)
1056 {
1057 if (queue->hw_ctx)
1058 queue->device->ws->ctx_destroy(queue->hw_ctx);
1059
1060 if (queue->initial_full_flush_preamble_cs)
1061 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1062 if (queue->initial_preamble_cs)
1063 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1064 if (queue->continue_preamble_cs)
1065 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1066 if (queue->descriptor_bo)
1067 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1068 if (queue->scratch_bo)
1069 queue->device->ws->buffer_destroy(queue->scratch_bo);
1070 if (queue->esgs_ring_bo)
1071 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1072 if (queue->gsvs_ring_bo)
1073 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1074 if (queue->tess_factor_ring_bo)
1075 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1076 if (queue->tess_offchip_ring_bo)
1077 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1078 if (queue->compute_scratch_bo)
1079 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1080 }
1081
1082 static void
1083 radv_device_init_gs_info(struct radv_device *device)
1084 {
1085 switch (device->physical_device->rad_info.family) {
1086 case CHIP_OLAND:
1087 case CHIP_HAINAN:
1088 case CHIP_KAVERI:
1089 case CHIP_KABINI:
1090 case CHIP_MULLINS:
1091 case CHIP_ICELAND:
1092 case CHIP_CARRIZO:
1093 case CHIP_STONEY:
1094 device->gs_table_depth = 16;
1095 return;
1096 case CHIP_TAHITI:
1097 case CHIP_PITCAIRN:
1098 case CHIP_VERDE:
1099 case CHIP_BONAIRE:
1100 case CHIP_HAWAII:
1101 case CHIP_TONGA:
1102 case CHIP_FIJI:
1103 case CHIP_POLARIS10:
1104 case CHIP_POLARIS11:
1105 case CHIP_POLARIS12:
1106 case CHIP_VEGA10:
1107 case CHIP_RAVEN:
1108 device->gs_table_depth = 32;
1109 return;
1110 default:
1111 unreachable("unknown GPU");
1112 }
1113 }
1114
1115 VkResult radv_CreateDevice(
1116 VkPhysicalDevice physicalDevice,
1117 const VkDeviceCreateInfo* pCreateInfo,
1118 const VkAllocationCallbacks* pAllocator,
1119 VkDevice* pDevice)
1120 {
1121 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1122 VkResult result;
1123 struct radv_device *device;
1124
1125 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1126 if (!is_extension_enabled(physical_device->extensions.ext_array,
1127 physical_device->extensions.num_ext,
1128 pCreateInfo->ppEnabledExtensionNames[i]))
1129 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1130 }
1131
1132 /* Check enabled features */
1133 if (pCreateInfo->pEnabledFeatures) {
1134 VkPhysicalDeviceFeatures supported_features;
1135 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1136 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1137 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1138 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1139 for (uint32_t i = 0; i < num_features; i++) {
1140 if (enabled_feature[i] && !supported_feature[i])
1141 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1142 }
1143 }
1144
1145 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1146 sizeof(*device), 8,
1147 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1148 if (!device)
1149 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1150
1151 memset(device, 0, sizeof(*device));
1152
1153 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1154 device->instance = physical_device->instance;
1155 device->physical_device = physical_device;
1156
1157 device->debug_flags = device->instance->debug_flags;
1158
1159 device->ws = physical_device->ws;
1160 if (pAllocator)
1161 device->alloc = *pAllocator;
1162 else
1163 device->alloc = physical_device->instance->alloc;
1164
1165 mtx_init(&device->shader_slab_mutex, mtx_plain);
1166 list_inithead(&device->shader_slabs);
1167
1168 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1169 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1170 uint32_t qfi = queue_create->queueFamilyIndex;
1171
1172 device->queues[qfi] = vk_alloc(&device->alloc,
1173 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1174 if (!device->queues[qfi]) {
1175 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1176 goto fail;
1177 }
1178
1179 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1180
1181 device->queue_count[qfi] = queue_create->queueCount;
1182
1183 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1184 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1185 if (result != VK_SUCCESS)
1186 goto fail;
1187 }
1188 }
1189
1190 #if HAVE_LLVM < 0x0400
1191 device->llvm_supports_spill = false;
1192 #else
1193 device->llvm_supports_spill = true;
1194 #endif
1195
1196 /* The maximum number of scratch waves. Scratch space isn't divided
1197 * evenly between CUs. The number is only a function of the number of CUs.
1198 * We can decrease the constant to decrease the scratch buffer size.
1199 *
1200 * sctx->scratch_waves must be >= the maximum posible size of
1201 * 1 threadgroup, so that the hw doesn't hang from being unable
1202 * to start any.
1203 *
1204 * The recommended value is 4 per CU at most. Higher numbers don't
1205 * bring much benefit, but they still occupy chip resources (think
1206 * async compute). I've seen ~2% performance difference between 4 and 32.
1207 */
1208 uint32_t max_threads_per_block = 2048;
1209 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1210 max_threads_per_block / 64);
1211
1212 radv_device_init_gs_info(device);
1213
1214 device->tess_offchip_block_dw_size =
1215 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1216 device->has_distributed_tess =
1217 device->physical_device->rad_info.chip_class >= VI &&
1218 device->physical_device->rad_info.max_se >= 2;
1219
1220 if (getenv("RADV_TRACE_FILE")) {
1221 if (!radv_init_trace(device))
1222 goto fail;
1223 }
1224
1225 result = radv_device_init_meta(device);
1226 if (result != VK_SUCCESS)
1227 goto fail;
1228
1229 radv_device_init_msaa(device);
1230
1231 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1232 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1233 switch (family) {
1234 case RADV_QUEUE_GENERAL:
1235 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1236 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1237 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1238 break;
1239 case RADV_QUEUE_COMPUTE:
1240 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1241 radeon_emit(device->empty_cs[family], 0);
1242 break;
1243 }
1244 device->ws->cs_finalize(device->empty_cs[family]);
1245 }
1246
1247 if (device->physical_device->rad_info.chip_class >= CIK)
1248 cik_create_gfx_config(device);
1249
1250 VkPipelineCacheCreateInfo ci;
1251 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1252 ci.pNext = NULL;
1253 ci.flags = 0;
1254 ci.pInitialData = NULL;
1255 ci.initialDataSize = 0;
1256 VkPipelineCache pc;
1257 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1258 &ci, NULL, &pc);
1259 if (result != VK_SUCCESS)
1260 goto fail;
1261
1262 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1263
1264 *pDevice = radv_device_to_handle(device);
1265 return VK_SUCCESS;
1266
1267 fail:
1268 if (device->trace_bo)
1269 device->ws->buffer_destroy(device->trace_bo);
1270
1271 if (device->gfx_init)
1272 device->ws->buffer_destroy(device->gfx_init);
1273
1274 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1275 for (unsigned q = 0; q < device->queue_count[i]; q++)
1276 radv_queue_finish(&device->queues[i][q]);
1277 if (device->queue_count[i])
1278 vk_free(&device->alloc, device->queues[i]);
1279 }
1280
1281 vk_free(&device->alloc, device);
1282 return result;
1283 }
1284
1285 void radv_DestroyDevice(
1286 VkDevice _device,
1287 const VkAllocationCallbacks* pAllocator)
1288 {
1289 RADV_FROM_HANDLE(radv_device, device, _device);
1290
1291 if (!device)
1292 return;
1293
1294 if (device->trace_bo)
1295 device->ws->buffer_destroy(device->trace_bo);
1296
1297 if (device->gfx_init)
1298 device->ws->buffer_destroy(device->gfx_init);
1299
1300 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1301 for (unsigned q = 0; q < device->queue_count[i]; q++)
1302 radv_queue_finish(&device->queues[i][q]);
1303 if (device->queue_count[i])
1304 vk_free(&device->alloc, device->queues[i]);
1305 if (device->empty_cs[i])
1306 device->ws->cs_destroy(device->empty_cs[i]);
1307 }
1308 radv_device_finish_meta(device);
1309
1310 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1311 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1312
1313 radv_destroy_shader_slabs(device);
1314
1315 vk_free(&device->alloc, device);
1316 }
1317
1318 VkResult radv_EnumerateInstanceExtensionProperties(
1319 const char* pLayerName,
1320 uint32_t* pPropertyCount,
1321 VkExtensionProperties* pProperties)
1322 {
1323 if (pProperties == NULL) {
1324 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1325 return VK_SUCCESS;
1326 }
1327
1328 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1329 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1330
1331 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1332 return VK_INCOMPLETE;
1333
1334 return VK_SUCCESS;
1335 }
1336
1337 VkResult radv_EnumerateDeviceExtensionProperties(
1338 VkPhysicalDevice physicalDevice,
1339 const char* pLayerName,
1340 uint32_t* pPropertyCount,
1341 VkExtensionProperties* pProperties)
1342 {
1343 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1344
1345 if (pProperties == NULL) {
1346 *pPropertyCount = pdevice->extensions.num_ext;
1347 return VK_SUCCESS;
1348 }
1349
1350 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1351 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1352
1353 if (*pPropertyCount < pdevice->extensions.num_ext)
1354 return VK_INCOMPLETE;
1355
1356 return VK_SUCCESS;
1357 }
1358
1359 VkResult radv_EnumerateInstanceLayerProperties(
1360 uint32_t* pPropertyCount,
1361 VkLayerProperties* pProperties)
1362 {
1363 if (pProperties == NULL) {
1364 *pPropertyCount = 0;
1365 return VK_SUCCESS;
1366 }
1367
1368 /* None supported at this time */
1369 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1370 }
1371
1372 VkResult radv_EnumerateDeviceLayerProperties(
1373 VkPhysicalDevice physicalDevice,
1374 uint32_t* pPropertyCount,
1375 VkLayerProperties* pProperties)
1376 {
1377 if (pProperties == NULL) {
1378 *pPropertyCount = 0;
1379 return VK_SUCCESS;
1380 }
1381
1382 /* None supported at this time */
1383 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1384 }
1385
1386 void radv_GetDeviceQueue(
1387 VkDevice _device,
1388 uint32_t queueFamilyIndex,
1389 uint32_t queueIndex,
1390 VkQueue* pQueue)
1391 {
1392 RADV_FROM_HANDLE(radv_device, device, _device);
1393
1394 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1395 }
1396
1397 static void
1398 fill_geom_tess_rings(struct radv_queue *queue,
1399 uint32_t *map,
1400 bool add_sample_positions,
1401 uint32_t esgs_ring_size,
1402 struct radeon_winsys_bo *esgs_ring_bo,
1403 uint32_t gsvs_ring_size,
1404 struct radeon_winsys_bo *gsvs_ring_bo,
1405 uint32_t tess_factor_ring_size,
1406 struct radeon_winsys_bo *tess_factor_ring_bo,
1407 uint32_t tess_offchip_ring_size,
1408 struct radeon_winsys_bo *tess_offchip_ring_bo)
1409 {
1410 uint64_t esgs_va = 0, gsvs_va = 0;
1411 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1412 uint32_t *desc = &map[4];
1413
1414 if (esgs_ring_bo)
1415 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1416 if (gsvs_ring_bo)
1417 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1418 if (tess_factor_ring_bo)
1419 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1420 if (tess_offchip_ring_bo)
1421 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1422
1423 /* stride 0, num records - size, add tid, swizzle, elsize4,
1424 index stride 64 */
1425 desc[0] = esgs_va;
1426 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1427 S_008F04_STRIDE(0) |
1428 S_008F04_SWIZZLE_ENABLE(true);
1429 desc[2] = esgs_ring_size;
1430 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1431 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1432 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1433 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1434 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1435 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1436 S_008F0C_ELEMENT_SIZE(1) |
1437 S_008F0C_INDEX_STRIDE(3) |
1438 S_008F0C_ADD_TID_ENABLE(true);
1439
1440 desc += 4;
1441 /* GS entry for ES->GS ring */
1442 /* stride 0, num records - size, elsize0,
1443 index stride 0 */
1444 desc[0] = esgs_va;
1445 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1446 S_008F04_STRIDE(0) |
1447 S_008F04_SWIZZLE_ENABLE(false);
1448 desc[2] = esgs_ring_size;
1449 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1450 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1451 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1452 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1453 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1454 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1455 S_008F0C_ELEMENT_SIZE(0) |
1456 S_008F0C_INDEX_STRIDE(0) |
1457 S_008F0C_ADD_TID_ENABLE(false);
1458
1459 desc += 4;
1460 /* VS entry for GS->VS ring */
1461 /* stride 0, num records - size, elsize0,
1462 index stride 0 */
1463 desc[0] = gsvs_va;
1464 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1465 S_008F04_STRIDE(0) |
1466 S_008F04_SWIZZLE_ENABLE(false);
1467 desc[2] = gsvs_ring_size;
1468 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1469 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1470 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1471 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1472 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1473 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1474 S_008F0C_ELEMENT_SIZE(0) |
1475 S_008F0C_INDEX_STRIDE(0) |
1476 S_008F0C_ADD_TID_ENABLE(false);
1477 desc += 4;
1478
1479 /* stride gsvs_itemsize, num records 64
1480 elsize 4, index stride 16 */
1481 /* shader will patch stride and desc[2] */
1482 desc[0] = gsvs_va;
1483 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1484 S_008F04_STRIDE(0) |
1485 S_008F04_SWIZZLE_ENABLE(true);
1486 desc[2] = 0;
1487 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1488 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1489 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1490 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1491 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1492 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1493 S_008F0C_ELEMENT_SIZE(1) |
1494 S_008F0C_INDEX_STRIDE(1) |
1495 S_008F0C_ADD_TID_ENABLE(true);
1496 desc += 4;
1497
1498 desc[0] = tess_factor_va;
1499 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1500 S_008F04_STRIDE(0) |
1501 S_008F04_SWIZZLE_ENABLE(false);
1502 desc[2] = tess_factor_ring_size;
1503 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1504 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1505 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1506 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1507 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1508 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1509 S_008F0C_ELEMENT_SIZE(0) |
1510 S_008F0C_INDEX_STRIDE(0) |
1511 S_008F0C_ADD_TID_ENABLE(false);
1512 desc += 4;
1513
1514 desc[0] = tess_offchip_va;
1515 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1516 S_008F04_STRIDE(0) |
1517 S_008F04_SWIZZLE_ENABLE(false);
1518 desc[2] = tess_offchip_ring_size;
1519 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1520 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1521 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1522 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1523 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1524 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1525 S_008F0C_ELEMENT_SIZE(0) |
1526 S_008F0C_INDEX_STRIDE(0) |
1527 S_008F0C_ADD_TID_ENABLE(false);
1528 desc += 4;
1529
1530 /* add sample positions after all rings */
1531 memcpy(desc, queue->device->sample_locations_1x, 8);
1532 desc += 2;
1533 memcpy(desc, queue->device->sample_locations_2x, 16);
1534 desc += 4;
1535 memcpy(desc, queue->device->sample_locations_4x, 32);
1536 desc += 8;
1537 memcpy(desc, queue->device->sample_locations_8x, 64);
1538 desc += 16;
1539 memcpy(desc, queue->device->sample_locations_16x, 128);
1540 }
1541
1542 static unsigned
1543 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1544 {
1545 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1546 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1547 device->physical_device->rad_info.family != CHIP_STONEY;
1548 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1549 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1550 device->physical_device->rad_info.max_se;
1551 unsigned offchip_granularity;
1552 unsigned hs_offchip_param;
1553 switch (device->tess_offchip_block_dw_size) {
1554 default:
1555 assert(0);
1556 /* fall through */
1557 case 8192:
1558 offchip_granularity = V_03093C_X_8K_DWORDS;
1559 break;
1560 case 4096:
1561 offchip_granularity = V_03093C_X_4K_DWORDS;
1562 break;
1563 }
1564
1565 switch (device->physical_device->rad_info.chip_class) {
1566 case SI:
1567 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1568 break;
1569 case CIK:
1570 case VI:
1571 case GFX9:
1572 default:
1573 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1574 break;
1575 }
1576
1577 *max_offchip_buffers_p = max_offchip_buffers;
1578 if (device->physical_device->rad_info.chip_class >= CIK) {
1579 if (device->physical_device->rad_info.chip_class >= VI)
1580 --max_offchip_buffers;
1581 hs_offchip_param =
1582 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1583 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1584 } else {
1585 hs_offchip_param =
1586 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1587 }
1588 return hs_offchip_param;
1589 }
1590
1591 static VkResult
1592 radv_get_preamble_cs(struct radv_queue *queue,
1593 uint32_t scratch_size,
1594 uint32_t compute_scratch_size,
1595 uint32_t esgs_ring_size,
1596 uint32_t gsvs_ring_size,
1597 bool needs_tess_rings,
1598 bool needs_sample_positions,
1599 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1600 struct radeon_winsys_cs **initial_preamble_cs,
1601 struct radeon_winsys_cs **continue_preamble_cs)
1602 {
1603 struct radeon_winsys_bo *scratch_bo = NULL;
1604 struct radeon_winsys_bo *descriptor_bo = NULL;
1605 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1606 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1607 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1608 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1609 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1610 struct radeon_winsys_cs *dest_cs[3] = {0};
1611 bool add_tess_rings = false, add_sample_positions = false;
1612 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1613 unsigned max_offchip_buffers;
1614 unsigned hs_offchip_param = 0;
1615 if (!queue->has_tess_rings) {
1616 if (needs_tess_rings)
1617 add_tess_rings = true;
1618 }
1619 if (!queue->has_sample_positions) {
1620 if (needs_sample_positions)
1621 add_sample_positions = true;
1622 }
1623 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1624 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1625 &max_offchip_buffers);
1626 tess_offchip_ring_size = max_offchip_buffers *
1627 queue->device->tess_offchip_block_dw_size * 4;
1628
1629 if (scratch_size <= queue->scratch_size &&
1630 compute_scratch_size <= queue->compute_scratch_size &&
1631 esgs_ring_size <= queue->esgs_ring_size &&
1632 gsvs_ring_size <= queue->gsvs_ring_size &&
1633 !add_tess_rings && !add_sample_positions &&
1634 queue->initial_preamble_cs) {
1635 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1636 *initial_preamble_cs = queue->initial_preamble_cs;
1637 *continue_preamble_cs = queue->continue_preamble_cs;
1638 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1639 *continue_preamble_cs = NULL;
1640 return VK_SUCCESS;
1641 }
1642
1643 if (scratch_size > queue->scratch_size) {
1644 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1645 scratch_size,
1646 4096,
1647 RADEON_DOMAIN_VRAM,
1648 RADEON_FLAG_NO_CPU_ACCESS);
1649 if (!scratch_bo)
1650 goto fail;
1651 } else
1652 scratch_bo = queue->scratch_bo;
1653
1654 if (compute_scratch_size > queue->compute_scratch_size) {
1655 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1656 compute_scratch_size,
1657 4096,
1658 RADEON_DOMAIN_VRAM,
1659 RADEON_FLAG_NO_CPU_ACCESS);
1660 if (!compute_scratch_bo)
1661 goto fail;
1662
1663 } else
1664 compute_scratch_bo = queue->compute_scratch_bo;
1665
1666 if (esgs_ring_size > queue->esgs_ring_size) {
1667 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1668 esgs_ring_size,
1669 4096,
1670 RADEON_DOMAIN_VRAM,
1671 RADEON_FLAG_NO_CPU_ACCESS);
1672 if (!esgs_ring_bo)
1673 goto fail;
1674 } else {
1675 esgs_ring_bo = queue->esgs_ring_bo;
1676 esgs_ring_size = queue->esgs_ring_size;
1677 }
1678
1679 if (gsvs_ring_size > queue->gsvs_ring_size) {
1680 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1681 gsvs_ring_size,
1682 4096,
1683 RADEON_DOMAIN_VRAM,
1684 RADEON_FLAG_NO_CPU_ACCESS);
1685 if (!gsvs_ring_bo)
1686 goto fail;
1687 } else {
1688 gsvs_ring_bo = queue->gsvs_ring_bo;
1689 gsvs_ring_size = queue->gsvs_ring_size;
1690 }
1691
1692 if (add_tess_rings) {
1693 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1694 tess_factor_ring_size,
1695 256,
1696 RADEON_DOMAIN_VRAM,
1697 RADEON_FLAG_NO_CPU_ACCESS);
1698 if (!tess_factor_ring_bo)
1699 goto fail;
1700 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1701 tess_offchip_ring_size,
1702 256,
1703 RADEON_DOMAIN_VRAM,
1704 RADEON_FLAG_NO_CPU_ACCESS);
1705 if (!tess_offchip_ring_bo)
1706 goto fail;
1707 } else {
1708 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1709 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1710 }
1711
1712 if (scratch_bo != queue->scratch_bo ||
1713 esgs_ring_bo != queue->esgs_ring_bo ||
1714 gsvs_ring_bo != queue->gsvs_ring_bo ||
1715 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1716 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1717 uint32_t size = 0;
1718 if (gsvs_ring_bo || esgs_ring_bo ||
1719 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1720 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1721 if (add_sample_positions)
1722 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1723 }
1724 else if (scratch_bo)
1725 size = 8; /* 2 dword */
1726
1727 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1728 size,
1729 4096,
1730 RADEON_DOMAIN_VRAM,
1731 RADEON_FLAG_CPU_ACCESS);
1732 if (!descriptor_bo)
1733 goto fail;
1734 } else
1735 descriptor_bo = queue->descriptor_bo;
1736
1737 for(int i = 0; i < 3; ++i) {
1738 struct radeon_winsys_cs *cs = NULL;
1739 cs = queue->device->ws->cs_create(queue->device->ws,
1740 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1741 if (!cs)
1742 goto fail;
1743
1744 dest_cs[i] = cs;
1745
1746 if (scratch_bo)
1747 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1748
1749 if (esgs_ring_bo)
1750 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1751
1752 if (gsvs_ring_bo)
1753 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1754
1755 if (tess_factor_ring_bo)
1756 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1757
1758 if (tess_offchip_ring_bo)
1759 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1760
1761 if (descriptor_bo)
1762 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1763
1764 if (descriptor_bo != queue->descriptor_bo) {
1765 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1766
1767 if (scratch_bo) {
1768 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1769 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1770 S_008F04_SWIZZLE_ENABLE(1);
1771 map[0] = scratch_va;
1772 map[1] = rsrc1;
1773 }
1774
1775 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1776 add_sample_positions)
1777 fill_geom_tess_rings(queue, map, add_sample_positions,
1778 esgs_ring_size, esgs_ring_bo,
1779 gsvs_ring_size, gsvs_ring_bo,
1780 tess_factor_ring_size, tess_factor_ring_bo,
1781 tess_offchip_ring_size, tess_offchip_ring_bo);
1782
1783 queue->device->ws->buffer_unmap(descriptor_bo);
1784 }
1785
1786 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1787 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1788 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1789 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1790 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1791 }
1792
1793 if (esgs_ring_bo || gsvs_ring_bo) {
1794 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1795 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1796 radeon_emit(cs, esgs_ring_size >> 8);
1797 radeon_emit(cs, gsvs_ring_size >> 8);
1798 } else {
1799 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1800 radeon_emit(cs, esgs_ring_size >> 8);
1801 radeon_emit(cs, gsvs_ring_size >> 8);
1802 }
1803 }
1804
1805 if (tess_factor_ring_bo) {
1806 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1807 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1808 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1809 S_030938_SIZE(tess_factor_ring_size / 4));
1810 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1811 tf_va >> 8);
1812 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1813 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1814 tf_va >> 40);
1815 }
1816 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1817 } else {
1818 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1819 S_008988_SIZE(tess_factor_ring_size / 4));
1820 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1821 tf_va >> 8);
1822 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1823 hs_offchip_param);
1824 }
1825 }
1826
1827 if (descriptor_bo) {
1828 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1829 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1830 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1831 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1832 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1833 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1834
1835 uint64_t va = radv_buffer_get_va(descriptor_bo);
1836
1837 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1838 radeon_set_sh_reg_seq(cs, regs[i], 2);
1839 radeon_emit(cs, va);
1840 radeon_emit(cs, va >> 32);
1841 }
1842 }
1843
1844 if (compute_scratch_bo) {
1845 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1846 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1847 S_008F04_SWIZZLE_ENABLE(1);
1848
1849 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1850
1851 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1852 radeon_emit(cs, scratch_va);
1853 radeon_emit(cs, rsrc1);
1854 }
1855
1856 if (i == 0) {
1857 si_cs_emit_cache_flush(cs,
1858 false,
1859 queue->device->physical_device->rad_info.chip_class,
1860 NULL, 0,
1861 queue->queue_family_index == RING_COMPUTE &&
1862 queue->device->physical_device->rad_info.chip_class >= CIK,
1863 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1864 RADV_CMD_FLAG_INV_ICACHE |
1865 RADV_CMD_FLAG_INV_SMEM_L1 |
1866 RADV_CMD_FLAG_INV_VMEM_L1 |
1867 RADV_CMD_FLAG_INV_GLOBAL_L2);
1868 } else if (i == 1) {
1869 si_cs_emit_cache_flush(cs,
1870 false,
1871 queue->device->physical_device->rad_info.chip_class,
1872 NULL, 0,
1873 queue->queue_family_index == RING_COMPUTE &&
1874 queue->device->physical_device->rad_info.chip_class >= CIK,
1875 RADV_CMD_FLAG_INV_ICACHE |
1876 RADV_CMD_FLAG_INV_SMEM_L1 |
1877 RADV_CMD_FLAG_INV_VMEM_L1 |
1878 RADV_CMD_FLAG_INV_GLOBAL_L2);
1879 }
1880
1881 if (!queue->device->ws->cs_finalize(cs))
1882 goto fail;
1883 }
1884
1885 if (queue->initial_full_flush_preamble_cs)
1886 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1887
1888 if (queue->initial_preamble_cs)
1889 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1890
1891 if (queue->continue_preamble_cs)
1892 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1893
1894 queue->initial_full_flush_preamble_cs = dest_cs[0];
1895 queue->initial_preamble_cs = dest_cs[1];
1896 queue->continue_preamble_cs = dest_cs[2];
1897
1898 if (scratch_bo != queue->scratch_bo) {
1899 if (queue->scratch_bo)
1900 queue->device->ws->buffer_destroy(queue->scratch_bo);
1901 queue->scratch_bo = scratch_bo;
1902 queue->scratch_size = scratch_size;
1903 }
1904
1905 if (compute_scratch_bo != queue->compute_scratch_bo) {
1906 if (queue->compute_scratch_bo)
1907 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1908 queue->compute_scratch_bo = compute_scratch_bo;
1909 queue->compute_scratch_size = compute_scratch_size;
1910 }
1911
1912 if (esgs_ring_bo != queue->esgs_ring_bo) {
1913 if (queue->esgs_ring_bo)
1914 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1915 queue->esgs_ring_bo = esgs_ring_bo;
1916 queue->esgs_ring_size = esgs_ring_size;
1917 }
1918
1919 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1920 if (queue->gsvs_ring_bo)
1921 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1922 queue->gsvs_ring_bo = gsvs_ring_bo;
1923 queue->gsvs_ring_size = gsvs_ring_size;
1924 }
1925
1926 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1927 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1928 }
1929
1930 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1931 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1932 queue->has_tess_rings = true;
1933 }
1934
1935 if (descriptor_bo != queue->descriptor_bo) {
1936 if (queue->descriptor_bo)
1937 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1938
1939 queue->descriptor_bo = descriptor_bo;
1940 }
1941
1942 if (add_sample_positions)
1943 queue->has_sample_positions = true;
1944
1945 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1946 *initial_preamble_cs = queue->initial_preamble_cs;
1947 *continue_preamble_cs = queue->continue_preamble_cs;
1948 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1949 *continue_preamble_cs = NULL;
1950 return VK_SUCCESS;
1951 fail:
1952 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1953 if (dest_cs[i])
1954 queue->device->ws->cs_destroy(dest_cs[i]);
1955 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1956 queue->device->ws->buffer_destroy(descriptor_bo);
1957 if (scratch_bo && scratch_bo != queue->scratch_bo)
1958 queue->device->ws->buffer_destroy(scratch_bo);
1959 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1960 queue->device->ws->buffer_destroy(compute_scratch_bo);
1961 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1962 queue->device->ws->buffer_destroy(esgs_ring_bo);
1963 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1964 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1965 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1966 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1967 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1968 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1969 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1970 }
1971
1972 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1973 int num_sems,
1974 const VkSemaphore *sems,
1975 bool reset_temp)
1976 {
1977 int syncobj_idx = 0, sem_idx = 0;
1978
1979 if (num_sems == 0)
1980 return VK_SUCCESS;
1981 for (uint32_t i = 0; i < num_sems; i++) {
1982 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1983
1984 if (sem->temp_syncobj || sem->syncobj)
1985 counts->syncobj_count++;
1986 else
1987 counts->sem_count++;
1988 }
1989
1990 if (counts->syncobj_count) {
1991 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1992 if (!counts->syncobj)
1993 return VK_ERROR_OUT_OF_HOST_MEMORY;
1994 }
1995
1996 if (counts->sem_count) {
1997 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1998 if (!counts->sem) {
1999 free(counts->syncobj);
2000 return VK_ERROR_OUT_OF_HOST_MEMORY;
2001 }
2002 }
2003
2004 for (uint32_t i = 0; i < num_sems; i++) {
2005 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2006
2007 if (sem->temp_syncobj) {
2008 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2009 if (reset_temp) {
2010 /* after we wait on a temp import - drop it */
2011 sem->temp_syncobj = 0;
2012 }
2013 }
2014 else if (sem->syncobj)
2015 counts->syncobj[syncobj_idx++] = sem->syncobj;
2016 else {
2017 assert(sem->sem);
2018 counts->sem[sem_idx++] = sem->sem;
2019 }
2020 }
2021
2022 return VK_SUCCESS;
2023 }
2024
2025 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2026 {
2027 free(sem_info->wait.syncobj);
2028 free(sem_info->wait.sem);
2029 free(sem_info->signal.syncobj);
2030 free(sem_info->signal.sem);
2031 }
2032
2033 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2034 int num_wait_sems,
2035 const VkSemaphore *wait_sems,
2036 int num_signal_sems,
2037 const VkSemaphore *signal_sems)
2038 {
2039 VkResult ret;
2040 memset(sem_info, 0, sizeof(*sem_info));
2041
2042 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2043 if (ret)
2044 return ret;
2045 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2046 if (ret)
2047 radv_free_sem_info(sem_info);
2048
2049 /* caller can override these */
2050 sem_info->cs_emit_wait = true;
2051 sem_info->cs_emit_signal = true;
2052 return ret;
2053 }
2054
2055 VkResult radv_QueueSubmit(
2056 VkQueue _queue,
2057 uint32_t submitCount,
2058 const VkSubmitInfo* pSubmits,
2059 VkFence _fence)
2060 {
2061 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2062 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2063 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2064 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2065 int ret;
2066 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2067 uint32_t scratch_size = 0;
2068 uint32_t compute_scratch_size = 0;
2069 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2070 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2071 VkResult result;
2072 bool fence_emitted = false;
2073 bool tess_rings_needed = false;
2074 bool sample_positions_needed = false;
2075
2076 /* Do this first so failing to allocate scratch buffers can't result in
2077 * partially executed submissions. */
2078 for (uint32_t i = 0; i < submitCount; i++) {
2079 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2080 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2081 pSubmits[i].pCommandBuffers[j]);
2082
2083 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2084 compute_scratch_size = MAX2(compute_scratch_size,
2085 cmd_buffer->compute_scratch_size_needed);
2086 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2087 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2088 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2089 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2090 }
2091 }
2092
2093 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2094 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2095 sample_positions_needed, &initial_flush_preamble_cs,
2096 &initial_preamble_cs, &continue_preamble_cs);
2097 if (result != VK_SUCCESS)
2098 return result;
2099
2100 for (uint32_t i = 0; i < submitCount; i++) {
2101 struct radeon_winsys_cs **cs_array;
2102 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2103 bool can_patch = true;
2104 uint32_t advance;
2105 struct radv_winsys_sem_info sem_info;
2106
2107 result = radv_alloc_sem_info(&sem_info,
2108 pSubmits[i].waitSemaphoreCount,
2109 pSubmits[i].pWaitSemaphores,
2110 pSubmits[i].signalSemaphoreCount,
2111 pSubmits[i].pSignalSemaphores);
2112 if (result != VK_SUCCESS)
2113 return result;
2114
2115 if (!pSubmits[i].commandBufferCount) {
2116 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2117 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2118 &queue->device->empty_cs[queue->queue_family_index],
2119 1, NULL, NULL,
2120 &sem_info,
2121 false, base_fence);
2122 if (ret) {
2123 radv_loge("failed to submit CS %d\n", i);
2124 abort();
2125 }
2126 fence_emitted = true;
2127 }
2128 radv_free_sem_info(&sem_info);
2129 continue;
2130 }
2131
2132 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2133 (pSubmits[i].commandBufferCount));
2134
2135 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2136 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2137 pSubmits[i].pCommandBuffers[j]);
2138 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2139
2140 cs_array[j] = cmd_buffer->cs;
2141 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2142 can_patch = false;
2143 }
2144
2145 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2146 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2147 advance = MIN2(max_cs_submission,
2148 pSubmits[i].commandBufferCount - j);
2149
2150 if (queue->device->trace_bo)
2151 *queue->device->trace_id_ptr = 0;
2152
2153 sem_info.cs_emit_wait = j == 0;
2154 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2155
2156 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2157 advance, initial_preamble, continue_preamble_cs,
2158 &sem_info,
2159 can_patch, base_fence);
2160
2161 if (ret) {
2162 radv_loge("failed to submit CS %d\n", i);
2163 abort();
2164 }
2165 fence_emitted = true;
2166 if (queue->device->trace_bo) {
2167 radv_check_gpu_hangs(queue, cs_array[j]);
2168 }
2169 }
2170
2171 radv_free_sem_info(&sem_info);
2172 free(cs_array);
2173 }
2174
2175 if (fence) {
2176 if (!fence_emitted) {
2177 struct radv_winsys_sem_info sem_info = {0};
2178 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2179 &queue->device->empty_cs[queue->queue_family_index],
2180 1, NULL, NULL, &sem_info,
2181 false, base_fence);
2182 }
2183 fence->submitted = true;
2184 }
2185
2186 return VK_SUCCESS;
2187 }
2188
2189 VkResult radv_QueueWaitIdle(
2190 VkQueue _queue)
2191 {
2192 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2193
2194 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2195 radv_queue_family_to_ring(queue->queue_family_index),
2196 queue->queue_idx);
2197 return VK_SUCCESS;
2198 }
2199
2200 VkResult radv_DeviceWaitIdle(
2201 VkDevice _device)
2202 {
2203 RADV_FROM_HANDLE(radv_device, device, _device);
2204
2205 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2206 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2207 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2208 }
2209 }
2210 return VK_SUCCESS;
2211 }
2212
2213 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2214 VkInstance instance,
2215 const char* pName)
2216 {
2217 return radv_lookup_entrypoint(pName);
2218 }
2219
2220 /* The loader wants us to expose a second GetInstanceProcAddr function
2221 * to work around certain LD_PRELOAD issues seen in apps.
2222 */
2223 PUBLIC
2224 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2225 VkInstance instance,
2226 const char* pName);
2227
2228 PUBLIC
2229 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2230 VkInstance instance,
2231 const char* pName)
2232 {
2233 return radv_GetInstanceProcAddr(instance, pName);
2234 }
2235
2236 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2237 VkDevice device,
2238 const char* pName)
2239 {
2240 return radv_lookup_entrypoint(pName);
2241 }
2242
2243 bool radv_get_memory_fd(struct radv_device *device,
2244 struct radv_device_memory *memory,
2245 int *pFD)
2246 {
2247 struct radeon_bo_metadata metadata;
2248
2249 if (memory->image) {
2250 radv_init_metadata(device, memory->image, &metadata);
2251 device->ws->buffer_set_metadata(memory->bo, &metadata);
2252 }
2253
2254 return device->ws->buffer_get_fd(device->ws, memory->bo,
2255 pFD);
2256 }
2257
2258 VkResult radv_AllocateMemory(
2259 VkDevice _device,
2260 const VkMemoryAllocateInfo* pAllocateInfo,
2261 const VkAllocationCallbacks* pAllocator,
2262 VkDeviceMemory* pMem)
2263 {
2264 RADV_FROM_HANDLE(radv_device, device, _device);
2265 struct radv_device_memory *mem;
2266 VkResult result;
2267 enum radeon_bo_domain domain;
2268 uint32_t flags = 0;
2269
2270 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2271
2272 if (pAllocateInfo->allocationSize == 0) {
2273 /* Apparently, this is allowed */
2274 *pMem = VK_NULL_HANDLE;
2275 return VK_SUCCESS;
2276 }
2277
2278 const VkImportMemoryFdInfoKHR *import_info =
2279 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2280 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2281 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2282
2283 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2284 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2285 if (mem == NULL)
2286 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2287
2288 if (dedicate_info) {
2289 mem->image = radv_image_from_handle(dedicate_info->image);
2290 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2291 } else {
2292 mem->image = NULL;
2293 mem->buffer = NULL;
2294 }
2295
2296 if (import_info) {
2297 assert(import_info->handleType ==
2298 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2299 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2300 NULL, NULL);
2301 if (!mem->bo) {
2302 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2303 goto fail;
2304 } else {
2305 close(import_info->fd);
2306 goto out_success;
2307 }
2308 }
2309
2310 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2311 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2312 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2313 domain = RADEON_DOMAIN_GTT;
2314 else
2315 domain = RADEON_DOMAIN_VRAM;
2316
2317 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2318 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2319 else
2320 flags |= RADEON_FLAG_CPU_ACCESS;
2321
2322 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2323 flags |= RADEON_FLAG_GTT_WC;
2324
2325 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2326 domain, flags);
2327
2328 if (!mem->bo) {
2329 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2330 goto fail;
2331 }
2332 mem->type_index = pAllocateInfo->memoryTypeIndex;
2333 out_success:
2334 *pMem = radv_device_memory_to_handle(mem);
2335
2336 return VK_SUCCESS;
2337
2338 fail:
2339 vk_free2(&device->alloc, pAllocator, mem);
2340
2341 return result;
2342 }
2343
2344 void radv_FreeMemory(
2345 VkDevice _device,
2346 VkDeviceMemory _mem,
2347 const VkAllocationCallbacks* pAllocator)
2348 {
2349 RADV_FROM_HANDLE(radv_device, device, _device);
2350 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2351
2352 if (mem == NULL)
2353 return;
2354
2355 device->ws->buffer_destroy(mem->bo);
2356 mem->bo = NULL;
2357
2358 vk_free2(&device->alloc, pAllocator, mem);
2359 }
2360
2361 VkResult radv_MapMemory(
2362 VkDevice _device,
2363 VkDeviceMemory _memory,
2364 VkDeviceSize offset,
2365 VkDeviceSize size,
2366 VkMemoryMapFlags flags,
2367 void** ppData)
2368 {
2369 RADV_FROM_HANDLE(radv_device, device, _device);
2370 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2371
2372 if (mem == NULL) {
2373 *ppData = NULL;
2374 return VK_SUCCESS;
2375 }
2376
2377 *ppData = device->ws->buffer_map(mem->bo);
2378 if (*ppData) {
2379 *ppData += offset;
2380 return VK_SUCCESS;
2381 }
2382
2383 return VK_ERROR_MEMORY_MAP_FAILED;
2384 }
2385
2386 void radv_UnmapMemory(
2387 VkDevice _device,
2388 VkDeviceMemory _memory)
2389 {
2390 RADV_FROM_HANDLE(radv_device, device, _device);
2391 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2392
2393 if (mem == NULL)
2394 return;
2395
2396 device->ws->buffer_unmap(mem->bo);
2397 }
2398
2399 VkResult radv_FlushMappedMemoryRanges(
2400 VkDevice _device,
2401 uint32_t memoryRangeCount,
2402 const VkMappedMemoryRange* pMemoryRanges)
2403 {
2404 return VK_SUCCESS;
2405 }
2406
2407 VkResult radv_InvalidateMappedMemoryRanges(
2408 VkDevice _device,
2409 uint32_t memoryRangeCount,
2410 const VkMappedMemoryRange* pMemoryRanges)
2411 {
2412 return VK_SUCCESS;
2413 }
2414
2415 void radv_GetBufferMemoryRequirements(
2416 VkDevice device,
2417 VkBuffer _buffer,
2418 VkMemoryRequirements* pMemoryRequirements)
2419 {
2420 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2421
2422 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2423
2424 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2425 pMemoryRequirements->alignment = 4096;
2426 else
2427 pMemoryRequirements->alignment = 16;
2428
2429 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2430 }
2431
2432 void radv_GetBufferMemoryRequirements2KHR(
2433 VkDevice device,
2434 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2435 VkMemoryRequirements2KHR* pMemoryRequirements)
2436 {
2437 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2438 &pMemoryRequirements->memoryRequirements);
2439
2440 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2441 switch (ext->sType) {
2442 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2443 VkMemoryDedicatedRequirementsKHR *req =
2444 (VkMemoryDedicatedRequirementsKHR *) ext;
2445 req->requiresDedicatedAllocation = false;
2446 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2447 break;
2448 }
2449 default:
2450 break;
2451 }
2452 }
2453 }
2454
2455 void radv_GetImageMemoryRequirements(
2456 VkDevice device,
2457 VkImage _image,
2458 VkMemoryRequirements* pMemoryRequirements)
2459 {
2460 RADV_FROM_HANDLE(radv_image, image, _image);
2461
2462 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2463
2464 pMemoryRequirements->size = image->size;
2465 pMemoryRequirements->alignment = image->alignment;
2466 }
2467
2468 void radv_GetImageMemoryRequirements2KHR(
2469 VkDevice device,
2470 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2471 VkMemoryRequirements2KHR* pMemoryRequirements)
2472 {
2473 radv_GetImageMemoryRequirements(device, pInfo->image,
2474 &pMemoryRequirements->memoryRequirements);
2475
2476 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2477
2478 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2479 switch (ext->sType) {
2480 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2481 VkMemoryDedicatedRequirementsKHR *req =
2482 (VkMemoryDedicatedRequirementsKHR *) ext;
2483 req->requiresDedicatedAllocation = image->shareable;
2484 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2485 break;
2486 }
2487 default:
2488 break;
2489 }
2490 }
2491 }
2492
2493 void radv_GetImageSparseMemoryRequirements(
2494 VkDevice device,
2495 VkImage image,
2496 uint32_t* pSparseMemoryRequirementCount,
2497 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2498 {
2499 stub();
2500 }
2501
2502 void radv_GetImageSparseMemoryRequirements2KHR(
2503 VkDevice device,
2504 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2505 uint32_t* pSparseMemoryRequirementCount,
2506 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2507 {
2508 stub();
2509 }
2510
2511 void radv_GetDeviceMemoryCommitment(
2512 VkDevice device,
2513 VkDeviceMemory memory,
2514 VkDeviceSize* pCommittedMemoryInBytes)
2515 {
2516 *pCommittedMemoryInBytes = 0;
2517 }
2518
2519 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2520 uint32_t bindInfoCount,
2521 const VkBindBufferMemoryInfoKHR *pBindInfos)
2522 {
2523 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2524 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2525 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2526
2527 if (mem) {
2528 buffer->bo = mem->bo;
2529 buffer->offset = pBindInfos[i].memoryOffset;
2530 } else {
2531 buffer->bo = NULL;
2532 }
2533 }
2534 return VK_SUCCESS;
2535 }
2536
2537 VkResult radv_BindBufferMemory(
2538 VkDevice device,
2539 VkBuffer buffer,
2540 VkDeviceMemory memory,
2541 VkDeviceSize memoryOffset)
2542 {
2543 const VkBindBufferMemoryInfoKHR info = {
2544 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2545 .buffer = buffer,
2546 .memory = memory,
2547 .memoryOffset = memoryOffset
2548 };
2549
2550 return radv_BindBufferMemory2KHR(device, 1, &info);
2551 }
2552
2553 VkResult radv_BindImageMemory2KHR(VkDevice device,
2554 uint32_t bindInfoCount,
2555 const VkBindImageMemoryInfoKHR *pBindInfos)
2556 {
2557 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2558 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2559 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2560
2561 if (mem) {
2562 image->bo = mem->bo;
2563 image->offset = pBindInfos[i].memoryOffset;
2564 } else {
2565 image->bo = NULL;
2566 image->offset = 0;
2567 }
2568 }
2569 return VK_SUCCESS;
2570 }
2571
2572
2573 VkResult radv_BindImageMemory(
2574 VkDevice device,
2575 VkImage image,
2576 VkDeviceMemory memory,
2577 VkDeviceSize memoryOffset)
2578 {
2579 const VkBindImageMemoryInfoKHR info = {
2580 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2581 .image = image,
2582 .memory = memory,
2583 .memoryOffset = memoryOffset
2584 };
2585
2586 return radv_BindImageMemory2KHR(device, 1, &info);
2587 }
2588
2589
2590 static void
2591 radv_sparse_buffer_bind_memory(struct radv_device *device,
2592 const VkSparseBufferMemoryBindInfo *bind)
2593 {
2594 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2595
2596 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2597 struct radv_device_memory *mem = NULL;
2598
2599 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2600 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2601
2602 device->ws->buffer_virtual_bind(buffer->bo,
2603 bind->pBinds[i].resourceOffset,
2604 bind->pBinds[i].size,
2605 mem ? mem->bo : NULL,
2606 bind->pBinds[i].memoryOffset);
2607 }
2608 }
2609
2610 static void
2611 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2612 const VkSparseImageOpaqueMemoryBindInfo *bind)
2613 {
2614 RADV_FROM_HANDLE(radv_image, image, bind->image);
2615
2616 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2617 struct radv_device_memory *mem = NULL;
2618
2619 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2620 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2621
2622 device->ws->buffer_virtual_bind(image->bo,
2623 bind->pBinds[i].resourceOffset,
2624 bind->pBinds[i].size,
2625 mem ? mem->bo : NULL,
2626 bind->pBinds[i].memoryOffset);
2627 }
2628 }
2629
2630 VkResult radv_QueueBindSparse(
2631 VkQueue _queue,
2632 uint32_t bindInfoCount,
2633 const VkBindSparseInfo* pBindInfo,
2634 VkFence _fence)
2635 {
2636 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2637 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2638 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2639 bool fence_emitted = false;
2640
2641 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2642 struct radv_winsys_sem_info sem_info;
2643 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2644 radv_sparse_buffer_bind_memory(queue->device,
2645 pBindInfo[i].pBufferBinds + j);
2646 }
2647
2648 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2649 radv_sparse_image_opaque_bind_memory(queue->device,
2650 pBindInfo[i].pImageOpaqueBinds + j);
2651 }
2652
2653 VkResult result;
2654 result = radv_alloc_sem_info(&sem_info,
2655 pBindInfo[i].waitSemaphoreCount,
2656 pBindInfo[i].pWaitSemaphores,
2657 pBindInfo[i].signalSemaphoreCount,
2658 pBindInfo[i].pSignalSemaphores);
2659 if (result != VK_SUCCESS)
2660 return result;
2661
2662 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2663 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2664 &queue->device->empty_cs[queue->queue_family_index],
2665 1, NULL, NULL,
2666 &sem_info,
2667 false, base_fence);
2668 fence_emitted = true;
2669 if (fence)
2670 fence->submitted = true;
2671 }
2672
2673 radv_free_sem_info(&sem_info);
2674
2675 }
2676
2677 if (fence && !fence_emitted) {
2678 fence->signalled = true;
2679 }
2680
2681 return VK_SUCCESS;
2682 }
2683
2684 VkResult radv_CreateFence(
2685 VkDevice _device,
2686 const VkFenceCreateInfo* pCreateInfo,
2687 const VkAllocationCallbacks* pAllocator,
2688 VkFence* pFence)
2689 {
2690 RADV_FROM_HANDLE(radv_device, device, _device);
2691 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2692 sizeof(*fence), 8,
2693 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2694
2695 if (!fence)
2696 return VK_ERROR_OUT_OF_HOST_MEMORY;
2697
2698 memset(fence, 0, sizeof(*fence));
2699 fence->submitted = false;
2700 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2701 fence->fence = device->ws->create_fence();
2702 if (!fence->fence) {
2703 vk_free2(&device->alloc, pAllocator, fence);
2704 return VK_ERROR_OUT_OF_HOST_MEMORY;
2705 }
2706
2707 *pFence = radv_fence_to_handle(fence);
2708
2709 return VK_SUCCESS;
2710 }
2711
2712 void radv_DestroyFence(
2713 VkDevice _device,
2714 VkFence _fence,
2715 const VkAllocationCallbacks* pAllocator)
2716 {
2717 RADV_FROM_HANDLE(radv_device, device, _device);
2718 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2719
2720 if (!fence)
2721 return;
2722 device->ws->destroy_fence(fence->fence);
2723 vk_free2(&device->alloc, pAllocator, fence);
2724 }
2725
2726 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2727 {
2728 uint64_t current_time;
2729 struct timespec tv;
2730
2731 clock_gettime(CLOCK_MONOTONIC, &tv);
2732 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2733
2734 timeout = MIN2(UINT64_MAX - current_time, timeout);
2735
2736 return current_time + timeout;
2737 }
2738
2739 VkResult radv_WaitForFences(
2740 VkDevice _device,
2741 uint32_t fenceCount,
2742 const VkFence* pFences,
2743 VkBool32 waitAll,
2744 uint64_t timeout)
2745 {
2746 RADV_FROM_HANDLE(radv_device, device, _device);
2747 timeout = radv_get_absolute_timeout(timeout);
2748
2749 if (!waitAll && fenceCount > 1) {
2750 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2751 }
2752
2753 for (uint32_t i = 0; i < fenceCount; ++i) {
2754 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2755 bool expired = false;
2756
2757 if (fence->signalled)
2758 continue;
2759
2760 if (!fence->submitted)
2761 return VK_TIMEOUT;
2762
2763 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2764 if (!expired)
2765 return VK_TIMEOUT;
2766
2767 fence->signalled = true;
2768 }
2769
2770 return VK_SUCCESS;
2771 }
2772
2773 VkResult radv_ResetFences(VkDevice device,
2774 uint32_t fenceCount,
2775 const VkFence *pFences)
2776 {
2777 for (unsigned i = 0; i < fenceCount; ++i) {
2778 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2779 fence->submitted = fence->signalled = false;
2780 }
2781
2782 return VK_SUCCESS;
2783 }
2784
2785 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2786 {
2787 RADV_FROM_HANDLE(radv_device, device, _device);
2788 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2789
2790 if (fence->signalled)
2791 return VK_SUCCESS;
2792 if (!fence->submitted)
2793 return VK_NOT_READY;
2794
2795 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2796 return VK_NOT_READY;
2797
2798 return VK_SUCCESS;
2799 }
2800
2801
2802 // Queue semaphore functions
2803
2804 VkResult radv_CreateSemaphore(
2805 VkDevice _device,
2806 const VkSemaphoreCreateInfo* pCreateInfo,
2807 const VkAllocationCallbacks* pAllocator,
2808 VkSemaphore* pSemaphore)
2809 {
2810 RADV_FROM_HANDLE(radv_device, device, _device);
2811 const VkExportSemaphoreCreateInfoKHR *export =
2812 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2813 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2814 export ? export->handleTypes : 0;
2815
2816 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2817 sizeof(*sem), 8,
2818 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2819 if (!sem)
2820 return VK_ERROR_OUT_OF_HOST_MEMORY;
2821
2822 sem->temp_syncobj = 0;
2823 /* create a syncobject if we are going to export this semaphore */
2824 if (handleTypes) {
2825 assert (device->physical_device->rad_info.has_syncobj);
2826 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2827 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2828 if (ret) {
2829 vk_free2(&device->alloc, pAllocator, sem);
2830 return VK_ERROR_OUT_OF_HOST_MEMORY;
2831 }
2832 sem->sem = NULL;
2833 } else {
2834 sem->sem = device->ws->create_sem(device->ws);
2835 if (!sem->sem) {
2836 vk_free2(&device->alloc, pAllocator, sem);
2837 return VK_ERROR_OUT_OF_HOST_MEMORY;
2838 }
2839 sem->syncobj = 0;
2840 }
2841
2842 *pSemaphore = radv_semaphore_to_handle(sem);
2843 return VK_SUCCESS;
2844 }
2845
2846 void radv_DestroySemaphore(
2847 VkDevice _device,
2848 VkSemaphore _semaphore,
2849 const VkAllocationCallbacks* pAllocator)
2850 {
2851 RADV_FROM_HANDLE(radv_device, device, _device);
2852 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2853 if (!_semaphore)
2854 return;
2855
2856 if (sem->syncobj)
2857 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2858 else
2859 device->ws->destroy_sem(sem->sem);
2860 vk_free2(&device->alloc, pAllocator, sem);
2861 }
2862
2863 VkResult radv_CreateEvent(
2864 VkDevice _device,
2865 const VkEventCreateInfo* pCreateInfo,
2866 const VkAllocationCallbacks* pAllocator,
2867 VkEvent* pEvent)
2868 {
2869 RADV_FROM_HANDLE(radv_device, device, _device);
2870 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2871 sizeof(*event), 8,
2872 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2873
2874 if (!event)
2875 return VK_ERROR_OUT_OF_HOST_MEMORY;
2876
2877 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2878 RADEON_DOMAIN_GTT,
2879 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2880 if (!event->bo) {
2881 vk_free2(&device->alloc, pAllocator, event);
2882 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2883 }
2884
2885 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2886
2887 *pEvent = radv_event_to_handle(event);
2888
2889 return VK_SUCCESS;
2890 }
2891
2892 void radv_DestroyEvent(
2893 VkDevice _device,
2894 VkEvent _event,
2895 const VkAllocationCallbacks* pAllocator)
2896 {
2897 RADV_FROM_HANDLE(radv_device, device, _device);
2898 RADV_FROM_HANDLE(radv_event, event, _event);
2899
2900 if (!event)
2901 return;
2902 device->ws->buffer_destroy(event->bo);
2903 vk_free2(&device->alloc, pAllocator, event);
2904 }
2905
2906 VkResult radv_GetEventStatus(
2907 VkDevice _device,
2908 VkEvent _event)
2909 {
2910 RADV_FROM_HANDLE(radv_event, event, _event);
2911
2912 if (*event->map == 1)
2913 return VK_EVENT_SET;
2914 return VK_EVENT_RESET;
2915 }
2916
2917 VkResult radv_SetEvent(
2918 VkDevice _device,
2919 VkEvent _event)
2920 {
2921 RADV_FROM_HANDLE(radv_event, event, _event);
2922 *event->map = 1;
2923
2924 return VK_SUCCESS;
2925 }
2926
2927 VkResult radv_ResetEvent(
2928 VkDevice _device,
2929 VkEvent _event)
2930 {
2931 RADV_FROM_HANDLE(radv_event, event, _event);
2932 *event->map = 0;
2933
2934 return VK_SUCCESS;
2935 }
2936
2937 VkResult radv_CreateBuffer(
2938 VkDevice _device,
2939 const VkBufferCreateInfo* pCreateInfo,
2940 const VkAllocationCallbacks* pAllocator,
2941 VkBuffer* pBuffer)
2942 {
2943 RADV_FROM_HANDLE(radv_device, device, _device);
2944 struct radv_buffer *buffer;
2945
2946 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2947
2948 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2949 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2950 if (buffer == NULL)
2951 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2952
2953 buffer->size = pCreateInfo->size;
2954 buffer->usage = pCreateInfo->usage;
2955 buffer->bo = NULL;
2956 buffer->offset = 0;
2957 buffer->flags = pCreateInfo->flags;
2958
2959 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2960 buffer->bo = device->ws->buffer_create(device->ws,
2961 align64(buffer->size, 4096),
2962 4096, 0, RADEON_FLAG_VIRTUAL);
2963 if (!buffer->bo) {
2964 vk_free2(&device->alloc, pAllocator, buffer);
2965 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2966 }
2967 }
2968
2969 *pBuffer = radv_buffer_to_handle(buffer);
2970
2971 return VK_SUCCESS;
2972 }
2973
2974 void radv_DestroyBuffer(
2975 VkDevice _device,
2976 VkBuffer _buffer,
2977 const VkAllocationCallbacks* pAllocator)
2978 {
2979 RADV_FROM_HANDLE(radv_device, device, _device);
2980 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2981
2982 if (!buffer)
2983 return;
2984
2985 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2986 device->ws->buffer_destroy(buffer->bo);
2987
2988 vk_free2(&device->alloc, pAllocator, buffer);
2989 }
2990
2991 static inline unsigned
2992 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2993 {
2994 if (stencil)
2995 return image->surface.u.legacy.stencil_tiling_index[level];
2996 else
2997 return image->surface.u.legacy.tiling_index[level];
2998 }
2999
3000 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
3001 {
3002 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
3003 }
3004
3005 static void
3006 radv_initialise_color_surface(struct radv_device *device,
3007 struct radv_color_buffer_info *cb,
3008 struct radv_image_view *iview)
3009 {
3010 const struct vk_format_description *desc;
3011 unsigned ntype, format, swap, endian;
3012 unsigned blend_clamp = 0, blend_bypass = 0;
3013 uint64_t va;
3014 const struct radeon_surf *surf = &iview->image->surface;
3015
3016 desc = vk_format_description(iview->vk_format);
3017
3018 memset(cb, 0, sizeof(*cb));
3019
3020 /* Intensity is implemented as Red, so treat it that way. */
3021 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3022
3023 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3024
3025 cb->cb_color_base = va >> 8;
3026
3027 if (device->physical_device->rad_info.chip_class >= GFX9) {
3028 struct gfx9_surf_meta_flags meta;
3029 if (iview->image->dcc_offset)
3030 meta = iview->image->surface.u.gfx9.dcc;
3031 else
3032 meta = iview->image->surface.u.gfx9.cmask;
3033
3034 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3035 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3036 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3037 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3038
3039 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3040 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3041 } else {
3042 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3043 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3044
3045 cb->cb_color_base += level_info->offset >> 8;
3046 if (level_info->mode == RADEON_SURF_MODE_2D)
3047 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3048
3049 pitch_tile_max = level_info->nblk_x / 8 - 1;
3050 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3051 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3052
3053 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3054 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3055 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3056
3057 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3058 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3059
3060 if (iview->image->fmask.size) {
3061 if (device->physical_device->rad_info.chip_class >= CIK)
3062 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3063 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3064 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3065 } else {
3066 /* This must be set for fast clear to work without FMASK. */
3067 if (device->physical_device->rad_info.chip_class >= CIK)
3068 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3069 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3070 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3071 }
3072 }
3073
3074 /* CMASK variables */
3075 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3076 va += iview->image->cmask.offset;
3077 cb->cb_color_cmask = va >> 8;
3078
3079 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3080 va += iview->image->dcc_offset;
3081 cb->cb_dcc_base = va >> 8;
3082 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3083
3084 uint32_t max_slice = radv_surface_layer_count(iview);
3085 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3086 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3087
3088 if (iview->image->info.samples > 1) {
3089 unsigned log_samples = util_logbase2(iview->image->info.samples);
3090
3091 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3092 S_028C74_NUM_FRAGMENTS(log_samples);
3093 }
3094
3095 if (iview->image->fmask.size) {
3096 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3097 cb->cb_color_fmask = va >> 8;
3098 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3099 } else {
3100 cb->cb_color_fmask = cb->cb_color_base;
3101 }
3102
3103 ntype = radv_translate_color_numformat(iview->vk_format,
3104 desc,
3105 vk_format_get_first_non_void_channel(iview->vk_format));
3106 format = radv_translate_colorformat(iview->vk_format);
3107 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3108 radv_finishme("Illegal color\n");
3109 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3110 endian = radv_colorformat_endian_swap(format);
3111
3112 /* blend clamp should be set for all NORM/SRGB types */
3113 if (ntype == V_028C70_NUMBER_UNORM ||
3114 ntype == V_028C70_NUMBER_SNORM ||
3115 ntype == V_028C70_NUMBER_SRGB)
3116 blend_clamp = 1;
3117
3118 /* set blend bypass according to docs if SINT/UINT or
3119 8/24 COLOR variants */
3120 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3121 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3122 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3123 blend_clamp = 0;
3124 blend_bypass = 1;
3125 }
3126 #if 0
3127 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3128 (format == V_028C70_COLOR_8 ||
3129 format == V_028C70_COLOR_8_8 ||
3130 format == V_028C70_COLOR_8_8_8_8))
3131 ->color_is_int8 = true;
3132 #endif
3133 cb->cb_color_info = S_028C70_FORMAT(format) |
3134 S_028C70_COMP_SWAP(swap) |
3135 S_028C70_BLEND_CLAMP(blend_clamp) |
3136 S_028C70_BLEND_BYPASS(blend_bypass) |
3137 S_028C70_SIMPLE_FLOAT(1) |
3138 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3139 ntype != V_028C70_NUMBER_SNORM &&
3140 ntype != V_028C70_NUMBER_SRGB &&
3141 format != V_028C70_COLOR_8_24 &&
3142 format != V_028C70_COLOR_24_8) |
3143 S_028C70_NUMBER_TYPE(ntype) |
3144 S_028C70_ENDIAN(endian);
3145 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3146 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3147 if (device->physical_device->rad_info.chip_class == SI) {
3148 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3149 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3150 }
3151 }
3152
3153 if (iview->image->cmask.size &&
3154 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3155 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3156
3157 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3158 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3159
3160 if (device->physical_device->rad_info.chip_class >= VI) {
3161 unsigned max_uncompressed_block_size = 2;
3162 if (iview->image->info.samples > 1) {
3163 if (iview->image->surface.bpe == 1)
3164 max_uncompressed_block_size = 0;
3165 else if (iview->image->surface.bpe == 2)
3166 max_uncompressed_block_size = 1;
3167 }
3168
3169 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3170 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3171 }
3172
3173 /* This must be set for fast clear to work without FMASK. */
3174 if (!iview->image->fmask.size &&
3175 device->physical_device->rad_info.chip_class == SI) {
3176 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3177 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3178 }
3179
3180 if (device->physical_device->rad_info.chip_class >= GFX9) {
3181 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3182 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3183
3184 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3185 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3186 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3187 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3188 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3189 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3190
3191 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3192
3193 }
3194 }
3195
3196 static void
3197 radv_initialise_ds_surface(struct radv_device *device,
3198 struct radv_ds_buffer_info *ds,
3199 struct radv_image_view *iview)
3200 {
3201 unsigned level = iview->base_mip;
3202 unsigned format, stencil_format;
3203 uint64_t va, s_offs, z_offs;
3204 bool stencil_only = false;
3205 memset(ds, 0, sizeof(*ds));
3206 switch (iview->image->vk_format) {
3207 case VK_FORMAT_D24_UNORM_S8_UINT:
3208 case VK_FORMAT_X8_D24_UNORM_PACK32:
3209 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3210 ds->offset_scale = 2.0f;
3211 break;
3212 case VK_FORMAT_D16_UNORM:
3213 case VK_FORMAT_D16_UNORM_S8_UINT:
3214 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3215 ds->offset_scale = 4.0f;
3216 break;
3217 case VK_FORMAT_D32_SFLOAT:
3218 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3219 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3220 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3221 ds->offset_scale = 1.0f;
3222 break;
3223 case VK_FORMAT_S8_UINT:
3224 stencil_only = true;
3225 break;
3226 default:
3227 break;
3228 }
3229
3230 format = radv_translate_dbformat(iview->image->vk_format);
3231 stencil_format = iview->image->surface.has_stencil ?
3232 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3233
3234 uint32_t max_slice = radv_surface_layer_count(iview);
3235 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3236 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3237
3238 ds->db_htile_data_base = 0;
3239 ds->db_htile_surface = 0;
3240
3241 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3242 s_offs = z_offs = va;
3243
3244 if (device->physical_device->rad_info.chip_class >= GFX9) {
3245 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3246 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3247
3248 ds->db_z_info = S_028038_FORMAT(format) |
3249 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3250 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3251 S_028038_MAXMIP(iview->image->info.levels - 1);
3252 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3253 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3254
3255 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3256 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3257 ds->db_depth_view |= S_028008_MIPID(level);
3258
3259 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3260 S_02801C_Y_MAX(iview->image->info.height - 1);
3261
3262 if (radv_htile_enabled(iview->image, level)) {
3263 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3264
3265 if (iview->image->tc_compatible_htile) {
3266 unsigned max_zplanes = 4;
3267
3268 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3269 iview->image->info.samples > 1)
3270 max_zplanes = 2;
3271
3272 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3273 S_028038_ITERATE_FLUSH(1);
3274 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3275 }
3276
3277 if (!iview->image->surface.has_stencil)
3278 /* Use all of the htile_buffer for depth if there's no stencil. */
3279 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3280 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3281 iview->image->htile_offset;
3282 ds->db_htile_data_base = va >> 8;
3283 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3284 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3285 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3286 }
3287 } else {
3288 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3289
3290 if (stencil_only)
3291 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3292
3293 z_offs += iview->image->surface.u.legacy.level[level].offset;
3294 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3295
3296 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3297 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3298 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3299
3300 if (iview->image->info.samples > 1)
3301 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3302
3303 if (device->physical_device->rad_info.chip_class >= CIK) {
3304 struct radeon_info *info = &device->physical_device->rad_info;
3305 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3306 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3307 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3308 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3309 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3310 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3311
3312 if (stencil_only)
3313 tile_mode = stencil_tile_mode;
3314
3315 ds->db_depth_info |=
3316 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3317 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3318 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3319 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3320 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3321 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3322 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3323 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3324 } else {
3325 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3326 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3327 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3328 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3329 if (stencil_only)
3330 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3331 }
3332
3333 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3334 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3335 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3336
3337 if (radv_htile_enabled(iview->image, level)) {
3338 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3339
3340 if (!iview->image->surface.has_stencil &&
3341 !iview->image->tc_compatible_htile)
3342 /* Use all of the htile_buffer for depth if there's no stencil. */
3343 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3344
3345 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3346 iview->image->htile_offset;
3347 ds->db_htile_data_base = va >> 8;
3348 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3349
3350 if (iview->image->tc_compatible_htile) {
3351 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3352
3353 if (iview->image->info.samples <= 1)
3354 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3355 else if (iview->image->info.samples <= 4)
3356 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3357 else
3358 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3359 }
3360 }
3361 }
3362
3363 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3364 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3365 }
3366
3367 VkResult radv_CreateFramebuffer(
3368 VkDevice _device,
3369 const VkFramebufferCreateInfo* pCreateInfo,
3370 const VkAllocationCallbacks* pAllocator,
3371 VkFramebuffer* pFramebuffer)
3372 {
3373 RADV_FROM_HANDLE(radv_device, device, _device);
3374 struct radv_framebuffer *framebuffer;
3375
3376 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3377
3378 size_t size = sizeof(*framebuffer) +
3379 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3380 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3381 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3382 if (framebuffer == NULL)
3383 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3384
3385 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3386 framebuffer->width = pCreateInfo->width;
3387 framebuffer->height = pCreateInfo->height;
3388 framebuffer->layers = pCreateInfo->layers;
3389 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3390 VkImageView _iview = pCreateInfo->pAttachments[i];
3391 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3392 framebuffer->attachments[i].attachment = iview;
3393 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3394 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3395 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3396 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3397 }
3398 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3399 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3400 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3401 }
3402
3403 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3404 return VK_SUCCESS;
3405 }
3406
3407 void radv_DestroyFramebuffer(
3408 VkDevice _device,
3409 VkFramebuffer _fb,
3410 const VkAllocationCallbacks* pAllocator)
3411 {
3412 RADV_FROM_HANDLE(radv_device, device, _device);
3413 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3414
3415 if (!fb)
3416 return;
3417 vk_free2(&device->alloc, pAllocator, fb);
3418 }
3419
3420 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3421 {
3422 switch (address_mode) {
3423 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3424 return V_008F30_SQ_TEX_WRAP;
3425 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3426 return V_008F30_SQ_TEX_MIRROR;
3427 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3428 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3429 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3430 return V_008F30_SQ_TEX_CLAMP_BORDER;
3431 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3432 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3433 default:
3434 unreachable("illegal tex wrap mode");
3435 break;
3436 }
3437 }
3438
3439 static unsigned
3440 radv_tex_compare(VkCompareOp op)
3441 {
3442 switch (op) {
3443 case VK_COMPARE_OP_NEVER:
3444 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3445 case VK_COMPARE_OP_LESS:
3446 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3447 case VK_COMPARE_OP_EQUAL:
3448 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3449 case VK_COMPARE_OP_LESS_OR_EQUAL:
3450 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3451 case VK_COMPARE_OP_GREATER:
3452 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3453 case VK_COMPARE_OP_NOT_EQUAL:
3454 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3455 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3456 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3457 case VK_COMPARE_OP_ALWAYS:
3458 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3459 default:
3460 unreachable("illegal compare mode");
3461 break;
3462 }
3463 }
3464
3465 static unsigned
3466 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3467 {
3468 switch (filter) {
3469 case VK_FILTER_NEAREST:
3470 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3471 V_008F38_SQ_TEX_XY_FILTER_POINT);
3472 case VK_FILTER_LINEAR:
3473 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3474 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3475 case VK_FILTER_CUBIC_IMG:
3476 default:
3477 fprintf(stderr, "illegal texture filter");
3478 return 0;
3479 }
3480 }
3481
3482 static unsigned
3483 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3484 {
3485 switch (mode) {
3486 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3487 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3488 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3489 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3490 default:
3491 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3492 }
3493 }
3494
3495 static unsigned
3496 radv_tex_bordercolor(VkBorderColor bcolor)
3497 {
3498 switch (bcolor) {
3499 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3500 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3501 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3502 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3503 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3504 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3505 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3506 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3507 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3508 default:
3509 break;
3510 }
3511 return 0;
3512 }
3513
3514 static unsigned
3515 radv_tex_aniso_filter(unsigned filter)
3516 {
3517 if (filter < 2)
3518 return 0;
3519 if (filter < 4)
3520 return 1;
3521 if (filter < 8)
3522 return 2;
3523 if (filter < 16)
3524 return 3;
3525 return 4;
3526 }
3527
3528 static void
3529 radv_init_sampler(struct radv_device *device,
3530 struct radv_sampler *sampler,
3531 const VkSamplerCreateInfo *pCreateInfo)
3532 {
3533 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3534 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3535 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3536 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3537
3538 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3539 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3540 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3541 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3542 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3543 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3544 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3545 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3546 S_008F30_DISABLE_CUBE_WRAP(0) |
3547 S_008F30_COMPAT_MODE(is_vi));
3548 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3549 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3550 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3551 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3552 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3553 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3554 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3555 S_008F38_MIP_POINT_PRECLAMP(0) |
3556 S_008F38_DISABLE_LSB_CEIL(1) |
3557 S_008F38_FILTER_PREC_FIX(1) |
3558 S_008F38_ANISO_OVERRIDE(is_vi));
3559 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3560 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3561 }
3562
3563 VkResult radv_CreateSampler(
3564 VkDevice _device,
3565 const VkSamplerCreateInfo* pCreateInfo,
3566 const VkAllocationCallbacks* pAllocator,
3567 VkSampler* pSampler)
3568 {
3569 RADV_FROM_HANDLE(radv_device, device, _device);
3570 struct radv_sampler *sampler;
3571
3572 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3573
3574 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3575 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3576 if (!sampler)
3577 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3578
3579 radv_init_sampler(device, sampler, pCreateInfo);
3580 *pSampler = radv_sampler_to_handle(sampler);
3581
3582 return VK_SUCCESS;
3583 }
3584
3585 void radv_DestroySampler(
3586 VkDevice _device,
3587 VkSampler _sampler,
3588 const VkAllocationCallbacks* pAllocator)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3592
3593 if (!sampler)
3594 return;
3595 vk_free2(&device->alloc, pAllocator, sampler);
3596 }
3597
3598 /* vk_icd.h does not declare this function, so we declare it here to
3599 * suppress Wmissing-prototypes.
3600 */
3601 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3602 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3603
3604 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3605 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3606 {
3607 /* For the full details on loader interface versioning, see
3608 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3609 * What follows is a condensed summary, to help you navigate the large and
3610 * confusing official doc.
3611 *
3612 * - Loader interface v0 is incompatible with later versions. We don't
3613 * support it.
3614 *
3615 * - In loader interface v1:
3616 * - The first ICD entrypoint called by the loader is
3617 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3618 * entrypoint.
3619 * - The ICD must statically expose no other Vulkan symbol unless it is
3620 * linked with -Bsymbolic.
3621 * - Each dispatchable Vulkan handle created by the ICD must be
3622 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3623 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3624 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3625 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3626 * such loader-managed surfaces.
3627 *
3628 * - Loader interface v2 differs from v1 in:
3629 * - The first ICD entrypoint called by the loader is
3630 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3631 * statically expose this entrypoint.
3632 *
3633 * - Loader interface v3 differs from v2 in:
3634 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3635 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3636 * because the loader no longer does so.
3637 */
3638 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3639 return VK_SUCCESS;
3640 }
3641
3642 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3643 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3644 int *pFD)
3645 {
3646 RADV_FROM_HANDLE(radv_device, device, _device);
3647 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3648
3649 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3650
3651 /* We support only one handle type. */
3652 assert(pGetFdInfo->handleType ==
3653 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3654
3655 bool ret = radv_get_memory_fd(device, memory, pFD);
3656 if (ret == false)
3657 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3658 return VK_SUCCESS;
3659 }
3660
3661 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3662 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3663 int fd,
3664 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3665 {
3666 /* The valid usage section for this function says:
3667 *
3668 * "handleType must not be one of the handle types defined as opaque."
3669 *
3670 * Since we only handle opaque handles for now, there are no FD properties.
3671 */
3672 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3673 }
3674
3675 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3676 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3677 {
3678 RADV_FROM_HANDLE(radv_device, device, _device);
3679 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3680 uint32_t syncobj_handle = 0;
3681 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3682
3683 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3684 if (ret != 0)
3685 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3686
3687 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3688 sem->temp_syncobj = syncobj_handle;
3689 } else {
3690 sem->syncobj = syncobj_handle;
3691 }
3692 close(pImportSemaphoreFdInfo->fd);
3693 return VK_SUCCESS;
3694 }
3695
3696 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3697 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3698 int *pFd)
3699 {
3700 RADV_FROM_HANDLE(radv_device, device, _device);
3701 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3702 int ret;
3703 uint32_t syncobj_handle;
3704
3705 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3706 if (sem->temp_syncobj)
3707 syncobj_handle = sem->temp_syncobj;
3708 else
3709 syncobj_handle = sem->syncobj;
3710 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3711 if (ret)
3712 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3713 return VK_SUCCESS;
3714 }
3715
3716 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3717 VkPhysicalDevice physicalDevice,
3718 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3719 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3720 {
3721 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3722 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3723 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3724 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3725 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3726 } else {
3727 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3728 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3729 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3730 }
3731 }