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ac: rename has_syncobj_wait -> has_syncobj_wait_for_submit
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 radv_physical_device_init_mem_types(device);
267
268 result = radv_init_wsi(device);
269 if (result != VK_SUCCESS) {
270 device->ws->destroy(device->ws);
271 goto fail;
272 }
273
274 return VK_SUCCESS;
275
276 fail:
277 close(fd);
278 return result;
279 }
280
281 static void
282 radv_physical_device_finish(struct radv_physical_device *device)
283 {
284 radv_finish_wsi(device);
285 device->ws->destroy(device->ws);
286 disk_cache_destroy(device->disk_cache);
287 close(device->local_fd);
288 }
289
290 static void *
291 default_alloc_func(void *pUserData, size_t size, size_t align,
292 VkSystemAllocationScope allocationScope)
293 {
294 return malloc(size);
295 }
296
297 static void *
298 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
299 size_t align, VkSystemAllocationScope allocationScope)
300 {
301 return realloc(pOriginal, size);
302 }
303
304 static void
305 default_free_func(void *pUserData, void *pMemory)
306 {
307 free(pMemory);
308 }
309
310 static const VkAllocationCallbacks default_alloc = {
311 .pUserData = NULL,
312 .pfnAllocation = default_alloc_func,
313 .pfnReallocation = default_realloc_func,
314 .pfnFree = default_free_func,
315 };
316
317 static const struct debug_control radv_debug_options[] = {
318 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
319 {"nodcc", RADV_DEBUG_NO_DCC},
320 {"shaders", RADV_DEBUG_DUMP_SHADERS},
321 {"nocache", RADV_DEBUG_NO_CACHE},
322 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
323 {"nohiz", RADV_DEBUG_NO_HIZ},
324 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
325 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
326 {"allbos", RADV_DEBUG_ALL_BOS},
327 {"noibs", RADV_DEBUG_NO_IBS},
328 {"spirv", RADV_DEBUG_DUMP_SPIRV},
329 {"vmfaults", RADV_DEBUG_VM_FAULTS},
330 {"zerovram", RADV_DEBUG_ZERO_VRAM},
331 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
332 {"nosisched", RADV_DEBUG_NO_SISCHED},
333 {NULL, 0}
334 };
335
336 const char *
337 radv_get_debug_option_name(int id)
338 {
339 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
340 return radv_debug_options[id].string;
341 }
342
343 static const struct debug_control radv_perftest_options[] = {
344 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
345 {"sisched", RADV_PERFTEST_SISCHED},
346 {"localbos", RADV_PERFTEST_LOCAL_BOS},
347 {"binning", RADV_PERFTEST_BINNING},
348 {NULL, 0}
349 };
350
351 const char *
352 radv_get_perftest_option_name(int id)
353 {
354 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
355 return radv_perftest_options[id].string;
356 }
357
358 static void
359 radv_handle_per_app_options(struct radv_instance *instance,
360 const VkApplicationInfo *info)
361 {
362 const char *name = info ? info->pApplicationName : NULL;
363
364 if (!name)
365 return;
366
367 if (!strcmp(name, "Talos - Linux - 32bit") ||
368 !strcmp(name, "Talos - Linux - 64bit")) {
369 /* Force enable LLVM sisched for Talos because it looks safe
370 * and it gives few more FPS.
371 */
372 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
373 }
374 }
375
376 VkResult radv_CreateInstance(
377 const VkInstanceCreateInfo* pCreateInfo,
378 const VkAllocationCallbacks* pAllocator,
379 VkInstance* pInstance)
380 {
381 struct radv_instance *instance;
382
383 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
384
385 uint32_t client_version;
386 if (pCreateInfo->pApplicationInfo &&
387 pCreateInfo->pApplicationInfo->apiVersion != 0) {
388 client_version = pCreateInfo->pApplicationInfo->apiVersion;
389 } else {
390 client_version = VK_MAKE_VERSION(1, 0, 0);
391 }
392
393 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
394 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
395 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
396 "Client requested version %d.%d.%d",
397 VK_VERSION_MAJOR(client_version),
398 VK_VERSION_MINOR(client_version),
399 VK_VERSION_PATCH(client_version));
400 }
401
402 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
403 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
404 if (!radv_instance_extension_supported(ext_name))
405 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
406 }
407
408 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
409 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
410 if (!instance)
411 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
412
413 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
414
415 if (pAllocator)
416 instance->alloc = *pAllocator;
417 else
418 instance->alloc = default_alloc;
419
420 instance->apiVersion = client_version;
421 instance->physicalDeviceCount = -1;
422
423 _mesa_locale_init();
424
425 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
426
427 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
428 radv_debug_options);
429
430 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
431 radv_perftest_options);
432
433 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
434
435 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
436 /* Disable sisched when the user requests it, this is mostly
437 * useful when the driver force-enable sisched for the given
438 * application.
439 */
440 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
441 }
442
443 *pInstance = radv_instance_to_handle(instance);
444
445 return VK_SUCCESS;
446 }
447
448 void radv_DestroyInstance(
449 VkInstance _instance,
450 const VkAllocationCallbacks* pAllocator)
451 {
452 RADV_FROM_HANDLE(radv_instance, instance, _instance);
453
454 if (!instance)
455 return;
456
457 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
458 radv_physical_device_finish(instance->physicalDevices + i);
459 }
460
461 VG(VALGRIND_DESTROY_MEMPOOL(instance));
462
463 _mesa_locale_fini();
464
465 vk_free(&instance->alloc, instance);
466 }
467
468 static VkResult
469 radv_enumerate_devices(struct radv_instance *instance)
470 {
471 /* TODO: Check for more devices ? */
472 drmDevicePtr devices[8];
473 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
474 int max_devices;
475
476 instance->physicalDeviceCount = 0;
477
478 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
479 if (max_devices < 1)
480 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
481
482 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
483 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
484 devices[i]->bustype == DRM_BUS_PCI &&
485 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
486
487 result = radv_physical_device_init(instance->physicalDevices +
488 instance->physicalDeviceCount,
489 instance,
490 devices[i]);
491 if (result == VK_SUCCESS)
492 ++instance->physicalDeviceCount;
493 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
494 break;
495 }
496 }
497 drmFreeDevices(devices, max_devices);
498
499 return result;
500 }
501
502 VkResult radv_EnumeratePhysicalDevices(
503 VkInstance _instance,
504 uint32_t* pPhysicalDeviceCount,
505 VkPhysicalDevice* pPhysicalDevices)
506 {
507 RADV_FROM_HANDLE(radv_instance, instance, _instance);
508 VkResult result;
509
510 if (instance->physicalDeviceCount < 0) {
511 result = radv_enumerate_devices(instance);
512 if (result != VK_SUCCESS &&
513 result != VK_ERROR_INCOMPATIBLE_DRIVER)
514 return result;
515 }
516
517 if (!pPhysicalDevices) {
518 *pPhysicalDeviceCount = instance->physicalDeviceCount;
519 } else {
520 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
521 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
522 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
523 }
524
525 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
526 : VK_SUCCESS;
527 }
528
529 void radv_GetPhysicalDeviceFeatures(
530 VkPhysicalDevice physicalDevice,
531 VkPhysicalDeviceFeatures* pFeatures)
532 {
533 memset(pFeatures, 0, sizeof(*pFeatures));
534
535 *pFeatures = (VkPhysicalDeviceFeatures) {
536 .robustBufferAccess = true,
537 .fullDrawIndexUint32 = true,
538 .imageCubeArray = true,
539 .independentBlend = true,
540 .geometryShader = true,
541 .tessellationShader = true,
542 .sampleRateShading = true,
543 .dualSrcBlend = true,
544 .logicOp = true,
545 .multiDrawIndirect = true,
546 .drawIndirectFirstInstance = true,
547 .depthClamp = true,
548 .depthBiasClamp = true,
549 .fillModeNonSolid = true,
550 .depthBounds = true,
551 .wideLines = true,
552 .largePoints = true,
553 .alphaToOne = true,
554 .multiViewport = true,
555 .samplerAnisotropy = true,
556 .textureCompressionETC2 = false,
557 .textureCompressionASTC_LDR = false,
558 .textureCompressionBC = true,
559 .occlusionQueryPrecise = true,
560 .pipelineStatisticsQuery = true,
561 .vertexPipelineStoresAndAtomics = true,
562 .fragmentStoresAndAtomics = true,
563 .shaderTessellationAndGeometryPointSize = true,
564 .shaderImageGatherExtended = true,
565 .shaderStorageImageExtendedFormats = true,
566 .shaderStorageImageMultisample = false,
567 .shaderUniformBufferArrayDynamicIndexing = true,
568 .shaderSampledImageArrayDynamicIndexing = true,
569 .shaderStorageBufferArrayDynamicIndexing = true,
570 .shaderStorageImageArrayDynamicIndexing = true,
571 .shaderStorageImageReadWithoutFormat = true,
572 .shaderStorageImageWriteWithoutFormat = true,
573 .shaderClipDistance = true,
574 .shaderCullDistance = true,
575 .shaderFloat64 = true,
576 .shaderInt64 = true,
577 .shaderInt16 = false,
578 .sparseBinding = true,
579 .variableMultisampleRate = true,
580 .inheritedQueries = true,
581 };
582 }
583
584 void radv_GetPhysicalDeviceFeatures2KHR(
585 VkPhysicalDevice physicalDevice,
586 VkPhysicalDeviceFeatures2KHR *pFeatures)
587 {
588 vk_foreach_struct(ext, pFeatures->pNext) {
589 switch (ext->sType) {
590 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
591 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
592 features->variablePointersStorageBuffer = true;
593 features->variablePointers = false;
594 break;
595 }
596 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
597 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
598 features->multiview = true;
599 features->multiviewGeometryShader = true;
600 features->multiviewTessellationShader = true;
601 break;
602 }
603 default:
604 break;
605 }
606 }
607 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
608 }
609
610 void radv_GetPhysicalDeviceProperties(
611 VkPhysicalDevice physicalDevice,
612 VkPhysicalDeviceProperties* pProperties)
613 {
614 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
615 VkSampleCountFlags sample_counts = 0xf;
616
617 /* make sure that the entire descriptor set is addressable with a signed
618 * 32-bit int. So the sum of all limits scaled by descriptor size has to
619 * be at most 2 GiB. the combined image & samples object count as one of
620 * both. This limit is for the pipeline layout, not for the set layout, but
621 * there is no set limit, so we just set a pipeline limit. I don't think
622 * any app is going to hit this soon. */
623 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
624 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
625 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
626 32 /* sampler, largest when combined with image */ +
627 64 /* sampled image */ +
628 64 /* storage image */);
629
630 VkPhysicalDeviceLimits limits = {
631 .maxImageDimension1D = (1 << 14),
632 .maxImageDimension2D = (1 << 14),
633 .maxImageDimension3D = (1 << 11),
634 .maxImageDimensionCube = (1 << 14),
635 .maxImageArrayLayers = (1 << 11),
636 .maxTexelBufferElements = 128 * 1024 * 1024,
637 .maxUniformBufferRange = UINT32_MAX,
638 .maxStorageBufferRange = UINT32_MAX,
639 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
640 .maxMemoryAllocationCount = UINT32_MAX,
641 .maxSamplerAllocationCount = 64 * 1024,
642 .bufferImageGranularity = 64, /* A cache line */
643 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
644 .maxBoundDescriptorSets = MAX_SETS,
645 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
646 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
647 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
648 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
649 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
650 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
651 .maxPerStageResources = max_descriptor_set_size,
652 .maxDescriptorSetSamplers = max_descriptor_set_size,
653 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
654 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
655 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
656 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
657 .maxDescriptorSetSampledImages = max_descriptor_set_size,
658 .maxDescriptorSetStorageImages = max_descriptor_set_size,
659 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
660 .maxVertexInputAttributes = 32,
661 .maxVertexInputBindings = 32,
662 .maxVertexInputAttributeOffset = 2047,
663 .maxVertexInputBindingStride = 2048,
664 .maxVertexOutputComponents = 128,
665 .maxTessellationGenerationLevel = 64,
666 .maxTessellationPatchSize = 32,
667 .maxTessellationControlPerVertexInputComponents = 128,
668 .maxTessellationControlPerVertexOutputComponents = 128,
669 .maxTessellationControlPerPatchOutputComponents = 120,
670 .maxTessellationControlTotalOutputComponents = 4096,
671 .maxTessellationEvaluationInputComponents = 128,
672 .maxTessellationEvaluationOutputComponents = 128,
673 .maxGeometryShaderInvocations = 127,
674 .maxGeometryInputComponents = 64,
675 .maxGeometryOutputComponents = 128,
676 .maxGeometryOutputVertices = 256,
677 .maxGeometryTotalOutputComponents = 1024,
678 .maxFragmentInputComponents = 128,
679 .maxFragmentOutputAttachments = 8,
680 .maxFragmentDualSrcAttachments = 1,
681 .maxFragmentCombinedOutputResources = 8,
682 .maxComputeSharedMemorySize = 32768,
683 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
684 .maxComputeWorkGroupInvocations = 2048,
685 .maxComputeWorkGroupSize = {
686 2048,
687 2048,
688 2048
689 },
690 .subPixelPrecisionBits = 4 /* FIXME */,
691 .subTexelPrecisionBits = 4 /* FIXME */,
692 .mipmapPrecisionBits = 4 /* FIXME */,
693 .maxDrawIndexedIndexValue = UINT32_MAX,
694 .maxDrawIndirectCount = UINT32_MAX,
695 .maxSamplerLodBias = 16,
696 .maxSamplerAnisotropy = 16,
697 .maxViewports = MAX_VIEWPORTS,
698 .maxViewportDimensions = { (1 << 14), (1 << 14) },
699 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
700 .viewportSubPixelBits = 13, /* We take a float? */
701 .minMemoryMapAlignment = 4096, /* A page */
702 .minTexelBufferOffsetAlignment = 1,
703 .minUniformBufferOffsetAlignment = 4,
704 .minStorageBufferOffsetAlignment = 4,
705 .minTexelOffset = -32,
706 .maxTexelOffset = 31,
707 .minTexelGatherOffset = -32,
708 .maxTexelGatherOffset = 31,
709 .minInterpolationOffset = -2,
710 .maxInterpolationOffset = 2,
711 .subPixelInterpolationOffsetBits = 8,
712 .maxFramebufferWidth = (1 << 14),
713 .maxFramebufferHeight = (1 << 14),
714 .maxFramebufferLayers = (1 << 10),
715 .framebufferColorSampleCounts = sample_counts,
716 .framebufferDepthSampleCounts = sample_counts,
717 .framebufferStencilSampleCounts = sample_counts,
718 .framebufferNoAttachmentsSampleCounts = sample_counts,
719 .maxColorAttachments = MAX_RTS,
720 .sampledImageColorSampleCounts = sample_counts,
721 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
722 .sampledImageDepthSampleCounts = sample_counts,
723 .sampledImageStencilSampleCounts = sample_counts,
724 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
725 .maxSampleMaskWords = 1,
726 .timestampComputeAndGraphics = true,
727 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
728 .maxClipDistances = 8,
729 .maxCullDistances = 8,
730 .maxCombinedClipAndCullDistances = 8,
731 .discreteQueuePriorities = 1,
732 .pointSizeRange = { 0.125, 255.875 },
733 .lineWidthRange = { 0.0, 7.9921875 },
734 .pointSizeGranularity = (1.0 / 8.0),
735 .lineWidthGranularity = (1.0 / 128.0),
736 .strictLines = false, /* FINISHME */
737 .standardSampleLocations = true,
738 .optimalBufferCopyOffsetAlignment = 128,
739 .optimalBufferCopyRowPitchAlignment = 128,
740 .nonCoherentAtomSize = 64,
741 };
742
743 *pProperties = (VkPhysicalDeviceProperties) {
744 .apiVersion = radv_physical_device_api_version(pdevice),
745 .driverVersion = vk_get_driver_version(),
746 .vendorID = ATI_VENDOR_ID,
747 .deviceID = pdevice->rad_info.pci_id,
748 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
749 .limits = limits,
750 .sparseProperties = {0},
751 };
752
753 strcpy(pProperties->deviceName, pdevice->name);
754 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
755 }
756
757 void radv_GetPhysicalDeviceProperties2KHR(
758 VkPhysicalDevice physicalDevice,
759 VkPhysicalDeviceProperties2KHR *pProperties)
760 {
761 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
762 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
763
764 vk_foreach_struct(ext, pProperties->pNext) {
765 switch (ext->sType) {
766 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
767 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
768 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
769 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
770 break;
771 }
772 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
773 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
774 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
775 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
776 properties->deviceLUIDValid = false;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
780 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
781 properties->maxMultiviewViewCount = MAX_VIEWS;
782 properties->maxMultiviewInstanceIndex = INT_MAX;
783 break;
784 }
785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
786 VkPhysicalDevicePointClippingPropertiesKHR *properties =
787 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
788 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
789 break;
790 }
791 default:
792 break;
793 }
794 }
795 }
796
797 static void radv_get_physical_device_queue_family_properties(
798 struct radv_physical_device* pdevice,
799 uint32_t* pCount,
800 VkQueueFamilyProperties** pQueueFamilyProperties)
801 {
802 int num_queue_families = 1;
803 int idx;
804 if (pdevice->rad_info.num_compute_rings > 0 &&
805 pdevice->rad_info.chip_class >= CIK &&
806 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
807 num_queue_families++;
808
809 if (pQueueFamilyProperties == NULL) {
810 *pCount = num_queue_families;
811 return;
812 }
813
814 if (!*pCount)
815 return;
816
817 idx = 0;
818 if (*pCount >= 1) {
819 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
820 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
821 VK_QUEUE_COMPUTE_BIT |
822 VK_QUEUE_TRANSFER_BIT |
823 VK_QUEUE_SPARSE_BINDING_BIT,
824 .queueCount = 1,
825 .timestampValidBits = 64,
826 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
827 };
828 idx++;
829 }
830
831 if (pdevice->rad_info.num_compute_rings > 0 &&
832 pdevice->rad_info.chip_class >= CIK &&
833 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
834 if (*pCount > idx) {
835 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
836 .queueFlags = VK_QUEUE_COMPUTE_BIT |
837 VK_QUEUE_TRANSFER_BIT |
838 VK_QUEUE_SPARSE_BINDING_BIT,
839 .queueCount = pdevice->rad_info.num_compute_rings,
840 .timestampValidBits = 64,
841 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
842 };
843 idx++;
844 }
845 }
846 *pCount = idx;
847 }
848
849 void radv_GetPhysicalDeviceQueueFamilyProperties(
850 VkPhysicalDevice physicalDevice,
851 uint32_t* pCount,
852 VkQueueFamilyProperties* pQueueFamilyProperties)
853 {
854 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
855 if (!pQueueFamilyProperties) {
856 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
857 return;
858 }
859 VkQueueFamilyProperties *properties[] = {
860 pQueueFamilyProperties + 0,
861 pQueueFamilyProperties + 1,
862 pQueueFamilyProperties + 2,
863 };
864 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
865 assert(*pCount <= 3);
866 }
867
868 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
869 VkPhysicalDevice physicalDevice,
870 uint32_t* pCount,
871 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
872 {
873 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
874 if (!pQueueFamilyProperties) {
875 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
876 return;
877 }
878 VkQueueFamilyProperties *properties[] = {
879 &pQueueFamilyProperties[0].queueFamilyProperties,
880 &pQueueFamilyProperties[1].queueFamilyProperties,
881 &pQueueFamilyProperties[2].queueFamilyProperties,
882 };
883 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
884 assert(*pCount <= 3);
885 }
886
887 void radv_GetPhysicalDeviceMemoryProperties(
888 VkPhysicalDevice physicalDevice,
889 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
890 {
891 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
892
893 *pMemoryProperties = physical_device->memory_properties;
894 }
895
896 void radv_GetPhysicalDeviceMemoryProperties2KHR(
897 VkPhysicalDevice physicalDevice,
898 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
899 {
900 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
901 &pMemoryProperties->memoryProperties);
902 }
903
904 static enum radeon_ctx_priority
905 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
906 {
907 /* Default to MEDIUM when a specific global priority isn't requested */
908 if (!pObj)
909 return RADEON_CTX_PRIORITY_MEDIUM;
910
911 switch(pObj->globalPriority) {
912 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
913 return RADEON_CTX_PRIORITY_REALTIME;
914 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
915 return RADEON_CTX_PRIORITY_HIGH;
916 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
917 return RADEON_CTX_PRIORITY_MEDIUM;
918 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
919 return RADEON_CTX_PRIORITY_LOW;
920 default:
921 unreachable("Illegal global priority value");
922 return RADEON_CTX_PRIORITY_INVALID;
923 }
924 }
925
926 static int
927 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
928 uint32_t queue_family_index, int idx,
929 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
930 {
931 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
932 queue->device = device;
933 queue->queue_family_index = queue_family_index;
934 queue->queue_idx = idx;
935 queue->priority = radv_get_queue_global_priority(global_priority);
936
937 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
938 if (!queue->hw_ctx)
939 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
940
941 return VK_SUCCESS;
942 }
943
944 static void
945 radv_queue_finish(struct radv_queue *queue)
946 {
947 if (queue->hw_ctx)
948 queue->device->ws->ctx_destroy(queue->hw_ctx);
949
950 if (queue->initial_full_flush_preamble_cs)
951 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
952 if (queue->initial_preamble_cs)
953 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
954 if (queue->continue_preamble_cs)
955 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
956 if (queue->descriptor_bo)
957 queue->device->ws->buffer_destroy(queue->descriptor_bo);
958 if (queue->scratch_bo)
959 queue->device->ws->buffer_destroy(queue->scratch_bo);
960 if (queue->esgs_ring_bo)
961 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
962 if (queue->gsvs_ring_bo)
963 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
964 if (queue->tess_factor_ring_bo)
965 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
966 if (queue->tess_offchip_ring_bo)
967 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
968 if (queue->compute_scratch_bo)
969 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
970 }
971
972 static void
973 radv_device_init_gs_info(struct radv_device *device)
974 {
975 switch (device->physical_device->rad_info.family) {
976 case CHIP_OLAND:
977 case CHIP_HAINAN:
978 case CHIP_KAVERI:
979 case CHIP_KABINI:
980 case CHIP_MULLINS:
981 case CHIP_ICELAND:
982 case CHIP_CARRIZO:
983 case CHIP_STONEY:
984 device->gs_table_depth = 16;
985 return;
986 case CHIP_TAHITI:
987 case CHIP_PITCAIRN:
988 case CHIP_VERDE:
989 case CHIP_BONAIRE:
990 case CHIP_HAWAII:
991 case CHIP_TONGA:
992 case CHIP_FIJI:
993 case CHIP_POLARIS10:
994 case CHIP_POLARIS11:
995 case CHIP_POLARIS12:
996 case CHIP_VEGA10:
997 case CHIP_RAVEN:
998 device->gs_table_depth = 32;
999 return;
1000 default:
1001 unreachable("unknown GPU");
1002 }
1003 }
1004
1005 VkResult radv_CreateDevice(
1006 VkPhysicalDevice physicalDevice,
1007 const VkDeviceCreateInfo* pCreateInfo,
1008 const VkAllocationCallbacks* pAllocator,
1009 VkDevice* pDevice)
1010 {
1011 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1012 VkResult result;
1013 struct radv_device *device;
1014
1015 bool keep_shader_info = false;
1016
1017 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1018 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1019 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1020 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1021
1022 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1023 keep_shader_info = true;
1024 }
1025
1026 /* Check enabled features */
1027 if (pCreateInfo->pEnabledFeatures) {
1028 VkPhysicalDeviceFeatures supported_features;
1029 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1030 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1031 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1032 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1033 for (uint32_t i = 0; i < num_features; i++) {
1034 if (enabled_feature[i] && !supported_feature[i])
1035 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1036 }
1037 }
1038
1039 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1040 sizeof(*device), 8,
1041 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1042 if (!device)
1043 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1044
1045 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1046 device->instance = physical_device->instance;
1047 device->physical_device = physical_device;
1048
1049 device->ws = physical_device->ws;
1050 if (pAllocator)
1051 device->alloc = *pAllocator;
1052 else
1053 device->alloc = physical_device->instance->alloc;
1054
1055 mtx_init(&device->shader_slab_mutex, mtx_plain);
1056 list_inithead(&device->shader_slabs);
1057
1058 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1059 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1060 uint32_t qfi = queue_create->queueFamilyIndex;
1061 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1062 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1063
1064 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1065
1066 device->queues[qfi] = vk_alloc(&device->alloc,
1067 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1068 if (!device->queues[qfi]) {
1069 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1070 goto fail;
1071 }
1072
1073 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1074
1075 device->queue_count[qfi] = queue_create->queueCount;
1076
1077 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1078 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1079 if (result != VK_SUCCESS)
1080 goto fail;
1081 }
1082 }
1083
1084 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1085 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1086
1087 /* Disabled and not implemented for now. */
1088 device->dfsm_allowed = device->pbb_allowed && false;
1089
1090
1091 #if HAVE_LLVM < 0x0400
1092 device->llvm_supports_spill = false;
1093 #else
1094 device->llvm_supports_spill = true;
1095 #endif
1096
1097 /* The maximum number of scratch waves. Scratch space isn't divided
1098 * evenly between CUs. The number is only a function of the number of CUs.
1099 * We can decrease the constant to decrease the scratch buffer size.
1100 *
1101 * sctx->scratch_waves must be >= the maximum posible size of
1102 * 1 threadgroup, so that the hw doesn't hang from being unable
1103 * to start any.
1104 *
1105 * The recommended value is 4 per CU at most. Higher numbers don't
1106 * bring much benefit, but they still occupy chip resources (think
1107 * async compute). I've seen ~2% performance difference between 4 and 32.
1108 */
1109 uint32_t max_threads_per_block = 2048;
1110 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1111 max_threads_per_block / 64);
1112
1113 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1114 S_00B800_FORCE_START_AT_000(1);
1115
1116 if (device->physical_device->rad_info.chip_class >= CIK) {
1117 /* If the KMD allows it (there is a KMD hw register for it),
1118 * allow launching waves out-of-order.
1119 */
1120 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1121 }
1122
1123 radv_device_init_gs_info(device);
1124
1125 device->tess_offchip_block_dw_size =
1126 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1127 device->has_distributed_tess =
1128 device->physical_device->rad_info.chip_class >= VI &&
1129 device->physical_device->rad_info.max_se >= 2;
1130
1131 if (getenv("RADV_TRACE_FILE")) {
1132 keep_shader_info = true;
1133
1134 if (!radv_init_trace(device))
1135 goto fail;
1136 }
1137
1138 device->keep_shader_info = keep_shader_info;
1139
1140 result = radv_device_init_meta(device);
1141 if (result != VK_SUCCESS)
1142 goto fail;
1143
1144 radv_device_init_msaa(device);
1145
1146 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1147 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1148 switch (family) {
1149 case RADV_QUEUE_GENERAL:
1150 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1151 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1152 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1153 break;
1154 case RADV_QUEUE_COMPUTE:
1155 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1156 radeon_emit(device->empty_cs[family], 0);
1157 break;
1158 }
1159 device->ws->cs_finalize(device->empty_cs[family]);
1160 }
1161
1162 if (device->physical_device->rad_info.chip_class >= CIK)
1163 cik_create_gfx_config(device);
1164
1165 VkPipelineCacheCreateInfo ci;
1166 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1167 ci.pNext = NULL;
1168 ci.flags = 0;
1169 ci.pInitialData = NULL;
1170 ci.initialDataSize = 0;
1171 VkPipelineCache pc;
1172 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1173 &ci, NULL, &pc);
1174 if (result != VK_SUCCESS)
1175 goto fail;
1176
1177 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1178
1179 *pDevice = radv_device_to_handle(device);
1180 return VK_SUCCESS;
1181
1182 fail:
1183 if (device->trace_bo)
1184 device->ws->buffer_destroy(device->trace_bo);
1185
1186 if (device->gfx_init)
1187 device->ws->buffer_destroy(device->gfx_init);
1188
1189 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1190 for (unsigned q = 0; q < device->queue_count[i]; q++)
1191 radv_queue_finish(&device->queues[i][q]);
1192 if (device->queue_count[i])
1193 vk_free(&device->alloc, device->queues[i]);
1194 }
1195
1196 vk_free(&device->alloc, device);
1197 return result;
1198 }
1199
1200 void radv_DestroyDevice(
1201 VkDevice _device,
1202 const VkAllocationCallbacks* pAllocator)
1203 {
1204 RADV_FROM_HANDLE(radv_device, device, _device);
1205
1206 if (!device)
1207 return;
1208
1209 if (device->trace_bo)
1210 device->ws->buffer_destroy(device->trace_bo);
1211
1212 if (device->gfx_init)
1213 device->ws->buffer_destroy(device->gfx_init);
1214
1215 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1216 for (unsigned q = 0; q < device->queue_count[i]; q++)
1217 radv_queue_finish(&device->queues[i][q]);
1218 if (device->queue_count[i])
1219 vk_free(&device->alloc, device->queues[i]);
1220 if (device->empty_cs[i])
1221 device->ws->cs_destroy(device->empty_cs[i]);
1222 }
1223 radv_device_finish_meta(device);
1224
1225 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1226 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1227
1228 radv_destroy_shader_slabs(device);
1229
1230 vk_free(&device->alloc, device);
1231 }
1232
1233 VkResult radv_EnumerateInstanceLayerProperties(
1234 uint32_t* pPropertyCount,
1235 VkLayerProperties* pProperties)
1236 {
1237 if (pProperties == NULL) {
1238 *pPropertyCount = 0;
1239 return VK_SUCCESS;
1240 }
1241
1242 /* None supported at this time */
1243 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1244 }
1245
1246 VkResult radv_EnumerateDeviceLayerProperties(
1247 VkPhysicalDevice physicalDevice,
1248 uint32_t* pPropertyCount,
1249 VkLayerProperties* pProperties)
1250 {
1251 if (pProperties == NULL) {
1252 *pPropertyCount = 0;
1253 return VK_SUCCESS;
1254 }
1255
1256 /* None supported at this time */
1257 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1258 }
1259
1260 void radv_GetDeviceQueue(
1261 VkDevice _device,
1262 uint32_t queueFamilyIndex,
1263 uint32_t queueIndex,
1264 VkQueue* pQueue)
1265 {
1266 RADV_FROM_HANDLE(radv_device, device, _device);
1267
1268 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1269 }
1270
1271 static void
1272 fill_geom_tess_rings(struct radv_queue *queue,
1273 uint32_t *map,
1274 bool add_sample_positions,
1275 uint32_t esgs_ring_size,
1276 struct radeon_winsys_bo *esgs_ring_bo,
1277 uint32_t gsvs_ring_size,
1278 struct radeon_winsys_bo *gsvs_ring_bo,
1279 uint32_t tess_factor_ring_size,
1280 struct radeon_winsys_bo *tess_factor_ring_bo,
1281 uint32_t tess_offchip_ring_size,
1282 struct radeon_winsys_bo *tess_offchip_ring_bo)
1283 {
1284 uint64_t esgs_va = 0, gsvs_va = 0;
1285 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1286 uint32_t *desc = &map[4];
1287
1288 if (esgs_ring_bo)
1289 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1290 if (gsvs_ring_bo)
1291 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1292 if (tess_factor_ring_bo)
1293 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1294 if (tess_offchip_ring_bo)
1295 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1296
1297 /* stride 0, num records - size, add tid, swizzle, elsize4,
1298 index stride 64 */
1299 desc[0] = esgs_va;
1300 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1301 S_008F04_STRIDE(0) |
1302 S_008F04_SWIZZLE_ENABLE(true);
1303 desc[2] = esgs_ring_size;
1304 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1305 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1306 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1307 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1308 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1310 S_008F0C_ELEMENT_SIZE(1) |
1311 S_008F0C_INDEX_STRIDE(3) |
1312 S_008F0C_ADD_TID_ENABLE(true);
1313
1314 desc += 4;
1315 /* GS entry for ES->GS ring */
1316 /* stride 0, num records - size, elsize0,
1317 index stride 0 */
1318 desc[0] = esgs_va;
1319 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1320 S_008F04_STRIDE(0) |
1321 S_008F04_SWIZZLE_ENABLE(false);
1322 desc[2] = esgs_ring_size;
1323 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1324 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1325 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1326 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1327 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1328 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1329 S_008F0C_ELEMENT_SIZE(0) |
1330 S_008F0C_INDEX_STRIDE(0) |
1331 S_008F0C_ADD_TID_ENABLE(false);
1332
1333 desc += 4;
1334 /* VS entry for GS->VS ring */
1335 /* stride 0, num records - size, elsize0,
1336 index stride 0 */
1337 desc[0] = gsvs_va;
1338 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1339 S_008F04_STRIDE(0) |
1340 S_008F04_SWIZZLE_ENABLE(false);
1341 desc[2] = gsvs_ring_size;
1342 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1343 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1344 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1345 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1346 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1347 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1348 S_008F0C_ELEMENT_SIZE(0) |
1349 S_008F0C_INDEX_STRIDE(0) |
1350 S_008F0C_ADD_TID_ENABLE(false);
1351 desc += 4;
1352
1353 /* stride gsvs_itemsize, num records 64
1354 elsize 4, index stride 16 */
1355 /* shader will patch stride and desc[2] */
1356 desc[0] = gsvs_va;
1357 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1358 S_008F04_STRIDE(0) |
1359 S_008F04_SWIZZLE_ENABLE(true);
1360 desc[2] = 0;
1361 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1362 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1363 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1364 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1365 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1366 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1367 S_008F0C_ELEMENT_SIZE(1) |
1368 S_008F0C_INDEX_STRIDE(1) |
1369 S_008F0C_ADD_TID_ENABLE(true);
1370 desc += 4;
1371
1372 desc[0] = tess_factor_va;
1373 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1374 S_008F04_STRIDE(0) |
1375 S_008F04_SWIZZLE_ENABLE(false);
1376 desc[2] = tess_factor_ring_size;
1377 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1378 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1379 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1380 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1381 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1382 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1383 S_008F0C_ELEMENT_SIZE(0) |
1384 S_008F0C_INDEX_STRIDE(0) |
1385 S_008F0C_ADD_TID_ENABLE(false);
1386 desc += 4;
1387
1388 desc[0] = tess_offchip_va;
1389 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1390 S_008F04_STRIDE(0) |
1391 S_008F04_SWIZZLE_ENABLE(false);
1392 desc[2] = tess_offchip_ring_size;
1393 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1394 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1395 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1396 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1397 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1398 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1399 S_008F0C_ELEMENT_SIZE(0) |
1400 S_008F0C_INDEX_STRIDE(0) |
1401 S_008F0C_ADD_TID_ENABLE(false);
1402 desc += 4;
1403
1404 /* add sample positions after all rings */
1405 memcpy(desc, queue->device->sample_locations_1x, 8);
1406 desc += 2;
1407 memcpy(desc, queue->device->sample_locations_2x, 16);
1408 desc += 4;
1409 memcpy(desc, queue->device->sample_locations_4x, 32);
1410 desc += 8;
1411 memcpy(desc, queue->device->sample_locations_8x, 64);
1412 desc += 16;
1413 memcpy(desc, queue->device->sample_locations_16x, 128);
1414 }
1415
1416 static unsigned
1417 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1418 {
1419 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1420 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1421 device->physical_device->rad_info.family != CHIP_STONEY;
1422 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1423 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1424 device->physical_device->rad_info.max_se;
1425 unsigned offchip_granularity;
1426 unsigned hs_offchip_param;
1427 switch (device->tess_offchip_block_dw_size) {
1428 default:
1429 assert(0);
1430 /* fall through */
1431 case 8192:
1432 offchip_granularity = V_03093C_X_8K_DWORDS;
1433 break;
1434 case 4096:
1435 offchip_granularity = V_03093C_X_4K_DWORDS;
1436 break;
1437 }
1438
1439 switch (device->physical_device->rad_info.chip_class) {
1440 case SI:
1441 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1442 break;
1443 case CIK:
1444 case VI:
1445 case GFX9:
1446 default:
1447 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1448 break;
1449 }
1450
1451 *max_offchip_buffers_p = max_offchip_buffers;
1452 if (device->physical_device->rad_info.chip_class >= CIK) {
1453 if (device->physical_device->rad_info.chip_class >= VI)
1454 --max_offchip_buffers;
1455 hs_offchip_param =
1456 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1457 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1458 } else {
1459 hs_offchip_param =
1460 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1461 }
1462 return hs_offchip_param;
1463 }
1464
1465 static VkResult
1466 radv_get_preamble_cs(struct radv_queue *queue,
1467 uint32_t scratch_size,
1468 uint32_t compute_scratch_size,
1469 uint32_t esgs_ring_size,
1470 uint32_t gsvs_ring_size,
1471 bool needs_tess_rings,
1472 bool needs_sample_positions,
1473 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1474 struct radeon_winsys_cs **initial_preamble_cs,
1475 struct radeon_winsys_cs **continue_preamble_cs)
1476 {
1477 struct radeon_winsys_bo *scratch_bo = NULL;
1478 struct radeon_winsys_bo *descriptor_bo = NULL;
1479 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1480 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1481 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1482 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1483 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1484 struct radeon_winsys_cs *dest_cs[3] = {0};
1485 bool add_tess_rings = false, add_sample_positions = false;
1486 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1487 unsigned max_offchip_buffers;
1488 unsigned hs_offchip_param = 0;
1489 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1490 if (!queue->has_tess_rings) {
1491 if (needs_tess_rings)
1492 add_tess_rings = true;
1493 }
1494 if (!queue->has_sample_positions) {
1495 if (needs_sample_positions)
1496 add_sample_positions = true;
1497 }
1498 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1499 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1500 &max_offchip_buffers);
1501 tess_offchip_ring_size = max_offchip_buffers *
1502 queue->device->tess_offchip_block_dw_size * 4;
1503
1504 if (scratch_size <= queue->scratch_size &&
1505 compute_scratch_size <= queue->compute_scratch_size &&
1506 esgs_ring_size <= queue->esgs_ring_size &&
1507 gsvs_ring_size <= queue->gsvs_ring_size &&
1508 !add_tess_rings && !add_sample_positions &&
1509 queue->initial_preamble_cs) {
1510 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1511 *initial_preamble_cs = queue->initial_preamble_cs;
1512 *continue_preamble_cs = queue->continue_preamble_cs;
1513 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1514 *continue_preamble_cs = NULL;
1515 return VK_SUCCESS;
1516 }
1517
1518 if (scratch_size > queue->scratch_size) {
1519 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1520 scratch_size,
1521 4096,
1522 RADEON_DOMAIN_VRAM,
1523 ring_bo_flags);
1524 if (!scratch_bo)
1525 goto fail;
1526 } else
1527 scratch_bo = queue->scratch_bo;
1528
1529 if (compute_scratch_size > queue->compute_scratch_size) {
1530 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1531 compute_scratch_size,
1532 4096,
1533 RADEON_DOMAIN_VRAM,
1534 ring_bo_flags);
1535 if (!compute_scratch_bo)
1536 goto fail;
1537
1538 } else
1539 compute_scratch_bo = queue->compute_scratch_bo;
1540
1541 if (esgs_ring_size > queue->esgs_ring_size) {
1542 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1543 esgs_ring_size,
1544 4096,
1545 RADEON_DOMAIN_VRAM,
1546 ring_bo_flags);
1547 if (!esgs_ring_bo)
1548 goto fail;
1549 } else {
1550 esgs_ring_bo = queue->esgs_ring_bo;
1551 esgs_ring_size = queue->esgs_ring_size;
1552 }
1553
1554 if (gsvs_ring_size > queue->gsvs_ring_size) {
1555 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1556 gsvs_ring_size,
1557 4096,
1558 RADEON_DOMAIN_VRAM,
1559 ring_bo_flags);
1560 if (!gsvs_ring_bo)
1561 goto fail;
1562 } else {
1563 gsvs_ring_bo = queue->gsvs_ring_bo;
1564 gsvs_ring_size = queue->gsvs_ring_size;
1565 }
1566
1567 if (add_tess_rings) {
1568 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1569 tess_factor_ring_size,
1570 256,
1571 RADEON_DOMAIN_VRAM,
1572 ring_bo_flags);
1573 if (!tess_factor_ring_bo)
1574 goto fail;
1575 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1576 tess_offchip_ring_size,
1577 256,
1578 RADEON_DOMAIN_VRAM,
1579 ring_bo_flags);
1580 if (!tess_offchip_ring_bo)
1581 goto fail;
1582 } else {
1583 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1584 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1585 }
1586
1587 if (scratch_bo != queue->scratch_bo ||
1588 esgs_ring_bo != queue->esgs_ring_bo ||
1589 gsvs_ring_bo != queue->gsvs_ring_bo ||
1590 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1591 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1592 uint32_t size = 0;
1593 if (gsvs_ring_bo || esgs_ring_bo ||
1594 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1595 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1596 if (add_sample_positions)
1597 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1598 }
1599 else if (scratch_bo)
1600 size = 8; /* 2 dword */
1601
1602 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1603 size,
1604 4096,
1605 RADEON_DOMAIN_VRAM,
1606 RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
1607 if (!descriptor_bo)
1608 goto fail;
1609 } else
1610 descriptor_bo = queue->descriptor_bo;
1611
1612 for(int i = 0; i < 3; ++i) {
1613 struct radeon_winsys_cs *cs = NULL;
1614 cs = queue->device->ws->cs_create(queue->device->ws,
1615 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1616 if (!cs)
1617 goto fail;
1618
1619 dest_cs[i] = cs;
1620
1621 if (scratch_bo)
1622 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1623
1624 if (esgs_ring_bo)
1625 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1626
1627 if (gsvs_ring_bo)
1628 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1629
1630 if (tess_factor_ring_bo)
1631 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1632
1633 if (tess_offchip_ring_bo)
1634 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1635
1636 if (descriptor_bo)
1637 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1638
1639 if (descriptor_bo != queue->descriptor_bo) {
1640 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1641
1642 if (scratch_bo) {
1643 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1644 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1645 S_008F04_SWIZZLE_ENABLE(1);
1646 map[0] = scratch_va;
1647 map[1] = rsrc1;
1648 }
1649
1650 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1651 add_sample_positions)
1652 fill_geom_tess_rings(queue, map, add_sample_positions,
1653 esgs_ring_size, esgs_ring_bo,
1654 gsvs_ring_size, gsvs_ring_bo,
1655 tess_factor_ring_size, tess_factor_ring_bo,
1656 tess_offchip_ring_size, tess_offchip_ring_bo);
1657
1658 queue->device->ws->buffer_unmap(descriptor_bo);
1659 }
1660
1661 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1662 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1663 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1664 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1665 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1666 }
1667
1668 if (esgs_ring_bo || gsvs_ring_bo) {
1669 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1670 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1671 radeon_emit(cs, esgs_ring_size >> 8);
1672 radeon_emit(cs, gsvs_ring_size >> 8);
1673 } else {
1674 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1675 radeon_emit(cs, esgs_ring_size >> 8);
1676 radeon_emit(cs, gsvs_ring_size >> 8);
1677 }
1678 }
1679
1680 if (tess_factor_ring_bo) {
1681 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1682 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1683 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1684 S_030938_SIZE(tess_factor_ring_size / 4));
1685 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1686 tf_va >> 8);
1687 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1688 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1689 tf_va >> 40);
1690 }
1691 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1692 } else {
1693 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1694 S_008988_SIZE(tess_factor_ring_size / 4));
1695 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1696 tf_va >> 8);
1697 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1698 hs_offchip_param);
1699 }
1700 }
1701
1702 if (descriptor_bo) {
1703 uint64_t va = radv_buffer_get_va(descriptor_bo);
1704 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1705 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1706 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1707 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1708 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1709
1710 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1711 radeon_set_sh_reg_seq(cs, regs[i], 2);
1712 radeon_emit(cs, va);
1713 radeon_emit(cs, va >> 32);
1714 }
1715 } else {
1716 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1717 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1718 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1719 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1720 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1721 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1722
1723 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1724 radeon_set_sh_reg_seq(cs, regs[i], 2);
1725 radeon_emit(cs, va);
1726 radeon_emit(cs, va >> 32);
1727 }
1728 }
1729 }
1730
1731 if (compute_scratch_bo) {
1732 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1733 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1734 S_008F04_SWIZZLE_ENABLE(1);
1735
1736 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1737
1738 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1739 radeon_emit(cs, scratch_va);
1740 radeon_emit(cs, rsrc1);
1741 }
1742
1743 if (i == 0) {
1744 si_cs_emit_cache_flush(cs,
1745 false,
1746 queue->device->physical_device->rad_info.chip_class,
1747 NULL, 0,
1748 queue->queue_family_index == RING_COMPUTE &&
1749 queue->device->physical_device->rad_info.chip_class >= CIK,
1750 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1751 RADV_CMD_FLAG_INV_ICACHE |
1752 RADV_CMD_FLAG_INV_SMEM_L1 |
1753 RADV_CMD_FLAG_INV_VMEM_L1 |
1754 RADV_CMD_FLAG_INV_GLOBAL_L2);
1755 } else if (i == 1) {
1756 si_cs_emit_cache_flush(cs,
1757 false,
1758 queue->device->physical_device->rad_info.chip_class,
1759 NULL, 0,
1760 queue->queue_family_index == RING_COMPUTE &&
1761 queue->device->physical_device->rad_info.chip_class >= CIK,
1762 RADV_CMD_FLAG_INV_ICACHE |
1763 RADV_CMD_FLAG_INV_SMEM_L1 |
1764 RADV_CMD_FLAG_INV_VMEM_L1 |
1765 RADV_CMD_FLAG_INV_GLOBAL_L2);
1766 }
1767
1768 if (!queue->device->ws->cs_finalize(cs))
1769 goto fail;
1770 }
1771
1772 if (queue->initial_full_flush_preamble_cs)
1773 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1774
1775 if (queue->initial_preamble_cs)
1776 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1777
1778 if (queue->continue_preamble_cs)
1779 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1780
1781 queue->initial_full_flush_preamble_cs = dest_cs[0];
1782 queue->initial_preamble_cs = dest_cs[1];
1783 queue->continue_preamble_cs = dest_cs[2];
1784
1785 if (scratch_bo != queue->scratch_bo) {
1786 if (queue->scratch_bo)
1787 queue->device->ws->buffer_destroy(queue->scratch_bo);
1788 queue->scratch_bo = scratch_bo;
1789 queue->scratch_size = scratch_size;
1790 }
1791
1792 if (compute_scratch_bo != queue->compute_scratch_bo) {
1793 if (queue->compute_scratch_bo)
1794 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1795 queue->compute_scratch_bo = compute_scratch_bo;
1796 queue->compute_scratch_size = compute_scratch_size;
1797 }
1798
1799 if (esgs_ring_bo != queue->esgs_ring_bo) {
1800 if (queue->esgs_ring_bo)
1801 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1802 queue->esgs_ring_bo = esgs_ring_bo;
1803 queue->esgs_ring_size = esgs_ring_size;
1804 }
1805
1806 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1807 if (queue->gsvs_ring_bo)
1808 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1809 queue->gsvs_ring_bo = gsvs_ring_bo;
1810 queue->gsvs_ring_size = gsvs_ring_size;
1811 }
1812
1813 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1814 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1815 }
1816
1817 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1818 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1819 queue->has_tess_rings = true;
1820 }
1821
1822 if (descriptor_bo != queue->descriptor_bo) {
1823 if (queue->descriptor_bo)
1824 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1825
1826 queue->descriptor_bo = descriptor_bo;
1827 }
1828
1829 if (add_sample_positions)
1830 queue->has_sample_positions = true;
1831
1832 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1833 *initial_preamble_cs = queue->initial_preamble_cs;
1834 *continue_preamble_cs = queue->continue_preamble_cs;
1835 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1836 *continue_preamble_cs = NULL;
1837 return VK_SUCCESS;
1838 fail:
1839 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1840 if (dest_cs[i])
1841 queue->device->ws->cs_destroy(dest_cs[i]);
1842 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1843 queue->device->ws->buffer_destroy(descriptor_bo);
1844 if (scratch_bo && scratch_bo != queue->scratch_bo)
1845 queue->device->ws->buffer_destroy(scratch_bo);
1846 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1847 queue->device->ws->buffer_destroy(compute_scratch_bo);
1848 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1849 queue->device->ws->buffer_destroy(esgs_ring_bo);
1850 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1851 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1852 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1853 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1854 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1855 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1856 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1857 }
1858
1859 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1860 int num_sems,
1861 const VkSemaphore *sems,
1862 VkFence _fence,
1863 bool reset_temp)
1864 {
1865 int syncobj_idx = 0, sem_idx = 0;
1866
1867 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
1868 return VK_SUCCESS;
1869
1870 for (uint32_t i = 0; i < num_sems; i++) {
1871 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1872
1873 if (sem->temp_syncobj || sem->syncobj)
1874 counts->syncobj_count++;
1875 else
1876 counts->sem_count++;
1877 }
1878
1879 if (_fence != VK_NULL_HANDLE) {
1880 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1881 if (fence->temp_syncobj || fence->syncobj)
1882 counts->syncobj_count++;
1883 }
1884
1885 if (counts->syncobj_count) {
1886 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1887 if (!counts->syncobj)
1888 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1889 }
1890
1891 if (counts->sem_count) {
1892 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1893 if (!counts->sem) {
1894 free(counts->syncobj);
1895 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1896 }
1897 }
1898
1899 for (uint32_t i = 0; i < num_sems; i++) {
1900 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1901
1902 if (sem->temp_syncobj) {
1903 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1904 }
1905 else if (sem->syncobj)
1906 counts->syncobj[syncobj_idx++] = sem->syncobj;
1907 else {
1908 assert(sem->sem);
1909 counts->sem[sem_idx++] = sem->sem;
1910 }
1911 }
1912
1913 if (_fence != VK_NULL_HANDLE) {
1914 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1915 if (fence->temp_syncobj)
1916 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
1917 else if (fence->syncobj)
1918 counts->syncobj[syncobj_idx++] = fence->syncobj;
1919 }
1920
1921 return VK_SUCCESS;
1922 }
1923
1924 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1925 {
1926 free(sem_info->wait.syncobj);
1927 free(sem_info->wait.sem);
1928 free(sem_info->signal.syncobj);
1929 free(sem_info->signal.sem);
1930 }
1931
1932
1933 static void radv_free_temp_syncobjs(struct radv_device *device,
1934 int num_sems,
1935 const VkSemaphore *sems)
1936 {
1937 for (uint32_t i = 0; i < num_sems; i++) {
1938 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1939
1940 if (sem->temp_syncobj) {
1941 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1942 sem->temp_syncobj = 0;
1943 }
1944 }
1945 }
1946
1947 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1948 int num_wait_sems,
1949 const VkSemaphore *wait_sems,
1950 int num_signal_sems,
1951 const VkSemaphore *signal_sems,
1952 VkFence fence)
1953 {
1954 VkResult ret;
1955 memset(sem_info, 0, sizeof(*sem_info));
1956
1957 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
1958 if (ret)
1959 return ret;
1960 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
1961 if (ret)
1962 radv_free_sem_info(sem_info);
1963
1964 /* caller can override these */
1965 sem_info->cs_emit_wait = true;
1966 sem_info->cs_emit_signal = true;
1967 return ret;
1968 }
1969
1970 VkResult radv_QueueSubmit(
1971 VkQueue _queue,
1972 uint32_t submitCount,
1973 const VkSubmitInfo* pSubmits,
1974 VkFence _fence)
1975 {
1976 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1977 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1978 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1979 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1980 int ret;
1981 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1982 uint32_t scratch_size = 0;
1983 uint32_t compute_scratch_size = 0;
1984 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1985 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1986 VkResult result;
1987 bool fence_emitted = false;
1988 bool tess_rings_needed = false;
1989 bool sample_positions_needed = false;
1990
1991 /* Do this first so failing to allocate scratch buffers can't result in
1992 * partially executed submissions. */
1993 for (uint32_t i = 0; i < submitCount; i++) {
1994 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1995 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1996 pSubmits[i].pCommandBuffers[j]);
1997
1998 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1999 compute_scratch_size = MAX2(compute_scratch_size,
2000 cmd_buffer->compute_scratch_size_needed);
2001 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2002 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2003 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2004 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2005 }
2006 }
2007
2008 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2009 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2010 sample_positions_needed, &initial_flush_preamble_cs,
2011 &initial_preamble_cs, &continue_preamble_cs);
2012 if (result != VK_SUCCESS)
2013 return result;
2014
2015 for (uint32_t i = 0; i < submitCount; i++) {
2016 struct radeon_winsys_cs **cs_array;
2017 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2018 bool can_patch = true;
2019 uint32_t advance;
2020 struct radv_winsys_sem_info sem_info;
2021
2022 result = radv_alloc_sem_info(&sem_info,
2023 pSubmits[i].waitSemaphoreCount,
2024 pSubmits[i].pWaitSemaphores,
2025 pSubmits[i].signalSemaphoreCount,
2026 pSubmits[i].pSignalSemaphores,
2027 _fence);
2028 if (result != VK_SUCCESS)
2029 return result;
2030
2031 if (!pSubmits[i].commandBufferCount) {
2032 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2033 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2034 &queue->device->empty_cs[queue->queue_family_index],
2035 1, NULL, NULL,
2036 &sem_info,
2037 false, base_fence);
2038 if (ret) {
2039 radv_loge("failed to submit CS %d\n", i);
2040 abort();
2041 }
2042 fence_emitted = true;
2043 }
2044 radv_free_sem_info(&sem_info);
2045 continue;
2046 }
2047
2048 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2049 (pSubmits[i].commandBufferCount));
2050
2051 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2052 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2053 pSubmits[i].pCommandBuffers[j]);
2054 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2055
2056 cs_array[j] = cmd_buffer->cs;
2057 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2058 can_patch = false;
2059
2060 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2061 }
2062
2063 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2064 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2065 advance = MIN2(max_cs_submission,
2066 pSubmits[i].commandBufferCount - j);
2067
2068 if (queue->device->trace_bo)
2069 *queue->device->trace_id_ptr = 0;
2070
2071 sem_info.cs_emit_wait = j == 0;
2072 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2073
2074 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2075 advance, initial_preamble, continue_preamble_cs,
2076 &sem_info,
2077 can_patch, base_fence);
2078
2079 if (ret) {
2080 radv_loge("failed to submit CS %d\n", i);
2081 abort();
2082 }
2083 fence_emitted = true;
2084 if (queue->device->trace_bo) {
2085 radv_check_gpu_hangs(queue, cs_array[j]);
2086 }
2087 }
2088
2089 radv_free_temp_syncobjs(queue->device,
2090 pSubmits[i].waitSemaphoreCount,
2091 pSubmits[i].pWaitSemaphores);
2092 radv_free_sem_info(&sem_info);
2093 free(cs_array);
2094 }
2095
2096 if (fence) {
2097 if (!fence_emitted) {
2098 struct radv_winsys_sem_info sem_info;
2099
2100 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2101 _fence);
2102 if (result != VK_SUCCESS)
2103 return result;
2104
2105 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2106 &queue->device->empty_cs[queue->queue_family_index],
2107 1, NULL, NULL, &sem_info,
2108 false, base_fence);
2109 radv_free_sem_info(&sem_info);
2110 }
2111 fence->submitted = true;
2112 }
2113
2114 return VK_SUCCESS;
2115 }
2116
2117 VkResult radv_QueueWaitIdle(
2118 VkQueue _queue)
2119 {
2120 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2121
2122 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2123 radv_queue_family_to_ring(queue->queue_family_index),
2124 queue->queue_idx);
2125 return VK_SUCCESS;
2126 }
2127
2128 VkResult radv_DeviceWaitIdle(
2129 VkDevice _device)
2130 {
2131 RADV_FROM_HANDLE(radv_device, device, _device);
2132
2133 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2134 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2135 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2136 }
2137 }
2138 return VK_SUCCESS;
2139 }
2140
2141 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2142 VkInstance instance,
2143 const char* pName)
2144 {
2145 return radv_lookup_entrypoint(pName);
2146 }
2147
2148 /* The loader wants us to expose a second GetInstanceProcAddr function
2149 * to work around certain LD_PRELOAD issues seen in apps.
2150 */
2151 PUBLIC
2152 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2153 VkInstance instance,
2154 const char* pName);
2155
2156 PUBLIC
2157 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2158 VkInstance instance,
2159 const char* pName)
2160 {
2161 return radv_GetInstanceProcAddr(instance, pName);
2162 }
2163
2164 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2165 VkDevice device,
2166 const char* pName)
2167 {
2168 return radv_lookup_entrypoint(pName);
2169 }
2170
2171 bool radv_get_memory_fd(struct radv_device *device,
2172 struct radv_device_memory *memory,
2173 int *pFD)
2174 {
2175 struct radeon_bo_metadata metadata;
2176
2177 if (memory->image) {
2178 radv_init_metadata(device, memory->image, &metadata);
2179 device->ws->buffer_set_metadata(memory->bo, &metadata);
2180 }
2181
2182 return device->ws->buffer_get_fd(device->ws, memory->bo,
2183 pFD);
2184 }
2185
2186 static VkResult radv_alloc_memory(struct radv_device *device,
2187 const VkMemoryAllocateInfo* pAllocateInfo,
2188 const VkAllocationCallbacks* pAllocator,
2189 VkDeviceMemory* pMem)
2190 {
2191 struct radv_device_memory *mem;
2192 VkResult result;
2193 enum radeon_bo_domain domain;
2194 uint32_t flags = 0;
2195 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2196
2197 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2198
2199 if (pAllocateInfo->allocationSize == 0) {
2200 /* Apparently, this is allowed */
2201 *pMem = VK_NULL_HANDLE;
2202 return VK_SUCCESS;
2203 }
2204
2205 const VkImportMemoryFdInfoKHR *import_info =
2206 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2207 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2208 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2209 const VkExportMemoryAllocateInfoKHR *export_info =
2210 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2211
2212 const struct wsi_memory_allocate_info *wsi_info =
2213 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2214
2215 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2216 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2217 if (mem == NULL)
2218 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2219
2220 if (wsi_info && wsi_info->implicit_sync)
2221 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2222
2223 if (dedicate_info) {
2224 mem->image = radv_image_from_handle(dedicate_info->image);
2225 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2226 } else {
2227 mem->image = NULL;
2228 mem->buffer = NULL;
2229 }
2230
2231 if (import_info) {
2232 assert(import_info->handleType ==
2233 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2234 import_info->handleType ==
2235 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2236 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2237 NULL, NULL);
2238 if (!mem->bo) {
2239 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2240 goto fail;
2241 } else {
2242 close(import_info->fd);
2243 goto out_success;
2244 }
2245 }
2246
2247 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2248 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2249 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2250 domain = RADEON_DOMAIN_GTT;
2251 else
2252 domain = RADEON_DOMAIN_VRAM;
2253
2254 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2255 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2256 else
2257 flags |= RADEON_FLAG_CPU_ACCESS;
2258
2259 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2260 flags |= RADEON_FLAG_GTT_WC;
2261
2262 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2263 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2264
2265 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2266 domain, flags);
2267
2268 if (!mem->bo) {
2269 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2270 goto fail;
2271 }
2272 mem->type_index = mem_type_index;
2273 out_success:
2274 *pMem = radv_device_memory_to_handle(mem);
2275
2276 return VK_SUCCESS;
2277
2278 fail:
2279 vk_free2(&device->alloc, pAllocator, mem);
2280
2281 return result;
2282 }
2283
2284 VkResult radv_AllocateMemory(
2285 VkDevice _device,
2286 const VkMemoryAllocateInfo* pAllocateInfo,
2287 const VkAllocationCallbacks* pAllocator,
2288 VkDeviceMemory* pMem)
2289 {
2290 RADV_FROM_HANDLE(radv_device, device, _device);
2291 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2292 }
2293
2294 void radv_FreeMemory(
2295 VkDevice _device,
2296 VkDeviceMemory _mem,
2297 const VkAllocationCallbacks* pAllocator)
2298 {
2299 RADV_FROM_HANDLE(radv_device, device, _device);
2300 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2301
2302 if (mem == NULL)
2303 return;
2304
2305 device->ws->buffer_destroy(mem->bo);
2306 mem->bo = NULL;
2307
2308 vk_free2(&device->alloc, pAllocator, mem);
2309 }
2310
2311 VkResult radv_MapMemory(
2312 VkDevice _device,
2313 VkDeviceMemory _memory,
2314 VkDeviceSize offset,
2315 VkDeviceSize size,
2316 VkMemoryMapFlags flags,
2317 void** ppData)
2318 {
2319 RADV_FROM_HANDLE(radv_device, device, _device);
2320 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2321
2322 if (mem == NULL) {
2323 *ppData = NULL;
2324 return VK_SUCCESS;
2325 }
2326
2327 *ppData = device->ws->buffer_map(mem->bo);
2328 if (*ppData) {
2329 *ppData += offset;
2330 return VK_SUCCESS;
2331 }
2332
2333 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2334 }
2335
2336 void radv_UnmapMemory(
2337 VkDevice _device,
2338 VkDeviceMemory _memory)
2339 {
2340 RADV_FROM_HANDLE(radv_device, device, _device);
2341 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2342
2343 if (mem == NULL)
2344 return;
2345
2346 device->ws->buffer_unmap(mem->bo);
2347 }
2348
2349 VkResult radv_FlushMappedMemoryRanges(
2350 VkDevice _device,
2351 uint32_t memoryRangeCount,
2352 const VkMappedMemoryRange* pMemoryRanges)
2353 {
2354 return VK_SUCCESS;
2355 }
2356
2357 VkResult radv_InvalidateMappedMemoryRanges(
2358 VkDevice _device,
2359 uint32_t memoryRangeCount,
2360 const VkMappedMemoryRange* pMemoryRanges)
2361 {
2362 return VK_SUCCESS;
2363 }
2364
2365 void radv_GetBufferMemoryRequirements(
2366 VkDevice _device,
2367 VkBuffer _buffer,
2368 VkMemoryRequirements* pMemoryRequirements)
2369 {
2370 RADV_FROM_HANDLE(radv_device, device, _device);
2371 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2372
2373 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2374
2375 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2376 pMemoryRequirements->alignment = 4096;
2377 else
2378 pMemoryRequirements->alignment = 16;
2379
2380 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2381 }
2382
2383 void radv_GetBufferMemoryRequirements2KHR(
2384 VkDevice device,
2385 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2386 VkMemoryRequirements2KHR* pMemoryRequirements)
2387 {
2388 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2389 &pMemoryRequirements->memoryRequirements);
2390 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2391 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2392 switch (ext->sType) {
2393 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2394 VkMemoryDedicatedRequirementsKHR *req =
2395 (VkMemoryDedicatedRequirementsKHR *) ext;
2396 req->requiresDedicatedAllocation = buffer->shareable;
2397 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2398 break;
2399 }
2400 default:
2401 break;
2402 }
2403 }
2404 }
2405
2406 void radv_GetImageMemoryRequirements(
2407 VkDevice _device,
2408 VkImage _image,
2409 VkMemoryRequirements* pMemoryRequirements)
2410 {
2411 RADV_FROM_HANDLE(radv_device, device, _device);
2412 RADV_FROM_HANDLE(radv_image, image, _image);
2413
2414 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2415
2416 pMemoryRequirements->size = image->size;
2417 pMemoryRequirements->alignment = image->alignment;
2418 }
2419
2420 void radv_GetImageMemoryRequirements2KHR(
2421 VkDevice device,
2422 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2423 VkMemoryRequirements2KHR* pMemoryRequirements)
2424 {
2425 radv_GetImageMemoryRequirements(device, pInfo->image,
2426 &pMemoryRequirements->memoryRequirements);
2427
2428 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2429
2430 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2431 switch (ext->sType) {
2432 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2433 VkMemoryDedicatedRequirementsKHR *req =
2434 (VkMemoryDedicatedRequirementsKHR *) ext;
2435 req->requiresDedicatedAllocation = image->shareable;
2436 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2437 break;
2438 }
2439 default:
2440 break;
2441 }
2442 }
2443 }
2444
2445 void radv_GetImageSparseMemoryRequirements(
2446 VkDevice device,
2447 VkImage image,
2448 uint32_t* pSparseMemoryRequirementCount,
2449 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2450 {
2451 stub();
2452 }
2453
2454 void radv_GetImageSparseMemoryRequirements2KHR(
2455 VkDevice device,
2456 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2457 uint32_t* pSparseMemoryRequirementCount,
2458 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2459 {
2460 stub();
2461 }
2462
2463 void radv_GetDeviceMemoryCommitment(
2464 VkDevice device,
2465 VkDeviceMemory memory,
2466 VkDeviceSize* pCommittedMemoryInBytes)
2467 {
2468 *pCommittedMemoryInBytes = 0;
2469 }
2470
2471 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2472 uint32_t bindInfoCount,
2473 const VkBindBufferMemoryInfoKHR *pBindInfos)
2474 {
2475 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2476 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2477 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2478
2479 if (mem) {
2480 buffer->bo = mem->bo;
2481 buffer->offset = pBindInfos[i].memoryOffset;
2482 } else {
2483 buffer->bo = NULL;
2484 }
2485 }
2486 return VK_SUCCESS;
2487 }
2488
2489 VkResult radv_BindBufferMemory(
2490 VkDevice device,
2491 VkBuffer buffer,
2492 VkDeviceMemory memory,
2493 VkDeviceSize memoryOffset)
2494 {
2495 const VkBindBufferMemoryInfoKHR info = {
2496 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2497 .buffer = buffer,
2498 .memory = memory,
2499 .memoryOffset = memoryOffset
2500 };
2501
2502 return radv_BindBufferMemory2KHR(device, 1, &info);
2503 }
2504
2505 VkResult radv_BindImageMemory2KHR(VkDevice device,
2506 uint32_t bindInfoCount,
2507 const VkBindImageMemoryInfoKHR *pBindInfos)
2508 {
2509 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2510 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2511 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2512
2513 if (mem) {
2514 image->bo = mem->bo;
2515 image->offset = pBindInfos[i].memoryOffset;
2516 } else {
2517 image->bo = NULL;
2518 image->offset = 0;
2519 }
2520 }
2521 return VK_SUCCESS;
2522 }
2523
2524
2525 VkResult radv_BindImageMemory(
2526 VkDevice device,
2527 VkImage image,
2528 VkDeviceMemory memory,
2529 VkDeviceSize memoryOffset)
2530 {
2531 const VkBindImageMemoryInfoKHR info = {
2532 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2533 .image = image,
2534 .memory = memory,
2535 .memoryOffset = memoryOffset
2536 };
2537
2538 return radv_BindImageMemory2KHR(device, 1, &info);
2539 }
2540
2541
2542 static void
2543 radv_sparse_buffer_bind_memory(struct radv_device *device,
2544 const VkSparseBufferMemoryBindInfo *bind)
2545 {
2546 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2547
2548 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2549 struct radv_device_memory *mem = NULL;
2550
2551 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2552 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2553
2554 device->ws->buffer_virtual_bind(buffer->bo,
2555 bind->pBinds[i].resourceOffset,
2556 bind->pBinds[i].size,
2557 mem ? mem->bo : NULL,
2558 bind->pBinds[i].memoryOffset);
2559 }
2560 }
2561
2562 static void
2563 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2564 const VkSparseImageOpaqueMemoryBindInfo *bind)
2565 {
2566 RADV_FROM_HANDLE(radv_image, image, bind->image);
2567
2568 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2569 struct radv_device_memory *mem = NULL;
2570
2571 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2572 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2573
2574 device->ws->buffer_virtual_bind(image->bo,
2575 bind->pBinds[i].resourceOffset,
2576 bind->pBinds[i].size,
2577 mem ? mem->bo : NULL,
2578 bind->pBinds[i].memoryOffset);
2579 }
2580 }
2581
2582 VkResult radv_QueueBindSparse(
2583 VkQueue _queue,
2584 uint32_t bindInfoCount,
2585 const VkBindSparseInfo* pBindInfo,
2586 VkFence _fence)
2587 {
2588 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2589 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2590 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2591 bool fence_emitted = false;
2592
2593 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2594 struct radv_winsys_sem_info sem_info;
2595 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2596 radv_sparse_buffer_bind_memory(queue->device,
2597 pBindInfo[i].pBufferBinds + j);
2598 }
2599
2600 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2601 radv_sparse_image_opaque_bind_memory(queue->device,
2602 pBindInfo[i].pImageOpaqueBinds + j);
2603 }
2604
2605 VkResult result;
2606 result = radv_alloc_sem_info(&sem_info,
2607 pBindInfo[i].waitSemaphoreCount,
2608 pBindInfo[i].pWaitSemaphores,
2609 pBindInfo[i].signalSemaphoreCount,
2610 pBindInfo[i].pSignalSemaphores,
2611 _fence);
2612 if (result != VK_SUCCESS)
2613 return result;
2614
2615 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2616 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2617 &queue->device->empty_cs[queue->queue_family_index],
2618 1, NULL, NULL,
2619 &sem_info,
2620 false, base_fence);
2621 fence_emitted = true;
2622 if (fence)
2623 fence->submitted = true;
2624 }
2625
2626 radv_free_sem_info(&sem_info);
2627
2628 }
2629
2630 if (fence && !fence_emitted) {
2631 fence->signalled = true;
2632 }
2633
2634 return VK_SUCCESS;
2635 }
2636
2637 VkResult radv_CreateFence(
2638 VkDevice _device,
2639 const VkFenceCreateInfo* pCreateInfo,
2640 const VkAllocationCallbacks* pAllocator,
2641 VkFence* pFence)
2642 {
2643 RADV_FROM_HANDLE(radv_device, device, _device);
2644 const VkExportFenceCreateInfoKHR *export =
2645 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
2646 VkExternalFenceHandleTypeFlagsKHR handleTypes =
2647 export ? export->handleTypes : 0;
2648
2649 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2650 sizeof(*fence), 8,
2651 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2652
2653 if (!fence)
2654 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2655
2656 fence->submitted = false;
2657 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2658 fence->temp_syncobj = 0;
2659 if (handleTypes) {
2660 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
2661 if (ret) {
2662 vk_free2(&device->alloc, pAllocator, fence);
2663 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2664 }
2665 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
2666 device->ws->signal_syncobj(device->ws, fence->syncobj);
2667 }
2668 fence->fence = NULL;
2669 } else {
2670 fence->fence = device->ws->create_fence();
2671 if (!fence->fence) {
2672 vk_free2(&device->alloc, pAllocator, fence);
2673 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2674 }
2675 fence->syncobj = 0;
2676 }
2677
2678 *pFence = radv_fence_to_handle(fence);
2679
2680 return VK_SUCCESS;
2681 }
2682
2683 void radv_DestroyFence(
2684 VkDevice _device,
2685 VkFence _fence,
2686 const VkAllocationCallbacks* pAllocator)
2687 {
2688 RADV_FROM_HANDLE(radv_device, device, _device);
2689 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2690
2691 if (!fence)
2692 return;
2693
2694 if (fence->temp_syncobj)
2695 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2696 if (fence->syncobj)
2697 device->ws->destroy_syncobj(device->ws, fence->syncobj);
2698 if (fence->fence)
2699 device->ws->destroy_fence(fence->fence);
2700 vk_free2(&device->alloc, pAllocator, fence);
2701 }
2702
2703 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2704 {
2705 uint64_t current_time;
2706 struct timespec tv;
2707
2708 clock_gettime(CLOCK_MONOTONIC, &tv);
2709 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2710
2711 timeout = MIN2(UINT64_MAX - current_time, timeout);
2712
2713 return current_time + timeout;
2714 }
2715
2716 VkResult radv_WaitForFences(
2717 VkDevice _device,
2718 uint32_t fenceCount,
2719 const VkFence* pFences,
2720 VkBool32 waitAll,
2721 uint64_t timeout)
2722 {
2723 RADV_FROM_HANDLE(radv_device, device, _device);
2724 timeout = radv_get_absolute_timeout(timeout);
2725
2726 if (!waitAll && fenceCount > 1) {
2727 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2728 }
2729
2730 for (uint32_t i = 0; i < fenceCount; ++i) {
2731 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2732 bool expired = false;
2733
2734 if (fence->temp_syncobj) {
2735 if (!device->ws->wait_syncobj(device->ws, fence->temp_syncobj, timeout))
2736 return VK_TIMEOUT;
2737 continue;
2738 }
2739
2740 if (fence->syncobj) {
2741 if (!device->ws->wait_syncobj(device->ws, fence->syncobj, timeout))
2742 return VK_TIMEOUT;
2743 continue;
2744 }
2745
2746 if (fence->signalled)
2747 continue;
2748
2749 if (!fence->submitted)
2750 return VK_TIMEOUT;
2751
2752 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2753 if (!expired)
2754 return VK_TIMEOUT;
2755
2756 fence->signalled = true;
2757 }
2758
2759 return VK_SUCCESS;
2760 }
2761
2762 VkResult radv_ResetFences(VkDevice _device,
2763 uint32_t fenceCount,
2764 const VkFence *pFences)
2765 {
2766 RADV_FROM_HANDLE(radv_device, device, _device);
2767
2768 for (unsigned i = 0; i < fenceCount; ++i) {
2769 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2770 fence->submitted = fence->signalled = false;
2771
2772 /* Per spec, we first restore the permanent payload, and then reset, so
2773 * having a temp syncobj should not skip resetting the permanent syncobj. */
2774 if (fence->temp_syncobj) {
2775 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
2776 fence->temp_syncobj = 0;
2777 }
2778
2779 if (fence->syncobj) {
2780 device->ws->reset_syncobj(device->ws, fence->syncobj);
2781 }
2782 }
2783
2784 return VK_SUCCESS;
2785 }
2786
2787 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2788 {
2789 RADV_FROM_HANDLE(radv_device, device, _device);
2790 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2791
2792 if (fence->temp_syncobj) {
2793 bool success = device->ws->wait_syncobj(device->ws, fence->temp_syncobj, 0);
2794 return success ? VK_SUCCESS : VK_NOT_READY;
2795 }
2796
2797 if (fence->syncobj) {
2798 bool success = device->ws->wait_syncobj(device->ws, fence->syncobj, 0);
2799 return success ? VK_SUCCESS : VK_NOT_READY;
2800 }
2801
2802 if (fence->signalled)
2803 return VK_SUCCESS;
2804 if (!fence->submitted)
2805 return VK_NOT_READY;
2806 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2807 return VK_NOT_READY;
2808
2809 return VK_SUCCESS;
2810 }
2811
2812
2813 // Queue semaphore functions
2814
2815 VkResult radv_CreateSemaphore(
2816 VkDevice _device,
2817 const VkSemaphoreCreateInfo* pCreateInfo,
2818 const VkAllocationCallbacks* pAllocator,
2819 VkSemaphore* pSemaphore)
2820 {
2821 RADV_FROM_HANDLE(radv_device, device, _device);
2822 const VkExportSemaphoreCreateInfoKHR *export =
2823 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2824 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2825 export ? export->handleTypes : 0;
2826
2827 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2828 sizeof(*sem), 8,
2829 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2830 if (!sem)
2831 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2832
2833 sem->temp_syncobj = 0;
2834 /* create a syncobject if we are going to export this semaphore */
2835 if (handleTypes) {
2836 assert (device->physical_device->rad_info.has_syncobj);
2837 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2838 if (ret) {
2839 vk_free2(&device->alloc, pAllocator, sem);
2840 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2841 }
2842 sem->sem = NULL;
2843 } else {
2844 sem->sem = device->ws->create_sem(device->ws);
2845 if (!sem->sem) {
2846 vk_free2(&device->alloc, pAllocator, sem);
2847 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2848 }
2849 sem->syncobj = 0;
2850 }
2851
2852 *pSemaphore = radv_semaphore_to_handle(sem);
2853 return VK_SUCCESS;
2854 }
2855
2856 void radv_DestroySemaphore(
2857 VkDevice _device,
2858 VkSemaphore _semaphore,
2859 const VkAllocationCallbacks* pAllocator)
2860 {
2861 RADV_FROM_HANDLE(radv_device, device, _device);
2862 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2863 if (!_semaphore)
2864 return;
2865
2866 if (sem->syncobj)
2867 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2868 else
2869 device->ws->destroy_sem(sem->sem);
2870 vk_free2(&device->alloc, pAllocator, sem);
2871 }
2872
2873 VkResult radv_CreateEvent(
2874 VkDevice _device,
2875 const VkEventCreateInfo* pCreateInfo,
2876 const VkAllocationCallbacks* pAllocator,
2877 VkEvent* pEvent)
2878 {
2879 RADV_FROM_HANDLE(radv_device, device, _device);
2880 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2881 sizeof(*event), 8,
2882 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2883
2884 if (!event)
2885 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2886
2887 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2888 RADEON_DOMAIN_GTT,
2889 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2890 if (!event->bo) {
2891 vk_free2(&device->alloc, pAllocator, event);
2892 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2893 }
2894
2895 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2896
2897 *pEvent = radv_event_to_handle(event);
2898
2899 return VK_SUCCESS;
2900 }
2901
2902 void radv_DestroyEvent(
2903 VkDevice _device,
2904 VkEvent _event,
2905 const VkAllocationCallbacks* pAllocator)
2906 {
2907 RADV_FROM_HANDLE(radv_device, device, _device);
2908 RADV_FROM_HANDLE(radv_event, event, _event);
2909
2910 if (!event)
2911 return;
2912 device->ws->buffer_destroy(event->bo);
2913 vk_free2(&device->alloc, pAllocator, event);
2914 }
2915
2916 VkResult radv_GetEventStatus(
2917 VkDevice _device,
2918 VkEvent _event)
2919 {
2920 RADV_FROM_HANDLE(radv_event, event, _event);
2921
2922 if (*event->map == 1)
2923 return VK_EVENT_SET;
2924 return VK_EVENT_RESET;
2925 }
2926
2927 VkResult radv_SetEvent(
2928 VkDevice _device,
2929 VkEvent _event)
2930 {
2931 RADV_FROM_HANDLE(radv_event, event, _event);
2932 *event->map = 1;
2933
2934 return VK_SUCCESS;
2935 }
2936
2937 VkResult radv_ResetEvent(
2938 VkDevice _device,
2939 VkEvent _event)
2940 {
2941 RADV_FROM_HANDLE(radv_event, event, _event);
2942 *event->map = 0;
2943
2944 return VK_SUCCESS;
2945 }
2946
2947 VkResult radv_CreateBuffer(
2948 VkDevice _device,
2949 const VkBufferCreateInfo* pCreateInfo,
2950 const VkAllocationCallbacks* pAllocator,
2951 VkBuffer* pBuffer)
2952 {
2953 RADV_FROM_HANDLE(radv_device, device, _device);
2954 struct radv_buffer *buffer;
2955
2956 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2957
2958 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2959 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2960 if (buffer == NULL)
2961 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2962
2963 buffer->size = pCreateInfo->size;
2964 buffer->usage = pCreateInfo->usage;
2965 buffer->bo = NULL;
2966 buffer->offset = 0;
2967 buffer->flags = pCreateInfo->flags;
2968
2969 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2970 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2971
2972 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2973 buffer->bo = device->ws->buffer_create(device->ws,
2974 align64(buffer->size, 4096),
2975 4096, 0, RADEON_FLAG_VIRTUAL);
2976 if (!buffer->bo) {
2977 vk_free2(&device->alloc, pAllocator, buffer);
2978 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2979 }
2980 }
2981
2982 *pBuffer = radv_buffer_to_handle(buffer);
2983
2984 return VK_SUCCESS;
2985 }
2986
2987 void radv_DestroyBuffer(
2988 VkDevice _device,
2989 VkBuffer _buffer,
2990 const VkAllocationCallbacks* pAllocator)
2991 {
2992 RADV_FROM_HANDLE(radv_device, device, _device);
2993 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2994
2995 if (!buffer)
2996 return;
2997
2998 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2999 device->ws->buffer_destroy(buffer->bo);
3000
3001 vk_free2(&device->alloc, pAllocator, buffer);
3002 }
3003
3004 static inline unsigned
3005 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3006 {
3007 if (stencil)
3008 return image->surface.u.legacy.stencil_tiling_index[level];
3009 else
3010 return image->surface.u.legacy.tiling_index[level];
3011 }
3012
3013 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3014 {
3015 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3016 }
3017
3018 static void
3019 radv_initialise_color_surface(struct radv_device *device,
3020 struct radv_color_buffer_info *cb,
3021 struct radv_image_view *iview)
3022 {
3023 const struct vk_format_description *desc;
3024 unsigned ntype, format, swap, endian;
3025 unsigned blend_clamp = 0, blend_bypass = 0;
3026 uint64_t va;
3027 const struct radeon_surf *surf = &iview->image->surface;
3028
3029 desc = vk_format_description(iview->vk_format);
3030
3031 memset(cb, 0, sizeof(*cb));
3032
3033 /* Intensity is implemented as Red, so treat it that way. */
3034 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3035
3036 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3037
3038 cb->cb_color_base = va >> 8;
3039
3040 if (device->physical_device->rad_info.chip_class >= GFX9) {
3041 struct gfx9_surf_meta_flags meta;
3042 if (iview->image->dcc_offset)
3043 meta = iview->image->surface.u.gfx9.dcc;
3044 else
3045 meta = iview->image->surface.u.gfx9.cmask;
3046
3047 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3048 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3049 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3050 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3051
3052 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3053 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3054 } else {
3055 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3056 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3057
3058 cb->cb_color_base += level_info->offset >> 8;
3059 if (level_info->mode == RADEON_SURF_MODE_2D)
3060 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3061
3062 pitch_tile_max = level_info->nblk_x / 8 - 1;
3063 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3064 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3065
3066 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3067 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3068 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3069
3070 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3071
3072 if (iview->image->fmask.size) {
3073 if (device->physical_device->rad_info.chip_class >= CIK)
3074 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3075 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3076 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3077 } else {
3078 /* This must be set for fast clear to work without FMASK. */
3079 if (device->physical_device->rad_info.chip_class >= CIK)
3080 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3081 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3082 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3083 }
3084 }
3085
3086 /* CMASK variables */
3087 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3088 va += iview->image->cmask.offset;
3089 cb->cb_color_cmask = va >> 8;
3090
3091 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3092 va += iview->image->dcc_offset;
3093 cb->cb_dcc_base = va >> 8;
3094 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3095
3096 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3097 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3098 S_028C6C_SLICE_MAX(max_slice);
3099
3100 if (iview->image->info.samples > 1) {
3101 unsigned log_samples = util_logbase2(iview->image->info.samples);
3102
3103 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3104 S_028C74_NUM_FRAGMENTS(log_samples);
3105 }
3106
3107 if (iview->image->fmask.size) {
3108 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3109 cb->cb_color_fmask = va >> 8;
3110 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3111 } else {
3112 cb->cb_color_fmask = cb->cb_color_base;
3113 }
3114
3115 ntype = radv_translate_color_numformat(iview->vk_format,
3116 desc,
3117 vk_format_get_first_non_void_channel(iview->vk_format));
3118 format = radv_translate_colorformat(iview->vk_format);
3119 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3120 radv_finishme("Illegal color\n");
3121 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3122 endian = radv_colorformat_endian_swap(format);
3123
3124 /* blend clamp should be set for all NORM/SRGB types */
3125 if (ntype == V_028C70_NUMBER_UNORM ||
3126 ntype == V_028C70_NUMBER_SNORM ||
3127 ntype == V_028C70_NUMBER_SRGB)
3128 blend_clamp = 1;
3129
3130 /* set blend bypass according to docs if SINT/UINT or
3131 8/24 COLOR variants */
3132 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3133 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3134 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3135 blend_clamp = 0;
3136 blend_bypass = 1;
3137 }
3138 #if 0
3139 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3140 (format == V_028C70_COLOR_8 ||
3141 format == V_028C70_COLOR_8_8 ||
3142 format == V_028C70_COLOR_8_8_8_8))
3143 ->color_is_int8 = true;
3144 #endif
3145 cb->cb_color_info = S_028C70_FORMAT(format) |
3146 S_028C70_COMP_SWAP(swap) |
3147 S_028C70_BLEND_CLAMP(blend_clamp) |
3148 S_028C70_BLEND_BYPASS(blend_bypass) |
3149 S_028C70_SIMPLE_FLOAT(1) |
3150 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3151 ntype != V_028C70_NUMBER_SNORM &&
3152 ntype != V_028C70_NUMBER_SRGB &&
3153 format != V_028C70_COLOR_8_24 &&
3154 format != V_028C70_COLOR_24_8) |
3155 S_028C70_NUMBER_TYPE(ntype) |
3156 S_028C70_ENDIAN(endian);
3157 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3158 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3159 if (device->physical_device->rad_info.chip_class == SI) {
3160 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3161 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3162 }
3163 }
3164
3165 if (iview->image->cmask.size &&
3166 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3167 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3168
3169 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3170 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3171
3172 if (device->physical_device->rad_info.chip_class >= VI) {
3173 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3174 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3175 unsigned independent_64b_blocks = 0;
3176 unsigned max_compressed_block_size;
3177
3178 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3179 64 for APU because all of our APUs to date use DIMMs which have
3180 a request granularity size of 64B while all other chips have a
3181 32B request size */
3182 if (!device->physical_device->rad_info.has_dedicated_vram)
3183 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3184
3185 if (iview->image->info.samples > 1) {
3186 if (iview->image->surface.bpe == 1)
3187 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3188 else if (iview->image->surface.bpe == 2)
3189 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3190 }
3191
3192 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3193 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3194 independent_64b_blocks = 1;
3195 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3196 } else
3197 max_compressed_block_size = max_uncompressed_block_size;
3198
3199 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3200 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3201 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3202 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3203 }
3204
3205 /* This must be set for fast clear to work without FMASK. */
3206 if (!iview->image->fmask.size &&
3207 device->physical_device->rad_info.chip_class == SI) {
3208 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3209 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3210 }
3211
3212 if (device->physical_device->rad_info.chip_class >= GFX9) {
3213 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3214 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3215
3216 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3217 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3218 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3219 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3220 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3221 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3222 }
3223 }
3224
3225 static void
3226 radv_initialise_ds_surface(struct radv_device *device,
3227 struct radv_ds_buffer_info *ds,
3228 struct radv_image_view *iview)
3229 {
3230 unsigned level = iview->base_mip;
3231 unsigned format, stencil_format;
3232 uint64_t va, s_offs, z_offs;
3233 bool stencil_only = false;
3234 memset(ds, 0, sizeof(*ds));
3235 switch (iview->image->vk_format) {
3236 case VK_FORMAT_D24_UNORM_S8_UINT:
3237 case VK_FORMAT_X8_D24_UNORM_PACK32:
3238 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3239 ds->offset_scale = 2.0f;
3240 break;
3241 case VK_FORMAT_D16_UNORM:
3242 case VK_FORMAT_D16_UNORM_S8_UINT:
3243 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3244 ds->offset_scale = 4.0f;
3245 break;
3246 case VK_FORMAT_D32_SFLOAT:
3247 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3248 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3249 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3250 ds->offset_scale = 1.0f;
3251 break;
3252 case VK_FORMAT_S8_UINT:
3253 stencil_only = true;
3254 break;
3255 default:
3256 break;
3257 }
3258
3259 format = radv_translate_dbformat(iview->image->vk_format);
3260 stencil_format = iview->image->surface.has_stencil ?
3261 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3262
3263 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3264 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3265 S_028008_SLICE_MAX(max_slice);
3266
3267 ds->db_htile_data_base = 0;
3268 ds->db_htile_surface = 0;
3269
3270 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3271 s_offs = z_offs = va;
3272
3273 if (device->physical_device->rad_info.chip_class >= GFX9) {
3274 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3275 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3276
3277 ds->db_z_info = S_028038_FORMAT(format) |
3278 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3279 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3280 S_028038_MAXMIP(iview->image->info.levels - 1);
3281 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3282 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3283
3284 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3285 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3286 ds->db_depth_view |= S_028008_MIPID(level);
3287
3288 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3289 S_02801C_Y_MAX(iview->image->info.height - 1);
3290
3291 if (radv_htile_enabled(iview->image, level)) {
3292 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3293
3294 if (iview->image->tc_compatible_htile) {
3295 unsigned max_zplanes = 4;
3296
3297 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3298 iview->image->info.samples > 1)
3299 max_zplanes = 2;
3300
3301 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3302 S_028038_ITERATE_FLUSH(1);
3303 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3304 }
3305
3306 if (!iview->image->surface.has_stencil)
3307 /* Use all of the htile_buffer for depth if there's no stencil. */
3308 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3309 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3310 iview->image->htile_offset;
3311 ds->db_htile_data_base = va >> 8;
3312 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3313 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3314 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3315 }
3316 } else {
3317 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3318
3319 if (stencil_only)
3320 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3321
3322 z_offs += iview->image->surface.u.legacy.level[level].offset;
3323 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3324
3325 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3326 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3327 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3328
3329 if (iview->image->info.samples > 1)
3330 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3331
3332 if (device->physical_device->rad_info.chip_class >= CIK) {
3333 struct radeon_info *info = &device->physical_device->rad_info;
3334 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3335 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3336 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3337 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3338 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3339 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3340
3341 if (stencil_only)
3342 tile_mode = stencil_tile_mode;
3343
3344 ds->db_depth_info |=
3345 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3346 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3347 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3348 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3349 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3350 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3351 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3352 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3353 } else {
3354 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3355 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3356 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3357 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3358 if (stencil_only)
3359 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3360 }
3361
3362 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3363 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3364 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3365
3366 if (radv_htile_enabled(iview->image, level)) {
3367 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3368
3369 if (!iview->image->surface.has_stencil &&
3370 !iview->image->tc_compatible_htile)
3371 /* Use all of the htile_buffer for depth if there's no stencil. */
3372 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3373
3374 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3375 iview->image->htile_offset;
3376 ds->db_htile_data_base = va >> 8;
3377 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3378
3379 if (iview->image->tc_compatible_htile) {
3380 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3381
3382 if (iview->image->info.samples <= 1)
3383 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3384 else if (iview->image->info.samples <= 4)
3385 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3386 else
3387 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3388 }
3389 }
3390 }
3391
3392 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3393 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3394 }
3395
3396 VkResult radv_CreateFramebuffer(
3397 VkDevice _device,
3398 const VkFramebufferCreateInfo* pCreateInfo,
3399 const VkAllocationCallbacks* pAllocator,
3400 VkFramebuffer* pFramebuffer)
3401 {
3402 RADV_FROM_HANDLE(radv_device, device, _device);
3403 struct radv_framebuffer *framebuffer;
3404
3405 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3406
3407 size_t size = sizeof(*framebuffer) +
3408 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3409 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3410 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3411 if (framebuffer == NULL)
3412 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3413
3414 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3415 framebuffer->width = pCreateInfo->width;
3416 framebuffer->height = pCreateInfo->height;
3417 framebuffer->layers = pCreateInfo->layers;
3418 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3419 VkImageView _iview = pCreateInfo->pAttachments[i];
3420 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3421 framebuffer->attachments[i].attachment = iview;
3422 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3423 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3424 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3425 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3426 }
3427 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3428 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3429 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3430 }
3431
3432 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3433 return VK_SUCCESS;
3434 }
3435
3436 void radv_DestroyFramebuffer(
3437 VkDevice _device,
3438 VkFramebuffer _fb,
3439 const VkAllocationCallbacks* pAllocator)
3440 {
3441 RADV_FROM_HANDLE(radv_device, device, _device);
3442 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3443
3444 if (!fb)
3445 return;
3446 vk_free2(&device->alloc, pAllocator, fb);
3447 }
3448
3449 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3450 {
3451 switch (address_mode) {
3452 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3453 return V_008F30_SQ_TEX_WRAP;
3454 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3455 return V_008F30_SQ_TEX_MIRROR;
3456 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3457 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3458 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3459 return V_008F30_SQ_TEX_CLAMP_BORDER;
3460 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3461 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3462 default:
3463 unreachable("illegal tex wrap mode");
3464 break;
3465 }
3466 }
3467
3468 static unsigned
3469 radv_tex_compare(VkCompareOp op)
3470 {
3471 switch (op) {
3472 case VK_COMPARE_OP_NEVER:
3473 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3474 case VK_COMPARE_OP_LESS:
3475 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3476 case VK_COMPARE_OP_EQUAL:
3477 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3478 case VK_COMPARE_OP_LESS_OR_EQUAL:
3479 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3480 case VK_COMPARE_OP_GREATER:
3481 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3482 case VK_COMPARE_OP_NOT_EQUAL:
3483 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3484 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3485 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3486 case VK_COMPARE_OP_ALWAYS:
3487 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3488 default:
3489 unreachable("illegal compare mode");
3490 break;
3491 }
3492 }
3493
3494 static unsigned
3495 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3496 {
3497 switch (filter) {
3498 case VK_FILTER_NEAREST:
3499 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3500 V_008F38_SQ_TEX_XY_FILTER_POINT);
3501 case VK_FILTER_LINEAR:
3502 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3503 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3504 case VK_FILTER_CUBIC_IMG:
3505 default:
3506 fprintf(stderr, "illegal texture filter");
3507 return 0;
3508 }
3509 }
3510
3511 static unsigned
3512 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3513 {
3514 switch (mode) {
3515 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3516 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3517 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3518 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3519 default:
3520 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3521 }
3522 }
3523
3524 static unsigned
3525 radv_tex_bordercolor(VkBorderColor bcolor)
3526 {
3527 switch (bcolor) {
3528 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3529 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3530 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3531 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3532 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3533 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3534 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3535 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3536 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3537 default:
3538 break;
3539 }
3540 return 0;
3541 }
3542
3543 static unsigned
3544 radv_tex_aniso_filter(unsigned filter)
3545 {
3546 if (filter < 2)
3547 return 0;
3548 if (filter < 4)
3549 return 1;
3550 if (filter < 8)
3551 return 2;
3552 if (filter < 16)
3553 return 3;
3554 return 4;
3555 }
3556
3557 static void
3558 radv_init_sampler(struct radv_device *device,
3559 struct radv_sampler *sampler,
3560 const VkSamplerCreateInfo *pCreateInfo)
3561 {
3562 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3563 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3564 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3565 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3566
3567 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3568 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3569 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3570 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3571 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3572 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3573 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3574 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3575 S_008F30_DISABLE_CUBE_WRAP(0) |
3576 S_008F30_COMPAT_MODE(is_vi));
3577 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3578 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3579 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3580 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3581 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3582 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3583 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3584 S_008F38_MIP_POINT_PRECLAMP(0) |
3585 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3586 S_008F38_FILTER_PREC_FIX(1) |
3587 S_008F38_ANISO_OVERRIDE(is_vi));
3588 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3589 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3590 }
3591
3592 VkResult radv_CreateSampler(
3593 VkDevice _device,
3594 const VkSamplerCreateInfo* pCreateInfo,
3595 const VkAllocationCallbacks* pAllocator,
3596 VkSampler* pSampler)
3597 {
3598 RADV_FROM_HANDLE(radv_device, device, _device);
3599 struct radv_sampler *sampler;
3600
3601 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3602
3603 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3604 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3605 if (!sampler)
3606 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3607
3608 radv_init_sampler(device, sampler, pCreateInfo);
3609 *pSampler = radv_sampler_to_handle(sampler);
3610
3611 return VK_SUCCESS;
3612 }
3613
3614 void radv_DestroySampler(
3615 VkDevice _device,
3616 VkSampler _sampler,
3617 const VkAllocationCallbacks* pAllocator)
3618 {
3619 RADV_FROM_HANDLE(radv_device, device, _device);
3620 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3621
3622 if (!sampler)
3623 return;
3624 vk_free2(&device->alloc, pAllocator, sampler);
3625 }
3626
3627 /* vk_icd.h does not declare this function, so we declare it here to
3628 * suppress Wmissing-prototypes.
3629 */
3630 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3631 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3632
3633 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3634 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3635 {
3636 /* For the full details on loader interface versioning, see
3637 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3638 * What follows is a condensed summary, to help you navigate the large and
3639 * confusing official doc.
3640 *
3641 * - Loader interface v0 is incompatible with later versions. We don't
3642 * support it.
3643 *
3644 * - In loader interface v1:
3645 * - The first ICD entrypoint called by the loader is
3646 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3647 * entrypoint.
3648 * - The ICD must statically expose no other Vulkan symbol unless it is
3649 * linked with -Bsymbolic.
3650 * - Each dispatchable Vulkan handle created by the ICD must be
3651 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3652 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3653 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3654 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3655 * such loader-managed surfaces.
3656 *
3657 * - Loader interface v2 differs from v1 in:
3658 * - The first ICD entrypoint called by the loader is
3659 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3660 * statically expose this entrypoint.
3661 *
3662 * - Loader interface v3 differs from v2 in:
3663 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3664 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3665 * because the loader no longer does so.
3666 */
3667 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3668 return VK_SUCCESS;
3669 }
3670
3671 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3672 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3673 int *pFD)
3674 {
3675 RADV_FROM_HANDLE(radv_device, device, _device);
3676 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3677
3678 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3679
3680 /* At the moment, we support only the below handle types. */
3681 assert(pGetFdInfo->handleType ==
3682 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3683 pGetFdInfo->handleType ==
3684 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3685
3686 bool ret = radv_get_memory_fd(device, memory, pFD);
3687 if (ret == false)
3688 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3689 return VK_SUCCESS;
3690 }
3691
3692 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3693 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3694 int fd,
3695 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3696 {
3697 switch (handleType) {
3698 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3699 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3700 return VK_SUCCESS;
3701
3702 default:
3703 /* The valid usage section for this function says:
3704 *
3705 * "handleType must not be one of the handle types defined as
3706 * opaque."
3707 *
3708 * So opaque handle types fall into the default "unsupported" case.
3709 */
3710 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3711 }
3712 }
3713
3714 static VkResult radv_import_opaque_fd(struct radv_device *device,
3715 int fd,
3716 uint32_t *syncobj)
3717 {
3718 uint32_t syncobj_handle = 0;
3719 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
3720 if (ret != 0)
3721 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3722
3723 if (*syncobj)
3724 device->ws->destroy_syncobj(device->ws, *syncobj);
3725
3726 *syncobj = syncobj_handle;
3727 close(fd);
3728
3729 return VK_SUCCESS;
3730 }
3731
3732 static VkResult radv_import_sync_fd(struct radv_device *device,
3733 int fd,
3734 uint32_t *syncobj)
3735 {
3736 /* If we create a syncobj we do it locally so that if we have an error, we don't
3737 * leave a syncobj in an undetermined state in the fence. */
3738 uint32_t syncobj_handle = *syncobj;
3739 if (!syncobj_handle) {
3740 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
3741 if (ret) {
3742 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3743 }
3744 }
3745
3746 if (fd == -1) {
3747 device->ws->signal_syncobj(device->ws, syncobj_handle);
3748 } else {
3749 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
3750 if (ret != 0)
3751 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3752 }
3753
3754 *syncobj = syncobj_handle;
3755 if (fd != -1)
3756 close(fd);
3757
3758 return VK_SUCCESS;
3759 }
3760
3761 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3762 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3763 {
3764 RADV_FROM_HANDLE(radv_device, device, _device);
3765 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3766 uint32_t *syncobj_dst = NULL;
3767
3768 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3769 syncobj_dst = &sem->temp_syncobj;
3770 } else {
3771 syncobj_dst = &sem->syncobj;
3772 }
3773
3774 switch(pImportSemaphoreFdInfo->handleType) {
3775 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3776 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3777 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3778 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
3779 default:
3780 unreachable("Unhandled semaphore handle type");
3781 }
3782 }
3783
3784 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3785 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3786 int *pFd)
3787 {
3788 RADV_FROM_HANDLE(radv_device, device, _device);
3789 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3790 int ret;
3791 uint32_t syncobj_handle;
3792
3793 if (sem->temp_syncobj)
3794 syncobj_handle = sem->temp_syncobj;
3795 else
3796 syncobj_handle = sem->syncobj;
3797
3798 switch(pGetFdInfo->handleType) {
3799 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3800 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3801 break;
3802 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3803 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3804 break;
3805 default:
3806 unreachable("Unhandled semaphore handle type");
3807 }
3808
3809 if (ret)
3810 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3811 return VK_SUCCESS;
3812 }
3813
3814 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3815 VkPhysicalDevice physicalDevice,
3816 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3817 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3818 {
3819 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3820
3821 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
3822 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3823 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3824 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3825 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3826 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3827 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3828 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3829 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3830 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3831 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3832 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3833 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3834 } else {
3835 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3836 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3837 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3838 }
3839 }
3840
3841 VkResult radv_ImportFenceFdKHR(VkDevice _device,
3842 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
3843 {
3844 RADV_FROM_HANDLE(radv_device, device, _device);
3845 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
3846 uint32_t *syncobj_dst = NULL;
3847
3848
3849 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
3850 syncobj_dst = &fence->temp_syncobj;
3851 } else {
3852 syncobj_dst = &fence->syncobj;
3853 }
3854
3855 switch(pImportFenceFdInfo->handleType) {
3856 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3857 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3858 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3859 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
3860 default:
3861 unreachable("Unhandled fence handle type");
3862 }
3863 }
3864
3865 VkResult radv_GetFenceFdKHR(VkDevice _device,
3866 const VkFenceGetFdInfoKHR *pGetFdInfo,
3867 int *pFd)
3868 {
3869 RADV_FROM_HANDLE(radv_device, device, _device);
3870 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
3871 int ret;
3872 uint32_t syncobj_handle;
3873
3874 if (fence->temp_syncobj)
3875 syncobj_handle = fence->temp_syncobj;
3876 else
3877 syncobj_handle = fence->syncobj;
3878
3879 switch(pGetFdInfo->handleType) {
3880 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
3881 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3882 break;
3883 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
3884 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
3885 break;
3886 default:
3887 unreachable("Unhandled fence handle type");
3888 }
3889
3890 if (ret)
3891 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3892 return VK_SUCCESS;
3893 }
3894
3895 void radv_GetPhysicalDeviceExternalFencePropertiesKHR(
3896 VkPhysicalDevice physicalDevice,
3897 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
3898 VkExternalFencePropertiesKHR* pExternalFenceProperties)
3899 {
3900 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
3901
3902 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
3903 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3904 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
3905 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3906 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
3907 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
3908 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3909 } else {
3910 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
3911 pExternalFenceProperties->compatibleHandleTypes = 0;
3912 pExternalFenceProperties->externalFenceFeatures = 0;
3913 }
3914 }