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radv: add radv_htile_enabled() helper
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 {
174 .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 {
178 .extensionName = VK_KHR_BIND_MEMORY_2_EXTENSION_NAME,
179 .specVersion = 1,
180 },
181 {
182 .extensionName = VK_KHR_MAINTENANCE2_EXTENSION_NAME,
183 .specVersion = 1,
184 },
185 };
186
187 static const VkExtensionProperties rasterization_order_extension[] ={
188 {
189 .extensionName = VK_AMD_RASTERIZATION_ORDER_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static const VkExtensionProperties ext_sema_device_extensions[] = {
195 {
196 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
197 .specVersion = 1,
198 },
199 {
200 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
201 .specVersion = 1,
202 },
203 {
204 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
205 .specVersion = 1,
206 },
207 };
208
209 static VkResult
210 radv_extensions_register(struct radv_instance *instance,
211 struct radv_extensions *extensions,
212 const VkExtensionProperties *new_ext,
213 uint32_t num_ext)
214 {
215 size_t new_size;
216 VkExtensionProperties *new_ptr;
217
218 assert(new_ext && num_ext > 0);
219
220 if (!new_ext)
221 return VK_ERROR_INITIALIZATION_FAILED;
222
223 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
224 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
225 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
226
227 /* Old array continues to be valid, update nothing */
228 if (!new_ptr)
229 return VK_ERROR_OUT_OF_HOST_MEMORY;
230
231 memcpy(&new_ptr[extensions->num_ext], new_ext,
232 num_ext * sizeof(VkExtensionProperties));
233 extensions->ext_array = new_ptr;
234 extensions->num_ext += num_ext;
235
236 return VK_SUCCESS;
237 }
238
239 static void
240 radv_extensions_finish(struct radv_instance *instance,
241 struct radv_extensions *extensions)
242 {
243 assert(extensions);
244
245 if (!extensions)
246 radv_loge("Attemted to free invalid extension struct\n");
247
248 if (extensions->ext_array)
249 vk_free(&instance->alloc, extensions->ext_array);
250 }
251
252 static bool
253 is_extension_enabled(const VkExtensionProperties *extensions,
254 size_t num_ext,
255 const char *name)
256 {
257 assert(extensions && name);
258
259 for (uint32_t i = 0; i < num_ext; i++) {
260 if (strcmp(name, extensions[i].extensionName) == 0)
261 return true;
262 }
263
264 return false;
265 }
266
267 static const char *
268 get_chip_name(enum radeon_family family)
269 {
270 switch (family) {
271 case CHIP_TAHITI: return "AMD RADV TAHITI";
272 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
273 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
274 case CHIP_OLAND: return "AMD RADV OLAND";
275 case CHIP_HAINAN: return "AMD RADV HAINAN";
276 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
277 case CHIP_KAVERI: return "AMD RADV KAVERI";
278 case CHIP_KABINI: return "AMD RADV KABINI";
279 case CHIP_HAWAII: return "AMD RADV HAWAII";
280 case CHIP_MULLINS: return "AMD RADV MULLINS";
281 case CHIP_TONGA: return "AMD RADV TONGA";
282 case CHIP_ICELAND: return "AMD RADV ICELAND";
283 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
284 case CHIP_FIJI: return "AMD RADV FIJI";
285 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
286 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
287 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
288 case CHIP_STONEY: return "AMD RADV STONEY";
289 case CHIP_VEGA10: return "AMD RADV VEGA";
290 case CHIP_RAVEN: return "AMD RADV RAVEN";
291 default: return "AMD RADV unknown";
292 }
293 }
294
295 static VkResult
296 radv_physical_device_init(struct radv_physical_device *device,
297 struct radv_instance *instance,
298 drmDevicePtr drm_device)
299 {
300 const char *path = drm_device->nodes[DRM_NODE_RENDER];
301 VkResult result;
302 drmVersionPtr version;
303 int fd;
304
305 fd = open(path, O_RDWR | O_CLOEXEC);
306 if (fd < 0)
307 return VK_ERROR_INCOMPATIBLE_DRIVER;
308
309 version = drmGetVersion(fd);
310 if (!version) {
311 close(fd);
312 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
313 "failed to get version %s: %m", path);
314 }
315
316 if (strcmp(version->name, "amdgpu")) {
317 drmFreeVersion(version);
318 close(fd);
319 return VK_ERROR_INCOMPATIBLE_DRIVER;
320 }
321 drmFreeVersion(version);
322
323 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
324 device->instance = instance;
325 assert(strlen(path) < ARRAY_SIZE(device->path));
326 strncpy(device->path, path, ARRAY_SIZE(device->path));
327
328 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
329 instance->perftest_flags);
330 if (!device->ws) {
331 result = VK_ERROR_INCOMPATIBLE_DRIVER;
332 goto fail;
333 }
334
335 device->local_fd = fd;
336 device->ws->query_info(device->ws, &device->rad_info);
337 result = radv_init_wsi(device);
338 if (result != VK_SUCCESS) {
339 device->ws->destroy(device->ws);
340 goto fail;
341 }
342
343 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
344 radv_finish_wsi(device);
345 device->ws->destroy(device->ws);
346 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
347 "cannot generate UUID");
348 goto fail;
349 }
350
351 result = radv_extensions_register(instance,
352 &device->extensions,
353 common_device_extensions,
354 ARRAY_SIZE(common_device_extensions));
355 if (result != VK_SUCCESS)
356 goto fail;
357
358 if (device->rad_info.chip_class >= VI && device->rad_info.max_se >= 2) {
359 result = radv_extensions_register(instance,
360 &device->extensions,
361 rasterization_order_extension,
362 ARRAY_SIZE(rasterization_order_extension));
363 if (result != VK_SUCCESS)
364 goto fail;
365 }
366
367 if (device->rad_info.has_syncobj) {
368 result = radv_extensions_register(instance,
369 &device->extensions,
370 ext_sema_device_extensions,
371 ARRAY_SIZE(ext_sema_device_extensions));
372 if (result != VK_SUCCESS)
373 goto fail;
374 }
375
376 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
377 device->name = get_chip_name(device->rad_info.family);
378
379 radv_get_driver_uuid(&device->device_uuid);
380 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
381
382 if (device->rad_info.family == CHIP_STONEY ||
383 device->rad_info.chip_class >= GFX9) {
384 device->has_rbplus = true;
385 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
386 }
387
388 return VK_SUCCESS;
389
390 fail:
391 close(fd);
392 return result;
393 }
394
395 static void
396 radv_physical_device_finish(struct radv_physical_device *device)
397 {
398 radv_extensions_finish(device->instance, &device->extensions);
399 radv_finish_wsi(device);
400 device->ws->destroy(device->ws);
401 close(device->local_fd);
402 }
403
404 static void *
405 default_alloc_func(void *pUserData, size_t size, size_t align,
406 VkSystemAllocationScope allocationScope)
407 {
408 return malloc(size);
409 }
410
411 static void *
412 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
413 size_t align, VkSystemAllocationScope allocationScope)
414 {
415 return realloc(pOriginal, size);
416 }
417
418 static void
419 default_free_func(void *pUserData, void *pMemory)
420 {
421 free(pMemory);
422 }
423
424 static const VkAllocationCallbacks default_alloc = {
425 .pUserData = NULL,
426 .pfnAllocation = default_alloc_func,
427 .pfnReallocation = default_realloc_func,
428 .pfnFree = default_free_func,
429 };
430
431 static const struct debug_control radv_debug_options[] = {
432 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
433 {"nodcc", RADV_DEBUG_NO_DCC},
434 {"shaders", RADV_DEBUG_DUMP_SHADERS},
435 {"nocache", RADV_DEBUG_NO_CACHE},
436 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
437 {"nohiz", RADV_DEBUG_NO_HIZ},
438 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
439 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
440 {"allbos", RADV_DEBUG_ALL_BOS},
441 {"noibs", RADV_DEBUG_NO_IBS},
442 {"spirv", RADV_DEBUG_DUMP_SPIRV},
443 {"vmfaults", RADV_DEBUG_VM_FAULTS},
444 {"zerovram", RADV_DEBUG_ZERO_VRAM},
445 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
446 {NULL, 0}
447 };
448
449 const char *
450 radv_get_debug_option_name(int id)
451 {
452 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
453 return radv_debug_options[id].string;
454 }
455
456 static const struct debug_control radv_perftest_options[] = {
457 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
458 {"sisched", RADV_PERFTEST_SISCHED},
459 {NULL, 0}
460 };
461
462 const char *
463 radv_get_perftest_option_name(int id)
464 {
465 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
466 return radv_perftest_options[id].string;
467 }
468
469 VkResult radv_CreateInstance(
470 const VkInstanceCreateInfo* pCreateInfo,
471 const VkAllocationCallbacks* pAllocator,
472 VkInstance* pInstance)
473 {
474 struct radv_instance *instance;
475
476 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
477
478 uint32_t client_version;
479 if (pCreateInfo->pApplicationInfo &&
480 pCreateInfo->pApplicationInfo->apiVersion != 0) {
481 client_version = pCreateInfo->pApplicationInfo->apiVersion;
482 } else {
483 client_version = VK_MAKE_VERSION(1, 0, 0);
484 }
485
486 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
487 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
488 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
489 "Client requested version %d.%d.%d",
490 VK_VERSION_MAJOR(client_version),
491 VK_VERSION_MINOR(client_version),
492 VK_VERSION_PATCH(client_version));
493 }
494
495 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
496 if (!is_extension_enabled(instance_extensions,
497 ARRAY_SIZE(instance_extensions),
498 pCreateInfo->ppEnabledExtensionNames[i]))
499 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
500 }
501
502 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
503 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
504 if (!instance)
505 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
506
507 memset(instance, 0, sizeof(*instance));
508
509 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
510
511 if (pAllocator)
512 instance->alloc = *pAllocator;
513 else
514 instance->alloc = default_alloc;
515
516 instance->apiVersion = client_version;
517 instance->physicalDeviceCount = -1;
518
519 _mesa_locale_init();
520
521 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
522
523 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
524 radv_debug_options);
525
526 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
527 radv_perftest_options);
528
529 *pInstance = radv_instance_to_handle(instance);
530
531 return VK_SUCCESS;
532 }
533
534 void radv_DestroyInstance(
535 VkInstance _instance,
536 const VkAllocationCallbacks* pAllocator)
537 {
538 RADV_FROM_HANDLE(radv_instance, instance, _instance);
539
540 if (!instance)
541 return;
542
543 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
544 radv_physical_device_finish(instance->physicalDevices + i);
545 }
546
547 VG(VALGRIND_DESTROY_MEMPOOL(instance));
548
549 _mesa_locale_fini();
550
551 vk_free(&instance->alloc, instance);
552 }
553
554 static VkResult
555 radv_enumerate_devices(struct radv_instance *instance)
556 {
557 /* TODO: Check for more devices ? */
558 drmDevicePtr devices[8];
559 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
560 int max_devices;
561
562 instance->physicalDeviceCount = 0;
563
564 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
565 if (max_devices < 1)
566 return VK_ERROR_INCOMPATIBLE_DRIVER;
567
568 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
569 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
570 devices[i]->bustype == DRM_BUS_PCI &&
571 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
572
573 result = radv_physical_device_init(instance->physicalDevices +
574 instance->physicalDeviceCount,
575 instance,
576 devices[i]);
577 if (result == VK_SUCCESS)
578 ++instance->physicalDeviceCount;
579 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
580 break;
581 }
582 }
583 drmFreeDevices(devices, max_devices);
584
585 return result;
586 }
587
588 VkResult radv_EnumeratePhysicalDevices(
589 VkInstance _instance,
590 uint32_t* pPhysicalDeviceCount,
591 VkPhysicalDevice* pPhysicalDevices)
592 {
593 RADV_FROM_HANDLE(radv_instance, instance, _instance);
594 VkResult result;
595
596 if (instance->physicalDeviceCount < 0) {
597 result = radv_enumerate_devices(instance);
598 if (result != VK_SUCCESS &&
599 result != VK_ERROR_INCOMPATIBLE_DRIVER)
600 return result;
601 }
602
603 if (!pPhysicalDevices) {
604 *pPhysicalDeviceCount = instance->physicalDeviceCount;
605 } else {
606 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
607 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
608 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
609 }
610
611 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
612 : VK_SUCCESS;
613 }
614
615 void radv_GetPhysicalDeviceFeatures(
616 VkPhysicalDevice physicalDevice,
617 VkPhysicalDeviceFeatures* pFeatures)
618 {
619 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
620 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
621 memset(pFeatures, 0, sizeof(*pFeatures));
622
623 *pFeatures = (VkPhysicalDeviceFeatures) {
624 .robustBufferAccess = true,
625 .fullDrawIndexUint32 = true,
626 .imageCubeArray = true,
627 .independentBlend = true,
628 .geometryShader = !is_gfx9,
629 .tessellationShader = !is_gfx9,
630 .sampleRateShading = true,
631 .dualSrcBlend = true,
632 .logicOp = true,
633 .multiDrawIndirect = true,
634 .drawIndirectFirstInstance = true,
635 .depthClamp = true,
636 .depthBiasClamp = true,
637 .fillModeNonSolid = true,
638 .depthBounds = true,
639 .wideLines = true,
640 .largePoints = true,
641 .alphaToOne = true,
642 .multiViewport = true,
643 .samplerAnisotropy = true,
644 .textureCompressionETC2 = false,
645 .textureCompressionASTC_LDR = false,
646 .textureCompressionBC = true,
647 .occlusionQueryPrecise = true,
648 .pipelineStatisticsQuery = true,
649 .vertexPipelineStoresAndAtomics = true,
650 .fragmentStoresAndAtomics = true,
651 .shaderTessellationAndGeometryPointSize = true,
652 .shaderImageGatherExtended = true,
653 .shaderStorageImageExtendedFormats = true,
654 .shaderStorageImageMultisample = false,
655 .shaderUniformBufferArrayDynamicIndexing = true,
656 .shaderSampledImageArrayDynamicIndexing = true,
657 .shaderStorageBufferArrayDynamicIndexing = true,
658 .shaderStorageImageArrayDynamicIndexing = true,
659 .shaderStorageImageReadWithoutFormat = true,
660 .shaderStorageImageWriteWithoutFormat = true,
661 .shaderClipDistance = true,
662 .shaderCullDistance = true,
663 .shaderFloat64 = true,
664 .shaderInt64 = true,
665 .shaderInt16 = false,
666 .sparseBinding = true,
667 .variableMultisampleRate = true,
668 .inheritedQueries = true,
669 };
670 }
671
672 void radv_GetPhysicalDeviceFeatures2KHR(
673 VkPhysicalDevice physicalDevice,
674 VkPhysicalDeviceFeatures2KHR *pFeatures)
675 {
676 vk_foreach_struct(ext, pFeatures->pNext) {
677 switch (ext->sType) {
678 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
679 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
680 features->variablePointersStorageBuffer = true;
681 features->variablePointers = false;
682 break;
683 }
684 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
685 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
686 features->multiview = true;
687 features->multiviewGeometryShader = true;
688 features->multiviewTessellationShader = true;
689 break;
690 }
691 default:
692 break;
693 }
694 }
695 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
696 }
697
698 void radv_GetPhysicalDeviceProperties(
699 VkPhysicalDevice physicalDevice,
700 VkPhysicalDeviceProperties* pProperties)
701 {
702 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
703 VkSampleCountFlags sample_counts = 0xf;
704
705 /* make sure that the entire descriptor set is addressable with a signed
706 * 32-bit int. So the sum of all limits scaled by descriptor size has to
707 * be at most 2 GiB. the combined image & samples object count as one of
708 * both. This limit is for the pipeline layout, not for the set layout, but
709 * there is no set limit, so we just set a pipeline limit. I don't think
710 * any app is going to hit this soon. */
711 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
712 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
713 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
714 32 /* sampler, largest when combined with image */ +
715 64 /* sampled image */ +
716 64 /* storage image */);
717
718 VkPhysicalDeviceLimits limits = {
719 .maxImageDimension1D = (1 << 14),
720 .maxImageDimension2D = (1 << 14),
721 .maxImageDimension3D = (1 << 11),
722 .maxImageDimensionCube = (1 << 14),
723 .maxImageArrayLayers = (1 << 11),
724 .maxTexelBufferElements = 128 * 1024 * 1024,
725 .maxUniformBufferRange = UINT32_MAX,
726 .maxStorageBufferRange = UINT32_MAX,
727 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
728 .maxMemoryAllocationCount = UINT32_MAX,
729 .maxSamplerAllocationCount = 64 * 1024,
730 .bufferImageGranularity = 64, /* A cache line */
731 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
732 .maxBoundDescriptorSets = MAX_SETS,
733 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
734 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
735 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
736 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
737 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
738 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
739 .maxPerStageResources = max_descriptor_set_size,
740 .maxDescriptorSetSamplers = max_descriptor_set_size,
741 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
742 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
743 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
744 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
745 .maxDescriptorSetSampledImages = max_descriptor_set_size,
746 .maxDescriptorSetStorageImages = max_descriptor_set_size,
747 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
748 .maxVertexInputAttributes = 32,
749 .maxVertexInputBindings = 32,
750 .maxVertexInputAttributeOffset = 2047,
751 .maxVertexInputBindingStride = 2048,
752 .maxVertexOutputComponents = 128,
753 .maxTessellationGenerationLevel = 64,
754 .maxTessellationPatchSize = 32,
755 .maxTessellationControlPerVertexInputComponents = 128,
756 .maxTessellationControlPerVertexOutputComponents = 128,
757 .maxTessellationControlPerPatchOutputComponents = 120,
758 .maxTessellationControlTotalOutputComponents = 4096,
759 .maxTessellationEvaluationInputComponents = 128,
760 .maxTessellationEvaluationOutputComponents = 128,
761 .maxGeometryShaderInvocations = 127,
762 .maxGeometryInputComponents = 64,
763 .maxGeometryOutputComponents = 128,
764 .maxGeometryOutputVertices = 256,
765 .maxGeometryTotalOutputComponents = 1024,
766 .maxFragmentInputComponents = 128,
767 .maxFragmentOutputAttachments = 8,
768 .maxFragmentDualSrcAttachments = 1,
769 .maxFragmentCombinedOutputResources = 8,
770 .maxComputeSharedMemorySize = 32768,
771 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
772 .maxComputeWorkGroupInvocations = 2048,
773 .maxComputeWorkGroupSize = {
774 2048,
775 2048,
776 2048
777 },
778 .subPixelPrecisionBits = 4 /* FIXME */,
779 .subTexelPrecisionBits = 4 /* FIXME */,
780 .mipmapPrecisionBits = 4 /* FIXME */,
781 .maxDrawIndexedIndexValue = UINT32_MAX,
782 .maxDrawIndirectCount = UINT32_MAX,
783 .maxSamplerLodBias = 16,
784 .maxSamplerAnisotropy = 16,
785 .maxViewports = MAX_VIEWPORTS,
786 .maxViewportDimensions = { (1 << 14), (1 << 14) },
787 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
788 .viewportSubPixelBits = 13, /* We take a float? */
789 .minMemoryMapAlignment = 4096, /* A page */
790 .minTexelBufferOffsetAlignment = 1,
791 .minUniformBufferOffsetAlignment = 4,
792 .minStorageBufferOffsetAlignment = 4,
793 .minTexelOffset = -32,
794 .maxTexelOffset = 31,
795 .minTexelGatherOffset = -32,
796 .maxTexelGatherOffset = 31,
797 .minInterpolationOffset = -2,
798 .maxInterpolationOffset = 2,
799 .subPixelInterpolationOffsetBits = 8,
800 .maxFramebufferWidth = (1 << 14),
801 .maxFramebufferHeight = (1 << 14),
802 .maxFramebufferLayers = (1 << 10),
803 .framebufferColorSampleCounts = sample_counts,
804 .framebufferDepthSampleCounts = sample_counts,
805 .framebufferStencilSampleCounts = sample_counts,
806 .framebufferNoAttachmentsSampleCounts = sample_counts,
807 .maxColorAttachments = MAX_RTS,
808 .sampledImageColorSampleCounts = sample_counts,
809 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
810 .sampledImageDepthSampleCounts = sample_counts,
811 .sampledImageStencilSampleCounts = sample_counts,
812 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
813 .maxSampleMaskWords = 1,
814 .timestampComputeAndGraphics = true,
815 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
816 .maxClipDistances = 8,
817 .maxCullDistances = 8,
818 .maxCombinedClipAndCullDistances = 8,
819 .discreteQueuePriorities = 1,
820 .pointSizeRange = { 0.125, 255.875 },
821 .lineWidthRange = { 0.0, 7.9921875 },
822 .pointSizeGranularity = (1.0 / 8.0),
823 .lineWidthGranularity = (1.0 / 128.0),
824 .strictLines = false, /* FINISHME */
825 .standardSampleLocations = true,
826 .optimalBufferCopyOffsetAlignment = 128,
827 .optimalBufferCopyRowPitchAlignment = 128,
828 .nonCoherentAtomSize = 64,
829 };
830
831 *pProperties = (VkPhysicalDeviceProperties) {
832 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
833 .driverVersion = vk_get_driver_version(),
834 .vendorID = ATI_VENDOR_ID,
835 .deviceID = pdevice->rad_info.pci_id,
836 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
837 .limits = limits,
838 .sparseProperties = {0},
839 };
840
841 strcpy(pProperties->deviceName, pdevice->name);
842 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
843 }
844
845 void radv_GetPhysicalDeviceProperties2KHR(
846 VkPhysicalDevice physicalDevice,
847 VkPhysicalDeviceProperties2KHR *pProperties)
848 {
849 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
850 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
851
852 vk_foreach_struct(ext, pProperties->pNext) {
853 switch (ext->sType) {
854 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
855 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
856 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
857 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
861 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
862 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
863 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
864 properties->deviceLUIDValid = false;
865 break;
866 }
867 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
868 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
869 properties->maxMultiviewViewCount = MAX_VIEWS;
870 properties->maxMultiviewInstanceIndex = INT_MAX;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
874 VkPhysicalDevicePointClippingPropertiesKHR *properties =
875 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
876 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
877 break;
878 }
879 default:
880 break;
881 }
882 }
883 }
884
885 static void radv_get_physical_device_queue_family_properties(
886 struct radv_physical_device* pdevice,
887 uint32_t* pCount,
888 VkQueueFamilyProperties** pQueueFamilyProperties)
889 {
890 int num_queue_families = 1;
891 int idx;
892 if (pdevice->rad_info.num_compute_rings > 0 &&
893 pdevice->rad_info.chip_class >= CIK &&
894 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
895 num_queue_families++;
896
897 if (pQueueFamilyProperties == NULL) {
898 *pCount = num_queue_families;
899 return;
900 }
901
902 if (!*pCount)
903 return;
904
905 idx = 0;
906 if (*pCount >= 1) {
907 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
908 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
909 VK_QUEUE_COMPUTE_BIT |
910 VK_QUEUE_TRANSFER_BIT |
911 VK_QUEUE_SPARSE_BINDING_BIT,
912 .queueCount = 1,
913 .timestampValidBits = 64,
914 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
915 };
916 idx++;
917 }
918
919 if (pdevice->rad_info.num_compute_rings > 0 &&
920 pdevice->rad_info.chip_class >= CIK &&
921 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
922 if (*pCount > idx) {
923 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
924 .queueFlags = VK_QUEUE_COMPUTE_BIT |
925 VK_QUEUE_TRANSFER_BIT |
926 VK_QUEUE_SPARSE_BINDING_BIT,
927 .queueCount = pdevice->rad_info.num_compute_rings,
928 .timestampValidBits = 64,
929 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
930 };
931 idx++;
932 }
933 }
934 *pCount = idx;
935 }
936
937 void radv_GetPhysicalDeviceQueueFamilyProperties(
938 VkPhysicalDevice physicalDevice,
939 uint32_t* pCount,
940 VkQueueFamilyProperties* pQueueFamilyProperties)
941 {
942 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
943 if (!pQueueFamilyProperties) {
944 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
945 return;
946 }
947 VkQueueFamilyProperties *properties[] = {
948 pQueueFamilyProperties + 0,
949 pQueueFamilyProperties + 1,
950 pQueueFamilyProperties + 2,
951 };
952 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
953 assert(*pCount <= 3);
954 }
955
956 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
957 VkPhysicalDevice physicalDevice,
958 uint32_t* pCount,
959 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
960 {
961 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
962 if (!pQueueFamilyProperties) {
963 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
964 return;
965 }
966 VkQueueFamilyProperties *properties[] = {
967 &pQueueFamilyProperties[0].queueFamilyProperties,
968 &pQueueFamilyProperties[1].queueFamilyProperties,
969 &pQueueFamilyProperties[2].queueFamilyProperties,
970 };
971 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
972 assert(*pCount <= 3);
973 }
974
975 void radv_GetPhysicalDeviceMemoryProperties(
976 VkPhysicalDevice physicalDevice,
977 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
978 {
979 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
980
981 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
982
983 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
984 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
985 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
986 .heapIndex = RADV_MEM_HEAP_VRAM,
987 };
988 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
989 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
990 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
991 .heapIndex = RADV_MEM_HEAP_GTT,
992 };
993 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
994 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
995 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
996 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
997 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
998 };
999 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
1000 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
1001 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
1002 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
1003 .heapIndex = RADV_MEM_HEAP_GTT,
1004 };
1005
1006 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
1007 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
1008 physical_device->rad_info.vram_vis_size);
1009
1010 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
1011 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
1012 .size = physical_device->rad_info.vram_size -
1013 visible_vram_size,
1014 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1015 };
1016 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
1017 .size = visible_vram_size,
1018 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
1019 };
1020 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
1021 .size = physical_device->rad_info.gart_size,
1022 .flags = 0,
1023 };
1024 }
1025
1026 void radv_GetPhysicalDeviceMemoryProperties2KHR(
1027 VkPhysicalDevice physicalDevice,
1028 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1029 {
1030 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1031 &pMemoryProperties->memoryProperties);
1032 }
1033
1034 static int
1035 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1036 int queue_family_index, int idx)
1037 {
1038 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1039 queue->device = device;
1040 queue->queue_family_index = queue_family_index;
1041 queue->queue_idx = idx;
1042
1043 queue->hw_ctx = device->ws->ctx_create(device->ws);
1044 if (!queue->hw_ctx)
1045 return VK_ERROR_OUT_OF_HOST_MEMORY;
1046
1047 return VK_SUCCESS;
1048 }
1049
1050 static void
1051 radv_queue_finish(struct radv_queue *queue)
1052 {
1053 if (queue->hw_ctx)
1054 queue->device->ws->ctx_destroy(queue->hw_ctx);
1055
1056 if (queue->initial_full_flush_preamble_cs)
1057 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1058 if (queue->initial_preamble_cs)
1059 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1060 if (queue->continue_preamble_cs)
1061 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1062 if (queue->descriptor_bo)
1063 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1064 if (queue->scratch_bo)
1065 queue->device->ws->buffer_destroy(queue->scratch_bo);
1066 if (queue->esgs_ring_bo)
1067 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1068 if (queue->gsvs_ring_bo)
1069 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1070 if (queue->tess_factor_ring_bo)
1071 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1072 if (queue->tess_offchip_ring_bo)
1073 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1074 if (queue->compute_scratch_bo)
1075 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1076 }
1077
1078 static void
1079 radv_device_init_gs_info(struct radv_device *device)
1080 {
1081 switch (device->physical_device->rad_info.family) {
1082 case CHIP_OLAND:
1083 case CHIP_HAINAN:
1084 case CHIP_KAVERI:
1085 case CHIP_KABINI:
1086 case CHIP_MULLINS:
1087 case CHIP_ICELAND:
1088 case CHIP_CARRIZO:
1089 case CHIP_STONEY:
1090 device->gs_table_depth = 16;
1091 return;
1092 case CHIP_TAHITI:
1093 case CHIP_PITCAIRN:
1094 case CHIP_VERDE:
1095 case CHIP_BONAIRE:
1096 case CHIP_HAWAII:
1097 case CHIP_TONGA:
1098 case CHIP_FIJI:
1099 case CHIP_POLARIS10:
1100 case CHIP_POLARIS11:
1101 case CHIP_POLARIS12:
1102 case CHIP_VEGA10:
1103 case CHIP_RAVEN:
1104 device->gs_table_depth = 32;
1105 return;
1106 default:
1107 unreachable("unknown GPU");
1108 }
1109 }
1110
1111 VkResult radv_CreateDevice(
1112 VkPhysicalDevice physicalDevice,
1113 const VkDeviceCreateInfo* pCreateInfo,
1114 const VkAllocationCallbacks* pAllocator,
1115 VkDevice* pDevice)
1116 {
1117 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1118 VkResult result;
1119 struct radv_device *device;
1120
1121 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1122 if (!is_extension_enabled(physical_device->extensions.ext_array,
1123 physical_device->extensions.num_ext,
1124 pCreateInfo->ppEnabledExtensionNames[i]))
1125 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1126 }
1127
1128 /* Check enabled features */
1129 if (pCreateInfo->pEnabledFeatures) {
1130 VkPhysicalDeviceFeatures supported_features;
1131 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1132 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1133 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1134 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1135 for (uint32_t i = 0; i < num_features; i++) {
1136 if (enabled_feature[i] && !supported_feature[i])
1137 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1138 }
1139 }
1140
1141 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1142 sizeof(*device), 8,
1143 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1144 if (!device)
1145 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1146
1147 memset(device, 0, sizeof(*device));
1148
1149 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1150 device->instance = physical_device->instance;
1151 device->physical_device = physical_device;
1152
1153 device->debug_flags = device->instance->debug_flags;
1154
1155 device->ws = physical_device->ws;
1156 if (pAllocator)
1157 device->alloc = *pAllocator;
1158 else
1159 device->alloc = physical_device->instance->alloc;
1160
1161 mtx_init(&device->shader_slab_mutex, mtx_plain);
1162 list_inithead(&device->shader_slabs);
1163
1164 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1165 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1166 uint32_t qfi = queue_create->queueFamilyIndex;
1167
1168 device->queues[qfi] = vk_alloc(&device->alloc,
1169 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1170 if (!device->queues[qfi]) {
1171 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1172 goto fail;
1173 }
1174
1175 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1176
1177 device->queue_count[qfi] = queue_create->queueCount;
1178
1179 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1180 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1181 if (result != VK_SUCCESS)
1182 goto fail;
1183 }
1184 }
1185
1186 #if HAVE_LLVM < 0x0400
1187 device->llvm_supports_spill = false;
1188 #else
1189 device->llvm_supports_spill = true;
1190 #endif
1191
1192 /* The maximum number of scratch waves. Scratch space isn't divided
1193 * evenly between CUs. The number is only a function of the number of CUs.
1194 * We can decrease the constant to decrease the scratch buffer size.
1195 *
1196 * sctx->scratch_waves must be >= the maximum posible size of
1197 * 1 threadgroup, so that the hw doesn't hang from being unable
1198 * to start any.
1199 *
1200 * The recommended value is 4 per CU at most. Higher numbers don't
1201 * bring much benefit, but they still occupy chip resources (think
1202 * async compute). I've seen ~2% performance difference between 4 and 32.
1203 */
1204 uint32_t max_threads_per_block = 2048;
1205 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1206 max_threads_per_block / 64);
1207
1208 radv_device_init_gs_info(device);
1209
1210 device->tess_offchip_block_dw_size =
1211 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1212 device->has_distributed_tess =
1213 device->physical_device->rad_info.chip_class >= VI &&
1214 device->physical_device->rad_info.max_se >= 2;
1215
1216 if (getenv("RADV_TRACE_FILE")) {
1217 if (!radv_init_trace(device))
1218 goto fail;
1219 }
1220
1221 result = radv_device_init_meta(device);
1222 if (result != VK_SUCCESS)
1223 goto fail;
1224
1225 radv_device_init_msaa(device);
1226
1227 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1228 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1229 switch (family) {
1230 case RADV_QUEUE_GENERAL:
1231 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1232 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1233 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1234 break;
1235 case RADV_QUEUE_COMPUTE:
1236 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1237 radeon_emit(device->empty_cs[family], 0);
1238 break;
1239 }
1240 device->ws->cs_finalize(device->empty_cs[family]);
1241 }
1242
1243 if (device->physical_device->rad_info.chip_class >= CIK)
1244 cik_create_gfx_config(device);
1245
1246 VkPipelineCacheCreateInfo ci;
1247 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1248 ci.pNext = NULL;
1249 ci.flags = 0;
1250 ci.pInitialData = NULL;
1251 ci.initialDataSize = 0;
1252 VkPipelineCache pc;
1253 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1254 &ci, NULL, &pc);
1255 if (result != VK_SUCCESS)
1256 goto fail;
1257
1258 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1259
1260 *pDevice = radv_device_to_handle(device);
1261 return VK_SUCCESS;
1262
1263 fail:
1264 if (device->trace_bo)
1265 device->ws->buffer_destroy(device->trace_bo);
1266
1267 if (device->gfx_init)
1268 device->ws->buffer_destroy(device->gfx_init);
1269
1270 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1271 for (unsigned q = 0; q < device->queue_count[i]; q++)
1272 radv_queue_finish(&device->queues[i][q]);
1273 if (device->queue_count[i])
1274 vk_free(&device->alloc, device->queues[i]);
1275 }
1276
1277 vk_free(&device->alloc, device);
1278 return result;
1279 }
1280
1281 void radv_DestroyDevice(
1282 VkDevice _device,
1283 const VkAllocationCallbacks* pAllocator)
1284 {
1285 RADV_FROM_HANDLE(radv_device, device, _device);
1286
1287 if (!device)
1288 return;
1289
1290 if (device->trace_bo)
1291 device->ws->buffer_destroy(device->trace_bo);
1292
1293 if (device->gfx_init)
1294 device->ws->buffer_destroy(device->gfx_init);
1295
1296 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1297 for (unsigned q = 0; q < device->queue_count[i]; q++)
1298 radv_queue_finish(&device->queues[i][q]);
1299 if (device->queue_count[i])
1300 vk_free(&device->alloc, device->queues[i]);
1301 if (device->empty_cs[i])
1302 device->ws->cs_destroy(device->empty_cs[i]);
1303 }
1304 radv_device_finish_meta(device);
1305
1306 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1307 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1308
1309 radv_destroy_shader_slabs(device);
1310
1311 vk_free(&device->alloc, device);
1312 }
1313
1314 VkResult radv_EnumerateInstanceExtensionProperties(
1315 const char* pLayerName,
1316 uint32_t* pPropertyCount,
1317 VkExtensionProperties* pProperties)
1318 {
1319 if (pProperties == NULL) {
1320 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1321 return VK_SUCCESS;
1322 }
1323
1324 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1325 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1326
1327 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1328 return VK_INCOMPLETE;
1329
1330 return VK_SUCCESS;
1331 }
1332
1333 VkResult radv_EnumerateDeviceExtensionProperties(
1334 VkPhysicalDevice physicalDevice,
1335 const char* pLayerName,
1336 uint32_t* pPropertyCount,
1337 VkExtensionProperties* pProperties)
1338 {
1339 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1340
1341 if (pProperties == NULL) {
1342 *pPropertyCount = pdevice->extensions.num_ext;
1343 return VK_SUCCESS;
1344 }
1345
1346 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1347 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1348
1349 if (*pPropertyCount < pdevice->extensions.num_ext)
1350 return VK_INCOMPLETE;
1351
1352 return VK_SUCCESS;
1353 }
1354
1355 VkResult radv_EnumerateInstanceLayerProperties(
1356 uint32_t* pPropertyCount,
1357 VkLayerProperties* pProperties)
1358 {
1359 if (pProperties == NULL) {
1360 *pPropertyCount = 0;
1361 return VK_SUCCESS;
1362 }
1363
1364 /* None supported at this time */
1365 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1366 }
1367
1368 VkResult radv_EnumerateDeviceLayerProperties(
1369 VkPhysicalDevice physicalDevice,
1370 uint32_t* pPropertyCount,
1371 VkLayerProperties* pProperties)
1372 {
1373 if (pProperties == NULL) {
1374 *pPropertyCount = 0;
1375 return VK_SUCCESS;
1376 }
1377
1378 /* None supported at this time */
1379 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1380 }
1381
1382 void radv_GetDeviceQueue(
1383 VkDevice _device,
1384 uint32_t queueFamilyIndex,
1385 uint32_t queueIndex,
1386 VkQueue* pQueue)
1387 {
1388 RADV_FROM_HANDLE(radv_device, device, _device);
1389
1390 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1391 }
1392
1393 static void
1394 fill_geom_tess_rings(struct radv_queue *queue,
1395 uint32_t *map,
1396 bool add_sample_positions,
1397 uint32_t esgs_ring_size,
1398 struct radeon_winsys_bo *esgs_ring_bo,
1399 uint32_t gsvs_ring_size,
1400 struct radeon_winsys_bo *gsvs_ring_bo,
1401 uint32_t tess_factor_ring_size,
1402 struct radeon_winsys_bo *tess_factor_ring_bo,
1403 uint32_t tess_offchip_ring_size,
1404 struct radeon_winsys_bo *tess_offchip_ring_bo)
1405 {
1406 uint64_t esgs_va = 0, gsvs_va = 0;
1407 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1408 uint32_t *desc = &map[4];
1409
1410 if (esgs_ring_bo)
1411 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1412 if (gsvs_ring_bo)
1413 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1414 if (tess_factor_ring_bo)
1415 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1416 if (tess_offchip_ring_bo)
1417 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1418
1419 /* stride 0, num records - size, add tid, swizzle, elsize4,
1420 index stride 64 */
1421 desc[0] = esgs_va;
1422 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1423 S_008F04_STRIDE(0) |
1424 S_008F04_SWIZZLE_ENABLE(true);
1425 desc[2] = esgs_ring_size;
1426 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1427 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1428 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1429 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1430 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1431 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1432 S_008F0C_ELEMENT_SIZE(1) |
1433 S_008F0C_INDEX_STRIDE(3) |
1434 S_008F0C_ADD_TID_ENABLE(true);
1435
1436 desc += 4;
1437 /* GS entry for ES->GS ring */
1438 /* stride 0, num records - size, elsize0,
1439 index stride 0 */
1440 desc[0] = esgs_va;
1441 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1442 S_008F04_STRIDE(0) |
1443 S_008F04_SWIZZLE_ENABLE(false);
1444 desc[2] = esgs_ring_size;
1445 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1446 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1447 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1448 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1449 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1450 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1451 S_008F0C_ELEMENT_SIZE(0) |
1452 S_008F0C_INDEX_STRIDE(0) |
1453 S_008F0C_ADD_TID_ENABLE(false);
1454
1455 desc += 4;
1456 /* VS entry for GS->VS ring */
1457 /* stride 0, num records - size, elsize0,
1458 index stride 0 */
1459 desc[0] = gsvs_va;
1460 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1461 S_008F04_STRIDE(0) |
1462 S_008F04_SWIZZLE_ENABLE(false);
1463 desc[2] = gsvs_ring_size;
1464 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1468 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1469 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1470 S_008F0C_ELEMENT_SIZE(0) |
1471 S_008F0C_INDEX_STRIDE(0) |
1472 S_008F0C_ADD_TID_ENABLE(false);
1473 desc += 4;
1474
1475 /* stride gsvs_itemsize, num records 64
1476 elsize 4, index stride 16 */
1477 /* shader will patch stride and desc[2] */
1478 desc[0] = gsvs_va;
1479 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1480 S_008F04_STRIDE(0) |
1481 S_008F04_SWIZZLE_ENABLE(true);
1482 desc[2] = 0;
1483 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1484 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1485 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1486 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1487 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1488 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1489 S_008F0C_ELEMENT_SIZE(1) |
1490 S_008F0C_INDEX_STRIDE(1) |
1491 S_008F0C_ADD_TID_ENABLE(true);
1492 desc += 4;
1493
1494 desc[0] = tess_factor_va;
1495 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1496 S_008F04_STRIDE(0) |
1497 S_008F04_SWIZZLE_ENABLE(false);
1498 desc[2] = tess_factor_ring_size;
1499 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1500 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1501 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1502 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1503 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1504 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1505 S_008F0C_ELEMENT_SIZE(0) |
1506 S_008F0C_INDEX_STRIDE(0) |
1507 S_008F0C_ADD_TID_ENABLE(false);
1508 desc += 4;
1509
1510 desc[0] = tess_offchip_va;
1511 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1512 S_008F04_STRIDE(0) |
1513 S_008F04_SWIZZLE_ENABLE(false);
1514 desc[2] = tess_offchip_ring_size;
1515 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1516 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1517 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1518 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1519 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1520 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1521 S_008F0C_ELEMENT_SIZE(0) |
1522 S_008F0C_INDEX_STRIDE(0) |
1523 S_008F0C_ADD_TID_ENABLE(false);
1524 desc += 4;
1525
1526 /* add sample positions after all rings */
1527 memcpy(desc, queue->device->sample_locations_1x, 8);
1528 desc += 2;
1529 memcpy(desc, queue->device->sample_locations_2x, 16);
1530 desc += 4;
1531 memcpy(desc, queue->device->sample_locations_4x, 32);
1532 desc += 8;
1533 memcpy(desc, queue->device->sample_locations_8x, 64);
1534 desc += 16;
1535 memcpy(desc, queue->device->sample_locations_16x, 128);
1536 }
1537
1538 static unsigned
1539 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1540 {
1541 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1542 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1543 device->physical_device->rad_info.family != CHIP_STONEY;
1544 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1545 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1546 device->physical_device->rad_info.max_se;
1547 unsigned offchip_granularity;
1548 unsigned hs_offchip_param;
1549 switch (device->tess_offchip_block_dw_size) {
1550 default:
1551 assert(0);
1552 /* fall through */
1553 case 8192:
1554 offchip_granularity = V_03093C_X_8K_DWORDS;
1555 break;
1556 case 4096:
1557 offchip_granularity = V_03093C_X_4K_DWORDS;
1558 break;
1559 }
1560
1561 switch (device->physical_device->rad_info.chip_class) {
1562 case SI:
1563 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1564 break;
1565 case CIK:
1566 case VI:
1567 case GFX9:
1568 default:
1569 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1570 break;
1571 }
1572
1573 *max_offchip_buffers_p = max_offchip_buffers;
1574 if (device->physical_device->rad_info.chip_class >= CIK) {
1575 if (device->physical_device->rad_info.chip_class >= VI)
1576 --max_offchip_buffers;
1577 hs_offchip_param =
1578 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1579 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1580 } else {
1581 hs_offchip_param =
1582 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1583 }
1584 return hs_offchip_param;
1585 }
1586
1587 static VkResult
1588 radv_get_preamble_cs(struct radv_queue *queue,
1589 uint32_t scratch_size,
1590 uint32_t compute_scratch_size,
1591 uint32_t esgs_ring_size,
1592 uint32_t gsvs_ring_size,
1593 bool needs_tess_rings,
1594 bool needs_sample_positions,
1595 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1596 struct radeon_winsys_cs **initial_preamble_cs,
1597 struct radeon_winsys_cs **continue_preamble_cs)
1598 {
1599 struct radeon_winsys_bo *scratch_bo = NULL;
1600 struct radeon_winsys_bo *descriptor_bo = NULL;
1601 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1602 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1603 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1604 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1605 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1606 struct radeon_winsys_cs *dest_cs[3] = {0};
1607 bool add_tess_rings = false, add_sample_positions = false;
1608 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1609 unsigned max_offchip_buffers;
1610 unsigned hs_offchip_param = 0;
1611 if (!queue->has_tess_rings) {
1612 if (needs_tess_rings)
1613 add_tess_rings = true;
1614 }
1615 if (!queue->has_sample_positions) {
1616 if (needs_sample_positions)
1617 add_sample_positions = true;
1618 }
1619 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1620 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1621 &max_offchip_buffers);
1622 tess_offchip_ring_size = max_offchip_buffers *
1623 queue->device->tess_offchip_block_dw_size * 4;
1624
1625 if (scratch_size <= queue->scratch_size &&
1626 compute_scratch_size <= queue->compute_scratch_size &&
1627 esgs_ring_size <= queue->esgs_ring_size &&
1628 gsvs_ring_size <= queue->gsvs_ring_size &&
1629 !add_tess_rings && !add_sample_positions &&
1630 queue->initial_preamble_cs) {
1631 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1632 *initial_preamble_cs = queue->initial_preamble_cs;
1633 *continue_preamble_cs = queue->continue_preamble_cs;
1634 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1635 *continue_preamble_cs = NULL;
1636 return VK_SUCCESS;
1637 }
1638
1639 if (scratch_size > queue->scratch_size) {
1640 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1641 scratch_size,
1642 4096,
1643 RADEON_DOMAIN_VRAM,
1644 RADEON_FLAG_NO_CPU_ACCESS);
1645 if (!scratch_bo)
1646 goto fail;
1647 } else
1648 scratch_bo = queue->scratch_bo;
1649
1650 if (compute_scratch_size > queue->compute_scratch_size) {
1651 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1652 compute_scratch_size,
1653 4096,
1654 RADEON_DOMAIN_VRAM,
1655 RADEON_FLAG_NO_CPU_ACCESS);
1656 if (!compute_scratch_bo)
1657 goto fail;
1658
1659 } else
1660 compute_scratch_bo = queue->compute_scratch_bo;
1661
1662 if (esgs_ring_size > queue->esgs_ring_size) {
1663 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1664 esgs_ring_size,
1665 4096,
1666 RADEON_DOMAIN_VRAM,
1667 RADEON_FLAG_NO_CPU_ACCESS);
1668 if (!esgs_ring_bo)
1669 goto fail;
1670 } else {
1671 esgs_ring_bo = queue->esgs_ring_bo;
1672 esgs_ring_size = queue->esgs_ring_size;
1673 }
1674
1675 if (gsvs_ring_size > queue->gsvs_ring_size) {
1676 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1677 gsvs_ring_size,
1678 4096,
1679 RADEON_DOMAIN_VRAM,
1680 RADEON_FLAG_NO_CPU_ACCESS);
1681 if (!gsvs_ring_bo)
1682 goto fail;
1683 } else {
1684 gsvs_ring_bo = queue->gsvs_ring_bo;
1685 gsvs_ring_size = queue->gsvs_ring_size;
1686 }
1687
1688 if (add_tess_rings) {
1689 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1690 tess_factor_ring_size,
1691 256,
1692 RADEON_DOMAIN_VRAM,
1693 RADEON_FLAG_NO_CPU_ACCESS);
1694 if (!tess_factor_ring_bo)
1695 goto fail;
1696 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1697 tess_offchip_ring_size,
1698 256,
1699 RADEON_DOMAIN_VRAM,
1700 RADEON_FLAG_NO_CPU_ACCESS);
1701 if (!tess_offchip_ring_bo)
1702 goto fail;
1703 } else {
1704 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1705 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1706 }
1707
1708 if (scratch_bo != queue->scratch_bo ||
1709 esgs_ring_bo != queue->esgs_ring_bo ||
1710 gsvs_ring_bo != queue->gsvs_ring_bo ||
1711 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1712 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1713 uint32_t size = 0;
1714 if (gsvs_ring_bo || esgs_ring_bo ||
1715 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1716 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1717 if (add_sample_positions)
1718 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1719 }
1720 else if (scratch_bo)
1721 size = 8; /* 2 dword */
1722
1723 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1724 size,
1725 4096,
1726 RADEON_DOMAIN_VRAM,
1727 RADEON_FLAG_CPU_ACCESS);
1728 if (!descriptor_bo)
1729 goto fail;
1730 } else
1731 descriptor_bo = queue->descriptor_bo;
1732
1733 for(int i = 0; i < 3; ++i) {
1734 struct radeon_winsys_cs *cs = NULL;
1735 cs = queue->device->ws->cs_create(queue->device->ws,
1736 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1737 if (!cs)
1738 goto fail;
1739
1740 dest_cs[i] = cs;
1741
1742 if (scratch_bo)
1743 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1744
1745 if (esgs_ring_bo)
1746 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1747
1748 if (gsvs_ring_bo)
1749 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1750
1751 if (tess_factor_ring_bo)
1752 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1753
1754 if (tess_offchip_ring_bo)
1755 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1756
1757 if (descriptor_bo)
1758 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1759
1760 if (descriptor_bo != queue->descriptor_bo) {
1761 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1762
1763 if (scratch_bo) {
1764 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1765 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1766 S_008F04_SWIZZLE_ENABLE(1);
1767 map[0] = scratch_va;
1768 map[1] = rsrc1;
1769 }
1770
1771 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1772 add_sample_positions)
1773 fill_geom_tess_rings(queue, map, add_sample_positions,
1774 esgs_ring_size, esgs_ring_bo,
1775 gsvs_ring_size, gsvs_ring_bo,
1776 tess_factor_ring_size, tess_factor_ring_bo,
1777 tess_offchip_ring_size, tess_offchip_ring_bo);
1778
1779 queue->device->ws->buffer_unmap(descriptor_bo);
1780 }
1781
1782 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1783 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1784 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1785 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1786 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1787 }
1788
1789 if (esgs_ring_bo || gsvs_ring_bo) {
1790 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1791 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1792 radeon_emit(cs, esgs_ring_size >> 8);
1793 radeon_emit(cs, gsvs_ring_size >> 8);
1794 } else {
1795 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1796 radeon_emit(cs, esgs_ring_size >> 8);
1797 radeon_emit(cs, gsvs_ring_size >> 8);
1798 }
1799 }
1800
1801 if (tess_factor_ring_bo) {
1802 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1803 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1804 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1805 S_030938_SIZE(tess_factor_ring_size / 4));
1806 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1807 tf_va >> 8);
1808 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1809 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1810 tf_va >> 40);
1811 }
1812 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1813 } else {
1814 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1815 S_008988_SIZE(tess_factor_ring_size / 4));
1816 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1817 tf_va >> 8);
1818 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1819 hs_offchip_param);
1820 }
1821 }
1822
1823 if (descriptor_bo) {
1824 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1825 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1826 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1827 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1828 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1829 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1830
1831 uint64_t va = radv_buffer_get_va(descriptor_bo);
1832
1833 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1834 radeon_set_sh_reg_seq(cs, regs[i], 2);
1835 radeon_emit(cs, va);
1836 radeon_emit(cs, va >> 32);
1837 }
1838 }
1839
1840 if (compute_scratch_bo) {
1841 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1842 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1843 S_008F04_SWIZZLE_ENABLE(1);
1844
1845 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1846
1847 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1848 radeon_emit(cs, scratch_va);
1849 radeon_emit(cs, rsrc1);
1850 }
1851
1852 if (i == 0) {
1853 si_cs_emit_cache_flush(cs,
1854 false,
1855 queue->device->physical_device->rad_info.chip_class,
1856 NULL, 0,
1857 queue->queue_family_index == RING_COMPUTE &&
1858 queue->device->physical_device->rad_info.chip_class >= CIK,
1859 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1860 RADV_CMD_FLAG_INV_ICACHE |
1861 RADV_CMD_FLAG_INV_SMEM_L1 |
1862 RADV_CMD_FLAG_INV_VMEM_L1 |
1863 RADV_CMD_FLAG_INV_GLOBAL_L2);
1864 } else if (i == 1) {
1865 si_cs_emit_cache_flush(cs,
1866 false,
1867 queue->device->physical_device->rad_info.chip_class,
1868 NULL, 0,
1869 queue->queue_family_index == RING_COMPUTE &&
1870 queue->device->physical_device->rad_info.chip_class >= CIK,
1871 RADV_CMD_FLAG_INV_ICACHE |
1872 RADV_CMD_FLAG_INV_SMEM_L1 |
1873 RADV_CMD_FLAG_INV_VMEM_L1 |
1874 RADV_CMD_FLAG_INV_GLOBAL_L2);
1875 }
1876
1877 if (!queue->device->ws->cs_finalize(cs))
1878 goto fail;
1879 }
1880
1881 if (queue->initial_full_flush_preamble_cs)
1882 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1883
1884 if (queue->initial_preamble_cs)
1885 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1886
1887 if (queue->continue_preamble_cs)
1888 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1889
1890 queue->initial_full_flush_preamble_cs = dest_cs[0];
1891 queue->initial_preamble_cs = dest_cs[1];
1892 queue->continue_preamble_cs = dest_cs[2];
1893
1894 if (scratch_bo != queue->scratch_bo) {
1895 if (queue->scratch_bo)
1896 queue->device->ws->buffer_destroy(queue->scratch_bo);
1897 queue->scratch_bo = scratch_bo;
1898 queue->scratch_size = scratch_size;
1899 }
1900
1901 if (compute_scratch_bo != queue->compute_scratch_bo) {
1902 if (queue->compute_scratch_bo)
1903 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1904 queue->compute_scratch_bo = compute_scratch_bo;
1905 queue->compute_scratch_size = compute_scratch_size;
1906 }
1907
1908 if (esgs_ring_bo != queue->esgs_ring_bo) {
1909 if (queue->esgs_ring_bo)
1910 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1911 queue->esgs_ring_bo = esgs_ring_bo;
1912 queue->esgs_ring_size = esgs_ring_size;
1913 }
1914
1915 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1916 if (queue->gsvs_ring_bo)
1917 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1918 queue->gsvs_ring_bo = gsvs_ring_bo;
1919 queue->gsvs_ring_size = gsvs_ring_size;
1920 }
1921
1922 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1923 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1924 }
1925
1926 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1927 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1928 queue->has_tess_rings = true;
1929 }
1930
1931 if (descriptor_bo != queue->descriptor_bo) {
1932 if (queue->descriptor_bo)
1933 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1934
1935 queue->descriptor_bo = descriptor_bo;
1936 }
1937
1938 if (add_sample_positions)
1939 queue->has_sample_positions = true;
1940
1941 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1942 *initial_preamble_cs = queue->initial_preamble_cs;
1943 *continue_preamble_cs = queue->continue_preamble_cs;
1944 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1945 *continue_preamble_cs = NULL;
1946 return VK_SUCCESS;
1947 fail:
1948 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1949 if (dest_cs[i])
1950 queue->device->ws->cs_destroy(dest_cs[i]);
1951 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1952 queue->device->ws->buffer_destroy(descriptor_bo);
1953 if (scratch_bo && scratch_bo != queue->scratch_bo)
1954 queue->device->ws->buffer_destroy(scratch_bo);
1955 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1956 queue->device->ws->buffer_destroy(compute_scratch_bo);
1957 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1958 queue->device->ws->buffer_destroy(esgs_ring_bo);
1959 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1960 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1961 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1962 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1963 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1964 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1965 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1966 }
1967
1968 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1969 int num_sems,
1970 const VkSemaphore *sems,
1971 bool reset_temp)
1972 {
1973 int syncobj_idx = 0, sem_idx = 0;
1974
1975 if (num_sems == 0)
1976 return VK_SUCCESS;
1977 for (uint32_t i = 0; i < num_sems; i++) {
1978 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1979
1980 if (sem->temp_syncobj || sem->syncobj)
1981 counts->syncobj_count++;
1982 else
1983 counts->sem_count++;
1984 }
1985
1986 if (counts->syncobj_count) {
1987 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1988 if (!counts->syncobj)
1989 return VK_ERROR_OUT_OF_HOST_MEMORY;
1990 }
1991
1992 if (counts->sem_count) {
1993 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1994 if (!counts->sem) {
1995 free(counts->syncobj);
1996 return VK_ERROR_OUT_OF_HOST_MEMORY;
1997 }
1998 }
1999
2000 for (uint32_t i = 0; i < num_sems; i++) {
2001 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2002
2003 if (sem->temp_syncobj) {
2004 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2005 if (reset_temp) {
2006 /* after we wait on a temp import - drop it */
2007 sem->temp_syncobj = 0;
2008 }
2009 }
2010 else if (sem->syncobj)
2011 counts->syncobj[syncobj_idx++] = sem->syncobj;
2012 else {
2013 assert(sem->sem);
2014 counts->sem[sem_idx++] = sem->sem;
2015 }
2016 }
2017
2018 return VK_SUCCESS;
2019 }
2020
2021 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2022 {
2023 free(sem_info->wait.syncobj);
2024 free(sem_info->wait.sem);
2025 free(sem_info->signal.syncobj);
2026 free(sem_info->signal.sem);
2027 }
2028
2029 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2030 int num_wait_sems,
2031 const VkSemaphore *wait_sems,
2032 int num_signal_sems,
2033 const VkSemaphore *signal_sems)
2034 {
2035 VkResult ret;
2036 memset(sem_info, 0, sizeof(*sem_info));
2037
2038 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2039 if (ret)
2040 return ret;
2041 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2042 if (ret)
2043 radv_free_sem_info(sem_info);
2044
2045 /* caller can override these */
2046 sem_info->cs_emit_wait = true;
2047 sem_info->cs_emit_signal = true;
2048 return ret;
2049 }
2050
2051 VkResult radv_QueueSubmit(
2052 VkQueue _queue,
2053 uint32_t submitCount,
2054 const VkSubmitInfo* pSubmits,
2055 VkFence _fence)
2056 {
2057 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2058 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2059 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2060 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2061 int ret;
2062 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2063 uint32_t scratch_size = 0;
2064 uint32_t compute_scratch_size = 0;
2065 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2066 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2067 VkResult result;
2068 bool fence_emitted = false;
2069 bool tess_rings_needed = false;
2070 bool sample_positions_needed = false;
2071
2072 /* Do this first so failing to allocate scratch buffers can't result in
2073 * partially executed submissions. */
2074 for (uint32_t i = 0; i < submitCount; i++) {
2075 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2076 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2077 pSubmits[i].pCommandBuffers[j]);
2078
2079 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2080 compute_scratch_size = MAX2(compute_scratch_size,
2081 cmd_buffer->compute_scratch_size_needed);
2082 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2083 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2084 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2085 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2086 }
2087 }
2088
2089 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2090 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2091 sample_positions_needed, &initial_flush_preamble_cs,
2092 &initial_preamble_cs, &continue_preamble_cs);
2093 if (result != VK_SUCCESS)
2094 return result;
2095
2096 for (uint32_t i = 0; i < submitCount; i++) {
2097 struct radeon_winsys_cs **cs_array;
2098 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2099 bool can_patch = true;
2100 uint32_t advance;
2101 struct radv_winsys_sem_info sem_info;
2102
2103 result = radv_alloc_sem_info(&sem_info,
2104 pSubmits[i].waitSemaphoreCount,
2105 pSubmits[i].pWaitSemaphores,
2106 pSubmits[i].signalSemaphoreCount,
2107 pSubmits[i].pSignalSemaphores);
2108 if (result != VK_SUCCESS)
2109 return result;
2110
2111 if (!pSubmits[i].commandBufferCount) {
2112 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2113 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2114 &queue->device->empty_cs[queue->queue_family_index],
2115 1, NULL, NULL,
2116 &sem_info,
2117 false, base_fence);
2118 if (ret) {
2119 radv_loge("failed to submit CS %d\n", i);
2120 abort();
2121 }
2122 fence_emitted = true;
2123 }
2124 radv_free_sem_info(&sem_info);
2125 continue;
2126 }
2127
2128 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2129 (pSubmits[i].commandBufferCount));
2130
2131 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2132 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2133 pSubmits[i].pCommandBuffers[j]);
2134 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2135
2136 cs_array[j] = cmd_buffer->cs;
2137 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2138 can_patch = false;
2139 }
2140
2141 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2142 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2143 advance = MIN2(max_cs_submission,
2144 pSubmits[i].commandBufferCount - j);
2145
2146 if (queue->device->trace_bo)
2147 *queue->device->trace_id_ptr = 0;
2148
2149 sem_info.cs_emit_wait = j == 0;
2150 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2151
2152 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2153 advance, initial_preamble, continue_preamble_cs,
2154 &sem_info,
2155 can_patch, base_fence);
2156
2157 if (ret) {
2158 radv_loge("failed to submit CS %d\n", i);
2159 abort();
2160 }
2161 fence_emitted = true;
2162 if (queue->device->trace_bo) {
2163 radv_check_gpu_hangs(queue, cs_array[j]);
2164 }
2165 }
2166
2167 radv_free_sem_info(&sem_info);
2168 free(cs_array);
2169 }
2170
2171 if (fence) {
2172 if (!fence_emitted) {
2173 struct radv_winsys_sem_info sem_info = {0};
2174 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2175 &queue->device->empty_cs[queue->queue_family_index],
2176 1, NULL, NULL, &sem_info,
2177 false, base_fence);
2178 }
2179 fence->submitted = true;
2180 }
2181
2182 return VK_SUCCESS;
2183 }
2184
2185 VkResult radv_QueueWaitIdle(
2186 VkQueue _queue)
2187 {
2188 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2189
2190 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2191 radv_queue_family_to_ring(queue->queue_family_index),
2192 queue->queue_idx);
2193 return VK_SUCCESS;
2194 }
2195
2196 VkResult radv_DeviceWaitIdle(
2197 VkDevice _device)
2198 {
2199 RADV_FROM_HANDLE(radv_device, device, _device);
2200
2201 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2202 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2203 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2204 }
2205 }
2206 return VK_SUCCESS;
2207 }
2208
2209 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2210 VkInstance instance,
2211 const char* pName)
2212 {
2213 return radv_lookup_entrypoint(pName);
2214 }
2215
2216 /* The loader wants us to expose a second GetInstanceProcAddr function
2217 * to work around certain LD_PRELOAD issues seen in apps.
2218 */
2219 PUBLIC
2220 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2221 VkInstance instance,
2222 const char* pName);
2223
2224 PUBLIC
2225 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2226 VkInstance instance,
2227 const char* pName)
2228 {
2229 return radv_GetInstanceProcAddr(instance, pName);
2230 }
2231
2232 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2233 VkDevice device,
2234 const char* pName)
2235 {
2236 return radv_lookup_entrypoint(pName);
2237 }
2238
2239 bool radv_get_memory_fd(struct radv_device *device,
2240 struct radv_device_memory *memory,
2241 int *pFD)
2242 {
2243 struct radeon_bo_metadata metadata;
2244
2245 if (memory->image) {
2246 radv_init_metadata(device, memory->image, &metadata);
2247 device->ws->buffer_set_metadata(memory->bo, &metadata);
2248 }
2249
2250 return device->ws->buffer_get_fd(device->ws, memory->bo,
2251 pFD);
2252 }
2253
2254 VkResult radv_AllocateMemory(
2255 VkDevice _device,
2256 const VkMemoryAllocateInfo* pAllocateInfo,
2257 const VkAllocationCallbacks* pAllocator,
2258 VkDeviceMemory* pMem)
2259 {
2260 RADV_FROM_HANDLE(radv_device, device, _device);
2261 struct radv_device_memory *mem;
2262 VkResult result;
2263 enum radeon_bo_domain domain;
2264 uint32_t flags = 0;
2265
2266 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2267
2268 if (pAllocateInfo->allocationSize == 0) {
2269 /* Apparently, this is allowed */
2270 *pMem = VK_NULL_HANDLE;
2271 return VK_SUCCESS;
2272 }
2273
2274 const VkImportMemoryFdInfoKHR *import_info =
2275 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2276 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2277 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2278
2279 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2280 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2281 if (mem == NULL)
2282 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2283
2284 if (dedicate_info) {
2285 mem->image = radv_image_from_handle(dedicate_info->image);
2286 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2287 } else {
2288 mem->image = NULL;
2289 mem->buffer = NULL;
2290 }
2291
2292 if (import_info) {
2293 assert(import_info->handleType ==
2294 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2295 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2296 NULL, NULL);
2297 if (!mem->bo) {
2298 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2299 goto fail;
2300 } else {
2301 close(import_info->fd);
2302 goto out_success;
2303 }
2304 }
2305
2306 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2307 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2308 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2309 domain = RADEON_DOMAIN_GTT;
2310 else
2311 domain = RADEON_DOMAIN_VRAM;
2312
2313 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2314 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2315 else
2316 flags |= RADEON_FLAG_CPU_ACCESS;
2317
2318 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2319 flags |= RADEON_FLAG_GTT_WC;
2320
2321 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2322 domain, flags);
2323
2324 if (!mem->bo) {
2325 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2326 goto fail;
2327 }
2328 mem->type_index = pAllocateInfo->memoryTypeIndex;
2329 out_success:
2330 *pMem = radv_device_memory_to_handle(mem);
2331
2332 return VK_SUCCESS;
2333
2334 fail:
2335 vk_free2(&device->alloc, pAllocator, mem);
2336
2337 return result;
2338 }
2339
2340 void radv_FreeMemory(
2341 VkDevice _device,
2342 VkDeviceMemory _mem,
2343 const VkAllocationCallbacks* pAllocator)
2344 {
2345 RADV_FROM_HANDLE(radv_device, device, _device);
2346 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2347
2348 if (mem == NULL)
2349 return;
2350
2351 device->ws->buffer_destroy(mem->bo);
2352 mem->bo = NULL;
2353
2354 vk_free2(&device->alloc, pAllocator, mem);
2355 }
2356
2357 VkResult radv_MapMemory(
2358 VkDevice _device,
2359 VkDeviceMemory _memory,
2360 VkDeviceSize offset,
2361 VkDeviceSize size,
2362 VkMemoryMapFlags flags,
2363 void** ppData)
2364 {
2365 RADV_FROM_HANDLE(radv_device, device, _device);
2366 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2367
2368 if (mem == NULL) {
2369 *ppData = NULL;
2370 return VK_SUCCESS;
2371 }
2372
2373 *ppData = device->ws->buffer_map(mem->bo);
2374 if (*ppData) {
2375 *ppData += offset;
2376 return VK_SUCCESS;
2377 }
2378
2379 return VK_ERROR_MEMORY_MAP_FAILED;
2380 }
2381
2382 void radv_UnmapMemory(
2383 VkDevice _device,
2384 VkDeviceMemory _memory)
2385 {
2386 RADV_FROM_HANDLE(radv_device, device, _device);
2387 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2388
2389 if (mem == NULL)
2390 return;
2391
2392 device->ws->buffer_unmap(mem->bo);
2393 }
2394
2395 VkResult radv_FlushMappedMemoryRanges(
2396 VkDevice _device,
2397 uint32_t memoryRangeCount,
2398 const VkMappedMemoryRange* pMemoryRanges)
2399 {
2400 return VK_SUCCESS;
2401 }
2402
2403 VkResult radv_InvalidateMappedMemoryRanges(
2404 VkDevice _device,
2405 uint32_t memoryRangeCount,
2406 const VkMappedMemoryRange* pMemoryRanges)
2407 {
2408 return VK_SUCCESS;
2409 }
2410
2411 void radv_GetBufferMemoryRequirements(
2412 VkDevice device,
2413 VkBuffer _buffer,
2414 VkMemoryRequirements* pMemoryRequirements)
2415 {
2416 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2417
2418 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2419
2420 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2421 pMemoryRequirements->alignment = 4096;
2422 else
2423 pMemoryRequirements->alignment = 16;
2424
2425 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2426 }
2427
2428 void radv_GetBufferMemoryRequirements2KHR(
2429 VkDevice device,
2430 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2431 VkMemoryRequirements2KHR* pMemoryRequirements)
2432 {
2433 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2434 &pMemoryRequirements->memoryRequirements);
2435
2436 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2437 switch (ext->sType) {
2438 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2439 VkMemoryDedicatedRequirementsKHR *req =
2440 (VkMemoryDedicatedRequirementsKHR *) ext;
2441 req->requiresDedicatedAllocation = false;
2442 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2443 break;
2444 }
2445 default:
2446 break;
2447 }
2448 }
2449 }
2450
2451 void radv_GetImageMemoryRequirements(
2452 VkDevice device,
2453 VkImage _image,
2454 VkMemoryRequirements* pMemoryRequirements)
2455 {
2456 RADV_FROM_HANDLE(radv_image, image, _image);
2457
2458 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2459
2460 pMemoryRequirements->size = image->size;
2461 pMemoryRequirements->alignment = image->alignment;
2462 }
2463
2464 void radv_GetImageMemoryRequirements2KHR(
2465 VkDevice device,
2466 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2467 VkMemoryRequirements2KHR* pMemoryRequirements)
2468 {
2469 radv_GetImageMemoryRequirements(device, pInfo->image,
2470 &pMemoryRequirements->memoryRequirements);
2471
2472 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2473
2474 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2475 switch (ext->sType) {
2476 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2477 VkMemoryDedicatedRequirementsKHR *req =
2478 (VkMemoryDedicatedRequirementsKHR *) ext;
2479 req->requiresDedicatedAllocation = image->shareable;
2480 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2481 break;
2482 }
2483 default:
2484 break;
2485 }
2486 }
2487 }
2488
2489 void radv_GetImageSparseMemoryRequirements(
2490 VkDevice device,
2491 VkImage image,
2492 uint32_t* pSparseMemoryRequirementCount,
2493 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2494 {
2495 stub();
2496 }
2497
2498 void radv_GetImageSparseMemoryRequirements2KHR(
2499 VkDevice device,
2500 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2501 uint32_t* pSparseMemoryRequirementCount,
2502 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2503 {
2504 stub();
2505 }
2506
2507 void radv_GetDeviceMemoryCommitment(
2508 VkDevice device,
2509 VkDeviceMemory memory,
2510 VkDeviceSize* pCommittedMemoryInBytes)
2511 {
2512 *pCommittedMemoryInBytes = 0;
2513 }
2514
2515 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2516 uint32_t bindInfoCount,
2517 const VkBindBufferMemoryInfoKHR *pBindInfos)
2518 {
2519 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2520 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2521 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2522
2523 if (mem) {
2524 buffer->bo = mem->bo;
2525 buffer->offset = pBindInfos[i].memoryOffset;
2526 } else {
2527 buffer->bo = NULL;
2528 }
2529 }
2530 return VK_SUCCESS;
2531 }
2532
2533 VkResult radv_BindBufferMemory(
2534 VkDevice device,
2535 VkBuffer buffer,
2536 VkDeviceMemory memory,
2537 VkDeviceSize memoryOffset)
2538 {
2539 const VkBindBufferMemoryInfoKHR info = {
2540 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2541 .buffer = buffer,
2542 .memory = memory,
2543 .memoryOffset = memoryOffset
2544 };
2545
2546 return radv_BindBufferMemory2KHR(device, 1, &info);
2547 }
2548
2549 VkResult radv_BindImageMemory2KHR(VkDevice device,
2550 uint32_t bindInfoCount,
2551 const VkBindImageMemoryInfoKHR *pBindInfos)
2552 {
2553 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2554 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2555 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2556
2557 if (mem) {
2558 image->bo = mem->bo;
2559 image->offset = pBindInfos[i].memoryOffset;
2560 } else {
2561 image->bo = NULL;
2562 image->offset = 0;
2563 }
2564 }
2565 return VK_SUCCESS;
2566 }
2567
2568
2569 VkResult radv_BindImageMemory(
2570 VkDevice device,
2571 VkImage image,
2572 VkDeviceMemory memory,
2573 VkDeviceSize memoryOffset)
2574 {
2575 const VkBindImageMemoryInfoKHR info = {
2576 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2577 .image = image,
2578 .memory = memory,
2579 .memoryOffset = memoryOffset
2580 };
2581
2582 return radv_BindImageMemory2KHR(device, 1, &info);
2583 }
2584
2585
2586 static void
2587 radv_sparse_buffer_bind_memory(struct radv_device *device,
2588 const VkSparseBufferMemoryBindInfo *bind)
2589 {
2590 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2591
2592 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2593 struct radv_device_memory *mem = NULL;
2594
2595 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2596 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2597
2598 device->ws->buffer_virtual_bind(buffer->bo,
2599 bind->pBinds[i].resourceOffset,
2600 bind->pBinds[i].size,
2601 mem ? mem->bo : NULL,
2602 bind->pBinds[i].memoryOffset);
2603 }
2604 }
2605
2606 static void
2607 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2608 const VkSparseImageOpaqueMemoryBindInfo *bind)
2609 {
2610 RADV_FROM_HANDLE(radv_image, image, bind->image);
2611
2612 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2613 struct radv_device_memory *mem = NULL;
2614
2615 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2616 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2617
2618 device->ws->buffer_virtual_bind(image->bo,
2619 bind->pBinds[i].resourceOffset,
2620 bind->pBinds[i].size,
2621 mem ? mem->bo : NULL,
2622 bind->pBinds[i].memoryOffset);
2623 }
2624 }
2625
2626 VkResult radv_QueueBindSparse(
2627 VkQueue _queue,
2628 uint32_t bindInfoCount,
2629 const VkBindSparseInfo* pBindInfo,
2630 VkFence _fence)
2631 {
2632 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2633 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2634 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2635 bool fence_emitted = false;
2636
2637 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2638 struct radv_winsys_sem_info sem_info;
2639 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2640 radv_sparse_buffer_bind_memory(queue->device,
2641 pBindInfo[i].pBufferBinds + j);
2642 }
2643
2644 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2645 radv_sparse_image_opaque_bind_memory(queue->device,
2646 pBindInfo[i].pImageOpaqueBinds + j);
2647 }
2648
2649 VkResult result;
2650 result = radv_alloc_sem_info(&sem_info,
2651 pBindInfo[i].waitSemaphoreCount,
2652 pBindInfo[i].pWaitSemaphores,
2653 pBindInfo[i].signalSemaphoreCount,
2654 pBindInfo[i].pSignalSemaphores);
2655 if (result != VK_SUCCESS)
2656 return result;
2657
2658 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2659 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2660 &queue->device->empty_cs[queue->queue_family_index],
2661 1, NULL, NULL,
2662 &sem_info,
2663 false, base_fence);
2664 fence_emitted = true;
2665 if (fence)
2666 fence->submitted = true;
2667 }
2668
2669 radv_free_sem_info(&sem_info);
2670
2671 }
2672
2673 if (fence && !fence_emitted) {
2674 fence->signalled = true;
2675 }
2676
2677 return VK_SUCCESS;
2678 }
2679
2680 VkResult radv_CreateFence(
2681 VkDevice _device,
2682 const VkFenceCreateInfo* pCreateInfo,
2683 const VkAllocationCallbacks* pAllocator,
2684 VkFence* pFence)
2685 {
2686 RADV_FROM_HANDLE(radv_device, device, _device);
2687 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2688 sizeof(*fence), 8,
2689 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2690
2691 if (!fence)
2692 return VK_ERROR_OUT_OF_HOST_MEMORY;
2693
2694 memset(fence, 0, sizeof(*fence));
2695 fence->submitted = false;
2696 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2697 fence->fence = device->ws->create_fence();
2698 if (!fence->fence) {
2699 vk_free2(&device->alloc, pAllocator, fence);
2700 return VK_ERROR_OUT_OF_HOST_MEMORY;
2701 }
2702
2703 *pFence = radv_fence_to_handle(fence);
2704
2705 return VK_SUCCESS;
2706 }
2707
2708 void radv_DestroyFence(
2709 VkDevice _device,
2710 VkFence _fence,
2711 const VkAllocationCallbacks* pAllocator)
2712 {
2713 RADV_FROM_HANDLE(radv_device, device, _device);
2714 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2715
2716 if (!fence)
2717 return;
2718 device->ws->destroy_fence(fence->fence);
2719 vk_free2(&device->alloc, pAllocator, fence);
2720 }
2721
2722 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2723 {
2724 uint64_t current_time;
2725 struct timespec tv;
2726
2727 clock_gettime(CLOCK_MONOTONIC, &tv);
2728 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2729
2730 timeout = MIN2(UINT64_MAX - current_time, timeout);
2731
2732 return current_time + timeout;
2733 }
2734
2735 VkResult radv_WaitForFences(
2736 VkDevice _device,
2737 uint32_t fenceCount,
2738 const VkFence* pFences,
2739 VkBool32 waitAll,
2740 uint64_t timeout)
2741 {
2742 RADV_FROM_HANDLE(radv_device, device, _device);
2743 timeout = radv_get_absolute_timeout(timeout);
2744
2745 if (!waitAll && fenceCount > 1) {
2746 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2747 }
2748
2749 for (uint32_t i = 0; i < fenceCount; ++i) {
2750 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2751 bool expired = false;
2752
2753 if (fence->signalled)
2754 continue;
2755
2756 if (!fence->submitted)
2757 return VK_TIMEOUT;
2758
2759 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2760 if (!expired)
2761 return VK_TIMEOUT;
2762
2763 fence->signalled = true;
2764 }
2765
2766 return VK_SUCCESS;
2767 }
2768
2769 VkResult radv_ResetFences(VkDevice device,
2770 uint32_t fenceCount,
2771 const VkFence *pFences)
2772 {
2773 for (unsigned i = 0; i < fenceCount; ++i) {
2774 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2775 fence->submitted = fence->signalled = false;
2776 }
2777
2778 return VK_SUCCESS;
2779 }
2780
2781 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2782 {
2783 RADV_FROM_HANDLE(radv_device, device, _device);
2784 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2785
2786 if (fence->signalled)
2787 return VK_SUCCESS;
2788 if (!fence->submitted)
2789 return VK_NOT_READY;
2790
2791 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2792 return VK_NOT_READY;
2793
2794 return VK_SUCCESS;
2795 }
2796
2797
2798 // Queue semaphore functions
2799
2800 VkResult radv_CreateSemaphore(
2801 VkDevice _device,
2802 const VkSemaphoreCreateInfo* pCreateInfo,
2803 const VkAllocationCallbacks* pAllocator,
2804 VkSemaphore* pSemaphore)
2805 {
2806 RADV_FROM_HANDLE(radv_device, device, _device);
2807 const VkExportSemaphoreCreateInfoKHR *export =
2808 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2809 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2810 export ? export->handleTypes : 0;
2811
2812 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2813 sizeof(*sem), 8,
2814 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2815 if (!sem)
2816 return VK_ERROR_OUT_OF_HOST_MEMORY;
2817
2818 sem->temp_syncobj = 0;
2819 /* create a syncobject if we are going to export this semaphore */
2820 if (handleTypes) {
2821 assert (device->physical_device->rad_info.has_syncobj);
2822 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2823 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2824 if (ret) {
2825 vk_free2(&device->alloc, pAllocator, sem);
2826 return VK_ERROR_OUT_OF_HOST_MEMORY;
2827 }
2828 sem->sem = NULL;
2829 } else {
2830 sem->sem = device->ws->create_sem(device->ws);
2831 if (!sem->sem) {
2832 vk_free2(&device->alloc, pAllocator, sem);
2833 return VK_ERROR_OUT_OF_HOST_MEMORY;
2834 }
2835 sem->syncobj = 0;
2836 }
2837
2838 *pSemaphore = radv_semaphore_to_handle(sem);
2839 return VK_SUCCESS;
2840 }
2841
2842 void radv_DestroySemaphore(
2843 VkDevice _device,
2844 VkSemaphore _semaphore,
2845 const VkAllocationCallbacks* pAllocator)
2846 {
2847 RADV_FROM_HANDLE(radv_device, device, _device);
2848 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2849 if (!_semaphore)
2850 return;
2851
2852 if (sem->syncobj)
2853 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2854 else
2855 device->ws->destroy_sem(sem->sem);
2856 vk_free2(&device->alloc, pAllocator, sem);
2857 }
2858
2859 VkResult radv_CreateEvent(
2860 VkDevice _device,
2861 const VkEventCreateInfo* pCreateInfo,
2862 const VkAllocationCallbacks* pAllocator,
2863 VkEvent* pEvent)
2864 {
2865 RADV_FROM_HANDLE(radv_device, device, _device);
2866 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2867 sizeof(*event), 8,
2868 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2869
2870 if (!event)
2871 return VK_ERROR_OUT_OF_HOST_MEMORY;
2872
2873 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2874 RADEON_DOMAIN_GTT,
2875 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2876 if (!event->bo) {
2877 vk_free2(&device->alloc, pAllocator, event);
2878 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2879 }
2880
2881 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2882
2883 *pEvent = radv_event_to_handle(event);
2884
2885 return VK_SUCCESS;
2886 }
2887
2888 void radv_DestroyEvent(
2889 VkDevice _device,
2890 VkEvent _event,
2891 const VkAllocationCallbacks* pAllocator)
2892 {
2893 RADV_FROM_HANDLE(radv_device, device, _device);
2894 RADV_FROM_HANDLE(radv_event, event, _event);
2895
2896 if (!event)
2897 return;
2898 device->ws->buffer_destroy(event->bo);
2899 vk_free2(&device->alloc, pAllocator, event);
2900 }
2901
2902 VkResult radv_GetEventStatus(
2903 VkDevice _device,
2904 VkEvent _event)
2905 {
2906 RADV_FROM_HANDLE(radv_event, event, _event);
2907
2908 if (*event->map == 1)
2909 return VK_EVENT_SET;
2910 return VK_EVENT_RESET;
2911 }
2912
2913 VkResult radv_SetEvent(
2914 VkDevice _device,
2915 VkEvent _event)
2916 {
2917 RADV_FROM_HANDLE(radv_event, event, _event);
2918 *event->map = 1;
2919
2920 return VK_SUCCESS;
2921 }
2922
2923 VkResult radv_ResetEvent(
2924 VkDevice _device,
2925 VkEvent _event)
2926 {
2927 RADV_FROM_HANDLE(radv_event, event, _event);
2928 *event->map = 0;
2929
2930 return VK_SUCCESS;
2931 }
2932
2933 VkResult radv_CreateBuffer(
2934 VkDevice _device,
2935 const VkBufferCreateInfo* pCreateInfo,
2936 const VkAllocationCallbacks* pAllocator,
2937 VkBuffer* pBuffer)
2938 {
2939 RADV_FROM_HANDLE(radv_device, device, _device);
2940 struct radv_buffer *buffer;
2941
2942 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2943
2944 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2945 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2946 if (buffer == NULL)
2947 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2948
2949 buffer->size = pCreateInfo->size;
2950 buffer->usage = pCreateInfo->usage;
2951 buffer->bo = NULL;
2952 buffer->offset = 0;
2953 buffer->flags = pCreateInfo->flags;
2954
2955 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2956 buffer->bo = device->ws->buffer_create(device->ws,
2957 align64(buffer->size, 4096),
2958 4096, 0, RADEON_FLAG_VIRTUAL);
2959 if (!buffer->bo) {
2960 vk_free2(&device->alloc, pAllocator, buffer);
2961 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2962 }
2963 }
2964
2965 *pBuffer = radv_buffer_to_handle(buffer);
2966
2967 return VK_SUCCESS;
2968 }
2969
2970 void radv_DestroyBuffer(
2971 VkDevice _device,
2972 VkBuffer _buffer,
2973 const VkAllocationCallbacks* pAllocator)
2974 {
2975 RADV_FROM_HANDLE(radv_device, device, _device);
2976 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2977
2978 if (!buffer)
2979 return;
2980
2981 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2982 device->ws->buffer_destroy(buffer->bo);
2983
2984 vk_free2(&device->alloc, pAllocator, buffer);
2985 }
2986
2987 static inline unsigned
2988 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2989 {
2990 if (stencil)
2991 return image->surface.u.legacy.stencil_tiling_index[level];
2992 else
2993 return image->surface.u.legacy.tiling_index[level];
2994 }
2995
2996 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2997 {
2998 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2999 }
3000
3001 static void
3002 radv_initialise_color_surface(struct radv_device *device,
3003 struct radv_color_buffer_info *cb,
3004 struct radv_image_view *iview)
3005 {
3006 const struct vk_format_description *desc;
3007 unsigned ntype, format, swap, endian;
3008 unsigned blend_clamp = 0, blend_bypass = 0;
3009 uint64_t va;
3010 const struct radeon_surf *surf = &iview->image->surface;
3011
3012 desc = vk_format_description(iview->vk_format);
3013
3014 memset(cb, 0, sizeof(*cb));
3015
3016 /* Intensity is implemented as Red, so treat it that way. */
3017 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3018
3019 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3020
3021 cb->cb_color_base = va >> 8;
3022
3023 if (device->physical_device->rad_info.chip_class >= GFX9) {
3024 struct gfx9_surf_meta_flags meta;
3025 if (iview->image->dcc_offset)
3026 meta = iview->image->surface.u.gfx9.dcc;
3027 else
3028 meta = iview->image->surface.u.gfx9.cmask;
3029
3030 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3031 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3032 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3033 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3034
3035 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3036 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3037 } else {
3038 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3039 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3040
3041 cb->cb_color_base += level_info->offset >> 8;
3042 if (level_info->mode == RADEON_SURF_MODE_2D)
3043 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3044
3045 pitch_tile_max = level_info->nblk_x / 8 - 1;
3046 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3047 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3048
3049 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3050 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3051 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3052
3053 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3054 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
3055
3056 if (iview->image->fmask.size) {
3057 if (device->physical_device->rad_info.chip_class >= CIK)
3058 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3059 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3060 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3061 } else {
3062 /* This must be set for fast clear to work without FMASK. */
3063 if (device->physical_device->rad_info.chip_class >= CIK)
3064 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3065 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3066 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3067 }
3068 }
3069
3070 /* CMASK variables */
3071 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3072 va += iview->image->cmask.offset;
3073 cb->cb_color_cmask = va >> 8;
3074
3075 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3076 va += iview->image->dcc_offset;
3077 cb->cb_dcc_base = va >> 8;
3078 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3079
3080 uint32_t max_slice = radv_surface_layer_count(iview);
3081 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3082 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3083
3084 if (iview->image->info.samples > 1) {
3085 unsigned log_samples = util_logbase2(iview->image->info.samples);
3086
3087 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3088 S_028C74_NUM_FRAGMENTS(log_samples);
3089 }
3090
3091 if (iview->image->fmask.size) {
3092 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3093 cb->cb_color_fmask = va >> 8;
3094 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3095 } else {
3096 cb->cb_color_fmask = cb->cb_color_base;
3097 }
3098
3099 ntype = radv_translate_color_numformat(iview->vk_format,
3100 desc,
3101 vk_format_get_first_non_void_channel(iview->vk_format));
3102 format = radv_translate_colorformat(iview->vk_format);
3103 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3104 radv_finishme("Illegal color\n");
3105 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3106 endian = radv_colorformat_endian_swap(format);
3107
3108 /* blend clamp should be set for all NORM/SRGB types */
3109 if (ntype == V_028C70_NUMBER_UNORM ||
3110 ntype == V_028C70_NUMBER_SNORM ||
3111 ntype == V_028C70_NUMBER_SRGB)
3112 blend_clamp = 1;
3113
3114 /* set blend bypass according to docs if SINT/UINT or
3115 8/24 COLOR variants */
3116 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3117 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3118 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3119 blend_clamp = 0;
3120 blend_bypass = 1;
3121 }
3122 #if 0
3123 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3124 (format == V_028C70_COLOR_8 ||
3125 format == V_028C70_COLOR_8_8 ||
3126 format == V_028C70_COLOR_8_8_8_8))
3127 ->color_is_int8 = true;
3128 #endif
3129 cb->cb_color_info = S_028C70_FORMAT(format) |
3130 S_028C70_COMP_SWAP(swap) |
3131 S_028C70_BLEND_CLAMP(blend_clamp) |
3132 S_028C70_BLEND_BYPASS(blend_bypass) |
3133 S_028C70_SIMPLE_FLOAT(1) |
3134 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3135 ntype != V_028C70_NUMBER_SNORM &&
3136 ntype != V_028C70_NUMBER_SRGB &&
3137 format != V_028C70_COLOR_8_24 &&
3138 format != V_028C70_COLOR_24_8) |
3139 S_028C70_NUMBER_TYPE(ntype) |
3140 S_028C70_ENDIAN(endian);
3141 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3142 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3143 if (device->physical_device->rad_info.chip_class == SI) {
3144 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3145 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3146 }
3147 }
3148
3149 if (iview->image->cmask.size &&
3150 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3151 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3152
3153 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3154 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3155
3156 if (device->physical_device->rad_info.chip_class >= VI) {
3157 unsigned max_uncompressed_block_size = 2;
3158 if (iview->image->info.samples > 1) {
3159 if (iview->image->surface.bpe == 1)
3160 max_uncompressed_block_size = 0;
3161 else if (iview->image->surface.bpe == 2)
3162 max_uncompressed_block_size = 1;
3163 }
3164
3165 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3166 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3167 }
3168
3169 /* This must be set for fast clear to work without FMASK. */
3170 if (!iview->image->fmask.size &&
3171 device->physical_device->rad_info.chip_class == SI) {
3172 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3173 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3174 }
3175
3176 if (device->physical_device->rad_info.chip_class >= GFX9) {
3177 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3178 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3179
3180 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3181 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3182 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3183 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3184 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3185 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3186
3187 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3188
3189 }
3190 }
3191
3192 static void
3193 radv_initialise_ds_surface(struct radv_device *device,
3194 struct radv_ds_buffer_info *ds,
3195 struct radv_image_view *iview)
3196 {
3197 unsigned level = iview->base_mip;
3198 unsigned format, stencil_format;
3199 uint64_t va, s_offs, z_offs;
3200 bool stencil_only = false;
3201 memset(ds, 0, sizeof(*ds));
3202 switch (iview->image->vk_format) {
3203 case VK_FORMAT_D24_UNORM_S8_UINT:
3204 case VK_FORMAT_X8_D24_UNORM_PACK32:
3205 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3206 ds->offset_scale = 2.0f;
3207 break;
3208 case VK_FORMAT_D16_UNORM:
3209 case VK_FORMAT_D16_UNORM_S8_UINT:
3210 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3211 ds->offset_scale = 4.0f;
3212 break;
3213 case VK_FORMAT_D32_SFLOAT:
3214 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3215 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3216 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3217 ds->offset_scale = 1.0f;
3218 break;
3219 case VK_FORMAT_S8_UINT:
3220 stencil_only = true;
3221 break;
3222 default:
3223 break;
3224 }
3225
3226 format = radv_translate_dbformat(iview->image->vk_format);
3227 stencil_format = iview->image->surface.has_stencil ?
3228 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3229
3230 uint32_t max_slice = radv_surface_layer_count(iview);
3231 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3232 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3233
3234 ds->db_htile_data_base = 0;
3235 ds->db_htile_surface = 0;
3236
3237 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3238 s_offs = z_offs = va;
3239
3240 if (device->physical_device->rad_info.chip_class >= GFX9) {
3241 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3242 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3243
3244 ds->db_z_info = S_028038_FORMAT(format) |
3245 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3246 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3247 S_028038_MAXMIP(iview->image->info.levels - 1);
3248 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3249 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3250
3251 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3252 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3253 ds->db_depth_view |= S_028008_MIPID(level);
3254
3255 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3256 S_02801C_Y_MAX(iview->image->info.height - 1);
3257
3258 if (radv_htile_enabled(iview->image, level)) {
3259 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3260
3261 if (iview->image->tc_compatible_htile) {
3262 unsigned max_zplanes = 4;
3263
3264 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3265 iview->image->info.samples > 1)
3266 max_zplanes = 2;
3267
3268 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3269 S_028038_ITERATE_FLUSH(1);
3270 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3271 }
3272
3273 if (!iview->image->surface.has_stencil)
3274 /* Use all of the htile_buffer for depth if there's no stencil. */
3275 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3276 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3277 iview->image->htile_offset;
3278 ds->db_htile_data_base = va >> 8;
3279 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3280 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3281 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3282 }
3283 } else {
3284 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3285
3286 if (stencil_only)
3287 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3288
3289 z_offs += iview->image->surface.u.legacy.level[level].offset;
3290 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3291
3292 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3293 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3294 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3295
3296 if (iview->image->info.samples > 1)
3297 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3298
3299 if (device->physical_device->rad_info.chip_class >= CIK) {
3300 struct radeon_info *info = &device->physical_device->rad_info;
3301 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3302 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3303 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3304 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3305 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3306 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3307
3308 if (stencil_only)
3309 tile_mode = stencil_tile_mode;
3310
3311 ds->db_depth_info |=
3312 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3313 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3314 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3315 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3316 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3317 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3318 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3319 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3320 } else {
3321 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3322 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3323 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3324 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3325 if (stencil_only)
3326 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3327 }
3328
3329 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3330 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3331 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3332
3333 if (radv_htile_enabled(iview->image, level)) {
3334 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3335
3336 if (!iview->image->surface.has_stencil &&
3337 !iview->image->tc_compatible_htile)
3338 /* Use all of the htile_buffer for depth if there's no stencil. */
3339 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3340
3341 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3342 iview->image->htile_offset;
3343 ds->db_htile_data_base = va >> 8;
3344 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3345
3346 if (iview->image->tc_compatible_htile) {
3347 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3348
3349 if (iview->image->info.samples <= 1)
3350 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3351 else if (iview->image->info.samples <= 4)
3352 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3353 else
3354 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3355 }
3356 }
3357 }
3358
3359 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3360 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3361 }
3362
3363 VkResult radv_CreateFramebuffer(
3364 VkDevice _device,
3365 const VkFramebufferCreateInfo* pCreateInfo,
3366 const VkAllocationCallbacks* pAllocator,
3367 VkFramebuffer* pFramebuffer)
3368 {
3369 RADV_FROM_HANDLE(radv_device, device, _device);
3370 struct radv_framebuffer *framebuffer;
3371
3372 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3373
3374 size_t size = sizeof(*framebuffer) +
3375 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3376 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3377 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3378 if (framebuffer == NULL)
3379 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3380
3381 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3382 framebuffer->width = pCreateInfo->width;
3383 framebuffer->height = pCreateInfo->height;
3384 framebuffer->layers = pCreateInfo->layers;
3385 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3386 VkImageView _iview = pCreateInfo->pAttachments[i];
3387 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3388 framebuffer->attachments[i].attachment = iview;
3389 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3390 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3391 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3392 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3393 }
3394 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3395 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3396 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3397 }
3398
3399 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3400 return VK_SUCCESS;
3401 }
3402
3403 void radv_DestroyFramebuffer(
3404 VkDevice _device,
3405 VkFramebuffer _fb,
3406 const VkAllocationCallbacks* pAllocator)
3407 {
3408 RADV_FROM_HANDLE(radv_device, device, _device);
3409 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3410
3411 if (!fb)
3412 return;
3413 vk_free2(&device->alloc, pAllocator, fb);
3414 }
3415
3416 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3417 {
3418 switch (address_mode) {
3419 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3420 return V_008F30_SQ_TEX_WRAP;
3421 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3422 return V_008F30_SQ_TEX_MIRROR;
3423 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3424 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3425 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3426 return V_008F30_SQ_TEX_CLAMP_BORDER;
3427 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3428 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3429 default:
3430 unreachable("illegal tex wrap mode");
3431 break;
3432 }
3433 }
3434
3435 static unsigned
3436 radv_tex_compare(VkCompareOp op)
3437 {
3438 switch (op) {
3439 case VK_COMPARE_OP_NEVER:
3440 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3441 case VK_COMPARE_OP_LESS:
3442 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3443 case VK_COMPARE_OP_EQUAL:
3444 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3445 case VK_COMPARE_OP_LESS_OR_EQUAL:
3446 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3447 case VK_COMPARE_OP_GREATER:
3448 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3449 case VK_COMPARE_OP_NOT_EQUAL:
3450 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3451 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3452 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3453 case VK_COMPARE_OP_ALWAYS:
3454 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3455 default:
3456 unreachable("illegal compare mode");
3457 break;
3458 }
3459 }
3460
3461 static unsigned
3462 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3463 {
3464 switch (filter) {
3465 case VK_FILTER_NEAREST:
3466 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3467 V_008F38_SQ_TEX_XY_FILTER_POINT);
3468 case VK_FILTER_LINEAR:
3469 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3470 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3471 case VK_FILTER_CUBIC_IMG:
3472 default:
3473 fprintf(stderr, "illegal texture filter");
3474 return 0;
3475 }
3476 }
3477
3478 static unsigned
3479 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3480 {
3481 switch (mode) {
3482 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3483 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3484 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3485 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3486 default:
3487 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3488 }
3489 }
3490
3491 static unsigned
3492 radv_tex_bordercolor(VkBorderColor bcolor)
3493 {
3494 switch (bcolor) {
3495 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3496 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3497 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3498 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3499 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3500 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3501 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3502 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3503 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3504 default:
3505 break;
3506 }
3507 return 0;
3508 }
3509
3510 static unsigned
3511 radv_tex_aniso_filter(unsigned filter)
3512 {
3513 if (filter < 2)
3514 return 0;
3515 if (filter < 4)
3516 return 1;
3517 if (filter < 8)
3518 return 2;
3519 if (filter < 16)
3520 return 3;
3521 return 4;
3522 }
3523
3524 static void
3525 radv_init_sampler(struct radv_device *device,
3526 struct radv_sampler *sampler,
3527 const VkSamplerCreateInfo *pCreateInfo)
3528 {
3529 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3530 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3531 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3532 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3533
3534 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3535 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3536 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3537 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3538 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3539 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3540 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3541 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3542 S_008F30_DISABLE_CUBE_WRAP(0) |
3543 S_008F30_COMPAT_MODE(is_vi));
3544 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3545 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3546 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3547 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3548 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3549 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3550 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3551 S_008F38_MIP_POINT_PRECLAMP(0) |
3552 S_008F38_DISABLE_LSB_CEIL(1) |
3553 S_008F38_FILTER_PREC_FIX(1) |
3554 S_008F38_ANISO_OVERRIDE(is_vi));
3555 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3556 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3557 }
3558
3559 VkResult radv_CreateSampler(
3560 VkDevice _device,
3561 const VkSamplerCreateInfo* pCreateInfo,
3562 const VkAllocationCallbacks* pAllocator,
3563 VkSampler* pSampler)
3564 {
3565 RADV_FROM_HANDLE(radv_device, device, _device);
3566 struct radv_sampler *sampler;
3567
3568 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3569
3570 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3571 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3572 if (!sampler)
3573 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3574
3575 radv_init_sampler(device, sampler, pCreateInfo);
3576 *pSampler = radv_sampler_to_handle(sampler);
3577
3578 return VK_SUCCESS;
3579 }
3580
3581 void radv_DestroySampler(
3582 VkDevice _device,
3583 VkSampler _sampler,
3584 const VkAllocationCallbacks* pAllocator)
3585 {
3586 RADV_FROM_HANDLE(radv_device, device, _device);
3587 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3588
3589 if (!sampler)
3590 return;
3591 vk_free2(&device->alloc, pAllocator, sampler);
3592 }
3593
3594 /* vk_icd.h does not declare this function, so we declare it here to
3595 * suppress Wmissing-prototypes.
3596 */
3597 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3598 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3599
3600 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3601 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3602 {
3603 /* For the full details on loader interface versioning, see
3604 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3605 * What follows is a condensed summary, to help you navigate the large and
3606 * confusing official doc.
3607 *
3608 * - Loader interface v0 is incompatible with later versions. We don't
3609 * support it.
3610 *
3611 * - In loader interface v1:
3612 * - The first ICD entrypoint called by the loader is
3613 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3614 * entrypoint.
3615 * - The ICD must statically expose no other Vulkan symbol unless it is
3616 * linked with -Bsymbolic.
3617 * - Each dispatchable Vulkan handle created by the ICD must be
3618 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3619 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3620 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3621 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3622 * such loader-managed surfaces.
3623 *
3624 * - Loader interface v2 differs from v1 in:
3625 * - The first ICD entrypoint called by the loader is
3626 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3627 * statically expose this entrypoint.
3628 *
3629 * - Loader interface v3 differs from v2 in:
3630 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3631 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3632 * because the loader no longer does so.
3633 */
3634 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3635 return VK_SUCCESS;
3636 }
3637
3638 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3639 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3640 int *pFD)
3641 {
3642 RADV_FROM_HANDLE(radv_device, device, _device);
3643 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3644
3645 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3646
3647 /* We support only one handle type. */
3648 assert(pGetFdInfo->handleType ==
3649 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3650
3651 bool ret = radv_get_memory_fd(device, memory, pFD);
3652 if (ret == false)
3653 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3654 return VK_SUCCESS;
3655 }
3656
3657 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3658 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3659 int fd,
3660 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3661 {
3662 /* The valid usage section for this function says:
3663 *
3664 * "handleType must not be one of the handle types defined as opaque."
3665 *
3666 * Since we only handle opaque handles for now, there are no FD properties.
3667 */
3668 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3669 }
3670
3671 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3672 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3673 {
3674 RADV_FROM_HANDLE(radv_device, device, _device);
3675 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3676 uint32_t syncobj_handle = 0;
3677 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3678
3679 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3680 if (ret != 0)
3681 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3682
3683 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3684 sem->temp_syncobj = syncobj_handle;
3685 } else {
3686 sem->syncobj = syncobj_handle;
3687 }
3688 close(pImportSemaphoreFdInfo->fd);
3689 return VK_SUCCESS;
3690 }
3691
3692 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3693 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3694 int *pFd)
3695 {
3696 RADV_FROM_HANDLE(radv_device, device, _device);
3697 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3698 int ret;
3699 uint32_t syncobj_handle;
3700
3701 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3702 if (sem->temp_syncobj)
3703 syncobj_handle = sem->temp_syncobj;
3704 else
3705 syncobj_handle = sem->syncobj;
3706 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3707 if (ret)
3708 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3709 return VK_SUCCESS;
3710 }
3711
3712 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3713 VkPhysicalDevice physicalDevice,
3714 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3715 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3716 {
3717 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3718 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3719 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3720 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3721 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3722 } else {
3723 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3724 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3725 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3726 }
3727 }