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radv: implement VK_AMD_shader_core_properties
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
105 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
106 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
107 default: chip_string = "AMD RADV unknown"; break;
108 }
109
110 if (HAVE_LLVM > 0) {
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 }
115
116 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
117 }
118
119 static void
120 radv_physical_device_init_mem_types(struct radv_physical_device *device)
121 {
122 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
123 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
124 device->rad_info.vram_vis_size);
125
126 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
127 device->memory_properties.memoryHeapCount = 0;
128 if (device->rad_info.vram_size - visible_vram_size > 0) {
129 vram_index = device->memory_properties.memoryHeapCount++;
130 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
131 .size = device->rad_info.vram_size - visible_vram_size,
132 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
133 };
134 }
135 if (visible_vram_size) {
136 visible_vram_index = device->memory_properties.memoryHeapCount++;
137 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
138 .size = visible_vram_size,
139 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
140 };
141 }
142 if (device->rad_info.gart_size > 0) {
143 gart_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
145 .size = device->rad_info.gart_size,
146 .flags = 0,
147 };
148 }
149
150 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
151 unsigned type_count = 0;
152 if (vram_index >= 0) {
153 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
154 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
155 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
156 .heapIndex = vram_index,
157 };
158 }
159 if (gart_index >= 0) {
160 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
161 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
162 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
163 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
164 .heapIndex = gart_index,
165 };
166 }
167 if (visible_vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
171 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
172 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
173 .heapIndex = visible_vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228
229 fd = open(path, O_RDWR | O_CLOEXEC);
230 if (fd < 0)
231 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
232
233 version = drmGetVersion(fd);
234 if (!version) {
235 close(fd);
236 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
237 "failed to get version %s: %m", path);
238 }
239
240 if (strcmp(version->name, "amdgpu")) {
241 drmFreeVersion(version);
242 close(fd);
243 return VK_ERROR_INCOMPATIBLE_DRIVER;
244 }
245 drmFreeVersion(version);
246
247 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
248 device->instance = instance;
249 assert(strlen(path) < ARRAY_SIZE(device->path));
250 strncpy(device->path, path, ARRAY_SIZE(device->path));
251
252 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
253 instance->perftest_flags);
254 if (!device->ws) {
255 result = VK_ERROR_INCOMPATIBLE_DRIVER;
256 goto fail;
257 }
258
259 device->local_fd = fd;
260 device->ws->query_info(device->ws, &device->rad_info);
261
262 radv_handle_env_var_force_family(device);
263
264 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
265
266 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
267 device->ws->destroy(device->ws);
268 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
269 "cannot generate UUID");
270 goto fail;
271 }
272
273 /* These flags affect shader compilation. */
274 uint64_t shader_env_flags =
275 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
276 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
277
278 /* The gpu id is already embeded in the uuid so we just pass "radv"
279 * when creating the cache.
280 */
281 char buf[VK_UUID_SIZE * 2 + 1];
282 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
283 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
284
285 if (device->rad_info.chip_class < VI ||
286 device->rad_info.chip_class > GFX9)
287 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
288
289 radv_get_driver_uuid(&device->device_uuid);
290 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
291
292 if (device->rad_info.family == CHIP_STONEY ||
293 device->rad_info.chip_class >= GFX9) {
294 device->has_rbplus = true;
295 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
296 device->rad_info.family == CHIP_VEGA12;
297 }
298
299 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
300 * on SI.
301 */
302 device->has_clear_state = device->rad_info.chip_class >= CIK;
303
304 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
305
306 /* Vega10/Raven need a special workaround for a hardware bug. */
307 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
308 device->rad_info.family == CHIP_RAVEN;
309
310 /* Out-of-order primitive rasterization. */
311 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
312 device->rad_info.max_se >= 2;
313 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
314 (device->instance->perftest_flags & RADV_PERFTEST_OUT_OF_ORDER);
315
316 radv_physical_device_init_mem_types(device);
317 radv_fill_device_extension_table(device, &device->supported_extensions);
318
319 result = radv_init_wsi(device);
320 if (result != VK_SUCCESS) {
321 device->ws->destroy(device->ws);
322 goto fail;
323 }
324
325 return VK_SUCCESS;
326
327 fail:
328 close(fd);
329 return result;
330 }
331
332 static void
333 radv_physical_device_finish(struct radv_physical_device *device)
334 {
335 radv_finish_wsi(device);
336 device->ws->destroy(device->ws);
337 disk_cache_destroy(device->disk_cache);
338 close(device->local_fd);
339 }
340
341 static void *
342 default_alloc_func(void *pUserData, size_t size, size_t align,
343 VkSystemAllocationScope allocationScope)
344 {
345 return malloc(size);
346 }
347
348 static void *
349 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
350 size_t align, VkSystemAllocationScope allocationScope)
351 {
352 return realloc(pOriginal, size);
353 }
354
355 static void
356 default_free_func(void *pUserData, void *pMemory)
357 {
358 free(pMemory);
359 }
360
361 static const VkAllocationCallbacks default_alloc = {
362 .pUserData = NULL,
363 .pfnAllocation = default_alloc_func,
364 .pfnReallocation = default_realloc_func,
365 .pfnFree = default_free_func,
366 };
367
368 static const struct debug_control radv_debug_options[] = {
369 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
370 {"nodcc", RADV_DEBUG_NO_DCC},
371 {"shaders", RADV_DEBUG_DUMP_SHADERS},
372 {"nocache", RADV_DEBUG_NO_CACHE},
373 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
374 {"nohiz", RADV_DEBUG_NO_HIZ},
375 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
376 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
377 {"allbos", RADV_DEBUG_ALL_BOS},
378 {"noibs", RADV_DEBUG_NO_IBS},
379 {"spirv", RADV_DEBUG_DUMP_SPIRV},
380 {"vmfaults", RADV_DEBUG_VM_FAULTS},
381 {"zerovram", RADV_DEBUG_ZERO_VRAM},
382 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
383 {"nosisched", RADV_DEBUG_NO_SISCHED},
384 {"preoptir", RADV_DEBUG_PREOPTIR},
385 {NULL, 0}
386 };
387
388 const char *
389 radv_get_debug_option_name(int id)
390 {
391 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
392 return radv_debug_options[id].string;
393 }
394
395 static const struct debug_control radv_perftest_options[] = {
396 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
397 {"sisched", RADV_PERFTEST_SISCHED},
398 {"localbos", RADV_PERFTEST_LOCAL_BOS},
399 {"binning", RADV_PERFTEST_BINNING},
400 {"outoforderrast", RADV_PERFTEST_OUT_OF_ORDER},
401 {NULL, 0}
402 };
403
404 const char *
405 radv_get_perftest_option_name(int id)
406 {
407 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
408 return radv_perftest_options[id].string;
409 }
410
411 static void
412 radv_handle_per_app_options(struct radv_instance *instance,
413 const VkApplicationInfo *info)
414 {
415 const char *name = info ? info->pApplicationName : NULL;
416
417 if (!name)
418 return;
419
420 if (!strcmp(name, "Talos - Linux - 32bit") ||
421 !strcmp(name, "Talos - Linux - 64bit")) {
422 /* Force enable LLVM sisched for Talos because it looks safe
423 * and it gives few more FPS.
424 */
425 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
426 }
427 }
428
429 static int radv_get_instance_extension_index(const char *name)
430 {
431 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
432 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
433 return i;
434 }
435 return -1;
436 }
437
438
439 VkResult radv_CreateInstance(
440 const VkInstanceCreateInfo* pCreateInfo,
441 const VkAllocationCallbacks* pAllocator,
442 VkInstance* pInstance)
443 {
444 struct radv_instance *instance;
445 VkResult result;
446
447 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
448
449 uint32_t client_version;
450 if (pCreateInfo->pApplicationInfo &&
451 pCreateInfo->pApplicationInfo->apiVersion != 0) {
452 client_version = pCreateInfo->pApplicationInfo->apiVersion;
453 } else {
454 client_version = VK_MAKE_VERSION(1, 0, 0);
455 }
456
457 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
458 client_version > VK_MAKE_VERSION(1, 1, 0xfff)) {
459 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
460 "Client requested version %d.%d.%d",
461 VK_VERSION_MAJOR(client_version),
462 VK_VERSION_MINOR(client_version),
463 VK_VERSION_PATCH(client_version));
464 }
465
466 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
467 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
468 if (!instance)
469 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
470
471 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
472
473 if (pAllocator)
474 instance->alloc = *pAllocator;
475 else
476 instance->alloc = default_alloc;
477
478 instance->apiVersion = client_version;
479 instance->physicalDeviceCount = -1;
480
481 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
482 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
483 int index = radv_get_instance_extension_index(ext_name);
484
485 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
486 vk_free2(&default_alloc, pAllocator, instance);
487 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
488 }
489
490 instance->enabled_extensions.extensions[index] = true;
491 }
492
493 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
494 if (result != VK_SUCCESS) {
495 vk_free2(&default_alloc, pAllocator, instance);
496 return vk_error(result);
497 }
498
499 _mesa_locale_init();
500
501 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
502
503 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
504 radv_debug_options);
505
506 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
507 radv_perftest_options);
508
509 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
510
511 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
512 /* Disable sisched when the user requests it, this is mostly
513 * useful when the driver force-enable sisched for the given
514 * application.
515 */
516 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
517 }
518
519 *pInstance = radv_instance_to_handle(instance);
520
521 return VK_SUCCESS;
522 }
523
524 void radv_DestroyInstance(
525 VkInstance _instance,
526 const VkAllocationCallbacks* pAllocator)
527 {
528 RADV_FROM_HANDLE(radv_instance, instance, _instance);
529
530 if (!instance)
531 return;
532
533 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
534 radv_physical_device_finish(instance->physicalDevices + i);
535 }
536
537 VG(VALGRIND_DESTROY_MEMPOOL(instance));
538
539 _mesa_locale_fini();
540
541 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
542
543 vk_free(&instance->alloc, instance);
544 }
545
546 static VkResult
547 radv_enumerate_devices(struct radv_instance *instance)
548 {
549 /* TODO: Check for more devices ? */
550 drmDevicePtr devices[8];
551 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
552 int max_devices;
553
554 instance->physicalDeviceCount = 0;
555
556 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
557 if (max_devices < 1)
558 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
559
560 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
561 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
562 devices[i]->bustype == DRM_BUS_PCI &&
563 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
564
565 result = radv_physical_device_init(instance->physicalDevices +
566 instance->physicalDeviceCount,
567 instance,
568 devices[i]);
569 if (result == VK_SUCCESS)
570 ++instance->physicalDeviceCount;
571 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
572 break;
573 }
574 }
575 drmFreeDevices(devices, max_devices);
576
577 return result;
578 }
579
580 VkResult radv_EnumeratePhysicalDevices(
581 VkInstance _instance,
582 uint32_t* pPhysicalDeviceCount,
583 VkPhysicalDevice* pPhysicalDevices)
584 {
585 RADV_FROM_HANDLE(radv_instance, instance, _instance);
586 VkResult result;
587
588 if (instance->physicalDeviceCount < 0) {
589 result = radv_enumerate_devices(instance);
590 if (result != VK_SUCCESS &&
591 result != VK_ERROR_INCOMPATIBLE_DRIVER)
592 return result;
593 }
594
595 if (!pPhysicalDevices) {
596 *pPhysicalDeviceCount = instance->physicalDeviceCount;
597 } else {
598 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
599 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
600 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
601 }
602
603 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
604 : VK_SUCCESS;
605 }
606
607 VkResult radv_EnumeratePhysicalDeviceGroups(
608 VkInstance _instance,
609 uint32_t* pPhysicalDeviceGroupCount,
610 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
611 {
612 RADV_FROM_HANDLE(radv_instance, instance, _instance);
613 VkResult result;
614
615 if (instance->physicalDeviceCount < 0) {
616 result = radv_enumerate_devices(instance);
617 if (result != VK_SUCCESS &&
618 result != VK_ERROR_INCOMPATIBLE_DRIVER)
619 return result;
620 }
621
622 if (!pPhysicalDeviceGroupProperties) {
623 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
624 } else {
625 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
626 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
627 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
628 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
629 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
630 }
631 }
632 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
633 : VK_SUCCESS;
634 }
635
636 void radv_GetPhysicalDeviceFeatures(
637 VkPhysicalDevice physicalDevice,
638 VkPhysicalDeviceFeatures* pFeatures)
639 {
640 memset(pFeatures, 0, sizeof(*pFeatures));
641
642 *pFeatures = (VkPhysicalDeviceFeatures) {
643 .robustBufferAccess = true,
644 .fullDrawIndexUint32 = true,
645 .imageCubeArray = true,
646 .independentBlend = true,
647 .geometryShader = true,
648 .tessellationShader = true,
649 .sampleRateShading = true,
650 .dualSrcBlend = true,
651 .logicOp = true,
652 .multiDrawIndirect = true,
653 .drawIndirectFirstInstance = true,
654 .depthClamp = true,
655 .depthBiasClamp = true,
656 .fillModeNonSolid = true,
657 .depthBounds = true,
658 .wideLines = true,
659 .largePoints = true,
660 .alphaToOne = true,
661 .multiViewport = true,
662 .samplerAnisotropy = true,
663 .textureCompressionETC2 = false,
664 .textureCompressionASTC_LDR = false,
665 .textureCompressionBC = true,
666 .occlusionQueryPrecise = true,
667 .pipelineStatisticsQuery = true,
668 .vertexPipelineStoresAndAtomics = true,
669 .fragmentStoresAndAtomics = true,
670 .shaderTessellationAndGeometryPointSize = true,
671 .shaderImageGatherExtended = true,
672 .shaderStorageImageExtendedFormats = true,
673 .shaderStorageImageMultisample = false,
674 .shaderUniformBufferArrayDynamicIndexing = true,
675 .shaderSampledImageArrayDynamicIndexing = true,
676 .shaderStorageBufferArrayDynamicIndexing = true,
677 .shaderStorageImageArrayDynamicIndexing = true,
678 .shaderStorageImageReadWithoutFormat = true,
679 .shaderStorageImageWriteWithoutFormat = true,
680 .shaderClipDistance = true,
681 .shaderCullDistance = true,
682 .shaderFloat64 = true,
683 .shaderInt64 = true,
684 .shaderInt16 = false,
685 .sparseBinding = true,
686 .variableMultisampleRate = true,
687 .inheritedQueries = true,
688 };
689 }
690
691 void radv_GetPhysicalDeviceFeatures2(
692 VkPhysicalDevice physicalDevice,
693 VkPhysicalDeviceFeatures2KHR *pFeatures)
694 {
695 vk_foreach_struct(ext, pFeatures->pNext) {
696 switch (ext->sType) {
697 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
698 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
699 features->variablePointersStorageBuffer = true;
700 features->variablePointers = false;
701 break;
702 }
703 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
704 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
705 features->multiview = true;
706 features->multiviewGeometryShader = true;
707 features->multiviewTessellationShader = true;
708 break;
709 }
710 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
711 VkPhysicalDeviceShaderDrawParameterFeatures *features =
712 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
713 features->shaderDrawParameters = true;
714 break;
715 }
716 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
717 VkPhysicalDeviceProtectedMemoryFeatures *features =
718 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
719 features->protectedMemory = false;
720 break;
721 }
722 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
723 VkPhysicalDevice16BitStorageFeatures *features =
724 (VkPhysicalDevice16BitStorageFeatures*)ext;
725 features->storageBuffer16BitAccess = false;
726 features->uniformAndStorageBuffer16BitAccess = false;
727 features->storagePushConstant16 = false;
728 features->storageInputOutput16 = false;
729 break;
730 }
731 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
732 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
733 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
734 features->samplerYcbcrConversion = false;
735 break;
736 }
737 default:
738 break;
739 }
740 }
741 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
742 }
743
744 void radv_GetPhysicalDeviceProperties(
745 VkPhysicalDevice physicalDevice,
746 VkPhysicalDeviceProperties* pProperties)
747 {
748 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
749 VkSampleCountFlags sample_counts = 0xf;
750
751 /* make sure that the entire descriptor set is addressable with a signed
752 * 32-bit int. So the sum of all limits scaled by descriptor size has to
753 * be at most 2 GiB. the combined image & samples object count as one of
754 * both. This limit is for the pipeline layout, not for the set layout, but
755 * there is no set limit, so we just set a pipeline limit. I don't think
756 * any app is going to hit this soon. */
757 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
758 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
759 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
760 32 /* sampler, largest when combined with image */ +
761 64 /* sampled image */ +
762 64 /* storage image */);
763
764 VkPhysicalDeviceLimits limits = {
765 .maxImageDimension1D = (1 << 14),
766 .maxImageDimension2D = (1 << 14),
767 .maxImageDimension3D = (1 << 11),
768 .maxImageDimensionCube = (1 << 14),
769 .maxImageArrayLayers = (1 << 11),
770 .maxTexelBufferElements = 128 * 1024 * 1024,
771 .maxUniformBufferRange = UINT32_MAX,
772 .maxStorageBufferRange = UINT32_MAX,
773 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
774 .maxMemoryAllocationCount = UINT32_MAX,
775 .maxSamplerAllocationCount = 64 * 1024,
776 .bufferImageGranularity = 64, /* A cache line */
777 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
778 .maxBoundDescriptorSets = MAX_SETS,
779 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
780 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
781 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
782 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
783 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
784 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
785 .maxPerStageResources = max_descriptor_set_size,
786 .maxDescriptorSetSamplers = max_descriptor_set_size,
787 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
788 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
789 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
790 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
791 .maxDescriptorSetSampledImages = max_descriptor_set_size,
792 .maxDescriptorSetStorageImages = max_descriptor_set_size,
793 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
794 .maxVertexInputAttributes = 32,
795 .maxVertexInputBindings = 32,
796 .maxVertexInputAttributeOffset = 2047,
797 .maxVertexInputBindingStride = 2048,
798 .maxVertexOutputComponents = 128,
799 .maxTessellationGenerationLevel = 64,
800 .maxTessellationPatchSize = 32,
801 .maxTessellationControlPerVertexInputComponents = 128,
802 .maxTessellationControlPerVertexOutputComponents = 128,
803 .maxTessellationControlPerPatchOutputComponents = 120,
804 .maxTessellationControlTotalOutputComponents = 4096,
805 .maxTessellationEvaluationInputComponents = 128,
806 .maxTessellationEvaluationOutputComponents = 128,
807 .maxGeometryShaderInvocations = 127,
808 .maxGeometryInputComponents = 64,
809 .maxGeometryOutputComponents = 128,
810 .maxGeometryOutputVertices = 256,
811 .maxGeometryTotalOutputComponents = 1024,
812 .maxFragmentInputComponents = 128,
813 .maxFragmentOutputAttachments = 8,
814 .maxFragmentDualSrcAttachments = 1,
815 .maxFragmentCombinedOutputResources = 8,
816 .maxComputeSharedMemorySize = 32768,
817 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
818 .maxComputeWorkGroupInvocations = 2048,
819 .maxComputeWorkGroupSize = {
820 2048,
821 2048,
822 2048
823 },
824 .subPixelPrecisionBits = 4 /* FIXME */,
825 .subTexelPrecisionBits = 4 /* FIXME */,
826 .mipmapPrecisionBits = 4 /* FIXME */,
827 .maxDrawIndexedIndexValue = UINT32_MAX,
828 .maxDrawIndirectCount = UINT32_MAX,
829 .maxSamplerLodBias = 16,
830 .maxSamplerAnisotropy = 16,
831 .maxViewports = MAX_VIEWPORTS,
832 .maxViewportDimensions = { (1 << 14), (1 << 14) },
833 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
834 .viewportSubPixelBits = 13, /* We take a float? */
835 .minMemoryMapAlignment = 4096, /* A page */
836 .minTexelBufferOffsetAlignment = 1,
837 .minUniformBufferOffsetAlignment = 4,
838 .minStorageBufferOffsetAlignment = 4,
839 .minTexelOffset = -32,
840 .maxTexelOffset = 31,
841 .minTexelGatherOffset = -32,
842 .maxTexelGatherOffset = 31,
843 .minInterpolationOffset = -2,
844 .maxInterpolationOffset = 2,
845 .subPixelInterpolationOffsetBits = 8,
846 .maxFramebufferWidth = (1 << 14),
847 .maxFramebufferHeight = (1 << 14),
848 .maxFramebufferLayers = (1 << 10),
849 .framebufferColorSampleCounts = sample_counts,
850 .framebufferDepthSampleCounts = sample_counts,
851 .framebufferStencilSampleCounts = sample_counts,
852 .framebufferNoAttachmentsSampleCounts = sample_counts,
853 .maxColorAttachments = MAX_RTS,
854 .sampledImageColorSampleCounts = sample_counts,
855 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
856 .sampledImageDepthSampleCounts = sample_counts,
857 .sampledImageStencilSampleCounts = sample_counts,
858 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
859 .maxSampleMaskWords = 1,
860 .timestampComputeAndGraphics = true,
861 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
862 .maxClipDistances = 8,
863 .maxCullDistances = 8,
864 .maxCombinedClipAndCullDistances = 8,
865 .discreteQueuePriorities = 1,
866 .pointSizeRange = { 0.125, 255.875 },
867 .lineWidthRange = { 0.0, 7.9921875 },
868 .pointSizeGranularity = (1.0 / 8.0),
869 .lineWidthGranularity = (1.0 / 128.0),
870 .strictLines = false, /* FINISHME */
871 .standardSampleLocations = true,
872 .optimalBufferCopyOffsetAlignment = 128,
873 .optimalBufferCopyRowPitchAlignment = 128,
874 .nonCoherentAtomSize = 64,
875 };
876
877 *pProperties = (VkPhysicalDeviceProperties) {
878 .apiVersion = radv_physical_device_api_version(pdevice),
879 .driverVersion = vk_get_driver_version(),
880 .vendorID = ATI_VENDOR_ID,
881 .deviceID = pdevice->rad_info.pci_id,
882 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
883 .limits = limits,
884 .sparseProperties = {0},
885 };
886
887 strcpy(pProperties->deviceName, pdevice->name);
888 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
889 }
890
891 void radv_GetPhysicalDeviceProperties2(
892 VkPhysicalDevice physicalDevice,
893 VkPhysicalDeviceProperties2KHR *pProperties)
894 {
895 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
896 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
897
898 vk_foreach_struct(ext, pProperties->pNext) {
899 switch (ext->sType) {
900 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
901 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
902 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
903 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
904 break;
905 }
906 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
907 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
908 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
909 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
910 properties->deviceLUIDValid = false;
911 break;
912 }
913 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
914 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
915 properties->maxMultiviewViewCount = MAX_VIEWS;
916 properties->maxMultiviewInstanceIndex = INT_MAX;
917 break;
918 }
919 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
920 VkPhysicalDevicePointClippingPropertiesKHR *properties =
921 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
922 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
926 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
927 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
928 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
932 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
933 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
934 properties->minImportedHostPointerAlignment = 4096;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
938 VkPhysicalDeviceSubgroupProperties *properties =
939 (VkPhysicalDeviceSubgroupProperties*)ext;
940 properties->subgroupSize = 64;
941 properties->supportedStages = VK_SHADER_STAGE_ALL;
942 properties->supportedOperations = VK_SUBGROUP_FEATURE_BASIC_BIT;
943 properties->quadOperationsInAllStages = false;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
947 VkPhysicalDeviceMaintenance3Properties *properties =
948 (VkPhysicalDeviceMaintenance3Properties*)ext;
949 /* Make sure everything is addressable by a signed 32-bit int, and
950 * our largest descriptors are 96 bytes. */
951 properties->maxPerSetDescriptors = (1ull << 31) / 96;
952 /* Our buffer size fields allow only this much */
953 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
957 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
958 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
959 /* GFX6-8 only support single channel min/max filter. */
960 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
961 properties->filterMinmaxSingleComponentFormats = true;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
965 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
966 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
967
968 /* Shader engines. */
969 properties->shaderEngineCount =
970 pdevice->rad_info.max_se;
971 properties->shaderArraysPerEngineCount =
972 pdevice->rad_info.max_sh_per_se;
973 properties->computeUnitsPerShaderArray =
974 pdevice->rad_info.num_good_compute_units /
975 (pdevice->rad_info.max_se *
976 pdevice->rad_info.max_sh_per_se);
977 properties->simdPerComputeUnit = 4;
978 properties->wavefrontsPerSimd =
979 pdevice->rad_info.family == CHIP_TONGA ||
980 pdevice->rad_info.family == CHIP_ICELAND ||
981 pdevice->rad_info.family == CHIP_POLARIS10 ||
982 pdevice->rad_info.family == CHIP_POLARIS11 ||
983 pdevice->rad_info.family == CHIP_POLARIS12 ? 8 : 10;
984 properties->wavefrontSize = 64;
985
986 /* SGPR. */
987 properties->sgprsPerSimd =
988 radv_get_num_physical_sgprs(pdevice);
989 properties->minSgprAllocation =
990 pdevice->rad_info.chip_class >= VI ? 16 : 8;
991 properties->maxSgprAllocation =
992 pdevice->rad_info.family == CHIP_TONGA ||
993 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
994 properties->sgprAllocationGranularity =
995 pdevice->rad_info.chip_class >= VI ? 16 : 8;
996
997 /* VGPR. */
998 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
999 properties->minVgprAllocation = 4;
1000 properties->maxVgprAllocation = 256;
1001 properties->vgprAllocationGranularity = 4;
1002 break;
1003 }
1004 default:
1005 break;
1006 }
1007 }
1008 }
1009
1010 static void radv_get_physical_device_queue_family_properties(
1011 struct radv_physical_device* pdevice,
1012 uint32_t* pCount,
1013 VkQueueFamilyProperties** pQueueFamilyProperties)
1014 {
1015 int num_queue_families = 1;
1016 int idx;
1017 if (pdevice->rad_info.num_compute_rings > 0 &&
1018 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1019 num_queue_families++;
1020
1021 if (pQueueFamilyProperties == NULL) {
1022 *pCount = num_queue_families;
1023 return;
1024 }
1025
1026 if (!*pCount)
1027 return;
1028
1029 idx = 0;
1030 if (*pCount >= 1) {
1031 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1032 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1033 VK_QUEUE_COMPUTE_BIT |
1034 VK_QUEUE_TRANSFER_BIT |
1035 VK_QUEUE_SPARSE_BINDING_BIT,
1036 .queueCount = 1,
1037 .timestampValidBits = 64,
1038 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1039 };
1040 idx++;
1041 }
1042
1043 if (pdevice->rad_info.num_compute_rings > 0 &&
1044 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1045 if (*pCount > idx) {
1046 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1047 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1048 VK_QUEUE_TRANSFER_BIT |
1049 VK_QUEUE_SPARSE_BINDING_BIT,
1050 .queueCount = pdevice->rad_info.num_compute_rings,
1051 .timestampValidBits = 64,
1052 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1053 };
1054 idx++;
1055 }
1056 }
1057 *pCount = idx;
1058 }
1059
1060 void radv_GetPhysicalDeviceQueueFamilyProperties(
1061 VkPhysicalDevice physicalDevice,
1062 uint32_t* pCount,
1063 VkQueueFamilyProperties* pQueueFamilyProperties)
1064 {
1065 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1066 if (!pQueueFamilyProperties) {
1067 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1068 return;
1069 }
1070 VkQueueFamilyProperties *properties[] = {
1071 pQueueFamilyProperties + 0,
1072 pQueueFamilyProperties + 1,
1073 pQueueFamilyProperties + 2,
1074 };
1075 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1076 assert(*pCount <= 3);
1077 }
1078
1079 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1080 VkPhysicalDevice physicalDevice,
1081 uint32_t* pCount,
1082 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1083 {
1084 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1085 if (!pQueueFamilyProperties) {
1086 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1087 return;
1088 }
1089 VkQueueFamilyProperties *properties[] = {
1090 &pQueueFamilyProperties[0].queueFamilyProperties,
1091 &pQueueFamilyProperties[1].queueFamilyProperties,
1092 &pQueueFamilyProperties[2].queueFamilyProperties,
1093 };
1094 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1095 assert(*pCount <= 3);
1096 }
1097
1098 void radv_GetPhysicalDeviceMemoryProperties(
1099 VkPhysicalDevice physicalDevice,
1100 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1101 {
1102 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1103
1104 *pMemoryProperties = physical_device->memory_properties;
1105 }
1106
1107 void radv_GetPhysicalDeviceMemoryProperties2(
1108 VkPhysicalDevice physicalDevice,
1109 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1110 {
1111 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1112 &pMemoryProperties->memoryProperties);
1113 }
1114
1115 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1116 VkDevice _device,
1117 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1118 const void *pHostPointer,
1119 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1120 {
1121 RADV_FROM_HANDLE(radv_device, device, _device);
1122
1123 switch (handleType)
1124 {
1125 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1126 const struct radv_physical_device *physical_device = device->physical_device;
1127 uint32_t memoryTypeBits = 0;
1128 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1129 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1130 memoryTypeBits = (1 << i);
1131 break;
1132 }
1133 }
1134 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1135 return VK_SUCCESS;
1136 }
1137 default:
1138 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1139 }
1140 }
1141
1142 static enum radeon_ctx_priority
1143 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1144 {
1145 /* Default to MEDIUM when a specific global priority isn't requested */
1146 if (!pObj)
1147 return RADEON_CTX_PRIORITY_MEDIUM;
1148
1149 switch(pObj->globalPriority) {
1150 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1151 return RADEON_CTX_PRIORITY_REALTIME;
1152 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1153 return RADEON_CTX_PRIORITY_HIGH;
1154 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1155 return RADEON_CTX_PRIORITY_MEDIUM;
1156 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1157 return RADEON_CTX_PRIORITY_LOW;
1158 default:
1159 unreachable("Illegal global priority value");
1160 return RADEON_CTX_PRIORITY_INVALID;
1161 }
1162 }
1163
1164 static int
1165 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1166 uint32_t queue_family_index, int idx,
1167 VkDeviceQueueCreateFlags flags,
1168 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1169 {
1170 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1171 queue->device = device;
1172 queue->queue_family_index = queue_family_index;
1173 queue->queue_idx = idx;
1174 queue->priority = radv_get_queue_global_priority(global_priority);
1175 queue->flags = flags;
1176
1177 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1178 if (!queue->hw_ctx)
1179 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1180
1181 return VK_SUCCESS;
1182 }
1183
1184 static void
1185 radv_queue_finish(struct radv_queue *queue)
1186 {
1187 if (queue->hw_ctx)
1188 queue->device->ws->ctx_destroy(queue->hw_ctx);
1189
1190 if (queue->initial_full_flush_preamble_cs)
1191 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1192 if (queue->initial_preamble_cs)
1193 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1194 if (queue->continue_preamble_cs)
1195 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1196 if (queue->descriptor_bo)
1197 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1198 if (queue->scratch_bo)
1199 queue->device->ws->buffer_destroy(queue->scratch_bo);
1200 if (queue->esgs_ring_bo)
1201 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1202 if (queue->gsvs_ring_bo)
1203 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1204 if (queue->tess_rings_bo)
1205 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1206 if (queue->compute_scratch_bo)
1207 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1208 }
1209
1210 static void
1211 radv_device_init_gs_info(struct radv_device *device)
1212 {
1213 switch (device->physical_device->rad_info.family) {
1214 case CHIP_OLAND:
1215 case CHIP_HAINAN:
1216 case CHIP_KAVERI:
1217 case CHIP_KABINI:
1218 case CHIP_MULLINS:
1219 case CHIP_ICELAND:
1220 case CHIP_CARRIZO:
1221 case CHIP_STONEY:
1222 device->gs_table_depth = 16;
1223 return;
1224 case CHIP_TAHITI:
1225 case CHIP_PITCAIRN:
1226 case CHIP_VERDE:
1227 case CHIP_BONAIRE:
1228 case CHIP_HAWAII:
1229 case CHIP_TONGA:
1230 case CHIP_FIJI:
1231 case CHIP_POLARIS10:
1232 case CHIP_POLARIS11:
1233 case CHIP_POLARIS12:
1234 case CHIP_VEGA10:
1235 case CHIP_VEGA12:
1236 case CHIP_RAVEN:
1237 device->gs_table_depth = 32;
1238 return;
1239 default:
1240 unreachable("unknown GPU");
1241 }
1242 }
1243
1244 static int radv_get_device_extension_index(const char *name)
1245 {
1246 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1247 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1248 return i;
1249 }
1250 return -1;
1251 }
1252
1253 VkResult radv_CreateDevice(
1254 VkPhysicalDevice physicalDevice,
1255 const VkDeviceCreateInfo* pCreateInfo,
1256 const VkAllocationCallbacks* pAllocator,
1257 VkDevice* pDevice)
1258 {
1259 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1260 VkResult result;
1261 struct radv_device *device;
1262
1263 bool keep_shader_info = false;
1264
1265 /* Check enabled features */
1266 if (pCreateInfo->pEnabledFeatures) {
1267 VkPhysicalDeviceFeatures supported_features;
1268 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1269 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1270 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1271 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1272 for (uint32_t i = 0; i < num_features; i++) {
1273 if (enabled_feature[i] && !supported_feature[i])
1274 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1275 }
1276 }
1277
1278 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1279 sizeof(*device), 8,
1280 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1281 if (!device)
1282 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1283
1284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1285 device->instance = physical_device->instance;
1286 device->physical_device = physical_device;
1287
1288 device->ws = physical_device->ws;
1289 if (pAllocator)
1290 device->alloc = *pAllocator;
1291 else
1292 device->alloc = physical_device->instance->alloc;
1293
1294 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1295 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1296 int index = radv_get_device_extension_index(ext_name);
1297 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1298 vk_free(&device->alloc, device);
1299 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1300 }
1301
1302 device->enabled_extensions.extensions[index] = true;
1303 }
1304
1305 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1306
1307 mtx_init(&device->shader_slab_mutex, mtx_plain);
1308 list_inithead(&device->shader_slabs);
1309
1310 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1311 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1312 uint32_t qfi = queue_create->queueFamilyIndex;
1313 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1314 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1315
1316 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1317
1318 device->queues[qfi] = vk_alloc(&device->alloc,
1319 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1320 if (!device->queues[qfi]) {
1321 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1322 goto fail;
1323 }
1324
1325 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1326
1327 device->queue_count[qfi] = queue_create->queueCount;
1328
1329 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1330 result = radv_queue_init(device, &device->queues[qfi][q],
1331 qfi, q, queue_create->flags,
1332 global_priority);
1333 if (result != VK_SUCCESS)
1334 goto fail;
1335 }
1336 }
1337
1338 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1339 (device->instance->perftest_flags & RADV_PERFTEST_BINNING);
1340
1341 /* Disabled and not implemented for now. */
1342 device->dfsm_allowed = device->pbb_allowed && false;
1343
1344 #ifdef ANDROID
1345 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1346 #endif
1347
1348 device->llvm_supports_spill = true;
1349
1350 /* The maximum number of scratch waves. Scratch space isn't divided
1351 * evenly between CUs. The number is only a function of the number of CUs.
1352 * We can decrease the constant to decrease the scratch buffer size.
1353 *
1354 * sctx->scratch_waves must be >= the maximum posible size of
1355 * 1 threadgroup, so that the hw doesn't hang from being unable
1356 * to start any.
1357 *
1358 * The recommended value is 4 per CU at most. Higher numbers don't
1359 * bring much benefit, but they still occupy chip resources (think
1360 * async compute). I've seen ~2% performance difference between 4 and 32.
1361 */
1362 uint32_t max_threads_per_block = 2048;
1363 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1364 max_threads_per_block / 64);
1365
1366 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1367
1368 if (device->physical_device->rad_info.chip_class >= CIK) {
1369 /* If the KMD allows it (there is a KMD hw register for it),
1370 * allow launching waves out-of-order.
1371 */
1372 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1373 }
1374
1375 radv_device_init_gs_info(device);
1376
1377 device->tess_offchip_block_dw_size =
1378 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1379 device->has_distributed_tess =
1380 device->physical_device->rad_info.chip_class >= VI &&
1381 device->physical_device->rad_info.max_se >= 2;
1382
1383 if (getenv("RADV_TRACE_FILE")) {
1384 const char *filename = getenv("RADV_TRACE_FILE");
1385
1386 keep_shader_info = true;
1387
1388 if (!radv_init_trace(device))
1389 goto fail;
1390
1391 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1392 radv_dump_enabled_options(device, stderr);
1393 }
1394
1395 device->keep_shader_info = keep_shader_info;
1396
1397 result = radv_device_init_meta(device);
1398 if (result != VK_SUCCESS)
1399 goto fail;
1400
1401 radv_device_init_msaa(device);
1402
1403 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1404 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1405 switch (family) {
1406 case RADV_QUEUE_GENERAL:
1407 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1408 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1409 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1410 break;
1411 case RADV_QUEUE_COMPUTE:
1412 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1413 radeon_emit(device->empty_cs[family], 0);
1414 break;
1415 }
1416 device->ws->cs_finalize(device->empty_cs[family]);
1417 }
1418
1419 if (device->physical_device->rad_info.chip_class >= CIK)
1420 cik_create_gfx_config(device);
1421
1422 VkPipelineCacheCreateInfo ci;
1423 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1424 ci.pNext = NULL;
1425 ci.flags = 0;
1426 ci.pInitialData = NULL;
1427 ci.initialDataSize = 0;
1428 VkPipelineCache pc;
1429 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1430 &ci, NULL, &pc);
1431 if (result != VK_SUCCESS)
1432 goto fail_meta;
1433
1434 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1435
1436 *pDevice = radv_device_to_handle(device);
1437 return VK_SUCCESS;
1438
1439 fail_meta:
1440 radv_device_finish_meta(device);
1441 fail:
1442 if (device->trace_bo)
1443 device->ws->buffer_destroy(device->trace_bo);
1444
1445 if (device->gfx_init)
1446 device->ws->buffer_destroy(device->gfx_init);
1447
1448 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1449 for (unsigned q = 0; q < device->queue_count[i]; q++)
1450 radv_queue_finish(&device->queues[i][q]);
1451 if (device->queue_count[i])
1452 vk_free(&device->alloc, device->queues[i]);
1453 }
1454
1455 vk_free(&device->alloc, device);
1456 return result;
1457 }
1458
1459 void radv_DestroyDevice(
1460 VkDevice _device,
1461 const VkAllocationCallbacks* pAllocator)
1462 {
1463 RADV_FROM_HANDLE(radv_device, device, _device);
1464
1465 if (!device)
1466 return;
1467
1468 if (device->trace_bo)
1469 device->ws->buffer_destroy(device->trace_bo);
1470
1471 if (device->gfx_init)
1472 device->ws->buffer_destroy(device->gfx_init);
1473
1474 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1475 for (unsigned q = 0; q < device->queue_count[i]; q++)
1476 radv_queue_finish(&device->queues[i][q]);
1477 if (device->queue_count[i])
1478 vk_free(&device->alloc, device->queues[i]);
1479 if (device->empty_cs[i])
1480 device->ws->cs_destroy(device->empty_cs[i]);
1481 }
1482 radv_device_finish_meta(device);
1483
1484 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1485 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1486
1487 radv_destroy_shader_slabs(device);
1488
1489 vk_free(&device->alloc, device);
1490 }
1491
1492 VkResult radv_EnumerateInstanceLayerProperties(
1493 uint32_t* pPropertyCount,
1494 VkLayerProperties* pProperties)
1495 {
1496 if (pProperties == NULL) {
1497 *pPropertyCount = 0;
1498 return VK_SUCCESS;
1499 }
1500
1501 /* None supported at this time */
1502 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1503 }
1504
1505 VkResult radv_EnumerateDeviceLayerProperties(
1506 VkPhysicalDevice physicalDevice,
1507 uint32_t* pPropertyCount,
1508 VkLayerProperties* pProperties)
1509 {
1510 if (pProperties == NULL) {
1511 *pPropertyCount = 0;
1512 return VK_SUCCESS;
1513 }
1514
1515 /* None supported at this time */
1516 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1517 }
1518
1519 void radv_GetDeviceQueue2(
1520 VkDevice _device,
1521 const VkDeviceQueueInfo2* pQueueInfo,
1522 VkQueue* pQueue)
1523 {
1524 RADV_FROM_HANDLE(radv_device, device, _device);
1525 struct radv_queue *queue;
1526
1527 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1528 if (pQueueInfo->flags != queue->flags) {
1529 /* From the Vulkan 1.1.70 spec:
1530 *
1531 * "The queue returned by vkGetDeviceQueue2 must have the same
1532 * flags value from this structure as that used at device
1533 * creation time in a VkDeviceQueueCreateInfo instance. If no
1534 * matching flags were specified at device creation time then
1535 * pQueue will return VK_NULL_HANDLE."
1536 */
1537 *pQueue = VK_NULL_HANDLE;
1538 return;
1539 }
1540
1541 *pQueue = radv_queue_to_handle(queue);
1542 }
1543
1544 void radv_GetDeviceQueue(
1545 VkDevice _device,
1546 uint32_t queueFamilyIndex,
1547 uint32_t queueIndex,
1548 VkQueue* pQueue)
1549 {
1550 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1551 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1552 .queueFamilyIndex = queueFamilyIndex,
1553 .queueIndex = queueIndex
1554 };
1555
1556 radv_GetDeviceQueue2(_device, &info, pQueue);
1557 }
1558
1559 static void
1560 fill_geom_tess_rings(struct radv_queue *queue,
1561 uint32_t *map,
1562 bool add_sample_positions,
1563 uint32_t esgs_ring_size,
1564 struct radeon_winsys_bo *esgs_ring_bo,
1565 uint32_t gsvs_ring_size,
1566 struct radeon_winsys_bo *gsvs_ring_bo,
1567 uint32_t tess_factor_ring_size,
1568 uint32_t tess_offchip_ring_offset,
1569 uint32_t tess_offchip_ring_size,
1570 struct radeon_winsys_bo *tess_rings_bo)
1571 {
1572 uint64_t esgs_va = 0, gsvs_va = 0;
1573 uint64_t tess_va = 0, tess_offchip_va = 0;
1574 uint32_t *desc = &map[4];
1575
1576 if (esgs_ring_bo)
1577 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1578 if (gsvs_ring_bo)
1579 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1580 if (tess_rings_bo) {
1581 tess_va = radv_buffer_get_va(tess_rings_bo);
1582 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1583 }
1584
1585 /* stride 0, num records - size, add tid, swizzle, elsize4,
1586 index stride 64 */
1587 desc[0] = esgs_va;
1588 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1589 S_008F04_STRIDE(0) |
1590 S_008F04_SWIZZLE_ENABLE(true);
1591 desc[2] = esgs_ring_size;
1592 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1593 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1594 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1595 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1596 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1597 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1598 S_008F0C_ELEMENT_SIZE(1) |
1599 S_008F0C_INDEX_STRIDE(3) |
1600 S_008F0C_ADD_TID_ENABLE(true);
1601
1602 desc += 4;
1603 /* GS entry for ES->GS ring */
1604 /* stride 0, num records - size, elsize0,
1605 index stride 0 */
1606 desc[0] = esgs_va;
1607 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1608 S_008F04_STRIDE(0) |
1609 S_008F04_SWIZZLE_ENABLE(false);
1610 desc[2] = esgs_ring_size;
1611 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1612 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1613 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1614 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1615 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1616 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1617 S_008F0C_ELEMENT_SIZE(0) |
1618 S_008F0C_INDEX_STRIDE(0) |
1619 S_008F0C_ADD_TID_ENABLE(false);
1620
1621 desc += 4;
1622 /* VS entry for GS->VS ring */
1623 /* stride 0, num records - size, elsize0,
1624 index stride 0 */
1625 desc[0] = gsvs_va;
1626 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1627 S_008F04_STRIDE(0) |
1628 S_008F04_SWIZZLE_ENABLE(false);
1629 desc[2] = gsvs_ring_size;
1630 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1631 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1632 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1633 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1634 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1635 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1636 S_008F0C_ELEMENT_SIZE(0) |
1637 S_008F0C_INDEX_STRIDE(0) |
1638 S_008F0C_ADD_TID_ENABLE(false);
1639 desc += 4;
1640
1641 /* stride gsvs_itemsize, num records 64
1642 elsize 4, index stride 16 */
1643 /* shader will patch stride and desc[2] */
1644 desc[0] = gsvs_va;
1645 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1646 S_008F04_STRIDE(0) |
1647 S_008F04_SWIZZLE_ENABLE(true);
1648 desc[2] = 0;
1649 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1650 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1651 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1652 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1653 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1654 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1655 S_008F0C_ELEMENT_SIZE(1) |
1656 S_008F0C_INDEX_STRIDE(1) |
1657 S_008F0C_ADD_TID_ENABLE(true);
1658 desc += 4;
1659
1660 desc[0] = tess_va;
1661 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1662 S_008F04_STRIDE(0) |
1663 S_008F04_SWIZZLE_ENABLE(false);
1664 desc[2] = tess_factor_ring_size;
1665 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1666 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1667 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1668 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1669 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1670 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1671 S_008F0C_ELEMENT_SIZE(0) |
1672 S_008F0C_INDEX_STRIDE(0) |
1673 S_008F0C_ADD_TID_ENABLE(false);
1674 desc += 4;
1675
1676 desc[0] = tess_offchip_va;
1677 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1678 S_008F04_STRIDE(0) |
1679 S_008F04_SWIZZLE_ENABLE(false);
1680 desc[2] = tess_offchip_ring_size;
1681 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1682 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1683 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1684 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1685 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1686 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1687 S_008F0C_ELEMENT_SIZE(0) |
1688 S_008F0C_INDEX_STRIDE(0) |
1689 S_008F0C_ADD_TID_ENABLE(false);
1690 desc += 4;
1691
1692 /* add sample positions after all rings */
1693 memcpy(desc, queue->device->sample_locations_1x, 8);
1694 desc += 2;
1695 memcpy(desc, queue->device->sample_locations_2x, 16);
1696 desc += 4;
1697 memcpy(desc, queue->device->sample_locations_4x, 32);
1698 desc += 8;
1699 memcpy(desc, queue->device->sample_locations_8x, 64);
1700 desc += 16;
1701 memcpy(desc, queue->device->sample_locations_16x, 128);
1702 }
1703
1704 static unsigned
1705 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1706 {
1707 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1708 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1709 device->physical_device->rad_info.family != CHIP_STONEY;
1710 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1711 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1712 device->physical_device->rad_info.max_se;
1713 unsigned offchip_granularity;
1714 unsigned hs_offchip_param;
1715 switch (device->tess_offchip_block_dw_size) {
1716 default:
1717 assert(0);
1718 /* fall through */
1719 case 8192:
1720 offchip_granularity = V_03093C_X_8K_DWORDS;
1721 break;
1722 case 4096:
1723 offchip_granularity = V_03093C_X_4K_DWORDS;
1724 break;
1725 }
1726
1727 switch (device->physical_device->rad_info.chip_class) {
1728 case SI:
1729 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1730 break;
1731 case CIK:
1732 case VI:
1733 case GFX9:
1734 default:
1735 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1736 break;
1737 }
1738
1739 *max_offchip_buffers_p = max_offchip_buffers;
1740 if (device->physical_device->rad_info.chip_class >= CIK) {
1741 if (device->physical_device->rad_info.chip_class >= VI)
1742 --max_offchip_buffers;
1743 hs_offchip_param =
1744 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1745 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1746 } else {
1747 hs_offchip_param =
1748 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1749 }
1750 return hs_offchip_param;
1751 }
1752
1753 static VkResult
1754 radv_get_preamble_cs(struct radv_queue *queue,
1755 uint32_t scratch_size,
1756 uint32_t compute_scratch_size,
1757 uint32_t esgs_ring_size,
1758 uint32_t gsvs_ring_size,
1759 bool needs_tess_rings,
1760 bool needs_sample_positions,
1761 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1762 struct radeon_winsys_cs **initial_preamble_cs,
1763 struct radeon_winsys_cs **continue_preamble_cs)
1764 {
1765 struct radeon_winsys_bo *scratch_bo = NULL;
1766 struct radeon_winsys_bo *descriptor_bo = NULL;
1767 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1768 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1769 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1770 struct radeon_winsys_bo *tess_rings_bo = NULL;
1771 struct radeon_winsys_cs *dest_cs[3] = {0};
1772 bool add_tess_rings = false, add_sample_positions = false;
1773 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1774 unsigned max_offchip_buffers;
1775 unsigned hs_offchip_param = 0;
1776 unsigned tess_offchip_ring_offset;
1777 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1778 if (!queue->has_tess_rings) {
1779 if (needs_tess_rings)
1780 add_tess_rings = true;
1781 }
1782 if (!queue->has_sample_positions) {
1783 if (needs_sample_positions)
1784 add_sample_positions = true;
1785 }
1786 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1787 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1788 &max_offchip_buffers);
1789 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
1790 tess_offchip_ring_size = max_offchip_buffers *
1791 queue->device->tess_offchip_block_dw_size * 4;
1792
1793 if (scratch_size <= queue->scratch_size &&
1794 compute_scratch_size <= queue->compute_scratch_size &&
1795 esgs_ring_size <= queue->esgs_ring_size &&
1796 gsvs_ring_size <= queue->gsvs_ring_size &&
1797 !add_tess_rings && !add_sample_positions &&
1798 queue->initial_preamble_cs) {
1799 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1800 *initial_preamble_cs = queue->initial_preamble_cs;
1801 *continue_preamble_cs = queue->continue_preamble_cs;
1802 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1803 *continue_preamble_cs = NULL;
1804 return VK_SUCCESS;
1805 }
1806
1807 if (scratch_size > queue->scratch_size) {
1808 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1809 scratch_size,
1810 4096,
1811 RADEON_DOMAIN_VRAM,
1812 ring_bo_flags);
1813 if (!scratch_bo)
1814 goto fail;
1815 } else
1816 scratch_bo = queue->scratch_bo;
1817
1818 if (compute_scratch_size > queue->compute_scratch_size) {
1819 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1820 compute_scratch_size,
1821 4096,
1822 RADEON_DOMAIN_VRAM,
1823 ring_bo_flags);
1824 if (!compute_scratch_bo)
1825 goto fail;
1826
1827 } else
1828 compute_scratch_bo = queue->compute_scratch_bo;
1829
1830 if (esgs_ring_size > queue->esgs_ring_size) {
1831 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1832 esgs_ring_size,
1833 4096,
1834 RADEON_DOMAIN_VRAM,
1835 ring_bo_flags);
1836 if (!esgs_ring_bo)
1837 goto fail;
1838 } else {
1839 esgs_ring_bo = queue->esgs_ring_bo;
1840 esgs_ring_size = queue->esgs_ring_size;
1841 }
1842
1843 if (gsvs_ring_size > queue->gsvs_ring_size) {
1844 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1845 gsvs_ring_size,
1846 4096,
1847 RADEON_DOMAIN_VRAM,
1848 ring_bo_flags);
1849 if (!gsvs_ring_bo)
1850 goto fail;
1851 } else {
1852 gsvs_ring_bo = queue->gsvs_ring_bo;
1853 gsvs_ring_size = queue->gsvs_ring_size;
1854 }
1855
1856 if (add_tess_rings) {
1857 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
1858 tess_offchip_ring_offset + tess_offchip_ring_size,
1859 256,
1860 RADEON_DOMAIN_VRAM,
1861 ring_bo_flags);
1862 if (!tess_rings_bo)
1863 goto fail;
1864 } else {
1865 tess_rings_bo = queue->tess_rings_bo;
1866 }
1867
1868 if (scratch_bo != queue->scratch_bo ||
1869 esgs_ring_bo != queue->esgs_ring_bo ||
1870 gsvs_ring_bo != queue->gsvs_ring_bo ||
1871 tess_rings_bo != queue->tess_rings_bo ||
1872 add_sample_positions) {
1873 uint32_t size = 0;
1874 if (gsvs_ring_bo || esgs_ring_bo ||
1875 tess_rings_bo || add_sample_positions) {
1876 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1877 if (add_sample_positions)
1878 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1879 }
1880 else if (scratch_bo)
1881 size = 8; /* 2 dword */
1882
1883 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1884 size,
1885 4096,
1886 RADEON_DOMAIN_VRAM,
1887 RADEON_FLAG_CPU_ACCESS |
1888 RADEON_FLAG_NO_INTERPROCESS_SHARING |
1889 RADEON_FLAG_READ_ONLY);
1890 if (!descriptor_bo)
1891 goto fail;
1892 } else
1893 descriptor_bo = queue->descriptor_bo;
1894
1895 for(int i = 0; i < 3; ++i) {
1896 struct radeon_winsys_cs *cs = NULL;
1897 cs = queue->device->ws->cs_create(queue->device->ws,
1898 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1899 if (!cs)
1900 goto fail;
1901
1902 dest_cs[i] = cs;
1903
1904 if (scratch_bo)
1905 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1906
1907 if (esgs_ring_bo)
1908 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1909
1910 if (gsvs_ring_bo)
1911 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1912
1913 if (tess_rings_bo)
1914 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo, 8);
1915
1916 if (descriptor_bo)
1917 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1918
1919 if (descriptor_bo != queue->descriptor_bo) {
1920 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1921
1922 if (scratch_bo) {
1923 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1924 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1925 S_008F04_SWIZZLE_ENABLE(1);
1926 map[0] = scratch_va;
1927 map[1] = rsrc1;
1928 }
1929
1930 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
1931 add_sample_positions)
1932 fill_geom_tess_rings(queue, map, add_sample_positions,
1933 esgs_ring_size, esgs_ring_bo,
1934 gsvs_ring_size, gsvs_ring_bo,
1935 tess_factor_ring_size,
1936 tess_offchip_ring_offset,
1937 tess_offchip_ring_size,
1938 tess_rings_bo);
1939
1940 queue->device->ws->buffer_unmap(descriptor_bo);
1941 }
1942
1943 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
1944 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1945 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1946 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1947 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1948 }
1949
1950 if (esgs_ring_bo || gsvs_ring_bo) {
1951 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1952 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1953 radeon_emit(cs, esgs_ring_size >> 8);
1954 radeon_emit(cs, gsvs_ring_size >> 8);
1955 } else {
1956 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1957 radeon_emit(cs, esgs_ring_size >> 8);
1958 radeon_emit(cs, gsvs_ring_size >> 8);
1959 }
1960 }
1961
1962 if (tess_rings_bo) {
1963 uint64_t tf_va = radv_buffer_get_va(tess_rings_bo);
1964 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1965 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1966 S_030938_SIZE(tess_factor_ring_size / 4));
1967 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1968 tf_va >> 8);
1969 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1970 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1971 S_030944_BASE_HI(tf_va >> 40));
1972 }
1973 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1974 } else {
1975 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1976 S_008988_SIZE(tess_factor_ring_size / 4));
1977 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1978 tf_va >> 8);
1979 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1980 hs_offchip_param);
1981 }
1982 }
1983
1984 if (descriptor_bo) {
1985 uint64_t va = radv_buffer_get_va(descriptor_bo);
1986 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1987 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1988 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1989 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1990 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1991
1992 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1993 radeon_set_sh_reg_seq(cs, regs[i], 2);
1994 radeon_emit(cs, va);
1995 radeon_emit(cs, va >> 32);
1996 }
1997 } else {
1998 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1999 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2000 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2001 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2002 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2003 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2004
2005 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2006 radeon_set_sh_reg_seq(cs, regs[i], 2);
2007 radeon_emit(cs, va);
2008 radeon_emit(cs, va >> 32);
2009 }
2010 }
2011 }
2012
2013 if (compute_scratch_bo) {
2014 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
2015 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2016 S_008F04_SWIZZLE_ENABLE(1);
2017
2018 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
2019
2020 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2021 radeon_emit(cs, scratch_va);
2022 radeon_emit(cs, rsrc1);
2023 }
2024
2025 if (i == 0) {
2026 si_cs_emit_cache_flush(cs,
2027 queue->device->physical_device->rad_info.chip_class,
2028 NULL, 0,
2029 queue->queue_family_index == RING_COMPUTE &&
2030 queue->device->physical_device->rad_info.chip_class >= CIK,
2031 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2032 RADV_CMD_FLAG_INV_ICACHE |
2033 RADV_CMD_FLAG_INV_SMEM_L1 |
2034 RADV_CMD_FLAG_INV_VMEM_L1 |
2035 RADV_CMD_FLAG_INV_GLOBAL_L2);
2036 } else if (i == 1) {
2037 si_cs_emit_cache_flush(cs,
2038 queue->device->physical_device->rad_info.chip_class,
2039 NULL, 0,
2040 queue->queue_family_index == RING_COMPUTE &&
2041 queue->device->physical_device->rad_info.chip_class >= CIK,
2042 RADV_CMD_FLAG_INV_ICACHE |
2043 RADV_CMD_FLAG_INV_SMEM_L1 |
2044 RADV_CMD_FLAG_INV_VMEM_L1 |
2045 RADV_CMD_FLAG_INV_GLOBAL_L2);
2046 }
2047
2048 if (!queue->device->ws->cs_finalize(cs))
2049 goto fail;
2050 }
2051
2052 if (queue->initial_full_flush_preamble_cs)
2053 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2054
2055 if (queue->initial_preamble_cs)
2056 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2057
2058 if (queue->continue_preamble_cs)
2059 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2060
2061 queue->initial_full_flush_preamble_cs = dest_cs[0];
2062 queue->initial_preamble_cs = dest_cs[1];
2063 queue->continue_preamble_cs = dest_cs[2];
2064
2065 if (scratch_bo != queue->scratch_bo) {
2066 if (queue->scratch_bo)
2067 queue->device->ws->buffer_destroy(queue->scratch_bo);
2068 queue->scratch_bo = scratch_bo;
2069 queue->scratch_size = scratch_size;
2070 }
2071
2072 if (compute_scratch_bo != queue->compute_scratch_bo) {
2073 if (queue->compute_scratch_bo)
2074 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2075 queue->compute_scratch_bo = compute_scratch_bo;
2076 queue->compute_scratch_size = compute_scratch_size;
2077 }
2078
2079 if (esgs_ring_bo != queue->esgs_ring_bo) {
2080 if (queue->esgs_ring_bo)
2081 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2082 queue->esgs_ring_bo = esgs_ring_bo;
2083 queue->esgs_ring_size = esgs_ring_size;
2084 }
2085
2086 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2087 if (queue->gsvs_ring_bo)
2088 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2089 queue->gsvs_ring_bo = gsvs_ring_bo;
2090 queue->gsvs_ring_size = gsvs_ring_size;
2091 }
2092
2093 if (tess_rings_bo != queue->tess_rings_bo) {
2094 queue->tess_rings_bo = tess_rings_bo;
2095 queue->has_tess_rings = true;
2096 }
2097
2098 if (descriptor_bo != queue->descriptor_bo) {
2099 if (queue->descriptor_bo)
2100 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2101
2102 queue->descriptor_bo = descriptor_bo;
2103 }
2104
2105 if (add_sample_positions)
2106 queue->has_sample_positions = true;
2107
2108 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2109 *initial_preamble_cs = queue->initial_preamble_cs;
2110 *continue_preamble_cs = queue->continue_preamble_cs;
2111 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2112 *continue_preamble_cs = NULL;
2113 return VK_SUCCESS;
2114 fail:
2115 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2116 if (dest_cs[i])
2117 queue->device->ws->cs_destroy(dest_cs[i]);
2118 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2119 queue->device->ws->buffer_destroy(descriptor_bo);
2120 if (scratch_bo && scratch_bo != queue->scratch_bo)
2121 queue->device->ws->buffer_destroy(scratch_bo);
2122 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2123 queue->device->ws->buffer_destroy(compute_scratch_bo);
2124 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2125 queue->device->ws->buffer_destroy(esgs_ring_bo);
2126 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2127 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2128 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2129 queue->device->ws->buffer_destroy(tess_rings_bo);
2130 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2131 }
2132
2133 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
2134 int num_sems,
2135 const VkSemaphore *sems,
2136 VkFence _fence,
2137 bool reset_temp)
2138 {
2139 int syncobj_idx = 0, sem_idx = 0;
2140
2141 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2142 return VK_SUCCESS;
2143
2144 for (uint32_t i = 0; i < num_sems; i++) {
2145 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2146
2147 if (sem->temp_syncobj || sem->syncobj)
2148 counts->syncobj_count++;
2149 else
2150 counts->sem_count++;
2151 }
2152
2153 if (_fence != VK_NULL_HANDLE) {
2154 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2155 if (fence->temp_syncobj || fence->syncobj)
2156 counts->syncobj_count++;
2157 }
2158
2159 if (counts->syncobj_count) {
2160 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2161 if (!counts->syncobj)
2162 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2163 }
2164
2165 if (counts->sem_count) {
2166 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2167 if (!counts->sem) {
2168 free(counts->syncobj);
2169 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2170 }
2171 }
2172
2173 for (uint32_t i = 0; i < num_sems; i++) {
2174 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2175
2176 if (sem->temp_syncobj) {
2177 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2178 }
2179 else if (sem->syncobj)
2180 counts->syncobj[syncobj_idx++] = sem->syncobj;
2181 else {
2182 assert(sem->sem);
2183 counts->sem[sem_idx++] = sem->sem;
2184 }
2185 }
2186
2187 if (_fence != VK_NULL_HANDLE) {
2188 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2189 if (fence->temp_syncobj)
2190 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2191 else if (fence->syncobj)
2192 counts->syncobj[syncobj_idx++] = fence->syncobj;
2193 }
2194
2195 return VK_SUCCESS;
2196 }
2197
2198 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2199 {
2200 free(sem_info->wait.syncobj);
2201 free(sem_info->wait.sem);
2202 free(sem_info->signal.syncobj);
2203 free(sem_info->signal.sem);
2204 }
2205
2206
2207 static void radv_free_temp_syncobjs(struct radv_device *device,
2208 int num_sems,
2209 const VkSemaphore *sems)
2210 {
2211 for (uint32_t i = 0; i < num_sems; i++) {
2212 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2213
2214 if (sem->temp_syncobj) {
2215 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2216 sem->temp_syncobj = 0;
2217 }
2218 }
2219 }
2220
2221 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
2222 int num_wait_sems,
2223 const VkSemaphore *wait_sems,
2224 int num_signal_sems,
2225 const VkSemaphore *signal_sems,
2226 VkFence fence)
2227 {
2228 VkResult ret;
2229 memset(sem_info, 0, sizeof(*sem_info));
2230
2231 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2232 if (ret)
2233 return ret;
2234 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, fence, false);
2235 if (ret)
2236 radv_free_sem_info(sem_info);
2237
2238 /* caller can override these */
2239 sem_info->cs_emit_wait = true;
2240 sem_info->cs_emit_signal = true;
2241 return ret;
2242 }
2243
2244 /* Signals fence as soon as all the work currently put on queue is done. */
2245 static VkResult radv_signal_fence(struct radv_queue *queue,
2246 struct radv_fence *fence)
2247 {
2248 int ret;
2249 VkResult result;
2250 struct radv_winsys_sem_info sem_info;
2251
2252 result = radv_alloc_sem_info(&sem_info, 0, NULL, 0, NULL,
2253 radv_fence_to_handle(fence));
2254 if (result != VK_SUCCESS)
2255 return result;
2256
2257 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2258 &queue->device->empty_cs[queue->queue_family_index],
2259 1, NULL, NULL, &sem_info,
2260 false, fence->fence);
2261 radv_free_sem_info(&sem_info);
2262
2263 /* TODO: find a better error */
2264 if (ret)
2265 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2266
2267 return VK_SUCCESS;
2268 }
2269
2270 VkResult radv_QueueSubmit(
2271 VkQueue _queue,
2272 uint32_t submitCount,
2273 const VkSubmitInfo* pSubmits,
2274 VkFence _fence)
2275 {
2276 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2277 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2278 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2279 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2280 int ret;
2281 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2282 uint32_t scratch_size = 0;
2283 uint32_t compute_scratch_size = 0;
2284 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2285 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2286 VkResult result;
2287 bool fence_emitted = false;
2288 bool tess_rings_needed = false;
2289 bool sample_positions_needed = false;
2290
2291 /* Do this first so failing to allocate scratch buffers can't result in
2292 * partially executed submissions. */
2293 for (uint32_t i = 0; i < submitCount; i++) {
2294 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2295 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2296 pSubmits[i].pCommandBuffers[j]);
2297
2298 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2299 compute_scratch_size = MAX2(compute_scratch_size,
2300 cmd_buffer->compute_scratch_size_needed);
2301 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2302 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2303 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2304 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2305 }
2306 }
2307
2308 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2309 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2310 sample_positions_needed, &initial_flush_preamble_cs,
2311 &initial_preamble_cs, &continue_preamble_cs);
2312 if (result != VK_SUCCESS)
2313 return result;
2314
2315 for (uint32_t i = 0; i < submitCount; i++) {
2316 struct radeon_winsys_cs **cs_array;
2317 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2318 bool can_patch = true;
2319 uint32_t advance;
2320 struct radv_winsys_sem_info sem_info;
2321
2322 result = radv_alloc_sem_info(&sem_info,
2323 pSubmits[i].waitSemaphoreCount,
2324 pSubmits[i].pWaitSemaphores,
2325 pSubmits[i].signalSemaphoreCount,
2326 pSubmits[i].pSignalSemaphores,
2327 _fence);
2328 if (result != VK_SUCCESS)
2329 return result;
2330
2331 if (!pSubmits[i].commandBufferCount) {
2332 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2333 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2334 &queue->device->empty_cs[queue->queue_family_index],
2335 1, NULL, NULL,
2336 &sem_info,
2337 false, base_fence);
2338 if (ret) {
2339 radv_loge("failed to submit CS %d\n", i);
2340 abort();
2341 }
2342 fence_emitted = true;
2343 }
2344 radv_free_sem_info(&sem_info);
2345 continue;
2346 }
2347
2348 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2349 (pSubmits[i].commandBufferCount));
2350
2351 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2352 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2353 pSubmits[i].pCommandBuffers[j]);
2354 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2355
2356 cs_array[j] = cmd_buffer->cs;
2357 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2358 can_patch = false;
2359
2360 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2361 }
2362
2363 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2364 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2365 advance = MIN2(max_cs_submission,
2366 pSubmits[i].commandBufferCount - j);
2367
2368 if (queue->device->trace_bo)
2369 *queue->device->trace_id_ptr = 0;
2370
2371 sem_info.cs_emit_wait = j == 0;
2372 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2373
2374 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2375 advance, initial_preamble, continue_preamble_cs,
2376 &sem_info,
2377 can_patch, base_fence);
2378
2379 if (ret) {
2380 radv_loge("failed to submit CS %d\n", i);
2381 abort();
2382 }
2383 fence_emitted = true;
2384 if (queue->device->trace_bo) {
2385 radv_check_gpu_hangs(queue, cs_array[j]);
2386 }
2387 }
2388
2389 radv_free_temp_syncobjs(queue->device,
2390 pSubmits[i].waitSemaphoreCount,
2391 pSubmits[i].pWaitSemaphores);
2392 radv_free_sem_info(&sem_info);
2393 free(cs_array);
2394 }
2395
2396 if (fence) {
2397 if (!fence_emitted) {
2398 radv_signal_fence(queue, fence);
2399 }
2400 fence->submitted = true;
2401 }
2402
2403 return VK_SUCCESS;
2404 }
2405
2406 VkResult radv_QueueWaitIdle(
2407 VkQueue _queue)
2408 {
2409 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2410
2411 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2412 radv_queue_family_to_ring(queue->queue_family_index),
2413 queue->queue_idx);
2414 return VK_SUCCESS;
2415 }
2416
2417 VkResult radv_DeviceWaitIdle(
2418 VkDevice _device)
2419 {
2420 RADV_FROM_HANDLE(radv_device, device, _device);
2421
2422 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2423 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2424 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2425 }
2426 }
2427 return VK_SUCCESS;
2428 }
2429
2430 VkResult radv_EnumerateInstanceExtensionProperties(
2431 const char* pLayerName,
2432 uint32_t* pPropertyCount,
2433 VkExtensionProperties* pProperties)
2434 {
2435 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2436
2437 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2438 if (radv_supported_instance_extensions.extensions[i]) {
2439 vk_outarray_append(&out, prop) {
2440 *prop = radv_instance_extensions[i];
2441 }
2442 }
2443 }
2444
2445 return vk_outarray_status(&out);
2446 }
2447
2448 VkResult radv_EnumerateDeviceExtensionProperties(
2449 VkPhysicalDevice physicalDevice,
2450 const char* pLayerName,
2451 uint32_t* pPropertyCount,
2452 VkExtensionProperties* pProperties)
2453 {
2454 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2455 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2456
2457 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2458 if (device->supported_extensions.extensions[i]) {
2459 vk_outarray_append(&out, prop) {
2460 *prop = radv_device_extensions[i];
2461 }
2462 }
2463 }
2464
2465 return vk_outarray_status(&out);
2466 }
2467
2468 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2469 VkInstance _instance,
2470 const char* pName)
2471 {
2472 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2473
2474 return radv_lookup_entrypoint_checked(pName,
2475 instance ? instance->apiVersion : 0,
2476 instance ? &instance->enabled_extensions : NULL,
2477 NULL);
2478 }
2479
2480 /* The loader wants us to expose a second GetInstanceProcAddr function
2481 * to work around certain LD_PRELOAD issues seen in apps.
2482 */
2483 PUBLIC
2484 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2485 VkInstance instance,
2486 const char* pName);
2487
2488 PUBLIC
2489 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2490 VkInstance instance,
2491 const char* pName)
2492 {
2493 return radv_GetInstanceProcAddr(instance, pName);
2494 }
2495
2496 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2497 VkDevice _device,
2498 const char* pName)
2499 {
2500 RADV_FROM_HANDLE(radv_device, device, _device);
2501
2502 return radv_lookup_entrypoint_checked(pName,
2503 device->instance->apiVersion,
2504 &device->instance->enabled_extensions,
2505 &device->enabled_extensions);
2506 }
2507
2508 bool radv_get_memory_fd(struct radv_device *device,
2509 struct radv_device_memory *memory,
2510 int *pFD)
2511 {
2512 struct radeon_bo_metadata metadata;
2513
2514 if (memory->image) {
2515 radv_init_metadata(device, memory->image, &metadata);
2516 device->ws->buffer_set_metadata(memory->bo, &metadata);
2517 }
2518
2519 return device->ws->buffer_get_fd(device->ws, memory->bo,
2520 pFD);
2521 }
2522
2523 static VkResult radv_alloc_memory(struct radv_device *device,
2524 const VkMemoryAllocateInfo* pAllocateInfo,
2525 const VkAllocationCallbacks* pAllocator,
2526 VkDeviceMemory* pMem)
2527 {
2528 struct radv_device_memory *mem;
2529 VkResult result;
2530 enum radeon_bo_domain domain;
2531 uint32_t flags = 0;
2532 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2533
2534 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2535
2536 if (pAllocateInfo->allocationSize == 0) {
2537 /* Apparently, this is allowed */
2538 *pMem = VK_NULL_HANDLE;
2539 return VK_SUCCESS;
2540 }
2541
2542 const VkImportMemoryFdInfoKHR *import_info =
2543 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2544 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2545 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2546 const VkExportMemoryAllocateInfoKHR *export_info =
2547 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2548 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2549 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2550
2551 const struct wsi_memory_allocate_info *wsi_info =
2552 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2553
2554 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2555 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2556 if (mem == NULL)
2557 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2558
2559 if (wsi_info && wsi_info->implicit_sync)
2560 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2561
2562 if (dedicate_info) {
2563 mem->image = radv_image_from_handle(dedicate_info->image);
2564 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2565 } else {
2566 mem->image = NULL;
2567 mem->buffer = NULL;
2568 }
2569
2570 mem->user_ptr = NULL;
2571
2572 if (import_info) {
2573 assert(import_info->handleType ==
2574 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2575 import_info->handleType ==
2576 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2577 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2578 NULL, NULL);
2579 if (!mem->bo) {
2580 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2581 goto fail;
2582 } else {
2583 close(import_info->fd);
2584 goto out_success;
2585 }
2586 }
2587
2588 if (host_ptr_info) {
2589 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2590 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2591 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2592 pAllocateInfo->allocationSize);
2593 if (!mem->bo) {
2594 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2595 goto fail;
2596 } else {
2597 mem->user_ptr = host_ptr_info->pHostPointer;
2598 goto out_success;
2599 }
2600 }
2601
2602 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2603 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2604 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2605 domain = RADEON_DOMAIN_GTT;
2606 else
2607 domain = RADEON_DOMAIN_VRAM;
2608
2609 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2610 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2611 else
2612 flags |= RADEON_FLAG_CPU_ACCESS;
2613
2614 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2615 flags |= RADEON_FLAG_GTT_WC;
2616
2617 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2618 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2619
2620 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2621 domain, flags);
2622
2623 if (!mem->bo) {
2624 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2625 goto fail;
2626 }
2627 mem->type_index = mem_type_index;
2628 out_success:
2629 *pMem = radv_device_memory_to_handle(mem);
2630
2631 return VK_SUCCESS;
2632
2633 fail:
2634 vk_free2(&device->alloc, pAllocator, mem);
2635
2636 return result;
2637 }
2638
2639 VkResult radv_AllocateMemory(
2640 VkDevice _device,
2641 const VkMemoryAllocateInfo* pAllocateInfo,
2642 const VkAllocationCallbacks* pAllocator,
2643 VkDeviceMemory* pMem)
2644 {
2645 RADV_FROM_HANDLE(radv_device, device, _device);
2646 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2647 }
2648
2649 void radv_FreeMemory(
2650 VkDevice _device,
2651 VkDeviceMemory _mem,
2652 const VkAllocationCallbacks* pAllocator)
2653 {
2654 RADV_FROM_HANDLE(radv_device, device, _device);
2655 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2656
2657 if (mem == NULL)
2658 return;
2659
2660 device->ws->buffer_destroy(mem->bo);
2661 mem->bo = NULL;
2662
2663 vk_free2(&device->alloc, pAllocator, mem);
2664 }
2665
2666 VkResult radv_MapMemory(
2667 VkDevice _device,
2668 VkDeviceMemory _memory,
2669 VkDeviceSize offset,
2670 VkDeviceSize size,
2671 VkMemoryMapFlags flags,
2672 void** ppData)
2673 {
2674 RADV_FROM_HANDLE(radv_device, device, _device);
2675 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2676
2677 if (mem == NULL) {
2678 *ppData = NULL;
2679 return VK_SUCCESS;
2680 }
2681
2682 if (mem->user_ptr)
2683 *ppData = mem->user_ptr;
2684 else
2685 *ppData = device->ws->buffer_map(mem->bo);
2686
2687 if (*ppData) {
2688 *ppData += offset;
2689 return VK_SUCCESS;
2690 }
2691
2692 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2693 }
2694
2695 void radv_UnmapMemory(
2696 VkDevice _device,
2697 VkDeviceMemory _memory)
2698 {
2699 RADV_FROM_HANDLE(radv_device, device, _device);
2700 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2701
2702 if (mem == NULL)
2703 return;
2704
2705 if (mem->user_ptr == NULL)
2706 device->ws->buffer_unmap(mem->bo);
2707 }
2708
2709 VkResult radv_FlushMappedMemoryRanges(
2710 VkDevice _device,
2711 uint32_t memoryRangeCount,
2712 const VkMappedMemoryRange* pMemoryRanges)
2713 {
2714 return VK_SUCCESS;
2715 }
2716
2717 VkResult radv_InvalidateMappedMemoryRanges(
2718 VkDevice _device,
2719 uint32_t memoryRangeCount,
2720 const VkMappedMemoryRange* pMemoryRanges)
2721 {
2722 return VK_SUCCESS;
2723 }
2724
2725 void radv_GetBufferMemoryRequirements(
2726 VkDevice _device,
2727 VkBuffer _buffer,
2728 VkMemoryRequirements* pMemoryRequirements)
2729 {
2730 RADV_FROM_HANDLE(radv_device, device, _device);
2731 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2732
2733 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2734
2735 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2736 pMemoryRequirements->alignment = 4096;
2737 else
2738 pMemoryRequirements->alignment = 16;
2739
2740 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2741 }
2742
2743 void radv_GetBufferMemoryRequirements2(
2744 VkDevice device,
2745 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2746 VkMemoryRequirements2KHR* pMemoryRequirements)
2747 {
2748 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2749 &pMemoryRequirements->memoryRequirements);
2750 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2751 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2752 switch (ext->sType) {
2753 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2754 VkMemoryDedicatedRequirementsKHR *req =
2755 (VkMemoryDedicatedRequirementsKHR *) ext;
2756 req->requiresDedicatedAllocation = buffer->shareable;
2757 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2758 break;
2759 }
2760 default:
2761 break;
2762 }
2763 }
2764 }
2765
2766 void radv_GetImageMemoryRequirements(
2767 VkDevice _device,
2768 VkImage _image,
2769 VkMemoryRequirements* pMemoryRequirements)
2770 {
2771 RADV_FROM_HANDLE(radv_device, device, _device);
2772 RADV_FROM_HANDLE(radv_image, image, _image);
2773
2774 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2775
2776 pMemoryRequirements->size = image->size;
2777 pMemoryRequirements->alignment = image->alignment;
2778 }
2779
2780 void radv_GetImageMemoryRequirements2(
2781 VkDevice device,
2782 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2783 VkMemoryRequirements2KHR* pMemoryRequirements)
2784 {
2785 radv_GetImageMemoryRequirements(device, pInfo->image,
2786 &pMemoryRequirements->memoryRequirements);
2787
2788 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2789
2790 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2791 switch (ext->sType) {
2792 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2793 VkMemoryDedicatedRequirementsKHR *req =
2794 (VkMemoryDedicatedRequirementsKHR *) ext;
2795 req->requiresDedicatedAllocation = image->shareable;
2796 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2797 break;
2798 }
2799 default:
2800 break;
2801 }
2802 }
2803 }
2804
2805 void radv_GetImageSparseMemoryRequirements(
2806 VkDevice device,
2807 VkImage image,
2808 uint32_t* pSparseMemoryRequirementCount,
2809 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2810 {
2811 stub();
2812 }
2813
2814 void radv_GetImageSparseMemoryRequirements2(
2815 VkDevice device,
2816 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2817 uint32_t* pSparseMemoryRequirementCount,
2818 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2819 {
2820 stub();
2821 }
2822
2823 void radv_GetDeviceMemoryCommitment(
2824 VkDevice device,
2825 VkDeviceMemory memory,
2826 VkDeviceSize* pCommittedMemoryInBytes)
2827 {
2828 *pCommittedMemoryInBytes = 0;
2829 }
2830
2831 VkResult radv_BindBufferMemory2(VkDevice device,
2832 uint32_t bindInfoCount,
2833 const VkBindBufferMemoryInfoKHR *pBindInfos)
2834 {
2835 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2836 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2837 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2838
2839 if (mem) {
2840 buffer->bo = mem->bo;
2841 buffer->offset = pBindInfos[i].memoryOffset;
2842 } else {
2843 buffer->bo = NULL;
2844 }
2845 }
2846 return VK_SUCCESS;
2847 }
2848
2849 VkResult radv_BindBufferMemory(
2850 VkDevice device,
2851 VkBuffer buffer,
2852 VkDeviceMemory memory,
2853 VkDeviceSize memoryOffset)
2854 {
2855 const VkBindBufferMemoryInfoKHR info = {
2856 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2857 .buffer = buffer,
2858 .memory = memory,
2859 .memoryOffset = memoryOffset
2860 };
2861
2862 return radv_BindBufferMemory2(device, 1, &info);
2863 }
2864
2865 VkResult radv_BindImageMemory2(VkDevice device,
2866 uint32_t bindInfoCount,
2867 const VkBindImageMemoryInfoKHR *pBindInfos)
2868 {
2869 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2870 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2871 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2872
2873 if (mem) {
2874 image->bo = mem->bo;
2875 image->offset = pBindInfos[i].memoryOffset;
2876 } else {
2877 image->bo = NULL;
2878 image->offset = 0;
2879 }
2880 }
2881 return VK_SUCCESS;
2882 }
2883
2884
2885 VkResult radv_BindImageMemory(
2886 VkDevice device,
2887 VkImage image,
2888 VkDeviceMemory memory,
2889 VkDeviceSize memoryOffset)
2890 {
2891 const VkBindImageMemoryInfoKHR info = {
2892 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2893 .image = image,
2894 .memory = memory,
2895 .memoryOffset = memoryOffset
2896 };
2897
2898 return radv_BindImageMemory2(device, 1, &info);
2899 }
2900
2901
2902 static void
2903 radv_sparse_buffer_bind_memory(struct radv_device *device,
2904 const VkSparseBufferMemoryBindInfo *bind)
2905 {
2906 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2907
2908 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2909 struct radv_device_memory *mem = NULL;
2910
2911 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2912 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2913
2914 device->ws->buffer_virtual_bind(buffer->bo,
2915 bind->pBinds[i].resourceOffset,
2916 bind->pBinds[i].size,
2917 mem ? mem->bo : NULL,
2918 bind->pBinds[i].memoryOffset);
2919 }
2920 }
2921
2922 static void
2923 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2924 const VkSparseImageOpaqueMemoryBindInfo *bind)
2925 {
2926 RADV_FROM_HANDLE(radv_image, image, bind->image);
2927
2928 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2929 struct radv_device_memory *mem = NULL;
2930
2931 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2932 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2933
2934 device->ws->buffer_virtual_bind(image->bo,
2935 bind->pBinds[i].resourceOffset,
2936 bind->pBinds[i].size,
2937 mem ? mem->bo : NULL,
2938 bind->pBinds[i].memoryOffset);
2939 }
2940 }
2941
2942 VkResult radv_QueueBindSparse(
2943 VkQueue _queue,
2944 uint32_t bindInfoCount,
2945 const VkBindSparseInfo* pBindInfo,
2946 VkFence _fence)
2947 {
2948 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2949 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2950 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2951 bool fence_emitted = false;
2952
2953 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2954 struct radv_winsys_sem_info sem_info;
2955 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2956 radv_sparse_buffer_bind_memory(queue->device,
2957 pBindInfo[i].pBufferBinds + j);
2958 }
2959
2960 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2961 radv_sparse_image_opaque_bind_memory(queue->device,
2962 pBindInfo[i].pImageOpaqueBinds + j);
2963 }
2964
2965 VkResult result;
2966 result = radv_alloc_sem_info(&sem_info,
2967 pBindInfo[i].waitSemaphoreCount,
2968 pBindInfo[i].pWaitSemaphores,
2969 pBindInfo[i].signalSemaphoreCount,
2970 pBindInfo[i].pSignalSemaphores,
2971 _fence);
2972 if (result != VK_SUCCESS)
2973 return result;
2974
2975 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2976 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2977 &queue->device->empty_cs[queue->queue_family_index],
2978 1, NULL, NULL,
2979 &sem_info,
2980 false, base_fence);
2981 fence_emitted = true;
2982 if (fence)
2983 fence->submitted = true;
2984 }
2985
2986 radv_free_sem_info(&sem_info);
2987
2988 }
2989
2990 if (fence) {
2991 if (!fence_emitted) {
2992 radv_signal_fence(queue, fence);
2993 }
2994 fence->submitted = true;
2995 }
2996
2997 return VK_SUCCESS;
2998 }
2999
3000 VkResult radv_CreateFence(
3001 VkDevice _device,
3002 const VkFenceCreateInfo* pCreateInfo,
3003 const VkAllocationCallbacks* pAllocator,
3004 VkFence* pFence)
3005 {
3006 RADV_FROM_HANDLE(radv_device, device, _device);
3007 const VkExportFenceCreateInfoKHR *export =
3008 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3009 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3010 export ? export->handleTypes : 0;
3011
3012 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3013 sizeof(*fence), 8,
3014 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3015
3016 if (!fence)
3017 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3018
3019 fence->submitted = false;
3020 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3021 fence->temp_syncobj = 0;
3022 if (device->always_use_syncobj || handleTypes) {
3023 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3024 if (ret) {
3025 vk_free2(&device->alloc, pAllocator, fence);
3026 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3027 }
3028 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3029 device->ws->signal_syncobj(device->ws, fence->syncobj);
3030 }
3031 fence->fence = NULL;
3032 } else {
3033 fence->fence = device->ws->create_fence();
3034 if (!fence->fence) {
3035 vk_free2(&device->alloc, pAllocator, fence);
3036 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3037 }
3038 fence->syncobj = 0;
3039 }
3040
3041 *pFence = radv_fence_to_handle(fence);
3042
3043 return VK_SUCCESS;
3044 }
3045
3046 void radv_DestroyFence(
3047 VkDevice _device,
3048 VkFence _fence,
3049 const VkAllocationCallbacks* pAllocator)
3050 {
3051 RADV_FROM_HANDLE(radv_device, device, _device);
3052 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3053
3054 if (!fence)
3055 return;
3056
3057 if (fence->temp_syncobj)
3058 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3059 if (fence->syncobj)
3060 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3061 if (fence->fence)
3062 device->ws->destroy_fence(fence->fence);
3063 vk_free2(&device->alloc, pAllocator, fence);
3064 }
3065
3066
3067 static uint64_t radv_get_current_time()
3068 {
3069 struct timespec tv;
3070 clock_gettime(CLOCK_MONOTONIC, &tv);
3071 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3072 }
3073
3074 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3075 {
3076 uint64_t current_time = radv_get_current_time();
3077
3078 timeout = MIN2(UINT64_MAX - current_time, timeout);
3079
3080 return current_time + timeout;
3081 }
3082
3083
3084 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3085 {
3086 for (uint32_t i = 0; i < fenceCount; ++i) {
3087 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3088 if (fence->syncobj || fence->temp_syncobj || (!fence->signalled && !fence->submitted))
3089 return false;
3090 }
3091 return true;
3092 }
3093
3094 VkResult radv_WaitForFences(
3095 VkDevice _device,
3096 uint32_t fenceCount,
3097 const VkFence* pFences,
3098 VkBool32 waitAll,
3099 uint64_t timeout)
3100 {
3101 RADV_FROM_HANDLE(radv_device, device, _device);
3102 timeout = radv_get_absolute_timeout(timeout);
3103
3104 if (device->always_use_syncobj) {
3105 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3106 if (!handles)
3107 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3108
3109 for (uint32_t i = 0; i < fenceCount; ++i) {
3110 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3111 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3112 }
3113
3114 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3115
3116 free(handles);
3117 return success ? VK_SUCCESS : VK_TIMEOUT;
3118 }
3119
3120 if (!waitAll && fenceCount > 1) {
3121 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3122 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3123 uint32_t wait_count = 0;
3124 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3125 if (!fences)
3126 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3127
3128 for (uint32_t i = 0; i < fenceCount; ++i) {
3129 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3130
3131 if (fence->signalled) {
3132 free(fences);
3133 return VK_SUCCESS;
3134 }
3135
3136 fences[wait_count++] = fence->fence;
3137 }
3138
3139 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3140 waitAll, timeout - radv_get_current_time());
3141
3142 free(fences);
3143 return success ? VK_SUCCESS : VK_TIMEOUT;
3144 }
3145
3146 while(radv_get_current_time() <= timeout) {
3147 for (uint32_t i = 0; i < fenceCount; ++i) {
3148 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3149 return VK_SUCCESS;
3150 }
3151 }
3152 return VK_TIMEOUT;
3153 }
3154
3155 for (uint32_t i = 0; i < fenceCount; ++i) {
3156 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3157 bool expired = false;
3158
3159 if (fence->temp_syncobj) {
3160 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3161 return VK_TIMEOUT;
3162 continue;
3163 }
3164
3165 if (fence->syncobj) {
3166 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3167 return VK_TIMEOUT;
3168 continue;
3169 }
3170
3171 if (fence->signalled)
3172 continue;
3173
3174 if (!fence->submitted) {
3175 while(radv_get_current_time() <= timeout && !fence->submitted)
3176 /* Do nothing */;
3177
3178 if (!fence->submitted)
3179 return VK_TIMEOUT;
3180
3181 /* Recheck as it may have been set by submitting operations. */
3182 if (fence->signalled)
3183 continue;
3184 }
3185
3186 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
3187 if (!expired)
3188 return VK_TIMEOUT;
3189
3190 fence->signalled = true;
3191 }
3192
3193 return VK_SUCCESS;
3194 }
3195
3196 VkResult radv_ResetFences(VkDevice _device,
3197 uint32_t fenceCount,
3198 const VkFence *pFences)
3199 {
3200 RADV_FROM_HANDLE(radv_device, device, _device);
3201
3202 for (unsigned i = 0; i < fenceCount; ++i) {
3203 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3204 fence->submitted = fence->signalled = false;
3205
3206 /* Per spec, we first restore the permanent payload, and then reset, so
3207 * having a temp syncobj should not skip resetting the permanent syncobj. */
3208 if (fence->temp_syncobj) {
3209 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3210 fence->temp_syncobj = 0;
3211 }
3212
3213 if (fence->syncobj) {
3214 device->ws->reset_syncobj(device->ws, fence->syncobj);
3215 }
3216 }
3217
3218 return VK_SUCCESS;
3219 }
3220
3221 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3222 {
3223 RADV_FROM_HANDLE(radv_device, device, _device);
3224 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3225
3226 if (fence->temp_syncobj) {
3227 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3228 return success ? VK_SUCCESS : VK_NOT_READY;
3229 }
3230
3231 if (fence->syncobj) {
3232 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3233 return success ? VK_SUCCESS : VK_NOT_READY;
3234 }
3235
3236 if (fence->signalled)
3237 return VK_SUCCESS;
3238 if (!fence->submitted)
3239 return VK_NOT_READY;
3240 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3241 return VK_NOT_READY;
3242
3243 return VK_SUCCESS;
3244 }
3245
3246
3247 // Queue semaphore functions
3248
3249 VkResult radv_CreateSemaphore(
3250 VkDevice _device,
3251 const VkSemaphoreCreateInfo* pCreateInfo,
3252 const VkAllocationCallbacks* pAllocator,
3253 VkSemaphore* pSemaphore)
3254 {
3255 RADV_FROM_HANDLE(radv_device, device, _device);
3256 const VkExportSemaphoreCreateInfoKHR *export =
3257 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3258 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3259 export ? export->handleTypes : 0;
3260
3261 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3262 sizeof(*sem), 8,
3263 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3264 if (!sem)
3265 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3266
3267 sem->temp_syncobj = 0;
3268 /* create a syncobject if we are going to export this semaphore */
3269 if (device->always_use_syncobj || handleTypes) {
3270 assert (device->physical_device->rad_info.has_syncobj);
3271 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3272 if (ret) {
3273 vk_free2(&device->alloc, pAllocator, sem);
3274 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3275 }
3276 sem->sem = NULL;
3277 } else {
3278 sem->sem = device->ws->create_sem(device->ws);
3279 if (!sem->sem) {
3280 vk_free2(&device->alloc, pAllocator, sem);
3281 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3282 }
3283 sem->syncobj = 0;
3284 }
3285
3286 *pSemaphore = radv_semaphore_to_handle(sem);
3287 return VK_SUCCESS;
3288 }
3289
3290 void radv_DestroySemaphore(
3291 VkDevice _device,
3292 VkSemaphore _semaphore,
3293 const VkAllocationCallbacks* pAllocator)
3294 {
3295 RADV_FROM_HANDLE(radv_device, device, _device);
3296 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3297 if (!_semaphore)
3298 return;
3299
3300 if (sem->syncobj)
3301 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3302 else
3303 device->ws->destroy_sem(sem->sem);
3304 vk_free2(&device->alloc, pAllocator, sem);
3305 }
3306
3307 VkResult radv_CreateEvent(
3308 VkDevice _device,
3309 const VkEventCreateInfo* pCreateInfo,
3310 const VkAllocationCallbacks* pAllocator,
3311 VkEvent* pEvent)
3312 {
3313 RADV_FROM_HANDLE(radv_device, device, _device);
3314 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3315 sizeof(*event), 8,
3316 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3317
3318 if (!event)
3319 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3320
3321 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3322 RADEON_DOMAIN_GTT,
3323 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3324 if (!event->bo) {
3325 vk_free2(&device->alloc, pAllocator, event);
3326 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3327 }
3328
3329 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3330
3331 *pEvent = radv_event_to_handle(event);
3332
3333 return VK_SUCCESS;
3334 }
3335
3336 void radv_DestroyEvent(
3337 VkDevice _device,
3338 VkEvent _event,
3339 const VkAllocationCallbacks* pAllocator)
3340 {
3341 RADV_FROM_HANDLE(radv_device, device, _device);
3342 RADV_FROM_HANDLE(radv_event, event, _event);
3343
3344 if (!event)
3345 return;
3346 device->ws->buffer_destroy(event->bo);
3347 vk_free2(&device->alloc, pAllocator, event);
3348 }
3349
3350 VkResult radv_GetEventStatus(
3351 VkDevice _device,
3352 VkEvent _event)
3353 {
3354 RADV_FROM_HANDLE(radv_event, event, _event);
3355
3356 if (*event->map == 1)
3357 return VK_EVENT_SET;
3358 return VK_EVENT_RESET;
3359 }
3360
3361 VkResult radv_SetEvent(
3362 VkDevice _device,
3363 VkEvent _event)
3364 {
3365 RADV_FROM_HANDLE(radv_event, event, _event);
3366 *event->map = 1;
3367
3368 return VK_SUCCESS;
3369 }
3370
3371 VkResult radv_ResetEvent(
3372 VkDevice _device,
3373 VkEvent _event)
3374 {
3375 RADV_FROM_HANDLE(radv_event, event, _event);
3376 *event->map = 0;
3377
3378 return VK_SUCCESS;
3379 }
3380
3381 VkResult radv_CreateBuffer(
3382 VkDevice _device,
3383 const VkBufferCreateInfo* pCreateInfo,
3384 const VkAllocationCallbacks* pAllocator,
3385 VkBuffer* pBuffer)
3386 {
3387 RADV_FROM_HANDLE(radv_device, device, _device);
3388 struct radv_buffer *buffer;
3389
3390 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3391
3392 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3393 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3394 if (buffer == NULL)
3395 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3396
3397 buffer->size = pCreateInfo->size;
3398 buffer->usage = pCreateInfo->usage;
3399 buffer->bo = NULL;
3400 buffer->offset = 0;
3401 buffer->flags = pCreateInfo->flags;
3402
3403 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3404 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3405
3406 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3407 buffer->bo = device->ws->buffer_create(device->ws,
3408 align64(buffer->size, 4096),
3409 4096, 0, RADEON_FLAG_VIRTUAL);
3410 if (!buffer->bo) {
3411 vk_free2(&device->alloc, pAllocator, buffer);
3412 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3413 }
3414 }
3415
3416 *pBuffer = radv_buffer_to_handle(buffer);
3417
3418 return VK_SUCCESS;
3419 }
3420
3421 void radv_DestroyBuffer(
3422 VkDevice _device,
3423 VkBuffer _buffer,
3424 const VkAllocationCallbacks* pAllocator)
3425 {
3426 RADV_FROM_HANDLE(radv_device, device, _device);
3427 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3428
3429 if (!buffer)
3430 return;
3431
3432 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3433 device->ws->buffer_destroy(buffer->bo);
3434
3435 vk_free2(&device->alloc, pAllocator, buffer);
3436 }
3437
3438 static inline unsigned
3439 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3440 {
3441 if (stencil)
3442 return image->surface.u.legacy.stencil_tiling_index[level];
3443 else
3444 return image->surface.u.legacy.tiling_index[level];
3445 }
3446
3447 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3448 {
3449 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3450 }
3451
3452 static void
3453 radv_initialise_color_surface(struct radv_device *device,
3454 struct radv_color_buffer_info *cb,
3455 struct radv_image_view *iview)
3456 {
3457 const struct vk_format_description *desc;
3458 unsigned ntype, format, swap, endian;
3459 unsigned blend_clamp = 0, blend_bypass = 0;
3460 uint64_t va;
3461 const struct radeon_surf *surf = &iview->image->surface;
3462
3463 desc = vk_format_description(iview->vk_format);
3464
3465 memset(cb, 0, sizeof(*cb));
3466
3467 /* Intensity is implemented as Red, so treat it that way. */
3468 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3469
3470 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3471
3472 cb->cb_color_base = va >> 8;
3473
3474 if (device->physical_device->rad_info.chip_class >= GFX9) {
3475 struct gfx9_surf_meta_flags meta;
3476 if (iview->image->dcc_offset)
3477 meta = iview->image->surface.u.gfx9.dcc;
3478 else
3479 meta = iview->image->surface.u.gfx9.cmask;
3480
3481 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3482 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3483 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3484 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3485
3486 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3487 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3488 } else {
3489 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3490 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3491
3492 cb->cb_color_base += level_info->offset >> 8;
3493 if (level_info->mode == RADEON_SURF_MODE_2D)
3494 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3495
3496 pitch_tile_max = level_info->nblk_x / 8 - 1;
3497 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3498 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3499
3500 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3501 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3502 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3503
3504 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3505
3506 if (radv_image_has_fmask(iview->image)) {
3507 if (device->physical_device->rad_info.chip_class >= CIK)
3508 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3509 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3510 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3511 } else {
3512 /* This must be set for fast clear to work without FMASK. */
3513 if (device->physical_device->rad_info.chip_class >= CIK)
3514 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3515 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3516 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3517 }
3518 }
3519
3520 /* CMASK variables */
3521 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3522 va += iview->image->cmask.offset;
3523 cb->cb_color_cmask = va >> 8;
3524
3525 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3526 va += iview->image->dcc_offset;
3527 cb->cb_dcc_base = va >> 8;
3528 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3529
3530 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3531 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3532 S_028C6C_SLICE_MAX(max_slice);
3533
3534 if (iview->image->info.samples > 1) {
3535 unsigned log_samples = util_logbase2(iview->image->info.samples);
3536
3537 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3538 S_028C74_NUM_FRAGMENTS(log_samples);
3539 }
3540
3541 if (radv_image_has_fmask(iview->image)) {
3542 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3543 cb->cb_color_fmask = va >> 8;
3544 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3545 } else {
3546 cb->cb_color_fmask = cb->cb_color_base;
3547 }
3548
3549 ntype = radv_translate_color_numformat(iview->vk_format,
3550 desc,
3551 vk_format_get_first_non_void_channel(iview->vk_format));
3552 format = radv_translate_colorformat(iview->vk_format);
3553 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3554 radv_finishme("Illegal color\n");
3555 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3556 endian = radv_colorformat_endian_swap(format);
3557
3558 /* blend clamp should be set for all NORM/SRGB types */
3559 if (ntype == V_028C70_NUMBER_UNORM ||
3560 ntype == V_028C70_NUMBER_SNORM ||
3561 ntype == V_028C70_NUMBER_SRGB)
3562 blend_clamp = 1;
3563
3564 /* set blend bypass according to docs if SINT/UINT or
3565 8/24 COLOR variants */
3566 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3567 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3568 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3569 blend_clamp = 0;
3570 blend_bypass = 1;
3571 }
3572 #if 0
3573 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3574 (format == V_028C70_COLOR_8 ||
3575 format == V_028C70_COLOR_8_8 ||
3576 format == V_028C70_COLOR_8_8_8_8))
3577 ->color_is_int8 = true;
3578 #endif
3579 cb->cb_color_info = S_028C70_FORMAT(format) |
3580 S_028C70_COMP_SWAP(swap) |
3581 S_028C70_BLEND_CLAMP(blend_clamp) |
3582 S_028C70_BLEND_BYPASS(blend_bypass) |
3583 S_028C70_SIMPLE_FLOAT(1) |
3584 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3585 ntype != V_028C70_NUMBER_SNORM &&
3586 ntype != V_028C70_NUMBER_SRGB &&
3587 format != V_028C70_COLOR_8_24 &&
3588 format != V_028C70_COLOR_24_8) |
3589 S_028C70_NUMBER_TYPE(ntype) |
3590 S_028C70_ENDIAN(endian);
3591 if (radv_image_has_fmask(iview->image)) {
3592 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3593 if (device->physical_device->rad_info.chip_class == SI) {
3594 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3595 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3596 }
3597 }
3598
3599 if (radv_image_has_cmask(iview->image) &&
3600 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3601 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3602
3603 if (radv_dcc_enabled(iview->image, iview->base_mip))
3604 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3605
3606 if (device->physical_device->rad_info.chip_class >= VI) {
3607 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3608 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3609 unsigned independent_64b_blocks = 0;
3610 unsigned max_compressed_block_size;
3611
3612 /* amdvlk: [min-compressed-block-size] should be set to 32 for dGPU and
3613 64 for APU because all of our APUs to date use DIMMs which have
3614 a request granularity size of 64B while all other chips have a
3615 32B request size */
3616 if (!device->physical_device->rad_info.has_dedicated_vram)
3617 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3618
3619 if (iview->image->info.samples > 1) {
3620 if (iview->image->surface.bpe == 1)
3621 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3622 else if (iview->image->surface.bpe == 2)
3623 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3624 }
3625
3626 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT | VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3627 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3628 independent_64b_blocks = 1;
3629 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3630 } else
3631 max_compressed_block_size = max_uncompressed_block_size;
3632
3633 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3634 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3635 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3636 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3637 }
3638
3639 /* This must be set for fast clear to work without FMASK. */
3640 if (!radv_image_has_fmask(iview->image) &&
3641 device->physical_device->rad_info.chip_class == SI) {
3642 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3643 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3644 }
3645
3646 if (device->physical_device->rad_info.chip_class >= GFX9) {
3647 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3648 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3649
3650 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3651 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3652 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3653 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3654 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3655 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3656 }
3657 }
3658
3659 static unsigned
3660 radv_calc_decompress_on_z_planes(struct radv_device *device,
3661 struct radv_image_view *iview)
3662 {
3663 unsigned max_zplanes = 0;
3664
3665 assert(radv_image_is_tc_compat_htile(iview->image));
3666
3667 if (device->physical_device->rad_info.chip_class >= GFX9) {
3668 /* Default value for 32-bit depth surfaces. */
3669 max_zplanes = 4;
3670
3671 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3672 iview->image->info.samples > 1)
3673 max_zplanes = 2;
3674
3675 max_zplanes = max_zplanes + 1;
3676 } else {
3677 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3678 /* Do not enable Z plane compression for 16-bit depth
3679 * surfaces because isn't supported on GFX8. Only
3680 * 32-bit depth surfaces are supported by the hardware.
3681 * This allows to maintain shader compatibility and to
3682 * reduce the number of depth decompressions.
3683 */
3684 max_zplanes = 1;
3685 } else {
3686 if (iview->image->info.samples <= 1)
3687 max_zplanes = 5;
3688 else if (iview->image->info.samples <= 4)
3689 max_zplanes = 3;
3690 else
3691 max_zplanes = 2;
3692 }
3693 }
3694
3695 return max_zplanes;
3696 }
3697
3698 static void
3699 radv_initialise_ds_surface(struct radv_device *device,
3700 struct radv_ds_buffer_info *ds,
3701 struct radv_image_view *iview)
3702 {
3703 unsigned level = iview->base_mip;
3704 unsigned format, stencil_format;
3705 uint64_t va, s_offs, z_offs;
3706 bool stencil_only = false;
3707 memset(ds, 0, sizeof(*ds));
3708 switch (iview->image->vk_format) {
3709 case VK_FORMAT_D24_UNORM_S8_UINT:
3710 case VK_FORMAT_X8_D24_UNORM_PACK32:
3711 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3712 ds->offset_scale = 2.0f;
3713 break;
3714 case VK_FORMAT_D16_UNORM:
3715 case VK_FORMAT_D16_UNORM_S8_UINT:
3716 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3717 ds->offset_scale = 4.0f;
3718 break;
3719 case VK_FORMAT_D32_SFLOAT:
3720 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3721 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3722 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3723 ds->offset_scale = 1.0f;
3724 break;
3725 case VK_FORMAT_S8_UINT:
3726 stencil_only = true;
3727 break;
3728 default:
3729 break;
3730 }
3731
3732 format = radv_translate_dbformat(iview->image->vk_format);
3733 stencil_format = iview->image->surface.has_stencil ?
3734 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3735
3736 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3737 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3738 S_028008_SLICE_MAX(max_slice);
3739
3740 ds->db_htile_data_base = 0;
3741 ds->db_htile_surface = 0;
3742
3743 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3744 s_offs = z_offs = va;
3745
3746 if (device->physical_device->rad_info.chip_class >= GFX9) {
3747 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3748 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3749
3750 ds->db_z_info = S_028038_FORMAT(format) |
3751 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3752 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3753 S_028038_MAXMIP(iview->image->info.levels - 1);
3754 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3755 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3756
3757 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3758 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3759 ds->db_depth_view |= S_028008_MIPID(level);
3760
3761 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3762 S_02801C_Y_MAX(iview->image->info.height - 1);
3763
3764 if (radv_htile_enabled(iview->image, level)) {
3765 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3766
3767 if (radv_image_is_tc_compat_htile(iview->image)) {
3768 unsigned max_zplanes =
3769 radv_calc_decompress_on_z_planes(device, iview);
3770
3771 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
3772 S_028038_ITERATE_FLUSH(1);
3773 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3774 }
3775
3776 if (!iview->image->surface.has_stencil)
3777 /* Use all of the htile_buffer for depth if there's no stencil. */
3778 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3779 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3780 iview->image->htile_offset;
3781 ds->db_htile_data_base = va >> 8;
3782 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3783 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3784 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3785 }
3786 } else {
3787 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3788
3789 if (stencil_only)
3790 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3791
3792 z_offs += iview->image->surface.u.legacy.level[level].offset;
3793 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3794
3795 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
3796 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3797 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3798
3799 if (iview->image->info.samples > 1)
3800 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3801
3802 if (device->physical_device->rad_info.chip_class >= CIK) {
3803 struct radeon_info *info = &device->physical_device->rad_info;
3804 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3805 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3806 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3807 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3808 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3809 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3810
3811 if (stencil_only)
3812 tile_mode = stencil_tile_mode;
3813
3814 ds->db_depth_info |=
3815 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3816 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3817 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3818 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3819 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3820 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3821 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3822 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3823 } else {
3824 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3825 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3826 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3827 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3828 if (stencil_only)
3829 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3830 }
3831
3832 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3833 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3834 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3835
3836 if (radv_htile_enabled(iview->image, level)) {
3837 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3838
3839 if (!iview->image->surface.has_stencil &&
3840 !radv_image_is_tc_compat_htile(iview->image))
3841 /* Use all of the htile_buffer for depth if there's no stencil. */
3842 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3843
3844 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3845 iview->image->htile_offset;
3846 ds->db_htile_data_base = va >> 8;
3847 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3848
3849 if (radv_image_is_tc_compat_htile(iview->image)) {
3850 unsigned max_zplanes =
3851 radv_calc_decompress_on_z_planes(device, iview);
3852
3853 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3854 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
3855 }
3856 }
3857 }
3858
3859 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3860 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3861 }
3862
3863 VkResult radv_CreateFramebuffer(
3864 VkDevice _device,
3865 const VkFramebufferCreateInfo* pCreateInfo,
3866 const VkAllocationCallbacks* pAllocator,
3867 VkFramebuffer* pFramebuffer)
3868 {
3869 RADV_FROM_HANDLE(radv_device, device, _device);
3870 struct radv_framebuffer *framebuffer;
3871
3872 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3873
3874 size_t size = sizeof(*framebuffer) +
3875 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3876 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3877 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3878 if (framebuffer == NULL)
3879 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3880
3881 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3882 framebuffer->width = pCreateInfo->width;
3883 framebuffer->height = pCreateInfo->height;
3884 framebuffer->layers = pCreateInfo->layers;
3885 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3886 VkImageView _iview = pCreateInfo->pAttachments[i];
3887 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3888 framebuffer->attachments[i].attachment = iview;
3889 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3890 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3891 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3892 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3893 }
3894 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3895 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3896 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
3897 }
3898
3899 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3900 return VK_SUCCESS;
3901 }
3902
3903 void radv_DestroyFramebuffer(
3904 VkDevice _device,
3905 VkFramebuffer _fb,
3906 const VkAllocationCallbacks* pAllocator)
3907 {
3908 RADV_FROM_HANDLE(radv_device, device, _device);
3909 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3910
3911 if (!fb)
3912 return;
3913 vk_free2(&device->alloc, pAllocator, fb);
3914 }
3915
3916 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3917 {
3918 switch (address_mode) {
3919 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3920 return V_008F30_SQ_TEX_WRAP;
3921 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3922 return V_008F30_SQ_TEX_MIRROR;
3923 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3924 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3925 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3926 return V_008F30_SQ_TEX_CLAMP_BORDER;
3927 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3928 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3929 default:
3930 unreachable("illegal tex wrap mode");
3931 break;
3932 }
3933 }
3934
3935 static unsigned
3936 radv_tex_compare(VkCompareOp op)
3937 {
3938 switch (op) {
3939 case VK_COMPARE_OP_NEVER:
3940 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3941 case VK_COMPARE_OP_LESS:
3942 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3943 case VK_COMPARE_OP_EQUAL:
3944 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3945 case VK_COMPARE_OP_LESS_OR_EQUAL:
3946 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3947 case VK_COMPARE_OP_GREATER:
3948 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3949 case VK_COMPARE_OP_NOT_EQUAL:
3950 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3951 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3952 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3953 case VK_COMPARE_OP_ALWAYS:
3954 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3955 default:
3956 unreachable("illegal compare mode");
3957 break;
3958 }
3959 }
3960
3961 static unsigned
3962 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3963 {
3964 switch (filter) {
3965 case VK_FILTER_NEAREST:
3966 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3967 V_008F38_SQ_TEX_XY_FILTER_POINT);
3968 case VK_FILTER_LINEAR:
3969 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3970 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3971 case VK_FILTER_CUBIC_IMG:
3972 default:
3973 fprintf(stderr, "illegal texture filter");
3974 return 0;
3975 }
3976 }
3977
3978 static unsigned
3979 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3980 {
3981 switch (mode) {
3982 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3983 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3984 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3985 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3986 default:
3987 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3988 }
3989 }
3990
3991 static unsigned
3992 radv_tex_bordercolor(VkBorderColor bcolor)
3993 {
3994 switch (bcolor) {
3995 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3996 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3997 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3998 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3999 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4000 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4001 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4002 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4003 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4004 default:
4005 break;
4006 }
4007 return 0;
4008 }
4009
4010 static unsigned
4011 radv_tex_aniso_filter(unsigned filter)
4012 {
4013 if (filter < 2)
4014 return 0;
4015 if (filter < 4)
4016 return 1;
4017 if (filter < 8)
4018 return 2;
4019 if (filter < 16)
4020 return 3;
4021 return 4;
4022 }
4023
4024 static unsigned
4025 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4026 {
4027 switch (mode) {
4028 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4029 return SQ_IMG_FILTER_MODE_BLEND;
4030 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4031 return SQ_IMG_FILTER_MODE_MIN;
4032 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4033 return SQ_IMG_FILTER_MODE_MAX;
4034 default:
4035 break;
4036 }
4037 return 0;
4038 }
4039
4040 static void
4041 radv_init_sampler(struct radv_device *device,
4042 struct radv_sampler *sampler,
4043 const VkSamplerCreateInfo *pCreateInfo)
4044 {
4045 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4046 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4047 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4048 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4049 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4050
4051 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4052 vk_find_struct_const(pCreateInfo->pNext,
4053 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4054 if (sampler_reduction)
4055 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4056
4057 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4058 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4059 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4060 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4061 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4062 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4063 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4064 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4065 S_008F30_DISABLE_CUBE_WRAP(0) |
4066 S_008F30_COMPAT_MODE(is_vi) |
4067 S_008F30_FILTER_MODE(filter_mode));
4068 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4069 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4070 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4071 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4072 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4073 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4074 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4075 S_008F38_MIP_POINT_PRECLAMP(0) |
4076 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4077 S_008F38_FILTER_PREC_FIX(1) |
4078 S_008F38_ANISO_OVERRIDE(is_vi));
4079 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4080 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4081 }
4082
4083 VkResult radv_CreateSampler(
4084 VkDevice _device,
4085 const VkSamplerCreateInfo* pCreateInfo,
4086 const VkAllocationCallbacks* pAllocator,
4087 VkSampler* pSampler)
4088 {
4089 RADV_FROM_HANDLE(radv_device, device, _device);
4090 struct radv_sampler *sampler;
4091
4092 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4093
4094 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4095 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4096 if (!sampler)
4097 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
4098
4099 radv_init_sampler(device, sampler, pCreateInfo);
4100 *pSampler = radv_sampler_to_handle(sampler);
4101
4102 return VK_SUCCESS;
4103 }
4104
4105 void radv_DestroySampler(
4106 VkDevice _device,
4107 VkSampler _sampler,
4108 const VkAllocationCallbacks* pAllocator)
4109 {
4110 RADV_FROM_HANDLE(radv_device, device, _device);
4111 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4112
4113 if (!sampler)
4114 return;
4115 vk_free2(&device->alloc, pAllocator, sampler);
4116 }
4117
4118 /* vk_icd.h does not declare this function, so we declare it here to
4119 * suppress Wmissing-prototypes.
4120 */
4121 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4122 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4123
4124 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4125 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4126 {
4127 /* For the full details on loader interface versioning, see
4128 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4129 * What follows is a condensed summary, to help you navigate the large and
4130 * confusing official doc.
4131 *
4132 * - Loader interface v0 is incompatible with later versions. We don't
4133 * support it.
4134 *
4135 * - In loader interface v1:
4136 * - The first ICD entrypoint called by the loader is
4137 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4138 * entrypoint.
4139 * - The ICD must statically expose no other Vulkan symbol unless it is
4140 * linked with -Bsymbolic.
4141 * - Each dispatchable Vulkan handle created by the ICD must be
4142 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4143 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4144 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4145 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4146 * such loader-managed surfaces.
4147 *
4148 * - Loader interface v2 differs from v1 in:
4149 * - The first ICD entrypoint called by the loader is
4150 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4151 * statically expose this entrypoint.
4152 *
4153 * - Loader interface v3 differs from v2 in:
4154 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4155 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4156 * because the loader no longer does so.
4157 */
4158 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4159 return VK_SUCCESS;
4160 }
4161
4162 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4163 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4164 int *pFD)
4165 {
4166 RADV_FROM_HANDLE(radv_device, device, _device);
4167 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4168
4169 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4170
4171 /* At the moment, we support only the below handle types. */
4172 assert(pGetFdInfo->handleType ==
4173 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4174 pGetFdInfo->handleType ==
4175 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4176
4177 bool ret = radv_get_memory_fd(device, memory, pFD);
4178 if (ret == false)
4179 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
4180 return VK_SUCCESS;
4181 }
4182
4183 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4184 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4185 int fd,
4186 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4187 {
4188 switch (handleType) {
4189 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4190 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4191 return VK_SUCCESS;
4192
4193 default:
4194 /* The valid usage section for this function says:
4195 *
4196 * "handleType must not be one of the handle types defined as
4197 * opaque."
4198 *
4199 * So opaque handle types fall into the default "unsupported" case.
4200 */
4201 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4202 }
4203 }
4204
4205 static VkResult radv_import_opaque_fd(struct radv_device *device,
4206 int fd,
4207 uint32_t *syncobj)
4208 {
4209 uint32_t syncobj_handle = 0;
4210 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4211 if (ret != 0)
4212 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4213
4214 if (*syncobj)
4215 device->ws->destroy_syncobj(device->ws, *syncobj);
4216
4217 *syncobj = syncobj_handle;
4218 close(fd);
4219
4220 return VK_SUCCESS;
4221 }
4222
4223 static VkResult radv_import_sync_fd(struct radv_device *device,
4224 int fd,
4225 uint32_t *syncobj)
4226 {
4227 /* If we create a syncobj we do it locally so that if we have an error, we don't
4228 * leave a syncobj in an undetermined state in the fence. */
4229 uint32_t syncobj_handle = *syncobj;
4230 if (!syncobj_handle) {
4231 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4232 if (ret) {
4233 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4234 }
4235 }
4236
4237 if (fd == -1) {
4238 device->ws->signal_syncobj(device->ws, syncobj_handle);
4239 } else {
4240 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4241 if (ret != 0)
4242 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4243 }
4244
4245 *syncobj = syncobj_handle;
4246 if (fd != -1)
4247 close(fd);
4248
4249 return VK_SUCCESS;
4250 }
4251
4252 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4253 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4254 {
4255 RADV_FROM_HANDLE(radv_device, device, _device);
4256 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4257 uint32_t *syncobj_dst = NULL;
4258
4259 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4260 syncobj_dst = &sem->temp_syncobj;
4261 } else {
4262 syncobj_dst = &sem->syncobj;
4263 }
4264
4265 switch(pImportSemaphoreFdInfo->handleType) {
4266 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4267 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4268 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4269 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4270 default:
4271 unreachable("Unhandled semaphore handle type");
4272 }
4273 }
4274
4275 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4276 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4277 int *pFd)
4278 {
4279 RADV_FROM_HANDLE(radv_device, device, _device);
4280 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4281 int ret;
4282 uint32_t syncobj_handle;
4283
4284 if (sem->temp_syncobj)
4285 syncobj_handle = sem->temp_syncobj;
4286 else
4287 syncobj_handle = sem->syncobj;
4288
4289 switch(pGetFdInfo->handleType) {
4290 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4291 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4292 break;
4293 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4294 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4295 if (!ret) {
4296 if (sem->temp_syncobj) {
4297 close (sem->temp_syncobj);
4298 sem->temp_syncobj = 0;
4299 } else {
4300 device->ws->reset_syncobj(device->ws, syncobj_handle);
4301 }
4302 }
4303 break;
4304 default:
4305 unreachable("Unhandled semaphore handle type");
4306 }
4307
4308 if (ret)
4309 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4310 return VK_SUCCESS;
4311 }
4312
4313 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4314 VkPhysicalDevice physicalDevice,
4315 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4316 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4317 {
4318 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4319
4320 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4321 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4322 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4323 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4324 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4325 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4326 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4327 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4328 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4329 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4330 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4331 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4332 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4333 } else {
4334 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4335 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4336 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4337 }
4338 }
4339
4340 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4341 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4342 {
4343 RADV_FROM_HANDLE(radv_device, device, _device);
4344 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4345 uint32_t *syncobj_dst = NULL;
4346
4347
4348 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4349 syncobj_dst = &fence->temp_syncobj;
4350 } else {
4351 syncobj_dst = &fence->syncobj;
4352 }
4353
4354 switch(pImportFenceFdInfo->handleType) {
4355 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4356 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4357 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4358 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4359 default:
4360 unreachable("Unhandled fence handle type");
4361 }
4362 }
4363
4364 VkResult radv_GetFenceFdKHR(VkDevice _device,
4365 const VkFenceGetFdInfoKHR *pGetFdInfo,
4366 int *pFd)
4367 {
4368 RADV_FROM_HANDLE(radv_device, device, _device);
4369 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4370 int ret;
4371 uint32_t syncobj_handle;
4372
4373 if (fence->temp_syncobj)
4374 syncobj_handle = fence->temp_syncobj;
4375 else
4376 syncobj_handle = fence->syncobj;
4377
4378 switch(pGetFdInfo->handleType) {
4379 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4380 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4381 break;
4382 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4383 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4384 if (!ret) {
4385 if (fence->temp_syncobj) {
4386 close (fence->temp_syncobj);
4387 fence->temp_syncobj = 0;
4388 } else {
4389 device->ws->reset_syncobj(device->ws, syncobj_handle);
4390 }
4391 }
4392 break;
4393 default:
4394 unreachable("Unhandled fence handle type");
4395 }
4396
4397 if (ret)
4398 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4399 return VK_SUCCESS;
4400 }
4401
4402 void radv_GetPhysicalDeviceExternalFenceProperties(
4403 VkPhysicalDevice physicalDevice,
4404 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4405 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4406 {
4407 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4408
4409 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4410 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4411 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4412 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4413 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4414 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4415 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4416 } else {
4417 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4418 pExternalFenceProperties->compatibleHandleTypes = 0;
4419 pExternalFenceProperties->externalFenceFeatures = 0;
4420 }
4421 }
4422
4423 VkResult
4424 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4425 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4426 const VkAllocationCallbacks* pAllocator,
4427 VkDebugReportCallbackEXT* pCallback)
4428 {
4429 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4430 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4431 pCreateInfo, pAllocator, &instance->alloc,
4432 pCallback);
4433 }
4434
4435 void
4436 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4437 VkDebugReportCallbackEXT _callback,
4438 const VkAllocationCallbacks* pAllocator)
4439 {
4440 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4441 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4442 _callback, pAllocator, &instance->alloc);
4443 }
4444
4445 void
4446 radv_DebugReportMessageEXT(VkInstance _instance,
4447 VkDebugReportFlagsEXT flags,
4448 VkDebugReportObjectTypeEXT objectType,
4449 uint64_t object,
4450 size_t location,
4451 int32_t messageCode,
4452 const char* pLayerPrefix,
4453 const char* pMessage)
4454 {
4455 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4456 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4457 object, location, messageCode, pLayerPrefix, pMessage);
4458 }
4459
4460 void
4461 radv_GetDeviceGroupPeerMemoryFeatures(
4462 VkDevice device,
4463 uint32_t heapIndex,
4464 uint32_t localDeviceIndex,
4465 uint32_t remoteDeviceIndex,
4466 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4467 {
4468 assert(localDeviceIndex == remoteDeviceIndex);
4469
4470 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4471 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4472 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4473 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4474 }