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radv: Don't use local BOs when allocating with export options.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "util/debug.h"
48
49 static int
50 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
51 {
52 uint32_t mesa_timestamp, llvm_timestamp;
53 uint16_t f = family;
54 memset(uuid, 0, VK_UUID_SIZE);
55 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
56 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
57 return -1;
58
59 memcpy(uuid, &mesa_timestamp, 4);
60 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
61 memcpy((char*)uuid + 8, &f, 2);
62 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
63 return 0;
64 }
65
66 static void
67 radv_get_driver_uuid(void *uuid)
68 {
69 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
70 }
71
72 static void
73 radv_get_device_uuid(struct radeon_info *info, void *uuid)
74 {
75 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
76 }
77
78 static void
79 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
80 {
81 const char *chip_string;
82 char llvm_string[32] = {};
83
84 switch (family) {
85 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
86 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
87 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
88 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
89 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
90 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
91 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
92 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
93 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
94 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
95 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
96 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
97 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
98 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
99 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
100 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
101 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
102 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
103 case CHIP_VEGA10: chip_string = "AMD RADV VEGA"; break;
104 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
105 default: chip_string = "AMD RADV unknown"; break;
106 }
107
108 if (HAVE_LLVM > 0) {
109 snprintf(llvm_string, sizeof(llvm_string),
110 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
111 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
112 }
113
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = 0,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
162 .heapIndex = gart_index,
163 };
164 }
165 if (visible_vram_index >= 0) {
166 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
167 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
168 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
169 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
171 .heapIndex = visible_vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
180 .heapIndex = gart_index,
181 };
182 }
183 device->memory_properties.memoryTypeCount = type_count;
184 }
185
186 static VkResult
187 radv_physical_device_init(struct radv_physical_device *device,
188 struct radv_instance *instance,
189 drmDevicePtr drm_device)
190 {
191 const char *path = drm_device->nodes[DRM_NODE_RENDER];
192 VkResult result;
193 drmVersionPtr version;
194 int fd;
195
196 fd = open(path, O_RDWR | O_CLOEXEC);
197 if (fd < 0)
198 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
199
200 version = drmGetVersion(fd);
201 if (!version) {
202 close(fd);
203 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
204 "failed to get version %s: %m", path);
205 }
206
207 if (strcmp(version->name, "amdgpu")) {
208 drmFreeVersion(version);
209 close(fd);
210 return VK_ERROR_INCOMPATIBLE_DRIVER;
211 }
212 drmFreeVersion(version);
213
214 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
215 device->instance = instance;
216 assert(strlen(path) < ARRAY_SIZE(device->path));
217 strncpy(device->path, path, ARRAY_SIZE(device->path));
218
219 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
220 instance->perftest_flags);
221 if (!device->ws) {
222 result = VK_ERROR_INCOMPATIBLE_DRIVER;
223 goto fail;
224 }
225
226 device->local_fd = fd;
227 device->ws->query_info(device->ws, &device->rad_info);
228
229 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
230
231 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
232 device->ws->destroy(device->ws);
233 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
234 "cannot generate UUID");
235 goto fail;
236 }
237
238 /* These flags affect shader compilation. */
239 uint64_t shader_env_flags =
240 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
241 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
242
243 /* The gpu id is already embeded in the uuid so we just pass "radv"
244 * when creating the cache.
245 */
246 char buf[VK_UUID_SIZE * 2 + 1];
247 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
248 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251
252 radv_get_driver_uuid(&device->device_uuid);
253 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
254
255 if (device->rad_info.family == CHIP_STONEY ||
256 device->rad_info.chip_class >= GFX9) {
257 device->has_rbplus = true;
258 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
259 }
260
261 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
262 * on SI.
263 */
264 device->has_clear_state = device->rad_info.chip_class >= CIK;
265
266 radv_physical_device_init_mem_types(device);
267
268 result = radv_init_wsi(device);
269 if (result != VK_SUCCESS) {
270 device->ws->destroy(device->ws);
271 goto fail;
272 }
273
274 return VK_SUCCESS;
275
276 fail:
277 close(fd);
278 return result;
279 }
280
281 static void
282 radv_physical_device_finish(struct radv_physical_device *device)
283 {
284 radv_finish_wsi(device);
285 device->ws->destroy(device->ws);
286 disk_cache_destroy(device->disk_cache);
287 close(device->local_fd);
288 }
289
290 static void *
291 default_alloc_func(void *pUserData, size_t size, size_t align,
292 VkSystemAllocationScope allocationScope)
293 {
294 return malloc(size);
295 }
296
297 static void *
298 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
299 size_t align, VkSystemAllocationScope allocationScope)
300 {
301 return realloc(pOriginal, size);
302 }
303
304 static void
305 default_free_func(void *pUserData, void *pMemory)
306 {
307 free(pMemory);
308 }
309
310 static const VkAllocationCallbacks default_alloc = {
311 .pUserData = NULL,
312 .pfnAllocation = default_alloc_func,
313 .pfnReallocation = default_realloc_func,
314 .pfnFree = default_free_func,
315 };
316
317 static const struct debug_control radv_debug_options[] = {
318 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
319 {"nodcc", RADV_DEBUG_NO_DCC},
320 {"shaders", RADV_DEBUG_DUMP_SHADERS},
321 {"nocache", RADV_DEBUG_NO_CACHE},
322 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
323 {"nohiz", RADV_DEBUG_NO_HIZ},
324 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
325 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
326 {"allbos", RADV_DEBUG_ALL_BOS},
327 {"noibs", RADV_DEBUG_NO_IBS},
328 {"spirv", RADV_DEBUG_DUMP_SPIRV},
329 {"vmfaults", RADV_DEBUG_VM_FAULTS},
330 {"zerovram", RADV_DEBUG_ZERO_VRAM},
331 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
332 {"nosisched", RADV_DEBUG_NO_SISCHED},
333 {NULL, 0}
334 };
335
336 const char *
337 radv_get_debug_option_name(int id)
338 {
339 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
340 return radv_debug_options[id].string;
341 }
342
343 static const struct debug_control radv_perftest_options[] = {
344 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
345 {"sisched", RADV_PERFTEST_SISCHED},
346 {NULL, 0}
347 };
348
349 const char *
350 radv_get_perftest_option_name(int id)
351 {
352 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
353 return radv_perftest_options[id].string;
354 }
355
356 static void
357 radv_handle_per_app_options(struct radv_instance *instance,
358 const VkApplicationInfo *info)
359 {
360 const char *name = info ? info->pApplicationName : NULL;
361
362 if (!name)
363 return;
364
365 if (!strcmp(name, "Talos - Linux - 32bit") ||
366 !strcmp(name, "Talos - Linux - 64bit")) {
367 /* Force enable LLVM sisched for Talos because it looks safe
368 * and it gives few more FPS.
369 */
370 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
371 }
372 }
373
374 VkResult radv_CreateInstance(
375 const VkInstanceCreateInfo* pCreateInfo,
376 const VkAllocationCallbacks* pAllocator,
377 VkInstance* pInstance)
378 {
379 struct radv_instance *instance;
380
381 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
382
383 uint32_t client_version;
384 if (pCreateInfo->pApplicationInfo &&
385 pCreateInfo->pApplicationInfo->apiVersion != 0) {
386 client_version = pCreateInfo->pApplicationInfo->apiVersion;
387 } else {
388 client_version = VK_MAKE_VERSION(1, 0, 0);
389 }
390
391 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
392 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
393 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
394 "Client requested version %d.%d.%d",
395 VK_VERSION_MAJOR(client_version),
396 VK_VERSION_MINOR(client_version),
397 VK_VERSION_PATCH(client_version));
398 }
399
400 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
401 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
402 if (!radv_instance_extension_supported(ext_name))
403 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
404 }
405
406 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
407 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
408 if (!instance)
409 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
410
411 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
412
413 if (pAllocator)
414 instance->alloc = *pAllocator;
415 else
416 instance->alloc = default_alloc;
417
418 instance->apiVersion = client_version;
419 instance->physicalDeviceCount = -1;
420
421 _mesa_locale_init();
422
423 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
424
425 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
426 radv_debug_options);
427
428 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
429 radv_perftest_options);
430
431 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
432
433 if (instance->debug_flags & RADV_DEBUG_NO_SISCHED) {
434 /* Disable sisched when the user requests it, this is mostly
435 * useful when the driver force-enable sisched for the given
436 * application.
437 */
438 instance->perftest_flags &= ~RADV_PERFTEST_SISCHED;
439 }
440
441 *pInstance = radv_instance_to_handle(instance);
442
443 return VK_SUCCESS;
444 }
445
446 void radv_DestroyInstance(
447 VkInstance _instance,
448 const VkAllocationCallbacks* pAllocator)
449 {
450 RADV_FROM_HANDLE(radv_instance, instance, _instance);
451
452 if (!instance)
453 return;
454
455 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
456 radv_physical_device_finish(instance->physicalDevices + i);
457 }
458
459 VG(VALGRIND_DESTROY_MEMPOOL(instance));
460
461 _mesa_locale_fini();
462
463 vk_free(&instance->alloc, instance);
464 }
465
466 static VkResult
467 radv_enumerate_devices(struct radv_instance *instance)
468 {
469 /* TODO: Check for more devices ? */
470 drmDevicePtr devices[8];
471 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
472 int max_devices;
473
474 instance->physicalDeviceCount = 0;
475
476 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
477 if (max_devices < 1)
478 return vk_error(VK_ERROR_INCOMPATIBLE_DRIVER);
479
480 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
481 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
482 devices[i]->bustype == DRM_BUS_PCI &&
483 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
484
485 result = radv_physical_device_init(instance->physicalDevices +
486 instance->physicalDeviceCount,
487 instance,
488 devices[i]);
489 if (result == VK_SUCCESS)
490 ++instance->physicalDeviceCount;
491 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
492 break;
493 }
494 }
495 drmFreeDevices(devices, max_devices);
496
497 return result;
498 }
499
500 VkResult radv_EnumeratePhysicalDevices(
501 VkInstance _instance,
502 uint32_t* pPhysicalDeviceCount,
503 VkPhysicalDevice* pPhysicalDevices)
504 {
505 RADV_FROM_HANDLE(radv_instance, instance, _instance);
506 VkResult result;
507
508 if (instance->physicalDeviceCount < 0) {
509 result = radv_enumerate_devices(instance);
510 if (result != VK_SUCCESS &&
511 result != VK_ERROR_INCOMPATIBLE_DRIVER)
512 return result;
513 }
514
515 if (!pPhysicalDevices) {
516 *pPhysicalDeviceCount = instance->physicalDeviceCount;
517 } else {
518 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
519 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
520 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
521 }
522
523 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
524 : VK_SUCCESS;
525 }
526
527 void radv_GetPhysicalDeviceFeatures(
528 VkPhysicalDevice physicalDevice,
529 VkPhysicalDeviceFeatures* pFeatures)
530 {
531 memset(pFeatures, 0, sizeof(*pFeatures));
532
533 *pFeatures = (VkPhysicalDeviceFeatures) {
534 .robustBufferAccess = true,
535 .fullDrawIndexUint32 = true,
536 .imageCubeArray = true,
537 .independentBlend = true,
538 .geometryShader = true,
539 .tessellationShader = true,
540 .sampleRateShading = true,
541 .dualSrcBlend = true,
542 .logicOp = true,
543 .multiDrawIndirect = true,
544 .drawIndirectFirstInstance = true,
545 .depthClamp = true,
546 .depthBiasClamp = true,
547 .fillModeNonSolid = true,
548 .depthBounds = true,
549 .wideLines = true,
550 .largePoints = true,
551 .alphaToOne = true,
552 .multiViewport = true,
553 .samplerAnisotropy = true,
554 .textureCompressionETC2 = false,
555 .textureCompressionASTC_LDR = false,
556 .textureCompressionBC = true,
557 .occlusionQueryPrecise = true,
558 .pipelineStatisticsQuery = true,
559 .vertexPipelineStoresAndAtomics = true,
560 .fragmentStoresAndAtomics = true,
561 .shaderTessellationAndGeometryPointSize = true,
562 .shaderImageGatherExtended = true,
563 .shaderStorageImageExtendedFormats = true,
564 .shaderStorageImageMultisample = false,
565 .shaderUniformBufferArrayDynamicIndexing = true,
566 .shaderSampledImageArrayDynamicIndexing = true,
567 .shaderStorageBufferArrayDynamicIndexing = true,
568 .shaderStorageImageArrayDynamicIndexing = true,
569 .shaderStorageImageReadWithoutFormat = true,
570 .shaderStorageImageWriteWithoutFormat = true,
571 .shaderClipDistance = true,
572 .shaderCullDistance = true,
573 .shaderFloat64 = true,
574 .shaderInt64 = true,
575 .shaderInt16 = false,
576 .sparseBinding = true,
577 .variableMultisampleRate = true,
578 .inheritedQueries = true,
579 };
580 }
581
582 void radv_GetPhysicalDeviceFeatures2KHR(
583 VkPhysicalDevice physicalDevice,
584 VkPhysicalDeviceFeatures2KHR *pFeatures)
585 {
586 vk_foreach_struct(ext, pFeatures->pNext) {
587 switch (ext->sType) {
588 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
589 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
590 features->variablePointersStorageBuffer = true;
591 features->variablePointers = false;
592 break;
593 }
594 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
595 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
596 features->multiview = true;
597 features->multiviewGeometryShader = true;
598 features->multiviewTessellationShader = true;
599 break;
600 }
601 default:
602 break;
603 }
604 }
605 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
606 }
607
608 void radv_GetPhysicalDeviceProperties(
609 VkPhysicalDevice physicalDevice,
610 VkPhysicalDeviceProperties* pProperties)
611 {
612 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
613 VkSampleCountFlags sample_counts = 0xf;
614
615 /* make sure that the entire descriptor set is addressable with a signed
616 * 32-bit int. So the sum of all limits scaled by descriptor size has to
617 * be at most 2 GiB. the combined image & samples object count as one of
618 * both. This limit is for the pipeline layout, not for the set layout, but
619 * there is no set limit, so we just set a pipeline limit. I don't think
620 * any app is going to hit this soon. */
621 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
622 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
623 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
624 32 /* sampler, largest when combined with image */ +
625 64 /* sampled image */ +
626 64 /* storage image */);
627
628 VkPhysicalDeviceLimits limits = {
629 .maxImageDimension1D = (1 << 14),
630 .maxImageDimension2D = (1 << 14),
631 .maxImageDimension3D = (1 << 11),
632 .maxImageDimensionCube = (1 << 14),
633 .maxImageArrayLayers = (1 << 11),
634 .maxTexelBufferElements = 128 * 1024 * 1024,
635 .maxUniformBufferRange = UINT32_MAX,
636 .maxStorageBufferRange = UINT32_MAX,
637 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
638 .maxMemoryAllocationCount = UINT32_MAX,
639 .maxSamplerAllocationCount = 64 * 1024,
640 .bufferImageGranularity = 64, /* A cache line */
641 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
642 .maxBoundDescriptorSets = MAX_SETS,
643 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
644 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
645 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
646 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
647 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
648 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
649 .maxPerStageResources = max_descriptor_set_size,
650 .maxDescriptorSetSamplers = max_descriptor_set_size,
651 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
652 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
653 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
654 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
655 .maxDescriptorSetSampledImages = max_descriptor_set_size,
656 .maxDescriptorSetStorageImages = max_descriptor_set_size,
657 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
658 .maxVertexInputAttributes = 32,
659 .maxVertexInputBindings = 32,
660 .maxVertexInputAttributeOffset = 2047,
661 .maxVertexInputBindingStride = 2048,
662 .maxVertexOutputComponents = 128,
663 .maxTessellationGenerationLevel = 64,
664 .maxTessellationPatchSize = 32,
665 .maxTessellationControlPerVertexInputComponents = 128,
666 .maxTessellationControlPerVertexOutputComponents = 128,
667 .maxTessellationControlPerPatchOutputComponents = 120,
668 .maxTessellationControlTotalOutputComponents = 4096,
669 .maxTessellationEvaluationInputComponents = 128,
670 .maxTessellationEvaluationOutputComponents = 128,
671 .maxGeometryShaderInvocations = 127,
672 .maxGeometryInputComponents = 64,
673 .maxGeometryOutputComponents = 128,
674 .maxGeometryOutputVertices = 256,
675 .maxGeometryTotalOutputComponents = 1024,
676 .maxFragmentInputComponents = 128,
677 .maxFragmentOutputAttachments = 8,
678 .maxFragmentDualSrcAttachments = 1,
679 .maxFragmentCombinedOutputResources = 8,
680 .maxComputeSharedMemorySize = 32768,
681 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
682 .maxComputeWorkGroupInvocations = 2048,
683 .maxComputeWorkGroupSize = {
684 2048,
685 2048,
686 2048
687 },
688 .subPixelPrecisionBits = 4 /* FIXME */,
689 .subTexelPrecisionBits = 4 /* FIXME */,
690 .mipmapPrecisionBits = 4 /* FIXME */,
691 .maxDrawIndexedIndexValue = UINT32_MAX,
692 .maxDrawIndirectCount = UINT32_MAX,
693 .maxSamplerLodBias = 16,
694 .maxSamplerAnisotropy = 16,
695 .maxViewports = MAX_VIEWPORTS,
696 .maxViewportDimensions = { (1 << 14), (1 << 14) },
697 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
698 .viewportSubPixelBits = 13, /* We take a float? */
699 .minMemoryMapAlignment = 4096, /* A page */
700 .minTexelBufferOffsetAlignment = 1,
701 .minUniformBufferOffsetAlignment = 4,
702 .minStorageBufferOffsetAlignment = 4,
703 .minTexelOffset = -32,
704 .maxTexelOffset = 31,
705 .minTexelGatherOffset = -32,
706 .maxTexelGatherOffset = 31,
707 .minInterpolationOffset = -2,
708 .maxInterpolationOffset = 2,
709 .subPixelInterpolationOffsetBits = 8,
710 .maxFramebufferWidth = (1 << 14),
711 .maxFramebufferHeight = (1 << 14),
712 .maxFramebufferLayers = (1 << 10),
713 .framebufferColorSampleCounts = sample_counts,
714 .framebufferDepthSampleCounts = sample_counts,
715 .framebufferStencilSampleCounts = sample_counts,
716 .framebufferNoAttachmentsSampleCounts = sample_counts,
717 .maxColorAttachments = MAX_RTS,
718 .sampledImageColorSampleCounts = sample_counts,
719 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
720 .sampledImageDepthSampleCounts = sample_counts,
721 .sampledImageStencilSampleCounts = sample_counts,
722 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
723 .maxSampleMaskWords = 1,
724 .timestampComputeAndGraphics = true,
725 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
726 .maxClipDistances = 8,
727 .maxCullDistances = 8,
728 .maxCombinedClipAndCullDistances = 8,
729 .discreteQueuePriorities = 1,
730 .pointSizeRange = { 0.125, 255.875 },
731 .lineWidthRange = { 0.0, 7.9921875 },
732 .pointSizeGranularity = (1.0 / 8.0),
733 .lineWidthGranularity = (1.0 / 128.0),
734 .strictLines = false, /* FINISHME */
735 .standardSampleLocations = true,
736 .optimalBufferCopyOffsetAlignment = 128,
737 .optimalBufferCopyRowPitchAlignment = 128,
738 .nonCoherentAtomSize = 64,
739 };
740
741 *pProperties = (VkPhysicalDeviceProperties) {
742 .apiVersion = radv_physical_device_api_version(pdevice),
743 .driverVersion = vk_get_driver_version(),
744 .vendorID = ATI_VENDOR_ID,
745 .deviceID = pdevice->rad_info.pci_id,
746 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
747 .limits = limits,
748 .sparseProperties = {0},
749 };
750
751 strcpy(pProperties->deviceName, pdevice->name);
752 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
753 }
754
755 void radv_GetPhysicalDeviceProperties2KHR(
756 VkPhysicalDevice physicalDevice,
757 VkPhysicalDeviceProperties2KHR *pProperties)
758 {
759 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
760 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
761
762 vk_foreach_struct(ext, pProperties->pNext) {
763 switch (ext->sType) {
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
765 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
766 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
767 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
771 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
772 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
773 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
774 properties->deviceLUIDValid = false;
775 break;
776 }
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
778 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
779 properties->maxMultiviewViewCount = MAX_VIEWS;
780 properties->maxMultiviewInstanceIndex = INT_MAX;
781 break;
782 }
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
784 VkPhysicalDevicePointClippingPropertiesKHR *properties =
785 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
786 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
787 break;
788 }
789 default:
790 break;
791 }
792 }
793 }
794
795 static void radv_get_physical_device_queue_family_properties(
796 struct radv_physical_device* pdevice,
797 uint32_t* pCount,
798 VkQueueFamilyProperties** pQueueFamilyProperties)
799 {
800 int num_queue_families = 1;
801 int idx;
802 if (pdevice->rad_info.num_compute_rings > 0 &&
803 pdevice->rad_info.chip_class >= CIK &&
804 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
805 num_queue_families++;
806
807 if (pQueueFamilyProperties == NULL) {
808 *pCount = num_queue_families;
809 return;
810 }
811
812 if (!*pCount)
813 return;
814
815 idx = 0;
816 if (*pCount >= 1) {
817 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
818 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
819 VK_QUEUE_COMPUTE_BIT |
820 VK_QUEUE_TRANSFER_BIT |
821 VK_QUEUE_SPARSE_BINDING_BIT,
822 .queueCount = 1,
823 .timestampValidBits = 64,
824 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
825 };
826 idx++;
827 }
828
829 if (pdevice->rad_info.num_compute_rings > 0 &&
830 pdevice->rad_info.chip_class >= CIK &&
831 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
832 if (*pCount > idx) {
833 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
834 .queueFlags = VK_QUEUE_COMPUTE_BIT |
835 VK_QUEUE_TRANSFER_BIT |
836 VK_QUEUE_SPARSE_BINDING_BIT,
837 .queueCount = pdevice->rad_info.num_compute_rings,
838 .timestampValidBits = 64,
839 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
840 };
841 idx++;
842 }
843 }
844 *pCount = idx;
845 }
846
847 void radv_GetPhysicalDeviceQueueFamilyProperties(
848 VkPhysicalDevice physicalDevice,
849 uint32_t* pCount,
850 VkQueueFamilyProperties* pQueueFamilyProperties)
851 {
852 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
853 if (!pQueueFamilyProperties) {
854 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
855 return;
856 }
857 VkQueueFamilyProperties *properties[] = {
858 pQueueFamilyProperties + 0,
859 pQueueFamilyProperties + 1,
860 pQueueFamilyProperties + 2,
861 };
862 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
863 assert(*pCount <= 3);
864 }
865
866 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
867 VkPhysicalDevice physicalDevice,
868 uint32_t* pCount,
869 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
870 {
871 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
872 if (!pQueueFamilyProperties) {
873 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
874 return;
875 }
876 VkQueueFamilyProperties *properties[] = {
877 &pQueueFamilyProperties[0].queueFamilyProperties,
878 &pQueueFamilyProperties[1].queueFamilyProperties,
879 &pQueueFamilyProperties[2].queueFamilyProperties,
880 };
881 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
882 assert(*pCount <= 3);
883 }
884
885 void radv_GetPhysicalDeviceMemoryProperties(
886 VkPhysicalDevice physicalDevice,
887 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
888 {
889 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
890
891 *pMemoryProperties = physical_device->memory_properties;
892 }
893
894 void radv_GetPhysicalDeviceMemoryProperties2KHR(
895 VkPhysicalDevice physicalDevice,
896 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
897 {
898 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
899 &pMemoryProperties->memoryProperties);
900 }
901
902 static enum radeon_ctx_priority
903 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
904 {
905 /* Default to MEDIUM when a specific global priority isn't requested */
906 if (!pObj)
907 return RADEON_CTX_PRIORITY_MEDIUM;
908
909 switch(pObj->globalPriority) {
910 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
911 return RADEON_CTX_PRIORITY_REALTIME;
912 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
913 return RADEON_CTX_PRIORITY_HIGH;
914 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
915 return RADEON_CTX_PRIORITY_MEDIUM;
916 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
917 return RADEON_CTX_PRIORITY_LOW;
918 default:
919 unreachable("Illegal global priority value");
920 return RADEON_CTX_PRIORITY_INVALID;
921 }
922 }
923
924 static int
925 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
926 uint32_t queue_family_index, int idx,
927 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
928 {
929 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
930 queue->device = device;
931 queue->queue_family_index = queue_family_index;
932 queue->queue_idx = idx;
933 queue->priority = radv_get_queue_global_priority(global_priority);
934
935 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
936 if (!queue->hw_ctx)
937 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
938
939 return VK_SUCCESS;
940 }
941
942 static void
943 radv_queue_finish(struct radv_queue *queue)
944 {
945 if (queue->hw_ctx)
946 queue->device->ws->ctx_destroy(queue->hw_ctx);
947
948 if (queue->initial_full_flush_preamble_cs)
949 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
950 if (queue->initial_preamble_cs)
951 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
952 if (queue->continue_preamble_cs)
953 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
954 if (queue->descriptor_bo)
955 queue->device->ws->buffer_destroy(queue->descriptor_bo);
956 if (queue->scratch_bo)
957 queue->device->ws->buffer_destroy(queue->scratch_bo);
958 if (queue->esgs_ring_bo)
959 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
960 if (queue->gsvs_ring_bo)
961 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
962 if (queue->tess_factor_ring_bo)
963 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
964 if (queue->tess_offchip_ring_bo)
965 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
966 if (queue->compute_scratch_bo)
967 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
968 }
969
970 static void
971 radv_device_init_gs_info(struct radv_device *device)
972 {
973 switch (device->physical_device->rad_info.family) {
974 case CHIP_OLAND:
975 case CHIP_HAINAN:
976 case CHIP_KAVERI:
977 case CHIP_KABINI:
978 case CHIP_MULLINS:
979 case CHIP_ICELAND:
980 case CHIP_CARRIZO:
981 case CHIP_STONEY:
982 device->gs_table_depth = 16;
983 return;
984 case CHIP_TAHITI:
985 case CHIP_PITCAIRN:
986 case CHIP_VERDE:
987 case CHIP_BONAIRE:
988 case CHIP_HAWAII:
989 case CHIP_TONGA:
990 case CHIP_FIJI:
991 case CHIP_POLARIS10:
992 case CHIP_POLARIS11:
993 case CHIP_POLARIS12:
994 case CHIP_VEGA10:
995 case CHIP_RAVEN:
996 device->gs_table_depth = 32;
997 return;
998 default:
999 unreachable("unknown GPU");
1000 }
1001 }
1002
1003 VkResult radv_CreateDevice(
1004 VkPhysicalDevice physicalDevice,
1005 const VkDeviceCreateInfo* pCreateInfo,
1006 const VkAllocationCallbacks* pAllocator,
1007 VkDevice* pDevice)
1008 {
1009 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1010 VkResult result;
1011 struct radv_device *device;
1012
1013 bool keep_shader_info = false;
1014
1015 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1016 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1017 if (!radv_physical_device_extension_supported(physical_device, ext_name))
1018 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1019
1020 if (strcmp(ext_name, VK_AMD_SHADER_INFO_EXTENSION_NAME) == 0)
1021 keep_shader_info = true;
1022 }
1023
1024 /* Check enabled features */
1025 if (pCreateInfo->pEnabledFeatures) {
1026 VkPhysicalDeviceFeatures supported_features;
1027 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1028 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1029 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1030 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1031 for (uint32_t i = 0; i < num_features; i++) {
1032 if (enabled_feature[i] && !supported_feature[i])
1033 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1034 }
1035 }
1036
1037 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1038 sizeof(*device), 8,
1039 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1040 if (!device)
1041 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1042
1043 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1044 device->instance = physical_device->instance;
1045 device->physical_device = physical_device;
1046
1047 device->ws = physical_device->ws;
1048 if (pAllocator)
1049 device->alloc = *pAllocator;
1050 else
1051 device->alloc = physical_device->instance->alloc;
1052
1053 mtx_init(&device->shader_slab_mutex, mtx_plain);
1054 list_inithead(&device->shader_slabs);
1055
1056 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1057 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1058 uint32_t qfi = queue_create->queueFamilyIndex;
1059 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1060 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1061
1062 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1063
1064 device->queues[qfi] = vk_alloc(&device->alloc,
1065 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1066 if (!device->queues[qfi]) {
1067 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1068 goto fail;
1069 }
1070
1071 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1072
1073 device->queue_count[qfi] = queue_create->queueCount;
1074
1075 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1076 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q, global_priority);
1077 if (result != VK_SUCCESS)
1078 goto fail;
1079 }
1080 }
1081
1082 #if HAVE_LLVM < 0x0400
1083 device->llvm_supports_spill = false;
1084 #else
1085 device->llvm_supports_spill = true;
1086 #endif
1087
1088 /* The maximum number of scratch waves. Scratch space isn't divided
1089 * evenly between CUs. The number is only a function of the number of CUs.
1090 * We can decrease the constant to decrease the scratch buffer size.
1091 *
1092 * sctx->scratch_waves must be >= the maximum posible size of
1093 * 1 threadgroup, so that the hw doesn't hang from being unable
1094 * to start any.
1095 *
1096 * The recommended value is 4 per CU at most. Higher numbers don't
1097 * bring much benefit, but they still occupy chip resources (think
1098 * async compute). I've seen ~2% performance difference between 4 and 32.
1099 */
1100 uint32_t max_threads_per_block = 2048;
1101 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1102 max_threads_per_block / 64);
1103
1104 radv_device_init_gs_info(device);
1105
1106 device->tess_offchip_block_dw_size =
1107 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1108 device->has_distributed_tess =
1109 device->physical_device->rad_info.chip_class >= VI &&
1110 device->physical_device->rad_info.max_se >= 2;
1111
1112 if (getenv("RADV_TRACE_FILE")) {
1113 keep_shader_info = true;
1114
1115 if (!radv_init_trace(device))
1116 goto fail;
1117 }
1118
1119 device->keep_shader_info = keep_shader_info;
1120
1121 result = radv_device_init_meta(device);
1122 if (result != VK_SUCCESS)
1123 goto fail;
1124
1125 radv_device_init_msaa(device);
1126
1127 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1128 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1129 switch (family) {
1130 case RADV_QUEUE_GENERAL:
1131 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1132 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1133 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1134 break;
1135 case RADV_QUEUE_COMPUTE:
1136 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1137 radeon_emit(device->empty_cs[family], 0);
1138 break;
1139 }
1140 device->ws->cs_finalize(device->empty_cs[family]);
1141 }
1142
1143 if (device->physical_device->rad_info.chip_class >= CIK)
1144 cik_create_gfx_config(device);
1145
1146 VkPipelineCacheCreateInfo ci;
1147 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1148 ci.pNext = NULL;
1149 ci.flags = 0;
1150 ci.pInitialData = NULL;
1151 ci.initialDataSize = 0;
1152 VkPipelineCache pc;
1153 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1154 &ci, NULL, &pc);
1155 if (result != VK_SUCCESS)
1156 goto fail;
1157
1158 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1159
1160 *pDevice = radv_device_to_handle(device);
1161 return VK_SUCCESS;
1162
1163 fail:
1164 if (device->trace_bo)
1165 device->ws->buffer_destroy(device->trace_bo);
1166
1167 if (device->gfx_init)
1168 device->ws->buffer_destroy(device->gfx_init);
1169
1170 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1171 for (unsigned q = 0; q < device->queue_count[i]; q++)
1172 radv_queue_finish(&device->queues[i][q]);
1173 if (device->queue_count[i])
1174 vk_free(&device->alloc, device->queues[i]);
1175 }
1176
1177 vk_free(&device->alloc, device);
1178 return result;
1179 }
1180
1181 void radv_DestroyDevice(
1182 VkDevice _device,
1183 const VkAllocationCallbacks* pAllocator)
1184 {
1185 RADV_FROM_HANDLE(radv_device, device, _device);
1186
1187 if (!device)
1188 return;
1189
1190 if (device->trace_bo)
1191 device->ws->buffer_destroy(device->trace_bo);
1192
1193 if (device->gfx_init)
1194 device->ws->buffer_destroy(device->gfx_init);
1195
1196 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1197 for (unsigned q = 0; q < device->queue_count[i]; q++)
1198 radv_queue_finish(&device->queues[i][q]);
1199 if (device->queue_count[i])
1200 vk_free(&device->alloc, device->queues[i]);
1201 if (device->empty_cs[i])
1202 device->ws->cs_destroy(device->empty_cs[i]);
1203 }
1204 radv_device_finish_meta(device);
1205
1206 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1207 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1208
1209 radv_destroy_shader_slabs(device);
1210
1211 vk_free(&device->alloc, device);
1212 }
1213
1214 VkResult radv_EnumerateInstanceLayerProperties(
1215 uint32_t* pPropertyCount,
1216 VkLayerProperties* pProperties)
1217 {
1218 if (pProperties == NULL) {
1219 *pPropertyCount = 0;
1220 return VK_SUCCESS;
1221 }
1222
1223 /* None supported at this time */
1224 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1225 }
1226
1227 VkResult radv_EnumerateDeviceLayerProperties(
1228 VkPhysicalDevice physicalDevice,
1229 uint32_t* pPropertyCount,
1230 VkLayerProperties* pProperties)
1231 {
1232 if (pProperties == NULL) {
1233 *pPropertyCount = 0;
1234 return VK_SUCCESS;
1235 }
1236
1237 /* None supported at this time */
1238 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1239 }
1240
1241 void radv_GetDeviceQueue(
1242 VkDevice _device,
1243 uint32_t queueFamilyIndex,
1244 uint32_t queueIndex,
1245 VkQueue* pQueue)
1246 {
1247 RADV_FROM_HANDLE(radv_device, device, _device);
1248
1249 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1250 }
1251
1252 static void
1253 fill_geom_tess_rings(struct radv_queue *queue,
1254 uint32_t *map,
1255 bool add_sample_positions,
1256 uint32_t esgs_ring_size,
1257 struct radeon_winsys_bo *esgs_ring_bo,
1258 uint32_t gsvs_ring_size,
1259 struct radeon_winsys_bo *gsvs_ring_bo,
1260 uint32_t tess_factor_ring_size,
1261 struct radeon_winsys_bo *tess_factor_ring_bo,
1262 uint32_t tess_offchip_ring_size,
1263 struct radeon_winsys_bo *tess_offchip_ring_bo)
1264 {
1265 uint64_t esgs_va = 0, gsvs_va = 0;
1266 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1267 uint32_t *desc = &map[4];
1268
1269 if (esgs_ring_bo)
1270 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1271 if (gsvs_ring_bo)
1272 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1273 if (tess_factor_ring_bo)
1274 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1275 if (tess_offchip_ring_bo)
1276 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1277
1278 /* stride 0, num records - size, add tid, swizzle, elsize4,
1279 index stride 64 */
1280 desc[0] = esgs_va;
1281 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1282 S_008F04_STRIDE(0) |
1283 S_008F04_SWIZZLE_ENABLE(true);
1284 desc[2] = esgs_ring_size;
1285 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1286 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1287 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1288 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1289 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1290 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1291 S_008F0C_ELEMENT_SIZE(1) |
1292 S_008F0C_INDEX_STRIDE(3) |
1293 S_008F0C_ADD_TID_ENABLE(true);
1294
1295 desc += 4;
1296 /* GS entry for ES->GS ring */
1297 /* stride 0, num records - size, elsize0,
1298 index stride 0 */
1299 desc[0] = esgs_va;
1300 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1301 S_008F04_STRIDE(0) |
1302 S_008F04_SWIZZLE_ENABLE(false);
1303 desc[2] = esgs_ring_size;
1304 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1305 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1306 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1307 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1308 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1309 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1310 S_008F0C_ELEMENT_SIZE(0) |
1311 S_008F0C_INDEX_STRIDE(0) |
1312 S_008F0C_ADD_TID_ENABLE(false);
1313
1314 desc += 4;
1315 /* VS entry for GS->VS ring */
1316 /* stride 0, num records - size, elsize0,
1317 index stride 0 */
1318 desc[0] = gsvs_va;
1319 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1320 S_008F04_STRIDE(0) |
1321 S_008F04_SWIZZLE_ENABLE(false);
1322 desc[2] = gsvs_ring_size;
1323 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1324 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1325 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1326 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1327 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1328 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1329 S_008F0C_ELEMENT_SIZE(0) |
1330 S_008F0C_INDEX_STRIDE(0) |
1331 S_008F0C_ADD_TID_ENABLE(false);
1332 desc += 4;
1333
1334 /* stride gsvs_itemsize, num records 64
1335 elsize 4, index stride 16 */
1336 /* shader will patch stride and desc[2] */
1337 desc[0] = gsvs_va;
1338 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1339 S_008F04_STRIDE(0) |
1340 S_008F04_SWIZZLE_ENABLE(true);
1341 desc[2] = 0;
1342 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1343 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1344 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1345 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1346 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1347 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1348 S_008F0C_ELEMENT_SIZE(1) |
1349 S_008F0C_INDEX_STRIDE(1) |
1350 S_008F0C_ADD_TID_ENABLE(true);
1351 desc += 4;
1352
1353 desc[0] = tess_factor_va;
1354 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1355 S_008F04_STRIDE(0) |
1356 S_008F04_SWIZZLE_ENABLE(false);
1357 desc[2] = tess_factor_ring_size;
1358 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1359 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1360 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1361 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1362 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1363 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1364 S_008F0C_ELEMENT_SIZE(0) |
1365 S_008F0C_INDEX_STRIDE(0) |
1366 S_008F0C_ADD_TID_ENABLE(false);
1367 desc += 4;
1368
1369 desc[0] = tess_offchip_va;
1370 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1371 S_008F04_STRIDE(0) |
1372 S_008F04_SWIZZLE_ENABLE(false);
1373 desc[2] = tess_offchip_ring_size;
1374 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1375 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1376 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1377 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1378 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1379 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1380 S_008F0C_ELEMENT_SIZE(0) |
1381 S_008F0C_INDEX_STRIDE(0) |
1382 S_008F0C_ADD_TID_ENABLE(false);
1383 desc += 4;
1384
1385 /* add sample positions after all rings */
1386 memcpy(desc, queue->device->sample_locations_1x, 8);
1387 desc += 2;
1388 memcpy(desc, queue->device->sample_locations_2x, 16);
1389 desc += 4;
1390 memcpy(desc, queue->device->sample_locations_4x, 32);
1391 desc += 8;
1392 memcpy(desc, queue->device->sample_locations_8x, 64);
1393 desc += 16;
1394 memcpy(desc, queue->device->sample_locations_16x, 128);
1395 }
1396
1397 static unsigned
1398 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1399 {
1400 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1401 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1402 device->physical_device->rad_info.family != CHIP_STONEY;
1403 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1404 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1405 device->physical_device->rad_info.max_se;
1406 unsigned offchip_granularity;
1407 unsigned hs_offchip_param;
1408 switch (device->tess_offchip_block_dw_size) {
1409 default:
1410 assert(0);
1411 /* fall through */
1412 case 8192:
1413 offchip_granularity = V_03093C_X_8K_DWORDS;
1414 break;
1415 case 4096:
1416 offchip_granularity = V_03093C_X_4K_DWORDS;
1417 break;
1418 }
1419
1420 switch (device->physical_device->rad_info.chip_class) {
1421 case SI:
1422 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1423 break;
1424 case CIK:
1425 case VI:
1426 case GFX9:
1427 default:
1428 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1429 break;
1430 }
1431
1432 *max_offchip_buffers_p = max_offchip_buffers;
1433 if (device->physical_device->rad_info.chip_class >= CIK) {
1434 if (device->physical_device->rad_info.chip_class >= VI)
1435 --max_offchip_buffers;
1436 hs_offchip_param =
1437 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1438 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1439 } else {
1440 hs_offchip_param =
1441 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1442 }
1443 return hs_offchip_param;
1444 }
1445
1446 static VkResult
1447 radv_get_preamble_cs(struct radv_queue *queue,
1448 uint32_t scratch_size,
1449 uint32_t compute_scratch_size,
1450 uint32_t esgs_ring_size,
1451 uint32_t gsvs_ring_size,
1452 bool needs_tess_rings,
1453 bool needs_sample_positions,
1454 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1455 struct radeon_winsys_cs **initial_preamble_cs,
1456 struct radeon_winsys_cs **continue_preamble_cs)
1457 {
1458 struct radeon_winsys_bo *scratch_bo = NULL;
1459 struct radeon_winsys_bo *descriptor_bo = NULL;
1460 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1461 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1462 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1463 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1464 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1465 struct radeon_winsys_cs *dest_cs[3] = {0};
1466 bool add_tess_rings = false, add_sample_positions = false;
1467 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1468 unsigned max_offchip_buffers;
1469 unsigned hs_offchip_param = 0;
1470 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
1471 if (!queue->has_tess_rings) {
1472 if (needs_tess_rings)
1473 add_tess_rings = true;
1474 }
1475 if (!queue->has_sample_positions) {
1476 if (needs_sample_positions)
1477 add_sample_positions = true;
1478 }
1479 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1480 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1481 &max_offchip_buffers);
1482 tess_offchip_ring_size = max_offchip_buffers *
1483 queue->device->tess_offchip_block_dw_size * 4;
1484
1485 if (scratch_size <= queue->scratch_size &&
1486 compute_scratch_size <= queue->compute_scratch_size &&
1487 esgs_ring_size <= queue->esgs_ring_size &&
1488 gsvs_ring_size <= queue->gsvs_ring_size &&
1489 !add_tess_rings && !add_sample_positions &&
1490 queue->initial_preamble_cs) {
1491 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1492 *initial_preamble_cs = queue->initial_preamble_cs;
1493 *continue_preamble_cs = queue->continue_preamble_cs;
1494 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1495 *continue_preamble_cs = NULL;
1496 return VK_SUCCESS;
1497 }
1498
1499 if (scratch_size > queue->scratch_size) {
1500 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1501 scratch_size,
1502 4096,
1503 RADEON_DOMAIN_VRAM,
1504 ring_bo_flags);
1505 if (!scratch_bo)
1506 goto fail;
1507 } else
1508 scratch_bo = queue->scratch_bo;
1509
1510 if (compute_scratch_size > queue->compute_scratch_size) {
1511 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1512 compute_scratch_size,
1513 4096,
1514 RADEON_DOMAIN_VRAM,
1515 ring_bo_flags);
1516 if (!compute_scratch_bo)
1517 goto fail;
1518
1519 } else
1520 compute_scratch_bo = queue->compute_scratch_bo;
1521
1522 if (esgs_ring_size > queue->esgs_ring_size) {
1523 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1524 esgs_ring_size,
1525 4096,
1526 RADEON_DOMAIN_VRAM,
1527 ring_bo_flags);
1528 if (!esgs_ring_bo)
1529 goto fail;
1530 } else {
1531 esgs_ring_bo = queue->esgs_ring_bo;
1532 esgs_ring_size = queue->esgs_ring_size;
1533 }
1534
1535 if (gsvs_ring_size > queue->gsvs_ring_size) {
1536 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1537 gsvs_ring_size,
1538 4096,
1539 RADEON_DOMAIN_VRAM,
1540 ring_bo_flags);
1541 if (!gsvs_ring_bo)
1542 goto fail;
1543 } else {
1544 gsvs_ring_bo = queue->gsvs_ring_bo;
1545 gsvs_ring_size = queue->gsvs_ring_size;
1546 }
1547
1548 if (add_tess_rings) {
1549 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1550 tess_factor_ring_size,
1551 256,
1552 RADEON_DOMAIN_VRAM,
1553 ring_bo_flags);
1554 if (!tess_factor_ring_bo)
1555 goto fail;
1556 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1557 tess_offchip_ring_size,
1558 256,
1559 RADEON_DOMAIN_VRAM,
1560 ring_bo_flags);
1561 if (!tess_offchip_ring_bo)
1562 goto fail;
1563 } else {
1564 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1565 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1566 }
1567
1568 if (scratch_bo != queue->scratch_bo ||
1569 esgs_ring_bo != queue->esgs_ring_bo ||
1570 gsvs_ring_bo != queue->gsvs_ring_bo ||
1571 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1572 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1573 uint32_t size = 0;
1574 if (gsvs_ring_bo || esgs_ring_bo ||
1575 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1576 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1577 if (add_sample_positions)
1578 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1579 }
1580 else if (scratch_bo)
1581 size = 8; /* 2 dword */
1582
1583 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1584 size,
1585 4096,
1586 RADEON_DOMAIN_VRAM,
1587 RADEON_FLAG_CPU_ACCESS|RADEON_FLAG_NO_INTERPROCESS_SHARING);
1588 if (!descriptor_bo)
1589 goto fail;
1590 } else
1591 descriptor_bo = queue->descriptor_bo;
1592
1593 for(int i = 0; i < 3; ++i) {
1594 struct radeon_winsys_cs *cs = NULL;
1595 cs = queue->device->ws->cs_create(queue->device->ws,
1596 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1597 if (!cs)
1598 goto fail;
1599
1600 dest_cs[i] = cs;
1601
1602 if (scratch_bo)
1603 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo, 8);
1604
1605 if (esgs_ring_bo)
1606 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo, 8);
1607
1608 if (gsvs_ring_bo)
1609 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo, 8);
1610
1611 if (tess_factor_ring_bo)
1612 radv_cs_add_buffer(queue->device->ws, cs, tess_factor_ring_bo, 8);
1613
1614 if (tess_offchip_ring_bo)
1615 radv_cs_add_buffer(queue->device->ws, cs, tess_offchip_ring_bo, 8);
1616
1617 if (descriptor_bo)
1618 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo, 8);
1619
1620 if (descriptor_bo != queue->descriptor_bo) {
1621 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1622
1623 if (scratch_bo) {
1624 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1625 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1626 S_008F04_SWIZZLE_ENABLE(1);
1627 map[0] = scratch_va;
1628 map[1] = rsrc1;
1629 }
1630
1631 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1632 add_sample_positions)
1633 fill_geom_tess_rings(queue, map, add_sample_positions,
1634 esgs_ring_size, esgs_ring_bo,
1635 gsvs_ring_size, gsvs_ring_bo,
1636 tess_factor_ring_size, tess_factor_ring_bo,
1637 tess_offchip_ring_size, tess_offchip_ring_bo);
1638
1639 queue->device->ws->buffer_unmap(descriptor_bo);
1640 }
1641
1642 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1643 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1644 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1645 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1646 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1647 }
1648
1649 if (esgs_ring_bo || gsvs_ring_bo) {
1650 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1651 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1652 radeon_emit(cs, esgs_ring_size >> 8);
1653 radeon_emit(cs, gsvs_ring_size >> 8);
1654 } else {
1655 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1656 radeon_emit(cs, esgs_ring_size >> 8);
1657 radeon_emit(cs, gsvs_ring_size >> 8);
1658 }
1659 }
1660
1661 if (tess_factor_ring_bo) {
1662 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1663 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1664 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1665 S_030938_SIZE(tess_factor_ring_size / 4));
1666 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1667 tf_va >> 8);
1668 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1669 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1670 tf_va >> 40);
1671 }
1672 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1673 } else {
1674 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1675 S_008988_SIZE(tess_factor_ring_size / 4));
1676 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1677 tf_va >> 8);
1678 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1679 hs_offchip_param);
1680 }
1681 }
1682
1683 if (descriptor_bo) {
1684 uint64_t va = radv_buffer_get_va(descriptor_bo);
1685 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1686 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1687 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1688 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1689 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1690
1691 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1692 radeon_set_sh_reg_seq(cs, regs[i], 2);
1693 radeon_emit(cs, va);
1694 radeon_emit(cs, va >> 32);
1695 }
1696 } else {
1697 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1698 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1699 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1700 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1701 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1702 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1703
1704 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1705 radeon_set_sh_reg_seq(cs, regs[i], 2);
1706 radeon_emit(cs, va);
1707 radeon_emit(cs, va >> 32);
1708 }
1709 }
1710 }
1711
1712 if (compute_scratch_bo) {
1713 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1714 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1715 S_008F04_SWIZZLE_ENABLE(1);
1716
1717 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo, 8);
1718
1719 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1720 radeon_emit(cs, scratch_va);
1721 radeon_emit(cs, rsrc1);
1722 }
1723
1724 if (i == 0) {
1725 si_cs_emit_cache_flush(cs,
1726 false,
1727 queue->device->physical_device->rad_info.chip_class,
1728 NULL, 0,
1729 queue->queue_family_index == RING_COMPUTE &&
1730 queue->device->physical_device->rad_info.chip_class >= CIK,
1731 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1732 RADV_CMD_FLAG_INV_ICACHE |
1733 RADV_CMD_FLAG_INV_SMEM_L1 |
1734 RADV_CMD_FLAG_INV_VMEM_L1 |
1735 RADV_CMD_FLAG_INV_GLOBAL_L2);
1736 } else if (i == 1) {
1737 si_cs_emit_cache_flush(cs,
1738 false,
1739 queue->device->physical_device->rad_info.chip_class,
1740 NULL, 0,
1741 queue->queue_family_index == RING_COMPUTE &&
1742 queue->device->physical_device->rad_info.chip_class >= CIK,
1743 RADV_CMD_FLAG_INV_ICACHE |
1744 RADV_CMD_FLAG_INV_SMEM_L1 |
1745 RADV_CMD_FLAG_INV_VMEM_L1 |
1746 RADV_CMD_FLAG_INV_GLOBAL_L2);
1747 }
1748
1749 if (!queue->device->ws->cs_finalize(cs))
1750 goto fail;
1751 }
1752
1753 if (queue->initial_full_flush_preamble_cs)
1754 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1755
1756 if (queue->initial_preamble_cs)
1757 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1758
1759 if (queue->continue_preamble_cs)
1760 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1761
1762 queue->initial_full_flush_preamble_cs = dest_cs[0];
1763 queue->initial_preamble_cs = dest_cs[1];
1764 queue->continue_preamble_cs = dest_cs[2];
1765
1766 if (scratch_bo != queue->scratch_bo) {
1767 if (queue->scratch_bo)
1768 queue->device->ws->buffer_destroy(queue->scratch_bo);
1769 queue->scratch_bo = scratch_bo;
1770 queue->scratch_size = scratch_size;
1771 }
1772
1773 if (compute_scratch_bo != queue->compute_scratch_bo) {
1774 if (queue->compute_scratch_bo)
1775 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1776 queue->compute_scratch_bo = compute_scratch_bo;
1777 queue->compute_scratch_size = compute_scratch_size;
1778 }
1779
1780 if (esgs_ring_bo != queue->esgs_ring_bo) {
1781 if (queue->esgs_ring_bo)
1782 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1783 queue->esgs_ring_bo = esgs_ring_bo;
1784 queue->esgs_ring_size = esgs_ring_size;
1785 }
1786
1787 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1788 if (queue->gsvs_ring_bo)
1789 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1790 queue->gsvs_ring_bo = gsvs_ring_bo;
1791 queue->gsvs_ring_size = gsvs_ring_size;
1792 }
1793
1794 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1795 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1796 }
1797
1798 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1799 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1800 queue->has_tess_rings = true;
1801 }
1802
1803 if (descriptor_bo != queue->descriptor_bo) {
1804 if (queue->descriptor_bo)
1805 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1806
1807 queue->descriptor_bo = descriptor_bo;
1808 }
1809
1810 if (add_sample_positions)
1811 queue->has_sample_positions = true;
1812
1813 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1814 *initial_preamble_cs = queue->initial_preamble_cs;
1815 *continue_preamble_cs = queue->continue_preamble_cs;
1816 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1817 *continue_preamble_cs = NULL;
1818 return VK_SUCCESS;
1819 fail:
1820 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1821 if (dest_cs[i])
1822 queue->device->ws->cs_destroy(dest_cs[i]);
1823 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1824 queue->device->ws->buffer_destroy(descriptor_bo);
1825 if (scratch_bo && scratch_bo != queue->scratch_bo)
1826 queue->device->ws->buffer_destroy(scratch_bo);
1827 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1828 queue->device->ws->buffer_destroy(compute_scratch_bo);
1829 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1830 queue->device->ws->buffer_destroy(esgs_ring_bo);
1831 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1832 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1833 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1834 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1835 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1836 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1837 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
1838 }
1839
1840 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1841 int num_sems,
1842 const VkSemaphore *sems,
1843 bool reset_temp)
1844 {
1845 int syncobj_idx = 0, sem_idx = 0;
1846
1847 if (num_sems == 0)
1848 return VK_SUCCESS;
1849 for (uint32_t i = 0; i < num_sems; i++) {
1850 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1851
1852 if (sem->temp_syncobj || sem->syncobj)
1853 counts->syncobj_count++;
1854 else
1855 counts->sem_count++;
1856 }
1857
1858 if (counts->syncobj_count) {
1859 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1860 if (!counts->syncobj)
1861 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1862 }
1863
1864 if (counts->sem_count) {
1865 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1866 if (!counts->sem) {
1867 free(counts->syncobj);
1868 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1869 }
1870 }
1871
1872 for (uint32_t i = 0; i < num_sems; i++) {
1873 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1874
1875 if (sem->temp_syncobj) {
1876 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1877 }
1878 else if (sem->syncobj)
1879 counts->syncobj[syncobj_idx++] = sem->syncobj;
1880 else {
1881 assert(sem->sem);
1882 counts->sem[sem_idx++] = sem->sem;
1883 }
1884 }
1885
1886 return VK_SUCCESS;
1887 }
1888
1889 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1890 {
1891 free(sem_info->wait.syncobj);
1892 free(sem_info->wait.sem);
1893 free(sem_info->signal.syncobj);
1894 free(sem_info->signal.sem);
1895 }
1896
1897
1898 static void radv_free_temp_syncobjs(struct radv_device *device,
1899 int num_sems,
1900 const VkSemaphore *sems)
1901 {
1902 for (uint32_t i = 0; i < num_sems; i++) {
1903 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1904
1905 if (sem->temp_syncobj) {
1906 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
1907 sem->temp_syncobj = 0;
1908 }
1909 }
1910 }
1911
1912 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1913 int num_wait_sems,
1914 const VkSemaphore *wait_sems,
1915 int num_signal_sems,
1916 const VkSemaphore *signal_sems)
1917 {
1918 VkResult ret;
1919 memset(sem_info, 0, sizeof(*sem_info));
1920
1921 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1922 if (ret)
1923 return ret;
1924 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1925 if (ret)
1926 radv_free_sem_info(sem_info);
1927
1928 /* caller can override these */
1929 sem_info->cs_emit_wait = true;
1930 sem_info->cs_emit_signal = true;
1931 return ret;
1932 }
1933
1934 VkResult radv_QueueSubmit(
1935 VkQueue _queue,
1936 uint32_t submitCount,
1937 const VkSubmitInfo* pSubmits,
1938 VkFence _fence)
1939 {
1940 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1941 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1942 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1943 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1944 int ret;
1945 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1946 uint32_t scratch_size = 0;
1947 uint32_t compute_scratch_size = 0;
1948 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1949 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1950 VkResult result;
1951 bool fence_emitted = false;
1952 bool tess_rings_needed = false;
1953 bool sample_positions_needed = false;
1954
1955 /* Do this first so failing to allocate scratch buffers can't result in
1956 * partially executed submissions. */
1957 for (uint32_t i = 0; i < submitCount; i++) {
1958 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1959 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1960 pSubmits[i].pCommandBuffers[j]);
1961
1962 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1963 compute_scratch_size = MAX2(compute_scratch_size,
1964 cmd_buffer->compute_scratch_size_needed);
1965 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1966 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1967 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1968 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1969 }
1970 }
1971
1972 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1973 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1974 sample_positions_needed, &initial_flush_preamble_cs,
1975 &initial_preamble_cs, &continue_preamble_cs);
1976 if (result != VK_SUCCESS)
1977 return result;
1978
1979 for (uint32_t i = 0; i < submitCount; i++) {
1980 struct radeon_winsys_cs **cs_array;
1981 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1982 bool can_patch = true;
1983 uint32_t advance;
1984 struct radv_winsys_sem_info sem_info;
1985
1986 result = radv_alloc_sem_info(&sem_info,
1987 pSubmits[i].waitSemaphoreCount,
1988 pSubmits[i].pWaitSemaphores,
1989 pSubmits[i].signalSemaphoreCount,
1990 pSubmits[i].pSignalSemaphores);
1991 if (result != VK_SUCCESS)
1992 return result;
1993
1994 if (!pSubmits[i].commandBufferCount) {
1995 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1996 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1997 &queue->device->empty_cs[queue->queue_family_index],
1998 1, NULL, NULL,
1999 &sem_info,
2000 false, base_fence);
2001 if (ret) {
2002 radv_loge("failed to submit CS %d\n", i);
2003 abort();
2004 }
2005 fence_emitted = true;
2006 }
2007 radv_free_sem_info(&sem_info);
2008 continue;
2009 }
2010
2011 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2012 (pSubmits[i].commandBufferCount));
2013
2014 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2015 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2016 pSubmits[i].pCommandBuffers[j]);
2017 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2018
2019 cs_array[j] = cmd_buffer->cs;
2020 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2021 can_patch = false;
2022
2023 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2024 }
2025
2026 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2027 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2028 advance = MIN2(max_cs_submission,
2029 pSubmits[i].commandBufferCount - j);
2030
2031 if (queue->device->trace_bo)
2032 *queue->device->trace_id_ptr = 0;
2033
2034 sem_info.cs_emit_wait = j == 0;
2035 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2036
2037 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2038 advance, initial_preamble, continue_preamble_cs,
2039 &sem_info,
2040 can_patch, base_fence);
2041
2042 if (ret) {
2043 radv_loge("failed to submit CS %d\n", i);
2044 abort();
2045 }
2046 fence_emitted = true;
2047 if (queue->device->trace_bo) {
2048 radv_check_gpu_hangs(queue, cs_array[j]);
2049 }
2050 }
2051
2052 radv_free_temp_syncobjs(queue->device,
2053 pSubmits[i].waitSemaphoreCount,
2054 pSubmits[i].pWaitSemaphores);
2055 radv_free_sem_info(&sem_info);
2056 free(cs_array);
2057 }
2058
2059 if (fence) {
2060 if (!fence_emitted) {
2061 struct radv_winsys_sem_info sem_info = {0};
2062 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2063 &queue->device->empty_cs[queue->queue_family_index],
2064 1, NULL, NULL, &sem_info,
2065 false, base_fence);
2066 }
2067 fence->submitted = true;
2068 }
2069
2070 return VK_SUCCESS;
2071 }
2072
2073 VkResult radv_QueueWaitIdle(
2074 VkQueue _queue)
2075 {
2076 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2077
2078 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2079 radv_queue_family_to_ring(queue->queue_family_index),
2080 queue->queue_idx);
2081 return VK_SUCCESS;
2082 }
2083
2084 VkResult radv_DeviceWaitIdle(
2085 VkDevice _device)
2086 {
2087 RADV_FROM_HANDLE(radv_device, device, _device);
2088
2089 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2090 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2091 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2092 }
2093 }
2094 return VK_SUCCESS;
2095 }
2096
2097 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2098 VkInstance instance,
2099 const char* pName)
2100 {
2101 return radv_lookup_entrypoint(pName);
2102 }
2103
2104 /* The loader wants us to expose a second GetInstanceProcAddr function
2105 * to work around certain LD_PRELOAD issues seen in apps.
2106 */
2107 PUBLIC
2108 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2109 VkInstance instance,
2110 const char* pName);
2111
2112 PUBLIC
2113 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2114 VkInstance instance,
2115 const char* pName)
2116 {
2117 return radv_GetInstanceProcAddr(instance, pName);
2118 }
2119
2120 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2121 VkDevice device,
2122 const char* pName)
2123 {
2124 return radv_lookup_entrypoint(pName);
2125 }
2126
2127 bool radv_get_memory_fd(struct radv_device *device,
2128 struct radv_device_memory *memory,
2129 int *pFD)
2130 {
2131 struct radeon_bo_metadata metadata;
2132
2133 if (memory->image) {
2134 radv_init_metadata(device, memory->image, &metadata);
2135 device->ws->buffer_set_metadata(memory->bo, &metadata);
2136 }
2137
2138 return device->ws->buffer_get_fd(device->ws, memory->bo,
2139 pFD);
2140 }
2141
2142 static VkResult radv_alloc_memory(struct radv_device *device,
2143 const VkMemoryAllocateInfo* pAllocateInfo,
2144 const VkAllocationCallbacks* pAllocator,
2145 VkDeviceMemory* pMem)
2146 {
2147 struct radv_device_memory *mem;
2148 VkResult result;
2149 enum radeon_bo_domain domain;
2150 uint32_t flags = 0;
2151 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2152
2153 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2154
2155 if (pAllocateInfo->allocationSize == 0) {
2156 /* Apparently, this is allowed */
2157 *pMem = VK_NULL_HANDLE;
2158 return VK_SUCCESS;
2159 }
2160
2161 const VkImportMemoryFdInfoKHR *import_info =
2162 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2163 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2164 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2165 const VkExportMemoryAllocateInfoKHR *export_info =
2166 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2167
2168 const struct wsi_memory_allocate_info *wsi_info =
2169 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2170
2171 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2172 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2173 if (mem == NULL)
2174 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2175
2176 if (wsi_info && wsi_info->implicit_sync)
2177 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2178
2179 if (dedicate_info) {
2180 mem->image = radv_image_from_handle(dedicate_info->image);
2181 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2182 } else {
2183 mem->image = NULL;
2184 mem->buffer = NULL;
2185 }
2186
2187 if (import_info) {
2188 assert(import_info->handleType ==
2189 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2190 import_info->handleType ==
2191 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2192 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2193 NULL, NULL);
2194 if (!mem->bo) {
2195 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2196 goto fail;
2197 } else {
2198 close(import_info->fd);
2199 goto out_success;
2200 }
2201 }
2202
2203 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2204 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2205 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2206 domain = RADEON_DOMAIN_GTT;
2207 else
2208 domain = RADEON_DOMAIN_VRAM;
2209
2210 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2211 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2212 else
2213 flags |= RADEON_FLAG_CPU_ACCESS;
2214
2215 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2216 flags |= RADEON_FLAG_GTT_WC;
2217
2218 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2219 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2220
2221 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2222 domain, flags);
2223
2224 if (!mem->bo) {
2225 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2226 goto fail;
2227 }
2228 mem->type_index = mem_type_index;
2229 out_success:
2230 *pMem = radv_device_memory_to_handle(mem);
2231
2232 return VK_SUCCESS;
2233
2234 fail:
2235 vk_free2(&device->alloc, pAllocator, mem);
2236
2237 return result;
2238 }
2239
2240 VkResult radv_AllocateMemory(
2241 VkDevice _device,
2242 const VkMemoryAllocateInfo* pAllocateInfo,
2243 const VkAllocationCallbacks* pAllocator,
2244 VkDeviceMemory* pMem)
2245 {
2246 RADV_FROM_HANDLE(radv_device, device, _device);
2247 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2248 }
2249
2250 void radv_FreeMemory(
2251 VkDevice _device,
2252 VkDeviceMemory _mem,
2253 const VkAllocationCallbacks* pAllocator)
2254 {
2255 RADV_FROM_HANDLE(radv_device, device, _device);
2256 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2257
2258 if (mem == NULL)
2259 return;
2260
2261 device->ws->buffer_destroy(mem->bo);
2262 mem->bo = NULL;
2263
2264 vk_free2(&device->alloc, pAllocator, mem);
2265 }
2266
2267 VkResult radv_MapMemory(
2268 VkDevice _device,
2269 VkDeviceMemory _memory,
2270 VkDeviceSize offset,
2271 VkDeviceSize size,
2272 VkMemoryMapFlags flags,
2273 void** ppData)
2274 {
2275 RADV_FROM_HANDLE(radv_device, device, _device);
2276 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2277
2278 if (mem == NULL) {
2279 *ppData = NULL;
2280 return VK_SUCCESS;
2281 }
2282
2283 *ppData = device->ws->buffer_map(mem->bo);
2284 if (*ppData) {
2285 *ppData += offset;
2286 return VK_SUCCESS;
2287 }
2288
2289 return vk_error(VK_ERROR_MEMORY_MAP_FAILED);
2290 }
2291
2292 void radv_UnmapMemory(
2293 VkDevice _device,
2294 VkDeviceMemory _memory)
2295 {
2296 RADV_FROM_HANDLE(radv_device, device, _device);
2297 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2298
2299 if (mem == NULL)
2300 return;
2301
2302 device->ws->buffer_unmap(mem->bo);
2303 }
2304
2305 VkResult radv_FlushMappedMemoryRanges(
2306 VkDevice _device,
2307 uint32_t memoryRangeCount,
2308 const VkMappedMemoryRange* pMemoryRanges)
2309 {
2310 return VK_SUCCESS;
2311 }
2312
2313 VkResult radv_InvalidateMappedMemoryRanges(
2314 VkDevice _device,
2315 uint32_t memoryRangeCount,
2316 const VkMappedMemoryRange* pMemoryRanges)
2317 {
2318 return VK_SUCCESS;
2319 }
2320
2321 void radv_GetBufferMemoryRequirements(
2322 VkDevice _device,
2323 VkBuffer _buffer,
2324 VkMemoryRequirements* pMemoryRequirements)
2325 {
2326 RADV_FROM_HANDLE(radv_device, device, _device);
2327 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2328
2329 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2330
2331 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2332 pMemoryRequirements->alignment = 4096;
2333 else
2334 pMemoryRequirements->alignment = 16;
2335
2336 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2337 }
2338
2339 void radv_GetBufferMemoryRequirements2KHR(
2340 VkDevice device,
2341 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2342 VkMemoryRequirements2KHR* pMemoryRequirements)
2343 {
2344 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2345 &pMemoryRequirements->memoryRequirements);
2346 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2347 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2348 switch (ext->sType) {
2349 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2350 VkMemoryDedicatedRequirementsKHR *req =
2351 (VkMemoryDedicatedRequirementsKHR *) ext;
2352 req->requiresDedicatedAllocation = buffer->shareable;
2353 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2354 break;
2355 }
2356 default:
2357 break;
2358 }
2359 }
2360 }
2361
2362 void radv_GetImageMemoryRequirements(
2363 VkDevice _device,
2364 VkImage _image,
2365 VkMemoryRequirements* pMemoryRequirements)
2366 {
2367 RADV_FROM_HANDLE(radv_device, device, _device);
2368 RADV_FROM_HANDLE(radv_image, image, _image);
2369
2370 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2371
2372 pMemoryRequirements->size = image->size;
2373 pMemoryRequirements->alignment = image->alignment;
2374 }
2375
2376 void radv_GetImageMemoryRequirements2KHR(
2377 VkDevice device,
2378 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2379 VkMemoryRequirements2KHR* pMemoryRequirements)
2380 {
2381 radv_GetImageMemoryRequirements(device, pInfo->image,
2382 &pMemoryRequirements->memoryRequirements);
2383
2384 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2385
2386 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2387 switch (ext->sType) {
2388 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2389 VkMemoryDedicatedRequirementsKHR *req =
2390 (VkMemoryDedicatedRequirementsKHR *) ext;
2391 req->requiresDedicatedAllocation = image->shareable;
2392 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2393 break;
2394 }
2395 default:
2396 break;
2397 }
2398 }
2399 }
2400
2401 void radv_GetImageSparseMemoryRequirements(
2402 VkDevice device,
2403 VkImage image,
2404 uint32_t* pSparseMemoryRequirementCount,
2405 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2406 {
2407 stub();
2408 }
2409
2410 void radv_GetImageSparseMemoryRequirements2KHR(
2411 VkDevice device,
2412 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2413 uint32_t* pSparseMemoryRequirementCount,
2414 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2415 {
2416 stub();
2417 }
2418
2419 void radv_GetDeviceMemoryCommitment(
2420 VkDevice device,
2421 VkDeviceMemory memory,
2422 VkDeviceSize* pCommittedMemoryInBytes)
2423 {
2424 *pCommittedMemoryInBytes = 0;
2425 }
2426
2427 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2428 uint32_t bindInfoCount,
2429 const VkBindBufferMemoryInfoKHR *pBindInfos)
2430 {
2431 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2432 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2433 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2434
2435 if (mem) {
2436 buffer->bo = mem->bo;
2437 buffer->offset = pBindInfos[i].memoryOffset;
2438 } else {
2439 buffer->bo = NULL;
2440 }
2441 }
2442 return VK_SUCCESS;
2443 }
2444
2445 VkResult radv_BindBufferMemory(
2446 VkDevice device,
2447 VkBuffer buffer,
2448 VkDeviceMemory memory,
2449 VkDeviceSize memoryOffset)
2450 {
2451 const VkBindBufferMemoryInfoKHR info = {
2452 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2453 .buffer = buffer,
2454 .memory = memory,
2455 .memoryOffset = memoryOffset
2456 };
2457
2458 return radv_BindBufferMemory2KHR(device, 1, &info);
2459 }
2460
2461 VkResult radv_BindImageMemory2KHR(VkDevice device,
2462 uint32_t bindInfoCount,
2463 const VkBindImageMemoryInfoKHR *pBindInfos)
2464 {
2465 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2466 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2467 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2468
2469 if (mem) {
2470 image->bo = mem->bo;
2471 image->offset = pBindInfos[i].memoryOffset;
2472 } else {
2473 image->bo = NULL;
2474 image->offset = 0;
2475 }
2476 }
2477 return VK_SUCCESS;
2478 }
2479
2480
2481 VkResult radv_BindImageMemory(
2482 VkDevice device,
2483 VkImage image,
2484 VkDeviceMemory memory,
2485 VkDeviceSize memoryOffset)
2486 {
2487 const VkBindImageMemoryInfoKHR info = {
2488 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2489 .image = image,
2490 .memory = memory,
2491 .memoryOffset = memoryOffset
2492 };
2493
2494 return radv_BindImageMemory2KHR(device, 1, &info);
2495 }
2496
2497
2498 static void
2499 radv_sparse_buffer_bind_memory(struct radv_device *device,
2500 const VkSparseBufferMemoryBindInfo *bind)
2501 {
2502 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2503
2504 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2505 struct radv_device_memory *mem = NULL;
2506
2507 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2508 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2509
2510 device->ws->buffer_virtual_bind(buffer->bo,
2511 bind->pBinds[i].resourceOffset,
2512 bind->pBinds[i].size,
2513 mem ? mem->bo : NULL,
2514 bind->pBinds[i].memoryOffset);
2515 }
2516 }
2517
2518 static void
2519 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2520 const VkSparseImageOpaqueMemoryBindInfo *bind)
2521 {
2522 RADV_FROM_HANDLE(radv_image, image, bind->image);
2523
2524 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2525 struct radv_device_memory *mem = NULL;
2526
2527 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2528 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2529
2530 device->ws->buffer_virtual_bind(image->bo,
2531 bind->pBinds[i].resourceOffset,
2532 bind->pBinds[i].size,
2533 mem ? mem->bo : NULL,
2534 bind->pBinds[i].memoryOffset);
2535 }
2536 }
2537
2538 VkResult radv_QueueBindSparse(
2539 VkQueue _queue,
2540 uint32_t bindInfoCount,
2541 const VkBindSparseInfo* pBindInfo,
2542 VkFence _fence)
2543 {
2544 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2545 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2546 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2547 bool fence_emitted = false;
2548
2549 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2550 struct radv_winsys_sem_info sem_info;
2551 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2552 radv_sparse_buffer_bind_memory(queue->device,
2553 pBindInfo[i].pBufferBinds + j);
2554 }
2555
2556 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2557 radv_sparse_image_opaque_bind_memory(queue->device,
2558 pBindInfo[i].pImageOpaqueBinds + j);
2559 }
2560
2561 VkResult result;
2562 result = radv_alloc_sem_info(&sem_info,
2563 pBindInfo[i].waitSemaphoreCount,
2564 pBindInfo[i].pWaitSemaphores,
2565 pBindInfo[i].signalSemaphoreCount,
2566 pBindInfo[i].pSignalSemaphores);
2567 if (result != VK_SUCCESS)
2568 return result;
2569
2570 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2571 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2572 &queue->device->empty_cs[queue->queue_family_index],
2573 1, NULL, NULL,
2574 &sem_info,
2575 false, base_fence);
2576 fence_emitted = true;
2577 if (fence)
2578 fence->submitted = true;
2579 }
2580
2581 radv_free_sem_info(&sem_info);
2582
2583 }
2584
2585 if (fence && !fence_emitted) {
2586 fence->signalled = true;
2587 }
2588
2589 return VK_SUCCESS;
2590 }
2591
2592 VkResult radv_CreateFence(
2593 VkDevice _device,
2594 const VkFenceCreateInfo* pCreateInfo,
2595 const VkAllocationCallbacks* pAllocator,
2596 VkFence* pFence)
2597 {
2598 RADV_FROM_HANDLE(radv_device, device, _device);
2599 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2600 sizeof(*fence), 8,
2601 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2602
2603 if (!fence)
2604 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2605
2606 fence->submitted = false;
2607 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2608 fence->fence = device->ws->create_fence();
2609 if (!fence->fence) {
2610 vk_free2(&device->alloc, pAllocator, fence);
2611 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2612 }
2613
2614 *pFence = radv_fence_to_handle(fence);
2615
2616 return VK_SUCCESS;
2617 }
2618
2619 void radv_DestroyFence(
2620 VkDevice _device,
2621 VkFence _fence,
2622 const VkAllocationCallbacks* pAllocator)
2623 {
2624 RADV_FROM_HANDLE(radv_device, device, _device);
2625 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2626
2627 if (!fence)
2628 return;
2629 device->ws->destroy_fence(fence->fence);
2630 vk_free2(&device->alloc, pAllocator, fence);
2631 }
2632
2633 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2634 {
2635 uint64_t current_time;
2636 struct timespec tv;
2637
2638 clock_gettime(CLOCK_MONOTONIC, &tv);
2639 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2640
2641 timeout = MIN2(UINT64_MAX - current_time, timeout);
2642
2643 return current_time + timeout;
2644 }
2645
2646 VkResult radv_WaitForFences(
2647 VkDevice _device,
2648 uint32_t fenceCount,
2649 const VkFence* pFences,
2650 VkBool32 waitAll,
2651 uint64_t timeout)
2652 {
2653 RADV_FROM_HANDLE(radv_device, device, _device);
2654 timeout = radv_get_absolute_timeout(timeout);
2655
2656 if (!waitAll && fenceCount > 1) {
2657 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2658 }
2659
2660 for (uint32_t i = 0; i < fenceCount; ++i) {
2661 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2662 bool expired = false;
2663
2664 if (fence->signalled)
2665 continue;
2666
2667 if (!fence->submitted)
2668 return VK_TIMEOUT;
2669
2670 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2671 if (!expired)
2672 return VK_TIMEOUT;
2673
2674 fence->signalled = true;
2675 }
2676
2677 return VK_SUCCESS;
2678 }
2679
2680 VkResult radv_ResetFences(VkDevice device,
2681 uint32_t fenceCount,
2682 const VkFence *pFences)
2683 {
2684 for (unsigned i = 0; i < fenceCount; ++i) {
2685 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2686 fence->submitted = fence->signalled = false;
2687 }
2688
2689 return VK_SUCCESS;
2690 }
2691
2692 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2693 {
2694 RADV_FROM_HANDLE(radv_device, device, _device);
2695 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2696
2697 if (fence->signalled)
2698 return VK_SUCCESS;
2699 if (!fence->submitted)
2700 return VK_NOT_READY;
2701
2702 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2703 return VK_NOT_READY;
2704
2705 return VK_SUCCESS;
2706 }
2707
2708
2709 // Queue semaphore functions
2710
2711 VkResult radv_CreateSemaphore(
2712 VkDevice _device,
2713 const VkSemaphoreCreateInfo* pCreateInfo,
2714 const VkAllocationCallbacks* pAllocator,
2715 VkSemaphore* pSemaphore)
2716 {
2717 RADV_FROM_HANDLE(radv_device, device, _device);
2718 const VkExportSemaphoreCreateInfoKHR *export =
2719 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2720 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2721 export ? export->handleTypes : 0;
2722
2723 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2724 sizeof(*sem), 8,
2725 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2726 if (!sem)
2727 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2728
2729 sem->temp_syncobj = 0;
2730 /* create a syncobject if we are going to export this semaphore */
2731 if (handleTypes) {
2732 assert (device->physical_device->rad_info.has_syncobj);
2733 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2734 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2735 if (ret) {
2736 vk_free2(&device->alloc, pAllocator, sem);
2737 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2738 }
2739 sem->sem = NULL;
2740 } else {
2741 sem->sem = device->ws->create_sem(device->ws);
2742 if (!sem->sem) {
2743 vk_free2(&device->alloc, pAllocator, sem);
2744 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2745 }
2746 sem->syncobj = 0;
2747 }
2748
2749 *pSemaphore = radv_semaphore_to_handle(sem);
2750 return VK_SUCCESS;
2751 }
2752
2753 void radv_DestroySemaphore(
2754 VkDevice _device,
2755 VkSemaphore _semaphore,
2756 const VkAllocationCallbacks* pAllocator)
2757 {
2758 RADV_FROM_HANDLE(radv_device, device, _device);
2759 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2760 if (!_semaphore)
2761 return;
2762
2763 if (sem->syncobj)
2764 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2765 else
2766 device->ws->destroy_sem(sem->sem);
2767 vk_free2(&device->alloc, pAllocator, sem);
2768 }
2769
2770 VkResult radv_CreateEvent(
2771 VkDevice _device,
2772 const VkEventCreateInfo* pCreateInfo,
2773 const VkAllocationCallbacks* pAllocator,
2774 VkEvent* pEvent)
2775 {
2776 RADV_FROM_HANDLE(radv_device, device, _device);
2777 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2778 sizeof(*event), 8,
2779 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2780
2781 if (!event)
2782 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2783
2784 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2785 RADEON_DOMAIN_GTT,
2786 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
2787 if (!event->bo) {
2788 vk_free2(&device->alloc, pAllocator, event);
2789 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2790 }
2791
2792 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2793
2794 *pEvent = radv_event_to_handle(event);
2795
2796 return VK_SUCCESS;
2797 }
2798
2799 void radv_DestroyEvent(
2800 VkDevice _device,
2801 VkEvent _event,
2802 const VkAllocationCallbacks* pAllocator)
2803 {
2804 RADV_FROM_HANDLE(radv_device, device, _device);
2805 RADV_FROM_HANDLE(radv_event, event, _event);
2806
2807 if (!event)
2808 return;
2809 device->ws->buffer_destroy(event->bo);
2810 vk_free2(&device->alloc, pAllocator, event);
2811 }
2812
2813 VkResult radv_GetEventStatus(
2814 VkDevice _device,
2815 VkEvent _event)
2816 {
2817 RADV_FROM_HANDLE(radv_event, event, _event);
2818
2819 if (*event->map == 1)
2820 return VK_EVENT_SET;
2821 return VK_EVENT_RESET;
2822 }
2823
2824 VkResult radv_SetEvent(
2825 VkDevice _device,
2826 VkEvent _event)
2827 {
2828 RADV_FROM_HANDLE(radv_event, event, _event);
2829 *event->map = 1;
2830
2831 return VK_SUCCESS;
2832 }
2833
2834 VkResult radv_ResetEvent(
2835 VkDevice _device,
2836 VkEvent _event)
2837 {
2838 RADV_FROM_HANDLE(radv_event, event, _event);
2839 *event->map = 0;
2840
2841 return VK_SUCCESS;
2842 }
2843
2844 VkResult radv_CreateBuffer(
2845 VkDevice _device,
2846 const VkBufferCreateInfo* pCreateInfo,
2847 const VkAllocationCallbacks* pAllocator,
2848 VkBuffer* pBuffer)
2849 {
2850 RADV_FROM_HANDLE(radv_device, device, _device);
2851 struct radv_buffer *buffer;
2852
2853 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2854
2855 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2856 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2857 if (buffer == NULL)
2858 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2859
2860 buffer->size = pCreateInfo->size;
2861 buffer->usage = pCreateInfo->usage;
2862 buffer->bo = NULL;
2863 buffer->offset = 0;
2864 buffer->flags = pCreateInfo->flags;
2865
2866 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
2867 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
2868
2869 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2870 buffer->bo = device->ws->buffer_create(device->ws,
2871 align64(buffer->size, 4096),
2872 4096, 0, RADEON_FLAG_VIRTUAL);
2873 if (!buffer->bo) {
2874 vk_free2(&device->alloc, pAllocator, buffer);
2875 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2876 }
2877 }
2878
2879 *pBuffer = radv_buffer_to_handle(buffer);
2880
2881 return VK_SUCCESS;
2882 }
2883
2884 void radv_DestroyBuffer(
2885 VkDevice _device,
2886 VkBuffer _buffer,
2887 const VkAllocationCallbacks* pAllocator)
2888 {
2889 RADV_FROM_HANDLE(radv_device, device, _device);
2890 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2891
2892 if (!buffer)
2893 return;
2894
2895 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2896 device->ws->buffer_destroy(buffer->bo);
2897
2898 vk_free2(&device->alloc, pAllocator, buffer);
2899 }
2900
2901 static inline unsigned
2902 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2903 {
2904 if (stencil)
2905 return image->surface.u.legacy.stencil_tiling_index[level];
2906 else
2907 return image->surface.u.legacy.tiling_index[level];
2908 }
2909
2910 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2911 {
2912 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2913 }
2914
2915 static void
2916 radv_initialise_color_surface(struct radv_device *device,
2917 struct radv_color_buffer_info *cb,
2918 struct radv_image_view *iview)
2919 {
2920 const struct vk_format_description *desc;
2921 unsigned ntype, format, swap, endian;
2922 unsigned blend_clamp = 0, blend_bypass = 0;
2923 uint64_t va;
2924 const struct radeon_surf *surf = &iview->image->surface;
2925
2926 desc = vk_format_description(iview->vk_format);
2927
2928 memset(cb, 0, sizeof(*cb));
2929
2930 /* Intensity is implemented as Red, so treat it that way. */
2931 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2932
2933 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2934
2935 cb->cb_color_base = va >> 8;
2936
2937 if (device->physical_device->rad_info.chip_class >= GFX9) {
2938 struct gfx9_surf_meta_flags meta;
2939 if (iview->image->dcc_offset)
2940 meta = iview->image->surface.u.gfx9.dcc;
2941 else
2942 meta = iview->image->surface.u.gfx9.cmask;
2943
2944 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2945 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2946 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2947 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2948
2949 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2950 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2951 } else {
2952 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2953 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2954
2955 cb->cb_color_base += level_info->offset >> 8;
2956 if (level_info->mode == RADEON_SURF_MODE_2D)
2957 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2958
2959 pitch_tile_max = level_info->nblk_x / 8 - 1;
2960 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2961 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2962
2963 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2964 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2965 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2966
2967 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2968
2969 if (iview->image->fmask.size) {
2970 if (device->physical_device->rad_info.chip_class >= CIK)
2971 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2972 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2973 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2974 } else {
2975 /* This must be set for fast clear to work without FMASK. */
2976 if (device->physical_device->rad_info.chip_class >= CIK)
2977 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2978 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2979 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2980 }
2981 }
2982
2983 /* CMASK variables */
2984 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2985 va += iview->image->cmask.offset;
2986 cb->cb_color_cmask = va >> 8;
2987
2988 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2989 va += iview->image->dcc_offset;
2990 cb->cb_dcc_base = va >> 8;
2991 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2992
2993 uint32_t max_slice = radv_surface_layer_count(iview);
2994 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2995 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2996
2997 if (iview->image->info.samples > 1) {
2998 unsigned log_samples = util_logbase2(iview->image->info.samples);
2999
3000 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3001 S_028C74_NUM_FRAGMENTS(log_samples);
3002 }
3003
3004 if (iview->image->fmask.size) {
3005 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3006 cb->cb_color_fmask = va >> 8;
3007 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3008 } else {
3009 cb->cb_color_fmask = cb->cb_color_base;
3010 }
3011
3012 ntype = radv_translate_color_numformat(iview->vk_format,
3013 desc,
3014 vk_format_get_first_non_void_channel(iview->vk_format));
3015 format = radv_translate_colorformat(iview->vk_format);
3016 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3017 radv_finishme("Illegal color\n");
3018 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3019 endian = radv_colorformat_endian_swap(format);
3020
3021 /* blend clamp should be set for all NORM/SRGB types */
3022 if (ntype == V_028C70_NUMBER_UNORM ||
3023 ntype == V_028C70_NUMBER_SNORM ||
3024 ntype == V_028C70_NUMBER_SRGB)
3025 blend_clamp = 1;
3026
3027 /* set blend bypass according to docs if SINT/UINT or
3028 8/24 COLOR variants */
3029 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3030 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3031 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3032 blend_clamp = 0;
3033 blend_bypass = 1;
3034 }
3035 #if 0
3036 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3037 (format == V_028C70_COLOR_8 ||
3038 format == V_028C70_COLOR_8_8 ||
3039 format == V_028C70_COLOR_8_8_8_8))
3040 ->color_is_int8 = true;
3041 #endif
3042 cb->cb_color_info = S_028C70_FORMAT(format) |
3043 S_028C70_COMP_SWAP(swap) |
3044 S_028C70_BLEND_CLAMP(blend_clamp) |
3045 S_028C70_BLEND_BYPASS(blend_bypass) |
3046 S_028C70_SIMPLE_FLOAT(1) |
3047 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3048 ntype != V_028C70_NUMBER_SNORM &&
3049 ntype != V_028C70_NUMBER_SRGB &&
3050 format != V_028C70_COLOR_8_24 &&
3051 format != V_028C70_COLOR_24_8) |
3052 S_028C70_NUMBER_TYPE(ntype) |
3053 S_028C70_ENDIAN(endian);
3054 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3055 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3056 if (device->physical_device->rad_info.chip_class == SI) {
3057 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3058 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3059 }
3060 }
3061
3062 if (iview->image->cmask.size &&
3063 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3064 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3065
3066 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
3067 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3068
3069 if (device->physical_device->rad_info.chip_class >= VI) {
3070 unsigned max_uncompressed_block_size = 2;
3071 if (iview->image->info.samples > 1) {
3072 if (iview->image->surface.bpe == 1)
3073 max_uncompressed_block_size = 0;
3074 else if (iview->image->surface.bpe == 2)
3075 max_uncompressed_block_size = 1;
3076 }
3077
3078 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3079 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3080 }
3081
3082 /* This must be set for fast clear to work without FMASK. */
3083 if (!iview->image->fmask.size &&
3084 device->physical_device->rad_info.chip_class == SI) {
3085 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3086 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3087 }
3088
3089 if (device->physical_device->rad_info.chip_class >= GFX9) {
3090 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3091 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3092
3093 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3094 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3095 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3096 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3097 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3098 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3099 }
3100 }
3101
3102 static void
3103 radv_initialise_ds_surface(struct radv_device *device,
3104 struct radv_ds_buffer_info *ds,
3105 struct radv_image_view *iview)
3106 {
3107 unsigned level = iview->base_mip;
3108 unsigned format, stencil_format;
3109 uint64_t va, s_offs, z_offs;
3110 bool stencil_only = false;
3111 memset(ds, 0, sizeof(*ds));
3112 switch (iview->image->vk_format) {
3113 case VK_FORMAT_D24_UNORM_S8_UINT:
3114 case VK_FORMAT_X8_D24_UNORM_PACK32:
3115 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3116 ds->offset_scale = 2.0f;
3117 break;
3118 case VK_FORMAT_D16_UNORM:
3119 case VK_FORMAT_D16_UNORM_S8_UINT:
3120 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3121 ds->offset_scale = 4.0f;
3122 break;
3123 case VK_FORMAT_D32_SFLOAT:
3124 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3125 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3126 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3127 ds->offset_scale = 1.0f;
3128 break;
3129 case VK_FORMAT_S8_UINT:
3130 stencil_only = true;
3131 break;
3132 default:
3133 break;
3134 }
3135
3136 format = radv_translate_dbformat(iview->image->vk_format);
3137 stencil_format = iview->image->surface.has_stencil ?
3138 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3139
3140 uint32_t max_slice = radv_surface_layer_count(iview);
3141 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3142 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3143
3144 ds->db_htile_data_base = 0;
3145 ds->db_htile_surface = 0;
3146
3147 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3148 s_offs = z_offs = va;
3149
3150 if (device->physical_device->rad_info.chip_class >= GFX9) {
3151 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3152 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3153
3154 ds->db_z_info = S_028038_FORMAT(format) |
3155 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3156 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3157 S_028038_MAXMIP(iview->image->info.levels - 1);
3158 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3159 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3160
3161 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3162 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3163 ds->db_depth_view |= S_028008_MIPID(level);
3164
3165 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3166 S_02801C_Y_MAX(iview->image->info.height - 1);
3167
3168 if (radv_htile_enabled(iview->image, level)) {
3169 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3170
3171 if (iview->image->tc_compatible_htile) {
3172 unsigned max_zplanes = 4;
3173
3174 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3175 iview->image->info.samples > 1)
3176 max_zplanes = 2;
3177
3178 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3179 S_028038_ITERATE_FLUSH(1);
3180 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3181 }
3182
3183 if (!iview->image->surface.has_stencil)
3184 /* Use all of the htile_buffer for depth if there's no stencil. */
3185 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3186 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3187 iview->image->htile_offset;
3188 ds->db_htile_data_base = va >> 8;
3189 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3190 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3191 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3192 }
3193 } else {
3194 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3195
3196 if (stencil_only)
3197 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3198
3199 z_offs += iview->image->surface.u.legacy.level[level].offset;
3200 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3201
3202 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3203 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3204 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3205
3206 if (iview->image->info.samples > 1)
3207 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3208
3209 if (device->physical_device->rad_info.chip_class >= CIK) {
3210 struct radeon_info *info = &device->physical_device->rad_info;
3211 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3212 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3213 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3214 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3215 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3216 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3217
3218 if (stencil_only)
3219 tile_mode = stencil_tile_mode;
3220
3221 ds->db_depth_info |=
3222 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3223 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3224 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3225 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3226 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3227 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3228 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3229 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3230 } else {
3231 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3232 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3233 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3234 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3235 if (stencil_only)
3236 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3237 }
3238
3239 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3240 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3241 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3242
3243 if (radv_htile_enabled(iview->image, level)) {
3244 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3245
3246 if (!iview->image->surface.has_stencil &&
3247 !iview->image->tc_compatible_htile)
3248 /* Use all of the htile_buffer for depth if there's no stencil. */
3249 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3250
3251 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3252 iview->image->htile_offset;
3253 ds->db_htile_data_base = va >> 8;
3254 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3255
3256 if (iview->image->tc_compatible_htile) {
3257 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3258
3259 if (iview->image->info.samples <= 1)
3260 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3261 else if (iview->image->info.samples <= 4)
3262 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3263 else
3264 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3265 }
3266 }
3267 }
3268
3269 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3270 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3271 }
3272
3273 VkResult radv_CreateFramebuffer(
3274 VkDevice _device,
3275 const VkFramebufferCreateInfo* pCreateInfo,
3276 const VkAllocationCallbacks* pAllocator,
3277 VkFramebuffer* pFramebuffer)
3278 {
3279 RADV_FROM_HANDLE(radv_device, device, _device);
3280 struct radv_framebuffer *framebuffer;
3281
3282 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3283
3284 size_t size = sizeof(*framebuffer) +
3285 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3286 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3287 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3288 if (framebuffer == NULL)
3289 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3290
3291 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3292 framebuffer->width = pCreateInfo->width;
3293 framebuffer->height = pCreateInfo->height;
3294 framebuffer->layers = pCreateInfo->layers;
3295 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3296 VkImageView _iview = pCreateInfo->pAttachments[i];
3297 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3298 framebuffer->attachments[i].attachment = iview;
3299 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3300 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3301 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3302 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3303 }
3304 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3305 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3306 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3307 }
3308
3309 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3310 return VK_SUCCESS;
3311 }
3312
3313 void radv_DestroyFramebuffer(
3314 VkDevice _device,
3315 VkFramebuffer _fb,
3316 const VkAllocationCallbacks* pAllocator)
3317 {
3318 RADV_FROM_HANDLE(radv_device, device, _device);
3319 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3320
3321 if (!fb)
3322 return;
3323 vk_free2(&device->alloc, pAllocator, fb);
3324 }
3325
3326 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3327 {
3328 switch (address_mode) {
3329 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3330 return V_008F30_SQ_TEX_WRAP;
3331 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3332 return V_008F30_SQ_TEX_MIRROR;
3333 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3334 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3335 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3336 return V_008F30_SQ_TEX_CLAMP_BORDER;
3337 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3338 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3339 default:
3340 unreachable("illegal tex wrap mode");
3341 break;
3342 }
3343 }
3344
3345 static unsigned
3346 radv_tex_compare(VkCompareOp op)
3347 {
3348 switch (op) {
3349 case VK_COMPARE_OP_NEVER:
3350 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3351 case VK_COMPARE_OP_LESS:
3352 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3353 case VK_COMPARE_OP_EQUAL:
3354 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3355 case VK_COMPARE_OP_LESS_OR_EQUAL:
3356 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3357 case VK_COMPARE_OP_GREATER:
3358 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3359 case VK_COMPARE_OP_NOT_EQUAL:
3360 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3361 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3362 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3363 case VK_COMPARE_OP_ALWAYS:
3364 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3365 default:
3366 unreachable("illegal compare mode");
3367 break;
3368 }
3369 }
3370
3371 static unsigned
3372 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3373 {
3374 switch (filter) {
3375 case VK_FILTER_NEAREST:
3376 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3377 V_008F38_SQ_TEX_XY_FILTER_POINT);
3378 case VK_FILTER_LINEAR:
3379 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3380 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3381 case VK_FILTER_CUBIC_IMG:
3382 default:
3383 fprintf(stderr, "illegal texture filter");
3384 return 0;
3385 }
3386 }
3387
3388 static unsigned
3389 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3390 {
3391 switch (mode) {
3392 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3393 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3394 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3395 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3396 default:
3397 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3398 }
3399 }
3400
3401 static unsigned
3402 radv_tex_bordercolor(VkBorderColor bcolor)
3403 {
3404 switch (bcolor) {
3405 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3406 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3407 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3408 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3409 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3410 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3411 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3412 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3413 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3414 default:
3415 break;
3416 }
3417 return 0;
3418 }
3419
3420 static unsigned
3421 radv_tex_aniso_filter(unsigned filter)
3422 {
3423 if (filter < 2)
3424 return 0;
3425 if (filter < 4)
3426 return 1;
3427 if (filter < 8)
3428 return 2;
3429 if (filter < 16)
3430 return 3;
3431 return 4;
3432 }
3433
3434 static void
3435 radv_init_sampler(struct radv_device *device,
3436 struct radv_sampler *sampler,
3437 const VkSamplerCreateInfo *pCreateInfo)
3438 {
3439 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3440 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3441 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3442 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3443
3444 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3445 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3446 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3447 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3448 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3449 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3450 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3451 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3452 S_008F30_DISABLE_CUBE_WRAP(0) |
3453 S_008F30_COMPAT_MODE(is_vi));
3454 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3455 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3456 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3457 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3458 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3459 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3460 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3461 S_008F38_MIP_POINT_PRECLAMP(0) |
3462 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
3463 S_008F38_FILTER_PREC_FIX(1) |
3464 S_008F38_ANISO_OVERRIDE(is_vi));
3465 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3466 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3467 }
3468
3469 VkResult radv_CreateSampler(
3470 VkDevice _device,
3471 const VkSamplerCreateInfo* pCreateInfo,
3472 const VkAllocationCallbacks* pAllocator,
3473 VkSampler* pSampler)
3474 {
3475 RADV_FROM_HANDLE(radv_device, device, _device);
3476 struct radv_sampler *sampler;
3477
3478 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3479
3480 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3481 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3482 if (!sampler)
3483 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3484
3485 radv_init_sampler(device, sampler, pCreateInfo);
3486 *pSampler = radv_sampler_to_handle(sampler);
3487
3488 return VK_SUCCESS;
3489 }
3490
3491 void radv_DestroySampler(
3492 VkDevice _device,
3493 VkSampler _sampler,
3494 const VkAllocationCallbacks* pAllocator)
3495 {
3496 RADV_FROM_HANDLE(radv_device, device, _device);
3497 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3498
3499 if (!sampler)
3500 return;
3501 vk_free2(&device->alloc, pAllocator, sampler);
3502 }
3503
3504 /* vk_icd.h does not declare this function, so we declare it here to
3505 * suppress Wmissing-prototypes.
3506 */
3507 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3508 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3509
3510 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3511 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3512 {
3513 /* For the full details on loader interface versioning, see
3514 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3515 * What follows is a condensed summary, to help you navigate the large and
3516 * confusing official doc.
3517 *
3518 * - Loader interface v0 is incompatible with later versions. We don't
3519 * support it.
3520 *
3521 * - In loader interface v1:
3522 * - The first ICD entrypoint called by the loader is
3523 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3524 * entrypoint.
3525 * - The ICD must statically expose no other Vulkan symbol unless it is
3526 * linked with -Bsymbolic.
3527 * - Each dispatchable Vulkan handle created by the ICD must be
3528 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3529 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3530 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3531 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3532 * such loader-managed surfaces.
3533 *
3534 * - Loader interface v2 differs from v1 in:
3535 * - The first ICD entrypoint called by the loader is
3536 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3537 * statically expose this entrypoint.
3538 *
3539 * - Loader interface v3 differs from v2 in:
3540 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3541 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3542 * because the loader no longer does so.
3543 */
3544 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3545 return VK_SUCCESS;
3546 }
3547
3548 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3549 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3550 int *pFD)
3551 {
3552 RADV_FROM_HANDLE(radv_device, device, _device);
3553 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3554
3555 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3556
3557 /* At the moment, we support only the below handle types. */
3558 assert(pGetFdInfo->handleType ==
3559 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3560 pGetFdInfo->handleType ==
3561 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3562
3563 bool ret = radv_get_memory_fd(device, memory, pFD);
3564 if (ret == false)
3565 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
3566 return VK_SUCCESS;
3567 }
3568
3569 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3570 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3571 int fd,
3572 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3573 {
3574 switch (handleType) {
3575 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
3576 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
3577 return VK_SUCCESS;
3578
3579 default:
3580 /* The valid usage section for this function says:
3581 *
3582 * "handleType must not be one of the handle types defined as
3583 * opaque."
3584 *
3585 * So opaque handle types fall into the default "unsupported" case.
3586 */
3587 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3588 }
3589 }
3590
3591 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3592 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3593 {
3594 RADV_FROM_HANDLE(radv_device, device, _device);
3595 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3596 uint32_t syncobj_handle = 0;
3597 uint32_t *syncobj_dst = NULL;
3598 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3599
3600 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3601 if (ret != 0)
3602 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3603
3604 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3605 syncobj_dst = &sem->temp_syncobj;
3606 } else {
3607 syncobj_dst = &sem->syncobj;
3608 }
3609
3610 if (*syncobj_dst)
3611 device->ws->destroy_syncobj(device->ws, *syncobj_dst);
3612
3613 *syncobj_dst = syncobj_handle;
3614 close(pImportSemaphoreFdInfo->fd);
3615 return VK_SUCCESS;
3616 }
3617
3618 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3619 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3620 int *pFd)
3621 {
3622 RADV_FROM_HANDLE(radv_device, device, _device);
3623 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3624 int ret;
3625 uint32_t syncobj_handle;
3626
3627 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3628 if (sem->temp_syncobj)
3629 syncobj_handle = sem->temp_syncobj;
3630 else
3631 syncobj_handle = sem->syncobj;
3632 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3633 if (ret)
3634 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3635 return VK_SUCCESS;
3636 }
3637
3638 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3639 VkPhysicalDevice physicalDevice,
3640 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3641 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3642 {
3643 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3644 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3645 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3646 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3647 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3648 } else {
3649 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3650 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3651 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3652 }
3653 }