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radv: add missing support for protected memory properties
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void *));
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 } else if (!strcmp(name, "DOOM_VFR")) {
484 /* Work around a Doom VFR game bug */
485 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
486 }
487 }
488
489 static int radv_get_instance_extension_index(const char *name)
490 {
491 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
492 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
493 return i;
494 }
495 return -1;
496 }
497
498
499 VkResult radv_CreateInstance(
500 const VkInstanceCreateInfo* pCreateInfo,
501 const VkAllocationCallbacks* pAllocator,
502 VkInstance* pInstance)
503 {
504 struct radv_instance *instance;
505 VkResult result;
506
507 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
508
509 uint32_t client_version;
510 if (pCreateInfo->pApplicationInfo &&
511 pCreateInfo->pApplicationInfo->apiVersion != 0) {
512 client_version = pCreateInfo->pApplicationInfo->apiVersion;
513 } else {
514 radv_EnumerateInstanceVersion(&client_version);
515 }
516
517 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
518 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
519 if (!instance)
520 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
521
522 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
523
524 if (pAllocator)
525 instance->alloc = *pAllocator;
526 else
527 instance->alloc = default_alloc;
528
529 instance->apiVersion = client_version;
530 instance->physicalDeviceCount = -1;
531
532 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
533 radv_debug_options);
534
535 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
536 radv_perftest_options);
537
538
539 if (instance->debug_flags & RADV_DEBUG_STARTUP)
540 radv_logi("Created an instance");
541
542 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
543 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
544 int index = radv_get_instance_extension_index(ext_name);
545
546 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
547 vk_free2(&default_alloc, pAllocator, instance);
548 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
549 }
550
551 instance->enabled_extensions.extensions[index] = true;
552 }
553
554 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
555 if (result != VK_SUCCESS) {
556 vk_free2(&default_alloc, pAllocator, instance);
557 return vk_error(instance, result);
558 }
559
560 _mesa_locale_init();
561
562 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
563
564 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
565
566 *pInstance = radv_instance_to_handle(instance);
567
568 return VK_SUCCESS;
569 }
570
571 void radv_DestroyInstance(
572 VkInstance _instance,
573 const VkAllocationCallbacks* pAllocator)
574 {
575 RADV_FROM_HANDLE(radv_instance, instance, _instance);
576
577 if (!instance)
578 return;
579
580 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
581 radv_physical_device_finish(instance->physicalDevices + i);
582 }
583
584 VG(VALGRIND_DESTROY_MEMPOOL(instance));
585
586 _mesa_locale_fini();
587
588 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
589
590 vk_free(&instance->alloc, instance);
591 }
592
593 static VkResult
594 radv_enumerate_devices(struct radv_instance *instance)
595 {
596 /* TODO: Check for more devices ? */
597 drmDevicePtr devices[8];
598 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
599 int max_devices;
600
601 instance->physicalDeviceCount = 0;
602
603 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
604
605 if (instance->debug_flags & RADV_DEBUG_STARTUP)
606 radv_logi("Found %d drm nodes", max_devices);
607
608 if (max_devices < 1)
609 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
610
611 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
612 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
613 devices[i]->bustype == DRM_BUS_PCI &&
614 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
615
616 result = radv_physical_device_init(instance->physicalDevices +
617 instance->physicalDeviceCount,
618 instance,
619 devices[i]);
620 if (result == VK_SUCCESS)
621 ++instance->physicalDeviceCount;
622 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
623 break;
624 }
625 }
626 drmFreeDevices(devices, max_devices);
627
628 return result;
629 }
630
631 VkResult radv_EnumeratePhysicalDevices(
632 VkInstance _instance,
633 uint32_t* pPhysicalDeviceCount,
634 VkPhysicalDevice* pPhysicalDevices)
635 {
636 RADV_FROM_HANDLE(radv_instance, instance, _instance);
637 VkResult result;
638
639 if (instance->physicalDeviceCount < 0) {
640 result = radv_enumerate_devices(instance);
641 if (result != VK_SUCCESS &&
642 result != VK_ERROR_INCOMPATIBLE_DRIVER)
643 return result;
644 }
645
646 if (!pPhysicalDevices) {
647 *pPhysicalDeviceCount = instance->physicalDeviceCount;
648 } else {
649 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
650 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
651 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
652 }
653
654 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
655 : VK_SUCCESS;
656 }
657
658 VkResult radv_EnumeratePhysicalDeviceGroups(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceGroupCount,
661 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDeviceGroupProperties) {
674 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
678 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
679 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
680 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
681 }
682 }
683 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
684 : VK_SUCCESS;
685 }
686
687 void radv_GetPhysicalDeviceFeatures(
688 VkPhysicalDevice physicalDevice,
689 VkPhysicalDeviceFeatures* pFeatures)
690 {
691 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
692 memset(pFeatures, 0, sizeof(*pFeatures));
693
694 *pFeatures = (VkPhysicalDeviceFeatures) {
695 .robustBufferAccess = true,
696 .fullDrawIndexUint32 = true,
697 .imageCubeArray = true,
698 .independentBlend = true,
699 .geometryShader = true,
700 .tessellationShader = true,
701 .sampleRateShading = true,
702 .dualSrcBlend = true,
703 .logicOp = true,
704 .multiDrawIndirect = true,
705 .drawIndirectFirstInstance = true,
706 .depthClamp = true,
707 .depthBiasClamp = true,
708 .fillModeNonSolid = true,
709 .depthBounds = true,
710 .wideLines = true,
711 .largePoints = true,
712 .alphaToOne = true,
713 .multiViewport = true,
714 .samplerAnisotropy = true,
715 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
716 pdevice->rad_info.family == CHIP_STONEY,
717 .textureCompressionASTC_LDR = false,
718 .textureCompressionBC = true,
719 .occlusionQueryPrecise = true,
720 .pipelineStatisticsQuery = true,
721 .vertexPipelineStoresAndAtomics = true,
722 .fragmentStoresAndAtomics = true,
723 .shaderTessellationAndGeometryPointSize = true,
724 .shaderImageGatherExtended = true,
725 .shaderStorageImageExtendedFormats = true,
726 .shaderStorageImageMultisample = false,
727 .shaderUniformBufferArrayDynamicIndexing = true,
728 .shaderSampledImageArrayDynamicIndexing = true,
729 .shaderStorageBufferArrayDynamicIndexing = true,
730 .shaderStorageImageArrayDynamicIndexing = true,
731 .shaderStorageImageReadWithoutFormat = true,
732 .shaderStorageImageWriteWithoutFormat = true,
733 .shaderClipDistance = true,
734 .shaderCullDistance = true,
735 .shaderFloat64 = true,
736 .shaderInt64 = true,
737 .shaderInt16 = false,
738 .sparseBinding = true,
739 .variableMultisampleRate = true,
740 .inheritedQueries = true,
741 };
742 }
743
744 void radv_GetPhysicalDeviceFeatures2(
745 VkPhysicalDevice physicalDevice,
746 VkPhysicalDeviceFeatures2KHR *pFeatures)
747 {
748 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
749 vk_foreach_struct(ext, pFeatures->pNext) {
750 switch (ext->sType) {
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
752 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
753 features->variablePointersStorageBuffer = true;
754 features->variablePointers = false;
755 break;
756 }
757 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
758 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
759 features->multiview = true;
760 features->multiviewGeometryShader = true;
761 features->multiviewTessellationShader = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
765 VkPhysicalDeviceShaderDrawParameterFeatures *features =
766 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
767 features->shaderDrawParameters = true;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
771 VkPhysicalDeviceProtectedMemoryFeatures *features =
772 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
773 features->protectedMemory = false;
774 break;
775 }
776 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
777 VkPhysicalDevice16BitStorageFeatures *features =
778 (VkPhysicalDevice16BitStorageFeatures*)ext;
779 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
780 features->storageBuffer16BitAccess = enabled;
781 features->uniformAndStorageBuffer16BitAccess = enabled;
782 features->storagePushConstant16 = enabled;
783 features->storageInputOutput16 = enabled;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
787 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
788 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
789 features->samplerYcbcrConversion = false;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
793 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
794 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
795 features->shaderInputAttachmentArrayDynamicIndexing = true;
796 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
797 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
798 features->shaderUniformBufferArrayNonUniformIndexing = false;
799 features->shaderSampledImageArrayNonUniformIndexing = false;
800 features->shaderStorageBufferArrayNonUniformIndexing = false;
801 features->shaderStorageImageArrayNonUniformIndexing = false;
802 features->shaderInputAttachmentArrayNonUniformIndexing = false;
803 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
804 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
805 features->descriptorBindingUniformBufferUpdateAfterBind = true;
806 features->descriptorBindingSampledImageUpdateAfterBind = true;
807 features->descriptorBindingStorageImageUpdateAfterBind = true;
808 features->descriptorBindingStorageBufferUpdateAfterBind = true;
809 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
810 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
811 features->descriptorBindingUpdateUnusedWhilePending = true;
812 features->descriptorBindingPartiallyBound = true;
813 features->descriptorBindingVariableDescriptorCount = true;
814 features->runtimeDescriptorArray = true;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
818 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
819 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
820 features->conditionalRendering = true;
821 features->inheritedConditionalRendering = false;
822 break;
823 }
824 default:
825 break;
826 }
827 }
828 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
829 }
830
831 void radv_GetPhysicalDeviceProperties(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceProperties* pProperties)
834 {
835 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
836 VkSampleCountFlags sample_counts = 0xf;
837
838 /* make sure that the entire descriptor set is addressable with a signed
839 * 32-bit int. So the sum of all limits scaled by descriptor size has to
840 * be at most 2 GiB. the combined image & samples object count as one of
841 * both. This limit is for the pipeline layout, not for the set layout, but
842 * there is no set limit, so we just set a pipeline limit. I don't think
843 * any app is going to hit this soon. */
844 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
845 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
846 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
847 32 /* sampler, largest when combined with image */ +
848 64 /* sampled image */ +
849 64 /* storage image */);
850
851 VkPhysicalDeviceLimits limits = {
852 .maxImageDimension1D = (1 << 14),
853 .maxImageDimension2D = (1 << 14),
854 .maxImageDimension3D = (1 << 11),
855 .maxImageDimensionCube = (1 << 14),
856 .maxImageArrayLayers = (1 << 11),
857 .maxTexelBufferElements = 128 * 1024 * 1024,
858 .maxUniformBufferRange = UINT32_MAX,
859 .maxStorageBufferRange = UINT32_MAX,
860 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
861 .maxMemoryAllocationCount = UINT32_MAX,
862 .maxSamplerAllocationCount = 64 * 1024,
863 .bufferImageGranularity = 64, /* A cache line */
864 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
865 .maxBoundDescriptorSets = MAX_SETS,
866 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
867 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
868 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
869 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
870 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
871 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
872 .maxPerStageResources = max_descriptor_set_size,
873 .maxDescriptorSetSamplers = max_descriptor_set_size,
874 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
875 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
876 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
877 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
878 .maxDescriptorSetSampledImages = max_descriptor_set_size,
879 .maxDescriptorSetStorageImages = max_descriptor_set_size,
880 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
881 .maxVertexInputAttributes = 32,
882 .maxVertexInputBindings = 32,
883 .maxVertexInputAttributeOffset = 2047,
884 .maxVertexInputBindingStride = 2048,
885 .maxVertexOutputComponents = 128,
886 .maxTessellationGenerationLevel = 64,
887 .maxTessellationPatchSize = 32,
888 .maxTessellationControlPerVertexInputComponents = 128,
889 .maxTessellationControlPerVertexOutputComponents = 128,
890 .maxTessellationControlPerPatchOutputComponents = 120,
891 .maxTessellationControlTotalOutputComponents = 4096,
892 .maxTessellationEvaluationInputComponents = 128,
893 .maxTessellationEvaluationOutputComponents = 128,
894 .maxGeometryShaderInvocations = 127,
895 .maxGeometryInputComponents = 64,
896 .maxGeometryOutputComponents = 128,
897 .maxGeometryOutputVertices = 256,
898 .maxGeometryTotalOutputComponents = 1024,
899 .maxFragmentInputComponents = 128,
900 .maxFragmentOutputAttachments = 8,
901 .maxFragmentDualSrcAttachments = 1,
902 .maxFragmentCombinedOutputResources = 8,
903 .maxComputeSharedMemorySize = 32768,
904 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
905 .maxComputeWorkGroupInvocations = 2048,
906 .maxComputeWorkGroupSize = {
907 2048,
908 2048,
909 2048
910 },
911 .subPixelPrecisionBits = 4 /* FIXME */,
912 .subTexelPrecisionBits = 4 /* FIXME */,
913 .mipmapPrecisionBits = 4 /* FIXME */,
914 .maxDrawIndexedIndexValue = UINT32_MAX,
915 .maxDrawIndirectCount = UINT32_MAX,
916 .maxSamplerLodBias = 16,
917 .maxSamplerAnisotropy = 16,
918 .maxViewports = MAX_VIEWPORTS,
919 .maxViewportDimensions = { (1 << 14), (1 << 14) },
920 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
921 .viewportSubPixelBits = 8,
922 .minMemoryMapAlignment = 4096, /* A page */
923 .minTexelBufferOffsetAlignment = 1,
924 .minUniformBufferOffsetAlignment = 4,
925 .minStorageBufferOffsetAlignment = 4,
926 .minTexelOffset = -32,
927 .maxTexelOffset = 31,
928 .minTexelGatherOffset = -32,
929 .maxTexelGatherOffset = 31,
930 .minInterpolationOffset = -2,
931 .maxInterpolationOffset = 2,
932 .subPixelInterpolationOffsetBits = 8,
933 .maxFramebufferWidth = (1 << 14),
934 .maxFramebufferHeight = (1 << 14),
935 .maxFramebufferLayers = (1 << 10),
936 .framebufferColorSampleCounts = sample_counts,
937 .framebufferDepthSampleCounts = sample_counts,
938 .framebufferStencilSampleCounts = sample_counts,
939 .framebufferNoAttachmentsSampleCounts = sample_counts,
940 .maxColorAttachments = MAX_RTS,
941 .sampledImageColorSampleCounts = sample_counts,
942 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
943 .sampledImageDepthSampleCounts = sample_counts,
944 .sampledImageStencilSampleCounts = sample_counts,
945 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
946 .maxSampleMaskWords = 1,
947 .timestampComputeAndGraphics = true,
948 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
949 .maxClipDistances = 8,
950 .maxCullDistances = 8,
951 .maxCombinedClipAndCullDistances = 8,
952 .discreteQueuePriorities = 1,
953 .pointSizeRange = { 0.125, 255.875 },
954 .lineWidthRange = { 0.0, 7.9921875 },
955 .pointSizeGranularity = (1.0 / 8.0),
956 .lineWidthGranularity = (1.0 / 128.0),
957 .strictLines = false, /* FINISHME */
958 .standardSampleLocations = true,
959 .optimalBufferCopyOffsetAlignment = 128,
960 .optimalBufferCopyRowPitchAlignment = 128,
961 .nonCoherentAtomSize = 64,
962 };
963
964 *pProperties = (VkPhysicalDeviceProperties) {
965 .apiVersion = radv_physical_device_api_version(pdevice),
966 .driverVersion = vk_get_driver_version(),
967 .vendorID = ATI_VENDOR_ID,
968 .deviceID = pdevice->rad_info.pci_id,
969 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
970 .limits = limits,
971 .sparseProperties = {0},
972 };
973
974 strcpy(pProperties->deviceName, pdevice->name);
975 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
976 }
977
978 void radv_GetPhysicalDeviceProperties2(
979 VkPhysicalDevice physicalDevice,
980 VkPhysicalDeviceProperties2KHR *pProperties)
981 {
982 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
983 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
984
985 vk_foreach_struct(ext, pProperties->pNext) {
986 switch (ext->sType) {
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
988 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
989 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
990 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
994 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
995 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
996 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
997 properties->deviceLUIDValid = false;
998 break;
999 }
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1001 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1002 properties->maxMultiviewViewCount = MAX_VIEWS;
1003 properties->maxMultiviewInstanceIndex = INT_MAX;
1004 break;
1005 }
1006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1007 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1008 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1009 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1010 break;
1011 }
1012 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1013 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1014 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1015 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1016 break;
1017 }
1018 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1019 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1020 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1021 properties->minImportedHostPointerAlignment = 4096;
1022 break;
1023 }
1024 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1025 VkPhysicalDeviceSubgroupProperties *properties =
1026 (VkPhysicalDeviceSubgroupProperties*)ext;
1027 properties->subgroupSize = 64;
1028 properties->supportedStages = VK_SHADER_STAGE_ALL;
1029 properties->supportedOperations =
1030 VK_SUBGROUP_FEATURE_BASIC_BIT |
1031 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1032 VK_SUBGROUP_FEATURE_QUAD_BIT |
1033 VK_SUBGROUP_FEATURE_VOTE_BIT;
1034 if (pdevice->rad_info.chip_class >= VI) {
1035 properties->supportedOperations |=
1036 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1037 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1038 }
1039 properties->quadOperationsInAllStages = true;
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1043 VkPhysicalDeviceMaintenance3Properties *properties =
1044 (VkPhysicalDeviceMaintenance3Properties*)ext;
1045 /* Make sure everything is addressable by a signed 32-bit int, and
1046 * our largest descriptors are 96 bytes. */
1047 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1048 /* Our buffer size fields allow only this much */
1049 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1050 break;
1051 }
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1053 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1054 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1055 /* GFX6-8 only support single channel min/max filter. */
1056 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1057 properties->filterMinmaxSingleComponentFormats = true;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1061 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1062 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1063
1064 /* Shader engines. */
1065 properties->shaderEngineCount =
1066 pdevice->rad_info.max_se;
1067 properties->shaderArraysPerEngineCount =
1068 pdevice->rad_info.max_sh_per_se;
1069 properties->computeUnitsPerShaderArray =
1070 pdevice->rad_info.num_good_compute_units /
1071 (pdevice->rad_info.max_se *
1072 pdevice->rad_info.max_sh_per_se);
1073 properties->simdPerComputeUnit = 4;
1074 properties->wavefrontsPerSimd =
1075 pdevice->rad_info.family == CHIP_TONGA ||
1076 pdevice->rad_info.family == CHIP_ICELAND ||
1077 pdevice->rad_info.family == CHIP_POLARIS10 ||
1078 pdevice->rad_info.family == CHIP_POLARIS11 ||
1079 pdevice->rad_info.family == CHIP_POLARIS12 ||
1080 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1081 properties->wavefrontSize = 64;
1082
1083 /* SGPR. */
1084 properties->sgprsPerSimd =
1085 radv_get_num_physical_sgprs(pdevice);
1086 properties->minSgprAllocation =
1087 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1088 properties->maxSgprAllocation =
1089 pdevice->rad_info.family == CHIP_TONGA ||
1090 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1091 properties->sgprAllocationGranularity =
1092 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1093
1094 /* VGPR. */
1095 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1096 properties->minVgprAllocation = 4;
1097 properties->maxVgprAllocation = 256;
1098 properties->vgprAllocationGranularity = 4;
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1102 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1103 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1104 properties->maxVertexAttribDivisor = UINT32_MAX;
1105 break;
1106 }
1107 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1108 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1109 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1110 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1111 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1112 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1113 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1114 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1115 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1116 properties->robustBufferAccessUpdateAfterBind = false;
1117 properties->quadDivergentImplicitLod = false;
1118
1119 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1120 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1121 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1122 32 /* sampler, largest when combined with image */ +
1123 64 /* sampled image */ +
1124 64 /* storage image */);
1125 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1126 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1127 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1128 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1129 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1130 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1131 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1132 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1133 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1134 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1135 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1136 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1137 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1138 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1139 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1143 VkPhysicalDeviceProtectedMemoryProperties *properties =
1144 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1145 properties->protectedNoFault = false;
1146 break;
1147 }
1148 default:
1149 break;
1150 }
1151 }
1152 }
1153
1154 static void radv_get_physical_device_queue_family_properties(
1155 struct radv_physical_device* pdevice,
1156 uint32_t* pCount,
1157 VkQueueFamilyProperties** pQueueFamilyProperties)
1158 {
1159 int num_queue_families = 1;
1160 int idx;
1161 if (pdevice->rad_info.num_compute_rings > 0 &&
1162 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1163 num_queue_families++;
1164
1165 if (pQueueFamilyProperties == NULL) {
1166 *pCount = num_queue_families;
1167 return;
1168 }
1169
1170 if (!*pCount)
1171 return;
1172
1173 idx = 0;
1174 if (*pCount >= 1) {
1175 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1176 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1177 VK_QUEUE_COMPUTE_BIT |
1178 VK_QUEUE_TRANSFER_BIT |
1179 VK_QUEUE_SPARSE_BINDING_BIT,
1180 .queueCount = 1,
1181 .timestampValidBits = 64,
1182 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1183 };
1184 idx++;
1185 }
1186
1187 if (pdevice->rad_info.num_compute_rings > 0 &&
1188 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1189 if (*pCount > idx) {
1190 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1191 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1192 VK_QUEUE_TRANSFER_BIT |
1193 VK_QUEUE_SPARSE_BINDING_BIT,
1194 .queueCount = pdevice->rad_info.num_compute_rings,
1195 .timestampValidBits = 64,
1196 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1197 };
1198 idx++;
1199 }
1200 }
1201 *pCount = idx;
1202 }
1203
1204 void radv_GetPhysicalDeviceQueueFamilyProperties(
1205 VkPhysicalDevice physicalDevice,
1206 uint32_t* pCount,
1207 VkQueueFamilyProperties* pQueueFamilyProperties)
1208 {
1209 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1210 if (!pQueueFamilyProperties) {
1211 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1212 return;
1213 }
1214 VkQueueFamilyProperties *properties[] = {
1215 pQueueFamilyProperties + 0,
1216 pQueueFamilyProperties + 1,
1217 pQueueFamilyProperties + 2,
1218 };
1219 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1220 assert(*pCount <= 3);
1221 }
1222
1223 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1224 VkPhysicalDevice physicalDevice,
1225 uint32_t* pCount,
1226 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1227 {
1228 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1229 if (!pQueueFamilyProperties) {
1230 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1231 return;
1232 }
1233 VkQueueFamilyProperties *properties[] = {
1234 &pQueueFamilyProperties[0].queueFamilyProperties,
1235 &pQueueFamilyProperties[1].queueFamilyProperties,
1236 &pQueueFamilyProperties[2].queueFamilyProperties,
1237 };
1238 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1239 assert(*pCount <= 3);
1240 }
1241
1242 void radv_GetPhysicalDeviceMemoryProperties(
1243 VkPhysicalDevice physicalDevice,
1244 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1245 {
1246 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1247
1248 *pMemoryProperties = physical_device->memory_properties;
1249 }
1250
1251 void radv_GetPhysicalDeviceMemoryProperties2(
1252 VkPhysicalDevice physicalDevice,
1253 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1254 {
1255 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1256 &pMemoryProperties->memoryProperties);
1257 }
1258
1259 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1260 VkDevice _device,
1261 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1262 const void *pHostPointer,
1263 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1264 {
1265 RADV_FROM_HANDLE(radv_device, device, _device);
1266
1267 switch (handleType)
1268 {
1269 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1270 const struct radv_physical_device *physical_device = device->physical_device;
1271 uint32_t memoryTypeBits = 0;
1272 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1273 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1274 memoryTypeBits = (1 << i);
1275 break;
1276 }
1277 }
1278 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1279 return VK_SUCCESS;
1280 }
1281 default:
1282 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1283 }
1284 }
1285
1286 static enum radeon_ctx_priority
1287 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1288 {
1289 /* Default to MEDIUM when a specific global priority isn't requested */
1290 if (!pObj)
1291 return RADEON_CTX_PRIORITY_MEDIUM;
1292
1293 switch(pObj->globalPriority) {
1294 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1295 return RADEON_CTX_PRIORITY_REALTIME;
1296 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1297 return RADEON_CTX_PRIORITY_HIGH;
1298 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1299 return RADEON_CTX_PRIORITY_MEDIUM;
1300 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1301 return RADEON_CTX_PRIORITY_LOW;
1302 default:
1303 unreachable("Illegal global priority value");
1304 return RADEON_CTX_PRIORITY_INVALID;
1305 }
1306 }
1307
1308 static int
1309 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1310 uint32_t queue_family_index, int idx,
1311 VkDeviceQueueCreateFlags flags,
1312 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1313 {
1314 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1315 queue->device = device;
1316 queue->queue_family_index = queue_family_index;
1317 queue->queue_idx = idx;
1318 queue->priority = radv_get_queue_global_priority(global_priority);
1319 queue->flags = flags;
1320
1321 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1322 if (!queue->hw_ctx)
1323 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1324
1325 return VK_SUCCESS;
1326 }
1327
1328 static void
1329 radv_queue_finish(struct radv_queue *queue)
1330 {
1331 if (queue->hw_ctx)
1332 queue->device->ws->ctx_destroy(queue->hw_ctx);
1333
1334 if (queue->initial_full_flush_preamble_cs)
1335 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1336 if (queue->initial_preamble_cs)
1337 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1338 if (queue->continue_preamble_cs)
1339 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1340 if (queue->descriptor_bo)
1341 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1342 if (queue->scratch_bo)
1343 queue->device->ws->buffer_destroy(queue->scratch_bo);
1344 if (queue->esgs_ring_bo)
1345 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1346 if (queue->gsvs_ring_bo)
1347 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1348 if (queue->tess_rings_bo)
1349 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1350 if (queue->compute_scratch_bo)
1351 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1352 }
1353
1354 static void
1355 radv_bo_list_init(struct radv_bo_list *bo_list)
1356 {
1357 pthread_mutex_init(&bo_list->mutex, NULL);
1358 bo_list->list.count = bo_list->capacity = 0;
1359 bo_list->list.bos = NULL;
1360 }
1361
1362 static void
1363 radv_bo_list_finish(struct radv_bo_list *bo_list)
1364 {
1365 free(bo_list->list.bos);
1366 pthread_mutex_destroy(&bo_list->mutex);
1367 }
1368
1369 static VkResult radv_bo_list_add(struct radv_device *device,
1370 struct radeon_winsys_bo *bo)
1371 {
1372 struct radv_bo_list *bo_list = &device->bo_list;
1373
1374 if (unlikely(!device->use_global_bo_list))
1375 return VK_SUCCESS;
1376
1377 pthread_mutex_lock(&bo_list->mutex);
1378 if (bo_list->list.count == bo_list->capacity) {
1379 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1380 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1381
1382 if (!data) {
1383 pthread_mutex_unlock(&bo_list->mutex);
1384 return VK_ERROR_OUT_OF_HOST_MEMORY;
1385 }
1386
1387 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1388 bo_list->capacity = capacity;
1389 }
1390
1391 bo_list->list.bos[bo_list->list.count++] = bo;
1392 pthread_mutex_unlock(&bo_list->mutex);
1393 return VK_SUCCESS;
1394 }
1395
1396 static void radv_bo_list_remove(struct radv_device *device,
1397 struct radeon_winsys_bo *bo)
1398 {
1399 struct radv_bo_list *bo_list = &device->bo_list;
1400
1401 if (unlikely(!device->use_global_bo_list))
1402 return;
1403
1404 pthread_mutex_lock(&bo_list->mutex);
1405 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1406 if (bo_list->list.bos[i] == bo) {
1407 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1408 --bo_list->list.count;
1409 break;
1410 }
1411 }
1412 pthread_mutex_unlock(&bo_list->mutex);
1413 }
1414
1415 static void
1416 radv_device_init_gs_info(struct radv_device *device)
1417 {
1418 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1419 device->physical_device->rad_info.family);
1420 }
1421
1422 static int radv_get_device_extension_index(const char *name)
1423 {
1424 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1425 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1426 return i;
1427 }
1428 return -1;
1429 }
1430
1431 VkResult radv_CreateDevice(
1432 VkPhysicalDevice physicalDevice,
1433 const VkDeviceCreateInfo* pCreateInfo,
1434 const VkAllocationCallbacks* pAllocator,
1435 VkDevice* pDevice)
1436 {
1437 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1438 VkResult result;
1439 struct radv_device *device;
1440
1441 bool keep_shader_info = false;
1442
1443 /* Check enabled features */
1444 if (pCreateInfo->pEnabledFeatures) {
1445 VkPhysicalDeviceFeatures supported_features;
1446 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1447 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1448 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1449 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1450 for (uint32_t i = 0; i < num_features; i++) {
1451 if (enabled_feature[i] && !supported_feature[i])
1452 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1453 }
1454 }
1455
1456 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1457 sizeof(*device), 8,
1458 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1459 if (!device)
1460 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1461
1462 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1463 device->instance = physical_device->instance;
1464 device->physical_device = physical_device;
1465
1466 device->ws = physical_device->ws;
1467 if (pAllocator)
1468 device->alloc = *pAllocator;
1469 else
1470 device->alloc = physical_device->instance->alloc;
1471
1472 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1473 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1474 int index = radv_get_device_extension_index(ext_name);
1475 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1476 vk_free(&device->alloc, device);
1477 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1478 }
1479
1480 device->enabled_extensions.extensions[index] = true;
1481 }
1482
1483 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1484
1485 /* With update after bind we can't attach bo's to the command buffer
1486 * from the descriptor set anymore, so we have to use a global BO list.
1487 */
1488 device->use_global_bo_list =
1489 device->enabled_extensions.EXT_descriptor_indexing;
1490
1491 mtx_init(&device->shader_slab_mutex, mtx_plain);
1492 list_inithead(&device->shader_slabs);
1493
1494 radv_bo_list_init(&device->bo_list);
1495
1496 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1497 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1498 uint32_t qfi = queue_create->queueFamilyIndex;
1499 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1500 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1501
1502 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1503
1504 device->queues[qfi] = vk_alloc(&device->alloc,
1505 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1506 if (!device->queues[qfi]) {
1507 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1508 goto fail;
1509 }
1510
1511 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1512
1513 device->queue_count[qfi] = queue_create->queueCount;
1514
1515 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1516 result = radv_queue_init(device, &device->queues[qfi][q],
1517 qfi, q, queue_create->flags,
1518 global_priority);
1519 if (result != VK_SUCCESS)
1520 goto fail;
1521 }
1522 }
1523
1524 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1525 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1526 device->physical_device->rad_info.family == CHIP_RAVEN);
1527
1528 /* Disabled and not implemented for now. */
1529 device->dfsm_allowed = device->pbb_allowed &&
1530 device->physical_device->rad_info.family == CHIP_RAVEN;
1531
1532 #ifdef ANDROID
1533 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1534 #endif
1535
1536 /* The maximum number of scratch waves. Scratch space isn't divided
1537 * evenly between CUs. The number is only a function of the number of CUs.
1538 * We can decrease the constant to decrease the scratch buffer size.
1539 *
1540 * sctx->scratch_waves must be >= the maximum possible size of
1541 * 1 threadgroup, so that the hw doesn't hang from being unable
1542 * to start any.
1543 *
1544 * The recommended value is 4 per CU at most. Higher numbers don't
1545 * bring much benefit, but they still occupy chip resources (think
1546 * async compute). I've seen ~2% performance difference between 4 and 32.
1547 */
1548 uint32_t max_threads_per_block = 2048;
1549 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1550 max_threads_per_block / 64);
1551
1552 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1553
1554 if (device->physical_device->rad_info.chip_class >= CIK) {
1555 /* If the KMD allows it (there is a KMD hw register for it),
1556 * allow launching waves out-of-order.
1557 */
1558 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1559 }
1560
1561 radv_device_init_gs_info(device);
1562
1563 device->tess_offchip_block_dw_size =
1564 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1565 device->has_distributed_tess =
1566 device->physical_device->rad_info.chip_class >= VI &&
1567 device->physical_device->rad_info.max_se >= 2;
1568
1569 if (getenv("RADV_TRACE_FILE")) {
1570 const char *filename = getenv("RADV_TRACE_FILE");
1571
1572 keep_shader_info = true;
1573
1574 if (!radv_init_trace(device))
1575 goto fail;
1576
1577 fprintf(stderr, "*****************************************************************************\n");
1578 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1579 fprintf(stderr, "*****************************************************************************\n");
1580
1581 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1582 radv_dump_enabled_options(device, stderr);
1583 }
1584
1585 device->keep_shader_info = keep_shader_info;
1586
1587 result = radv_device_init_meta(device);
1588 if (result != VK_SUCCESS)
1589 goto fail;
1590
1591 radv_device_init_msaa(device);
1592
1593 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1594 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1595 switch (family) {
1596 case RADV_QUEUE_GENERAL:
1597 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1598 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1599 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1600 break;
1601 case RADV_QUEUE_COMPUTE:
1602 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1603 radeon_emit(device->empty_cs[family], 0);
1604 break;
1605 }
1606 device->ws->cs_finalize(device->empty_cs[family]);
1607 }
1608
1609 if (device->physical_device->rad_info.chip_class >= CIK)
1610 cik_create_gfx_config(device);
1611
1612 VkPipelineCacheCreateInfo ci;
1613 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1614 ci.pNext = NULL;
1615 ci.flags = 0;
1616 ci.pInitialData = NULL;
1617 ci.initialDataSize = 0;
1618 VkPipelineCache pc;
1619 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1620 &ci, NULL, &pc);
1621 if (result != VK_SUCCESS)
1622 goto fail_meta;
1623
1624 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1625
1626 *pDevice = radv_device_to_handle(device);
1627 return VK_SUCCESS;
1628
1629 fail_meta:
1630 radv_device_finish_meta(device);
1631 fail:
1632 radv_bo_list_finish(&device->bo_list);
1633
1634 if (device->trace_bo)
1635 device->ws->buffer_destroy(device->trace_bo);
1636
1637 if (device->gfx_init)
1638 device->ws->buffer_destroy(device->gfx_init);
1639
1640 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1641 for (unsigned q = 0; q < device->queue_count[i]; q++)
1642 radv_queue_finish(&device->queues[i][q]);
1643 if (device->queue_count[i])
1644 vk_free(&device->alloc, device->queues[i]);
1645 }
1646
1647 vk_free(&device->alloc, device);
1648 return result;
1649 }
1650
1651 void radv_DestroyDevice(
1652 VkDevice _device,
1653 const VkAllocationCallbacks* pAllocator)
1654 {
1655 RADV_FROM_HANDLE(radv_device, device, _device);
1656
1657 if (!device)
1658 return;
1659
1660 if (device->trace_bo)
1661 device->ws->buffer_destroy(device->trace_bo);
1662
1663 if (device->gfx_init)
1664 device->ws->buffer_destroy(device->gfx_init);
1665
1666 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1667 for (unsigned q = 0; q < device->queue_count[i]; q++)
1668 radv_queue_finish(&device->queues[i][q]);
1669 if (device->queue_count[i])
1670 vk_free(&device->alloc, device->queues[i]);
1671 if (device->empty_cs[i])
1672 device->ws->cs_destroy(device->empty_cs[i]);
1673 }
1674 radv_device_finish_meta(device);
1675
1676 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1677 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1678
1679 radv_destroy_shader_slabs(device);
1680
1681 radv_bo_list_finish(&device->bo_list);
1682 vk_free(&device->alloc, device);
1683 }
1684
1685 VkResult radv_EnumerateInstanceLayerProperties(
1686 uint32_t* pPropertyCount,
1687 VkLayerProperties* pProperties)
1688 {
1689 if (pProperties == NULL) {
1690 *pPropertyCount = 0;
1691 return VK_SUCCESS;
1692 }
1693
1694 /* None supported at this time */
1695 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1696 }
1697
1698 VkResult radv_EnumerateDeviceLayerProperties(
1699 VkPhysicalDevice physicalDevice,
1700 uint32_t* pPropertyCount,
1701 VkLayerProperties* pProperties)
1702 {
1703 if (pProperties == NULL) {
1704 *pPropertyCount = 0;
1705 return VK_SUCCESS;
1706 }
1707
1708 /* None supported at this time */
1709 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1710 }
1711
1712 void radv_GetDeviceQueue2(
1713 VkDevice _device,
1714 const VkDeviceQueueInfo2* pQueueInfo,
1715 VkQueue* pQueue)
1716 {
1717 RADV_FROM_HANDLE(radv_device, device, _device);
1718 struct radv_queue *queue;
1719
1720 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1721 if (pQueueInfo->flags != queue->flags) {
1722 /* From the Vulkan 1.1.70 spec:
1723 *
1724 * "The queue returned by vkGetDeviceQueue2 must have the same
1725 * flags value from this structure as that used at device
1726 * creation time in a VkDeviceQueueCreateInfo instance. If no
1727 * matching flags were specified at device creation time then
1728 * pQueue will return VK_NULL_HANDLE."
1729 */
1730 *pQueue = VK_NULL_HANDLE;
1731 return;
1732 }
1733
1734 *pQueue = radv_queue_to_handle(queue);
1735 }
1736
1737 void radv_GetDeviceQueue(
1738 VkDevice _device,
1739 uint32_t queueFamilyIndex,
1740 uint32_t queueIndex,
1741 VkQueue* pQueue)
1742 {
1743 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1744 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1745 .queueFamilyIndex = queueFamilyIndex,
1746 .queueIndex = queueIndex
1747 };
1748
1749 radv_GetDeviceQueue2(_device, &info, pQueue);
1750 }
1751
1752 static void
1753 fill_geom_tess_rings(struct radv_queue *queue,
1754 uint32_t *map,
1755 bool add_sample_positions,
1756 uint32_t esgs_ring_size,
1757 struct radeon_winsys_bo *esgs_ring_bo,
1758 uint32_t gsvs_ring_size,
1759 struct radeon_winsys_bo *gsvs_ring_bo,
1760 uint32_t tess_factor_ring_size,
1761 uint32_t tess_offchip_ring_offset,
1762 uint32_t tess_offchip_ring_size,
1763 struct radeon_winsys_bo *tess_rings_bo)
1764 {
1765 uint64_t esgs_va = 0, gsvs_va = 0;
1766 uint64_t tess_va = 0, tess_offchip_va = 0;
1767 uint32_t *desc = &map[4];
1768
1769 if (esgs_ring_bo)
1770 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1771 if (gsvs_ring_bo)
1772 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1773 if (tess_rings_bo) {
1774 tess_va = radv_buffer_get_va(tess_rings_bo);
1775 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1776 }
1777
1778 /* stride 0, num records - size, add tid, swizzle, elsize4,
1779 index stride 64 */
1780 desc[0] = esgs_va;
1781 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1782 S_008F04_STRIDE(0) |
1783 S_008F04_SWIZZLE_ENABLE(true);
1784 desc[2] = esgs_ring_size;
1785 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1786 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1787 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1788 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1789 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1790 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1791 S_008F0C_ELEMENT_SIZE(1) |
1792 S_008F0C_INDEX_STRIDE(3) |
1793 S_008F0C_ADD_TID_ENABLE(true);
1794
1795 desc += 4;
1796 /* GS entry for ES->GS ring */
1797 /* stride 0, num records - size, elsize0,
1798 index stride 0 */
1799 desc[0] = esgs_va;
1800 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1801 S_008F04_STRIDE(0) |
1802 S_008F04_SWIZZLE_ENABLE(false);
1803 desc[2] = esgs_ring_size;
1804 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1805 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1806 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1807 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1808 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1809 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1810 S_008F0C_ELEMENT_SIZE(0) |
1811 S_008F0C_INDEX_STRIDE(0) |
1812 S_008F0C_ADD_TID_ENABLE(false);
1813
1814 desc += 4;
1815 /* VS entry for GS->VS ring */
1816 /* stride 0, num records - size, elsize0,
1817 index stride 0 */
1818 desc[0] = gsvs_va;
1819 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1820 S_008F04_STRIDE(0) |
1821 S_008F04_SWIZZLE_ENABLE(false);
1822 desc[2] = gsvs_ring_size;
1823 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1824 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1825 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1826 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1827 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1828 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1829 S_008F0C_ELEMENT_SIZE(0) |
1830 S_008F0C_INDEX_STRIDE(0) |
1831 S_008F0C_ADD_TID_ENABLE(false);
1832 desc += 4;
1833
1834 /* stride gsvs_itemsize, num records 64
1835 elsize 4, index stride 16 */
1836 /* shader will patch stride and desc[2] */
1837 desc[0] = gsvs_va;
1838 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1839 S_008F04_STRIDE(0) |
1840 S_008F04_SWIZZLE_ENABLE(true);
1841 desc[2] = 0;
1842 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1843 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1844 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1845 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1846 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1847 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1848 S_008F0C_ELEMENT_SIZE(1) |
1849 S_008F0C_INDEX_STRIDE(1) |
1850 S_008F0C_ADD_TID_ENABLE(true);
1851 desc += 4;
1852
1853 desc[0] = tess_va;
1854 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1855 S_008F04_STRIDE(0) |
1856 S_008F04_SWIZZLE_ENABLE(false);
1857 desc[2] = tess_factor_ring_size;
1858 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1859 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1860 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1861 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1862 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1863 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1864 S_008F0C_ELEMENT_SIZE(0) |
1865 S_008F0C_INDEX_STRIDE(0) |
1866 S_008F0C_ADD_TID_ENABLE(false);
1867 desc += 4;
1868
1869 desc[0] = tess_offchip_va;
1870 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1871 S_008F04_STRIDE(0) |
1872 S_008F04_SWIZZLE_ENABLE(false);
1873 desc[2] = tess_offchip_ring_size;
1874 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1875 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1876 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1877 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1878 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1879 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1880 S_008F0C_ELEMENT_SIZE(0) |
1881 S_008F0C_INDEX_STRIDE(0) |
1882 S_008F0C_ADD_TID_ENABLE(false);
1883 desc += 4;
1884
1885 /* add sample positions after all rings */
1886 memcpy(desc, queue->device->sample_locations_1x, 8);
1887 desc += 2;
1888 memcpy(desc, queue->device->sample_locations_2x, 16);
1889 desc += 4;
1890 memcpy(desc, queue->device->sample_locations_4x, 32);
1891 desc += 8;
1892 memcpy(desc, queue->device->sample_locations_8x, 64);
1893 desc += 16;
1894 memcpy(desc, queue->device->sample_locations_16x, 128);
1895 }
1896
1897 static unsigned
1898 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1899 {
1900 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1901 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1902 device->physical_device->rad_info.family != CHIP_STONEY;
1903 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1904 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1905 device->physical_device->rad_info.max_se;
1906 unsigned offchip_granularity;
1907 unsigned hs_offchip_param;
1908 switch (device->tess_offchip_block_dw_size) {
1909 default:
1910 assert(0);
1911 /* fall through */
1912 case 8192:
1913 offchip_granularity = V_03093C_X_8K_DWORDS;
1914 break;
1915 case 4096:
1916 offchip_granularity = V_03093C_X_4K_DWORDS;
1917 break;
1918 }
1919
1920 switch (device->physical_device->rad_info.chip_class) {
1921 case SI:
1922 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1923 break;
1924 case CIK:
1925 case VI:
1926 case GFX9:
1927 default:
1928 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1929 break;
1930 }
1931
1932 *max_offchip_buffers_p = max_offchip_buffers;
1933 if (device->physical_device->rad_info.chip_class >= CIK) {
1934 if (device->physical_device->rad_info.chip_class >= VI)
1935 --max_offchip_buffers;
1936 hs_offchip_param =
1937 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1938 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1939 } else {
1940 hs_offchip_param =
1941 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1942 }
1943 return hs_offchip_param;
1944 }
1945
1946 static void
1947 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1948 struct radeon_winsys_bo *esgs_ring_bo,
1949 uint32_t esgs_ring_size,
1950 struct radeon_winsys_bo *gsvs_ring_bo,
1951 uint32_t gsvs_ring_size)
1952 {
1953 if (!esgs_ring_bo && !gsvs_ring_bo)
1954 return;
1955
1956 if (esgs_ring_bo)
1957 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1958
1959 if (gsvs_ring_bo)
1960 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1961
1962 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1963 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1964 radeon_emit(cs, esgs_ring_size >> 8);
1965 radeon_emit(cs, gsvs_ring_size >> 8);
1966 } else {
1967 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1968 radeon_emit(cs, esgs_ring_size >> 8);
1969 radeon_emit(cs, gsvs_ring_size >> 8);
1970 }
1971 }
1972
1973 static void
1974 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1975 unsigned hs_offchip_param, unsigned tf_ring_size,
1976 struct radeon_winsys_bo *tess_rings_bo)
1977 {
1978 uint64_t tf_va;
1979
1980 if (!tess_rings_bo)
1981 return;
1982
1983 tf_va = radv_buffer_get_va(tess_rings_bo);
1984
1985 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
1986
1987 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1988 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1989 S_030938_SIZE(tf_ring_size / 4));
1990 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1991 tf_va >> 8);
1992 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1993 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1994 S_030944_BASE_HI(tf_va >> 40));
1995 }
1996 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1997 hs_offchip_param);
1998 } else {
1999 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2000 S_008988_SIZE(tf_ring_size / 4));
2001 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2002 tf_va >> 8);
2003 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2004 hs_offchip_param);
2005 }
2006 }
2007
2008 static void
2009 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2010 struct radeon_winsys_bo *compute_scratch_bo)
2011 {
2012 uint64_t scratch_va;
2013
2014 if (!compute_scratch_bo)
2015 return;
2016
2017 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2018
2019 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2020
2021 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2022 radeon_emit(cs, scratch_va);
2023 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2024 S_008F04_SWIZZLE_ENABLE(1));
2025 }
2026
2027 static void
2028 radv_emit_global_shader_pointers(struct radv_queue *queue,
2029 struct radeon_cmdbuf *cs,
2030 struct radeon_winsys_bo *descriptor_bo)
2031 {
2032 uint64_t va;
2033
2034 if (!descriptor_bo)
2035 return;
2036
2037 va = radv_buffer_get_va(descriptor_bo);
2038
2039 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2040
2041 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2042 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2043 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2044 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2045 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2046
2047 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2048 radv_emit_shader_pointer(queue->device, cs, regs[i],
2049 va, true);
2050 }
2051 } else {
2052 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2053 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2054 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2055 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2056 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2057 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2058
2059 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2060 radv_emit_shader_pointer(queue->device, cs, regs[i],
2061 va, true);
2062 }
2063 }
2064 }
2065
2066 static VkResult
2067 radv_get_preamble_cs(struct radv_queue *queue,
2068 uint32_t scratch_size,
2069 uint32_t compute_scratch_size,
2070 uint32_t esgs_ring_size,
2071 uint32_t gsvs_ring_size,
2072 bool needs_tess_rings,
2073 bool needs_sample_positions,
2074 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2075 struct radeon_cmdbuf **initial_preamble_cs,
2076 struct radeon_cmdbuf **continue_preamble_cs)
2077 {
2078 struct radeon_winsys_bo *scratch_bo = NULL;
2079 struct radeon_winsys_bo *descriptor_bo = NULL;
2080 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2081 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2082 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2083 struct radeon_winsys_bo *tess_rings_bo = NULL;
2084 struct radeon_cmdbuf *dest_cs[3] = {0};
2085 bool add_tess_rings = false, add_sample_positions = false;
2086 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2087 unsigned max_offchip_buffers;
2088 unsigned hs_offchip_param = 0;
2089 unsigned tess_offchip_ring_offset;
2090 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2091 if (!queue->has_tess_rings) {
2092 if (needs_tess_rings)
2093 add_tess_rings = true;
2094 }
2095 if (!queue->has_sample_positions) {
2096 if (needs_sample_positions)
2097 add_sample_positions = true;
2098 }
2099 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2100 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2101 &max_offchip_buffers);
2102 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2103 tess_offchip_ring_size = max_offchip_buffers *
2104 queue->device->tess_offchip_block_dw_size * 4;
2105
2106 if (scratch_size <= queue->scratch_size &&
2107 compute_scratch_size <= queue->compute_scratch_size &&
2108 esgs_ring_size <= queue->esgs_ring_size &&
2109 gsvs_ring_size <= queue->gsvs_ring_size &&
2110 !add_tess_rings && !add_sample_positions &&
2111 queue->initial_preamble_cs) {
2112 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2113 *initial_preamble_cs = queue->initial_preamble_cs;
2114 *continue_preamble_cs = queue->continue_preamble_cs;
2115 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2116 *continue_preamble_cs = NULL;
2117 return VK_SUCCESS;
2118 }
2119
2120 if (scratch_size > queue->scratch_size) {
2121 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2122 scratch_size,
2123 4096,
2124 RADEON_DOMAIN_VRAM,
2125 ring_bo_flags);
2126 if (!scratch_bo)
2127 goto fail;
2128 } else
2129 scratch_bo = queue->scratch_bo;
2130
2131 if (compute_scratch_size > queue->compute_scratch_size) {
2132 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2133 compute_scratch_size,
2134 4096,
2135 RADEON_DOMAIN_VRAM,
2136 ring_bo_flags);
2137 if (!compute_scratch_bo)
2138 goto fail;
2139
2140 } else
2141 compute_scratch_bo = queue->compute_scratch_bo;
2142
2143 if (esgs_ring_size > queue->esgs_ring_size) {
2144 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2145 esgs_ring_size,
2146 4096,
2147 RADEON_DOMAIN_VRAM,
2148 ring_bo_flags);
2149 if (!esgs_ring_bo)
2150 goto fail;
2151 } else {
2152 esgs_ring_bo = queue->esgs_ring_bo;
2153 esgs_ring_size = queue->esgs_ring_size;
2154 }
2155
2156 if (gsvs_ring_size > queue->gsvs_ring_size) {
2157 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2158 gsvs_ring_size,
2159 4096,
2160 RADEON_DOMAIN_VRAM,
2161 ring_bo_flags);
2162 if (!gsvs_ring_bo)
2163 goto fail;
2164 } else {
2165 gsvs_ring_bo = queue->gsvs_ring_bo;
2166 gsvs_ring_size = queue->gsvs_ring_size;
2167 }
2168
2169 if (add_tess_rings) {
2170 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2171 tess_offchip_ring_offset + tess_offchip_ring_size,
2172 256,
2173 RADEON_DOMAIN_VRAM,
2174 ring_bo_flags);
2175 if (!tess_rings_bo)
2176 goto fail;
2177 } else {
2178 tess_rings_bo = queue->tess_rings_bo;
2179 }
2180
2181 if (scratch_bo != queue->scratch_bo ||
2182 esgs_ring_bo != queue->esgs_ring_bo ||
2183 gsvs_ring_bo != queue->gsvs_ring_bo ||
2184 tess_rings_bo != queue->tess_rings_bo ||
2185 add_sample_positions) {
2186 uint32_t size = 0;
2187 if (gsvs_ring_bo || esgs_ring_bo ||
2188 tess_rings_bo || add_sample_positions) {
2189 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2190 if (add_sample_positions)
2191 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2192 }
2193 else if (scratch_bo)
2194 size = 8; /* 2 dword */
2195
2196 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2197 size,
2198 4096,
2199 RADEON_DOMAIN_VRAM,
2200 RADEON_FLAG_CPU_ACCESS |
2201 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2202 RADEON_FLAG_READ_ONLY);
2203 if (!descriptor_bo)
2204 goto fail;
2205 } else
2206 descriptor_bo = queue->descriptor_bo;
2207
2208 for(int i = 0; i < 3; ++i) {
2209 struct radeon_cmdbuf *cs = NULL;
2210 cs = queue->device->ws->cs_create(queue->device->ws,
2211 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2212 if (!cs)
2213 goto fail;
2214
2215 dest_cs[i] = cs;
2216
2217 if (scratch_bo)
2218 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2219
2220 if (descriptor_bo != queue->descriptor_bo) {
2221 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2222
2223 if (scratch_bo) {
2224 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2225 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2226 S_008F04_SWIZZLE_ENABLE(1);
2227 map[0] = scratch_va;
2228 map[1] = rsrc1;
2229 }
2230
2231 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2232 add_sample_positions)
2233 fill_geom_tess_rings(queue, map, add_sample_positions,
2234 esgs_ring_size, esgs_ring_bo,
2235 gsvs_ring_size, gsvs_ring_bo,
2236 tess_factor_ring_size,
2237 tess_offchip_ring_offset,
2238 tess_offchip_ring_size,
2239 tess_rings_bo);
2240
2241 queue->device->ws->buffer_unmap(descriptor_bo);
2242 }
2243
2244 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2245 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2246 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2247 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2248 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2249 }
2250
2251 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2252 gsvs_ring_bo, gsvs_ring_size);
2253 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2254 tess_factor_ring_size, tess_rings_bo);
2255 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2256 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2257
2258 if (i == 0) {
2259 si_cs_emit_cache_flush(cs,
2260 queue->device->physical_device->rad_info.chip_class,
2261 NULL, 0,
2262 queue->queue_family_index == RING_COMPUTE &&
2263 queue->device->physical_device->rad_info.chip_class >= CIK,
2264 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2265 RADV_CMD_FLAG_INV_ICACHE |
2266 RADV_CMD_FLAG_INV_SMEM_L1 |
2267 RADV_CMD_FLAG_INV_VMEM_L1 |
2268 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2269 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2270 } else if (i == 1) {
2271 si_cs_emit_cache_flush(cs,
2272 queue->device->physical_device->rad_info.chip_class,
2273 NULL, 0,
2274 queue->queue_family_index == RING_COMPUTE &&
2275 queue->device->physical_device->rad_info.chip_class >= CIK,
2276 RADV_CMD_FLAG_INV_ICACHE |
2277 RADV_CMD_FLAG_INV_SMEM_L1 |
2278 RADV_CMD_FLAG_INV_VMEM_L1 |
2279 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2280 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2281 }
2282
2283 if (!queue->device->ws->cs_finalize(cs))
2284 goto fail;
2285 }
2286
2287 if (queue->initial_full_flush_preamble_cs)
2288 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2289
2290 if (queue->initial_preamble_cs)
2291 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2292
2293 if (queue->continue_preamble_cs)
2294 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2295
2296 queue->initial_full_flush_preamble_cs = dest_cs[0];
2297 queue->initial_preamble_cs = dest_cs[1];
2298 queue->continue_preamble_cs = dest_cs[2];
2299
2300 if (scratch_bo != queue->scratch_bo) {
2301 if (queue->scratch_bo)
2302 queue->device->ws->buffer_destroy(queue->scratch_bo);
2303 queue->scratch_bo = scratch_bo;
2304 queue->scratch_size = scratch_size;
2305 }
2306
2307 if (compute_scratch_bo != queue->compute_scratch_bo) {
2308 if (queue->compute_scratch_bo)
2309 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2310 queue->compute_scratch_bo = compute_scratch_bo;
2311 queue->compute_scratch_size = compute_scratch_size;
2312 }
2313
2314 if (esgs_ring_bo != queue->esgs_ring_bo) {
2315 if (queue->esgs_ring_bo)
2316 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2317 queue->esgs_ring_bo = esgs_ring_bo;
2318 queue->esgs_ring_size = esgs_ring_size;
2319 }
2320
2321 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2322 if (queue->gsvs_ring_bo)
2323 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2324 queue->gsvs_ring_bo = gsvs_ring_bo;
2325 queue->gsvs_ring_size = gsvs_ring_size;
2326 }
2327
2328 if (tess_rings_bo != queue->tess_rings_bo) {
2329 queue->tess_rings_bo = tess_rings_bo;
2330 queue->has_tess_rings = true;
2331 }
2332
2333 if (descriptor_bo != queue->descriptor_bo) {
2334 if (queue->descriptor_bo)
2335 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2336
2337 queue->descriptor_bo = descriptor_bo;
2338 }
2339
2340 if (add_sample_positions)
2341 queue->has_sample_positions = true;
2342
2343 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2344 *initial_preamble_cs = queue->initial_preamble_cs;
2345 *continue_preamble_cs = queue->continue_preamble_cs;
2346 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2347 *continue_preamble_cs = NULL;
2348 return VK_SUCCESS;
2349 fail:
2350 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2351 if (dest_cs[i])
2352 queue->device->ws->cs_destroy(dest_cs[i]);
2353 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2354 queue->device->ws->buffer_destroy(descriptor_bo);
2355 if (scratch_bo && scratch_bo != queue->scratch_bo)
2356 queue->device->ws->buffer_destroy(scratch_bo);
2357 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2358 queue->device->ws->buffer_destroy(compute_scratch_bo);
2359 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2360 queue->device->ws->buffer_destroy(esgs_ring_bo);
2361 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2362 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2363 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2364 queue->device->ws->buffer_destroy(tess_rings_bo);
2365 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2366 }
2367
2368 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2369 struct radv_winsys_sem_counts *counts,
2370 int num_sems,
2371 const VkSemaphore *sems,
2372 VkFence _fence,
2373 bool reset_temp)
2374 {
2375 int syncobj_idx = 0, sem_idx = 0;
2376
2377 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2378 return VK_SUCCESS;
2379
2380 for (uint32_t i = 0; i < num_sems; i++) {
2381 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2382
2383 if (sem->temp_syncobj || sem->syncobj)
2384 counts->syncobj_count++;
2385 else
2386 counts->sem_count++;
2387 }
2388
2389 if (_fence != VK_NULL_HANDLE) {
2390 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2391 if (fence->temp_syncobj || fence->syncobj)
2392 counts->syncobj_count++;
2393 }
2394
2395 if (counts->syncobj_count) {
2396 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2397 if (!counts->syncobj)
2398 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2399 }
2400
2401 if (counts->sem_count) {
2402 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2403 if (!counts->sem) {
2404 free(counts->syncobj);
2405 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2406 }
2407 }
2408
2409 for (uint32_t i = 0; i < num_sems; i++) {
2410 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2411
2412 if (sem->temp_syncobj) {
2413 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2414 }
2415 else if (sem->syncobj)
2416 counts->syncobj[syncobj_idx++] = sem->syncobj;
2417 else {
2418 assert(sem->sem);
2419 counts->sem[sem_idx++] = sem->sem;
2420 }
2421 }
2422
2423 if (_fence != VK_NULL_HANDLE) {
2424 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2425 if (fence->temp_syncobj)
2426 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2427 else if (fence->syncobj)
2428 counts->syncobj[syncobj_idx++] = fence->syncobj;
2429 }
2430
2431 return VK_SUCCESS;
2432 }
2433
2434 static void
2435 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2436 {
2437 free(sem_info->wait.syncobj);
2438 free(sem_info->wait.sem);
2439 free(sem_info->signal.syncobj);
2440 free(sem_info->signal.sem);
2441 }
2442
2443
2444 static void radv_free_temp_syncobjs(struct radv_device *device,
2445 int num_sems,
2446 const VkSemaphore *sems)
2447 {
2448 for (uint32_t i = 0; i < num_sems; i++) {
2449 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2450
2451 if (sem->temp_syncobj) {
2452 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2453 sem->temp_syncobj = 0;
2454 }
2455 }
2456 }
2457
2458 static VkResult
2459 radv_alloc_sem_info(struct radv_instance *instance,
2460 struct radv_winsys_sem_info *sem_info,
2461 int num_wait_sems,
2462 const VkSemaphore *wait_sems,
2463 int num_signal_sems,
2464 const VkSemaphore *signal_sems,
2465 VkFence fence)
2466 {
2467 VkResult ret;
2468 memset(sem_info, 0, sizeof(*sem_info));
2469
2470 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2471 if (ret)
2472 return ret;
2473 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2474 if (ret)
2475 radv_free_sem_info(sem_info);
2476
2477 /* caller can override these */
2478 sem_info->cs_emit_wait = true;
2479 sem_info->cs_emit_signal = true;
2480 return ret;
2481 }
2482
2483 /* Signals fence as soon as all the work currently put on queue is done. */
2484 static VkResult radv_signal_fence(struct radv_queue *queue,
2485 struct radv_fence *fence)
2486 {
2487 int ret;
2488 VkResult result;
2489 struct radv_winsys_sem_info sem_info;
2490
2491 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2492 radv_fence_to_handle(fence));
2493 if (result != VK_SUCCESS)
2494 return result;
2495
2496 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2497 &queue->device->empty_cs[queue->queue_family_index],
2498 1, NULL, NULL, &sem_info, NULL,
2499 false, fence->fence);
2500 radv_free_sem_info(&sem_info);
2501
2502 if (ret)
2503 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2504
2505 return VK_SUCCESS;
2506 }
2507
2508 VkResult radv_QueueSubmit(
2509 VkQueue _queue,
2510 uint32_t submitCount,
2511 const VkSubmitInfo* pSubmits,
2512 VkFence _fence)
2513 {
2514 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2515 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2516 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2517 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2518 int ret;
2519 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2520 uint32_t scratch_size = 0;
2521 uint32_t compute_scratch_size = 0;
2522 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2523 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2524 VkResult result;
2525 bool fence_emitted = false;
2526 bool tess_rings_needed = false;
2527 bool sample_positions_needed = false;
2528
2529 /* Do this first so failing to allocate scratch buffers can't result in
2530 * partially executed submissions. */
2531 for (uint32_t i = 0; i < submitCount; i++) {
2532 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2533 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2534 pSubmits[i].pCommandBuffers[j]);
2535
2536 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2537 compute_scratch_size = MAX2(compute_scratch_size,
2538 cmd_buffer->compute_scratch_size_needed);
2539 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2540 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2541 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2542 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2543 }
2544 }
2545
2546 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2547 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2548 sample_positions_needed, &initial_flush_preamble_cs,
2549 &initial_preamble_cs, &continue_preamble_cs);
2550 if (result != VK_SUCCESS)
2551 return result;
2552
2553 for (uint32_t i = 0; i < submitCount; i++) {
2554 struct radeon_cmdbuf **cs_array;
2555 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2556 bool can_patch = true;
2557 uint32_t advance;
2558 struct radv_winsys_sem_info sem_info;
2559
2560 result = radv_alloc_sem_info(queue->device->instance,
2561 &sem_info,
2562 pSubmits[i].waitSemaphoreCount,
2563 pSubmits[i].pWaitSemaphores,
2564 pSubmits[i].signalSemaphoreCount,
2565 pSubmits[i].pSignalSemaphores,
2566 _fence);
2567 if (result != VK_SUCCESS)
2568 return result;
2569
2570 if (!pSubmits[i].commandBufferCount) {
2571 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2572 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2573 &queue->device->empty_cs[queue->queue_family_index],
2574 1, NULL, NULL,
2575 &sem_info, NULL,
2576 false, base_fence);
2577 if (ret) {
2578 radv_loge("failed to submit CS %d\n", i);
2579 abort();
2580 }
2581 fence_emitted = true;
2582 }
2583 radv_free_sem_info(&sem_info);
2584 continue;
2585 }
2586
2587 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2588 (pSubmits[i].commandBufferCount));
2589
2590 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2591 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2592 pSubmits[i].pCommandBuffers[j]);
2593 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2594
2595 cs_array[j] = cmd_buffer->cs;
2596 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2597 can_patch = false;
2598
2599 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2600 }
2601
2602 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2603 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2604 const struct radv_winsys_bo_list *bo_list = NULL;
2605
2606 advance = MIN2(max_cs_submission,
2607 pSubmits[i].commandBufferCount - j);
2608
2609 if (queue->device->trace_bo)
2610 *queue->device->trace_id_ptr = 0;
2611
2612 sem_info.cs_emit_wait = j == 0;
2613 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2614
2615 if (unlikely(queue->device->use_global_bo_list)) {
2616 pthread_mutex_lock(&queue->device->bo_list.mutex);
2617 bo_list = &queue->device->bo_list.list;
2618 }
2619
2620 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2621 advance, initial_preamble, continue_preamble_cs,
2622 &sem_info, bo_list,
2623 can_patch, base_fence);
2624
2625 if (unlikely(queue->device->use_global_bo_list))
2626 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2627
2628 if (ret) {
2629 radv_loge("failed to submit CS %d\n", i);
2630 abort();
2631 }
2632 fence_emitted = true;
2633 if (queue->device->trace_bo) {
2634 radv_check_gpu_hangs(queue, cs_array[j]);
2635 }
2636 }
2637
2638 radv_free_temp_syncobjs(queue->device,
2639 pSubmits[i].waitSemaphoreCount,
2640 pSubmits[i].pWaitSemaphores);
2641 radv_free_sem_info(&sem_info);
2642 free(cs_array);
2643 }
2644
2645 if (fence) {
2646 if (!fence_emitted) {
2647 result = radv_signal_fence(queue, fence);
2648 if (result != VK_SUCCESS)
2649 return result;
2650 }
2651 fence->submitted = true;
2652 }
2653
2654 return VK_SUCCESS;
2655 }
2656
2657 VkResult radv_QueueWaitIdle(
2658 VkQueue _queue)
2659 {
2660 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2661
2662 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2663 radv_queue_family_to_ring(queue->queue_family_index),
2664 queue->queue_idx);
2665 return VK_SUCCESS;
2666 }
2667
2668 VkResult radv_DeviceWaitIdle(
2669 VkDevice _device)
2670 {
2671 RADV_FROM_HANDLE(radv_device, device, _device);
2672
2673 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2674 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2675 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2676 }
2677 }
2678 return VK_SUCCESS;
2679 }
2680
2681 VkResult radv_EnumerateInstanceExtensionProperties(
2682 const char* pLayerName,
2683 uint32_t* pPropertyCount,
2684 VkExtensionProperties* pProperties)
2685 {
2686 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2687
2688 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2689 if (radv_supported_instance_extensions.extensions[i]) {
2690 vk_outarray_append(&out, prop) {
2691 *prop = radv_instance_extensions[i];
2692 }
2693 }
2694 }
2695
2696 return vk_outarray_status(&out);
2697 }
2698
2699 VkResult radv_EnumerateDeviceExtensionProperties(
2700 VkPhysicalDevice physicalDevice,
2701 const char* pLayerName,
2702 uint32_t* pPropertyCount,
2703 VkExtensionProperties* pProperties)
2704 {
2705 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2706 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2707
2708 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2709 if (device->supported_extensions.extensions[i]) {
2710 vk_outarray_append(&out, prop) {
2711 *prop = radv_device_extensions[i];
2712 }
2713 }
2714 }
2715
2716 return vk_outarray_status(&out);
2717 }
2718
2719 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2720 VkInstance _instance,
2721 const char* pName)
2722 {
2723 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2724
2725 return radv_lookup_entrypoint_checked(pName,
2726 instance ? instance->apiVersion : 0,
2727 instance ? &instance->enabled_extensions : NULL,
2728 NULL);
2729 }
2730
2731 /* The loader wants us to expose a second GetInstanceProcAddr function
2732 * to work around certain LD_PRELOAD issues seen in apps.
2733 */
2734 PUBLIC
2735 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2736 VkInstance instance,
2737 const char* pName);
2738
2739 PUBLIC
2740 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2741 VkInstance instance,
2742 const char* pName)
2743 {
2744 return radv_GetInstanceProcAddr(instance, pName);
2745 }
2746
2747 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2748 VkDevice _device,
2749 const char* pName)
2750 {
2751 RADV_FROM_HANDLE(radv_device, device, _device);
2752
2753 return radv_lookup_entrypoint_checked(pName,
2754 device->instance->apiVersion,
2755 &device->instance->enabled_extensions,
2756 &device->enabled_extensions);
2757 }
2758
2759 bool radv_get_memory_fd(struct radv_device *device,
2760 struct radv_device_memory *memory,
2761 int *pFD)
2762 {
2763 struct radeon_bo_metadata metadata;
2764
2765 if (memory->image) {
2766 radv_init_metadata(device, memory->image, &metadata);
2767 device->ws->buffer_set_metadata(memory->bo, &metadata);
2768 }
2769
2770 return device->ws->buffer_get_fd(device->ws, memory->bo,
2771 pFD);
2772 }
2773
2774 static VkResult radv_alloc_memory(struct radv_device *device,
2775 const VkMemoryAllocateInfo* pAllocateInfo,
2776 const VkAllocationCallbacks* pAllocator,
2777 VkDeviceMemory* pMem)
2778 {
2779 struct radv_device_memory *mem;
2780 VkResult result;
2781 enum radeon_bo_domain domain;
2782 uint32_t flags = 0;
2783 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2784
2785 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2786
2787 if (pAllocateInfo->allocationSize == 0) {
2788 /* Apparently, this is allowed */
2789 *pMem = VK_NULL_HANDLE;
2790 return VK_SUCCESS;
2791 }
2792
2793 const VkImportMemoryFdInfoKHR *import_info =
2794 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2795 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2796 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2797 const VkExportMemoryAllocateInfoKHR *export_info =
2798 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2799 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2800 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2801
2802 const struct wsi_memory_allocate_info *wsi_info =
2803 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2804
2805 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2806 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2807 if (mem == NULL)
2808 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2809
2810 if (wsi_info && wsi_info->implicit_sync)
2811 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2812
2813 if (dedicate_info) {
2814 mem->image = radv_image_from_handle(dedicate_info->image);
2815 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2816 } else {
2817 mem->image = NULL;
2818 mem->buffer = NULL;
2819 }
2820
2821 mem->user_ptr = NULL;
2822
2823 if (import_info) {
2824 assert(import_info->handleType ==
2825 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2826 import_info->handleType ==
2827 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2828 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2829 NULL, NULL);
2830 if (!mem->bo) {
2831 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2832 goto fail;
2833 } else {
2834 close(import_info->fd);
2835 }
2836 } else if (host_ptr_info) {
2837 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2838 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2839 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2840 pAllocateInfo->allocationSize);
2841 if (!mem->bo) {
2842 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2843 goto fail;
2844 } else {
2845 mem->user_ptr = host_ptr_info->pHostPointer;
2846 }
2847 } else {
2848 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2849 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2850 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2851 domain = RADEON_DOMAIN_GTT;
2852 else
2853 domain = RADEON_DOMAIN_VRAM;
2854
2855 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2856 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2857 else
2858 flags |= RADEON_FLAG_CPU_ACCESS;
2859
2860 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2861 flags |= RADEON_FLAG_GTT_WC;
2862
2863 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2864 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2865
2866 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2867 domain, flags);
2868
2869 if (!mem->bo) {
2870 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2871 goto fail;
2872 }
2873 mem->type_index = mem_type_index;
2874 }
2875
2876 result = radv_bo_list_add(device, mem->bo);
2877 if (result != VK_SUCCESS)
2878 goto fail_bo;
2879
2880 *pMem = radv_device_memory_to_handle(mem);
2881
2882 return VK_SUCCESS;
2883
2884 fail_bo:
2885 device->ws->buffer_destroy(mem->bo);
2886 fail:
2887 vk_free2(&device->alloc, pAllocator, mem);
2888
2889 return result;
2890 }
2891
2892 VkResult radv_AllocateMemory(
2893 VkDevice _device,
2894 const VkMemoryAllocateInfo* pAllocateInfo,
2895 const VkAllocationCallbacks* pAllocator,
2896 VkDeviceMemory* pMem)
2897 {
2898 RADV_FROM_HANDLE(radv_device, device, _device);
2899 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2900 }
2901
2902 void radv_FreeMemory(
2903 VkDevice _device,
2904 VkDeviceMemory _mem,
2905 const VkAllocationCallbacks* pAllocator)
2906 {
2907 RADV_FROM_HANDLE(radv_device, device, _device);
2908 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2909
2910 if (mem == NULL)
2911 return;
2912
2913 radv_bo_list_remove(device, mem->bo);
2914 device->ws->buffer_destroy(mem->bo);
2915 mem->bo = NULL;
2916
2917 vk_free2(&device->alloc, pAllocator, mem);
2918 }
2919
2920 VkResult radv_MapMemory(
2921 VkDevice _device,
2922 VkDeviceMemory _memory,
2923 VkDeviceSize offset,
2924 VkDeviceSize size,
2925 VkMemoryMapFlags flags,
2926 void** ppData)
2927 {
2928 RADV_FROM_HANDLE(radv_device, device, _device);
2929 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2930
2931 if (mem == NULL) {
2932 *ppData = NULL;
2933 return VK_SUCCESS;
2934 }
2935
2936 if (mem->user_ptr)
2937 *ppData = mem->user_ptr;
2938 else
2939 *ppData = device->ws->buffer_map(mem->bo);
2940
2941 if (*ppData) {
2942 *ppData += offset;
2943 return VK_SUCCESS;
2944 }
2945
2946 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2947 }
2948
2949 void radv_UnmapMemory(
2950 VkDevice _device,
2951 VkDeviceMemory _memory)
2952 {
2953 RADV_FROM_HANDLE(radv_device, device, _device);
2954 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2955
2956 if (mem == NULL)
2957 return;
2958
2959 if (mem->user_ptr == NULL)
2960 device->ws->buffer_unmap(mem->bo);
2961 }
2962
2963 VkResult radv_FlushMappedMemoryRanges(
2964 VkDevice _device,
2965 uint32_t memoryRangeCount,
2966 const VkMappedMemoryRange* pMemoryRanges)
2967 {
2968 return VK_SUCCESS;
2969 }
2970
2971 VkResult radv_InvalidateMappedMemoryRanges(
2972 VkDevice _device,
2973 uint32_t memoryRangeCount,
2974 const VkMappedMemoryRange* pMemoryRanges)
2975 {
2976 return VK_SUCCESS;
2977 }
2978
2979 void radv_GetBufferMemoryRequirements(
2980 VkDevice _device,
2981 VkBuffer _buffer,
2982 VkMemoryRequirements* pMemoryRequirements)
2983 {
2984 RADV_FROM_HANDLE(radv_device, device, _device);
2985 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2986
2987 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2988
2989 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2990 pMemoryRequirements->alignment = 4096;
2991 else
2992 pMemoryRequirements->alignment = 16;
2993
2994 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2995 }
2996
2997 void radv_GetBufferMemoryRequirements2(
2998 VkDevice device,
2999 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3000 VkMemoryRequirements2KHR* pMemoryRequirements)
3001 {
3002 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3003 &pMemoryRequirements->memoryRequirements);
3004 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3005 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3006 switch (ext->sType) {
3007 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3008 VkMemoryDedicatedRequirementsKHR *req =
3009 (VkMemoryDedicatedRequirementsKHR *) ext;
3010 req->requiresDedicatedAllocation = buffer->shareable;
3011 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3012 break;
3013 }
3014 default:
3015 break;
3016 }
3017 }
3018 }
3019
3020 void radv_GetImageMemoryRequirements(
3021 VkDevice _device,
3022 VkImage _image,
3023 VkMemoryRequirements* pMemoryRequirements)
3024 {
3025 RADV_FROM_HANDLE(radv_device, device, _device);
3026 RADV_FROM_HANDLE(radv_image, image, _image);
3027
3028 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3029
3030 pMemoryRequirements->size = image->size;
3031 pMemoryRequirements->alignment = image->alignment;
3032 }
3033
3034 void radv_GetImageMemoryRequirements2(
3035 VkDevice device,
3036 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3037 VkMemoryRequirements2KHR* pMemoryRequirements)
3038 {
3039 radv_GetImageMemoryRequirements(device, pInfo->image,
3040 &pMemoryRequirements->memoryRequirements);
3041
3042 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3043
3044 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3045 switch (ext->sType) {
3046 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3047 VkMemoryDedicatedRequirementsKHR *req =
3048 (VkMemoryDedicatedRequirementsKHR *) ext;
3049 req->requiresDedicatedAllocation = image->shareable;
3050 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3051 break;
3052 }
3053 default:
3054 break;
3055 }
3056 }
3057 }
3058
3059 void radv_GetImageSparseMemoryRequirements(
3060 VkDevice device,
3061 VkImage image,
3062 uint32_t* pSparseMemoryRequirementCount,
3063 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3064 {
3065 stub();
3066 }
3067
3068 void radv_GetImageSparseMemoryRequirements2(
3069 VkDevice device,
3070 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3071 uint32_t* pSparseMemoryRequirementCount,
3072 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3073 {
3074 stub();
3075 }
3076
3077 void radv_GetDeviceMemoryCommitment(
3078 VkDevice device,
3079 VkDeviceMemory memory,
3080 VkDeviceSize* pCommittedMemoryInBytes)
3081 {
3082 *pCommittedMemoryInBytes = 0;
3083 }
3084
3085 VkResult radv_BindBufferMemory2(VkDevice device,
3086 uint32_t bindInfoCount,
3087 const VkBindBufferMemoryInfoKHR *pBindInfos)
3088 {
3089 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3090 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3091 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3092
3093 if (mem) {
3094 buffer->bo = mem->bo;
3095 buffer->offset = pBindInfos[i].memoryOffset;
3096 } else {
3097 buffer->bo = NULL;
3098 }
3099 }
3100 return VK_SUCCESS;
3101 }
3102
3103 VkResult radv_BindBufferMemory(
3104 VkDevice device,
3105 VkBuffer buffer,
3106 VkDeviceMemory memory,
3107 VkDeviceSize memoryOffset)
3108 {
3109 const VkBindBufferMemoryInfoKHR info = {
3110 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3111 .buffer = buffer,
3112 .memory = memory,
3113 .memoryOffset = memoryOffset
3114 };
3115
3116 return radv_BindBufferMemory2(device, 1, &info);
3117 }
3118
3119 VkResult radv_BindImageMemory2(VkDevice device,
3120 uint32_t bindInfoCount,
3121 const VkBindImageMemoryInfoKHR *pBindInfos)
3122 {
3123 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3124 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3125 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3126
3127 if (mem) {
3128 image->bo = mem->bo;
3129 image->offset = pBindInfos[i].memoryOffset;
3130 } else {
3131 image->bo = NULL;
3132 image->offset = 0;
3133 }
3134 }
3135 return VK_SUCCESS;
3136 }
3137
3138
3139 VkResult radv_BindImageMemory(
3140 VkDevice device,
3141 VkImage image,
3142 VkDeviceMemory memory,
3143 VkDeviceSize memoryOffset)
3144 {
3145 const VkBindImageMemoryInfoKHR info = {
3146 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3147 .image = image,
3148 .memory = memory,
3149 .memoryOffset = memoryOffset
3150 };
3151
3152 return radv_BindImageMemory2(device, 1, &info);
3153 }
3154
3155
3156 static void
3157 radv_sparse_buffer_bind_memory(struct radv_device *device,
3158 const VkSparseBufferMemoryBindInfo *bind)
3159 {
3160 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3161
3162 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3163 struct radv_device_memory *mem = NULL;
3164
3165 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3166 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3167
3168 device->ws->buffer_virtual_bind(buffer->bo,
3169 bind->pBinds[i].resourceOffset,
3170 bind->pBinds[i].size,
3171 mem ? mem->bo : NULL,
3172 bind->pBinds[i].memoryOffset);
3173 }
3174 }
3175
3176 static void
3177 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3178 const VkSparseImageOpaqueMemoryBindInfo *bind)
3179 {
3180 RADV_FROM_HANDLE(radv_image, image, bind->image);
3181
3182 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3183 struct radv_device_memory *mem = NULL;
3184
3185 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3186 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3187
3188 device->ws->buffer_virtual_bind(image->bo,
3189 bind->pBinds[i].resourceOffset,
3190 bind->pBinds[i].size,
3191 mem ? mem->bo : NULL,
3192 bind->pBinds[i].memoryOffset);
3193 }
3194 }
3195
3196 VkResult radv_QueueBindSparse(
3197 VkQueue _queue,
3198 uint32_t bindInfoCount,
3199 const VkBindSparseInfo* pBindInfo,
3200 VkFence _fence)
3201 {
3202 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3203 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3204 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3205 bool fence_emitted = false;
3206 VkResult result;
3207 int ret;
3208
3209 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3210 struct radv_winsys_sem_info sem_info;
3211 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3212 radv_sparse_buffer_bind_memory(queue->device,
3213 pBindInfo[i].pBufferBinds + j);
3214 }
3215
3216 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3217 radv_sparse_image_opaque_bind_memory(queue->device,
3218 pBindInfo[i].pImageOpaqueBinds + j);
3219 }
3220
3221 VkResult result;
3222 result = radv_alloc_sem_info(queue->device->instance,
3223 &sem_info,
3224 pBindInfo[i].waitSemaphoreCount,
3225 pBindInfo[i].pWaitSemaphores,
3226 pBindInfo[i].signalSemaphoreCount,
3227 pBindInfo[i].pSignalSemaphores,
3228 _fence);
3229 if (result != VK_SUCCESS)
3230 return result;
3231
3232 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3233 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3234 &queue->device->empty_cs[queue->queue_family_index],
3235 1, NULL, NULL,
3236 &sem_info, NULL,
3237 false, base_fence);
3238 if (ret) {
3239 radv_loge("failed to submit CS %d\n", i);
3240 abort();
3241 }
3242
3243 fence_emitted = true;
3244 if (fence)
3245 fence->submitted = true;
3246 }
3247
3248 radv_free_sem_info(&sem_info);
3249
3250 }
3251
3252 if (fence) {
3253 if (!fence_emitted) {
3254 result = radv_signal_fence(queue, fence);
3255 if (result != VK_SUCCESS)
3256 return result;
3257 }
3258 fence->submitted = true;
3259 }
3260
3261 return VK_SUCCESS;
3262 }
3263
3264 VkResult radv_CreateFence(
3265 VkDevice _device,
3266 const VkFenceCreateInfo* pCreateInfo,
3267 const VkAllocationCallbacks* pAllocator,
3268 VkFence* pFence)
3269 {
3270 RADV_FROM_HANDLE(radv_device, device, _device);
3271 const VkExportFenceCreateInfoKHR *export =
3272 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3273 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3274 export ? export->handleTypes : 0;
3275
3276 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3277 sizeof(*fence), 8,
3278 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3279
3280 if (!fence)
3281 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3282
3283 fence->fence_wsi = NULL;
3284 fence->submitted = false;
3285 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3286 fence->temp_syncobj = 0;
3287 if (device->always_use_syncobj || handleTypes) {
3288 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3289 if (ret) {
3290 vk_free2(&device->alloc, pAllocator, fence);
3291 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3292 }
3293 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3294 device->ws->signal_syncobj(device->ws, fence->syncobj);
3295 }
3296 fence->fence = NULL;
3297 } else {
3298 fence->fence = device->ws->create_fence();
3299 if (!fence->fence) {
3300 vk_free2(&device->alloc, pAllocator, fence);
3301 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3302 }
3303 fence->syncobj = 0;
3304 }
3305
3306 *pFence = radv_fence_to_handle(fence);
3307
3308 return VK_SUCCESS;
3309 }
3310
3311 void radv_DestroyFence(
3312 VkDevice _device,
3313 VkFence _fence,
3314 const VkAllocationCallbacks* pAllocator)
3315 {
3316 RADV_FROM_HANDLE(radv_device, device, _device);
3317 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3318
3319 if (!fence)
3320 return;
3321
3322 if (fence->temp_syncobj)
3323 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3324 if (fence->syncobj)
3325 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3326 if (fence->fence)
3327 device->ws->destroy_fence(fence->fence);
3328 if (fence->fence_wsi)
3329 fence->fence_wsi->destroy(fence->fence_wsi);
3330 vk_free2(&device->alloc, pAllocator, fence);
3331 }
3332
3333
3334 static uint64_t radv_get_current_time()
3335 {
3336 struct timespec tv;
3337 clock_gettime(CLOCK_MONOTONIC, &tv);
3338 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3339 }
3340
3341 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3342 {
3343 uint64_t current_time = radv_get_current_time();
3344
3345 timeout = MIN2(UINT64_MAX - current_time, timeout);
3346
3347 return current_time + timeout;
3348 }
3349
3350
3351 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3352 {
3353 for (uint32_t i = 0; i < fenceCount; ++i) {
3354 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3355 if (fence->fence == NULL || fence->syncobj ||
3356 fence->temp_syncobj ||
3357 (!fence->signalled && !fence->submitted))
3358 return false;
3359 }
3360 return true;
3361 }
3362
3363 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3364 {
3365 for (uint32_t i = 0; i < fenceCount; ++i) {
3366 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3367 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3368 return false;
3369 }
3370 return true;
3371 }
3372
3373 VkResult radv_WaitForFences(
3374 VkDevice _device,
3375 uint32_t fenceCount,
3376 const VkFence* pFences,
3377 VkBool32 waitAll,
3378 uint64_t timeout)
3379 {
3380 RADV_FROM_HANDLE(radv_device, device, _device);
3381 timeout = radv_get_absolute_timeout(timeout);
3382
3383 if (device->always_use_syncobj &&
3384 radv_all_fences_syncobj(fenceCount, pFences))
3385 {
3386 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3387 if (!handles)
3388 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3389
3390 for (uint32_t i = 0; i < fenceCount; ++i) {
3391 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3392 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3393 }
3394
3395 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3396
3397 free(handles);
3398 return success ? VK_SUCCESS : VK_TIMEOUT;
3399 }
3400
3401 if (!waitAll && fenceCount > 1) {
3402 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3403 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3404 uint32_t wait_count = 0;
3405 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3406 if (!fences)
3407 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3408
3409 for (uint32_t i = 0; i < fenceCount; ++i) {
3410 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3411
3412 if (fence->signalled) {
3413 free(fences);
3414 return VK_SUCCESS;
3415 }
3416
3417 fences[wait_count++] = fence->fence;
3418 }
3419
3420 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3421 waitAll, timeout - radv_get_current_time());
3422
3423 free(fences);
3424 return success ? VK_SUCCESS : VK_TIMEOUT;
3425 }
3426
3427 while(radv_get_current_time() <= timeout) {
3428 for (uint32_t i = 0; i < fenceCount; ++i) {
3429 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3430 return VK_SUCCESS;
3431 }
3432 }
3433 return VK_TIMEOUT;
3434 }
3435
3436 for (uint32_t i = 0; i < fenceCount; ++i) {
3437 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3438 bool expired = false;
3439
3440 if (fence->temp_syncobj) {
3441 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3442 return VK_TIMEOUT;
3443 continue;
3444 }
3445
3446 if (fence->syncobj) {
3447 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3448 return VK_TIMEOUT;
3449 continue;
3450 }
3451
3452 if (fence->signalled)
3453 continue;
3454
3455 if (fence->fence) {
3456 if (!fence->submitted) {
3457 while(radv_get_current_time() <= timeout &&
3458 !fence->submitted)
3459 /* Do nothing */;
3460
3461 if (!fence->submitted)
3462 return VK_TIMEOUT;
3463
3464 /* Recheck as it may have been set by
3465 * submitting operations. */
3466
3467 if (fence->signalled)
3468 continue;
3469 }
3470
3471 expired = device->ws->fence_wait(device->ws,
3472 fence->fence,
3473 true, timeout);
3474 if (!expired)
3475 return VK_TIMEOUT;
3476 }
3477
3478 if (fence->fence_wsi) {
3479 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3480 if (result != VK_SUCCESS)
3481 return result;
3482 }
3483
3484 fence->signalled = true;
3485 }
3486
3487 return VK_SUCCESS;
3488 }
3489
3490 VkResult radv_ResetFences(VkDevice _device,
3491 uint32_t fenceCount,
3492 const VkFence *pFences)
3493 {
3494 RADV_FROM_HANDLE(radv_device, device, _device);
3495
3496 for (unsigned i = 0; i < fenceCount; ++i) {
3497 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3498 fence->submitted = fence->signalled = false;
3499
3500 /* Per spec, we first restore the permanent payload, and then reset, so
3501 * having a temp syncobj should not skip resetting the permanent syncobj. */
3502 if (fence->temp_syncobj) {
3503 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3504 fence->temp_syncobj = 0;
3505 }
3506
3507 if (fence->syncobj) {
3508 device->ws->reset_syncobj(device->ws, fence->syncobj);
3509 }
3510 }
3511
3512 return VK_SUCCESS;
3513 }
3514
3515 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3516 {
3517 RADV_FROM_HANDLE(radv_device, device, _device);
3518 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3519
3520 if (fence->temp_syncobj) {
3521 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3522 return success ? VK_SUCCESS : VK_NOT_READY;
3523 }
3524
3525 if (fence->syncobj) {
3526 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3527 return success ? VK_SUCCESS : VK_NOT_READY;
3528 }
3529
3530 if (fence->signalled)
3531 return VK_SUCCESS;
3532 if (!fence->submitted)
3533 return VK_NOT_READY;
3534 if (fence->fence) {
3535 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3536 return VK_NOT_READY;
3537 }
3538 if (fence->fence_wsi) {
3539 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3540
3541 if (result != VK_SUCCESS) {
3542 if (result == VK_TIMEOUT)
3543 return VK_NOT_READY;
3544 return result;
3545 }
3546 }
3547 return VK_SUCCESS;
3548 }
3549
3550
3551 // Queue semaphore functions
3552
3553 VkResult radv_CreateSemaphore(
3554 VkDevice _device,
3555 const VkSemaphoreCreateInfo* pCreateInfo,
3556 const VkAllocationCallbacks* pAllocator,
3557 VkSemaphore* pSemaphore)
3558 {
3559 RADV_FROM_HANDLE(radv_device, device, _device);
3560 const VkExportSemaphoreCreateInfoKHR *export =
3561 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3562 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3563 export ? export->handleTypes : 0;
3564
3565 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3566 sizeof(*sem), 8,
3567 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3568 if (!sem)
3569 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3570
3571 sem->temp_syncobj = 0;
3572 /* create a syncobject if we are going to export this semaphore */
3573 if (device->always_use_syncobj || handleTypes) {
3574 assert (device->physical_device->rad_info.has_syncobj);
3575 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3576 if (ret) {
3577 vk_free2(&device->alloc, pAllocator, sem);
3578 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3579 }
3580 sem->sem = NULL;
3581 } else {
3582 sem->sem = device->ws->create_sem(device->ws);
3583 if (!sem->sem) {
3584 vk_free2(&device->alloc, pAllocator, sem);
3585 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3586 }
3587 sem->syncobj = 0;
3588 }
3589
3590 *pSemaphore = radv_semaphore_to_handle(sem);
3591 return VK_SUCCESS;
3592 }
3593
3594 void radv_DestroySemaphore(
3595 VkDevice _device,
3596 VkSemaphore _semaphore,
3597 const VkAllocationCallbacks* pAllocator)
3598 {
3599 RADV_FROM_HANDLE(radv_device, device, _device);
3600 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3601 if (!_semaphore)
3602 return;
3603
3604 if (sem->syncobj)
3605 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3606 else
3607 device->ws->destroy_sem(sem->sem);
3608 vk_free2(&device->alloc, pAllocator, sem);
3609 }
3610
3611 VkResult radv_CreateEvent(
3612 VkDevice _device,
3613 const VkEventCreateInfo* pCreateInfo,
3614 const VkAllocationCallbacks* pAllocator,
3615 VkEvent* pEvent)
3616 {
3617 RADV_FROM_HANDLE(radv_device, device, _device);
3618 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3619 sizeof(*event), 8,
3620 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3621
3622 if (!event)
3623 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3624
3625 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3626 RADEON_DOMAIN_GTT,
3627 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3628 if (!event->bo) {
3629 vk_free2(&device->alloc, pAllocator, event);
3630 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3631 }
3632
3633 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3634
3635 *pEvent = radv_event_to_handle(event);
3636
3637 return VK_SUCCESS;
3638 }
3639
3640 void radv_DestroyEvent(
3641 VkDevice _device,
3642 VkEvent _event,
3643 const VkAllocationCallbacks* pAllocator)
3644 {
3645 RADV_FROM_HANDLE(radv_device, device, _device);
3646 RADV_FROM_HANDLE(radv_event, event, _event);
3647
3648 if (!event)
3649 return;
3650 device->ws->buffer_destroy(event->bo);
3651 vk_free2(&device->alloc, pAllocator, event);
3652 }
3653
3654 VkResult radv_GetEventStatus(
3655 VkDevice _device,
3656 VkEvent _event)
3657 {
3658 RADV_FROM_HANDLE(radv_event, event, _event);
3659
3660 if (*event->map == 1)
3661 return VK_EVENT_SET;
3662 return VK_EVENT_RESET;
3663 }
3664
3665 VkResult radv_SetEvent(
3666 VkDevice _device,
3667 VkEvent _event)
3668 {
3669 RADV_FROM_HANDLE(radv_event, event, _event);
3670 *event->map = 1;
3671
3672 return VK_SUCCESS;
3673 }
3674
3675 VkResult radv_ResetEvent(
3676 VkDevice _device,
3677 VkEvent _event)
3678 {
3679 RADV_FROM_HANDLE(radv_event, event, _event);
3680 *event->map = 0;
3681
3682 return VK_SUCCESS;
3683 }
3684
3685 VkResult radv_CreateBuffer(
3686 VkDevice _device,
3687 const VkBufferCreateInfo* pCreateInfo,
3688 const VkAllocationCallbacks* pAllocator,
3689 VkBuffer* pBuffer)
3690 {
3691 RADV_FROM_HANDLE(radv_device, device, _device);
3692 struct radv_buffer *buffer;
3693
3694 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3695
3696 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3697 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3698 if (buffer == NULL)
3699 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3700
3701 buffer->size = pCreateInfo->size;
3702 buffer->usage = pCreateInfo->usage;
3703 buffer->bo = NULL;
3704 buffer->offset = 0;
3705 buffer->flags = pCreateInfo->flags;
3706
3707 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3708 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3709
3710 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3711 buffer->bo = device->ws->buffer_create(device->ws,
3712 align64(buffer->size, 4096),
3713 4096, 0, RADEON_FLAG_VIRTUAL);
3714 if (!buffer->bo) {
3715 vk_free2(&device->alloc, pAllocator, buffer);
3716 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3717 }
3718 }
3719
3720 *pBuffer = radv_buffer_to_handle(buffer);
3721
3722 return VK_SUCCESS;
3723 }
3724
3725 void radv_DestroyBuffer(
3726 VkDevice _device,
3727 VkBuffer _buffer,
3728 const VkAllocationCallbacks* pAllocator)
3729 {
3730 RADV_FROM_HANDLE(radv_device, device, _device);
3731 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3732
3733 if (!buffer)
3734 return;
3735
3736 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3737 device->ws->buffer_destroy(buffer->bo);
3738
3739 vk_free2(&device->alloc, pAllocator, buffer);
3740 }
3741
3742 static inline unsigned
3743 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3744 {
3745 if (stencil)
3746 return image->surface.u.legacy.stencil_tiling_index[level];
3747 else
3748 return image->surface.u.legacy.tiling_index[level];
3749 }
3750
3751 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3752 {
3753 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3754 }
3755
3756 static uint32_t
3757 radv_init_dcc_control_reg(struct radv_device *device,
3758 struct radv_image_view *iview)
3759 {
3760 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3761 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3762 unsigned max_compressed_block_size;
3763 unsigned independent_64b_blocks;
3764
3765 if (device->physical_device->rad_info.chip_class < VI)
3766 return 0;
3767
3768 if (iview->image->info.samples > 1) {
3769 if (iview->image->surface.bpe == 1)
3770 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3771 else if (iview->image->surface.bpe == 2)
3772 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3773 }
3774
3775 if (!device->physical_device->rad_info.has_dedicated_vram) {
3776 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3777 * dGPU and 64 for APU because all of our APUs to date use
3778 * DIMMs which have a request granularity size of 64B while all
3779 * other chips have a 32B request size.
3780 */
3781 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3782 }
3783
3784 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3785 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3786 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3787 /* If this DCC image is potentially going to be used in texture
3788 * fetches, we need some special settings.
3789 */
3790 independent_64b_blocks = 1;
3791 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3792 } else {
3793 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3794 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3795 * big as possible for better compression state.
3796 */
3797 independent_64b_blocks = 0;
3798 max_compressed_block_size = max_uncompressed_block_size;
3799 }
3800
3801 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3802 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3803 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3804 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3805 }
3806
3807 static void
3808 radv_initialise_color_surface(struct radv_device *device,
3809 struct radv_color_buffer_info *cb,
3810 struct radv_image_view *iview)
3811 {
3812 const struct vk_format_description *desc;
3813 unsigned ntype, format, swap, endian;
3814 unsigned blend_clamp = 0, blend_bypass = 0;
3815 uint64_t va;
3816 const struct radeon_surf *surf = &iview->image->surface;
3817
3818 desc = vk_format_description(iview->vk_format);
3819
3820 memset(cb, 0, sizeof(*cb));
3821
3822 /* Intensity is implemented as Red, so treat it that way. */
3823 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3824
3825 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3826
3827 cb->cb_color_base = va >> 8;
3828
3829 if (device->physical_device->rad_info.chip_class >= GFX9) {
3830 struct gfx9_surf_meta_flags meta;
3831 if (iview->image->dcc_offset)
3832 meta = iview->image->surface.u.gfx9.dcc;
3833 else
3834 meta = iview->image->surface.u.gfx9.cmask;
3835
3836 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3837 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3838 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3839 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3840
3841 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3842 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3843 } else {
3844 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3845 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3846
3847 cb->cb_color_base += level_info->offset >> 8;
3848 if (level_info->mode == RADEON_SURF_MODE_2D)
3849 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3850
3851 pitch_tile_max = level_info->nblk_x / 8 - 1;
3852 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3853 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3854
3855 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3856 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3857 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3858
3859 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3860
3861 if (radv_image_has_fmask(iview->image)) {
3862 if (device->physical_device->rad_info.chip_class >= CIK)
3863 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3864 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3865 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3866 } else {
3867 /* This must be set for fast clear to work without FMASK. */
3868 if (device->physical_device->rad_info.chip_class >= CIK)
3869 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3870 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3871 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3872 }
3873 }
3874
3875 /* CMASK variables */
3876 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3877 va += iview->image->cmask.offset;
3878 cb->cb_color_cmask = va >> 8;
3879
3880 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3881 va += iview->image->dcc_offset;
3882 cb->cb_dcc_base = va >> 8;
3883 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3884
3885 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3886 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3887 S_028C6C_SLICE_MAX(max_slice);
3888
3889 if (iview->image->info.samples > 1) {
3890 unsigned log_samples = util_logbase2(iview->image->info.samples);
3891
3892 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3893 S_028C74_NUM_FRAGMENTS(log_samples);
3894 }
3895
3896 if (radv_image_has_fmask(iview->image)) {
3897 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3898 cb->cb_color_fmask = va >> 8;
3899 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3900 } else {
3901 cb->cb_color_fmask = cb->cb_color_base;
3902 }
3903
3904 ntype = radv_translate_color_numformat(iview->vk_format,
3905 desc,
3906 vk_format_get_first_non_void_channel(iview->vk_format));
3907 format = radv_translate_colorformat(iview->vk_format);
3908 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3909 radv_finishme("Illegal color\n");
3910 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3911 endian = radv_colorformat_endian_swap(format);
3912
3913 /* blend clamp should be set for all NORM/SRGB types */
3914 if (ntype == V_028C70_NUMBER_UNORM ||
3915 ntype == V_028C70_NUMBER_SNORM ||
3916 ntype == V_028C70_NUMBER_SRGB)
3917 blend_clamp = 1;
3918
3919 /* set blend bypass according to docs if SINT/UINT or
3920 8/24 COLOR variants */
3921 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3922 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3923 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3924 blend_clamp = 0;
3925 blend_bypass = 1;
3926 }
3927 #if 0
3928 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3929 (format == V_028C70_COLOR_8 ||
3930 format == V_028C70_COLOR_8_8 ||
3931 format == V_028C70_COLOR_8_8_8_8))
3932 ->color_is_int8 = true;
3933 #endif
3934 cb->cb_color_info = S_028C70_FORMAT(format) |
3935 S_028C70_COMP_SWAP(swap) |
3936 S_028C70_BLEND_CLAMP(blend_clamp) |
3937 S_028C70_BLEND_BYPASS(blend_bypass) |
3938 S_028C70_SIMPLE_FLOAT(1) |
3939 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3940 ntype != V_028C70_NUMBER_SNORM &&
3941 ntype != V_028C70_NUMBER_SRGB &&
3942 format != V_028C70_COLOR_8_24 &&
3943 format != V_028C70_COLOR_24_8) |
3944 S_028C70_NUMBER_TYPE(ntype) |
3945 S_028C70_ENDIAN(endian);
3946 if (radv_image_has_fmask(iview->image)) {
3947 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3948 if (device->physical_device->rad_info.chip_class == SI) {
3949 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3950 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3951 }
3952 }
3953
3954 if (radv_image_has_cmask(iview->image) &&
3955 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3956 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3957
3958 if (radv_dcc_enabled(iview->image, iview->base_mip))
3959 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3960
3961 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3962
3963 /* This must be set for fast clear to work without FMASK. */
3964 if (!radv_image_has_fmask(iview->image) &&
3965 device->physical_device->rad_info.chip_class == SI) {
3966 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3967 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3968 }
3969
3970 if (device->physical_device->rad_info.chip_class >= GFX9) {
3971 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3972 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3973
3974 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3975 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3976 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3977 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3978 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3979 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3980 }
3981 }
3982
3983 static unsigned
3984 radv_calc_decompress_on_z_planes(struct radv_device *device,
3985 struct radv_image_view *iview)
3986 {
3987 unsigned max_zplanes = 0;
3988
3989 assert(radv_image_is_tc_compat_htile(iview->image));
3990
3991 if (device->physical_device->rad_info.chip_class >= GFX9) {
3992 /* Default value for 32-bit depth surfaces. */
3993 max_zplanes = 4;
3994
3995 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3996 iview->image->info.samples > 1)
3997 max_zplanes = 2;
3998
3999 max_zplanes = max_zplanes + 1;
4000 } else {
4001 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4002 /* Do not enable Z plane compression for 16-bit depth
4003 * surfaces because isn't supported on GFX8. Only
4004 * 32-bit depth surfaces are supported by the hardware.
4005 * This allows to maintain shader compatibility and to
4006 * reduce the number of depth decompressions.
4007 */
4008 max_zplanes = 1;
4009 } else {
4010 if (iview->image->info.samples <= 1)
4011 max_zplanes = 5;
4012 else if (iview->image->info.samples <= 4)
4013 max_zplanes = 3;
4014 else
4015 max_zplanes = 2;
4016 }
4017 }
4018
4019 return max_zplanes;
4020 }
4021
4022 static void
4023 radv_initialise_ds_surface(struct radv_device *device,
4024 struct radv_ds_buffer_info *ds,
4025 struct radv_image_view *iview)
4026 {
4027 unsigned level = iview->base_mip;
4028 unsigned format, stencil_format;
4029 uint64_t va, s_offs, z_offs;
4030 bool stencil_only = false;
4031 memset(ds, 0, sizeof(*ds));
4032 switch (iview->image->vk_format) {
4033 case VK_FORMAT_D24_UNORM_S8_UINT:
4034 case VK_FORMAT_X8_D24_UNORM_PACK32:
4035 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4036 ds->offset_scale = 2.0f;
4037 break;
4038 case VK_FORMAT_D16_UNORM:
4039 case VK_FORMAT_D16_UNORM_S8_UINT:
4040 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4041 ds->offset_scale = 4.0f;
4042 break;
4043 case VK_FORMAT_D32_SFLOAT:
4044 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4045 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4046 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4047 ds->offset_scale = 1.0f;
4048 break;
4049 case VK_FORMAT_S8_UINT:
4050 stencil_only = true;
4051 break;
4052 default:
4053 break;
4054 }
4055
4056 format = radv_translate_dbformat(iview->image->vk_format);
4057 stencil_format = iview->image->surface.has_stencil ?
4058 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4059
4060 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4061 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4062 S_028008_SLICE_MAX(max_slice);
4063
4064 ds->db_htile_data_base = 0;
4065 ds->db_htile_surface = 0;
4066
4067 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4068 s_offs = z_offs = va;
4069
4070 if (device->physical_device->rad_info.chip_class >= GFX9) {
4071 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4072 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4073
4074 ds->db_z_info = S_028038_FORMAT(format) |
4075 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4076 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4077 S_028038_MAXMIP(iview->image->info.levels - 1) |
4078 S_028038_ZRANGE_PRECISION(1);
4079 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4080 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4081
4082 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4083 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4084 ds->db_depth_view |= S_028008_MIPID(level);
4085
4086 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4087 S_02801C_Y_MAX(iview->image->info.height - 1);
4088
4089 if (radv_htile_enabled(iview->image, level)) {
4090 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4091
4092 if (radv_image_is_tc_compat_htile(iview->image)) {
4093 unsigned max_zplanes =
4094 radv_calc_decompress_on_z_planes(device, iview);
4095
4096 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4097 S_028038_ITERATE_FLUSH(1);
4098 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4099 }
4100
4101 if (!iview->image->surface.has_stencil)
4102 /* Use all of the htile_buffer for depth if there's no stencil. */
4103 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4104 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4105 iview->image->htile_offset;
4106 ds->db_htile_data_base = va >> 8;
4107 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4108 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4109 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4110 }
4111 } else {
4112 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4113
4114 if (stencil_only)
4115 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4116
4117 z_offs += iview->image->surface.u.legacy.level[level].offset;
4118 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4119
4120 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4121 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4122 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4123
4124 if (iview->image->info.samples > 1)
4125 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4126
4127 if (device->physical_device->rad_info.chip_class >= CIK) {
4128 struct radeon_info *info = &device->physical_device->rad_info;
4129 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4130 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4131 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4132 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4133 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4134 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4135
4136 if (stencil_only)
4137 tile_mode = stencil_tile_mode;
4138
4139 ds->db_depth_info |=
4140 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4141 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4142 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4143 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4144 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4145 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4146 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4147 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4148 } else {
4149 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4150 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4151 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4152 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4153 if (stencil_only)
4154 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4155 }
4156
4157 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4158 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4159 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4160
4161 if (radv_htile_enabled(iview->image, level)) {
4162 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4163
4164 if (!iview->image->surface.has_stencil &&
4165 !radv_image_is_tc_compat_htile(iview->image))
4166 /* Use all of the htile_buffer for depth if there's no stencil. */
4167 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4168
4169 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4170 iview->image->htile_offset;
4171 ds->db_htile_data_base = va >> 8;
4172 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4173
4174 if (radv_image_is_tc_compat_htile(iview->image)) {
4175 unsigned max_zplanes =
4176 radv_calc_decompress_on_z_planes(device, iview);
4177
4178 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4179 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4180 }
4181 }
4182 }
4183
4184 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4185 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4186 }
4187
4188 VkResult radv_CreateFramebuffer(
4189 VkDevice _device,
4190 const VkFramebufferCreateInfo* pCreateInfo,
4191 const VkAllocationCallbacks* pAllocator,
4192 VkFramebuffer* pFramebuffer)
4193 {
4194 RADV_FROM_HANDLE(radv_device, device, _device);
4195 struct radv_framebuffer *framebuffer;
4196
4197 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4198
4199 size_t size = sizeof(*framebuffer) +
4200 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4201 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4202 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4203 if (framebuffer == NULL)
4204 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4205
4206 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4207 framebuffer->width = pCreateInfo->width;
4208 framebuffer->height = pCreateInfo->height;
4209 framebuffer->layers = pCreateInfo->layers;
4210 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4211 VkImageView _iview = pCreateInfo->pAttachments[i];
4212 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4213 framebuffer->attachments[i].attachment = iview;
4214 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4215 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4216 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4217 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4218 }
4219 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4220 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4221 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4222 }
4223
4224 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4225 return VK_SUCCESS;
4226 }
4227
4228 void radv_DestroyFramebuffer(
4229 VkDevice _device,
4230 VkFramebuffer _fb,
4231 const VkAllocationCallbacks* pAllocator)
4232 {
4233 RADV_FROM_HANDLE(radv_device, device, _device);
4234 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4235
4236 if (!fb)
4237 return;
4238 vk_free2(&device->alloc, pAllocator, fb);
4239 }
4240
4241 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4242 {
4243 switch (address_mode) {
4244 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4245 return V_008F30_SQ_TEX_WRAP;
4246 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4247 return V_008F30_SQ_TEX_MIRROR;
4248 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4249 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4250 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4251 return V_008F30_SQ_TEX_CLAMP_BORDER;
4252 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4253 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4254 default:
4255 unreachable("illegal tex wrap mode");
4256 break;
4257 }
4258 }
4259
4260 static unsigned
4261 radv_tex_compare(VkCompareOp op)
4262 {
4263 switch (op) {
4264 case VK_COMPARE_OP_NEVER:
4265 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4266 case VK_COMPARE_OP_LESS:
4267 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4268 case VK_COMPARE_OP_EQUAL:
4269 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4270 case VK_COMPARE_OP_LESS_OR_EQUAL:
4271 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4272 case VK_COMPARE_OP_GREATER:
4273 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4274 case VK_COMPARE_OP_NOT_EQUAL:
4275 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4276 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4277 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4278 case VK_COMPARE_OP_ALWAYS:
4279 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4280 default:
4281 unreachable("illegal compare mode");
4282 break;
4283 }
4284 }
4285
4286 static unsigned
4287 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4288 {
4289 switch (filter) {
4290 case VK_FILTER_NEAREST:
4291 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4292 V_008F38_SQ_TEX_XY_FILTER_POINT);
4293 case VK_FILTER_LINEAR:
4294 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4295 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4296 case VK_FILTER_CUBIC_IMG:
4297 default:
4298 fprintf(stderr, "illegal texture filter");
4299 return 0;
4300 }
4301 }
4302
4303 static unsigned
4304 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4305 {
4306 switch (mode) {
4307 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4308 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4309 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4310 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4311 default:
4312 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4313 }
4314 }
4315
4316 static unsigned
4317 radv_tex_bordercolor(VkBorderColor bcolor)
4318 {
4319 switch (bcolor) {
4320 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4321 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4322 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4323 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4324 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4325 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4326 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4327 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4328 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4329 default:
4330 break;
4331 }
4332 return 0;
4333 }
4334
4335 static unsigned
4336 radv_tex_aniso_filter(unsigned filter)
4337 {
4338 if (filter < 2)
4339 return 0;
4340 if (filter < 4)
4341 return 1;
4342 if (filter < 8)
4343 return 2;
4344 if (filter < 16)
4345 return 3;
4346 return 4;
4347 }
4348
4349 static unsigned
4350 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4351 {
4352 switch (mode) {
4353 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4354 return SQ_IMG_FILTER_MODE_BLEND;
4355 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4356 return SQ_IMG_FILTER_MODE_MIN;
4357 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4358 return SQ_IMG_FILTER_MODE_MAX;
4359 default:
4360 break;
4361 }
4362 return 0;
4363 }
4364
4365 static void
4366 radv_init_sampler(struct radv_device *device,
4367 struct radv_sampler *sampler,
4368 const VkSamplerCreateInfo *pCreateInfo)
4369 {
4370 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4371 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4372 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4373 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4374 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4375
4376 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4377 vk_find_struct_const(pCreateInfo->pNext,
4378 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4379 if (sampler_reduction)
4380 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4381
4382 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4383 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4384 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4385 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4386 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4387 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4388 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4389 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4390 S_008F30_DISABLE_CUBE_WRAP(0) |
4391 S_008F30_COMPAT_MODE(is_vi) |
4392 S_008F30_FILTER_MODE(filter_mode));
4393 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4394 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4395 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4396 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4397 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4398 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4399 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4400 S_008F38_MIP_POINT_PRECLAMP(0) |
4401 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4402 S_008F38_FILTER_PREC_FIX(1) |
4403 S_008F38_ANISO_OVERRIDE(is_vi));
4404 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4405 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4406 }
4407
4408 VkResult radv_CreateSampler(
4409 VkDevice _device,
4410 const VkSamplerCreateInfo* pCreateInfo,
4411 const VkAllocationCallbacks* pAllocator,
4412 VkSampler* pSampler)
4413 {
4414 RADV_FROM_HANDLE(radv_device, device, _device);
4415 struct radv_sampler *sampler;
4416
4417 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4418
4419 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4420 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4421 if (!sampler)
4422 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4423
4424 radv_init_sampler(device, sampler, pCreateInfo);
4425 *pSampler = radv_sampler_to_handle(sampler);
4426
4427 return VK_SUCCESS;
4428 }
4429
4430 void radv_DestroySampler(
4431 VkDevice _device,
4432 VkSampler _sampler,
4433 const VkAllocationCallbacks* pAllocator)
4434 {
4435 RADV_FROM_HANDLE(radv_device, device, _device);
4436 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4437
4438 if (!sampler)
4439 return;
4440 vk_free2(&device->alloc, pAllocator, sampler);
4441 }
4442
4443 /* vk_icd.h does not declare this function, so we declare it here to
4444 * suppress Wmissing-prototypes.
4445 */
4446 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4447 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4448
4449 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4450 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4451 {
4452 /* For the full details on loader interface versioning, see
4453 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4454 * What follows is a condensed summary, to help you navigate the large and
4455 * confusing official doc.
4456 *
4457 * - Loader interface v0 is incompatible with later versions. We don't
4458 * support it.
4459 *
4460 * - In loader interface v1:
4461 * - The first ICD entrypoint called by the loader is
4462 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4463 * entrypoint.
4464 * - The ICD must statically expose no other Vulkan symbol unless it is
4465 * linked with -Bsymbolic.
4466 * - Each dispatchable Vulkan handle created by the ICD must be
4467 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4468 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4469 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4470 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4471 * such loader-managed surfaces.
4472 *
4473 * - Loader interface v2 differs from v1 in:
4474 * - The first ICD entrypoint called by the loader is
4475 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4476 * statically expose this entrypoint.
4477 *
4478 * - Loader interface v3 differs from v2 in:
4479 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4480 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4481 * because the loader no longer does so.
4482 */
4483 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4484 return VK_SUCCESS;
4485 }
4486
4487 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4488 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4489 int *pFD)
4490 {
4491 RADV_FROM_HANDLE(radv_device, device, _device);
4492 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4493
4494 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4495
4496 /* At the moment, we support only the below handle types. */
4497 assert(pGetFdInfo->handleType ==
4498 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4499 pGetFdInfo->handleType ==
4500 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4501
4502 bool ret = radv_get_memory_fd(device, memory, pFD);
4503 if (ret == false)
4504 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4505 return VK_SUCCESS;
4506 }
4507
4508 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4509 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4510 int fd,
4511 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4512 {
4513 RADV_FROM_HANDLE(radv_device, device, _device);
4514
4515 switch (handleType) {
4516 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4517 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4518 return VK_SUCCESS;
4519
4520 default:
4521 /* The valid usage section for this function says:
4522 *
4523 * "handleType must not be one of the handle types defined as
4524 * opaque."
4525 *
4526 * So opaque handle types fall into the default "unsupported" case.
4527 */
4528 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4529 }
4530 }
4531
4532 static VkResult radv_import_opaque_fd(struct radv_device *device,
4533 int fd,
4534 uint32_t *syncobj)
4535 {
4536 uint32_t syncobj_handle = 0;
4537 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4538 if (ret != 0)
4539 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4540
4541 if (*syncobj)
4542 device->ws->destroy_syncobj(device->ws, *syncobj);
4543
4544 *syncobj = syncobj_handle;
4545 close(fd);
4546
4547 return VK_SUCCESS;
4548 }
4549
4550 static VkResult radv_import_sync_fd(struct radv_device *device,
4551 int fd,
4552 uint32_t *syncobj)
4553 {
4554 /* If we create a syncobj we do it locally so that if we have an error, we don't
4555 * leave a syncobj in an undetermined state in the fence. */
4556 uint32_t syncobj_handle = *syncobj;
4557 if (!syncobj_handle) {
4558 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4559 if (ret) {
4560 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4561 }
4562 }
4563
4564 if (fd == -1) {
4565 device->ws->signal_syncobj(device->ws, syncobj_handle);
4566 } else {
4567 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4568 if (ret != 0)
4569 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4570 }
4571
4572 *syncobj = syncobj_handle;
4573 if (fd != -1)
4574 close(fd);
4575
4576 return VK_SUCCESS;
4577 }
4578
4579 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4580 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4581 {
4582 RADV_FROM_HANDLE(radv_device, device, _device);
4583 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4584 uint32_t *syncobj_dst = NULL;
4585
4586 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4587 syncobj_dst = &sem->temp_syncobj;
4588 } else {
4589 syncobj_dst = &sem->syncobj;
4590 }
4591
4592 switch(pImportSemaphoreFdInfo->handleType) {
4593 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4594 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4595 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4596 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4597 default:
4598 unreachable("Unhandled semaphore handle type");
4599 }
4600 }
4601
4602 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4603 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4604 int *pFd)
4605 {
4606 RADV_FROM_HANDLE(radv_device, device, _device);
4607 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4608 int ret;
4609 uint32_t syncobj_handle;
4610
4611 if (sem->temp_syncobj)
4612 syncobj_handle = sem->temp_syncobj;
4613 else
4614 syncobj_handle = sem->syncobj;
4615
4616 switch(pGetFdInfo->handleType) {
4617 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4618 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4619 break;
4620 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4621 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4622 if (!ret) {
4623 if (sem->temp_syncobj) {
4624 close (sem->temp_syncobj);
4625 sem->temp_syncobj = 0;
4626 } else {
4627 device->ws->reset_syncobj(device->ws, syncobj_handle);
4628 }
4629 }
4630 break;
4631 default:
4632 unreachable("Unhandled semaphore handle type");
4633 }
4634
4635 if (ret)
4636 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4637 return VK_SUCCESS;
4638 }
4639
4640 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4641 VkPhysicalDevice physicalDevice,
4642 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4643 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4644 {
4645 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4646
4647 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4648 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4649 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4650 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4651 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4652 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4653 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4654 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4655 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4656 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4657 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4658 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4659 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4660 } else {
4661 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4662 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4663 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4664 }
4665 }
4666
4667 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4668 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4669 {
4670 RADV_FROM_HANDLE(radv_device, device, _device);
4671 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4672 uint32_t *syncobj_dst = NULL;
4673
4674
4675 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4676 syncobj_dst = &fence->temp_syncobj;
4677 } else {
4678 syncobj_dst = &fence->syncobj;
4679 }
4680
4681 switch(pImportFenceFdInfo->handleType) {
4682 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4683 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4684 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4685 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4686 default:
4687 unreachable("Unhandled fence handle type");
4688 }
4689 }
4690
4691 VkResult radv_GetFenceFdKHR(VkDevice _device,
4692 const VkFenceGetFdInfoKHR *pGetFdInfo,
4693 int *pFd)
4694 {
4695 RADV_FROM_HANDLE(radv_device, device, _device);
4696 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4697 int ret;
4698 uint32_t syncobj_handle;
4699
4700 if (fence->temp_syncobj)
4701 syncobj_handle = fence->temp_syncobj;
4702 else
4703 syncobj_handle = fence->syncobj;
4704
4705 switch(pGetFdInfo->handleType) {
4706 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4707 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4708 break;
4709 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4710 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4711 if (!ret) {
4712 if (fence->temp_syncobj) {
4713 close (fence->temp_syncobj);
4714 fence->temp_syncobj = 0;
4715 } else {
4716 device->ws->reset_syncobj(device->ws, syncobj_handle);
4717 }
4718 }
4719 break;
4720 default:
4721 unreachable("Unhandled fence handle type");
4722 }
4723
4724 if (ret)
4725 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4726 return VK_SUCCESS;
4727 }
4728
4729 void radv_GetPhysicalDeviceExternalFenceProperties(
4730 VkPhysicalDevice physicalDevice,
4731 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4732 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4733 {
4734 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4735
4736 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4737 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4738 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4739 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4740 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4741 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4742 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4743 } else {
4744 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4745 pExternalFenceProperties->compatibleHandleTypes = 0;
4746 pExternalFenceProperties->externalFenceFeatures = 0;
4747 }
4748 }
4749
4750 VkResult
4751 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4752 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4753 const VkAllocationCallbacks* pAllocator,
4754 VkDebugReportCallbackEXT* pCallback)
4755 {
4756 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4757 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4758 pCreateInfo, pAllocator, &instance->alloc,
4759 pCallback);
4760 }
4761
4762 void
4763 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4764 VkDebugReportCallbackEXT _callback,
4765 const VkAllocationCallbacks* pAllocator)
4766 {
4767 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4768 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4769 _callback, pAllocator, &instance->alloc);
4770 }
4771
4772 void
4773 radv_DebugReportMessageEXT(VkInstance _instance,
4774 VkDebugReportFlagsEXT flags,
4775 VkDebugReportObjectTypeEXT objectType,
4776 uint64_t object,
4777 size_t location,
4778 int32_t messageCode,
4779 const char* pLayerPrefix,
4780 const char* pMessage)
4781 {
4782 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4783 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4784 object, location, messageCode, pLayerPrefix, pMessage);
4785 }
4786
4787 void
4788 radv_GetDeviceGroupPeerMemoryFeatures(
4789 VkDevice device,
4790 uint32_t heapIndex,
4791 uint32_t localDeviceIndex,
4792 uint32_t remoteDeviceIndex,
4793 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4794 {
4795 assert(localDeviceIndex == remoteDeviceIndex);
4796
4797 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4798 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4799 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4800 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4801 }