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radv: Enable VK_EXT_memory_priority.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 radv_physical_device_init_mem_types(device);
373 radv_fill_device_extension_table(device, &device->supported_extensions);
374
375 device->bus_info = *drm_device->businfo.pci;
376
377 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
378 ac_print_gpu_info(&device->rad_info);
379
380 /* The WSI is structured as a layer on top of the driver, so this has
381 * to be the last part of initialization (at least until we get other
382 * semi-layers).
383 */
384 result = radv_init_wsi(device);
385 if (result != VK_SUCCESS) {
386 device->ws->destroy(device->ws);
387 vk_error(instance, result);
388 goto fail;
389 }
390
391 return VK_SUCCESS;
392
393 fail:
394 close(fd);
395 if (master_fd != -1)
396 close(master_fd);
397 return result;
398 }
399
400 static void
401 radv_physical_device_finish(struct radv_physical_device *device)
402 {
403 radv_finish_wsi(device);
404 device->ws->destroy(device->ws);
405 disk_cache_destroy(device->disk_cache);
406 close(device->local_fd);
407 if (device->master_fd != -1)
408 close(device->master_fd);
409 }
410
411 static void *
412 default_alloc_func(void *pUserData, size_t size, size_t align,
413 VkSystemAllocationScope allocationScope)
414 {
415 return malloc(size);
416 }
417
418 static void *
419 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
420 size_t align, VkSystemAllocationScope allocationScope)
421 {
422 return realloc(pOriginal, size);
423 }
424
425 static void
426 default_free_func(void *pUserData, void *pMemory)
427 {
428 free(pMemory);
429 }
430
431 static const VkAllocationCallbacks default_alloc = {
432 .pUserData = NULL,
433 .pfnAllocation = default_alloc_func,
434 .pfnReallocation = default_realloc_func,
435 .pfnFree = default_free_func,
436 };
437
438 static const struct debug_control radv_debug_options[] = {
439 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
440 {"nodcc", RADV_DEBUG_NO_DCC},
441 {"shaders", RADV_DEBUG_DUMP_SHADERS},
442 {"nocache", RADV_DEBUG_NO_CACHE},
443 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
444 {"nohiz", RADV_DEBUG_NO_HIZ},
445 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
446 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
447 {"allbos", RADV_DEBUG_ALL_BOS},
448 {"noibs", RADV_DEBUG_NO_IBS},
449 {"spirv", RADV_DEBUG_DUMP_SPIRV},
450 {"vmfaults", RADV_DEBUG_VM_FAULTS},
451 {"zerovram", RADV_DEBUG_ZERO_VRAM},
452 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
453 {"nosisched", RADV_DEBUG_NO_SISCHED},
454 {"preoptir", RADV_DEBUG_PREOPTIR},
455 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
456 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
457 {"info", RADV_DEBUG_INFO},
458 {"errors", RADV_DEBUG_ERRORS},
459 {"startup", RADV_DEBUG_STARTUP},
460 {"checkir", RADV_DEBUG_CHECKIR},
461 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
462 {"nobinning", RADV_DEBUG_NOBINNING},
463 {NULL, 0}
464 };
465
466 const char *
467 radv_get_debug_option_name(int id)
468 {
469 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
470 return radv_debug_options[id].string;
471 }
472
473 static const struct debug_control radv_perftest_options[] = {
474 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
475 {"sisched", RADV_PERFTEST_SISCHED},
476 {"localbos", RADV_PERFTEST_LOCAL_BOS},
477 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
478 {NULL, 0}
479 };
480
481 const char *
482 radv_get_perftest_option_name(int id)
483 {
484 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
485 return radv_perftest_options[id].string;
486 }
487
488 static void
489 radv_handle_per_app_options(struct radv_instance *instance,
490 const VkApplicationInfo *info)
491 {
492 const char *name = info ? info->pApplicationName : NULL;
493
494 if (!name)
495 return;
496
497 if (!strcmp(name, "Talos - Linux - 32bit") ||
498 !strcmp(name, "Talos - Linux - 64bit")) {
499 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
500 /* Force enable LLVM sisched for Talos because it looks
501 * safe and it gives few more FPS.
502 */
503 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
504 }
505 } else if (!strcmp(name, "DOOM_VFR")) {
506 /* Work around a Doom VFR game bug */
507 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
508 }
509 }
510
511 static int radv_get_instance_extension_index(const char *name)
512 {
513 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
514 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
515 return i;
516 }
517 return -1;
518 }
519
520
521 VkResult radv_CreateInstance(
522 const VkInstanceCreateInfo* pCreateInfo,
523 const VkAllocationCallbacks* pAllocator,
524 VkInstance* pInstance)
525 {
526 struct radv_instance *instance;
527 VkResult result;
528
529 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
530
531 uint32_t client_version;
532 if (pCreateInfo->pApplicationInfo &&
533 pCreateInfo->pApplicationInfo->apiVersion != 0) {
534 client_version = pCreateInfo->pApplicationInfo->apiVersion;
535 } else {
536 client_version = VK_API_VERSION_1_0;
537 }
538
539 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
540 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
541 if (!instance)
542 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
543
544 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
545
546 if (pAllocator)
547 instance->alloc = *pAllocator;
548 else
549 instance->alloc = default_alloc;
550
551 instance->apiVersion = client_version;
552 instance->physicalDeviceCount = -1;
553
554 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
555 radv_debug_options);
556
557 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
558 radv_perftest_options);
559
560
561 if (instance->debug_flags & RADV_DEBUG_STARTUP)
562 radv_logi("Created an instance");
563
564 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
565 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
566 int index = radv_get_instance_extension_index(ext_name);
567
568 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
569 vk_free2(&default_alloc, pAllocator, instance);
570 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
571 }
572
573 instance->enabled_extensions.extensions[index] = true;
574 }
575
576 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
577 if (result != VK_SUCCESS) {
578 vk_free2(&default_alloc, pAllocator, instance);
579 return vk_error(instance, result);
580 }
581
582 _mesa_locale_init();
583
584 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
585
586 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
587
588 *pInstance = radv_instance_to_handle(instance);
589
590 return VK_SUCCESS;
591 }
592
593 void radv_DestroyInstance(
594 VkInstance _instance,
595 const VkAllocationCallbacks* pAllocator)
596 {
597 RADV_FROM_HANDLE(radv_instance, instance, _instance);
598
599 if (!instance)
600 return;
601
602 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
603 radv_physical_device_finish(instance->physicalDevices + i);
604 }
605
606 VG(VALGRIND_DESTROY_MEMPOOL(instance));
607
608 _mesa_locale_fini();
609
610 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
611
612 vk_free(&instance->alloc, instance);
613 }
614
615 static VkResult
616 radv_enumerate_devices(struct radv_instance *instance)
617 {
618 /* TODO: Check for more devices ? */
619 drmDevicePtr devices[8];
620 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
621 int max_devices;
622
623 instance->physicalDeviceCount = 0;
624
625 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
626
627 if (instance->debug_flags & RADV_DEBUG_STARTUP)
628 radv_logi("Found %d drm nodes", max_devices);
629
630 if (max_devices < 1)
631 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
632
633 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
634 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
635 devices[i]->bustype == DRM_BUS_PCI &&
636 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
637
638 result = radv_physical_device_init(instance->physicalDevices +
639 instance->physicalDeviceCount,
640 instance,
641 devices[i]);
642 if (result == VK_SUCCESS)
643 ++instance->physicalDeviceCount;
644 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
645 break;
646 }
647 }
648 drmFreeDevices(devices, max_devices);
649
650 return result;
651 }
652
653 VkResult radv_EnumeratePhysicalDevices(
654 VkInstance _instance,
655 uint32_t* pPhysicalDeviceCount,
656 VkPhysicalDevice* pPhysicalDevices)
657 {
658 RADV_FROM_HANDLE(radv_instance, instance, _instance);
659 VkResult result;
660
661 if (instance->physicalDeviceCount < 0) {
662 result = radv_enumerate_devices(instance);
663 if (result != VK_SUCCESS &&
664 result != VK_ERROR_INCOMPATIBLE_DRIVER)
665 return result;
666 }
667
668 if (!pPhysicalDevices) {
669 *pPhysicalDeviceCount = instance->physicalDeviceCount;
670 } else {
671 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
672 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
673 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
674 }
675
676 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
677 : VK_SUCCESS;
678 }
679
680 VkResult radv_EnumeratePhysicalDeviceGroups(
681 VkInstance _instance,
682 uint32_t* pPhysicalDeviceGroupCount,
683 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
684 {
685 RADV_FROM_HANDLE(radv_instance, instance, _instance);
686 VkResult result;
687
688 if (instance->physicalDeviceCount < 0) {
689 result = radv_enumerate_devices(instance);
690 if (result != VK_SUCCESS &&
691 result != VK_ERROR_INCOMPATIBLE_DRIVER)
692 return result;
693 }
694
695 if (!pPhysicalDeviceGroupProperties) {
696 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
697 } else {
698 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
699 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
700 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
701 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
702 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
703 }
704 }
705 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
706 : VK_SUCCESS;
707 }
708
709 void radv_GetPhysicalDeviceFeatures(
710 VkPhysicalDevice physicalDevice,
711 VkPhysicalDeviceFeatures* pFeatures)
712 {
713 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
714 memset(pFeatures, 0, sizeof(*pFeatures));
715
716 *pFeatures = (VkPhysicalDeviceFeatures) {
717 .robustBufferAccess = true,
718 .fullDrawIndexUint32 = true,
719 .imageCubeArray = true,
720 .independentBlend = true,
721 .geometryShader = true,
722 .tessellationShader = true,
723 .sampleRateShading = true,
724 .dualSrcBlend = true,
725 .logicOp = true,
726 .multiDrawIndirect = true,
727 .drawIndirectFirstInstance = true,
728 .depthClamp = true,
729 .depthBiasClamp = true,
730 .fillModeNonSolid = true,
731 .depthBounds = true,
732 .wideLines = true,
733 .largePoints = true,
734 .alphaToOne = true,
735 .multiViewport = true,
736 .samplerAnisotropy = true,
737 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
738 pdevice->rad_info.family == CHIP_STONEY,
739 .textureCompressionASTC_LDR = false,
740 .textureCompressionBC = true,
741 .occlusionQueryPrecise = true,
742 .pipelineStatisticsQuery = true,
743 .vertexPipelineStoresAndAtomics = true,
744 .fragmentStoresAndAtomics = true,
745 .shaderTessellationAndGeometryPointSize = true,
746 .shaderImageGatherExtended = true,
747 .shaderStorageImageExtendedFormats = true,
748 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
749 .shaderUniformBufferArrayDynamicIndexing = true,
750 .shaderSampledImageArrayDynamicIndexing = true,
751 .shaderStorageBufferArrayDynamicIndexing = true,
752 .shaderStorageImageArrayDynamicIndexing = true,
753 .shaderStorageImageReadWithoutFormat = true,
754 .shaderStorageImageWriteWithoutFormat = true,
755 .shaderClipDistance = true,
756 .shaderCullDistance = true,
757 .shaderFloat64 = true,
758 .shaderInt64 = true,
759 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
760 .sparseBinding = true,
761 .variableMultisampleRate = true,
762 .inheritedQueries = true,
763 };
764 }
765
766 void radv_GetPhysicalDeviceFeatures2(
767 VkPhysicalDevice physicalDevice,
768 VkPhysicalDeviceFeatures2 *pFeatures)
769 {
770 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
771 vk_foreach_struct(ext, pFeatures->pNext) {
772 switch (ext->sType) {
773 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
774 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
775 features->variablePointersStorageBuffer = true;
776 features->variablePointers = true;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
780 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
781 features->multiview = true;
782 features->multiviewGeometryShader = true;
783 features->multiviewTessellationShader = true;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
787 VkPhysicalDeviceShaderDrawParameterFeatures *features =
788 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
789 features->shaderDrawParameters = true;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
793 VkPhysicalDeviceProtectedMemoryFeatures *features =
794 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
795 features->protectedMemory = false;
796 break;
797 }
798 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
799 VkPhysicalDevice16BitStorageFeatures *features =
800 (VkPhysicalDevice16BitStorageFeatures*)ext;
801 bool enabled = pdevice->rad_info.chip_class >= VI;
802 features->storageBuffer16BitAccess = enabled;
803 features->uniformAndStorageBuffer16BitAccess = enabled;
804 features->storagePushConstant16 = enabled;
805 features->storageInputOutput16 = enabled;
806 break;
807 }
808 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
809 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
810 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
811 features->samplerYcbcrConversion = false;
812 break;
813 }
814 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
815 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
816 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
817 features->shaderInputAttachmentArrayDynamicIndexing = true;
818 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
819 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
820 features->shaderUniformBufferArrayNonUniformIndexing = false;
821 features->shaderSampledImageArrayNonUniformIndexing = false;
822 features->shaderStorageBufferArrayNonUniformIndexing = false;
823 features->shaderStorageImageArrayNonUniformIndexing = false;
824 features->shaderInputAttachmentArrayNonUniformIndexing = false;
825 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
826 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
827 features->descriptorBindingUniformBufferUpdateAfterBind = true;
828 features->descriptorBindingSampledImageUpdateAfterBind = true;
829 features->descriptorBindingStorageImageUpdateAfterBind = true;
830 features->descriptorBindingStorageBufferUpdateAfterBind = true;
831 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
832 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
833 features->descriptorBindingUpdateUnusedWhilePending = true;
834 features->descriptorBindingPartiallyBound = true;
835 features->descriptorBindingVariableDescriptorCount = true;
836 features->runtimeDescriptorArray = true;
837 break;
838 }
839 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
840 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
841 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
842 features->conditionalRendering = true;
843 features->inheritedConditionalRendering = false;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
847 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
848 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
849 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
850 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
851 break;
852 }
853 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
854 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
855 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
856 features->transformFeedback = true;
857 features->geometryStreams = true;
858 break;
859 }
860 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
861 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
862 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
863 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
864 break;
865 }
866 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
867 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
868 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
869 features->memoryPriority = VK_TRUE;
870 break;
871 }
872 default:
873 break;
874 }
875 }
876 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
877 }
878
879 void radv_GetPhysicalDeviceProperties(
880 VkPhysicalDevice physicalDevice,
881 VkPhysicalDeviceProperties* pProperties)
882 {
883 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
884 VkSampleCountFlags sample_counts = 0xf;
885
886 /* make sure that the entire descriptor set is addressable with a signed
887 * 32-bit int. So the sum of all limits scaled by descriptor size has to
888 * be at most 2 GiB. the combined image & samples object count as one of
889 * both. This limit is for the pipeline layout, not for the set layout, but
890 * there is no set limit, so we just set a pipeline limit. I don't think
891 * any app is going to hit this soon. */
892 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
893 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
894 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
895 32 /* sampler, largest when combined with image */ +
896 64 /* sampled image */ +
897 64 /* storage image */);
898
899 VkPhysicalDeviceLimits limits = {
900 .maxImageDimension1D = (1 << 14),
901 .maxImageDimension2D = (1 << 14),
902 .maxImageDimension3D = (1 << 11),
903 .maxImageDimensionCube = (1 << 14),
904 .maxImageArrayLayers = (1 << 11),
905 .maxTexelBufferElements = 128 * 1024 * 1024,
906 .maxUniformBufferRange = UINT32_MAX,
907 .maxStorageBufferRange = UINT32_MAX,
908 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
909 .maxMemoryAllocationCount = UINT32_MAX,
910 .maxSamplerAllocationCount = 64 * 1024,
911 .bufferImageGranularity = 64, /* A cache line */
912 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
913 .maxBoundDescriptorSets = MAX_SETS,
914 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
915 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
916 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
917 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
918 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
919 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
920 .maxPerStageResources = max_descriptor_set_size,
921 .maxDescriptorSetSamplers = max_descriptor_set_size,
922 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
923 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
924 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
925 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
926 .maxDescriptorSetSampledImages = max_descriptor_set_size,
927 .maxDescriptorSetStorageImages = max_descriptor_set_size,
928 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
929 .maxVertexInputAttributes = 32,
930 .maxVertexInputBindings = 32,
931 .maxVertexInputAttributeOffset = 2047,
932 .maxVertexInputBindingStride = 2048,
933 .maxVertexOutputComponents = 128,
934 .maxTessellationGenerationLevel = 64,
935 .maxTessellationPatchSize = 32,
936 .maxTessellationControlPerVertexInputComponents = 128,
937 .maxTessellationControlPerVertexOutputComponents = 128,
938 .maxTessellationControlPerPatchOutputComponents = 120,
939 .maxTessellationControlTotalOutputComponents = 4096,
940 .maxTessellationEvaluationInputComponents = 128,
941 .maxTessellationEvaluationOutputComponents = 128,
942 .maxGeometryShaderInvocations = 127,
943 .maxGeometryInputComponents = 64,
944 .maxGeometryOutputComponents = 128,
945 .maxGeometryOutputVertices = 256,
946 .maxGeometryTotalOutputComponents = 1024,
947 .maxFragmentInputComponents = 128,
948 .maxFragmentOutputAttachments = 8,
949 .maxFragmentDualSrcAttachments = 1,
950 .maxFragmentCombinedOutputResources = 8,
951 .maxComputeSharedMemorySize = 32768,
952 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
953 .maxComputeWorkGroupInvocations = 2048,
954 .maxComputeWorkGroupSize = {
955 2048,
956 2048,
957 2048
958 },
959 .subPixelPrecisionBits = 8,
960 .subTexelPrecisionBits = 8,
961 .mipmapPrecisionBits = 8,
962 .maxDrawIndexedIndexValue = UINT32_MAX,
963 .maxDrawIndirectCount = UINT32_MAX,
964 .maxSamplerLodBias = 16,
965 .maxSamplerAnisotropy = 16,
966 .maxViewports = MAX_VIEWPORTS,
967 .maxViewportDimensions = { (1 << 14), (1 << 14) },
968 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
969 .viewportSubPixelBits = 8,
970 .minMemoryMapAlignment = 4096, /* A page */
971 .minTexelBufferOffsetAlignment = 1,
972 .minUniformBufferOffsetAlignment = 4,
973 .minStorageBufferOffsetAlignment = 4,
974 .minTexelOffset = -32,
975 .maxTexelOffset = 31,
976 .minTexelGatherOffset = -32,
977 .maxTexelGatherOffset = 31,
978 .minInterpolationOffset = -2,
979 .maxInterpolationOffset = 2,
980 .subPixelInterpolationOffsetBits = 8,
981 .maxFramebufferWidth = (1 << 14),
982 .maxFramebufferHeight = (1 << 14),
983 .maxFramebufferLayers = (1 << 10),
984 .framebufferColorSampleCounts = sample_counts,
985 .framebufferDepthSampleCounts = sample_counts,
986 .framebufferStencilSampleCounts = sample_counts,
987 .framebufferNoAttachmentsSampleCounts = sample_counts,
988 .maxColorAttachments = MAX_RTS,
989 .sampledImageColorSampleCounts = sample_counts,
990 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
991 .sampledImageDepthSampleCounts = sample_counts,
992 .sampledImageStencilSampleCounts = sample_counts,
993 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
994 .maxSampleMaskWords = 1,
995 .timestampComputeAndGraphics = true,
996 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
997 .maxClipDistances = 8,
998 .maxCullDistances = 8,
999 .maxCombinedClipAndCullDistances = 8,
1000 .discreteQueuePriorities = 2,
1001 .pointSizeRange = { 0.125, 255.875 },
1002 .lineWidthRange = { 0.0, 7.9921875 },
1003 .pointSizeGranularity = (1.0 / 8.0),
1004 .lineWidthGranularity = (1.0 / 128.0),
1005 .strictLines = false, /* FINISHME */
1006 .standardSampleLocations = true,
1007 .optimalBufferCopyOffsetAlignment = 128,
1008 .optimalBufferCopyRowPitchAlignment = 128,
1009 .nonCoherentAtomSize = 64,
1010 };
1011
1012 *pProperties = (VkPhysicalDeviceProperties) {
1013 .apiVersion = radv_physical_device_api_version(pdevice),
1014 .driverVersion = vk_get_driver_version(),
1015 .vendorID = ATI_VENDOR_ID,
1016 .deviceID = pdevice->rad_info.pci_id,
1017 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1018 .limits = limits,
1019 .sparseProperties = {0},
1020 };
1021
1022 strcpy(pProperties->deviceName, pdevice->name);
1023 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1024 }
1025
1026 void radv_GetPhysicalDeviceProperties2(
1027 VkPhysicalDevice physicalDevice,
1028 VkPhysicalDeviceProperties2 *pProperties)
1029 {
1030 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1031 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1032
1033 vk_foreach_struct(ext, pProperties->pNext) {
1034 switch (ext->sType) {
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1036 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1037 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1038 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1039 break;
1040 }
1041 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1042 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1043 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1044 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1045 properties->deviceLUIDValid = false;
1046 break;
1047 }
1048 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1049 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1050 properties->maxMultiviewViewCount = MAX_VIEWS;
1051 properties->maxMultiviewInstanceIndex = INT_MAX;
1052 break;
1053 }
1054 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1055 VkPhysicalDevicePointClippingProperties *properties =
1056 (VkPhysicalDevicePointClippingProperties*)ext;
1057 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1061 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1062 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1063 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1067 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1068 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1069 properties->minImportedHostPointerAlignment = 4096;
1070 break;
1071 }
1072 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1073 VkPhysicalDeviceSubgroupProperties *properties =
1074 (VkPhysicalDeviceSubgroupProperties*)ext;
1075 properties->subgroupSize = 64;
1076 properties->supportedStages = VK_SHADER_STAGE_ALL;
1077 properties->supportedOperations =
1078 VK_SUBGROUP_FEATURE_BASIC_BIT |
1079 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1080 VK_SUBGROUP_FEATURE_QUAD_BIT |
1081 VK_SUBGROUP_FEATURE_VOTE_BIT;
1082 if (pdevice->rad_info.chip_class >= VI) {
1083 properties->supportedOperations |=
1084 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1085 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1086 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1087 }
1088 properties->quadOperationsInAllStages = true;
1089 break;
1090 }
1091 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1092 VkPhysicalDeviceMaintenance3Properties *properties =
1093 (VkPhysicalDeviceMaintenance3Properties*)ext;
1094 /* Make sure everything is addressable by a signed 32-bit int, and
1095 * our largest descriptors are 96 bytes. */
1096 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1097 /* Our buffer size fields allow only this much */
1098 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1102 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1103 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1104 /* GFX6-8 only support single channel min/max filter. */
1105 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1106 properties->filterMinmaxSingleComponentFormats = true;
1107 break;
1108 }
1109 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1110 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1111 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1112
1113 /* Shader engines. */
1114 properties->shaderEngineCount =
1115 pdevice->rad_info.max_se;
1116 properties->shaderArraysPerEngineCount =
1117 pdevice->rad_info.max_sh_per_se;
1118 properties->computeUnitsPerShaderArray =
1119 pdevice->rad_info.num_good_cu_per_sh;
1120 properties->simdPerComputeUnit = 4;
1121 properties->wavefrontsPerSimd =
1122 pdevice->rad_info.family == CHIP_TONGA ||
1123 pdevice->rad_info.family == CHIP_ICELAND ||
1124 pdevice->rad_info.family == CHIP_POLARIS10 ||
1125 pdevice->rad_info.family == CHIP_POLARIS11 ||
1126 pdevice->rad_info.family == CHIP_POLARIS12 ||
1127 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1128 properties->wavefrontSize = 64;
1129
1130 /* SGPR. */
1131 properties->sgprsPerSimd =
1132 radv_get_num_physical_sgprs(pdevice);
1133 properties->minSgprAllocation =
1134 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1135 properties->maxSgprAllocation =
1136 pdevice->rad_info.family == CHIP_TONGA ||
1137 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1138 properties->sgprAllocationGranularity =
1139 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1140
1141 /* VGPR. */
1142 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1143 properties->minVgprAllocation = 4;
1144 properties->maxVgprAllocation = 256;
1145 properties->vgprAllocationGranularity = 4;
1146 break;
1147 }
1148 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1149 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1150 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1151 properties->maxVertexAttribDivisor = UINT32_MAX;
1152 break;
1153 }
1154 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1155 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1156 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1157 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1158 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1159 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1160 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1161 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1162 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1163 properties->robustBufferAccessUpdateAfterBind = false;
1164 properties->quadDivergentImplicitLod = false;
1165
1166 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1167 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1168 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1169 32 /* sampler, largest when combined with image */ +
1170 64 /* sampled image */ +
1171 64 /* storage image */);
1172 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1173 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1174 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1175 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1176 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1177 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1178 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1179 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1180 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1181 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1182 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1183 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1184 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1185 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1186 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1187 break;
1188 }
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1190 VkPhysicalDeviceProtectedMemoryProperties *properties =
1191 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1192 properties->protectedNoFault = false;
1193 break;
1194 }
1195 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1196 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1197 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1198 properties->primitiveOverestimationSize = 0;
1199 properties->maxExtraPrimitiveOverestimationSize = 0;
1200 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1201 properties->primitiveUnderestimation = VK_FALSE;
1202 properties->conservativePointAndLineRasterization = VK_FALSE;
1203 properties->degenerateTrianglesRasterized = VK_FALSE;
1204 properties->degenerateLinesRasterized = VK_FALSE;
1205 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1206 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1207 break;
1208 }
1209 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1210 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1211 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1212 properties->pciDomain = pdevice->bus_info.domain;
1213 properties->pciBus = pdevice->bus_info.bus;
1214 properties->pciDevice = pdevice->bus_info.dev;
1215 properties->pciFunction = pdevice->bus_info.func;
1216 break;
1217 }
1218 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1219 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1220 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1221
1222 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1223 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1224 strcpy(driver_props->driverName, "radv");
1225
1226 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1227 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1228 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1229 " (LLVM %d.%d.%d)",
1230 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1231 MESA_LLVM_VERSION_PATCH);
1232
1233 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1234 .major = 1,
1235 .minor = 1,
1236 .subminor = 2,
1237 .patch = 0,
1238 };
1239 break;
1240 }
1241 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1242 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1243 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1244 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1245 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1246 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1247 properties->maxTransformFeedbackStreamDataSize = 512;
1248 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1249 properties->maxTransformFeedbackBufferDataStride = 512;
1250 properties->transformFeedbackQueries = true;
1251 properties->transformFeedbackStreamsLinesTriangles = false;
1252 properties->transformFeedbackRasterizationStreamSelect = false;
1253 properties->transformFeedbackDraw = true;
1254 break;
1255 }
1256 default:
1257 break;
1258 }
1259 }
1260 }
1261
1262 static void radv_get_physical_device_queue_family_properties(
1263 struct radv_physical_device* pdevice,
1264 uint32_t* pCount,
1265 VkQueueFamilyProperties** pQueueFamilyProperties)
1266 {
1267 int num_queue_families = 1;
1268 int idx;
1269 if (pdevice->rad_info.num_compute_rings > 0 &&
1270 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1271 num_queue_families++;
1272
1273 if (pQueueFamilyProperties == NULL) {
1274 *pCount = num_queue_families;
1275 return;
1276 }
1277
1278 if (!*pCount)
1279 return;
1280
1281 idx = 0;
1282 if (*pCount >= 1) {
1283 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1284 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1285 VK_QUEUE_COMPUTE_BIT |
1286 VK_QUEUE_TRANSFER_BIT |
1287 VK_QUEUE_SPARSE_BINDING_BIT,
1288 .queueCount = 1,
1289 .timestampValidBits = 64,
1290 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1291 };
1292 idx++;
1293 }
1294
1295 if (pdevice->rad_info.num_compute_rings > 0 &&
1296 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1297 if (*pCount > idx) {
1298 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1299 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1300 VK_QUEUE_TRANSFER_BIT |
1301 VK_QUEUE_SPARSE_BINDING_BIT,
1302 .queueCount = pdevice->rad_info.num_compute_rings,
1303 .timestampValidBits = 64,
1304 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1305 };
1306 idx++;
1307 }
1308 }
1309 *pCount = idx;
1310 }
1311
1312 void radv_GetPhysicalDeviceQueueFamilyProperties(
1313 VkPhysicalDevice physicalDevice,
1314 uint32_t* pCount,
1315 VkQueueFamilyProperties* pQueueFamilyProperties)
1316 {
1317 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1318 if (!pQueueFamilyProperties) {
1319 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1320 return;
1321 }
1322 VkQueueFamilyProperties *properties[] = {
1323 pQueueFamilyProperties + 0,
1324 pQueueFamilyProperties + 1,
1325 pQueueFamilyProperties + 2,
1326 };
1327 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1328 assert(*pCount <= 3);
1329 }
1330
1331 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1332 VkPhysicalDevice physicalDevice,
1333 uint32_t* pCount,
1334 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1335 {
1336 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1337 if (!pQueueFamilyProperties) {
1338 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1339 return;
1340 }
1341 VkQueueFamilyProperties *properties[] = {
1342 &pQueueFamilyProperties[0].queueFamilyProperties,
1343 &pQueueFamilyProperties[1].queueFamilyProperties,
1344 &pQueueFamilyProperties[2].queueFamilyProperties,
1345 };
1346 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1347 assert(*pCount <= 3);
1348 }
1349
1350 void radv_GetPhysicalDeviceMemoryProperties(
1351 VkPhysicalDevice physicalDevice,
1352 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1353 {
1354 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1355
1356 *pMemoryProperties = physical_device->memory_properties;
1357 }
1358
1359 static void
1360 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1361 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1362 {
1363 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1364 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1365 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1366 uint64_t vram_size = radv_get_vram_size(device);
1367 uint64_t gtt_size = device->rad_info.gart_size;
1368 uint64_t heap_budget, heap_usage;
1369
1370 /* For all memory heaps, the computation of budget is as follow:
1371 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1372 *
1373 * The Vulkan spec 1.1.97 says that the budget should include any
1374 * currently allocated device memory.
1375 *
1376 * Note that the application heap usages are not really accurate (eg.
1377 * in presence of shared buffers).
1378 */
1379 if (vram_size) {
1380 heap_usage = device->ws->query_value(device->ws,
1381 RADEON_ALLOCATED_VRAM);
1382
1383 heap_budget = vram_size -
1384 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1385 heap_usage;
1386
1387 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1388 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1389 }
1390
1391 if (visible_vram_size) {
1392 heap_usage = device->ws->query_value(device->ws,
1393 RADEON_ALLOCATED_VRAM_VIS);
1394
1395 heap_budget = visible_vram_size -
1396 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1397 heap_usage;
1398
1399 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1400 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1401 }
1402
1403 if (gtt_size) {
1404 heap_usage = device->ws->query_value(device->ws,
1405 RADEON_ALLOCATED_GTT);
1406
1407 heap_budget = gtt_size -
1408 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1409 heap_usage;
1410
1411 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1412 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1413 }
1414
1415 /* The heapBudget and heapUsage values must be zero for array elements
1416 * greater than or equal to
1417 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1418 */
1419 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1420 memoryBudget->heapBudget[i] = 0;
1421 memoryBudget->heapUsage[i] = 0;
1422 }
1423 }
1424
1425 void radv_GetPhysicalDeviceMemoryProperties2(
1426 VkPhysicalDevice physicalDevice,
1427 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1428 {
1429 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1430 &pMemoryProperties->memoryProperties);
1431
1432 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1433 vk_find_struct(pMemoryProperties->pNext,
1434 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1435 if (memory_budget)
1436 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1437 }
1438
1439 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1440 VkDevice _device,
1441 VkExternalMemoryHandleTypeFlagBits handleType,
1442 const void *pHostPointer,
1443 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1444 {
1445 RADV_FROM_HANDLE(radv_device, device, _device);
1446
1447 switch (handleType)
1448 {
1449 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1450 const struct radv_physical_device *physical_device = device->physical_device;
1451 uint32_t memoryTypeBits = 0;
1452 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1453 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1454 memoryTypeBits = (1 << i);
1455 break;
1456 }
1457 }
1458 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1459 return VK_SUCCESS;
1460 }
1461 default:
1462 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1463 }
1464 }
1465
1466 static enum radeon_ctx_priority
1467 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1468 {
1469 /* Default to MEDIUM when a specific global priority isn't requested */
1470 if (!pObj)
1471 return RADEON_CTX_PRIORITY_MEDIUM;
1472
1473 switch(pObj->globalPriority) {
1474 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1475 return RADEON_CTX_PRIORITY_REALTIME;
1476 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1477 return RADEON_CTX_PRIORITY_HIGH;
1478 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1479 return RADEON_CTX_PRIORITY_MEDIUM;
1480 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1481 return RADEON_CTX_PRIORITY_LOW;
1482 default:
1483 unreachable("Illegal global priority value");
1484 return RADEON_CTX_PRIORITY_INVALID;
1485 }
1486 }
1487
1488 static int
1489 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1490 uint32_t queue_family_index, int idx,
1491 VkDeviceQueueCreateFlags flags,
1492 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1493 {
1494 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1495 queue->device = device;
1496 queue->queue_family_index = queue_family_index;
1497 queue->queue_idx = idx;
1498 queue->priority = radv_get_queue_global_priority(global_priority);
1499 queue->flags = flags;
1500
1501 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1502 if (!queue->hw_ctx)
1503 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1504
1505 return VK_SUCCESS;
1506 }
1507
1508 static void
1509 radv_queue_finish(struct radv_queue *queue)
1510 {
1511 if (queue->hw_ctx)
1512 queue->device->ws->ctx_destroy(queue->hw_ctx);
1513
1514 if (queue->initial_full_flush_preamble_cs)
1515 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1516 if (queue->initial_preamble_cs)
1517 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1518 if (queue->continue_preamble_cs)
1519 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1520 if (queue->descriptor_bo)
1521 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1522 if (queue->scratch_bo)
1523 queue->device->ws->buffer_destroy(queue->scratch_bo);
1524 if (queue->esgs_ring_bo)
1525 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1526 if (queue->gsvs_ring_bo)
1527 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1528 if (queue->tess_rings_bo)
1529 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1530 if (queue->compute_scratch_bo)
1531 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1532 }
1533
1534 static void
1535 radv_bo_list_init(struct radv_bo_list *bo_list)
1536 {
1537 pthread_mutex_init(&bo_list->mutex, NULL);
1538 bo_list->list.count = bo_list->capacity = 0;
1539 bo_list->list.bos = NULL;
1540 }
1541
1542 static void
1543 radv_bo_list_finish(struct radv_bo_list *bo_list)
1544 {
1545 free(bo_list->list.bos);
1546 pthread_mutex_destroy(&bo_list->mutex);
1547 }
1548
1549 static VkResult radv_bo_list_add(struct radv_device *device,
1550 struct radeon_winsys_bo *bo)
1551 {
1552 struct radv_bo_list *bo_list = &device->bo_list;
1553
1554 if (unlikely(!device->use_global_bo_list))
1555 return VK_SUCCESS;
1556
1557 pthread_mutex_lock(&bo_list->mutex);
1558 if (bo_list->list.count == bo_list->capacity) {
1559 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1560 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1561
1562 if (!data) {
1563 pthread_mutex_unlock(&bo_list->mutex);
1564 return VK_ERROR_OUT_OF_HOST_MEMORY;
1565 }
1566
1567 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1568 bo_list->capacity = capacity;
1569 }
1570
1571 bo_list->list.bos[bo_list->list.count++] = bo;
1572 pthread_mutex_unlock(&bo_list->mutex);
1573 return VK_SUCCESS;
1574 }
1575
1576 static void radv_bo_list_remove(struct radv_device *device,
1577 struct radeon_winsys_bo *bo)
1578 {
1579 struct radv_bo_list *bo_list = &device->bo_list;
1580
1581 if (unlikely(!device->use_global_bo_list))
1582 return;
1583
1584 pthread_mutex_lock(&bo_list->mutex);
1585 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1586 if (bo_list->list.bos[i] == bo) {
1587 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1588 --bo_list->list.count;
1589 break;
1590 }
1591 }
1592 pthread_mutex_unlock(&bo_list->mutex);
1593 }
1594
1595 static void
1596 radv_device_init_gs_info(struct radv_device *device)
1597 {
1598 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1599 device->physical_device->rad_info.family);
1600 }
1601
1602 static int radv_get_device_extension_index(const char *name)
1603 {
1604 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1605 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1606 return i;
1607 }
1608 return -1;
1609 }
1610
1611 static int
1612 radv_get_int_debug_option(const char *name, int default_value)
1613 {
1614 const char *str;
1615 int result;
1616
1617 str = getenv(name);
1618 if (!str) {
1619 result = default_value;
1620 } else {
1621 char *endptr;
1622
1623 result = strtol(str, &endptr, 0);
1624 if (str == endptr) {
1625 /* No digits founs. */
1626 result = default_value;
1627 }
1628 }
1629
1630 return result;
1631 }
1632
1633 VkResult radv_CreateDevice(
1634 VkPhysicalDevice physicalDevice,
1635 const VkDeviceCreateInfo* pCreateInfo,
1636 const VkAllocationCallbacks* pAllocator,
1637 VkDevice* pDevice)
1638 {
1639 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1640 VkResult result;
1641 struct radv_device *device;
1642
1643 bool keep_shader_info = false;
1644
1645 /* Check enabled features */
1646 if (pCreateInfo->pEnabledFeatures) {
1647 VkPhysicalDeviceFeatures supported_features;
1648 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1649 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1650 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1651 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1652 for (uint32_t i = 0; i < num_features; i++) {
1653 if (enabled_feature[i] && !supported_feature[i])
1654 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1655 }
1656 }
1657
1658 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1659 sizeof(*device), 8,
1660 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1661 if (!device)
1662 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1663
1664 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1665 device->instance = physical_device->instance;
1666 device->physical_device = physical_device;
1667
1668 device->ws = physical_device->ws;
1669 if (pAllocator)
1670 device->alloc = *pAllocator;
1671 else
1672 device->alloc = physical_device->instance->alloc;
1673
1674 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1675 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1676 int index = radv_get_device_extension_index(ext_name);
1677 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1678 vk_free(&device->alloc, device);
1679 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1680 }
1681
1682 device->enabled_extensions.extensions[index] = true;
1683 }
1684
1685 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1686
1687 /* With update after bind we can't attach bo's to the command buffer
1688 * from the descriptor set anymore, so we have to use a global BO list.
1689 */
1690 device->use_global_bo_list =
1691 device->enabled_extensions.EXT_descriptor_indexing;
1692
1693 mtx_init(&device->shader_slab_mutex, mtx_plain);
1694 list_inithead(&device->shader_slabs);
1695
1696 radv_bo_list_init(&device->bo_list);
1697
1698 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1699 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1700 uint32_t qfi = queue_create->queueFamilyIndex;
1701 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1702 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1703
1704 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1705
1706 device->queues[qfi] = vk_alloc(&device->alloc,
1707 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1708 if (!device->queues[qfi]) {
1709 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1710 goto fail;
1711 }
1712
1713 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1714
1715 device->queue_count[qfi] = queue_create->queueCount;
1716
1717 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1718 result = radv_queue_init(device, &device->queues[qfi][q],
1719 qfi, q, queue_create->flags,
1720 global_priority);
1721 if (result != VK_SUCCESS)
1722 goto fail;
1723 }
1724 }
1725
1726 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1727 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1728
1729 /* Disabled and not implemented for now. */
1730 device->dfsm_allowed = device->pbb_allowed &&
1731 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1732 device->physical_device->rad_info.family == CHIP_RAVEN2);
1733
1734 #ifdef ANDROID
1735 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1736 #endif
1737
1738 /* The maximum number of scratch waves. Scratch space isn't divided
1739 * evenly between CUs. The number is only a function of the number of CUs.
1740 * We can decrease the constant to decrease the scratch buffer size.
1741 *
1742 * sctx->scratch_waves must be >= the maximum possible size of
1743 * 1 threadgroup, so that the hw doesn't hang from being unable
1744 * to start any.
1745 *
1746 * The recommended value is 4 per CU at most. Higher numbers don't
1747 * bring much benefit, but they still occupy chip resources (think
1748 * async compute). I've seen ~2% performance difference between 4 and 32.
1749 */
1750 uint32_t max_threads_per_block = 2048;
1751 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1752 max_threads_per_block / 64);
1753
1754 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1755
1756 if (device->physical_device->rad_info.chip_class >= CIK) {
1757 /* If the KMD allows it (there is a KMD hw register for it),
1758 * allow launching waves out-of-order.
1759 */
1760 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1761 }
1762
1763 radv_device_init_gs_info(device);
1764
1765 device->tess_offchip_block_dw_size =
1766 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1767 device->has_distributed_tess =
1768 device->physical_device->rad_info.chip_class >= VI &&
1769 device->physical_device->rad_info.max_se >= 2;
1770
1771 if (getenv("RADV_TRACE_FILE")) {
1772 const char *filename = getenv("RADV_TRACE_FILE");
1773
1774 keep_shader_info = true;
1775
1776 if (!radv_init_trace(device))
1777 goto fail;
1778
1779 fprintf(stderr, "*****************************************************************************\n");
1780 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1781 fprintf(stderr, "*****************************************************************************\n");
1782
1783 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1784 radv_dump_enabled_options(device, stderr);
1785 }
1786
1787 device->keep_shader_info = keep_shader_info;
1788
1789 result = radv_device_init_meta(device);
1790 if (result != VK_SUCCESS)
1791 goto fail;
1792
1793 radv_device_init_msaa(device);
1794
1795 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1796 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1797 switch (family) {
1798 case RADV_QUEUE_GENERAL:
1799 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1800 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1801 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1802 break;
1803 case RADV_QUEUE_COMPUTE:
1804 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1805 radeon_emit(device->empty_cs[family], 0);
1806 break;
1807 }
1808 device->ws->cs_finalize(device->empty_cs[family]);
1809 }
1810
1811 if (device->physical_device->rad_info.chip_class >= CIK)
1812 cik_create_gfx_config(device);
1813
1814 VkPipelineCacheCreateInfo ci;
1815 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1816 ci.pNext = NULL;
1817 ci.flags = 0;
1818 ci.pInitialData = NULL;
1819 ci.initialDataSize = 0;
1820 VkPipelineCache pc;
1821 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1822 &ci, NULL, &pc);
1823 if (result != VK_SUCCESS)
1824 goto fail_meta;
1825
1826 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1827
1828 device->force_aniso =
1829 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1830 if (device->force_aniso >= 0) {
1831 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1832 1 << util_logbase2(device->force_aniso));
1833 }
1834
1835 *pDevice = radv_device_to_handle(device);
1836 return VK_SUCCESS;
1837
1838 fail_meta:
1839 radv_device_finish_meta(device);
1840 fail:
1841 radv_bo_list_finish(&device->bo_list);
1842
1843 if (device->trace_bo)
1844 device->ws->buffer_destroy(device->trace_bo);
1845
1846 if (device->gfx_init)
1847 device->ws->buffer_destroy(device->gfx_init);
1848
1849 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1850 for (unsigned q = 0; q < device->queue_count[i]; q++)
1851 radv_queue_finish(&device->queues[i][q]);
1852 if (device->queue_count[i])
1853 vk_free(&device->alloc, device->queues[i]);
1854 }
1855
1856 vk_free(&device->alloc, device);
1857 return result;
1858 }
1859
1860 void radv_DestroyDevice(
1861 VkDevice _device,
1862 const VkAllocationCallbacks* pAllocator)
1863 {
1864 RADV_FROM_HANDLE(radv_device, device, _device);
1865
1866 if (!device)
1867 return;
1868
1869 if (device->trace_bo)
1870 device->ws->buffer_destroy(device->trace_bo);
1871
1872 if (device->gfx_init)
1873 device->ws->buffer_destroy(device->gfx_init);
1874
1875 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1876 for (unsigned q = 0; q < device->queue_count[i]; q++)
1877 radv_queue_finish(&device->queues[i][q]);
1878 if (device->queue_count[i])
1879 vk_free(&device->alloc, device->queues[i]);
1880 if (device->empty_cs[i])
1881 device->ws->cs_destroy(device->empty_cs[i]);
1882 }
1883 radv_device_finish_meta(device);
1884
1885 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1886 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1887
1888 radv_destroy_shader_slabs(device);
1889
1890 radv_bo_list_finish(&device->bo_list);
1891 vk_free(&device->alloc, device);
1892 }
1893
1894 VkResult radv_EnumerateInstanceLayerProperties(
1895 uint32_t* pPropertyCount,
1896 VkLayerProperties* pProperties)
1897 {
1898 if (pProperties == NULL) {
1899 *pPropertyCount = 0;
1900 return VK_SUCCESS;
1901 }
1902
1903 /* None supported at this time */
1904 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1905 }
1906
1907 VkResult radv_EnumerateDeviceLayerProperties(
1908 VkPhysicalDevice physicalDevice,
1909 uint32_t* pPropertyCount,
1910 VkLayerProperties* pProperties)
1911 {
1912 if (pProperties == NULL) {
1913 *pPropertyCount = 0;
1914 return VK_SUCCESS;
1915 }
1916
1917 /* None supported at this time */
1918 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1919 }
1920
1921 void radv_GetDeviceQueue2(
1922 VkDevice _device,
1923 const VkDeviceQueueInfo2* pQueueInfo,
1924 VkQueue* pQueue)
1925 {
1926 RADV_FROM_HANDLE(radv_device, device, _device);
1927 struct radv_queue *queue;
1928
1929 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1930 if (pQueueInfo->flags != queue->flags) {
1931 /* From the Vulkan 1.1.70 spec:
1932 *
1933 * "The queue returned by vkGetDeviceQueue2 must have the same
1934 * flags value from this structure as that used at device
1935 * creation time in a VkDeviceQueueCreateInfo instance. If no
1936 * matching flags were specified at device creation time then
1937 * pQueue will return VK_NULL_HANDLE."
1938 */
1939 *pQueue = VK_NULL_HANDLE;
1940 return;
1941 }
1942
1943 *pQueue = radv_queue_to_handle(queue);
1944 }
1945
1946 void radv_GetDeviceQueue(
1947 VkDevice _device,
1948 uint32_t queueFamilyIndex,
1949 uint32_t queueIndex,
1950 VkQueue* pQueue)
1951 {
1952 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1953 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1954 .queueFamilyIndex = queueFamilyIndex,
1955 .queueIndex = queueIndex
1956 };
1957
1958 radv_GetDeviceQueue2(_device, &info, pQueue);
1959 }
1960
1961 static void
1962 fill_geom_tess_rings(struct radv_queue *queue,
1963 uint32_t *map,
1964 bool add_sample_positions,
1965 uint32_t esgs_ring_size,
1966 struct radeon_winsys_bo *esgs_ring_bo,
1967 uint32_t gsvs_ring_size,
1968 struct radeon_winsys_bo *gsvs_ring_bo,
1969 uint32_t tess_factor_ring_size,
1970 uint32_t tess_offchip_ring_offset,
1971 uint32_t tess_offchip_ring_size,
1972 struct radeon_winsys_bo *tess_rings_bo)
1973 {
1974 uint32_t *desc = &map[4];
1975
1976 if (esgs_ring_bo) {
1977 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
1978
1979 /* stride 0, num records - size, add tid, swizzle, elsize4,
1980 index stride 64 */
1981 desc[0] = esgs_va;
1982 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1983 S_008F04_STRIDE(0) |
1984 S_008F04_SWIZZLE_ENABLE(true);
1985 desc[2] = esgs_ring_size;
1986 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1987 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1988 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1989 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1990 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1991 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1992 S_008F0C_ELEMENT_SIZE(1) |
1993 S_008F0C_INDEX_STRIDE(3) |
1994 S_008F0C_ADD_TID_ENABLE(true);
1995
1996 /* GS entry for ES->GS ring */
1997 /* stride 0, num records - size, elsize0,
1998 index stride 0 */
1999 desc[4] = esgs_va;
2000 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2001 S_008F04_STRIDE(0) |
2002 S_008F04_SWIZZLE_ENABLE(false);
2003 desc[6] = esgs_ring_size;
2004 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2005 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2006 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2007 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2008 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2009 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2010 S_008F0C_ELEMENT_SIZE(0) |
2011 S_008F0C_INDEX_STRIDE(0) |
2012 S_008F0C_ADD_TID_ENABLE(false);
2013 }
2014
2015 desc += 8;
2016
2017 if (gsvs_ring_bo) {
2018 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2019
2020 /* VS entry for GS->VS ring */
2021 /* stride 0, num records - size, elsize0,
2022 index stride 0 */
2023 desc[0] = gsvs_va;
2024 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2025 S_008F04_STRIDE(0) |
2026 S_008F04_SWIZZLE_ENABLE(false);
2027 desc[2] = gsvs_ring_size;
2028 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2029 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2030 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2031 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2032 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2033 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2034 S_008F0C_ELEMENT_SIZE(0) |
2035 S_008F0C_INDEX_STRIDE(0) |
2036 S_008F0C_ADD_TID_ENABLE(false);
2037
2038 /* stride gsvs_itemsize, num records 64
2039 elsize 4, index stride 16 */
2040 /* shader will patch stride and desc[2] */
2041 desc[4] = gsvs_va;
2042 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2043 S_008F04_STRIDE(0) |
2044 S_008F04_SWIZZLE_ENABLE(true);
2045 desc[6] = 0;
2046 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2047 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2048 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2049 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2050 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2051 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2052 S_008F0C_ELEMENT_SIZE(1) |
2053 S_008F0C_INDEX_STRIDE(1) |
2054 S_008F0C_ADD_TID_ENABLE(true);
2055 }
2056
2057 desc += 8;
2058
2059 if (tess_rings_bo) {
2060 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2061 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2062
2063 desc[0] = tess_va;
2064 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2065 S_008F04_STRIDE(0) |
2066 S_008F04_SWIZZLE_ENABLE(false);
2067 desc[2] = tess_factor_ring_size;
2068 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2069 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2070 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2071 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2072 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2073 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2074 S_008F0C_ELEMENT_SIZE(0) |
2075 S_008F0C_INDEX_STRIDE(0) |
2076 S_008F0C_ADD_TID_ENABLE(false);
2077
2078 desc[4] = tess_offchip_va;
2079 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2080 S_008F04_STRIDE(0) |
2081 S_008F04_SWIZZLE_ENABLE(false);
2082 desc[6] = tess_offchip_ring_size;
2083 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2084 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2085 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2086 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2087 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2088 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2089 S_008F0C_ELEMENT_SIZE(0) |
2090 S_008F0C_INDEX_STRIDE(0) |
2091 S_008F0C_ADD_TID_ENABLE(false);
2092 }
2093
2094 desc += 8;
2095
2096 if (add_sample_positions) {
2097 /* add sample positions after all rings */
2098 memcpy(desc, queue->device->sample_locations_1x, 8);
2099 desc += 2;
2100 memcpy(desc, queue->device->sample_locations_2x, 16);
2101 desc += 4;
2102 memcpy(desc, queue->device->sample_locations_4x, 32);
2103 desc += 8;
2104 memcpy(desc, queue->device->sample_locations_8x, 64);
2105 }
2106 }
2107
2108 static unsigned
2109 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2110 {
2111 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2112 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2113 device->physical_device->rad_info.family != CHIP_STONEY;
2114 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2115 unsigned max_offchip_buffers;
2116 unsigned offchip_granularity;
2117 unsigned hs_offchip_param;
2118
2119 /*
2120 * Per RadeonSI:
2121 * This must be one less than the maximum number due to a hw limitation.
2122 * Various hardware bugs in SI, CIK, and GFX9 need this.
2123 *
2124 * Per AMDVLK:
2125 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2126 * Gfx7 should limit max_offchip_buffers to 508
2127 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2128 *
2129 * Follow AMDVLK here.
2130 */
2131 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2132 device->physical_device->rad_info.chip_class == CIK ||
2133 device->physical_device->rad_info.chip_class == SI)
2134 --max_offchip_buffers_per_se;
2135
2136 max_offchip_buffers = max_offchip_buffers_per_se *
2137 device->physical_device->rad_info.max_se;
2138
2139 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2140 * around by setting 4K granularity.
2141 */
2142 if (device->tess_offchip_block_dw_size == 4096) {
2143 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2144 offchip_granularity = V_03093C_X_4K_DWORDS;
2145 } else {
2146 assert(device->tess_offchip_block_dw_size == 8192);
2147 offchip_granularity = V_03093C_X_8K_DWORDS;
2148 }
2149
2150 switch (device->physical_device->rad_info.chip_class) {
2151 case SI:
2152 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2153 break;
2154 case CIK:
2155 case VI:
2156 case GFX9:
2157 default:
2158 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2159 break;
2160 }
2161
2162 *max_offchip_buffers_p = max_offchip_buffers;
2163 if (device->physical_device->rad_info.chip_class >= CIK) {
2164 if (device->physical_device->rad_info.chip_class >= VI)
2165 --max_offchip_buffers;
2166 hs_offchip_param =
2167 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2168 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2169 } else {
2170 hs_offchip_param =
2171 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2172 }
2173 return hs_offchip_param;
2174 }
2175
2176 static void
2177 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2178 struct radeon_winsys_bo *esgs_ring_bo,
2179 uint32_t esgs_ring_size,
2180 struct radeon_winsys_bo *gsvs_ring_bo,
2181 uint32_t gsvs_ring_size)
2182 {
2183 if (!esgs_ring_bo && !gsvs_ring_bo)
2184 return;
2185
2186 if (esgs_ring_bo)
2187 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2188
2189 if (gsvs_ring_bo)
2190 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2191
2192 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2193 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2194 radeon_emit(cs, esgs_ring_size >> 8);
2195 radeon_emit(cs, gsvs_ring_size >> 8);
2196 } else {
2197 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2198 radeon_emit(cs, esgs_ring_size >> 8);
2199 radeon_emit(cs, gsvs_ring_size >> 8);
2200 }
2201 }
2202
2203 static void
2204 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2205 unsigned hs_offchip_param, unsigned tf_ring_size,
2206 struct radeon_winsys_bo *tess_rings_bo)
2207 {
2208 uint64_t tf_va;
2209
2210 if (!tess_rings_bo)
2211 return;
2212
2213 tf_va = radv_buffer_get_va(tess_rings_bo);
2214
2215 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2216
2217 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2218 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2219 S_030938_SIZE(tf_ring_size / 4));
2220 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2221 tf_va >> 8);
2222 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2223 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2224 S_030944_BASE_HI(tf_va >> 40));
2225 }
2226 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2227 hs_offchip_param);
2228 } else {
2229 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2230 S_008988_SIZE(tf_ring_size / 4));
2231 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2232 tf_va >> 8);
2233 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2234 hs_offchip_param);
2235 }
2236 }
2237
2238 static void
2239 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2240 struct radeon_winsys_bo *compute_scratch_bo)
2241 {
2242 uint64_t scratch_va;
2243
2244 if (!compute_scratch_bo)
2245 return;
2246
2247 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2248
2249 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2250
2251 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2252 radeon_emit(cs, scratch_va);
2253 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2254 S_008F04_SWIZZLE_ENABLE(1));
2255 }
2256
2257 static void
2258 radv_emit_global_shader_pointers(struct radv_queue *queue,
2259 struct radeon_cmdbuf *cs,
2260 struct radeon_winsys_bo *descriptor_bo)
2261 {
2262 uint64_t va;
2263
2264 if (!descriptor_bo)
2265 return;
2266
2267 va = radv_buffer_get_va(descriptor_bo);
2268
2269 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2270
2271 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2272 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2273 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2274 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2275 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2276
2277 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2278 radv_emit_shader_pointer(queue->device, cs, regs[i],
2279 va, true);
2280 }
2281 } else {
2282 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2283 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2284 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2285 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2286 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2287 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2288
2289 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2290 radv_emit_shader_pointer(queue->device, cs, regs[i],
2291 va, true);
2292 }
2293 }
2294 }
2295
2296 static void
2297 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2298 {
2299 struct radv_device *device = queue->device;
2300
2301 if (device->gfx_init) {
2302 uint64_t va = radv_buffer_get_va(device->gfx_init);
2303
2304 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2305 radeon_emit(cs, va);
2306 radeon_emit(cs, va >> 32);
2307 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2308
2309 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2310 } else {
2311 struct radv_physical_device *physical_device = device->physical_device;
2312 si_emit_graphics(physical_device, cs);
2313 }
2314 }
2315
2316 static void
2317 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2318 {
2319 struct radv_physical_device *physical_device = queue->device->physical_device;
2320 si_emit_compute(physical_device, cs);
2321 }
2322
2323 static VkResult
2324 radv_get_preamble_cs(struct radv_queue *queue,
2325 uint32_t scratch_size,
2326 uint32_t compute_scratch_size,
2327 uint32_t esgs_ring_size,
2328 uint32_t gsvs_ring_size,
2329 bool needs_tess_rings,
2330 bool needs_sample_positions,
2331 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2332 struct radeon_cmdbuf **initial_preamble_cs,
2333 struct radeon_cmdbuf **continue_preamble_cs)
2334 {
2335 struct radeon_winsys_bo *scratch_bo = NULL;
2336 struct radeon_winsys_bo *descriptor_bo = NULL;
2337 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2338 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2339 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2340 struct radeon_winsys_bo *tess_rings_bo = NULL;
2341 struct radeon_cmdbuf *dest_cs[3] = {0};
2342 bool add_tess_rings = false, add_sample_positions = false;
2343 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2344 unsigned max_offchip_buffers;
2345 unsigned hs_offchip_param = 0;
2346 unsigned tess_offchip_ring_offset;
2347 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2348 if (!queue->has_tess_rings) {
2349 if (needs_tess_rings)
2350 add_tess_rings = true;
2351 }
2352 if (!queue->has_sample_positions) {
2353 if (needs_sample_positions)
2354 add_sample_positions = true;
2355 }
2356 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2357 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2358 &max_offchip_buffers);
2359 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2360 tess_offchip_ring_size = max_offchip_buffers *
2361 queue->device->tess_offchip_block_dw_size * 4;
2362
2363 if (scratch_size <= queue->scratch_size &&
2364 compute_scratch_size <= queue->compute_scratch_size &&
2365 esgs_ring_size <= queue->esgs_ring_size &&
2366 gsvs_ring_size <= queue->gsvs_ring_size &&
2367 !add_tess_rings && !add_sample_positions &&
2368 queue->initial_preamble_cs) {
2369 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2370 *initial_preamble_cs = queue->initial_preamble_cs;
2371 *continue_preamble_cs = queue->continue_preamble_cs;
2372 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2373 *continue_preamble_cs = NULL;
2374 return VK_SUCCESS;
2375 }
2376
2377 if (scratch_size > queue->scratch_size) {
2378 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2379 scratch_size,
2380 4096,
2381 RADEON_DOMAIN_VRAM,
2382 ring_bo_flags,
2383 RADV_BO_PRIORITY_SCRATCH);
2384 if (!scratch_bo)
2385 goto fail;
2386 } else
2387 scratch_bo = queue->scratch_bo;
2388
2389 if (compute_scratch_size > queue->compute_scratch_size) {
2390 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2391 compute_scratch_size,
2392 4096,
2393 RADEON_DOMAIN_VRAM,
2394 ring_bo_flags,
2395 RADV_BO_PRIORITY_SCRATCH);
2396 if (!compute_scratch_bo)
2397 goto fail;
2398
2399 } else
2400 compute_scratch_bo = queue->compute_scratch_bo;
2401
2402 if (esgs_ring_size > queue->esgs_ring_size) {
2403 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2404 esgs_ring_size,
2405 4096,
2406 RADEON_DOMAIN_VRAM,
2407 ring_bo_flags,
2408 RADV_BO_PRIORITY_SCRATCH);
2409 if (!esgs_ring_bo)
2410 goto fail;
2411 } else {
2412 esgs_ring_bo = queue->esgs_ring_bo;
2413 esgs_ring_size = queue->esgs_ring_size;
2414 }
2415
2416 if (gsvs_ring_size > queue->gsvs_ring_size) {
2417 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2418 gsvs_ring_size,
2419 4096,
2420 RADEON_DOMAIN_VRAM,
2421 ring_bo_flags,
2422 RADV_BO_PRIORITY_SCRATCH);
2423 if (!gsvs_ring_bo)
2424 goto fail;
2425 } else {
2426 gsvs_ring_bo = queue->gsvs_ring_bo;
2427 gsvs_ring_size = queue->gsvs_ring_size;
2428 }
2429
2430 if (add_tess_rings) {
2431 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2432 tess_offchip_ring_offset + tess_offchip_ring_size,
2433 256,
2434 RADEON_DOMAIN_VRAM,
2435 ring_bo_flags,
2436 RADV_BO_PRIORITY_SCRATCH);
2437 if (!tess_rings_bo)
2438 goto fail;
2439 } else {
2440 tess_rings_bo = queue->tess_rings_bo;
2441 }
2442
2443 if (scratch_bo != queue->scratch_bo ||
2444 esgs_ring_bo != queue->esgs_ring_bo ||
2445 gsvs_ring_bo != queue->gsvs_ring_bo ||
2446 tess_rings_bo != queue->tess_rings_bo ||
2447 add_sample_positions) {
2448 uint32_t size = 0;
2449 if (gsvs_ring_bo || esgs_ring_bo ||
2450 tess_rings_bo || add_sample_positions) {
2451 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2452 if (add_sample_positions)
2453 size += 128; /* 64+32+16+8 = 120 bytes */
2454 }
2455 else if (scratch_bo)
2456 size = 8; /* 2 dword */
2457
2458 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2459 size,
2460 4096,
2461 RADEON_DOMAIN_VRAM,
2462 RADEON_FLAG_CPU_ACCESS |
2463 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2464 RADEON_FLAG_READ_ONLY,
2465 RADV_BO_PRIORITY_DESCRIPTOR);
2466 if (!descriptor_bo)
2467 goto fail;
2468 } else
2469 descriptor_bo = queue->descriptor_bo;
2470
2471 if (descriptor_bo != queue->descriptor_bo) {
2472 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2473
2474 if (scratch_bo) {
2475 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2476 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2477 S_008F04_SWIZZLE_ENABLE(1);
2478 map[0] = scratch_va;
2479 map[1] = rsrc1;
2480 }
2481
2482 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2483 fill_geom_tess_rings(queue, map, add_sample_positions,
2484 esgs_ring_size, esgs_ring_bo,
2485 gsvs_ring_size, gsvs_ring_bo,
2486 tess_factor_ring_size,
2487 tess_offchip_ring_offset,
2488 tess_offchip_ring_size,
2489 tess_rings_bo);
2490
2491 queue->device->ws->buffer_unmap(descriptor_bo);
2492 }
2493
2494 for(int i = 0; i < 3; ++i) {
2495 struct radeon_cmdbuf *cs = NULL;
2496 cs = queue->device->ws->cs_create(queue->device->ws,
2497 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2498 if (!cs)
2499 goto fail;
2500
2501 dest_cs[i] = cs;
2502
2503 if (scratch_bo)
2504 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2505
2506 /* Emit initial configuration. */
2507 switch (queue->queue_family_index) {
2508 case RADV_QUEUE_GENERAL:
2509 radv_init_graphics_state(cs, queue);
2510 break;
2511 case RADV_QUEUE_COMPUTE:
2512 radv_init_compute_state(cs, queue);
2513 break;
2514 case RADV_QUEUE_TRANSFER:
2515 break;
2516 }
2517
2518 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2519 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2520 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2521 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2522 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2523 }
2524
2525 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2526 gsvs_ring_bo, gsvs_ring_size);
2527 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2528 tess_factor_ring_size, tess_rings_bo);
2529 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2530 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2531
2532 if (i == 0) {
2533 si_cs_emit_cache_flush(cs,
2534 queue->device->physical_device->rad_info.chip_class,
2535 NULL, 0,
2536 queue->queue_family_index == RING_COMPUTE &&
2537 queue->device->physical_device->rad_info.chip_class >= CIK,
2538 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2539 RADV_CMD_FLAG_INV_ICACHE |
2540 RADV_CMD_FLAG_INV_SMEM_L1 |
2541 RADV_CMD_FLAG_INV_VMEM_L1 |
2542 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2543 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2544 } else if (i == 1) {
2545 si_cs_emit_cache_flush(cs,
2546 queue->device->physical_device->rad_info.chip_class,
2547 NULL, 0,
2548 queue->queue_family_index == RING_COMPUTE &&
2549 queue->device->physical_device->rad_info.chip_class >= CIK,
2550 RADV_CMD_FLAG_INV_ICACHE |
2551 RADV_CMD_FLAG_INV_SMEM_L1 |
2552 RADV_CMD_FLAG_INV_VMEM_L1 |
2553 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2554 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2555 }
2556
2557 if (!queue->device->ws->cs_finalize(cs))
2558 goto fail;
2559 }
2560
2561 if (queue->initial_full_flush_preamble_cs)
2562 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2563
2564 if (queue->initial_preamble_cs)
2565 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2566
2567 if (queue->continue_preamble_cs)
2568 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2569
2570 queue->initial_full_flush_preamble_cs = dest_cs[0];
2571 queue->initial_preamble_cs = dest_cs[1];
2572 queue->continue_preamble_cs = dest_cs[2];
2573
2574 if (scratch_bo != queue->scratch_bo) {
2575 if (queue->scratch_bo)
2576 queue->device->ws->buffer_destroy(queue->scratch_bo);
2577 queue->scratch_bo = scratch_bo;
2578 queue->scratch_size = scratch_size;
2579 }
2580
2581 if (compute_scratch_bo != queue->compute_scratch_bo) {
2582 if (queue->compute_scratch_bo)
2583 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2584 queue->compute_scratch_bo = compute_scratch_bo;
2585 queue->compute_scratch_size = compute_scratch_size;
2586 }
2587
2588 if (esgs_ring_bo != queue->esgs_ring_bo) {
2589 if (queue->esgs_ring_bo)
2590 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2591 queue->esgs_ring_bo = esgs_ring_bo;
2592 queue->esgs_ring_size = esgs_ring_size;
2593 }
2594
2595 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2596 if (queue->gsvs_ring_bo)
2597 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2598 queue->gsvs_ring_bo = gsvs_ring_bo;
2599 queue->gsvs_ring_size = gsvs_ring_size;
2600 }
2601
2602 if (tess_rings_bo != queue->tess_rings_bo) {
2603 queue->tess_rings_bo = tess_rings_bo;
2604 queue->has_tess_rings = true;
2605 }
2606
2607 if (descriptor_bo != queue->descriptor_bo) {
2608 if (queue->descriptor_bo)
2609 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2610
2611 queue->descriptor_bo = descriptor_bo;
2612 }
2613
2614 if (add_sample_positions)
2615 queue->has_sample_positions = true;
2616
2617 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2618 *initial_preamble_cs = queue->initial_preamble_cs;
2619 *continue_preamble_cs = queue->continue_preamble_cs;
2620 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2621 *continue_preamble_cs = NULL;
2622 return VK_SUCCESS;
2623 fail:
2624 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2625 if (dest_cs[i])
2626 queue->device->ws->cs_destroy(dest_cs[i]);
2627 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2628 queue->device->ws->buffer_destroy(descriptor_bo);
2629 if (scratch_bo && scratch_bo != queue->scratch_bo)
2630 queue->device->ws->buffer_destroy(scratch_bo);
2631 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2632 queue->device->ws->buffer_destroy(compute_scratch_bo);
2633 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2634 queue->device->ws->buffer_destroy(esgs_ring_bo);
2635 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2636 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2637 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2638 queue->device->ws->buffer_destroy(tess_rings_bo);
2639 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2640 }
2641
2642 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2643 struct radv_winsys_sem_counts *counts,
2644 int num_sems,
2645 const VkSemaphore *sems,
2646 VkFence _fence,
2647 bool reset_temp)
2648 {
2649 int syncobj_idx = 0, sem_idx = 0;
2650
2651 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2652 return VK_SUCCESS;
2653
2654 for (uint32_t i = 0; i < num_sems; i++) {
2655 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2656
2657 if (sem->temp_syncobj || sem->syncobj)
2658 counts->syncobj_count++;
2659 else
2660 counts->sem_count++;
2661 }
2662
2663 if (_fence != VK_NULL_HANDLE) {
2664 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2665 if (fence->temp_syncobj || fence->syncobj)
2666 counts->syncobj_count++;
2667 }
2668
2669 if (counts->syncobj_count) {
2670 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2671 if (!counts->syncobj)
2672 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2673 }
2674
2675 if (counts->sem_count) {
2676 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2677 if (!counts->sem) {
2678 free(counts->syncobj);
2679 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2680 }
2681 }
2682
2683 for (uint32_t i = 0; i < num_sems; i++) {
2684 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2685
2686 if (sem->temp_syncobj) {
2687 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2688 }
2689 else if (sem->syncobj)
2690 counts->syncobj[syncobj_idx++] = sem->syncobj;
2691 else {
2692 assert(sem->sem);
2693 counts->sem[sem_idx++] = sem->sem;
2694 }
2695 }
2696
2697 if (_fence != VK_NULL_HANDLE) {
2698 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2699 if (fence->temp_syncobj)
2700 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2701 else if (fence->syncobj)
2702 counts->syncobj[syncobj_idx++] = fence->syncobj;
2703 }
2704
2705 return VK_SUCCESS;
2706 }
2707
2708 static void
2709 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2710 {
2711 free(sem_info->wait.syncobj);
2712 free(sem_info->wait.sem);
2713 free(sem_info->signal.syncobj);
2714 free(sem_info->signal.sem);
2715 }
2716
2717
2718 static void radv_free_temp_syncobjs(struct radv_device *device,
2719 int num_sems,
2720 const VkSemaphore *sems)
2721 {
2722 for (uint32_t i = 0; i < num_sems; i++) {
2723 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2724
2725 if (sem->temp_syncobj) {
2726 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2727 sem->temp_syncobj = 0;
2728 }
2729 }
2730 }
2731
2732 static VkResult
2733 radv_alloc_sem_info(struct radv_instance *instance,
2734 struct radv_winsys_sem_info *sem_info,
2735 int num_wait_sems,
2736 const VkSemaphore *wait_sems,
2737 int num_signal_sems,
2738 const VkSemaphore *signal_sems,
2739 VkFence fence)
2740 {
2741 VkResult ret;
2742 memset(sem_info, 0, sizeof(*sem_info));
2743
2744 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2745 if (ret)
2746 return ret;
2747 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2748 if (ret)
2749 radv_free_sem_info(sem_info);
2750
2751 /* caller can override these */
2752 sem_info->cs_emit_wait = true;
2753 sem_info->cs_emit_signal = true;
2754 return ret;
2755 }
2756
2757 /* Signals fence as soon as all the work currently put on queue is done. */
2758 static VkResult radv_signal_fence(struct radv_queue *queue,
2759 struct radv_fence *fence)
2760 {
2761 int ret;
2762 VkResult result;
2763 struct radv_winsys_sem_info sem_info;
2764
2765 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2766 radv_fence_to_handle(fence));
2767 if (result != VK_SUCCESS)
2768 return result;
2769
2770 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2771 &queue->device->empty_cs[queue->queue_family_index],
2772 1, NULL, NULL, &sem_info, NULL,
2773 false, fence->fence);
2774 radv_free_sem_info(&sem_info);
2775
2776 if (ret)
2777 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2778
2779 return VK_SUCCESS;
2780 }
2781
2782 VkResult radv_QueueSubmit(
2783 VkQueue _queue,
2784 uint32_t submitCount,
2785 const VkSubmitInfo* pSubmits,
2786 VkFence _fence)
2787 {
2788 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2789 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2790 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2791 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2792 int ret;
2793 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2794 uint32_t scratch_size = 0;
2795 uint32_t compute_scratch_size = 0;
2796 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2797 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2798 VkResult result;
2799 bool fence_emitted = false;
2800 bool tess_rings_needed = false;
2801 bool sample_positions_needed = false;
2802
2803 /* Do this first so failing to allocate scratch buffers can't result in
2804 * partially executed submissions. */
2805 for (uint32_t i = 0; i < submitCount; i++) {
2806 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2807 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2808 pSubmits[i].pCommandBuffers[j]);
2809
2810 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2811 compute_scratch_size = MAX2(compute_scratch_size,
2812 cmd_buffer->compute_scratch_size_needed);
2813 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2814 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2815 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2816 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2817 }
2818 }
2819
2820 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2821 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2822 sample_positions_needed, &initial_flush_preamble_cs,
2823 &initial_preamble_cs, &continue_preamble_cs);
2824 if (result != VK_SUCCESS)
2825 return result;
2826
2827 for (uint32_t i = 0; i < submitCount; i++) {
2828 struct radeon_cmdbuf **cs_array;
2829 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2830 bool can_patch = true;
2831 uint32_t advance;
2832 struct radv_winsys_sem_info sem_info;
2833
2834 result = radv_alloc_sem_info(queue->device->instance,
2835 &sem_info,
2836 pSubmits[i].waitSemaphoreCount,
2837 pSubmits[i].pWaitSemaphores,
2838 pSubmits[i].signalSemaphoreCount,
2839 pSubmits[i].pSignalSemaphores,
2840 _fence);
2841 if (result != VK_SUCCESS)
2842 return result;
2843
2844 if (!pSubmits[i].commandBufferCount) {
2845 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2846 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2847 &queue->device->empty_cs[queue->queue_family_index],
2848 1, NULL, NULL,
2849 &sem_info, NULL,
2850 false, base_fence);
2851 if (ret) {
2852 radv_loge("failed to submit CS %d\n", i);
2853 abort();
2854 }
2855 fence_emitted = true;
2856 }
2857 radv_free_sem_info(&sem_info);
2858 continue;
2859 }
2860
2861 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2862 (pSubmits[i].commandBufferCount));
2863
2864 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2865 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2866 pSubmits[i].pCommandBuffers[j]);
2867 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2868
2869 cs_array[j] = cmd_buffer->cs;
2870 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2871 can_patch = false;
2872
2873 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2874 }
2875
2876 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2877 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2878 const struct radv_winsys_bo_list *bo_list = NULL;
2879
2880 advance = MIN2(max_cs_submission,
2881 pSubmits[i].commandBufferCount - j);
2882
2883 if (queue->device->trace_bo)
2884 *queue->device->trace_id_ptr = 0;
2885
2886 sem_info.cs_emit_wait = j == 0;
2887 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2888
2889 if (unlikely(queue->device->use_global_bo_list)) {
2890 pthread_mutex_lock(&queue->device->bo_list.mutex);
2891 bo_list = &queue->device->bo_list.list;
2892 }
2893
2894 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2895 advance, initial_preamble, continue_preamble_cs,
2896 &sem_info, bo_list,
2897 can_patch, base_fence);
2898
2899 if (unlikely(queue->device->use_global_bo_list))
2900 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2901
2902 if (ret) {
2903 radv_loge("failed to submit CS %d\n", i);
2904 abort();
2905 }
2906 fence_emitted = true;
2907 if (queue->device->trace_bo) {
2908 radv_check_gpu_hangs(queue, cs_array[j]);
2909 }
2910 }
2911
2912 radv_free_temp_syncobjs(queue->device,
2913 pSubmits[i].waitSemaphoreCount,
2914 pSubmits[i].pWaitSemaphores);
2915 radv_free_sem_info(&sem_info);
2916 free(cs_array);
2917 }
2918
2919 if (fence) {
2920 if (!fence_emitted) {
2921 result = radv_signal_fence(queue, fence);
2922 if (result != VK_SUCCESS)
2923 return result;
2924 }
2925 fence->submitted = true;
2926 }
2927
2928 return VK_SUCCESS;
2929 }
2930
2931 VkResult radv_QueueWaitIdle(
2932 VkQueue _queue)
2933 {
2934 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2935
2936 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2937 radv_queue_family_to_ring(queue->queue_family_index),
2938 queue->queue_idx);
2939 return VK_SUCCESS;
2940 }
2941
2942 VkResult radv_DeviceWaitIdle(
2943 VkDevice _device)
2944 {
2945 RADV_FROM_HANDLE(radv_device, device, _device);
2946
2947 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2948 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2949 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2950 }
2951 }
2952 return VK_SUCCESS;
2953 }
2954
2955 VkResult radv_EnumerateInstanceExtensionProperties(
2956 const char* pLayerName,
2957 uint32_t* pPropertyCount,
2958 VkExtensionProperties* pProperties)
2959 {
2960 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2961
2962 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2963 if (radv_supported_instance_extensions.extensions[i]) {
2964 vk_outarray_append(&out, prop) {
2965 *prop = radv_instance_extensions[i];
2966 }
2967 }
2968 }
2969
2970 return vk_outarray_status(&out);
2971 }
2972
2973 VkResult radv_EnumerateDeviceExtensionProperties(
2974 VkPhysicalDevice physicalDevice,
2975 const char* pLayerName,
2976 uint32_t* pPropertyCount,
2977 VkExtensionProperties* pProperties)
2978 {
2979 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2980 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2981
2982 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2983 if (device->supported_extensions.extensions[i]) {
2984 vk_outarray_append(&out, prop) {
2985 *prop = radv_device_extensions[i];
2986 }
2987 }
2988 }
2989
2990 return vk_outarray_status(&out);
2991 }
2992
2993 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2994 VkInstance _instance,
2995 const char* pName)
2996 {
2997 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2998
2999 return radv_lookup_entrypoint_checked(pName,
3000 instance ? instance->apiVersion : 0,
3001 instance ? &instance->enabled_extensions : NULL,
3002 NULL);
3003 }
3004
3005 /* The loader wants us to expose a second GetInstanceProcAddr function
3006 * to work around certain LD_PRELOAD issues seen in apps.
3007 */
3008 PUBLIC
3009 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3010 VkInstance instance,
3011 const char* pName);
3012
3013 PUBLIC
3014 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3015 VkInstance instance,
3016 const char* pName)
3017 {
3018 return radv_GetInstanceProcAddr(instance, pName);
3019 }
3020
3021 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3022 VkDevice _device,
3023 const char* pName)
3024 {
3025 RADV_FROM_HANDLE(radv_device, device, _device);
3026
3027 return radv_lookup_entrypoint_checked(pName,
3028 device->instance->apiVersion,
3029 &device->instance->enabled_extensions,
3030 &device->enabled_extensions);
3031 }
3032
3033 bool radv_get_memory_fd(struct radv_device *device,
3034 struct radv_device_memory *memory,
3035 int *pFD)
3036 {
3037 struct radeon_bo_metadata metadata;
3038
3039 if (memory->image) {
3040 radv_init_metadata(device, memory->image, &metadata);
3041 device->ws->buffer_set_metadata(memory->bo, &metadata);
3042 }
3043
3044 return device->ws->buffer_get_fd(device->ws, memory->bo,
3045 pFD);
3046 }
3047
3048 static VkResult radv_alloc_memory(struct radv_device *device,
3049 const VkMemoryAllocateInfo* pAllocateInfo,
3050 const VkAllocationCallbacks* pAllocator,
3051 VkDeviceMemory* pMem)
3052 {
3053 struct radv_device_memory *mem;
3054 VkResult result;
3055 enum radeon_bo_domain domain;
3056 uint32_t flags = 0;
3057 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3058
3059 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3060
3061 if (pAllocateInfo->allocationSize == 0) {
3062 /* Apparently, this is allowed */
3063 *pMem = VK_NULL_HANDLE;
3064 return VK_SUCCESS;
3065 }
3066
3067 const VkImportMemoryFdInfoKHR *import_info =
3068 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3069 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3070 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3071 const VkExportMemoryAllocateInfo *export_info =
3072 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3073 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3074 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3075
3076 const struct wsi_memory_allocate_info *wsi_info =
3077 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3078
3079 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3080 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3081 if (mem == NULL)
3082 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3083
3084 if (wsi_info && wsi_info->implicit_sync)
3085 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3086
3087 if (dedicate_info) {
3088 mem->image = radv_image_from_handle(dedicate_info->image);
3089 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3090 } else {
3091 mem->image = NULL;
3092 mem->buffer = NULL;
3093 }
3094
3095 float priority_float = 0.5;
3096 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3097 vk_find_struct_const(pAllocateInfo->pNext,
3098 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3099 if (priority_ext)
3100 priority_float = priority_ext->priority;
3101
3102 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3103 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3104
3105 mem->user_ptr = NULL;
3106
3107 if (import_info) {
3108 assert(import_info->handleType ==
3109 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3110 import_info->handleType ==
3111 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3112 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3113 priority, NULL, NULL);
3114 if (!mem->bo) {
3115 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3116 goto fail;
3117 } else {
3118 close(import_info->fd);
3119 }
3120 } else if (host_ptr_info) {
3121 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3122 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3123 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3124 pAllocateInfo->allocationSize,
3125 priority);
3126 if (!mem->bo) {
3127 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3128 goto fail;
3129 } else {
3130 mem->user_ptr = host_ptr_info->pHostPointer;
3131 }
3132 } else {
3133 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3134 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3135 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3136 domain = RADEON_DOMAIN_GTT;
3137 else
3138 domain = RADEON_DOMAIN_VRAM;
3139
3140 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3141 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3142 else
3143 flags |= RADEON_FLAG_CPU_ACCESS;
3144
3145 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3146 flags |= RADEON_FLAG_GTT_WC;
3147
3148 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3149 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3150
3151 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3152 domain, flags, priority);
3153
3154 if (!mem->bo) {
3155 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3156 goto fail;
3157 }
3158 mem->type_index = mem_type_index;
3159 }
3160
3161 result = radv_bo_list_add(device, mem->bo);
3162 if (result != VK_SUCCESS)
3163 goto fail_bo;
3164
3165 *pMem = radv_device_memory_to_handle(mem);
3166
3167 return VK_SUCCESS;
3168
3169 fail_bo:
3170 device->ws->buffer_destroy(mem->bo);
3171 fail:
3172 vk_free2(&device->alloc, pAllocator, mem);
3173
3174 return result;
3175 }
3176
3177 VkResult radv_AllocateMemory(
3178 VkDevice _device,
3179 const VkMemoryAllocateInfo* pAllocateInfo,
3180 const VkAllocationCallbacks* pAllocator,
3181 VkDeviceMemory* pMem)
3182 {
3183 RADV_FROM_HANDLE(radv_device, device, _device);
3184 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3185 }
3186
3187 void radv_FreeMemory(
3188 VkDevice _device,
3189 VkDeviceMemory _mem,
3190 const VkAllocationCallbacks* pAllocator)
3191 {
3192 RADV_FROM_HANDLE(radv_device, device, _device);
3193 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3194
3195 if (mem == NULL)
3196 return;
3197
3198 radv_bo_list_remove(device, mem->bo);
3199 device->ws->buffer_destroy(mem->bo);
3200 mem->bo = NULL;
3201
3202 vk_free2(&device->alloc, pAllocator, mem);
3203 }
3204
3205 VkResult radv_MapMemory(
3206 VkDevice _device,
3207 VkDeviceMemory _memory,
3208 VkDeviceSize offset,
3209 VkDeviceSize size,
3210 VkMemoryMapFlags flags,
3211 void** ppData)
3212 {
3213 RADV_FROM_HANDLE(radv_device, device, _device);
3214 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3215
3216 if (mem == NULL) {
3217 *ppData = NULL;
3218 return VK_SUCCESS;
3219 }
3220
3221 if (mem->user_ptr)
3222 *ppData = mem->user_ptr;
3223 else
3224 *ppData = device->ws->buffer_map(mem->bo);
3225
3226 if (*ppData) {
3227 *ppData += offset;
3228 return VK_SUCCESS;
3229 }
3230
3231 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3232 }
3233
3234 void radv_UnmapMemory(
3235 VkDevice _device,
3236 VkDeviceMemory _memory)
3237 {
3238 RADV_FROM_HANDLE(radv_device, device, _device);
3239 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3240
3241 if (mem == NULL)
3242 return;
3243
3244 if (mem->user_ptr == NULL)
3245 device->ws->buffer_unmap(mem->bo);
3246 }
3247
3248 VkResult radv_FlushMappedMemoryRanges(
3249 VkDevice _device,
3250 uint32_t memoryRangeCount,
3251 const VkMappedMemoryRange* pMemoryRanges)
3252 {
3253 return VK_SUCCESS;
3254 }
3255
3256 VkResult radv_InvalidateMappedMemoryRanges(
3257 VkDevice _device,
3258 uint32_t memoryRangeCount,
3259 const VkMappedMemoryRange* pMemoryRanges)
3260 {
3261 return VK_SUCCESS;
3262 }
3263
3264 void radv_GetBufferMemoryRequirements(
3265 VkDevice _device,
3266 VkBuffer _buffer,
3267 VkMemoryRequirements* pMemoryRequirements)
3268 {
3269 RADV_FROM_HANDLE(radv_device, device, _device);
3270 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3271
3272 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3273
3274 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3275 pMemoryRequirements->alignment = 4096;
3276 else
3277 pMemoryRequirements->alignment = 16;
3278
3279 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3280 }
3281
3282 void radv_GetBufferMemoryRequirements2(
3283 VkDevice device,
3284 const VkBufferMemoryRequirementsInfo2 *pInfo,
3285 VkMemoryRequirements2 *pMemoryRequirements)
3286 {
3287 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3288 &pMemoryRequirements->memoryRequirements);
3289 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3290 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3291 switch (ext->sType) {
3292 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3293 VkMemoryDedicatedRequirements *req =
3294 (VkMemoryDedicatedRequirements *) ext;
3295 req->requiresDedicatedAllocation = buffer->shareable;
3296 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3297 break;
3298 }
3299 default:
3300 break;
3301 }
3302 }
3303 }
3304
3305 void radv_GetImageMemoryRequirements(
3306 VkDevice _device,
3307 VkImage _image,
3308 VkMemoryRequirements* pMemoryRequirements)
3309 {
3310 RADV_FROM_HANDLE(radv_device, device, _device);
3311 RADV_FROM_HANDLE(radv_image, image, _image);
3312
3313 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3314
3315 pMemoryRequirements->size = image->size;
3316 pMemoryRequirements->alignment = image->alignment;
3317 }
3318
3319 void radv_GetImageMemoryRequirements2(
3320 VkDevice device,
3321 const VkImageMemoryRequirementsInfo2 *pInfo,
3322 VkMemoryRequirements2 *pMemoryRequirements)
3323 {
3324 radv_GetImageMemoryRequirements(device, pInfo->image,
3325 &pMemoryRequirements->memoryRequirements);
3326
3327 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3328
3329 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3330 switch (ext->sType) {
3331 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3332 VkMemoryDedicatedRequirements *req =
3333 (VkMemoryDedicatedRequirements *) ext;
3334 req->requiresDedicatedAllocation = image->shareable;
3335 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3336 break;
3337 }
3338 default:
3339 break;
3340 }
3341 }
3342 }
3343
3344 void radv_GetImageSparseMemoryRequirements(
3345 VkDevice device,
3346 VkImage image,
3347 uint32_t* pSparseMemoryRequirementCount,
3348 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3349 {
3350 stub();
3351 }
3352
3353 void radv_GetImageSparseMemoryRequirements2(
3354 VkDevice device,
3355 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3356 uint32_t* pSparseMemoryRequirementCount,
3357 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3358 {
3359 stub();
3360 }
3361
3362 void radv_GetDeviceMemoryCommitment(
3363 VkDevice device,
3364 VkDeviceMemory memory,
3365 VkDeviceSize* pCommittedMemoryInBytes)
3366 {
3367 *pCommittedMemoryInBytes = 0;
3368 }
3369
3370 VkResult radv_BindBufferMemory2(VkDevice device,
3371 uint32_t bindInfoCount,
3372 const VkBindBufferMemoryInfo *pBindInfos)
3373 {
3374 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3375 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3376 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3377
3378 if (mem) {
3379 buffer->bo = mem->bo;
3380 buffer->offset = pBindInfos[i].memoryOffset;
3381 } else {
3382 buffer->bo = NULL;
3383 }
3384 }
3385 return VK_SUCCESS;
3386 }
3387
3388 VkResult radv_BindBufferMemory(
3389 VkDevice device,
3390 VkBuffer buffer,
3391 VkDeviceMemory memory,
3392 VkDeviceSize memoryOffset)
3393 {
3394 const VkBindBufferMemoryInfo info = {
3395 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3396 .buffer = buffer,
3397 .memory = memory,
3398 .memoryOffset = memoryOffset
3399 };
3400
3401 return radv_BindBufferMemory2(device, 1, &info);
3402 }
3403
3404 VkResult radv_BindImageMemory2(VkDevice device,
3405 uint32_t bindInfoCount,
3406 const VkBindImageMemoryInfo *pBindInfos)
3407 {
3408 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3409 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3410 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3411
3412 if (mem) {
3413 image->bo = mem->bo;
3414 image->offset = pBindInfos[i].memoryOffset;
3415 } else {
3416 image->bo = NULL;
3417 image->offset = 0;
3418 }
3419 }
3420 return VK_SUCCESS;
3421 }
3422
3423
3424 VkResult radv_BindImageMemory(
3425 VkDevice device,
3426 VkImage image,
3427 VkDeviceMemory memory,
3428 VkDeviceSize memoryOffset)
3429 {
3430 const VkBindImageMemoryInfo info = {
3431 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3432 .image = image,
3433 .memory = memory,
3434 .memoryOffset = memoryOffset
3435 };
3436
3437 return radv_BindImageMemory2(device, 1, &info);
3438 }
3439
3440
3441 static void
3442 radv_sparse_buffer_bind_memory(struct radv_device *device,
3443 const VkSparseBufferMemoryBindInfo *bind)
3444 {
3445 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3446
3447 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3448 struct radv_device_memory *mem = NULL;
3449
3450 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3451 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3452
3453 device->ws->buffer_virtual_bind(buffer->bo,
3454 bind->pBinds[i].resourceOffset,
3455 bind->pBinds[i].size,
3456 mem ? mem->bo : NULL,
3457 bind->pBinds[i].memoryOffset);
3458 }
3459 }
3460
3461 static void
3462 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3463 const VkSparseImageOpaqueMemoryBindInfo *bind)
3464 {
3465 RADV_FROM_HANDLE(radv_image, image, bind->image);
3466
3467 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3468 struct radv_device_memory *mem = NULL;
3469
3470 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3471 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3472
3473 device->ws->buffer_virtual_bind(image->bo,
3474 bind->pBinds[i].resourceOffset,
3475 bind->pBinds[i].size,
3476 mem ? mem->bo : NULL,
3477 bind->pBinds[i].memoryOffset);
3478 }
3479 }
3480
3481 VkResult radv_QueueBindSparse(
3482 VkQueue _queue,
3483 uint32_t bindInfoCount,
3484 const VkBindSparseInfo* pBindInfo,
3485 VkFence _fence)
3486 {
3487 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3488 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3489 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3490 bool fence_emitted = false;
3491 VkResult result;
3492 int ret;
3493
3494 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3495 struct radv_winsys_sem_info sem_info;
3496 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3497 radv_sparse_buffer_bind_memory(queue->device,
3498 pBindInfo[i].pBufferBinds + j);
3499 }
3500
3501 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3502 radv_sparse_image_opaque_bind_memory(queue->device,
3503 pBindInfo[i].pImageOpaqueBinds + j);
3504 }
3505
3506 VkResult result;
3507 result = radv_alloc_sem_info(queue->device->instance,
3508 &sem_info,
3509 pBindInfo[i].waitSemaphoreCount,
3510 pBindInfo[i].pWaitSemaphores,
3511 pBindInfo[i].signalSemaphoreCount,
3512 pBindInfo[i].pSignalSemaphores,
3513 _fence);
3514 if (result != VK_SUCCESS)
3515 return result;
3516
3517 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3518 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3519 &queue->device->empty_cs[queue->queue_family_index],
3520 1, NULL, NULL,
3521 &sem_info, NULL,
3522 false, base_fence);
3523 if (ret) {
3524 radv_loge("failed to submit CS %d\n", i);
3525 abort();
3526 }
3527
3528 fence_emitted = true;
3529 if (fence)
3530 fence->submitted = true;
3531 }
3532
3533 radv_free_sem_info(&sem_info);
3534
3535 }
3536
3537 if (fence) {
3538 if (!fence_emitted) {
3539 result = radv_signal_fence(queue, fence);
3540 if (result != VK_SUCCESS)
3541 return result;
3542 }
3543 fence->submitted = true;
3544 }
3545
3546 return VK_SUCCESS;
3547 }
3548
3549 VkResult radv_CreateFence(
3550 VkDevice _device,
3551 const VkFenceCreateInfo* pCreateInfo,
3552 const VkAllocationCallbacks* pAllocator,
3553 VkFence* pFence)
3554 {
3555 RADV_FROM_HANDLE(radv_device, device, _device);
3556 const VkExportFenceCreateInfo *export =
3557 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3558 VkExternalFenceHandleTypeFlags handleTypes =
3559 export ? export->handleTypes : 0;
3560
3561 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3562 sizeof(*fence), 8,
3563 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3564
3565 if (!fence)
3566 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3567
3568 fence->fence_wsi = NULL;
3569 fence->submitted = false;
3570 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3571 fence->temp_syncobj = 0;
3572 if (device->always_use_syncobj || handleTypes) {
3573 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3574 if (ret) {
3575 vk_free2(&device->alloc, pAllocator, fence);
3576 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3577 }
3578 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3579 device->ws->signal_syncobj(device->ws, fence->syncobj);
3580 }
3581 fence->fence = NULL;
3582 } else {
3583 fence->fence = device->ws->create_fence();
3584 if (!fence->fence) {
3585 vk_free2(&device->alloc, pAllocator, fence);
3586 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3587 }
3588 fence->syncobj = 0;
3589 }
3590
3591 *pFence = radv_fence_to_handle(fence);
3592
3593 return VK_SUCCESS;
3594 }
3595
3596 void radv_DestroyFence(
3597 VkDevice _device,
3598 VkFence _fence,
3599 const VkAllocationCallbacks* pAllocator)
3600 {
3601 RADV_FROM_HANDLE(radv_device, device, _device);
3602 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3603
3604 if (!fence)
3605 return;
3606
3607 if (fence->temp_syncobj)
3608 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3609 if (fence->syncobj)
3610 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3611 if (fence->fence)
3612 device->ws->destroy_fence(fence->fence);
3613 if (fence->fence_wsi)
3614 fence->fence_wsi->destroy(fence->fence_wsi);
3615 vk_free2(&device->alloc, pAllocator, fence);
3616 }
3617
3618
3619 static uint64_t radv_get_current_time()
3620 {
3621 struct timespec tv;
3622 clock_gettime(CLOCK_MONOTONIC, &tv);
3623 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3624 }
3625
3626 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3627 {
3628 uint64_t current_time = radv_get_current_time();
3629
3630 timeout = MIN2(UINT64_MAX - current_time, timeout);
3631
3632 return current_time + timeout;
3633 }
3634
3635
3636 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3637 {
3638 for (uint32_t i = 0; i < fenceCount; ++i) {
3639 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3640 if (fence->fence == NULL || fence->syncobj ||
3641 fence->temp_syncobj ||
3642 (!fence->signalled && !fence->submitted))
3643 return false;
3644 }
3645 return true;
3646 }
3647
3648 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3649 {
3650 for (uint32_t i = 0; i < fenceCount; ++i) {
3651 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3652 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3653 return false;
3654 }
3655 return true;
3656 }
3657
3658 VkResult radv_WaitForFences(
3659 VkDevice _device,
3660 uint32_t fenceCount,
3661 const VkFence* pFences,
3662 VkBool32 waitAll,
3663 uint64_t timeout)
3664 {
3665 RADV_FROM_HANDLE(radv_device, device, _device);
3666 timeout = radv_get_absolute_timeout(timeout);
3667
3668 if (device->always_use_syncobj &&
3669 radv_all_fences_syncobj(fenceCount, pFences))
3670 {
3671 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3672 if (!handles)
3673 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3674
3675 for (uint32_t i = 0; i < fenceCount; ++i) {
3676 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3677 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3678 }
3679
3680 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3681
3682 free(handles);
3683 return success ? VK_SUCCESS : VK_TIMEOUT;
3684 }
3685
3686 if (!waitAll && fenceCount > 1) {
3687 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3688 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3689 uint32_t wait_count = 0;
3690 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3691 if (!fences)
3692 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3693
3694 for (uint32_t i = 0; i < fenceCount; ++i) {
3695 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3696
3697 if (fence->signalled) {
3698 free(fences);
3699 return VK_SUCCESS;
3700 }
3701
3702 fences[wait_count++] = fence->fence;
3703 }
3704
3705 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3706 waitAll, timeout - radv_get_current_time());
3707
3708 free(fences);
3709 return success ? VK_SUCCESS : VK_TIMEOUT;
3710 }
3711
3712 while(radv_get_current_time() <= timeout) {
3713 for (uint32_t i = 0; i < fenceCount; ++i) {
3714 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3715 return VK_SUCCESS;
3716 }
3717 }
3718 return VK_TIMEOUT;
3719 }
3720
3721 for (uint32_t i = 0; i < fenceCount; ++i) {
3722 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3723 bool expired = false;
3724
3725 if (fence->temp_syncobj) {
3726 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3727 return VK_TIMEOUT;
3728 continue;
3729 }
3730
3731 if (fence->syncobj) {
3732 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3733 return VK_TIMEOUT;
3734 continue;
3735 }
3736
3737 if (fence->signalled)
3738 continue;
3739
3740 if (fence->fence) {
3741 if (!fence->submitted) {
3742 while(radv_get_current_time() <= timeout &&
3743 !fence->submitted)
3744 /* Do nothing */;
3745
3746 if (!fence->submitted)
3747 return VK_TIMEOUT;
3748
3749 /* Recheck as it may have been set by
3750 * submitting operations. */
3751
3752 if (fence->signalled)
3753 continue;
3754 }
3755
3756 expired = device->ws->fence_wait(device->ws,
3757 fence->fence,
3758 true, timeout);
3759 if (!expired)
3760 return VK_TIMEOUT;
3761 }
3762
3763 if (fence->fence_wsi) {
3764 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3765 if (result != VK_SUCCESS)
3766 return result;
3767 }
3768
3769 fence->signalled = true;
3770 }
3771
3772 return VK_SUCCESS;
3773 }
3774
3775 VkResult radv_ResetFences(VkDevice _device,
3776 uint32_t fenceCount,
3777 const VkFence *pFences)
3778 {
3779 RADV_FROM_HANDLE(radv_device, device, _device);
3780
3781 for (unsigned i = 0; i < fenceCount; ++i) {
3782 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3783 fence->submitted = fence->signalled = false;
3784
3785 /* Per spec, we first restore the permanent payload, and then reset, so
3786 * having a temp syncobj should not skip resetting the permanent syncobj. */
3787 if (fence->temp_syncobj) {
3788 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3789 fence->temp_syncobj = 0;
3790 }
3791
3792 if (fence->syncobj) {
3793 device->ws->reset_syncobj(device->ws, fence->syncobj);
3794 }
3795 }
3796
3797 return VK_SUCCESS;
3798 }
3799
3800 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3801 {
3802 RADV_FROM_HANDLE(radv_device, device, _device);
3803 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3804
3805 if (fence->temp_syncobj) {
3806 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3807 return success ? VK_SUCCESS : VK_NOT_READY;
3808 }
3809
3810 if (fence->syncobj) {
3811 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3812 return success ? VK_SUCCESS : VK_NOT_READY;
3813 }
3814
3815 if (fence->signalled)
3816 return VK_SUCCESS;
3817 if (!fence->submitted)
3818 return VK_NOT_READY;
3819 if (fence->fence) {
3820 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3821 return VK_NOT_READY;
3822 }
3823 if (fence->fence_wsi) {
3824 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3825
3826 if (result != VK_SUCCESS) {
3827 if (result == VK_TIMEOUT)
3828 return VK_NOT_READY;
3829 return result;
3830 }
3831 }
3832 return VK_SUCCESS;
3833 }
3834
3835
3836 // Queue semaphore functions
3837
3838 VkResult radv_CreateSemaphore(
3839 VkDevice _device,
3840 const VkSemaphoreCreateInfo* pCreateInfo,
3841 const VkAllocationCallbacks* pAllocator,
3842 VkSemaphore* pSemaphore)
3843 {
3844 RADV_FROM_HANDLE(radv_device, device, _device);
3845 const VkExportSemaphoreCreateInfo *export =
3846 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3847 VkExternalSemaphoreHandleTypeFlags handleTypes =
3848 export ? export->handleTypes : 0;
3849
3850 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3851 sizeof(*sem), 8,
3852 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3853 if (!sem)
3854 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3855
3856 sem->temp_syncobj = 0;
3857 /* create a syncobject if we are going to export this semaphore */
3858 if (device->always_use_syncobj || handleTypes) {
3859 assert (device->physical_device->rad_info.has_syncobj);
3860 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3861 if (ret) {
3862 vk_free2(&device->alloc, pAllocator, sem);
3863 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3864 }
3865 sem->sem = NULL;
3866 } else {
3867 sem->sem = device->ws->create_sem(device->ws);
3868 if (!sem->sem) {
3869 vk_free2(&device->alloc, pAllocator, sem);
3870 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3871 }
3872 sem->syncobj = 0;
3873 }
3874
3875 *pSemaphore = radv_semaphore_to_handle(sem);
3876 return VK_SUCCESS;
3877 }
3878
3879 void radv_DestroySemaphore(
3880 VkDevice _device,
3881 VkSemaphore _semaphore,
3882 const VkAllocationCallbacks* pAllocator)
3883 {
3884 RADV_FROM_HANDLE(radv_device, device, _device);
3885 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3886 if (!_semaphore)
3887 return;
3888
3889 if (sem->syncobj)
3890 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3891 else
3892 device->ws->destroy_sem(sem->sem);
3893 vk_free2(&device->alloc, pAllocator, sem);
3894 }
3895
3896 VkResult radv_CreateEvent(
3897 VkDevice _device,
3898 const VkEventCreateInfo* pCreateInfo,
3899 const VkAllocationCallbacks* pAllocator,
3900 VkEvent* pEvent)
3901 {
3902 RADV_FROM_HANDLE(radv_device, device, _device);
3903 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3904 sizeof(*event), 8,
3905 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3906
3907 if (!event)
3908 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3909
3910 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3911 RADEON_DOMAIN_GTT,
3912 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3913 RADV_BO_PRIORITY_FENCE);
3914 if (!event->bo) {
3915 vk_free2(&device->alloc, pAllocator, event);
3916 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3917 }
3918
3919 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3920
3921 *pEvent = radv_event_to_handle(event);
3922
3923 return VK_SUCCESS;
3924 }
3925
3926 void radv_DestroyEvent(
3927 VkDevice _device,
3928 VkEvent _event,
3929 const VkAllocationCallbacks* pAllocator)
3930 {
3931 RADV_FROM_HANDLE(radv_device, device, _device);
3932 RADV_FROM_HANDLE(radv_event, event, _event);
3933
3934 if (!event)
3935 return;
3936 device->ws->buffer_destroy(event->bo);
3937 vk_free2(&device->alloc, pAllocator, event);
3938 }
3939
3940 VkResult radv_GetEventStatus(
3941 VkDevice _device,
3942 VkEvent _event)
3943 {
3944 RADV_FROM_HANDLE(radv_event, event, _event);
3945
3946 if (*event->map == 1)
3947 return VK_EVENT_SET;
3948 return VK_EVENT_RESET;
3949 }
3950
3951 VkResult radv_SetEvent(
3952 VkDevice _device,
3953 VkEvent _event)
3954 {
3955 RADV_FROM_HANDLE(radv_event, event, _event);
3956 *event->map = 1;
3957
3958 return VK_SUCCESS;
3959 }
3960
3961 VkResult radv_ResetEvent(
3962 VkDevice _device,
3963 VkEvent _event)
3964 {
3965 RADV_FROM_HANDLE(radv_event, event, _event);
3966 *event->map = 0;
3967
3968 return VK_SUCCESS;
3969 }
3970
3971 VkResult radv_CreateBuffer(
3972 VkDevice _device,
3973 const VkBufferCreateInfo* pCreateInfo,
3974 const VkAllocationCallbacks* pAllocator,
3975 VkBuffer* pBuffer)
3976 {
3977 RADV_FROM_HANDLE(radv_device, device, _device);
3978 struct radv_buffer *buffer;
3979
3980 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3981
3982 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3983 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3984 if (buffer == NULL)
3985 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3986
3987 buffer->size = pCreateInfo->size;
3988 buffer->usage = pCreateInfo->usage;
3989 buffer->bo = NULL;
3990 buffer->offset = 0;
3991 buffer->flags = pCreateInfo->flags;
3992
3993 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3994 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
3995
3996 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3997 buffer->bo = device->ws->buffer_create(device->ws,
3998 align64(buffer->size, 4096),
3999 4096, 0, RADEON_FLAG_VIRTUAL,
4000 RADV_BO_PRIORITY_VIRTUAL);
4001 if (!buffer->bo) {
4002 vk_free2(&device->alloc, pAllocator, buffer);
4003 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4004 }
4005 }
4006
4007 *pBuffer = radv_buffer_to_handle(buffer);
4008
4009 return VK_SUCCESS;
4010 }
4011
4012 void radv_DestroyBuffer(
4013 VkDevice _device,
4014 VkBuffer _buffer,
4015 const VkAllocationCallbacks* pAllocator)
4016 {
4017 RADV_FROM_HANDLE(radv_device, device, _device);
4018 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4019
4020 if (!buffer)
4021 return;
4022
4023 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4024 device->ws->buffer_destroy(buffer->bo);
4025
4026 vk_free2(&device->alloc, pAllocator, buffer);
4027 }
4028
4029 static inline unsigned
4030 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4031 {
4032 if (stencil)
4033 return image->surface.u.legacy.stencil_tiling_index[level];
4034 else
4035 return image->surface.u.legacy.tiling_index[level];
4036 }
4037
4038 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4039 {
4040 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4041 }
4042
4043 static uint32_t
4044 radv_init_dcc_control_reg(struct radv_device *device,
4045 struct radv_image_view *iview)
4046 {
4047 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4048 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4049 unsigned max_compressed_block_size;
4050 unsigned independent_64b_blocks;
4051
4052 if (!radv_image_has_dcc(iview->image))
4053 return 0;
4054
4055 if (iview->image->info.samples > 1) {
4056 if (iview->image->surface.bpe == 1)
4057 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4058 else if (iview->image->surface.bpe == 2)
4059 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4060 }
4061
4062 if (!device->physical_device->rad_info.has_dedicated_vram) {
4063 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4064 * dGPU and 64 for APU because all of our APUs to date use
4065 * DIMMs which have a request granularity size of 64B while all
4066 * other chips have a 32B request size.
4067 */
4068 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4069 }
4070
4071 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4072 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4073 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4074 /* If this DCC image is potentially going to be used in texture
4075 * fetches, we need some special settings.
4076 */
4077 independent_64b_blocks = 1;
4078 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4079 } else {
4080 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4081 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4082 * big as possible for better compression state.
4083 */
4084 independent_64b_blocks = 0;
4085 max_compressed_block_size = max_uncompressed_block_size;
4086 }
4087
4088 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4089 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4090 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4091 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4092 }
4093
4094 static void
4095 radv_initialise_color_surface(struct radv_device *device,
4096 struct radv_color_buffer_info *cb,
4097 struct radv_image_view *iview)
4098 {
4099 const struct vk_format_description *desc;
4100 unsigned ntype, format, swap, endian;
4101 unsigned blend_clamp = 0, blend_bypass = 0;
4102 uint64_t va;
4103 const struct radeon_surf *surf = &iview->image->surface;
4104
4105 desc = vk_format_description(iview->vk_format);
4106
4107 memset(cb, 0, sizeof(*cb));
4108
4109 /* Intensity is implemented as Red, so treat it that way. */
4110 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4111
4112 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4113
4114 cb->cb_color_base = va >> 8;
4115
4116 if (device->physical_device->rad_info.chip_class >= GFX9) {
4117 struct gfx9_surf_meta_flags meta;
4118 if (iview->image->dcc_offset)
4119 meta = iview->image->surface.u.gfx9.dcc;
4120 else
4121 meta = iview->image->surface.u.gfx9.cmask;
4122
4123 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4124 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4125 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4126 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4127
4128 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4129 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4130 } else {
4131 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4132 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4133
4134 cb->cb_color_base += level_info->offset >> 8;
4135 if (level_info->mode == RADEON_SURF_MODE_2D)
4136 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4137
4138 pitch_tile_max = level_info->nblk_x / 8 - 1;
4139 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4140 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4141
4142 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4143 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4144 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4145
4146 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4147
4148 if (radv_image_has_fmask(iview->image)) {
4149 if (device->physical_device->rad_info.chip_class >= CIK)
4150 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4151 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4152 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4153 } else {
4154 /* This must be set for fast clear to work without FMASK. */
4155 if (device->physical_device->rad_info.chip_class >= CIK)
4156 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4157 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4158 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4159 }
4160 }
4161
4162 /* CMASK variables */
4163 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4164 va += iview->image->cmask.offset;
4165 cb->cb_color_cmask = va >> 8;
4166
4167 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4168 va += iview->image->dcc_offset;
4169 cb->cb_dcc_base = va >> 8;
4170 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4171
4172 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4173 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4174 S_028C6C_SLICE_MAX(max_slice);
4175
4176 if (iview->image->info.samples > 1) {
4177 unsigned log_samples = util_logbase2(iview->image->info.samples);
4178
4179 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4180 S_028C74_NUM_FRAGMENTS(log_samples);
4181 }
4182
4183 if (radv_image_has_fmask(iview->image)) {
4184 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4185 cb->cb_color_fmask = va >> 8;
4186 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4187 } else {
4188 cb->cb_color_fmask = cb->cb_color_base;
4189 }
4190
4191 ntype = radv_translate_color_numformat(iview->vk_format,
4192 desc,
4193 vk_format_get_first_non_void_channel(iview->vk_format));
4194 format = radv_translate_colorformat(iview->vk_format);
4195 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4196 radv_finishme("Illegal color\n");
4197 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4198 endian = radv_colorformat_endian_swap(format);
4199
4200 /* blend clamp should be set for all NORM/SRGB types */
4201 if (ntype == V_028C70_NUMBER_UNORM ||
4202 ntype == V_028C70_NUMBER_SNORM ||
4203 ntype == V_028C70_NUMBER_SRGB)
4204 blend_clamp = 1;
4205
4206 /* set blend bypass according to docs if SINT/UINT or
4207 8/24 COLOR variants */
4208 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4209 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4210 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4211 blend_clamp = 0;
4212 blend_bypass = 1;
4213 }
4214 #if 0
4215 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4216 (format == V_028C70_COLOR_8 ||
4217 format == V_028C70_COLOR_8_8 ||
4218 format == V_028C70_COLOR_8_8_8_8))
4219 ->color_is_int8 = true;
4220 #endif
4221 cb->cb_color_info = S_028C70_FORMAT(format) |
4222 S_028C70_COMP_SWAP(swap) |
4223 S_028C70_BLEND_CLAMP(blend_clamp) |
4224 S_028C70_BLEND_BYPASS(blend_bypass) |
4225 S_028C70_SIMPLE_FLOAT(1) |
4226 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4227 ntype != V_028C70_NUMBER_SNORM &&
4228 ntype != V_028C70_NUMBER_SRGB &&
4229 format != V_028C70_COLOR_8_24 &&
4230 format != V_028C70_COLOR_24_8) |
4231 S_028C70_NUMBER_TYPE(ntype) |
4232 S_028C70_ENDIAN(endian);
4233 if (radv_image_has_fmask(iview->image)) {
4234 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4235 if (device->physical_device->rad_info.chip_class == SI) {
4236 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4237 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4238 }
4239 }
4240
4241 if (radv_image_has_cmask(iview->image) &&
4242 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4243 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4244
4245 if (radv_dcc_enabled(iview->image, iview->base_mip))
4246 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4247
4248 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4249
4250 /* This must be set for fast clear to work without FMASK. */
4251 if (!radv_image_has_fmask(iview->image) &&
4252 device->physical_device->rad_info.chip_class == SI) {
4253 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4254 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4255 }
4256
4257 if (device->physical_device->rad_info.chip_class >= GFX9) {
4258 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4259 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4260
4261 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4262 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4263 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4264 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4265 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4266 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4267 }
4268 }
4269
4270 static unsigned
4271 radv_calc_decompress_on_z_planes(struct radv_device *device,
4272 struct radv_image_view *iview)
4273 {
4274 unsigned max_zplanes = 0;
4275
4276 assert(radv_image_is_tc_compat_htile(iview->image));
4277
4278 if (device->physical_device->rad_info.chip_class >= GFX9) {
4279 /* Default value for 32-bit depth surfaces. */
4280 max_zplanes = 4;
4281
4282 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4283 iview->image->info.samples > 1)
4284 max_zplanes = 2;
4285
4286 max_zplanes = max_zplanes + 1;
4287 } else {
4288 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4289 /* Do not enable Z plane compression for 16-bit depth
4290 * surfaces because isn't supported on GFX8. Only
4291 * 32-bit depth surfaces are supported by the hardware.
4292 * This allows to maintain shader compatibility and to
4293 * reduce the number of depth decompressions.
4294 */
4295 max_zplanes = 1;
4296 } else {
4297 if (iview->image->info.samples <= 1)
4298 max_zplanes = 5;
4299 else if (iview->image->info.samples <= 4)
4300 max_zplanes = 3;
4301 else
4302 max_zplanes = 2;
4303 }
4304 }
4305
4306 return max_zplanes;
4307 }
4308
4309 static void
4310 radv_initialise_ds_surface(struct radv_device *device,
4311 struct radv_ds_buffer_info *ds,
4312 struct radv_image_view *iview)
4313 {
4314 unsigned level = iview->base_mip;
4315 unsigned format, stencil_format;
4316 uint64_t va, s_offs, z_offs;
4317 bool stencil_only = false;
4318 memset(ds, 0, sizeof(*ds));
4319 switch (iview->image->vk_format) {
4320 case VK_FORMAT_D24_UNORM_S8_UINT:
4321 case VK_FORMAT_X8_D24_UNORM_PACK32:
4322 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4323 ds->offset_scale = 2.0f;
4324 break;
4325 case VK_FORMAT_D16_UNORM:
4326 case VK_FORMAT_D16_UNORM_S8_UINT:
4327 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4328 ds->offset_scale = 4.0f;
4329 break;
4330 case VK_FORMAT_D32_SFLOAT:
4331 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4332 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4333 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4334 ds->offset_scale = 1.0f;
4335 break;
4336 case VK_FORMAT_S8_UINT:
4337 stencil_only = true;
4338 break;
4339 default:
4340 break;
4341 }
4342
4343 format = radv_translate_dbformat(iview->image->vk_format);
4344 stencil_format = iview->image->surface.has_stencil ?
4345 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4346
4347 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4348 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4349 S_028008_SLICE_MAX(max_slice);
4350
4351 ds->db_htile_data_base = 0;
4352 ds->db_htile_surface = 0;
4353
4354 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4355 s_offs = z_offs = va;
4356
4357 if (device->physical_device->rad_info.chip_class >= GFX9) {
4358 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4359 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4360
4361 ds->db_z_info = S_028038_FORMAT(format) |
4362 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4363 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4364 S_028038_MAXMIP(iview->image->info.levels - 1) |
4365 S_028038_ZRANGE_PRECISION(1);
4366 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4367 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4368
4369 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4370 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4371 ds->db_depth_view |= S_028008_MIPID(level);
4372
4373 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4374 S_02801C_Y_MAX(iview->image->info.height - 1);
4375
4376 if (radv_htile_enabled(iview->image, level)) {
4377 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4378
4379 if (radv_image_is_tc_compat_htile(iview->image)) {
4380 unsigned max_zplanes =
4381 radv_calc_decompress_on_z_planes(device, iview);
4382
4383 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4384 S_028038_ITERATE_FLUSH(1);
4385 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4386 }
4387
4388 if (!iview->image->surface.has_stencil)
4389 /* Use all of the htile_buffer for depth if there's no stencil. */
4390 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4391 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4392 iview->image->htile_offset;
4393 ds->db_htile_data_base = va >> 8;
4394 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4395 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4396 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4397 }
4398 } else {
4399 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4400
4401 if (stencil_only)
4402 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4403
4404 z_offs += iview->image->surface.u.legacy.level[level].offset;
4405 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4406
4407 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4408 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4409 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4410
4411 if (iview->image->info.samples > 1)
4412 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4413
4414 if (device->physical_device->rad_info.chip_class >= CIK) {
4415 struct radeon_info *info = &device->physical_device->rad_info;
4416 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4417 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4418 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4419 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4420 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4421 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4422
4423 if (stencil_only)
4424 tile_mode = stencil_tile_mode;
4425
4426 ds->db_depth_info |=
4427 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4428 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4429 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4430 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4431 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4432 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4433 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4434 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4435 } else {
4436 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4437 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4438 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4439 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4440 if (stencil_only)
4441 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4442 }
4443
4444 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4445 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4446 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4447
4448 if (radv_htile_enabled(iview->image, level)) {
4449 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4450
4451 if (!iview->image->surface.has_stencil &&
4452 !radv_image_is_tc_compat_htile(iview->image))
4453 /* Use all of the htile_buffer for depth if there's no stencil. */
4454 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4455
4456 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4457 iview->image->htile_offset;
4458 ds->db_htile_data_base = va >> 8;
4459 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4460
4461 if (radv_image_is_tc_compat_htile(iview->image)) {
4462 unsigned max_zplanes =
4463 radv_calc_decompress_on_z_planes(device, iview);
4464
4465 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4466 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4467 }
4468 }
4469 }
4470
4471 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4472 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4473 }
4474
4475 VkResult radv_CreateFramebuffer(
4476 VkDevice _device,
4477 const VkFramebufferCreateInfo* pCreateInfo,
4478 const VkAllocationCallbacks* pAllocator,
4479 VkFramebuffer* pFramebuffer)
4480 {
4481 RADV_FROM_HANDLE(radv_device, device, _device);
4482 struct radv_framebuffer *framebuffer;
4483
4484 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4485
4486 size_t size = sizeof(*framebuffer) +
4487 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4488 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4489 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4490 if (framebuffer == NULL)
4491 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4492
4493 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4494 framebuffer->width = pCreateInfo->width;
4495 framebuffer->height = pCreateInfo->height;
4496 framebuffer->layers = pCreateInfo->layers;
4497 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4498 VkImageView _iview = pCreateInfo->pAttachments[i];
4499 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4500 framebuffer->attachments[i].attachment = iview;
4501 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4502 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4503 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4504 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4505 }
4506 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4507 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4508 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4509 }
4510
4511 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4512 return VK_SUCCESS;
4513 }
4514
4515 void radv_DestroyFramebuffer(
4516 VkDevice _device,
4517 VkFramebuffer _fb,
4518 const VkAllocationCallbacks* pAllocator)
4519 {
4520 RADV_FROM_HANDLE(radv_device, device, _device);
4521 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4522
4523 if (!fb)
4524 return;
4525 vk_free2(&device->alloc, pAllocator, fb);
4526 }
4527
4528 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4529 {
4530 switch (address_mode) {
4531 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4532 return V_008F30_SQ_TEX_WRAP;
4533 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4534 return V_008F30_SQ_TEX_MIRROR;
4535 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4536 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4537 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4538 return V_008F30_SQ_TEX_CLAMP_BORDER;
4539 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4540 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4541 default:
4542 unreachable("illegal tex wrap mode");
4543 break;
4544 }
4545 }
4546
4547 static unsigned
4548 radv_tex_compare(VkCompareOp op)
4549 {
4550 switch (op) {
4551 case VK_COMPARE_OP_NEVER:
4552 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4553 case VK_COMPARE_OP_LESS:
4554 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4555 case VK_COMPARE_OP_EQUAL:
4556 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4557 case VK_COMPARE_OP_LESS_OR_EQUAL:
4558 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4559 case VK_COMPARE_OP_GREATER:
4560 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4561 case VK_COMPARE_OP_NOT_EQUAL:
4562 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4563 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4564 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4565 case VK_COMPARE_OP_ALWAYS:
4566 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4567 default:
4568 unreachable("illegal compare mode");
4569 break;
4570 }
4571 }
4572
4573 static unsigned
4574 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4575 {
4576 switch (filter) {
4577 case VK_FILTER_NEAREST:
4578 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4579 V_008F38_SQ_TEX_XY_FILTER_POINT);
4580 case VK_FILTER_LINEAR:
4581 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4582 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4583 case VK_FILTER_CUBIC_IMG:
4584 default:
4585 fprintf(stderr, "illegal texture filter");
4586 return 0;
4587 }
4588 }
4589
4590 static unsigned
4591 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4592 {
4593 switch (mode) {
4594 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4595 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4596 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4597 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4598 default:
4599 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4600 }
4601 }
4602
4603 static unsigned
4604 radv_tex_bordercolor(VkBorderColor bcolor)
4605 {
4606 switch (bcolor) {
4607 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4608 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4609 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4610 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4611 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4612 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4613 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4614 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4615 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4616 default:
4617 break;
4618 }
4619 return 0;
4620 }
4621
4622 static unsigned
4623 radv_tex_aniso_filter(unsigned filter)
4624 {
4625 if (filter < 2)
4626 return 0;
4627 if (filter < 4)
4628 return 1;
4629 if (filter < 8)
4630 return 2;
4631 if (filter < 16)
4632 return 3;
4633 return 4;
4634 }
4635
4636 static unsigned
4637 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4638 {
4639 switch (mode) {
4640 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4641 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4642 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4643 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4644 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4645 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4646 default:
4647 break;
4648 }
4649 return 0;
4650 }
4651
4652 static uint32_t
4653 radv_get_max_anisotropy(struct radv_device *device,
4654 const VkSamplerCreateInfo *pCreateInfo)
4655 {
4656 if (device->force_aniso >= 0)
4657 return device->force_aniso;
4658
4659 if (pCreateInfo->anisotropyEnable &&
4660 pCreateInfo->maxAnisotropy > 1.0f)
4661 return (uint32_t)pCreateInfo->maxAnisotropy;
4662
4663 return 0;
4664 }
4665
4666 static void
4667 radv_init_sampler(struct radv_device *device,
4668 struct radv_sampler *sampler,
4669 const VkSamplerCreateInfo *pCreateInfo)
4670 {
4671 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4672 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4673 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4674 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4675
4676 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4677 vk_find_struct_const(pCreateInfo->pNext,
4678 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4679 if (sampler_reduction)
4680 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4681
4682 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4683 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4684 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4685 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4686 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4687 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4688 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4689 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4690 S_008F30_DISABLE_CUBE_WRAP(0) |
4691 S_008F30_COMPAT_MODE(is_vi) |
4692 S_008F30_FILTER_MODE(filter_mode));
4693 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4694 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4695 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4696 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4697 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4698 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4699 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4700 S_008F38_MIP_POINT_PRECLAMP(0) |
4701 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4702 S_008F38_FILTER_PREC_FIX(1) |
4703 S_008F38_ANISO_OVERRIDE(is_vi));
4704 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4705 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4706 }
4707
4708 VkResult radv_CreateSampler(
4709 VkDevice _device,
4710 const VkSamplerCreateInfo* pCreateInfo,
4711 const VkAllocationCallbacks* pAllocator,
4712 VkSampler* pSampler)
4713 {
4714 RADV_FROM_HANDLE(radv_device, device, _device);
4715 struct radv_sampler *sampler;
4716
4717 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4718
4719 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4720 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4721 if (!sampler)
4722 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4723
4724 radv_init_sampler(device, sampler, pCreateInfo);
4725 *pSampler = radv_sampler_to_handle(sampler);
4726
4727 return VK_SUCCESS;
4728 }
4729
4730 void radv_DestroySampler(
4731 VkDevice _device,
4732 VkSampler _sampler,
4733 const VkAllocationCallbacks* pAllocator)
4734 {
4735 RADV_FROM_HANDLE(radv_device, device, _device);
4736 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4737
4738 if (!sampler)
4739 return;
4740 vk_free2(&device->alloc, pAllocator, sampler);
4741 }
4742
4743 /* vk_icd.h does not declare this function, so we declare it here to
4744 * suppress Wmissing-prototypes.
4745 */
4746 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4747 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4748
4749 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4750 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4751 {
4752 /* For the full details on loader interface versioning, see
4753 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4754 * What follows is a condensed summary, to help you navigate the large and
4755 * confusing official doc.
4756 *
4757 * - Loader interface v0 is incompatible with later versions. We don't
4758 * support it.
4759 *
4760 * - In loader interface v1:
4761 * - The first ICD entrypoint called by the loader is
4762 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4763 * entrypoint.
4764 * - The ICD must statically expose no other Vulkan symbol unless it is
4765 * linked with -Bsymbolic.
4766 * - Each dispatchable Vulkan handle created by the ICD must be
4767 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4768 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4769 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4770 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4771 * such loader-managed surfaces.
4772 *
4773 * - Loader interface v2 differs from v1 in:
4774 * - The first ICD entrypoint called by the loader is
4775 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4776 * statically expose this entrypoint.
4777 *
4778 * - Loader interface v3 differs from v2 in:
4779 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4780 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4781 * because the loader no longer does so.
4782 */
4783 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4784 return VK_SUCCESS;
4785 }
4786
4787 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4788 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4789 int *pFD)
4790 {
4791 RADV_FROM_HANDLE(radv_device, device, _device);
4792 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4793
4794 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4795
4796 /* At the moment, we support only the below handle types. */
4797 assert(pGetFdInfo->handleType ==
4798 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4799 pGetFdInfo->handleType ==
4800 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4801
4802 bool ret = radv_get_memory_fd(device, memory, pFD);
4803 if (ret == false)
4804 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4805 return VK_SUCCESS;
4806 }
4807
4808 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4809 VkExternalMemoryHandleTypeFlagBits handleType,
4810 int fd,
4811 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4812 {
4813 RADV_FROM_HANDLE(radv_device, device, _device);
4814
4815 switch (handleType) {
4816 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4817 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4818 return VK_SUCCESS;
4819
4820 default:
4821 /* The valid usage section for this function says:
4822 *
4823 * "handleType must not be one of the handle types defined as
4824 * opaque."
4825 *
4826 * So opaque handle types fall into the default "unsupported" case.
4827 */
4828 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4829 }
4830 }
4831
4832 static VkResult radv_import_opaque_fd(struct radv_device *device,
4833 int fd,
4834 uint32_t *syncobj)
4835 {
4836 uint32_t syncobj_handle = 0;
4837 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4838 if (ret != 0)
4839 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4840
4841 if (*syncobj)
4842 device->ws->destroy_syncobj(device->ws, *syncobj);
4843
4844 *syncobj = syncobj_handle;
4845 close(fd);
4846
4847 return VK_SUCCESS;
4848 }
4849
4850 static VkResult radv_import_sync_fd(struct radv_device *device,
4851 int fd,
4852 uint32_t *syncobj)
4853 {
4854 /* If we create a syncobj we do it locally so that if we have an error, we don't
4855 * leave a syncobj in an undetermined state in the fence. */
4856 uint32_t syncobj_handle = *syncobj;
4857 if (!syncobj_handle) {
4858 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4859 if (ret) {
4860 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4861 }
4862 }
4863
4864 if (fd == -1) {
4865 device->ws->signal_syncobj(device->ws, syncobj_handle);
4866 } else {
4867 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4868 if (ret != 0)
4869 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4870 }
4871
4872 *syncobj = syncobj_handle;
4873 if (fd != -1)
4874 close(fd);
4875
4876 return VK_SUCCESS;
4877 }
4878
4879 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4880 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4881 {
4882 RADV_FROM_HANDLE(radv_device, device, _device);
4883 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4884 uint32_t *syncobj_dst = NULL;
4885
4886 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4887 syncobj_dst = &sem->temp_syncobj;
4888 } else {
4889 syncobj_dst = &sem->syncobj;
4890 }
4891
4892 switch(pImportSemaphoreFdInfo->handleType) {
4893 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4894 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4895 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4896 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4897 default:
4898 unreachable("Unhandled semaphore handle type");
4899 }
4900 }
4901
4902 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4903 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4904 int *pFd)
4905 {
4906 RADV_FROM_HANDLE(radv_device, device, _device);
4907 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4908 int ret;
4909 uint32_t syncobj_handle;
4910
4911 if (sem->temp_syncobj)
4912 syncobj_handle = sem->temp_syncobj;
4913 else
4914 syncobj_handle = sem->syncobj;
4915
4916 switch(pGetFdInfo->handleType) {
4917 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4918 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4919 break;
4920 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4921 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4922 if (!ret) {
4923 if (sem->temp_syncobj) {
4924 close (sem->temp_syncobj);
4925 sem->temp_syncobj = 0;
4926 } else {
4927 device->ws->reset_syncobj(device->ws, syncobj_handle);
4928 }
4929 }
4930 break;
4931 default:
4932 unreachable("Unhandled semaphore handle type");
4933 }
4934
4935 if (ret)
4936 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4937 return VK_SUCCESS;
4938 }
4939
4940 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4941 VkPhysicalDevice physicalDevice,
4942 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4943 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4944 {
4945 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4946
4947 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4948 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4949 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4950 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4951 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4952 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4953 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4954 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4955 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4956 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4957 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4958 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4959 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4960 } else {
4961 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4962 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4963 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4964 }
4965 }
4966
4967 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4968 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4969 {
4970 RADV_FROM_HANDLE(radv_device, device, _device);
4971 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4972 uint32_t *syncobj_dst = NULL;
4973
4974
4975 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
4976 syncobj_dst = &fence->temp_syncobj;
4977 } else {
4978 syncobj_dst = &fence->syncobj;
4979 }
4980
4981 switch(pImportFenceFdInfo->handleType) {
4982 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
4983 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4984 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
4985 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4986 default:
4987 unreachable("Unhandled fence handle type");
4988 }
4989 }
4990
4991 VkResult radv_GetFenceFdKHR(VkDevice _device,
4992 const VkFenceGetFdInfoKHR *pGetFdInfo,
4993 int *pFd)
4994 {
4995 RADV_FROM_HANDLE(radv_device, device, _device);
4996 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4997 int ret;
4998 uint32_t syncobj_handle;
4999
5000 if (fence->temp_syncobj)
5001 syncobj_handle = fence->temp_syncobj;
5002 else
5003 syncobj_handle = fence->syncobj;
5004
5005 switch(pGetFdInfo->handleType) {
5006 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5007 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5008 break;
5009 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5010 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5011 if (!ret) {
5012 if (fence->temp_syncobj) {
5013 close (fence->temp_syncobj);
5014 fence->temp_syncobj = 0;
5015 } else {
5016 device->ws->reset_syncobj(device->ws, syncobj_handle);
5017 }
5018 }
5019 break;
5020 default:
5021 unreachable("Unhandled fence handle type");
5022 }
5023
5024 if (ret)
5025 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5026 return VK_SUCCESS;
5027 }
5028
5029 void radv_GetPhysicalDeviceExternalFenceProperties(
5030 VkPhysicalDevice physicalDevice,
5031 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5032 VkExternalFenceProperties *pExternalFenceProperties)
5033 {
5034 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5035
5036 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5037 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5038 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5039 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5040 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5041 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5042 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5043 } else {
5044 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5045 pExternalFenceProperties->compatibleHandleTypes = 0;
5046 pExternalFenceProperties->externalFenceFeatures = 0;
5047 }
5048 }
5049
5050 VkResult
5051 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5052 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5053 const VkAllocationCallbacks* pAllocator,
5054 VkDebugReportCallbackEXT* pCallback)
5055 {
5056 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5057 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5058 pCreateInfo, pAllocator, &instance->alloc,
5059 pCallback);
5060 }
5061
5062 void
5063 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5064 VkDebugReportCallbackEXT _callback,
5065 const VkAllocationCallbacks* pAllocator)
5066 {
5067 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5068 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5069 _callback, pAllocator, &instance->alloc);
5070 }
5071
5072 void
5073 radv_DebugReportMessageEXT(VkInstance _instance,
5074 VkDebugReportFlagsEXT flags,
5075 VkDebugReportObjectTypeEXT objectType,
5076 uint64_t object,
5077 size_t location,
5078 int32_t messageCode,
5079 const char* pLayerPrefix,
5080 const char* pMessage)
5081 {
5082 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5083 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5084 object, location, messageCode, pLayerPrefix, pMessage);
5085 }
5086
5087 void
5088 radv_GetDeviceGroupPeerMemoryFeatures(
5089 VkDevice device,
5090 uint32_t heapIndex,
5091 uint32_t localDeviceIndex,
5092 uint32_t remoteDeviceIndex,
5093 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5094 {
5095 assert(localDeviceIndex == remoteDeviceIndex);
5096
5097 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5098 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5099 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5100 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5101 }
5102
5103 static const VkTimeDomainEXT radv_time_domains[] = {
5104 VK_TIME_DOMAIN_DEVICE_EXT,
5105 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5106 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5107 };
5108
5109 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5110 VkPhysicalDevice physicalDevice,
5111 uint32_t *pTimeDomainCount,
5112 VkTimeDomainEXT *pTimeDomains)
5113 {
5114 int d;
5115 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5116
5117 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5118 vk_outarray_append(&out, i) {
5119 *i = radv_time_domains[d];
5120 }
5121 }
5122
5123 return vk_outarray_status(&out);
5124 }
5125
5126 static uint64_t
5127 radv_clock_gettime(clockid_t clock_id)
5128 {
5129 struct timespec current;
5130 int ret;
5131
5132 ret = clock_gettime(clock_id, &current);
5133 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5134 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5135 if (ret < 0)
5136 return 0;
5137
5138 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5139 }
5140
5141 VkResult radv_GetCalibratedTimestampsEXT(
5142 VkDevice _device,
5143 uint32_t timestampCount,
5144 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5145 uint64_t *pTimestamps,
5146 uint64_t *pMaxDeviation)
5147 {
5148 RADV_FROM_HANDLE(radv_device, device, _device);
5149 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5150 int d;
5151 uint64_t begin, end;
5152 uint64_t max_clock_period = 0;
5153
5154 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5155
5156 for (d = 0; d < timestampCount; d++) {
5157 switch (pTimestampInfos[d].timeDomain) {
5158 case VK_TIME_DOMAIN_DEVICE_EXT:
5159 pTimestamps[d] = device->ws->query_value(device->ws,
5160 RADEON_TIMESTAMP);
5161 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5162 max_clock_period = MAX2(max_clock_period, device_period);
5163 break;
5164 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5165 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5166 max_clock_period = MAX2(max_clock_period, 1);
5167 break;
5168
5169 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5170 pTimestamps[d] = begin;
5171 break;
5172 default:
5173 pTimestamps[d] = 0;
5174 break;
5175 }
5176 }
5177
5178 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5179
5180 /*
5181 * The maximum deviation is the sum of the interval over which we
5182 * perform the sampling and the maximum period of any sampled
5183 * clock. That's because the maximum skew between any two sampled
5184 * clock edges is when the sampled clock with the largest period is
5185 * sampled at the end of that period but right at the beginning of the
5186 * sampling interval and some other clock is sampled right at the
5187 * begining of its sampling period and right at the end of the
5188 * sampling interval. Let's assume the GPU has the longest clock
5189 * period and that the application is sampling GPU and monotonic:
5190 *
5191 * s e
5192 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5193 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5194 *
5195 * g
5196 * 0 1 2 3
5197 * GPU -----_____-----_____-----_____-----_____
5198 *
5199 * m
5200 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5201 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5202 *
5203 * Interval <----------------->
5204 * Deviation <-------------------------->
5205 *
5206 * s = read(raw) 2
5207 * g = read(GPU) 1
5208 * m = read(monotonic) 2
5209 * e = read(raw) b
5210 *
5211 * We round the sample interval up by one tick to cover sampling error
5212 * in the interval clock
5213 */
5214
5215 uint64_t sample_interval = end - begin + 1;
5216
5217 *pMaxDeviation = sample_interval + max_clock_period;
5218
5219 return VK_SUCCESS;
5220 }