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radv: print a big warning when RADV_TRACE_FILE is set
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 }
484 }
485
486 static int radv_get_instance_extension_index(const char *name)
487 {
488 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
489 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
490 return i;
491 }
492 return -1;
493 }
494
495
496 VkResult radv_CreateInstance(
497 const VkInstanceCreateInfo* pCreateInfo,
498 const VkAllocationCallbacks* pAllocator,
499 VkInstance* pInstance)
500 {
501 struct radv_instance *instance;
502 VkResult result;
503
504 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
505
506 uint32_t client_version;
507 if (pCreateInfo->pApplicationInfo &&
508 pCreateInfo->pApplicationInfo->apiVersion != 0) {
509 client_version = pCreateInfo->pApplicationInfo->apiVersion;
510 } else {
511 radv_EnumerateInstanceVersion(&client_version);
512 }
513
514 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
515 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
516 if (!instance)
517 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
518
519 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
520
521 if (pAllocator)
522 instance->alloc = *pAllocator;
523 else
524 instance->alloc = default_alloc;
525
526 instance->apiVersion = client_version;
527 instance->physicalDeviceCount = -1;
528
529 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
530 radv_debug_options);
531
532 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
533 radv_perftest_options);
534
535
536 if (instance->debug_flags & RADV_DEBUG_STARTUP)
537 radv_logi("Created an instance");
538
539 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
540 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
541 int index = radv_get_instance_extension_index(ext_name);
542
543 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
544 vk_free2(&default_alloc, pAllocator, instance);
545 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
546 }
547
548 instance->enabled_extensions.extensions[index] = true;
549 }
550
551 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
552 if (result != VK_SUCCESS) {
553 vk_free2(&default_alloc, pAllocator, instance);
554 return vk_error(instance, result);
555 }
556
557 _mesa_locale_init();
558
559 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
560
561 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
562
563 *pInstance = radv_instance_to_handle(instance);
564
565 return VK_SUCCESS;
566 }
567
568 void radv_DestroyInstance(
569 VkInstance _instance,
570 const VkAllocationCallbacks* pAllocator)
571 {
572 RADV_FROM_HANDLE(radv_instance, instance, _instance);
573
574 if (!instance)
575 return;
576
577 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
578 radv_physical_device_finish(instance->physicalDevices + i);
579 }
580
581 VG(VALGRIND_DESTROY_MEMPOOL(instance));
582
583 _mesa_locale_fini();
584
585 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
586
587 vk_free(&instance->alloc, instance);
588 }
589
590 static VkResult
591 radv_enumerate_devices(struct radv_instance *instance)
592 {
593 /* TODO: Check for more devices ? */
594 drmDevicePtr devices[8];
595 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
596 int max_devices;
597
598 instance->physicalDeviceCount = 0;
599
600 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
601
602 if (instance->debug_flags & RADV_DEBUG_STARTUP)
603 radv_logi("Found %d drm nodes", max_devices);
604
605 if (max_devices < 1)
606 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
607
608 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
609 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
610 devices[i]->bustype == DRM_BUS_PCI &&
611 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
612
613 result = radv_physical_device_init(instance->physicalDevices +
614 instance->physicalDeviceCount,
615 instance,
616 devices[i]);
617 if (result == VK_SUCCESS)
618 ++instance->physicalDeviceCount;
619 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
620 break;
621 }
622 }
623 drmFreeDevices(devices, max_devices);
624
625 return result;
626 }
627
628 VkResult radv_EnumeratePhysicalDevices(
629 VkInstance _instance,
630 uint32_t* pPhysicalDeviceCount,
631 VkPhysicalDevice* pPhysicalDevices)
632 {
633 RADV_FROM_HANDLE(radv_instance, instance, _instance);
634 VkResult result;
635
636 if (instance->physicalDeviceCount < 0) {
637 result = radv_enumerate_devices(instance);
638 if (result != VK_SUCCESS &&
639 result != VK_ERROR_INCOMPATIBLE_DRIVER)
640 return result;
641 }
642
643 if (!pPhysicalDevices) {
644 *pPhysicalDeviceCount = instance->physicalDeviceCount;
645 } else {
646 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
647 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
648 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
649 }
650
651 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
652 : VK_SUCCESS;
653 }
654
655 VkResult radv_EnumeratePhysicalDeviceGroups(
656 VkInstance _instance,
657 uint32_t* pPhysicalDeviceGroupCount,
658 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
659 {
660 RADV_FROM_HANDLE(radv_instance, instance, _instance);
661 VkResult result;
662
663 if (instance->physicalDeviceCount < 0) {
664 result = radv_enumerate_devices(instance);
665 if (result != VK_SUCCESS &&
666 result != VK_ERROR_INCOMPATIBLE_DRIVER)
667 return result;
668 }
669
670 if (!pPhysicalDeviceGroupProperties) {
671 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
672 } else {
673 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
674 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
675 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
676 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
677 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
678 }
679 }
680 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
681 : VK_SUCCESS;
682 }
683
684 void radv_GetPhysicalDeviceFeatures(
685 VkPhysicalDevice physicalDevice,
686 VkPhysicalDeviceFeatures* pFeatures)
687 {
688 memset(pFeatures, 0, sizeof(*pFeatures));
689
690 *pFeatures = (VkPhysicalDeviceFeatures) {
691 .robustBufferAccess = true,
692 .fullDrawIndexUint32 = true,
693 .imageCubeArray = true,
694 .independentBlend = true,
695 .geometryShader = true,
696 .tessellationShader = true,
697 .sampleRateShading = true,
698 .dualSrcBlend = true,
699 .logicOp = true,
700 .multiDrawIndirect = true,
701 .drawIndirectFirstInstance = true,
702 .depthClamp = true,
703 .depthBiasClamp = true,
704 .fillModeNonSolid = true,
705 .depthBounds = true,
706 .wideLines = true,
707 .largePoints = true,
708 .alphaToOne = true,
709 .multiViewport = true,
710 .samplerAnisotropy = true,
711 .textureCompressionETC2 = false,
712 .textureCompressionASTC_LDR = false,
713 .textureCompressionBC = true,
714 .occlusionQueryPrecise = true,
715 .pipelineStatisticsQuery = true,
716 .vertexPipelineStoresAndAtomics = true,
717 .fragmentStoresAndAtomics = true,
718 .shaderTessellationAndGeometryPointSize = true,
719 .shaderImageGatherExtended = true,
720 .shaderStorageImageExtendedFormats = true,
721 .shaderStorageImageMultisample = false,
722 .shaderUniformBufferArrayDynamicIndexing = true,
723 .shaderSampledImageArrayDynamicIndexing = true,
724 .shaderStorageBufferArrayDynamicIndexing = true,
725 .shaderStorageImageArrayDynamicIndexing = true,
726 .shaderStorageImageReadWithoutFormat = true,
727 .shaderStorageImageWriteWithoutFormat = true,
728 .shaderClipDistance = true,
729 .shaderCullDistance = true,
730 .shaderFloat64 = true,
731 .shaderInt64 = true,
732 .shaderInt16 = false,
733 .sparseBinding = true,
734 .variableMultisampleRate = true,
735 .inheritedQueries = true,
736 };
737 }
738
739 void radv_GetPhysicalDeviceFeatures2(
740 VkPhysicalDevice physicalDevice,
741 VkPhysicalDeviceFeatures2KHR *pFeatures)
742 {
743 vk_foreach_struct(ext, pFeatures->pNext) {
744 switch (ext->sType) {
745 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
746 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
747 features->variablePointersStorageBuffer = true;
748 features->variablePointers = false;
749 break;
750 }
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
752 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
753 features->multiview = true;
754 features->multiviewGeometryShader = true;
755 features->multiviewTessellationShader = true;
756 break;
757 }
758 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
759 VkPhysicalDeviceShaderDrawParameterFeatures *features =
760 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
761 features->shaderDrawParameters = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
765 VkPhysicalDeviceProtectedMemoryFeatures *features =
766 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
767 features->protectedMemory = false;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
771 VkPhysicalDevice16BitStorageFeatures *features =
772 (VkPhysicalDevice16BitStorageFeatures*)ext;
773 features->storageBuffer16BitAccess = false;
774 features->uniformAndStorageBuffer16BitAccess = false;
775 features->storagePushConstant16 = false;
776 features->storageInputOutput16 = false;
777 break;
778 }
779 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
780 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
781 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
782 features->samplerYcbcrConversion = false;
783 break;
784 }
785 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
786 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
787 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
788 features->shaderInputAttachmentArrayDynamicIndexing = true;
789 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
790 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
791 features->shaderUniformBufferArrayNonUniformIndexing = false;
792 features->shaderSampledImageArrayNonUniformIndexing = false;
793 features->shaderStorageBufferArrayNonUniformIndexing = false;
794 features->shaderStorageImageArrayNonUniformIndexing = false;
795 features->shaderInputAttachmentArrayNonUniformIndexing = false;
796 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
797 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
798 features->descriptorBindingUniformBufferUpdateAfterBind = true;
799 features->descriptorBindingSampledImageUpdateAfterBind = true;
800 features->descriptorBindingStorageImageUpdateAfterBind = true;
801 features->descriptorBindingStorageBufferUpdateAfterBind = true;
802 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
803 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
804 features->descriptorBindingUpdateUnusedWhilePending = true;
805 features->descriptorBindingPartiallyBound = true;
806 features->descriptorBindingVariableDescriptorCount = true;
807 features->runtimeDescriptorArray = true;
808 break;
809 }
810 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
811 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
812 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
813 features->conditionalRendering = true;
814 features->inheritedConditionalRendering = false;
815 break;
816 }
817 default:
818 break;
819 }
820 }
821 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
822 }
823
824 void radv_GetPhysicalDeviceProperties(
825 VkPhysicalDevice physicalDevice,
826 VkPhysicalDeviceProperties* pProperties)
827 {
828 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
829 VkSampleCountFlags sample_counts = 0xf;
830
831 /* make sure that the entire descriptor set is addressable with a signed
832 * 32-bit int. So the sum of all limits scaled by descriptor size has to
833 * be at most 2 GiB. the combined image & samples object count as one of
834 * both. This limit is for the pipeline layout, not for the set layout, but
835 * there is no set limit, so we just set a pipeline limit. I don't think
836 * any app is going to hit this soon. */
837 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
838 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
839 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
840 32 /* sampler, largest when combined with image */ +
841 64 /* sampled image */ +
842 64 /* storage image */);
843
844 VkPhysicalDeviceLimits limits = {
845 .maxImageDimension1D = (1 << 14),
846 .maxImageDimension2D = (1 << 14),
847 .maxImageDimension3D = (1 << 11),
848 .maxImageDimensionCube = (1 << 14),
849 .maxImageArrayLayers = (1 << 11),
850 .maxTexelBufferElements = 128 * 1024 * 1024,
851 .maxUniformBufferRange = UINT32_MAX,
852 .maxStorageBufferRange = UINT32_MAX,
853 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
854 .maxMemoryAllocationCount = UINT32_MAX,
855 .maxSamplerAllocationCount = 64 * 1024,
856 .bufferImageGranularity = 64, /* A cache line */
857 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
858 .maxBoundDescriptorSets = MAX_SETS,
859 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
860 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
861 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
862 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
863 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
864 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
865 .maxPerStageResources = max_descriptor_set_size,
866 .maxDescriptorSetSamplers = max_descriptor_set_size,
867 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
868 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
869 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
870 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
871 .maxDescriptorSetSampledImages = max_descriptor_set_size,
872 .maxDescriptorSetStorageImages = max_descriptor_set_size,
873 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
874 .maxVertexInputAttributes = 32,
875 .maxVertexInputBindings = 32,
876 .maxVertexInputAttributeOffset = 2047,
877 .maxVertexInputBindingStride = 2048,
878 .maxVertexOutputComponents = 128,
879 .maxTessellationGenerationLevel = 64,
880 .maxTessellationPatchSize = 32,
881 .maxTessellationControlPerVertexInputComponents = 128,
882 .maxTessellationControlPerVertexOutputComponents = 128,
883 .maxTessellationControlPerPatchOutputComponents = 120,
884 .maxTessellationControlTotalOutputComponents = 4096,
885 .maxTessellationEvaluationInputComponents = 128,
886 .maxTessellationEvaluationOutputComponents = 128,
887 .maxGeometryShaderInvocations = 127,
888 .maxGeometryInputComponents = 64,
889 .maxGeometryOutputComponents = 128,
890 .maxGeometryOutputVertices = 256,
891 .maxGeometryTotalOutputComponents = 1024,
892 .maxFragmentInputComponents = 128,
893 .maxFragmentOutputAttachments = 8,
894 .maxFragmentDualSrcAttachments = 1,
895 .maxFragmentCombinedOutputResources = 8,
896 .maxComputeSharedMemorySize = 32768,
897 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
898 .maxComputeWorkGroupInvocations = 2048,
899 .maxComputeWorkGroupSize = {
900 2048,
901 2048,
902 2048
903 },
904 .subPixelPrecisionBits = 4 /* FIXME */,
905 .subTexelPrecisionBits = 4 /* FIXME */,
906 .mipmapPrecisionBits = 4 /* FIXME */,
907 .maxDrawIndexedIndexValue = UINT32_MAX,
908 .maxDrawIndirectCount = UINT32_MAX,
909 .maxSamplerLodBias = 16,
910 .maxSamplerAnisotropy = 16,
911 .maxViewports = MAX_VIEWPORTS,
912 .maxViewportDimensions = { (1 << 14), (1 << 14) },
913 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
914 .viewportSubPixelBits = 8,
915 .minMemoryMapAlignment = 4096, /* A page */
916 .minTexelBufferOffsetAlignment = 1,
917 .minUniformBufferOffsetAlignment = 4,
918 .minStorageBufferOffsetAlignment = 4,
919 .minTexelOffset = -32,
920 .maxTexelOffset = 31,
921 .minTexelGatherOffset = -32,
922 .maxTexelGatherOffset = 31,
923 .minInterpolationOffset = -2,
924 .maxInterpolationOffset = 2,
925 .subPixelInterpolationOffsetBits = 8,
926 .maxFramebufferWidth = (1 << 14),
927 .maxFramebufferHeight = (1 << 14),
928 .maxFramebufferLayers = (1 << 10),
929 .framebufferColorSampleCounts = sample_counts,
930 .framebufferDepthSampleCounts = sample_counts,
931 .framebufferStencilSampleCounts = sample_counts,
932 .framebufferNoAttachmentsSampleCounts = sample_counts,
933 .maxColorAttachments = MAX_RTS,
934 .sampledImageColorSampleCounts = sample_counts,
935 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
936 .sampledImageDepthSampleCounts = sample_counts,
937 .sampledImageStencilSampleCounts = sample_counts,
938 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
939 .maxSampleMaskWords = 1,
940 .timestampComputeAndGraphics = true,
941 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
942 .maxClipDistances = 8,
943 .maxCullDistances = 8,
944 .maxCombinedClipAndCullDistances = 8,
945 .discreteQueuePriorities = 1,
946 .pointSizeRange = { 0.125, 255.875 },
947 .lineWidthRange = { 0.0, 7.9921875 },
948 .pointSizeGranularity = (1.0 / 8.0),
949 .lineWidthGranularity = (1.0 / 128.0),
950 .strictLines = false, /* FINISHME */
951 .standardSampleLocations = true,
952 .optimalBufferCopyOffsetAlignment = 128,
953 .optimalBufferCopyRowPitchAlignment = 128,
954 .nonCoherentAtomSize = 64,
955 };
956
957 *pProperties = (VkPhysicalDeviceProperties) {
958 .apiVersion = radv_physical_device_api_version(pdevice),
959 .driverVersion = vk_get_driver_version(),
960 .vendorID = ATI_VENDOR_ID,
961 .deviceID = pdevice->rad_info.pci_id,
962 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
963 .limits = limits,
964 .sparseProperties = {0},
965 };
966
967 strcpy(pProperties->deviceName, pdevice->name);
968 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
969 }
970
971 void radv_GetPhysicalDeviceProperties2(
972 VkPhysicalDevice physicalDevice,
973 VkPhysicalDeviceProperties2KHR *pProperties)
974 {
975 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
976 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
977
978 vk_foreach_struct(ext, pProperties->pNext) {
979 switch (ext->sType) {
980 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
981 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
982 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
983 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
984 break;
985 }
986 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
987 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
988 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
989 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
990 properties->deviceLUIDValid = false;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
994 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
995 properties->maxMultiviewViewCount = MAX_VIEWS;
996 properties->maxMultiviewInstanceIndex = INT_MAX;
997 break;
998 }
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1000 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1001 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1002 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1003 break;
1004 }
1005 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1006 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1007 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1008 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1009 break;
1010 }
1011 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1012 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1013 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1014 properties->minImportedHostPointerAlignment = 4096;
1015 break;
1016 }
1017 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1018 VkPhysicalDeviceSubgroupProperties *properties =
1019 (VkPhysicalDeviceSubgroupProperties*)ext;
1020 properties->subgroupSize = 64;
1021 properties->supportedStages = VK_SHADER_STAGE_ALL;
1022 properties->supportedOperations =
1023 VK_SUBGROUP_FEATURE_BASIC_BIT |
1024 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1025 VK_SUBGROUP_FEATURE_QUAD_BIT |
1026 VK_SUBGROUP_FEATURE_VOTE_BIT;
1027 if (pdevice->rad_info.chip_class >= VI) {
1028 properties->supportedOperations |=
1029 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1030 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1031 }
1032 properties->quadOperationsInAllStages = true;
1033 break;
1034 }
1035 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1036 VkPhysicalDeviceMaintenance3Properties *properties =
1037 (VkPhysicalDeviceMaintenance3Properties*)ext;
1038 /* Make sure everything is addressable by a signed 32-bit int, and
1039 * our largest descriptors are 96 bytes. */
1040 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1041 /* Our buffer size fields allow only this much */
1042 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1043 break;
1044 }
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1046 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1047 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1048 /* GFX6-8 only support single channel min/max filter. */
1049 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1050 properties->filterMinmaxSingleComponentFormats = true;
1051 break;
1052 }
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1054 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1055 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1056
1057 /* Shader engines. */
1058 properties->shaderEngineCount =
1059 pdevice->rad_info.max_se;
1060 properties->shaderArraysPerEngineCount =
1061 pdevice->rad_info.max_sh_per_se;
1062 properties->computeUnitsPerShaderArray =
1063 pdevice->rad_info.num_good_compute_units /
1064 (pdevice->rad_info.max_se *
1065 pdevice->rad_info.max_sh_per_se);
1066 properties->simdPerComputeUnit = 4;
1067 properties->wavefrontsPerSimd =
1068 pdevice->rad_info.family == CHIP_TONGA ||
1069 pdevice->rad_info.family == CHIP_ICELAND ||
1070 pdevice->rad_info.family == CHIP_POLARIS10 ||
1071 pdevice->rad_info.family == CHIP_POLARIS11 ||
1072 pdevice->rad_info.family == CHIP_POLARIS12 ||
1073 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1074 properties->wavefrontSize = 64;
1075
1076 /* SGPR. */
1077 properties->sgprsPerSimd =
1078 radv_get_num_physical_sgprs(pdevice);
1079 properties->minSgprAllocation =
1080 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1081 properties->maxSgprAllocation =
1082 pdevice->rad_info.family == CHIP_TONGA ||
1083 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1084 properties->sgprAllocationGranularity =
1085 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1086
1087 /* VGPR. */
1088 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1089 properties->minVgprAllocation = 4;
1090 properties->maxVgprAllocation = 256;
1091 properties->vgprAllocationGranularity = 4;
1092 break;
1093 }
1094 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1095 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1096 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1097 properties->maxVertexAttribDivisor = UINT32_MAX;
1098 break;
1099 }
1100 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1101 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1102 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1103 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1104 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1105 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1106 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1107 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1108 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1109 properties->robustBufferAccessUpdateAfterBind = false;
1110 properties->quadDivergentImplicitLod = false;
1111
1112 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1113 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1114 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1115 32 /* sampler, largest when combined with image */ +
1116 64 /* sampled image */ +
1117 64 /* storage image */);
1118 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1119 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1120 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1121 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1122 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1123 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1124 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1125 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1126 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1127 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1128 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1129 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1130 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1131 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1132 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1133 break;
1134 }
1135 default:
1136 break;
1137 }
1138 }
1139 }
1140
1141 static void radv_get_physical_device_queue_family_properties(
1142 struct radv_physical_device* pdevice,
1143 uint32_t* pCount,
1144 VkQueueFamilyProperties** pQueueFamilyProperties)
1145 {
1146 int num_queue_families = 1;
1147 int idx;
1148 if (pdevice->rad_info.num_compute_rings > 0 &&
1149 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1150 num_queue_families++;
1151
1152 if (pQueueFamilyProperties == NULL) {
1153 *pCount = num_queue_families;
1154 return;
1155 }
1156
1157 if (!*pCount)
1158 return;
1159
1160 idx = 0;
1161 if (*pCount >= 1) {
1162 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1163 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1164 VK_QUEUE_COMPUTE_BIT |
1165 VK_QUEUE_TRANSFER_BIT |
1166 VK_QUEUE_SPARSE_BINDING_BIT,
1167 .queueCount = 1,
1168 .timestampValidBits = 64,
1169 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1170 };
1171 idx++;
1172 }
1173
1174 if (pdevice->rad_info.num_compute_rings > 0 &&
1175 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1176 if (*pCount > idx) {
1177 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1178 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1179 VK_QUEUE_TRANSFER_BIT |
1180 VK_QUEUE_SPARSE_BINDING_BIT,
1181 .queueCount = pdevice->rad_info.num_compute_rings,
1182 .timestampValidBits = 64,
1183 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1184 };
1185 idx++;
1186 }
1187 }
1188 *pCount = idx;
1189 }
1190
1191 void radv_GetPhysicalDeviceQueueFamilyProperties(
1192 VkPhysicalDevice physicalDevice,
1193 uint32_t* pCount,
1194 VkQueueFamilyProperties* pQueueFamilyProperties)
1195 {
1196 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1197 if (!pQueueFamilyProperties) {
1198 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1199 return;
1200 }
1201 VkQueueFamilyProperties *properties[] = {
1202 pQueueFamilyProperties + 0,
1203 pQueueFamilyProperties + 1,
1204 pQueueFamilyProperties + 2,
1205 };
1206 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1207 assert(*pCount <= 3);
1208 }
1209
1210 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1211 VkPhysicalDevice physicalDevice,
1212 uint32_t* pCount,
1213 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1214 {
1215 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1216 if (!pQueueFamilyProperties) {
1217 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1218 return;
1219 }
1220 VkQueueFamilyProperties *properties[] = {
1221 &pQueueFamilyProperties[0].queueFamilyProperties,
1222 &pQueueFamilyProperties[1].queueFamilyProperties,
1223 &pQueueFamilyProperties[2].queueFamilyProperties,
1224 };
1225 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1226 assert(*pCount <= 3);
1227 }
1228
1229 void radv_GetPhysicalDeviceMemoryProperties(
1230 VkPhysicalDevice physicalDevice,
1231 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1232 {
1233 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1234
1235 *pMemoryProperties = physical_device->memory_properties;
1236 }
1237
1238 void radv_GetPhysicalDeviceMemoryProperties2(
1239 VkPhysicalDevice physicalDevice,
1240 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1241 {
1242 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1243 &pMemoryProperties->memoryProperties);
1244 }
1245
1246 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1247 VkDevice _device,
1248 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1249 const void *pHostPointer,
1250 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1251 {
1252 RADV_FROM_HANDLE(radv_device, device, _device);
1253
1254 switch (handleType)
1255 {
1256 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1257 const struct radv_physical_device *physical_device = device->physical_device;
1258 uint32_t memoryTypeBits = 0;
1259 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1260 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1261 memoryTypeBits = (1 << i);
1262 break;
1263 }
1264 }
1265 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1266 return VK_SUCCESS;
1267 }
1268 default:
1269 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1270 }
1271 }
1272
1273 static enum radeon_ctx_priority
1274 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1275 {
1276 /* Default to MEDIUM when a specific global priority isn't requested */
1277 if (!pObj)
1278 return RADEON_CTX_PRIORITY_MEDIUM;
1279
1280 switch(pObj->globalPriority) {
1281 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1282 return RADEON_CTX_PRIORITY_REALTIME;
1283 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1284 return RADEON_CTX_PRIORITY_HIGH;
1285 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1286 return RADEON_CTX_PRIORITY_MEDIUM;
1287 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1288 return RADEON_CTX_PRIORITY_LOW;
1289 default:
1290 unreachable("Illegal global priority value");
1291 return RADEON_CTX_PRIORITY_INVALID;
1292 }
1293 }
1294
1295 static int
1296 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1297 uint32_t queue_family_index, int idx,
1298 VkDeviceQueueCreateFlags flags,
1299 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1300 {
1301 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1302 queue->device = device;
1303 queue->queue_family_index = queue_family_index;
1304 queue->queue_idx = idx;
1305 queue->priority = radv_get_queue_global_priority(global_priority);
1306 queue->flags = flags;
1307
1308 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1309 if (!queue->hw_ctx)
1310 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1311
1312 return VK_SUCCESS;
1313 }
1314
1315 static void
1316 radv_queue_finish(struct radv_queue *queue)
1317 {
1318 if (queue->hw_ctx)
1319 queue->device->ws->ctx_destroy(queue->hw_ctx);
1320
1321 if (queue->initial_full_flush_preamble_cs)
1322 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1323 if (queue->initial_preamble_cs)
1324 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1325 if (queue->continue_preamble_cs)
1326 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1327 if (queue->descriptor_bo)
1328 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1329 if (queue->scratch_bo)
1330 queue->device->ws->buffer_destroy(queue->scratch_bo);
1331 if (queue->esgs_ring_bo)
1332 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1333 if (queue->gsvs_ring_bo)
1334 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1335 if (queue->tess_rings_bo)
1336 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1337 if (queue->compute_scratch_bo)
1338 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1339 }
1340
1341 static void
1342 radv_bo_list_init(struct radv_bo_list *bo_list)
1343 {
1344 pthread_mutex_init(&bo_list->mutex, NULL);
1345 bo_list->list.count = bo_list->capacity = 0;
1346 bo_list->list.bos = NULL;
1347 }
1348
1349 static void
1350 radv_bo_list_finish(struct radv_bo_list *bo_list)
1351 {
1352 free(bo_list->list.bos);
1353 pthread_mutex_destroy(&bo_list->mutex);
1354 }
1355
1356 static VkResult radv_bo_list_add(struct radv_device *device,
1357 struct radeon_winsys_bo *bo)
1358 {
1359 struct radv_bo_list *bo_list = &device->bo_list;
1360
1361 if (unlikely(!device->use_global_bo_list))
1362 return VK_SUCCESS;
1363
1364 pthread_mutex_lock(&bo_list->mutex);
1365 if (bo_list->list.count == bo_list->capacity) {
1366 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1367 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1368
1369 if (!data) {
1370 pthread_mutex_unlock(&bo_list->mutex);
1371 return VK_ERROR_OUT_OF_HOST_MEMORY;
1372 }
1373
1374 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1375 bo_list->capacity = capacity;
1376 }
1377
1378 bo_list->list.bos[bo_list->list.count++] = bo;
1379 pthread_mutex_unlock(&bo_list->mutex);
1380 return VK_SUCCESS;
1381 }
1382
1383 static void radv_bo_list_remove(struct radv_device *device,
1384 struct radeon_winsys_bo *bo)
1385 {
1386 struct radv_bo_list *bo_list = &device->bo_list;
1387
1388 if (unlikely(!device->use_global_bo_list))
1389 return;
1390
1391 pthread_mutex_lock(&bo_list->mutex);
1392 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1393 if (bo_list->list.bos[i] == bo) {
1394 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1395 --bo_list->list.count;
1396 break;
1397 }
1398 }
1399 pthread_mutex_unlock(&bo_list->mutex);
1400 }
1401
1402 static void
1403 radv_device_init_gs_info(struct radv_device *device)
1404 {
1405 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1406 device->physical_device->rad_info.family);
1407 }
1408
1409 static int radv_get_device_extension_index(const char *name)
1410 {
1411 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1412 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1413 return i;
1414 }
1415 return -1;
1416 }
1417
1418 VkResult radv_CreateDevice(
1419 VkPhysicalDevice physicalDevice,
1420 const VkDeviceCreateInfo* pCreateInfo,
1421 const VkAllocationCallbacks* pAllocator,
1422 VkDevice* pDevice)
1423 {
1424 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1425 VkResult result;
1426 struct radv_device *device;
1427
1428 bool keep_shader_info = false;
1429
1430 /* Check enabled features */
1431 if (pCreateInfo->pEnabledFeatures) {
1432 VkPhysicalDeviceFeatures supported_features;
1433 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1434 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1435 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1436 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1437 for (uint32_t i = 0; i < num_features; i++) {
1438 if (enabled_feature[i] && !supported_feature[i])
1439 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1440 }
1441 }
1442
1443 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1444 sizeof(*device), 8,
1445 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1446 if (!device)
1447 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1448
1449 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1450 device->instance = physical_device->instance;
1451 device->physical_device = physical_device;
1452
1453 device->ws = physical_device->ws;
1454 if (pAllocator)
1455 device->alloc = *pAllocator;
1456 else
1457 device->alloc = physical_device->instance->alloc;
1458
1459 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1460 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1461 int index = radv_get_device_extension_index(ext_name);
1462 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1463 vk_free(&device->alloc, device);
1464 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1465 }
1466
1467 device->enabled_extensions.extensions[index] = true;
1468 }
1469
1470 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1471
1472 /* With update after bind we can't attach bo's to the command buffer
1473 * from the descriptor set anymore, so we have to use a global BO list.
1474 */
1475 device->use_global_bo_list =
1476 device->enabled_extensions.EXT_descriptor_indexing;
1477
1478 mtx_init(&device->shader_slab_mutex, mtx_plain);
1479 list_inithead(&device->shader_slabs);
1480
1481 radv_bo_list_init(&device->bo_list);
1482
1483 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1484 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1485 uint32_t qfi = queue_create->queueFamilyIndex;
1486 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1487 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1488
1489 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1490
1491 device->queues[qfi] = vk_alloc(&device->alloc,
1492 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1493 if (!device->queues[qfi]) {
1494 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1495 goto fail;
1496 }
1497
1498 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1499
1500 device->queue_count[qfi] = queue_create->queueCount;
1501
1502 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1503 result = radv_queue_init(device, &device->queues[qfi][q],
1504 qfi, q, queue_create->flags,
1505 global_priority);
1506 if (result != VK_SUCCESS)
1507 goto fail;
1508 }
1509 }
1510
1511 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1512 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1513 device->physical_device->rad_info.family == CHIP_RAVEN);
1514
1515 /* Disabled and not implemented for now. */
1516 device->dfsm_allowed = device->pbb_allowed &&
1517 device->physical_device->rad_info.family == CHIP_RAVEN;
1518
1519 #ifdef ANDROID
1520 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1521 #endif
1522
1523 /* The maximum number of scratch waves. Scratch space isn't divided
1524 * evenly between CUs. The number is only a function of the number of CUs.
1525 * We can decrease the constant to decrease the scratch buffer size.
1526 *
1527 * sctx->scratch_waves must be >= the maximum possible size of
1528 * 1 threadgroup, so that the hw doesn't hang from being unable
1529 * to start any.
1530 *
1531 * The recommended value is 4 per CU at most. Higher numbers don't
1532 * bring much benefit, but they still occupy chip resources (think
1533 * async compute). I've seen ~2% performance difference between 4 and 32.
1534 */
1535 uint32_t max_threads_per_block = 2048;
1536 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1537 max_threads_per_block / 64);
1538
1539 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1540
1541 if (device->physical_device->rad_info.chip_class >= CIK) {
1542 /* If the KMD allows it (there is a KMD hw register for it),
1543 * allow launching waves out-of-order.
1544 */
1545 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1546 }
1547
1548 radv_device_init_gs_info(device);
1549
1550 device->tess_offchip_block_dw_size =
1551 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1552 device->has_distributed_tess =
1553 device->physical_device->rad_info.chip_class >= VI &&
1554 device->physical_device->rad_info.max_se >= 2;
1555
1556 if (getenv("RADV_TRACE_FILE")) {
1557 const char *filename = getenv("RADV_TRACE_FILE");
1558
1559 keep_shader_info = true;
1560
1561 if (!radv_init_trace(device))
1562 goto fail;
1563
1564 fprintf(stderr, "*****************************************************************************\n");
1565 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1566 fprintf(stderr, "*****************************************************************************\n");
1567
1568 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1569 radv_dump_enabled_options(device, stderr);
1570 }
1571
1572 device->keep_shader_info = keep_shader_info;
1573
1574 result = radv_device_init_meta(device);
1575 if (result != VK_SUCCESS)
1576 goto fail;
1577
1578 radv_device_init_msaa(device);
1579
1580 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1581 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1582 switch (family) {
1583 case RADV_QUEUE_GENERAL:
1584 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1585 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1586 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1587 break;
1588 case RADV_QUEUE_COMPUTE:
1589 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1590 radeon_emit(device->empty_cs[family], 0);
1591 break;
1592 }
1593 device->ws->cs_finalize(device->empty_cs[family]);
1594 }
1595
1596 if (device->physical_device->rad_info.chip_class >= CIK)
1597 cik_create_gfx_config(device);
1598
1599 VkPipelineCacheCreateInfo ci;
1600 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1601 ci.pNext = NULL;
1602 ci.flags = 0;
1603 ci.pInitialData = NULL;
1604 ci.initialDataSize = 0;
1605 VkPipelineCache pc;
1606 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1607 &ci, NULL, &pc);
1608 if (result != VK_SUCCESS)
1609 goto fail_meta;
1610
1611 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1612
1613 *pDevice = radv_device_to_handle(device);
1614 return VK_SUCCESS;
1615
1616 fail_meta:
1617 radv_device_finish_meta(device);
1618 fail:
1619 radv_bo_list_finish(&device->bo_list);
1620
1621 if (device->trace_bo)
1622 device->ws->buffer_destroy(device->trace_bo);
1623
1624 if (device->gfx_init)
1625 device->ws->buffer_destroy(device->gfx_init);
1626
1627 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1628 for (unsigned q = 0; q < device->queue_count[i]; q++)
1629 radv_queue_finish(&device->queues[i][q]);
1630 if (device->queue_count[i])
1631 vk_free(&device->alloc, device->queues[i]);
1632 }
1633
1634 vk_free(&device->alloc, device);
1635 return result;
1636 }
1637
1638 void radv_DestroyDevice(
1639 VkDevice _device,
1640 const VkAllocationCallbacks* pAllocator)
1641 {
1642 RADV_FROM_HANDLE(radv_device, device, _device);
1643
1644 if (!device)
1645 return;
1646
1647 if (device->trace_bo)
1648 device->ws->buffer_destroy(device->trace_bo);
1649
1650 if (device->gfx_init)
1651 device->ws->buffer_destroy(device->gfx_init);
1652
1653 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1654 for (unsigned q = 0; q < device->queue_count[i]; q++)
1655 radv_queue_finish(&device->queues[i][q]);
1656 if (device->queue_count[i])
1657 vk_free(&device->alloc, device->queues[i]);
1658 if (device->empty_cs[i])
1659 device->ws->cs_destroy(device->empty_cs[i]);
1660 }
1661 radv_device_finish_meta(device);
1662
1663 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1664 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1665
1666 radv_destroy_shader_slabs(device);
1667
1668 radv_bo_list_finish(&device->bo_list);
1669 vk_free(&device->alloc, device);
1670 }
1671
1672 VkResult radv_EnumerateInstanceLayerProperties(
1673 uint32_t* pPropertyCount,
1674 VkLayerProperties* pProperties)
1675 {
1676 if (pProperties == NULL) {
1677 *pPropertyCount = 0;
1678 return VK_SUCCESS;
1679 }
1680
1681 /* None supported at this time */
1682 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1683 }
1684
1685 VkResult radv_EnumerateDeviceLayerProperties(
1686 VkPhysicalDevice physicalDevice,
1687 uint32_t* pPropertyCount,
1688 VkLayerProperties* pProperties)
1689 {
1690 if (pProperties == NULL) {
1691 *pPropertyCount = 0;
1692 return VK_SUCCESS;
1693 }
1694
1695 /* None supported at this time */
1696 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1697 }
1698
1699 void radv_GetDeviceQueue2(
1700 VkDevice _device,
1701 const VkDeviceQueueInfo2* pQueueInfo,
1702 VkQueue* pQueue)
1703 {
1704 RADV_FROM_HANDLE(radv_device, device, _device);
1705 struct radv_queue *queue;
1706
1707 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1708 if (pQueueInfo->flags != queue->flags) {
1709 /* From the Vulkan 1.1.70 spec:
1710 *
1711 * "The queue returned by vkGetDeviceQueue2 must have the same
1712 * flags value from this structure as that used at device
1713 * creation time in a VkDeviceQueueCreateInfo instance. If no
1714 * matching flags were specified at device creation time then
1715 * pQueue will return VK_NULL_HANDLE."
1716 */
1717 *pQueue = VK_NULL_HANDLE;
1718 return;
1719 }
1720
1721 *pQueue = radv_queue_to_handle(queue);
1722 }
1723
1724 void radv_GetDeviceQueue(
1725 VkDevice _device,
1726 uint32_t queueFamilyIndex,
1727 uint32_t queueIndex,
1728 VkQueue* pQueue)
1729 {
1730 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1731 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1732 .queueFamilyIndex = queueFamilyIndex,
1733 .queueIndex = queueIndex
1734 };
1735
1736 radv_GetDeviceQueue2(_device, &info, pQueue);
1737 }
1738
1739 static void
1740 fill_geom_tess_rings(struct radv_queue *queue,
1741 uint32_t *map,
1742 bool add_sample_positions,
1743 uint32_t esgs_ring_size,
1744 struct radeon_winsys_bo *esgs_ring_bo,
1745 uint32_t gsvs_ring_size,
1746 struct radeon_winsys_bo *gsvs_ring_bo,
1747 uint32_t tess_factor_ring_size,
1748 uint32_t tess_offchip_ring_offset,
1749 uint32_t tess_offchip_ring_size,
1750 struct radeon_winsys_bo *tess_rings_bo)
1751 {
1752 uint64_t esgs_va = 0, gsvs_va = 0;
1753 uint64_t tess_va = 0, tess_offchip_va = 0;
1754 uint32_t *desc = &map[4];
1755
1756 if (esgs_ring_bo)
1757 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1758 if (gsvs_ring_bo)
1759 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1760 if (tess_rings_bo) {
1761 tess_va = radv_buffer_get_va(tess_rings_bo);
1762 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1763 }
1764
1765 /* stride 0, num records - size, add tid, swizzle, elsize4,
1766 index stride 64 */
1767 desc[0] = esgs_va;
1768 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1769 S_008F04_STRIDE(0) |
1770 S_008F04_SWIZZLE_ENABLE(true);
1771 desc[2] = esgs_ring_size;
1772 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1773 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1774 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1775 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1776 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1777 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1778 S_008F0C_ELEMENT_SIZE(1) |
1779 S_008F0C_INDEX_STRIDE(3) |
1780 S_008F0C_ADD_TID_ENABLE(true);
1781
1782 desc += 4;
1783 /* GS entry for ES->GS ring */
1784 /* stride 0, num records - size, elsize0,
1785 index stride 0 */
1786 desc[0] = esgs_va;
1787 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1788 S_008F04_STRIDE(0) |
1789 S_008F04_SWIZZLE_ENABLE(false);
1790 desc[2] = esgs_ring_size;
1791 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1792 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1793 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1794 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1795 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1796 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1797 S_008F0C_ELEMENT_SIZE(0) |
1798 S_008F0C_INDEX_STRIDE(0) |
1799 S_008F0C_ADD_TID_ENABLE(false);
1800
1801 desc += 4;
1802 /* VS entry for GS->VS ring */
1803 /* stride 0, num records - size, elsize0,
1804 index stride 0 */
1805 desc[0] = gsvs_va;
1806 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1807 S_008F04_STRIDE(0) |
1808 S_008F04_SWIZZLE_ENABLE(false);
1809 desc[2] = gsvs_ring_size;
1810 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1811 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1812 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1813 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1814 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1815 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1816 S_008F0C_ELEMENT_SIZE(0) |
1817 S_008F0C_INDEX_STRIDE(0) |
1818 S_008F0C_ADD_TID_ENABLE(false);
1819 desc += 4;
1820
1821 /* stride gsvs_itemsize, num records 64
1822 elsize 4, index stride 16 */
1823 /* shader will patch stride and desc[2] */
1824 desc[0] = gsvs_va;
1825 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1826 S_008F04_STRIDE(0) |
1827 S_008F04_SWIZZLE_ENABLE(true);
1828 desc[2] = 0;
1829 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1830 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1831 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1832 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1833 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1834 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1835 S_008F0C_ELEMENT_SIZE(1) |
1836 S_008F0C_INDEX_STRIDE(1) |
1837 S_008F0C_ADD_TID_ENABLE(true);
1838 desc += 4;
1839
1840 desc[0] = tess_va;
1841 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1842 S_008F04_STRIDE(0) |
1843 S_008F04_SWIZZLE_ENABLE(false);
1844 desc[2] = tess_factor_ring_size;
1845 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1846 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1847 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1848 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1849 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1850 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1851 S_008F0C_ELEMENT_SIZE(0) |
1852 S_008F0C_INDEX_STRIDE(0) |
1853 S_008F0C_ADD_TID_ENABLE(false);
1854 desc += 4;
1855
1856 desc[0] = tess_offchip_va;
1857 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1858 S_008F04_STRIDE(0) |
1859 S_008F04_SWIZZLE_ENABLE(false);
1860 desc[2] = tess_offchip_ring_size;
1861 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1862 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1863 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1864 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1865 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1866 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1867 S_008F0C_ELEMENT_SIZE(0) |
1868 S_008F0C_INDEX_STRIDE(0) |
1869 S_008F0C_ADD_TID_ENABLE(false);
1870 desc += 4;
1871
1872 /* add sample positions after all rings */
1873 memcpy(desc, queue->device->sample_locations_1x, 8);
1874 desc += 2;
1875 memcpy(desc, queue->device->sample_locations_2x, 16);
1876 desc += 4;
1877 memcpy(desc, queue->device->sample_locations_4x, 32);
1878 desc += 8;
1879 memcpy(desc, queue->device->sample_locations_8x, 64);
1880 desc += 16;
1881 memcpy(desc, queue->device->sample_locations_16x, 128);
1882 }
1883
1884 static unsigned
1885 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1886 {
1887 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1888 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1889 device->physical_device->rad_info.family != CHIP_STONEY;
1890 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1891 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1892 device->physical_device->rad_info.max_se;
1893 unsigned offchip_granularity;
1894 unsigned hs_offchip_param;
1895 switch (device->tess_offchip_block_dw_size) {
1896 default:
1897 assert(0);
1898 /* fall through */
1899 case 8192:
1900 offchip_granularity = V_03093C_X_8K_DWORDS;
1901 break;
1902 case 4096:
1903 offchip_granularity = V_03093C_X_4K_DWORDS;
1904 break;
1905 }
1906
1907 switch (device->physical_device->rad_info.chip_class) {
1908 case SI:
1909 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1910 break;
1911 case CIK:
1912 case VI:
1913 case GFX9:
1914 default:
1915 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1916 break;
1917 }
1918
1919 *max_offchip_buffers_p = max_offchip_buffers;
1920 if (device->physical_device->rad_info.chip_class >= CIK) {
1921 if (device->physical_device->rad_info.chip_class >= VI)
1922 --max_offchip_buffers;
1923 hs_offchip_param =
1924 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1925 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1926 } else {
1927 hs_offchip_param =
1928 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1929 }
1930 return hs_offchip_param;
1931 }
1932
1933 static void
1934 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1935 struct radeon_winsys_bo *esgs_ring_bo,
1936 uint32_t esgs_ring_size,
1937 struct radeon_winsys_bo *gsvs_ring_bo,
1938 uint32_t gsvs_ring_size)
1939 {
1940 if (!esgs_ring_bo && !gsvs_ring_bo)
1941 return;
1942
1943 if (esgs_ring_bo)
1944 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1945
1946 if (gsvs_ring_bo)
1947 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1948
1949 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1950 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1951 radeon_emit(cs, esgs_ring_size >> 8);
1952 radeon_emit(cs, gsvs_ring_size >> 8);
1953 } else {
1954 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1955 radeon_emit(cs, esgs_ring_size >> 8);
1956 radeon_emit(cs, gsvs_ring_size >> 8);
1957 }
1958 }
1959
1960 static void
1961 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1962 unsigned hs_offchip_param, unsigned tf_ring_size,
1963 struct radeon_winsys_bo *tess_rings_bo)
1964 {
1965 uint64_t tf_va;
1966
1967 if (!tess_rings_bo)
1968 return;
1969
1970 tf_va = radv_buffer_get_va(tess_rings_bo);
1971
1972 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
1973
1974 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1975 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1976 S_030938_SIZE(tf_ring_size / 4));
1977 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1978 tf_va >> 8);
1979 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1980 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1981 S_030944_BASE_HI(tf_va >> 40));
1982 }
1983 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
1984 hs_offchip_param);
1985 } else {
1986 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1987 S_008988_SIZE(tf_ring_size / 4));
1988 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1989 tf_va >> 8);
1990 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1991 hs_offchip_param);
1992 }
1993 }
1994
1995 static void
1996 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1997 struct radeon_winsys_bo *compute_scratch_bo)
1998 {
1999 uint64_t scratch_va;
2000
2001 if (!compute_scratch_bo)
2002 return;
2003
2004 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2005
2006 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2007
2008 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2009 radeon_emit(cs, scratch_va);
2010 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2011 S_008F04_SWIZZLE_ENABLE(1));
2012 }
2013
2014 static void
2015 radv_emit_global_shader_pointers(struct radv_queue *queue,
2016 struct radeon_cmdbuf *cs,
2017 struct radeon_winsys_bo *descriptor_bo)
2018 {
2019 uint64_t va;
2020
2021 if (!descriptor_bo)
2022 return;
2023
2024 va = radv_buffer_get_va(descriptor_bo);
2025
2026 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2027
2028 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2029 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2030 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2031 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2032 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2033
2034 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2035 radv_emit_shader_pointer(queue->device, cs, regs[i],
2036 va, true);
2037 }
2038 } else {
2039 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2040 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2041 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2042 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2043 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2044 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2045
2046 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2047 radv_emit_shader_pointer(queue->device, cs, regs[i],
2048 va, true);
2049 }
2050 }
2051 }
2052
2053 static VkResult
2054 radv_get_preamble_cs(struct radv_queue *queue,
2055 uint32_t scratch_size,
2056 uint32_t compute_scratch_size,
2057 uint32_t esgs_ring_size,
2058 uint32_t gsvs_ring_size,
2059 bool needs_tess_rings,
2060 bool needs_sample_positions,
2061 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2062 struct radeon_cmdbuf **initial_preamble_cs,
2063 struct radeon_cmdbuf **continue_preamble_cs)
2064 {
2065 struct radeon_winsys_bo *scratch_bo = NULL;
2066 struct radeon_winsys_bo *descriptor_bo = NULL;
2067 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2068 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2069 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2070 struct radeon_winsys_bo *tess_rings_bo = NULL;
2071 struct radeon_cmdbuf *dest_cs[3] = {0};
2072 bool add_tess_rings = false, add_sample_positions = false;
2073 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2074 unsigned max_offchip_buffers;
2075 unsigned hs_offchip_param = 0;
2076 unsigned tess_offchip_ring_offset;
2077 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2078 if (!queue->has_tess_rings) {
2079 if (needs_tess_rings)
2080 add_tess_rings = true;
2081 }
2082 if (!queue->has_sample_positions) {
2083 if (needs_sample_positions)
2084 add_sample_positions = true;
2085 }
2086 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2087 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2088 &max_offchip_buffers);
2089 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2090 tess_offchip_ring_size = max_offchip_buffers *
2091 queue->device->tess_offchip_block_dw_size * 4;
2092
2093 if (scratch_size <= queue->scratch_size &&
2094 compute_scratch_size <= queue->compute_scratch_size &&
2095 esgs_ring_size <= queue->esgs_ring_size &&
2096 gsvs_ring_size <= queue->gsvs_ring_size &&
2097 !add_tess_rings && !add_sample_positions &&
2098 queue->initial_preamble_cs) {
2099 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2100 *initial_preamble_cs = queue->initial_preamble_cs;
2101 *continue_preamble_cs = queue->continue_preamble_cs;
2102 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2103 *continue_preamble_cs = NULL;
2104 return VK_SUCCESS;
2105 }
2106
2107 if (scratch_size > queue->scratch_size) {
2108 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2109 scratch_size,
2110 4096,
2111 RADEON_DOMAIN_VRAM,
2112 ring_bo_flags);
2113 if (!scratch_bo)
2114 goto fail;
2115 } else
2116 scratch_bo = queue->scratch_bo;
2117
2118 if (compute_scratch_size > queue->compute_scratch_size) {
2119 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2120 compute_scratch_size,
2121 4096,
2122 RADEON_DOMAIN_VRAM,
2123 ring_bo_flags);
2124 if (!compute_scratch_bo)
2125 goto fail;
2126
2127 } else
2128 compute_scratch_bo = queue->compute_scratch_bo;
2129
2130 if (esgs_ring_size > queue->esgs_ring_size) {
2131 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2132 esgs_ring_size,
2133 4096,
2134 RADEON_DOMAIN_VRAM,
2135 ring_bo_flags);
2136 if (!esgs_ring_bo)
2137 goto fail;
2138 } else {
2139 esgs_ring_bo = queue->esgs_ring_bo;
2140 esgs_ring_size = queue->esgs_ring_size;
2141 }
2142
2143 if (gsvs_ring_size > queue->gsvs_ring_size) {
2144 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2145 gsvs_ring_size,
2146 4096,
2147 RADEON_DOMAIN_VRAM,
2148 ring_bo_flags);
2149 if (!gsvs_ring_bo)
2150 goto fail;
2151 } else {
2152 gsvs_ring_bo = queue->gsvs_ring_bo;
2153 gsvs_ring_size = queue->gsvs_ring_size;
2154 }
2155
2156 if (add_tess_rings) {
2157 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2158 tess_offchip_ring_offset + tess_offchip_ring_size,
2159 256,
2160 RADEON_DOMAIN_VRAM,
2161 ring_bo_flags);
2162 if (!tess_rings_bo)
2163 goto fail;
2164 } else {
2165 tess_rings_bo = queue->tess_rings_bo;
2166 }
2167
2168 if (scratch_bo != queue->scratch_bo ||
2169 esgs_ring_bo != queue->esgs_ring_bo ||
2170 gsvs_ring_bo != queue->gsvs_ring_bo ||
2171 tess_rings_bo != queue->tess_rings_bo ||
2172 add_sample_positions) {
2173 uint32_t size = 0;
2174 if (gsvs_ring_bo || esgs_ring_bo ||
2175 tess_rings_bo || add_sample_positions) {
2176 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2177 if (add_sample_positions)
2178 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2179 }
2180 else if (scratch_bo)
2181 size = 8; /* 2 dword */
2182
2183 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2184 size,
2185 4096,
2186 RADEON_DOMAIN_VRAM,
2187 RADEON_FLAG_CPU_ACCESS |
2188 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2189 RADEON_FLAG_READ_ONLY);
2190 if (!descriptor_bo)
2191 goto fail;
2192 } else
2193 descriptor_bo = queue->descriptor_bo;
2194
2195 for(int i = 0; i < 3; ++i) {
2196 struct radeon_cmdbuf *cs = NULL;
2197 cs = queue->device->ws->cs_create(queue->device->ws,
2198 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2199 if (!cs)
2200 goto fail;
2201
2202 dest_cs[i] = cs;
2203
2204 if (scratch_bo)
2205 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2206
2207 if (descriptor_bo != queue->descriptor_bo) {
2208 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2209
2210 if (scratch_bo) {
2211 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2212 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2213 S_008F04_SWIZZLE_ENABLE(1);
2214 map[0] = scratch_va;
2215 map[1] = rsrc1;
2216 }
2217
2218 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2219 add_sample_positions)
2220 fill_geom_tess_rings(queue, map, add_sample_positions,
2221 esgs_ring_size, esgs_ring_bo,
2222 gsvs_ring_size, gsvs_ring_bo,
2223 tess_factor_ring_size,
2224 tess_offchip_ring_offset,
2225 tess_offchip_ring_size,
2226 tess_rings_bo);
2227
2228 queue->device->ws->buffer_unmap(descriptor_bo);
2229 }
2230
2231 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2232 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2233 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2234 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2235 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2236 }
2237
2238 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2239 gsvs_ring_bo, gsvs_ring_size);
2240 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2241 tess_factor_ring_size, tess_rings_bo);
2242 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2243 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2244
2245 if (i == 0) {
2246 si_cs_emit_cache_flush(cs,
2247 queue->device->physical_device->rad_info.chip_class,
2248 NULL, 0,
2249 queue->queue_family_index == RING_COMPUTE &&
2250 queue->device->physical_device->rad_info.chip_class >= CIK,
2251 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2252 RADV_CMD_FLAG_INV_ICACHE |
2253 RADV_CMD_FLAG_INV_SMEM_L1 |
2254 RADV_CMD_FLAG_INV_VMEM_L1 |
2255 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2256 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2257 } else if (i == 1) {
2258 si_cs_emit_cache_flush(cs,
2259 queue->device->physical_device->rad_info.chip_class,
2260 NULL, 0,
2261 queue->queue_family_index == RING_COMPUTE &&
2262 queue->device->physical_device->rad_info.chip_class >= CIK,
2263 RADV_CMD_FLAG_INV_ICACHE |
2264 RADV_CMD_FLAG_INV_SMEM_L1 |
2265 RADV_CMD_FLAG_INV_VMEM_L1 |
2266 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2267 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2268 }
2269
2270 if (!queue->device->ws->cs_finalize(cs))
2271 goto fail;
2272 }
2273
2274 if (queue->initial_full_flush_preamble_cs)
2275 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2276
2277 if (queue->initial_preamble_cs)
2278 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2279
2280 if (queue->continue_preamble_cs)
2281 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2282
2283 queue->initial_full_flush_preamble_cs = dest_cs[0];
2284 queue->initial_preamble_cs = dest_cs[1];
2285 queue->continue_preamble_cs = dest_cs[2];
2286
2287 if (scratch_bo != queue->scratch_bo) {
2288 if (queue->scratch_bo)
2289 queue->device->ws->buffer_destroy(queue->scratch_bo);
2290 queue->scratch_bo = scratch_bo;
2291 queue->scratch_size = scratch_size;
2292 }
2293
2294 if (compute_scratch_bo != queue->compute_scratch_bo) {
2295 if (queue->compute_scratch_bo)
2296 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2297 queue->compute_scratch_bo = compute_scratch_bo;
2298 queue->compute_scratch_size = compute_scratch_size;
2299 }
2300
2301 if (esgs_ring_bo != queue->esgs_ring_bo) {
2302 if (queue->esgs_ring_bo)
2303 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2304 queue->esgs_ring_bo = esgs_ring_bo;
2305 queue->esgs_ring_size = esgs_ring_size;
2306 }
2307
2308 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2309 if (queue->gsvs_ring_bo)
2310 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2311 queue->gsvs_ring_bo = gsvs_ring_bo;
2312 queue->gsvs_ring_size = gsvs_ring_size;
2313 }
2314
2315 if (tess_rings_bo != queue->tess_rings_bo) {
2316 queue->tess_rings_bo = tess_rings_bo;
2317 queue->has_tess_rings = true;
2318 }
2319
2320 if (descriptor_bo != queue->descriptor_bo) {
2321 if (queue->descriptor_bo)
2322 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2323
2324 queue->descriptor_bo = descriptor_bo;
2325 }
2326
2327 if (add_sample_positions)
2328 queue->has_sample_positions = true;
2329
2330 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2331 *initial_preamble_cs = queue->initial_preamble_cs;
2332 *continue_preamble_cs = queue->continue_preamble_cs;
2333 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2334 *continue_preamble_cs = NULL;
2335 return VK_SUCCESS;
2336 fail:
2337 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2338 if (dest_cs[i])
2339 queue->device->ws->cs_destroy(dest_cs[i]);
2340 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2341 queue->device->ws->buffer_destroy(descriptor_bo);
2342 if (scratch_bo && scratch_bo != queue->scratch_bo)
2343 queue->device->ws->buffer_destroy(scratch_bo);
2344 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2345 queue->device->ws->buffer_destroy(compute_scratch_bo);
2346 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2347 queue->device->ws->buffer_destroy(esgs_ring_bo);
2348 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2349 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2350 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2351 queue->device->ws->buffer_destroy(tess_rings_bo);
2352 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2353 }
2354
2355 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2356 struct radv_winsys_sem_counts *counts,
2357 int num_sems,
2358 const VkSemaphore *sems,
2359 VkFence _fence,
2360 bool reset_temp)
2361 {
2362 int syncobj_idx = 0, sem_idx = 0;
2363
2364 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2365 return VK_SUCCESS;
2366
2367 for (uint32_t i = 0; i < num_sems; i++) {
2368 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2369
2370 if (sem->temp_syncobj || sem->syncobj)
2371 counts->syncobj_count++;
2372 else
2373 counts->sem_count++;
2374 }
2375
2376 if (_fence != VK_NULL_HANDLE) {
2377 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2378 if (fence->temp_syncobj || fence->syncobj)
2379 counts->syncobj_count++;
2380 }
2381
2382 if (counts->syncobj_count) {
2383 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2384 if (!counts->syncobj)
2385 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2386 }
2387
2388 if (counts->sem_count) {
2389 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2390 if (!counts->sem) {
2391 free(counts->syncobj);
2392 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2393 }
2394 }
2395
2396 for (uint32_t i = 0; i < num_sems; i++) {
2397 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2398
2399 if (sem->temp_syncobj) {
2400 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2401 }
2402 else if (sem->syncobj)
2403 counts->syncobj[syncobj_idx++] = sem->syncobj;
2404 else {
2405 assert(sem->sem);
2406 counts->sem[sem_idx++] = sem->sem;
2407 }
2408 }
2409
2410 if (_fence != VK_NULL_HANDLE) {
2411 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2412 if (fence->temp_syncobj)
2413 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2414 else if (fence->syncobj)
2415 counts->syncobj[syncobj_idx++] = fence->syncobj;
2416 }
2417
2418 return VK_SUCCESS;
2419 }
2420
2421 static void
2422 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2423 {
2424 free(sem_info->wait.syncobj);
2425 free(sem_info->wait.sem);
2426 free(sem_info->signal.syncobj);
2427 free(sem_info->signal.sem);
2428 }
2429
2430
2431 static void radv_free_temp_syncobjs(struct radv_device *device,
2432 int num_sems,
2433 const VkSemaphore *sems)
2434 {
2435 for (uint32_t i = 0; i < num_sems; i++) {
2436 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2437
2438 if (sem->temp_syncobj) {
2439 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2440 sem->temp_syncobj = 0;
2441 }
2442 }
2443 }
2444
2445 static VkResult
2446 radv_alloc_sem_info(struct radv_instance *instance,
2447 struct radv_winsys_sem_info *sem_info,
2448 int num_wait_sems,
2449 const VkSemaphore *wait_sems,
2450 int num_signal_sems,
2451 const VkSemaphore *signal_sems,
2452 VkFence fence)
2453 {
2454 VkResult ret;
2455 memset(sem_info, 0, sizeof(*sem_info));
2456
2457 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2458 if (ret)
2459 return ret;
2460 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2461 if (ret)
2462 radv_free_sem_info(sem_info);
2463
2464 /* caller can override these */
2465 sem_info->cs_emit_wait = true;
2466 sem_info->cs_emit_signal = true;
2467 return ret;
2468 }
2469
2470 /* Signals fence as soon as all the work currently put on queue is done. */
2471 static VkResult radv_signal_fence(struct radv_queue *queue,
2472 struct radv_fence *fence)
2473 {
2474 int ret;
2475 VkResult result;
2476 struct radv_winsys_sem_info sem_info;
2477
2478 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2479 radv_fence_to_handle(fence));
2480 if (result != VK_SUCCESS)
2481 return result;
2482
2483 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2484 &queue->device->empty_cs[queue->queue_family_index],
2485 1, NULL, NULL, &sem_info, NULL,
2486 false, fence->fence);
2487 radv_free_sem_info(&sem_info);
2488
2489 if (ret)
2490 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2491
2492 return VK_SUCCESS;
2493 }
2494
2495 VkResult radv_QueueSubmit(
2496 VkQueue _queue,
2497 uint32_t submitCount,
2498 const VkSubmitInfo* pSubmits,
2499 VkFence _fence)
2500 {
2501 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2502 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2503 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2504 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2505 int ret;
2506 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2507 uint32_t scratch_size = 0;
2508 uint32_t compute_scratch_size = 0;
2509 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2510 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2511 VkResult result;
2512 bool fence_emitted = false;
2513 bool tess_rings_needed = false;
2514 bool sample_positions_needed = false;
2515
2516 /* Do this first so failing to allocate scratch buffers can't result in
2517 * partially executed submissions. */
2518 for (uint32_t i = 0; i < submitCount; i++) {
2519 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2520 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2521 pSubmits[i].pCommandBuffers[j]);
2522
2523 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2524 compute_scratch_size = MAX2(compute_scratch_size,
2525 cmd_buffer->compute_scratch_size_needed);
2526 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2527 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2528 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2529 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2530 }
2531 }
2532
2533 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2534 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2535 sample_positions_needed, &initial_flush_preamble_cs,
2536 &initial_preamble_cs, &continue_preamble_cs);
2537 if (result != VK_SUCCESS)
2538 return result;
2539
2540 for (uint32_t i = 0; i < submitCount; i++) {
2541 struct radeon_cmdbuf **cs_array;
2542 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2543 bool can_patch = true;
2544 uint32_t advance;
2545 struct radv_winsys_sem_info sem_info;
2546
2547 result = radv_alloc_sem_info(queue->device->instance,
2548 &sem_info,
2549 pSubmits[i].waitSemaphoreCount,
2550 pSubmits[i].pWaitSemaphores,
2551 pSubmits[i].signalSemaphoreCount,
2552 pSubmits[i].pSignalSemaphores,
2553 _fence);
2554 if (result != VK_SUCCESS)
2555 return result;
2556
2557 if (!pSubmits[i].commandBufferCount) {
2558 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2559 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2560 &queue->device->empty_cs[queue->queue_family_index],
2561 1, NULL, NULL,
2562 &sem_info, NULL,
2563 false, base_fence);
2564 if (ret) {
2565 radv_loge("failed to submit CS %d\n", i);
2566 abort();
2567 }
2568 fence_emitted = true;
2569 }
2570 radv_free_sem_info(&sem_info);
2571 continue;
2572 }
2573
2574 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2575 (pSubmits[i].commandBufferCount));
2576
2577 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2578 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2579 pSubmits[i].pCommandBuffers[j]);
2580 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2581
2582 cs_array[j] = cmd_buffer->cs;
2583 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2584 can_patch = false;
2585
2586 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2587 }
2588
2589 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2590 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2591 const struct radv_winsys_bo_list *bo_list = NULL;
2592
2593 advance = MIN2(max_cs_submission,
2594 pSubmits[i].commandBufferCount - j);
2595
2596 if (queue->device->trace_bo)
2597 *queue->device->trace_id_ptr = 0;
2598
2599 sem_info.cs_emit_wait = j == 0;
2600 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2601
2602 if (unlikely(queue->device->use_global_bo_list)) {
2603 pthread_mutex_lock(&queue->device->bo_list.mutex);
2604 bo_list = &queue->device->bo_list.list;
2605 }
2606
2607 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2608 advance, initial_preamble, continue_preamble_cs,
2609 &sem_info, bo_list,
2610 can_patch, base_fence);
2611
2612 if (unlikely(queue->device->use_global_bo_list))
2613 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2614
2615 if (ret) {
2616 radv_loge("failed to submit CS %d\n", i);
2617 abort();
2618 }
2619 fence_emitted = true;
2620 if (queue->device->trace_bo) {
2621 radv_check_gpu_hangs(queue, cs_array[j]);
2622 }
2623 }
2624
2625 radv_free_temp_syncobjs(queue->device,
2626 pSubmits[i].waitSemaphoreCount,
2627 pSubmits[i].pWaitSemaphores);
2628 radv_free_sem_info(&sem_info);
2629 free(cs_array);
2630 }
2631
2632 if (fence) {
2633 if (!fence_emitted) {
2634 result = radv_signal_fence(queue, fence);
2635 if (result != VK_SUCCESS)
2636 return result;
2637 }
2638 fence->submitted = true;
2639 }
2640
2641 return VK_SUCCESS;
2642 }
2643
2644 VkResult radv_QueueWaitIdle(
2645 VkQueue _queue)
2646 {
2647 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2648
2649 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2650 radv_queue_family_to_ring(queue->queue_family_index),
2651 queue->queue_idx);
2652 return VK_SUCCESS;
2653 }
2654
2655 VkResult radv_DeviceWaitIdle(
2656 VkDevice _device)
2657 {
2658 RADV_FROM_HANDLE(radv_device, device, _device);
2659
2660 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2661 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2662 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2663 }
2664 }
2665 return VK_SUCCESS;
2666 }
2667
2668 VkResult radv_EnumerateInstanceExtensionProperties(
2669 const char* pLayerName,
2670 uint32_t* pPropertyCount,
2671 VkExtensionProperties* pProperties)
2672 {
2673 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2674
2675 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2676 if (radv_supported_instance_extensions.extensions[i]) {
2677 vk_outarray_append(&out, prop) {
2678 *prop = radv_instance_extensions[i];
2679 }
2680 }
2681 }
2682
2683 return vk_outarray_status(&out);
2684 }
2685
2686 VkResult radv_EnumerateDeviceExtensionProperties(
2687 VkPhysicalDevice physicalDevice,
2688 const char* pLayerName,
2689 uint32_t* pPropertyCount,
2690 VkExtensionProperties* pProperties)
2691 {
2692 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2693 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2694
2695 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2696 if (device->supported_extensions.extensions[i]) {
2697 vk_outarray_append(&out, prop) {
2698 *prop = radv_device_extensions[i];
2699 }
2700 }
2701 }
2702
2703 return vk_outarray_status(&out);
2704 }
2705
2706 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2707 VkInstance _instance,
2708 const char* pName)
2709 {
2710 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2711
2712 return radv_lookup_entrypoint_checked(pName,
2713 instance ? instance->apiVersion : 0,
2714 instance ? &instance->enabled_extensions : NULL,
2715 NULL);
2716 }
2717
2718 /* The loader wants us to expose a second GetInstanceProcAddr function
2719 * to work around certain LD_PRELOAD issues seen in apps.
2720 */
2721 PUBLIC
2722 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2723 VkInstance instance,
2724 const char* pName);
2725
2726 PUBLIC
2727 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2728 VkInstance instance,
2729 const char* pName)
2730 {
2731 return radv_GetInstanceProcAddr(instance, pName);
2732 }
2733
2734 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2735 VkDevice _device,
2736 const char* pName)
2737 {
2738 RADV_FROM_HANDLE(radv_device, device, _device);
2739
2740 return radv_lookup_entrypoint_checked(pName,
2741 device->instance->apiVersion,
2742 &device->instance->enabled_extensions,
2743 &device->enabled_extensions);
2744 }
2745
2746 bool radv_get_memory_fd(struct radv_device *device,
2747 struct radv_device_memory *memory,
2748 int *pFD)
2749 {
2750 struct radeon_bo_metadata metadata;
2751
2752 if (memory->image) {
2753 radv_init_metadata(device, memory->image, &metadata);
2754 device->ws->buffer_set_metadata(memory->bo, &metadata);
2755 }
2756
2757 return device->ws->buffer_get_fd(device->ws, memory->bo,
2758 pFD);
2759 }
2760
2761 static VkResult radv_alloc_memory(struct radv_device *device,
2762 const VkMemoryAllocateInfo* pAllocateInfo,
2763 const VkAllocationCallbacks* pAllocator,
2764 VkDeviceMemory* pMem)
2765 {
2766 struct radv_device_memory *mem;
2767 VkResult result;
2768 enum radeon_bo_domain domain;
2769 uint32_t flags = 0;
2770 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2771
2772 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2773
2774 if (pAllocateInfo->allocationSize == 0) {
2775 /* Apparently, this is allowed */
2776 *pMem = VK_NULL_HANDLE;
2777 return VK_SUCCESS;
2778 }
2779
2780 const VkImportMemoryFdInfoKHR *import_info =
2781 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2782 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2783 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2784 const VkExportMemoryAllocateInfoKHR *export_info =
2785 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2786 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2787 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2788
2789 const struct wsi_memory_allocate_info *wsi_info =
2790 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2791
2792 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2793 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2794 if (mem == NULL)
2795 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2796
2797 if (wsi_info && wsi_info->implicit_sync)
2798 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2799
2800 if (dedicate_info) {
2801 mem->image = radv_image_from_handle(dedicate_info->image);
2802 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2803 } else {
2804 mem->image = NULL;
2805 mem->buffer = NULL;
2806 }
2807
2808 mem->user_ptr = NULL;
2809
2810 if (import_info) {
2811 assert(import_info->handleType ==
2812 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2813 import_info->handleType ==
2814 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2815 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2816 NULL, NULL);
2817 if (!mem->bo) {
2818 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2819 goto fail;
2820 } else {
2821 close(import_info->fd);
2822 }
2823 } else if (host_ptr_info) {
2824 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2825 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2826 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2827 pAllocateInfo->allocationSize);
2828 if (!mem->bo) {
2829 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2830 goto fail;
2831 } else {
2832 mem->user_ptr = host_ptr_info->pHostPointer;
2833 }
2834 } else {
2835 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2836 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2837 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2838 domain = RADEON_DOMAIN_GTT;
2839 else
2840 domain = RADEON_DOMAIN_VRAM;
2841
2842 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2843 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2844 else
2845 flags |= RADEON_FLAG_CPU_ACCESS;
2846
2847 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2848 flags |= RADEON_FLAG_GTT_WC;
2849
2850 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2851 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2852
2853 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2854 domain, flags);
2855
2856 if (!mem->bo) {
2857 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2858 goto fail;
2859 }
2860 mem->type_index = mem_type_index;
2861 }
2862
2863 result = radv_bo_list_add(device, mem->bo);
2864 if (result != VK_SUCCESS)
2865 goto fail_bo;
2866
2867 *pMem = radv_device_memory_to_handle(mem);
2868
2869 return VK_SUCCESS;
2870
2871 fail_bo:
2872 device->ws->buffer_destroy(mem->bo);
2873 fail:
2874 vk_free2(&device->alloc, pAllocator, mem);
2875
2876 return result;
2877 }
2878
2879 VkResult radv_AllocateMemory(
2880 VkDevice _device,
2881 const VkMemoryAllocateInfo* pAllocateInfo,
2882 const VkAllocationCallbacks* pAllocator,
2883 VkDeviceMemory* pMem)
2884 {
2885 RADV_FROM_HANDLE(radv_device, device, _device);
2886 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2887 }
2888
2889 void radv_FreeMemory(
2890 VkDevice _device,
2891 VkDeviceMemory _mem,
2892 const VkAllocationCallbacks* pAllocator)
2893 {
2894 RADV_FROM_HANDLE(radv_device, device, _device);
2895 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2896
2897 if (mem == NULL)
2898 return;
2899
2900 radv_bo_list_remove(device, mem->bo);
2901 device->ws->buffer_destroy(mem->bo);
2902 mem->bo = NULL;
2903
2904 vk_free2(&device->alloc, pAllocator, mem);
2905 }
2906
2907 VkResult radv_MapMemory(
2908 VkDevice _device,
2909 VkDeviceMemory _memory,
2910 VkDeviceSize offset,
2911 VkDeviceSize size,
2912 VkMemoryMapFlags flags,
2913 void** ppData)
2914 {
2915 RADV_FROM_HANDLE(radv_device, device, _device);
2916 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2917
2918 if (mem == NULL) {
2919 *ppData = NULL;
2920 return VK_SUCCESS;
2921 }
2922
2923 if (mem->user_ptr)
2924 *ppData = mem->user_ptr;
2925 else
2926 *ppData = device->ws->buffer_map(mem->bo);
2927
2928 if (*ppData) {
2929 *ppData += offset;
2930 return VK_SUCCESS;
2931 }
2932
2933 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2934 }
2935
2936 void radv_UnmapMemory(
2937 VkDevice _device,
2938 VkDeviceMemory _memory)
2939 {
2940 RADV_FROM_HANDLE(radv_device, device, _device);
2941 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2942
2943 if (mem == NULL)
2944 return;
2945
2946 if (mem->user_ptr == NULL)
2947 device->ws->buffer_unmap(mem->bo);
2948 }
2949
2950 VkResult radv_FlushMappedMemoryRanges(
2951 VkDevice _device,
2952 uint32_t memoryRangeCount,
2953 const VkMappedMemoryRange* pMemoryRanges)
2954 {
2955 return VK_SUCCESS;
2956 }
2957
2958 VkResult radv_InvalidateMappedMemoryRanges(
2959 VkDevice _device,
2960 uint32_t memoryRangeCount,
2961 const VkMappedMemoryRange* pMemoryRanges)
2962 {
2963 return VK_SUCCESS;
2964 }
2965
2966 void radv_GetBufferMemoryRequirements(
2967 VkDevice _device,
2968 VkBuffer _buffer,
2969 VkMemoryRequirements* pMemoryRequirements)
2970 {
2971 RADV_FROM_HANDLE(radv_device, device, _device);
2972 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2973
2974 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
2975
2976 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2977 pMemoryRequirements->alignment = 4096;
2978 else
2979 pMemoryRequirements->alignment = 16;
2980
2981 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2982 }
2983
2984 void radv_GetBufferMemoryRequirements2(
2985 VkDevice device,
2986 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2987 VkMemoryRequirements2KHR* pMemoryRequirements)
2988 {
2989 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2990 &pMemoryRequirements->memoryRequirements);
2991 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
2992 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2993 switch (ext->sType) {
2994 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2995 VkMemoryDedicatedRequirementsKHR *req =
2996 (VkMemoryDedicatedRequirementsKHR *) ext;
2997 req->requiresDedicatedAllocation = buffer->shareable;
2998 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2999 break;
3000 }
3001 default:
3002 break;
3003 }
3004 }
3005 }
3006
3007 void radv_GetImageMemoryRequirements(
3008 VkDevice _device,
3009 VkImage _image,
3010 VkMemoryRequirements* pMemoryRequirements)
3011 {
3012 RADV_FROM_HANDLE(radv_device, device, _device);
3013 RADV_FROM_HANDLE(radv_image, image, _image);
3014
3015 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3016
3017 pMemoryRequirements->size = image->size;
3018 pMemoryRequirements->alignment = image->alignment;
3019 }
3020
3021 void radv_GetImageMemoryRequirements2(
3022 VkDevice device,
3023 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3024 VkMemoryRequirements2KHR* pMemoryRequirements)
3025 {
3026 radv_GetImageMemoryRequirements(device, pInfo->image,
3027 &pMemoryRequirements->memoryRequirements);
3028
3029 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3030
3031 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3032 switch (ext->sType) {
3033 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3034 VkMemoryDedicatedRequirementsKHR *req =
3035 (VkMemoryDedicatedRequirementsKHR *) ext;
3036 req->requiresDedicatedAllocation = image->shareable;
3037 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3038 break;
3039 }
3040 default:
3041 break;
3042 }
3043 }
3044 }
3045
3046 void radv_GetImageSparseMemoryRequirements(
3047 VkDevice device,
3048 VkImage image,
3049 uint32_t* pSparseMemoryRequirementCount,
3050 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3051 {
3052 stub();
3053 }
3054
3055 void radv_GetImageSparseMemoryRequirements2(
3056 VkDevice device,
3057 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3058 uint32_t* pSparseMemoryRequirementCount,
3059 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3060 {
3061 stub();
3062 }
3063
3064 void radv_GetDeviceMemoryCommitment(
3065 VkDevice device,
3066 VkDeviceMemory memory,
3067 VkDeviceSize* pCommittedMemoryInBytes)
3068 {
3069 *pCommittedMemoryInBytes = 0;
3070 }
3071
3072 VkResult radv_BindBufferMemory2(VkDevice device,
3073 uint32_t bindInfoCount,
3074 const VkBindBufferMemoryInfoKHR *pBindInfos)
3075 {
3076 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3077 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3078 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3079
3080 if (mem) {
3081 buffer->bo = mem->bo;
3082 buffer->offset = pBindInfos[i].memoryOffset;
3083 } else {
3084 buffer->bo = NULL;
3085 }
3086 }
3087 return VK_SUCCESS;
3088 }
3089
3090 VkResult radv_BindBufferMemory(
3091 VkDevice device,
3092 VkBuffer buffer,
3093 VkDeviceMemory memory,
3094 VkDeviceSize memoryOffset)
3095 {
3096 const VkBindBufferMemoryInfoKHR info = {
3097 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3098 .buffer = buffer,
3099 .memory = memory,
3100 .memoryOffset = memoryOffset
3101 };
3102
3103 return radv_BindBufferMemory2(device, 1, &info);
3104 }
3105
3106 VkResult radv_BindImageMemory2(VkDevice device,
3107 uint32_t bindInfoCount,
3108 const VkBindImageMemoryInfoKHR *pBindInfos)
3109 {
3110 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3111 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3112 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3113
3114 if (mem) {
3115 image->bo = mem->bo;
3116 image->offset = pBindInfos[i].memoryOffset;
3117 } else {
3118 image->bo = NULL;
3119 image->offset = 0;
3120 }
3121 }
3122 return VK_SUCCESS;
3123 }
3124
3125
3126 VkResult radv_BindImageMemory(
3127 VkDevice device,
3128 VkImage image,
3129 VkDeviceMemory memory,
3130 VkDeviceSize memoryOffset)
3131 {
3132 const VkBindImageMemoryInfoKHR info = {
3133 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3134 .image = image,
3135 .memory = memory,
3136 .memoryOffset = memoryOffset
3137 };
3138
3139 return radv_BindImageMemory2(device, 1, &info);
3140 }
3141
3142
3143 static void
3144 radv_sparse_buffer_bind_memory(struct radv_device *device,
3145 const VkSparseBufferMemoryBindInfo *bind)
3146 {
3147 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3148
3149 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3150 struct radv_device_memory *mem = NULL;
3151
3152 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3153 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3154
3155 device->ws->buffer_virtual_bind(buffer->bo,
3156 bind->pBinds[i].resourceOffset,
3157 bind->pBinds[i].size,
3158 mem ? mem->bo : NULL,
3159 bind->pBinds[i].memoryOffset);
3160 }
3161 }
3162
3163 static void
3164 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3165 const VkSparseImageOpaqueMemoryBindInfo *bind)
3166 {
3167 RADV_FROM_HANDLE(radv_image, image, bind->image);
3168
3169 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3170 struct radv_device_memory *mem = NULL;
3171
3172 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3173 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3174
3175 device->ws->buffer_virtual_bind(image->bo,
3176 bind->pBinds[i].resourceOffset,
3177 bind->pBinds[i].size,
3178 mem ? mem->bo : NULL,
3179 bind->pBinds[i].memoryOffset);
3180 }
3181 }
3182
3183 VkResult radv_QueueBindSparse(
3184 VkQueue _queue,
3185 uint32_t bindInfoCount,
3186 const VkBindSparseInfo* pBindInfo,
3187 VkFence _fence)
3188 {
3189 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3190 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3191 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3192 bool fence_emitted = false;
3193 VkResult result;
3194 int ret;
3195
3196 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3197 struct radv_winsys_sem_info sem_info;
3198 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3199 radv_sparse_buffer_bind_memory(queue->device,
3200 pBindInfo[i].pBufferBinds + j);
3201 }
3202
3203 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3204 radv_sparse_image_opaque_bind_memory(queue->device,
3205 pBindInfo[i].pImageOpaqueBinds + j);
3206 }
3207
3208 VkResult result;
3209 result = radv_alloc_sem_info(queue->device->instance,
3210 &sem_info,
3211 pBindInfo[i].waitSemaphoreCount,
3212 pBindInfo[i].pWaitSemaphores,
3213 pBindInfo[i].signalSemaphoreCount,
3214 pBindInfo[i].pSignalSemaphores,
3215 _fence);
3216 if (result != VK_SUCCESS)
3217 return result;
3218
3219 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3220 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3221 &queue->device->empty_cs[queue->queue_family_index],
3222 1, NULL, NULL,
3223 &sem_info, NULL,
3224 false, base_fence);
3225 if (ret) {
3226 radv_loge("failed to submit CS %d\n", i);
3227 abort();
3228 }
3229
3230 fence_emitted = true;
3231 if (fence)
3232 fence->submitted = true;
3233 }
3234
3235 radv_free_sem_info(&sem_info);
3236
3237 }
3238
3239 if (fence) {
3240 if (!fence_emitted) {
3241 result = radv_signal_fence(queue, fence);
3242 if (result != VK_SUCCESS)
3243 return result;
3244 }
3245 fence->submitted = true;
3246 }
3247
3248 return VK_SUCCESS;
3249 }
3250
3251 VkResult radv_CreateFence(
3252 VkDevice _device,
3253 const VkFenceCreateInfo* pCreateInfo,
3254 const VkAllocationCallbacks* pAllocator,
3255 VkFence* pFence)
3256 {
3257 RADV_FROM_HANDLE(radv_device, device, _device);
3258 const VkExportFenceCreateInfoKHR *export =
3259 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3260 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3261 export ? export->handleTypes : 0;
3262
3263 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3264 sizeof(*fence), 8,
3265 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3266
3267 if (!fence)
3268 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3269
3270 fence->fence_wsi = NULL;
3271 fence->submitted = false;
3272 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3273 fence->temp_syncobj = 0;
3274 if (device->always_use_syncobj || handleTypes) {
3275 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3276 if (ret) {
3277 vk_free2(&device->alloc, pAllocator, fence);
3278 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3279 }
3280 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3281 device->ws->signal_syncobj(device->ws, fence->syncobj);
3282 }
3283 fence->fence = NULL;
3284 } else {
3285 fence->fence = device->ws->create_fence();
3286 if (!fence->fence) {
3287 vk_free2(&device->alloc, pAllocator, fence);
3288 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3289 }
3290 fence->syncobj = 0;
3291 }
3292
3293 *pFence = radv_fence_to_handle(fence);
3294
3295 return VK_SUCCESS;
3296 }
3297
3298 void radv_DestroyFence(
3299 VkDevice _device,
3300 VkFence _fence,
3301 const VkAllocationCallbacks* pAllocator)
3302 {
3303 RADV_FROM_HANDLE(radv_device, device, _device);
3304 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3305
3306 if (!fence)
3307 return;
3308
3309 if (fence->temp_syncobj)
3310 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3311 if (fence->syncobj)
3312 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3313 if (fence->fence)
3314 device->ws->destroy_fence(fence->fence);
3315 if (fence->fence_wsi)
3316 fence->fence_wsi->destroy(fence->fence_wsi);
3317 vk_free2(&device->alloc, pAllocator, fence);
3318 }
3319
3320
3321 static uint64_t radv_get_current_time()
3322 {
3323 struct timespec tv;
3324 clock_gettime(CLOCK_MONOTONIC, &tv);
3325 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3326 }
3327
3328 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3329 {
3330 uint64_t current_time = radv_get_current_time();
3331
3332 timeout = MIN2(UINT64_MAX - current_time, timeout);
3333
3334 return current_time + timeout;
3335 }
3336
3337
3338 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3339 {
3340 for (uint32_t i = 0; i < fenceCount; ++i) {
3341 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3342 if (fence->fence == NULL || fence->syncobj ||
3343 fence->temp_syncobj ||
3344 (!fence->signalled && !fence->submitted))
3345 return false;
3346 }
3347 return true;
3348 }
3349
3350 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3351 {
3352 for (uint32_t i = 0; i < fenceCount; ++i) {
3353 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3354 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3355 return false;
3356 }
3357 return true;
3358 }
3359
3360 VkResult radv_WaitForFences(
3361 VkDevice _device,
3362 uint32_t fenceCount,
3363 const VkFence* pFences,
3364 VkBool32 waitAll,
3365 uint64_t timeout)
3366 {
3367 RADV_FROM_HANDLE(radv_device, device, _device);
3368 timeout = radv_get_absolute_timeout(timeout);
3369
3370 if (device->always_use_syncobj &&
3371 radv_all_fences_syncobj(fenceCount, pFences))
3372 {
3373 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3374 if (!handles)
3375 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3376
3377 for (uint32_t i = 0; i < fenceCount; ++i) {
3378 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3379 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3380 }
3381
3382 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3383
3384 free(handles);
3385 return success ? VK_SUCCESS : VK_TIMEOUT;
3386 }
3387
3388 if (!waitAll && fenceCount > 1) {
3389 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3390 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3391 uint32_t wait_count = 0;
3392 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3393 if (!fences)
3394 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3395
3396 for (uint32_t i = 0; i < fenceCount; ++i) {
3397 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3398
3399 if (fence->signalled) {
3400 free(fences);
3401 return VK_SUCCESS;
3402 }
3403
3404 fences[wait_count++] = fence->fence;
3405 }
3406
3407 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3408 waitAll, timeout - radv_get_current_time());
3409
3410 free(fences);
3411 return success ? VK_SUCCESS : VK_TIMEOUT;
3412 }
3413
3414 while(radv_get_current_time() <= timeout) {
3415 for (uint32_t i = 0; i < fenceCount; ++i) {
3416 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3417 return VK_SUCCESS;
3418 }
3419 }
3420 return VK_TIMEOUT;
3421 }
3422
3423 for (uint32_t i = 0; i < fenceCount; ++i) {
3424 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3425 bool expired = false;
3426
3427 if (fence->temp_syncobj) {
3428 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3429 return VK_TIMEOUT;
3430 continue;
3431 }
3432
3433 if (fence->syncobj) {
3434 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3435 return VK_TIMEOUT;
3436 continue;
3437 }
3438
3439 if (fence->signalled)
3440 continue;
3441
3442 if (fence->fence) {
3443 if (!fence->submitted) {
3444 while(radv_get_current_time() <= timeout &&
3445 !fence->submitted)
3446 /* Do nothing */;
3447
3448 if (!fence->submitted)
3449 return VK_TIMEOUT;
3450
3451 /* Recheck as it may have been set by
3452 * submitting operations. */
3453
3454 if (fence->signalled)
3455 continue;
3456 }
3457
3458 expired = device->ws->fence_wait(device->ws,
3459 fence->fence,
3460 true, timeout);
3461 if (!expired)
3462 return VK_TIMEOUT;
3463 }
3464
3465 if (fence->fence_wsi) {
3466 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3467 if (result != VK_SUCCESS)
3468 return result;
3469 }
3470
3471 fence->signalled = true;
3472 }
3473
3474 return VK_SUCCESS;
3475 }
3476
3477 VkResult radv_ResetFences(VkDevice _device,
3478 uint32_t fenceCount,
3479 const VkFence *pFences)
3480 {
3481 RADV_FROM_HANDLE(radv_device, device, _device);
3482
3483 for (unsigned i = 0; i < fenceCount; ++i) {
3484 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3485 fence->submitted = fence->signalled = false;
3486
3487 /* Per spec, we first restore the permanent payload, and then reset, so
3488 * having a temp syncobj should not skip resetting the permanent syncobj. */
3489 if (fence->temp_syncobj) {
3490 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3491 fence->temp_syncobj = 0;
3492 }
3493
3494 if (fence->syncobj) {
3495 device->ws->reset_syncobj(device->ws, fence->syncobj);
3496 }
3497 }
3498
3499 return VK_SUCCESS;
3500 }
3501
3502 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3503 {
3504 RADV_FROM_HANDLE(radv_device, device, _device);
3505 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3506
3507 if (fence->temp_syncobj) {
3508 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3509 return success ? VK_SUCCESS : VK_NOT_READY;
3510 }
3511
3512 if (fence->syncobj) {
3513 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3514 return success ? VK_SUCCESS : VK_NOT_READY;
3515 }
3516
3517 if (fence->signalled)
3518 return VK_SUCCESS;
3519 if (!fence->submitted)
3520 return VK_NOT_READY;
3521 if (fence->fence) {
3522 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3523 return VK_NOT_READY;
3524 }
3525 if (fence->fence_wsi) {
3526 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3527
3528 if (result != VK_SUCCESS) {
3529 if (result == VK_TIMEOUT)
3530 return VK_NOT_READY;
3531 return result;
3532 }
3533 }
3534 return VK_SUCCESS;
3535 }
3536
3537
3538 // Queue semaphore functions
3539
3540 VkResult radv_CreateSemaphore(
3541 VkDevice _device,
3542 const VkSemaphoreCreateInfo* pCreateInfo,
3543 const VkAllocationCallbacks* pAllocator,
3544 VkSemaphore* pSemaphore)
3545 {
3546 RADV_FROM_HANDLE(radv_device, device, _device);
3547 const VkExportSemaphoreCreateInfoKHR *export =
3548 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3549 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3550 export ? export->handleTypes : 0;
3551
3552 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3553 sizeof(*sem), 8,
3554 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3555 if (!sem)
3556 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3557
3558 sem->temp_syncobj = 0;
3559 /* create a syncobject if we are going to export this semaphore */
3560 if (device->always_use_syncobj || handleTypes) {
3561 assert (device->physical_device->rad_info.has_syncobj);
3562 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3563 if (ret) {
3564 vk_free2(&device->alloc, pAllocator, sem);
3565 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3566 }
3567 sem->sem = NULL;
3568 } else {
3569 sem->sem = device->ws->create_sem(device->ws);
3570 if (!sem->sem) {
3571 vk_free2(&device->alloc, pAllocator, sem);
3572 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3573 }
3574 sem->syncobj = 0;
3575 }
3576
3577 *pSemaphore = radv_semaphore_to_handle(sem);
3578 return VK_SUCCESS;
3579 }
3580
3581 void radv_DestroySemaphore(
3582 VkDevice _device,
3583 VkSemaphore _semaphore,
3584 const VkAllocationCallbacks* pAllocator)
3585 {
3586 RADV_FROM_HANDLE(radv_device, device, _device);
3587 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3588 if (!_semaphore)
3589 return;
3590
3591 if (sem->syncobj)
3592 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3593 else
3594 device->ws->destroy_sem(sem->sem);
3595 vk_free2(&device->alloc, pAllocator, sem);
3596 }
3597
3598 VkResult radv_CreateEvent(
3599 VkDevice _device,
3600 const VkEventCreateInfo* pCreateInfo,
3601 const VkAllocationCallbacks* pAllocator,
3602 VkEvent* pEvent)
3603 {
3604 RADV_FROM_HANDLE(radv_device, device, _device);
3605 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3606 sizeof(*event), 8,
3607 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3608
3609 if (!event)
3610 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3611
3612 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3613 RADEON_DOMAIN_GTT,
3614 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3615 if (!event->bo) {
3616 vk_free2(&device->alloc, pAllocator, event);
3617 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3618 }
3619
3620 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3621
3622 *pEvent = radv_event_to_handle(event);
3623
3624 return VK_SUCCESS;
3625 }
3626
3627 void radv_DestroyEvent(
3628 VkDevice _device,
3629 VkEvent _event,
3630 const VkAllocationCallbacks* pAllocator)
3631 {
3632 RADV_FROM_HANDLE(radv_device, device, _device);
3633 RADV_FROM_HANDLE(radv_event, event, _event);
3634
3635 if (!event)
3636 return;
3637 device->ws->buffer_destroy(event->bo);
3638 vk_free2(&device->alloc, pAllocator, event);
3639 }
3640
3641 VkResult radv_GetEventStatus(
3642 VkDevice _device,
3643 VkEvent _event)
3644 {
3645 RADV_FROM_HANDLE(radv_event, event, _event);
3646
3647 if (*event->map == 1)
3648 return VK_EVENT_SET;
3649 return VK_EVENT_RESET;
3650 }
3651
3652 VkResult radv_SetEvent(
3653 VkDevice _device,
3654 VkEvent _event)
3655 {
3656 RADV_FROM_HANDLE(radv_event, event, _event);
3657 *event->map = 1;
3658
3659 return VK_SUCCESS;
3660 }
3661
3662 VkResult radv_ResetEvent(
3663 VkDevice _device,
3664 VkEvent _event)
3665 {
3666 RADV_FROM_HANDLE(radv_event, event, _event);
3667 *event->map = 0;
3668
3669 return VK_SUCCESS;
3670 }
3671
3672 VkResult radv_CreateBuffer(
3673 VkDevice _device,
3674 const VkBufferCreateInfo* pCreateInfo,
3675 const VkAllocationCallbacks* pAllocator,
3676 VkBuffer* pBuffer)
3677 {
3678 RADV_FROM_HANDLE(radv_device, device, _device);
3679 struct radv_buffer *buffer;
3680
3681 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3682
3683 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3684 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3685 if (buffer == NULL)
3686 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3687
3688 buffer->size = pCreateInfo->size;
3689 buffer->usage = pCreateInfo->usage;
3690 buffer->bo = NULL;
3691 buffer->offset = 0;
3692 buffer->flags = pCreateInfo->flags;
3693
3694 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3695 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3696
3697 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3698 buffer->bo = device->ws->buffer_create(device->ws,
3699 align64(buffer->size, 4096),
3700 4096, 0, RADEON_FLAG_VIRTUAL);
3701 if (!buffer->bo) {
3702 vk_free2(&device->alloc, pAllocator, buffer);
3703 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3704 }
3705 }
3706
3707 *pBuffer = radv_buffer_to_handle(buffer);
3708
3709 return VK_SUCCESS;
3710 }
3711
3712 void radv_DestroyBuffer(
3713 VkDevice _device,
3714 VkBuffer _buffer,
3715 const VkAllocationCallbacks* pAllocator)
3716 {
3717 RADV_FROM_HANDLE(radv_device, device, _device);
3718 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3719
3720 if (!buffer)
3721 return;
3722
3723 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3724 device->ws->buffer_destroy(buffer->bo);
3725
3726 vk_free2(&device->alloc, pAllocator, buffer);
3727 }
3728
3729 static inline unsigned
3730 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3731 {
3732 if (stencil)
3733 return image->surface.u.legacy.stencil_tiling_index[level];
3734 else
3735 return image->surface.u.legacy.tiling_index[level];
3736 }
3737
3738 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3739 {
3740 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3741 }
3742
3743 static uint32_t
3744 radv_init_dcc_control_reg(struct radv_device *device,
3745 struct radv_image_view *iview)
3746 {
3747 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3748 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3749 unsigned max_compressed_block_size;
3750 unsigned independent_64b_blocks;
3751
3752 if (device->physical_device->rad_info.chip_class < VI)
3753 return 0;
3754
3755 if (iview->image->info.samples > 1) {
3756 if (iview->image->surface.bpe == 1)
3757 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3758 else if (iview->image->surface.bpe == 2)
3759 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3760 }
3761
3762 if (!device->physical_device->rad_info.has_dedicated_vram) {
3763 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3764 * dGPU and 64 for APU because all of our APUs to date use
3765 * DIMMs which have a request granularity size of 64B while all
3766 * other chips have a 32B request size.
3767 */
3768 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3769 }
3770
3771 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3772 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3773 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3774 /* If this DCC image is potentially going to be used in texture
3775 * fetches, we need some special settings.
3776 */
3777 independent_64b_blocks = 1;
3778 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3779 } else {
3780 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3781 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3782 * big as possible for better compression state.
3783 */
3784 independent_64b_blocks = 0;
3785 max_compressed_block_size = max_uncompressed_block_size;
3786 }
3787
3788 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3789 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3790 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3791 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3792 }
3793
3794 static void
3795 radv_initialise_color_surface(struct radv_device *device,
3796 struct radv_color_buffer_info *cb,
3797 struct radv_image_view *iview)
3798 {
3799 const struct vk_format_description *desc;
3800 unsigned ntype, format, swap, endian;
3801 unsigned blend_clamp = 0, blend_bypass = 0;
3802 uint64_t va;
3803 const struct radeon_surf *surf = &iview->image->surface;
3804
3805 desc = vk_format_description(iview->vk_format);
3806
3807 memset(cb, 0, sizeof(*cb));
3808
3809 /* Intensity is implemented as Red, so treat it that way. */
3810 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3811
3812 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3813
3814 cb->cb_color_base = va >> 8;
3815
3816 if (device->physical_device->rad_info.chip_class >= GFX9) {
3817 struct gfx9_surf_meta_flags meta;
3818 if (iview->image->dcc_offset)
3819 meta = iview->image->surface.u.gfx9.dcc;
3820 else
3821 meta = iview->image->surface.u.gfx9.cmask;
3822
3823 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3824 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3825 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3826 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3827
3828 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3829 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3830 } else {
3831 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3832 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3833
3834 cb->cb_color_base += level_info->offset >> 8;
3835 if (level_info->mode == RADEON_SURF_MODE_2D)
3836 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3837
3838 pitch_tile_max = level_info->nblk_x / 8 - 1;
3839 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3840 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3841
3842 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3843 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3844 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3845
3846 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3847
3848 if (radv_image_has_fmask(iview->image)) {
3849 if (device->physical_device->rad_info.chip_class >= CIK)
3850 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3851 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3852 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3853 } else {
3854 /* This must be set for fast clear to work without FMASK. */
3855 if (device->physical_device->rad_info.chip_class >= CIK)
3856 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3857 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3858 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3859 }
3860 }
3861
3862 /* CMASK variables */
3863 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3864 va += iview->image->cmask.offset;
3865 cb->cb_color_cmask = va >> 8;
3866
3867 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3868 va += iview->image->dcc_offset;
3869 cb->cb_dcc_base = va >> 8;
3870 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3871
3872 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3873 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3874 S_028C6C_SLICE_MAX(max_slice);
3875
3876 if (iview->image->info.samples > 1) {
3877 unsigned log_samples = util_logbase2(iview->image->info.samples);
3878
3879 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3880 S_028C74_NUM_FRAGMENTS(log_samples);
3881 }
3882
3883 if (radv_image_has_fmask(iview->image)) {
3884 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3885 cb->cb_color_fmask = va >> 8;
3886 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3887 } else {
3888 cb->cb_color_fmask = cb->cb_color_base;
3889 }
3890
3891 ntype = radv_translate_color_numformat(iview->vk_format,
3892 desc,
3893 vk_format_get_first_non_void_channel(iview->vk_format));
3894 format = radv_translate_colorformat(iview->vk_format);
3895 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3896 radv_finishme("Illegal color\n");
3897 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3898 endian = radv_colorformat_endian_swap(format);
3899
3900 /* blend clamp should be set for all NORM/SRGB types */
3901 if (ntype == V_028C70_NUMBER_UNORM ||
3902 ntype == V_028C70_NUMBER_SNORM ||
3903 ntype == V_028C70_NUMBER_SRGB)
3904 blend_clamp = 1;
3905
3906 /* set blend bypass according to docs if SINT/UINT or
3907 8/24 COLOR variants */
3908 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3909 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3910 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3911 blend_clamp = 0;
3912 blend_bypass = 1;
3913 }
3914 #if 0
3915 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3916 (format == V_028C70_COLOR_8 ||
3917 format == V_028C70_COLOR_8_8 ||
3918 format == V_028C70_COLOR_8_8_8_8))
3919 ->color_is_int8 = true;
3920 #endif
3921 cb->cb_color_info = S_028C70_FORMAT(format) |
3922 S_028C70_COMP_SWAP(swap) |
3923 S_028C70_BLEND_CLAMP(blend_clamp) |
3924 S_028C70_BLEND_BYPASS(blend_bypass) |
3925 S_028C70_SIMPLE_FLOAT(1) |
3926 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3927 ntype != V_028C70_NUMBER_SNORM &&
3928 ntype != V_028C70_NUMBER_SRGB &&
3929 format != V_028C70_COLOR_8_24 &&
3930 format != V_028C70_COLOR_24_8) |
3931 S_028C70_NUMBER_TYPE(ntype) |
3932 S_028C70_ENDIAN(endian);
3933 if (radv_image_has_fmask(iview->image)) {
3934 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3935 if (device->physical_device->rad_info.chip_class == SI) {
3936 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3937 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3938 }
3939 }
3940
3941 if (radv_image_has_cmask(iview->image) &&
3942 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3943 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3944
3945 if (radv_dcc_enabled(iview->image, iview->base_mip))
3946 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3947
3948 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3949
3950 /* This must be set for fast clear to work without FMASK. */
3951 if (!radv_image_has_fmask(iview->image) &&
3952 device->physical_device->rad_info.chip_class == SI) {
3953 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3954 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3955 }
3956
3957 if (device->physical_device->rad_info.chip_class >= GFX9) {
3958 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3959 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3960
3961 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3962 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3963 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3964 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3965 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3966 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3967 }
3968 }
3969
3970 static unsigned
3971 radv_calc_decompress_on_z_planes(struct radv_device *device,
3972 struct radv_image_view *iview)
3973 {
3974 unsigned max_zplanes = 0;
3975
3976 assert(radv_image_is_tc_compat_htile(iview->image));
3977
3978 if (device->physical_device->rad_info.chip_class >= GFX9) {
3979 /* Default value for 32-bit depth surfaces. */
3980 max_zplanes = 4;
3981
3982 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3983 iview->image->info.samples > 1)
3984 max_zplanes = 2;
3985
3986 max_zplanes = max_zplanes + 1;
3987 } else {
3988 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
3989 /* Do not enable Z plane compression for 16-bit depth
3990 * surfaces because isn't supported on GFX8. Only
3991 * 32-bit depth surfaces are supported by the hardware.
3992 * This allows to maintain shader compatibility and to
3993 * reduce the number of depth decompressions.
3994 */
3995 max_zplanes = 1;
3996 } else {
3997 if (iview->image->info.samples <= 1)
3998 max_zplanes = 5;
3999 else if (iview->image->info.samples <= 4)
4000 max_zplanes = 3;
4001 else
4002 max_zplanes = 2;
4003 }
4004 }
4005
4006 return max_zplanes;
4007 }
4008
4009 static void
4010 radv_initialise_ds_surface(struct radv_device *device,
4011 struct radv_ds_buffer_info *ds,
4012 struct radv_image_view *iview)
4013 {
4014 unsigned level = iview->base_mip;
4015 unsigned format, stencil_format;
4016 uint64_t va, s_offs, z_offs;
4017 bool stencil_only = false;
4018 memset(ds, 0, sizeof(*ds));
4019 switch (iview->image->vk_format) {
4020 case VK_FORMAT_D24_UNORM_S8_UINT:
4021 case VK_FORMAT_X8_D24_UNORM_PACK32:
4022 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4023 ds->offset_scale = 2.0f;
4024 break;
4025 case VK_FORMAT_D16_UNORM:
4026 case VK_FORMAT_D16_UNORM_S8_UINT:
4027 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4028 ds->offset_scale = 4.0f;
4029 break;
4030 case VK_FORMAT_D32_SFLOAT:
4031 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4032 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4033 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4034 ds->offset_scale = 1.0f;
4035 break;
4036 case VK_FORMAT_S8_UINT:
4037 stencil_only = true;
4038 break;
4039 default:
4040 break;
4041 }
4042
4043 format = radv_translate_dbformat(iview->image->vk_format);
4044 stencil_format = iview->image->surface.has_stencil ?
4045 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4046
4047 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4048 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4049 S_028008_SLICE_MAX(max_slice);
4050
4051 ds->db_htile_data_base = 0;
4052 ds->db_htile_surface = 0;
4053
4054 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4055 s_offs = z_offs = va;
4056
4057 if (device->physical_device->rad_info.chip_class >= GFX9) {
4058 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4059 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4060
4061 ds->db_z_info = S_028038_FORMAT(format) |
4062 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4063 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4064 S_028038_MAXMIP(iview->image->info.levels - 1) |
4065 S_028038_ZRANGE_PRECISION(1);
4066 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4067 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4068
4069 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4070 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4071 ds->db_depth_view |= S_028008_MIPID(level);
4072
4073 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4074 S_02801C_Y_MAX(iview->image->info.height - 1);
4075
4076 if (radv_htile_enabled(iview->image, level)) {
4077 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4078
4079 if (radv_image_is_tc_compat_htile(iview->image)) {
4080 unsigned max_zplanes =
4081 radv_calc_decompress_on_z_planes(device, iview);
4082
4083 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4084 S_028038_ITERATE_FLUSH(1);
4085 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4086 }
4087
4088 if (!iview->image->surface.has_stencil)
4089 /* Use all of the htile_buffer for depth if there's no stencil. */
4090 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4091 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4092 iview->image->htile_offset;
4093 ds->db_htile_data_base = va >> 8;
4094 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4095 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4096 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4097 }
4098 } else {
4099 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4100
4101 if (stencil_only)
4102 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4103
4104 z_offs += iview->image->surface.u.legacy.level[level].offset;
4105 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4106
4107 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4108 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4109 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4110
4111 if (iview->image->info.samples > 1)
4112 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4113
4114 if (device->physical_device->rad_info.chip_class >= CIK) {
4115 struct radeon_info *info = &device->physical_device->rad_info;
4116 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4117 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4118 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4119 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4120 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4121 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4122
4123 if (stencil_only)
4124 tile_mode = stencil_tile_mode;
4125
4126 ds->db_depth_info |=
4127 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4128 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4129 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4130 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4131 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4132 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4133 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4134 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4135 } else {
4136 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4137 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4138 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4139 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4140 if (stencil_only)
4141 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4142 }
4143
4144 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4145 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4146 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4147
4148 if (radv_htile_enabled(iview->image, level)) {
4149 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4150
4151 if (!iview->image->surface.has_stencil &&
4152 !radv_image_is_tc_compat_htile(iview->image))
4153 /* Use all of the htile_buffer for depth if there's no stencil. */
4154 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4155
4156 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4157 iview->image->htile_offset;
4158 ds->db_htile_data_base = va >> 8;
4159 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4160
4161 if (radv_image_is_tc_compat_htile(iview->image)) {
4162 unsigned max_zplanes =
4163 radv_calc_decompress_on_z_planes(device, iview);
4164
4165 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4166 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4167 }
4168 }
4169 }
4170
4171 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4172 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4173 }
4174
4175 VkResult radv_CreateFramebuffer(
4176 VkDevice _device,
4177 const VkFramebufferCreateInfo* pCreateInfo,
4178 const VkAllocationCallbacks* pAllocator,
4179 VkFramebuffer* pFramebuffer)
4180 {
4181 RADV_FROM_HANDLE(radv_device, device, _device);
4182 struct radv_framebuffer *framebuffer;
4183
4184 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4185
4186 size_t size = sizeof(*framebuffer) +
4187 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4188 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4189 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4190 if (framebuffer == NULL)
4191 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4192
4193 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4194 framebuffer->width = pCreateInfo->width;
4195 framebuffer->height = pCreateInfo->height;
4196 framebuffer->layers = pCreateInfo->layers;
4197 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4198 VkImageView _iview = pCreateInfo->pAttachments[i];
4199 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4200 framebuffer->attachments[i].attachment = iview;
4201 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4202 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4203 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4204 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4205 }
4206 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4207 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4208 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4209 }
4210
4211 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4212 return VK_SUCCESS;
4213 }
4214
4215 void radv_DestroyFramebuffer(
4216 VkDevice _device,
4217 VkFramebuffer _fb,
4218 const VkAllocationCallbacks* pAllocator)
4219 {
4220 RADV_FROM_HANDLE(radv_device, device, _device);
4221 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4222
4223 if (!fb)
4224 return;
4225 vk_free2(&device->alloc, pAllocator, fb);
4226 }
4227
4228 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4229 {
4230 switch (address_mode) {
4231 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4232 return V_008F30_SQ_TEX_WRAP;
4233 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4234 return V_008F30_SQ_TEX_MIRROR;
4235 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4236 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4237 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4238 return V_008F30_SQ_TEX_CLAMP_BORDER;
4239 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4240 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4241 default:
4242 unreachable("illegal tex wrap mode");
4243 break;
4244 }
4245 }
4246
4247 static unsigned
4248 radv_tex_compare(VkCompareOp op)
4249 {
4250 switch (op) {
4251 case VK_COMPARE_OP_NEVER:
4252 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4253 case VK_COMPARE_OP_LESS:
4254 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4255 case VK_COMPARE_OP_EQUAL:
4256 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4257 case VK_COMPARE_OP_LESS_OR_EQUAL:
4258 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4259 case VK_COMPARE_OP_GREATER:
4260 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4261 case VK_COMPARE_OP_NOT_EQUAL:
4262 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4263 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4264 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4265 case VK_COMPARE_OP_ALWAYS:
4266 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4267 default:
4268 unreachable("illegal compare mode");
4269 break;
4270 }
4271 }
4272
4273 static unsigned
4274 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4275 {
4276 switch (filter) {
4277 case VK_FILTER_NEAREST:
4278 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4279 V_008F38_SQ_TEX_XY_FILTER_POINT);
4280 case VK_FILTER_LINEAR:
4281 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4282 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4283 case VK_FILTER_CUBIC_IMG:
4284 default:
4285 fprintf(stderr, "illegal texture filter");
4286 return 0;
4287 }
4288 }
4289
4290 static unsigned
4291 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4292 {
4293 switch (mode) {
4294 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4295 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4296 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4297 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4298 default:
4299 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4300 }
4301 }
4302
4303 static unsigned
4304 radv_tex_bordercolor(VkBorderColor bcolor)
4305 {
4306 switch (bcolor) {
4307 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4308 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4309 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4310 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4311 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4312 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4313 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4314 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4315 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4316 default:
4317 break;
4318 }
4319 return 0;
4320 }
4321
4322 static unsigned
4323 radv_tex_aniso_filter(unsigned filter)
4324 {
4325 if (filter < 2)
4326 return 0;
4327 if (filter < 4)
4328 return 1;
4329 if (filter < 8)
4330 return 2;
4331 if (filter < 16)
4332 return 3;
4333 return 4;
4334 }
4335
4336 static unsigned
4337 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4338 {
4339 switch (mode) {
4340 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4341 return SQ_IMG_FILTER_MODE_BLEND;
4342 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4343 return SQ_IMG_FILTER_MODE_MIN;
4344 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4345 return SQ_IMG_FILTER_MODE_MAX;
4346 default:
4347 break;
4348 }
4349 return 0;
4350 }
4351
4352 static void
4353 radv_init_sampler(struct radv_device *device,
4354 struct radv_sampler *sampler,
4355 const VkSamplerCreateInfo *pCreateInfo)
4356 {
4357 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4358 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4359 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4360 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4361 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4362
4363 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4364 vk_find_struct_const(pCreateInfo->pNext,
4365 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4366 if (sampler_reduction)
4367 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4368
4369 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4370 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4371 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4372 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4373 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4374 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4375 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4376 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4377 S_008F30_DISABLE_CUBE_WRAP(0) |
4378 S_008F30_COMPAT_MODE(is_vi) |
4379 S_008F30_FILTER_MODE(filter_mode));
4380 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4381 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4382 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4383 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4384 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4385 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4386 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4387 S_008F38_MIP_POINT_PRECLAMP(0) |
4388 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4389 S_008F38_FILTER_PREC_FIX(1) |
4390 S_008F38_ANISO_OVERRIDE(is_vi));
4391 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4392 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4393 }
4394
4395 VkResult radv_CreateSampler(
4396 VkDevice _device,
4397 const VkSamplerCreateInfo* pCreateInfo,
4398 const VkAllocationCallbacks* pAllocator,
4399 VkSampler* pSampler)
4400 {
4401 RADV_FROM_HANDLE(radv_device, device, _device);
4402 struct radv_sampler *sampler;
4403
4404 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4405
4406 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4407 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4408 if (!sampler)
4409 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4410
4411 radv_init_sampler(device, sampler, pCreateInfo);
4412 *pSampler = radv_sampler_to_handle(sampler);
4413
4414 return VK_SUCCESS;
4415 }
4416
4417 void radv_DestroySampler(
4418 VkDevice _device,
4419 VkSampler _sampler,
4420 const VkAllocationCallbacks* pAllocator)
4421 {
4422 RADV_FROM_HANDLE(radv_device, device, _device);
4423 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4424
4425 if (!sampler)
4426 return;
4427 vk_free2(&device->alloc, pAllocator, sampler);
4428 }
4429
4430 /* vk_icd.h does not declare this function, so we declare it here to
4431 * suppress Wmissing-prototypes.
4432 */
4433 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4434 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4435
4436 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4437 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4438 {
4439 /* For the full details on loader interface versioning, see
4440 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4441 * What follows is a condensed summary, to help you navigate the large and
4442 * confusing official doc.
4443 *
4444 * - Loader interface v0 is incompatible with later versions. We don't
4445 * support it.
4446 *
4447 * - In loader interface v1:
4448 * - The first ICD entrypoint called by the loader is
4449 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4450 * entrypoint.
4451 * - The ICD must statically expose no other Vulkan symbol unless it is
4452 * linked with -Bsymbolic.
4453 * - Each dispatchable Vulkan handle created by the ICD must be
4454 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4455 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4456 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4457 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4458 * such loader-managed surfaces.
4459 *
4460 * - Loader interface v2 differs from v1 in:
4461 * - The first ICD entrypoint called by the loader is
4462 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4463 * statically expose this entrypoint.
4464 *
4465 * - Loader interface v3 differs from v2 in:
4466 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4467 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4468 * because the loader no longer does so.
4469 */
4470 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4471 return VK_SUCCESS;
4472 }
4473
4474 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4475 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4476 int *pFD)
4477 {
4478 RADV_FROM_HANDLE(radv_device, device, _device);
4479 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4480
4481 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4482
4483 /* At the moment, we support only the below handle types. */
4484 assert(pGetFdInfo->handleType ==
4485 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4486 pGetFdInfo->handleType ==
4487 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4488
4489 bool ret = radv_get_memory_fd(device, memory, pFD);
4490 if (ret == false)
4491 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4492 return VK_SUCCESS;
4493 }
4494
4495 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4496 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4497 int fd,
4498 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4499 {
4500 RADV_FROM_HANDLE(radv_device, device, _device);
4501
4502 switch (handleType) {
4503 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4504 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4505 return VK_SUCCESS;
4506
4507 default:
4508 /* The valid usage section for this function says:
4509 *
4510 * "handleType must not be one of the handle types defined as
4511 * opaque."
4512 *
4513 * So opaque handle types fall into the default "unsupported" case.
4514 */
4515 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4516 }
4517 }
4518
4519 static VkResult radv_import_opaque_fd(struct radv_device *device,
4520 int fd,
4521 uint32_t *syncobj)
4522 {
4523 uint32_t syncobj_handle = 0;
4524 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4525 if (ret != 0)
4526 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4527
4528 if (*syncobj)
4529 device->ws->destroy_syncobj(device->ws, *syncobj);
4530
4531 *syncobj = syncobj_handle;
4532 close(fd);
4533
4534 return VK_SUCCESS;
4535 }
4536
4537 static VkResult radv_import_sync_fd(struct radv_device *device,
4538 int fd,
4539 uint32_t *syncobj)
4540 {
4541 /* If we create a syncobj we do it locally so that if we have an error, we don't
4542 * leave a syncobj in an undetermined state in the fence. */
4543 uint32_t syncobj_handle = *syncobj;
4544 if (!syncobj_handle) {
4545 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4546 if (ret) {
4547 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4548 }
4549 }
4550
4551 if (fd == -1) {
4552 device->ws->signal_syncobj(device->ws, syncobj_handle);
4553 } else {
4554 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4555 if (ret != 0)
4556 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4557 }
4558
4559 *syncobj = syncobj_handle;
4560 if (fd != -1)
4561 close(fd);
4562
4563 return VK_SUCCESS;
4564 }
4565
4566 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4567 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4568 {
4569 RADV_FROM_HANDLE(radv_device, device, _device);
4570 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4571 uint32_t *syncobj_dst = NULL;
4572
4573 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4574 syncobj_dst = &sem->temp_syncobj;
4575 } else {
4576 syncobj_dst = &sem->syncobj;
4577 }
4578
4579 switch(pImportSemaphoreFdInfo->handleType) {
4580 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4581 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4582 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4583 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4584 default:
4585 unreachable("Unhandled semaphore handle type");
4586 }
4587 }
4588
4589 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4590 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4591 int *pFd)
4592 {
4593 RADV_FROM_HANDLE(radv_device, device, _device);
4594 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4595 int ret;
4596 uint32_t syncobj_handle;
4597
4598 if (sem->temp_syncobj)
4599 syncobj_handle = sem->temp_syncobj;
4600 else
4601 syncobj_handle = sem->syncobj;
4602
4603 switch(pGetFdInfo->handleType) {
4604 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4605 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4606 break;
4607 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4608 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4609 if (!ret) {
4610 if (sem->temp_syncobj) {
4611 close (sem->temp_syncobj);
4612 sem->temp_syncobj = 0;
4613 } else {
4614 device->ws->reset_syncobj(device->ws, syncobj_handle);
4615 }
4616 }
4617 break;
4618 default:
4619 unreachable("Unhandled semaphore handle type");
4620 }
4621
4622 if (ret)
4623 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4624 return VK_SUCCESS;
4625 }
4626
4627 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4628 VkPhysicalDevice physicalDevice,
4629 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4630 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4631 {
4632 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4633
4634 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4635 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4636 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4637 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4638 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4639 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4640 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4641 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4642 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4643 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4644 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4645 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4646 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4647 } else {
4648 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4649 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4650 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4651 }
4652 }
4653
4654 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4655 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4656 {
4657 RADV_FROM_HANDLE(radv_device, device, _device);
4658 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4659 uint32_t *syncobj_dst = NULL;
4660
4661
4662 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4663 syncobj_dst = &fence->temp_syncobj;
4664 } else {
4665 syncobj_dst = &fence->syncobj;
4666 }
4667
4668 switch(pImportFenceFdInfo->handleType) {
4669 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4670 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4671 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4672 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4673 default:
4674 unreachable("Unhandled fence handle type");
4675 }
4676 }
4677
4678 VkResult radv_GetFenceFdKHR(VkDevice _device,
4679 const VkFenceGetFdInfoKHR *pGetFdInfo,
4680 int *pFd)
4681 {
4682 RADV_FROM_HANDLE(radv_device, device, _device);
4683 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4684 int ret;
4685 uint32_t syncobj_handle;
4686
4687 if (fence->temp_syncobj)
4688 syncobj_handle = fence->temp_syncobj;
4689 else
4690 syncobj_handle = fence->syncobj;
4691
4692 switch(pGetFdInfo->handleType) {
4693 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4694 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4695 break;
4696 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4697 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4698 if (!ret) {
4699 if (fence->temp_syncobj) {
4700 close (fence->temp_syncobj);
4701 fence->temp_syncobj = 0;
4702 } else {
4703 device->ws->reset_syncobj(device->ws, syncobj_handle);
4704 }
4705 }
4706 break;
4707 default:
4708 unreachable("Unhandled fence handle type");
4709 }
4710
4711 if (ret)
4712 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4713 return VK_SUCCESS;
4714 }
4715
4716 void radv_GetPhysicalDeviceExternalFenceProperties(
4717 VkPhysicalDevice physicalDevice,
4718 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4719 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4720 {
4721 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4722
4723 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4724 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4725 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4726 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4727 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4728 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4729 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4730 } else {
4731 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4732 pExternalFenceProperties->compatibleHandleTypes = 0;
4733 pExternalFenceProperties->externalFenceFeatures = 0;
4734 }
4735 }
4736
4737 VkResult
4738 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4739 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4740 const VkAllocationCallbacks* pAllocator,
4741 VkDebugReportCallbackEXT* pCallback)
4742 {
4743 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4744 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4745 pCreateInfo, pAllocator, &instance->alloc,
4746 pCallback);
4747 }
4748
4749 void
4750 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4751 VkDebugReportCallbackEXT _callback,
4752 const VkAllocationCallbacks* pAllocator)
4753 {
4754 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4755 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4756 _callback, pAllocator, &instance->alloc);
4757 }
4758
4759 void
4760 radv_DebugReportMessageEXT(VkInstance _instance,
4761 VkDebugReportFlagsEXT flags,
4762 VkDebugReportObjectTypeEXT objectType,
4763 uint64_t object,
4764 size_t location,
4765 int32_t messageCode,
4766 const char* pLayerPrefix,
4767 const char* pMessage)
4768 {
4769 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4770 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4771 object, location, messageCode, pLayerPrefix, pMessage);
4772 }
4773
4774 void
4775 radv_GetDeviceGroupPeerMemoryFeatures(
4776 VkDevice device,
4777 uint32_t heapIndex,
4778 uint32_t localDeviceIndex,
4779 uint32_t remoteDeviceIndex,
4780 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4781 {
4782 assert(localDeviceIndex == remoteDeviceIndex);
4783
4784 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4785 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4786 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4787 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4788 }