2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
53 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
56 unsigned char sha1
[20];
57 unsigned ptr_size
= sizeof(void*);
59 memset(uuid
, 0, VK_UUID_SIZE
);
60 _mesa_sha1_init(&ctx
);
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
66 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
67 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
68 _mesa_sha1_final(&ctx
, sha1
);
70 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
75 radv_get_driver_uuid(void *uuid
)
77 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
81 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
83 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
87 radv_get_device_name(enum radeon_family family
, char *name
, size_t name_len
)
89 const char *chip_string
;
90 char llvm_string
[32] = {};
93 case CHIP_TAHITI
: chip_string
= "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN
: chip_string
= "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE
: chip_string
= "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND
: chip_string
= "AMD RADV OLAND"; break;
97 case CHIP_HAINAN
: chip_string
= "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE
: chip_string
= "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI
: chip_string
= "AMD RADV KAVERI"; break;
100 case CHIP_KABINI
: chip_string
= "AMD RADV KABINI"; break;
101 case CHIP_HAWAII
: chip_string
= "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS
: chip_string
= "AMD RADV MULLINS"; break;
103 case CHIP_TONGA
: chip_string
= "AMD RADV TONGA"; break;
104 case CHIP_ICELAND
: chip_string
= "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO
: chip_string
= "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI
: chip_string
= "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10
: chip_string
= "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11
: chip_string
= "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12
: chip_string
= "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY
: chip_string
= "AMD RADV STONEY"; break;
111 case CHIP_VEGAM
: chip_string
= "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10
: chip_string
= "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12
: chip_string
= "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN
: chip_string
= "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2
: chip_string
= "AMD RADV RAVEN2"; break;
116 default: chip_string
= "AMD RADV unknown"; break;
119 snprintf(llvm_string
, sizeof(llvm_string
),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM
>> 8) & 0xff,
121 HAVE_LLVM
& 0xff, MESA_LLVM_VERSION_PATCH
);
122 snprintf(name
, name_len
, "%s%s", chip_string
, llvm_string
);
126 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
128 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
129 uint64_t visible_vram_size
= MIN2(device
->rad_info
.vram_size
,
130 device
->rad_info
.vram_vis_size
);
132 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
133 device
->memory_properties
.memoryHeapCount
= 0;
134 if (device
->rad_info
.vram_size
- visible_vram_size
> 0) {
135 vram_index
= device
->memory_properties
.memoryHeapCount
++;
136 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
137 .size
= device
->rad_info
.vram_size
- visible_vram_size
,
138 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
141 if (visible_vram_size
) {
142 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
143 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
144 .size
= visible_vram_size
,
145 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
148 if (device
->rad_info
.gart_size
> 0) {
149 gart_index
= device
->memory_properties
.memoryHeapCount
++;
150 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
151 .size
= device
->rad_info
.gart_size
,
152 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
156 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
157 unsigned type_count
= 0;
158 if (vram_index
>= 0) {
159 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
160 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
161 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
162 .heapIndex
= vram_index
,
165 if (gart_index
>= 0) {
166 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
167 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
168 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
169 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
170 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
171 .heapIndex
= gart_index
,
174 if (visible_vram_index
>= 0) {
175 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
176 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
177 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
178 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
180 .heapIndex
= visible_vram_index
,
183 if (gart_index
>= 0) {
184 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
185 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
186 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
188 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
189 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
190 .heapIndex
= gart_index
,
193 device
->memory_properties
.memoryTypeCount
= type_count
;
197 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
199 const char *family
= getenv("RADV_FORCE_FAMILY");
205 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
206 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
207 /* Override family and chip_class. */
208 device
->rad_info
.family
= i
;
210 if (i
>= CHIP_VEGA10
)
211 device
->rad_info
.chip_class
= GFX9
;
212 else if (i
>= CHIP_TONGA
)
213 device
->rad_info
.chip_class
= VI
;
214 else if (i
>= CHIP_BONAIRE
)
215 device
->rad_info
.chip_class
= CIK
;
217 device
->rad_info
.chip_class
= SI
;
223 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
228 radv_physical_device_init(struct radv_physical_device
*device
,
229 struct radv_instance
*instance
,
230 drmDevicePtr drm_device
)
232 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
234 drmVersionPtr version
;
238 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
240 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
241 radv_logi("Could not open device '%s'", path
);
243 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
246 version
= drmGetVersion(fd
);
250 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
251 radv_logi("Could not get the kernel driver version for device '%s'", path
);
253 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
254 "failed to get version %s: %m", path
);
257 if (strcmp(version
->name
, "amdgpu")) {
258 drmFreeVersion(version
);
261 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
262 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
264 return VK_ERROR_INCOMPATIBLE_DRIVER
;
266 drmFreeVersion(version
);
268 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
269 radv_logi("Found compatible device '%s'.", path
);
271 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
272 device
->instance
= instance
;
273 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
274 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
276 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
277 instance
->perftest_flags
);
279 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
283 if (instance
->enabled_extensions
.KHR_display
) {
284 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
285 if (master_fd
>= 0) {
286 uint32_t accel_working
= 0;
287 struct drm_amdgpu_info request
= {
288 .return_pointer
= (uintptr_t)&accel_working
,
289 .return_size
= sizeof(accel_working
),
290 .query
= AMDGPU_INFO_ACCEL_WORKING
293 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
300 device
->master_fd
= master_fd
;
301 device
->local_fd
= fd
;
302 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
304 radv_handle_env_var_force_family(device
);
306 radv_get_device_name(device
->rad_info
.family
, device
->name
, sizeof(device
->name
));
308 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
309 device
->ws
->destroy(device
->ws
);
310 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
311 "cannot generate UUID");
315 /* These flags affect shader compilation. */
316 uint64_t shader_env_flags
=
317 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
318 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
320 /* The gpu id is already embedded in the uuid so we just pass "radv"
321 * when creating the cache.
323 char buf
[VK_UUID_SIZE
* 2 + 1];
324 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
325 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
327 if (device
->rad_info
.chip_class
< VI
||
328 device
->rad_info
.chip_class
> GFX9
)
329 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
331 radv_get_driver_uuid(&device
->device_uuid
);
332 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
334 if (device
->rad_info
.family
== CHIP_STONEY
||
335 device
->rad_info
.chip_class
>= GFX9
) {
336 device
->has_rbplus
= true;
337 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
||
338 device
->rad_info
.family
== CHIP_VEGA12
||
339 device
->rad_info
.family
== CHIP_RAVEN
||
340 device
->rad_info
.family
== CHIP_RAVEN2
;
343 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
346 device
->has_clear_state
= device
->rad_info
.chip_class
>= CIK
;
348 device
->cpdma_prefetch_writes_memory
= device
->rad_info
.chip_class
<= VI
;
350 /* Vega10/Raven need a special workaround for a hardware bug. */
351 device
->has_scissor_bug
= device
->rad_info
.family
== CHIP_VEGA10
||
352 device
->rad_info
.family
== CHIP_RAVEN
;
354 /* Out-of-order primitive rasterization. */
355 device
->has_out_of_order_rast
= device
->rad_info
.chip_class
>= VI
&&
356 device
->rad_info
.max_se
>= 2;
357 device
->out_of_order_rast_allowed
= device
->has_out_of_order_rast
&&
358 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
360 device
->dcc_msaa_allowed
=
361 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
363 radv_physical_device_init_mem_types(device
);
364 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
366 device
->bus_info
= *drm_device
->businfo
.pci
;
368 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
369 ac_print_gpu_info(&device
->rad_info
);
371 /* The WSI is structured as a layer on top of the driver, so this has
372 * to be the last part of initialization (at least until we get other
375 result
= radv_init_wsi(device
);
376 if (result
!= VK_SUCCESS
) {
377 device
->ws
->destroy(device
->ws
);
378 vk_error(instance
, result
);
392 radv_physical_device_finish(struct radv_physical_device
*device
)
394 radv_finish_wsi(device
);
395 device
->ws
->destroy(device
->ws
);
396 disk_cache_destroy(device
->disk_cache
);
397 close(device
->local_fd
);
398 if (device
->master_fd
!= -1)
399 close(device
->master_fd
);
403 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
404 VkSystemAllocationScope allocationScope
)
410 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
411 size_t align
, VkSystemAllocationScope allocationScope
)
413 return realloc(pOriginal
, size
);
417 default_free_func(void *pUserData
, void *pMemory
)
422 static const VkAllocationCallbacks default_alloc
= {
424 .pfnAllocation
= default_alloc_func
,
425 .pfnReallocation
= default_realloc_func
,
426 .pfnFree
= default_free_func
,
429 static const struct debug_control radv_debug_options
[] = {
430 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
431 {"nodcc", RADV_DEBUG_NO_DCC
},
432 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
433 {"nocache", RADV_DEBUG_NO_CACHE
},
434 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
435 {"nohiz", RADV_DEBUG_NO_HIZ
},
436 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
437 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
438 {"allbos", RADV_DEBUG_ALL_BOS
},
439 {"noibs", RADV_DEBUG_NO_IBS
},
440 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
441 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
442 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
443 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
444 {"nosisched", RADV_DEBUG_NO_SISCHED
},
445 {"preoptir", RADV_DEBUG_PREOPTIR
},
446 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
447 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
448 {"info", RADV_DEBUG_INFO
},
449 {"errors", RADV_DEBUG_ERRORS
},
450 {"startup", RADV_DEBUG_STARTUP
},
451 {"checkir", RADV_DEBUG_CHECKIR
},
452 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
453 {"nobinning", RADV_DEBUG_NOBINNING
},
458 radv_get_debug_option_name(int id
)
460 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
461 return radv_debug_options
[id
].string
;
464 static const struct debug_control radv_perftest_options
[] = {
465 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
466 {"sisched", RADV_PERFTEST_SISCHED
},
467 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
468 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
473 radv_get_perftest_option_name(int id
)
475 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
476 return radv_perftest_options
[id
].string
;
480 radv_handle_per_app_options(struct radv_instance
*instance
,
481 const VkApplicationInfo
*info
)
483 const char *name
= info
? info
->pApplicationName
: NULL
;
488 if (!strcmp(name
, "Talos - Linux - 32bit") ||
489 !strcmp(name
, "Talos - Linux - 64bit")) {
490 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
491 /* Force enable LLVM sisched for Talos because it looks
492 * safe and it gives few more FPS.
494 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
496 } else if (!strcmp(name
, "DOOM_VFR")) {
497 /* Work around a Doom VFR game bug */
498 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
502 static int radv_get_instance_extension_index(const char *name
)
504 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
505 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
512 VkResult
radv_CreateInstance(
513 const VkInstanceCreateInfo
* pCreateInfo
,
514 const VkAllocationCallbacks
* pAllocator
,
515 VkInstance
* pInstance
)
517 struct radv_instance
*instance
;
520 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
522 uint32_t client_version
;
523 if (pCreateInfo
->pApplicationInfo
&&
524 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
525 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
527 radv_EnumerateInstanceVersion(&client_version
);
530 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
531 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
533 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
535 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
538 instance
->alloc
= *pAllocator
;
540 instance
->alloc
= default_alloc
;
542 instance
->apiVersion
= client_version
;
543 instance
->physicalDeviceCount
= -1;
545 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
548 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
549 radv_perftest_options
);
552 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
553 radv_logi("Created an instance");
555 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
556 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
557 int index
= radv_get_instance_extension_index(ext_name
);
559 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
560 vk_free2(&default_alloc
, pAllocator
, instance
);
561 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
564 instance
->enabled_extensions
.extensions
[index
] = true;
567 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
568 if (result
!= VK_SUCCESS
) {
569 vk_free2(&default_alloc
, pAllocator
, instance
);
570 return vk_error(instance
, result
);
575 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
577 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
579 *pInstance
= radv_instance_to_handle(instance
);
584 void radv_DestroyInstance(
585 VkInstance _instance
,
586 const VkAllocationCallbacks
* pAllocator
)
588 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
593 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
594 radv_physical_device_finish(instance
->physicalDevices
+ i
);
597 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
601 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
603 vk_free(&instance
->alloc
, instance
);
607 radv_enumerate_devices(struct radv_instance
*instance
)
609 /* TODO: Check for more devices ? */
610 drmDevicePtr devices
[8];
611 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
614 instance
->physicalDeviceCount
= 0;
616 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
618 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
619 radv_logi("Found %d drm nodes", max_devices
);
622 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
624 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
625 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
626 devices
[i
]->bustype
== DRM_BUS_PCI
&&
627 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
629 result
= radv_physical_device_init(instance
->physicalDevices
+
630 instance
->physicalDeviceCount
,
633 if (result
== VK_SUCCESS
)
634 ++instance
->physicalDeviceCount
;
635 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
639 drmFreeDevices(devices
, max_devices
);
644 VkResult
radv_EnumeratePhysicalDevices(
645 VkInstance _instance
,
646 uint32_t* pPhysicalDeviceCount
,
647 VkPhysicalDevice
* pPhysicalDevices
)
649 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
652 if (instance
->physicalDeviceCount
< 0) {
653 result
= radv_enumerate_devices(instance
);
654 if (result
!= VK_SUCCESS
&&
655 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
659 if (!pPhysicalDevices
) {
660 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
662 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
663 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
664 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
667 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
671 VkResult
radv_EnumeratePhysicalDeviceGroups(
672 VkInstance _instance
,
673 uint32_t* pPhysicalDeviceGroupCount
,
674 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
676 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
679 if (instance
->physicalDeviceCount
< 0) {
680 result
= radv_enumerate_devices(instance
);
681 if (result
!= VK_SUCCESS
&&
682 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
686 if (!pPhysicalDeviceGroupProperties
) {
687 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
689 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
690 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
691 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
692 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
693 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
696 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
700 void radv_GetPhysicalDeviceFeatures(
701 VkPhysicalDevice physicalDevice
,
702 VkPhysicalDeviceFeatures
* pFeatures
)
704 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
705 memset(pFeatures
, 0, sizeof(*pFeatures
));
707 *pFeatures
= (VkPhysicalDeviceFeatures
) {
708 .robustBufferAccess
= true,
709 .fullDrawIndexUint32
= true,
710 .imageCubeArray
= true,
711 .independentBlend
= true,
712 .geometryShader
= true,
713 .tessellationShader
= true,
714 .sampleRateShading
= true,
715 .dualSrcBlend
= true,
717 .multiDrawIndirect
= true,
718 .drawIndirectFirstInstance
= true,
720 .depthBiasClamp
= true,
721 .fillModeNonSolid
= true,
726 .multiViewport
= true,
727 .samplerAnisotropy
= true,
728 .textureCompressionETC2
= pdevice
->rad_info
.chip_class
>= GFX9
||
729 pdevice
->rad_info
.family
== CHIP_STONEY
,
730 .textureCompressionASTC_LDR
= false,
731 .textureCompressionBC
= true,
732 .occlusionQueryPrecise
= true,
733 .pipelineStatisticsQuery
= true,
734 .vertexPipelineStoresAndAtomics
= true,
735 .fragmentStoresAndAtomics
= true,
736 .shaderTessellationAndGeometryPointSize
= true,
737 .shaderImageGatherExtended
= true,
738 .shaderStorageImageExtendedFormats
= true,
739 .shaderStorageImageMultisample
= false,
740 .shaderUniformBufferArrayDynamicIndexing
= true,
741 .shaderSampledImageArrayDynamicIndexing
= true,
742 .shaderStorageBufferArrayDynamicIndexing
= true,
743 .shaderStorageImageArrayDynamicIndexing
= true,
744 .shaderStorageImageReadWithoutFormat
= true,
745 .shaderStorageImageWriteWithoutFormat
= true,
746 .shaderClipDistance
= true,
747 .shaderCullDistance
= true,
748 .shaderFloat64
= true,
750 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& HAVE_LLVM
>= 0x700,
751 .sparseBinding
= true,
752 .variableMultisampleRate
= true,
753 .inheritedQueries
= true,
757 void radv_GetPhysicalDeviceFeatures2(
758 VkPhysicalDevice physicalDevice
,
759 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
761 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
762 vk_foreach_struct(ext
, pFeatures
->pNext
) {
763 switch (ext
->sType
) {
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR
: {
765 VkPhysicalDeviceVariablePointerFeaturesKHR
*features
= (void *)ext
;
766 features
->variablePointersStorageBuffer
= true;
767 features
->variablePointers
= false;
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR
: {
771 VkPhysicalDeviceMultiviewFeaturesKHR
*features
= (VkPhysicalDeviceMultiviewFeaturesKHR
*)ext
;
772 features
->multiview
= true;
773 features
->multiviewGeometryShader
= true;
774 features
->multiviewTessellationShader
= true;
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES
: {
778 VkPhysicalDeviceShaderDrawParameterFeatures
*features
=
779 (VkPhysicalDeviceShaderDrawParameterFeatures
*)ext
;
780 features
->shaderDrawParameters
= true;
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
784 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
785 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
786 features
->protectedMemory
= false;
789 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
790 VkPhysicalDevice16BitStorageFeatures
*features
=
791 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
792 bool enabled
= HAVE_LLVM
>= 0x0700 && pdevice
->rad_info
.chip_class
>= VI
;
793 features
->storageBuffer16BitAccess
= enabled
;
794 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
795 features
->storagePushConstant16
= enabled
;
796 features
->storageInputOutput16
= enabled
;
799 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
800 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
801 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
802 features
->samplerYcbcrConversion
= false;
805 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
806 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
807 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
808 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
809 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
810 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
811 features
->shaderUniformBufferArrayNonUniformIndexing
= false;
812 features
->shaderSampledImageArrayNonUniformIndexing
= false;
813 features
->shaderStorageBufferArrayNonUniformIndexing
= false;
814 features
->shaderStorageImageArrayNonUniformIndexing
= false;
815 features
->shaderInputAttachmentArrayNonUniformIndexing
= false;
816 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= false;
817 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= false;
818 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
819 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
820 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
821 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
822 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
823 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
824 features
->descriptorBindingUpdateUnusedWhilePending
= true;
825 features
->descriptorBindingPartiallyBound
= true;
826 features
->descriptorBindingVariableDescriptorCount
= true;
827 features
->runtimeDescriptorArray
= true;
830 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
831 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
832 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
833 features
->conditionalRendering
= true;
834 features
->inheritedConditionalRendering
= false;
837 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
838 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
839 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
840 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
841 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
845 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
846 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
847 features
->transformFeedback
= true;
848 features
->geometryStreams
= true;
855 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
858 void radv_GetPhysicalDeviceProperties(
859 VkPhysicalDevice physicalDevice
,
860 VkPhysicalDeviceProperties
* pProperties
)
862 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
863 VkSampleCountFlags sample_counts
= 0xf;
865 /* make sure that the entire descriptor set is addressable with a signed
866 * 32-bit int. So the sum of all limits scaled by descriptor size has to
867 * be at most 2 GiB. the combined image & samples object count as one of
868 * both. This limit is for the pipeline layout, not for the set layout, but
869 * there is no set limit, so we just set a pipeline limit. I don't think
870 * any app is going to hit this soon. */
871 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
872 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
873 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
874 32 /* sampler, largest when combined with image */ +
875 64 /* sampled image */ +
876 64 /* storage image */);
878 VkPhysicalDeviceLimits limits
= {
879 .maxImageDimension1D
= (1 << 14),
880 .maxImageDimension2D
= (1 << 14),
881 .maxImageDimension3D
= (1 << 11),
882 .maxImageDimensionCube
= (1 << 14),
883 .maxImageArrayLayers
= (1 << 11),
884 .maxTexelBufferElements
= 128 * 1024 * 1024,
885 .maxUniformBufferRange
= UINT32_MAX
,
886 .maxStorageBufferRange
= UINT32_MAX
,
887 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
888 .maxMemoryAllocationCount
= UINT32_MAX
,
889 .maxSamplerAllocationCount
= 64 * 1024,
890 .bufferImageGranularity
= 64, /* A cache line */
891 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
892 .maxBoundDescriptorSets
= MAX_SETS
,
893 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
894 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
895 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
896 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
897 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
898 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
899 .maxPerStageResources
= max_descriptor_set_size
,
900 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
901 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
902 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
903 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
904 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
905 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
906 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
907 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
908 .maxVertexInputAttributes
= 32,
909 .maxVertexInputBindings
= 32,
910 .maxVertexInputAttributeOffset
= 2047,
911 .maxVertexInputBindingStride
= 2048,
912 .maxVertexOutputComponents
= 128,
913 .maxTessellationGenerationLevel
= 64,
914 .maxTessellationPatchSize
= 32,
915 .maxTessellationControlPerVertexInputComponents
= 128,
916 .maxTessellationControlPerVertexOutputComponents
= 128,
917 .maxTessellationControlPerPatchOutputComponents
= 120,
918 .maxTessellationControlTotalOutputComponents
= 4096,
919 .maxTessellationEvaluationInputComponents
= 128,
920 .maxTessellationEvaluationOutputComponents
= 128,
921 .maxGeometryShaderInvocations
= 127,
922 .maxGeometryInputComponents
= 64,
923 .maxGeometryOutputComponents
= 128,
924 .maxGeometryOutputVertices
= 256,
925 .maxGeometryTotalOutputComponents
= 1024,
926 .maxFragmentInputComponents
= 128,
927 .maxFragmentOutputAttachments
= 8,
928 .maxFragmentDualSrcAttachments
= 1,
929 .maxFragmentCombinedOutputResources
= 8,
930 .maxComputeSharedMemorySize
= 32768,
931 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
932 .maxComputeWorkGroupInvocations
= 2048,
933 .maxComputeWorkGroupSize
= {
938 .subPixelPrecisionBits
= 4 /* FIXME */,
939 .subTexelPrecisionBits
= 4 /* FIXME */,
940 .mipmapPrecisionBits
= 4 /* FIXME */,
941 .maxDrawIndexedIndexValue
= UINT32_MAX
,
942 .maxDrawIndirectCount
= UINT32_MAX
,
943 .maxSamplerLodBias
= 16,
944 .maxSamplerAnisotropy
= 16,
945 .maxViewports
= MAX_VIEWPORTS
,
946 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
947 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
948 .viewportSubPixelBits
= 8,
949 .minMemoryMapAlignment
= 4096, /* A page */
950 .minTexelBufferOffsetAlignment
= 1,
951 .minUniformBufferOffsetAlignment
= 4,
952 .minStorageBufferOffsetAlignment
= 4,
953 .minTexelOffset
= -32,
954 .maxTexelOffset
= 31,
955 .minTexelGatherOffset
= -32,
956 .maxTexelGatherOffset
= 31,
957 .minInterpolationOffset
= -2,
958 .maxInterpolationOffset
= 2,
959 .subPixelInterpolationOffsetBits
= 8,
960 .maxFramebufferWidth
= (1 << 14),
961 .maxFramebufferHeight
= (1 << 14),
962 .maxFramebufferLayers
= (1 << 10),
963 .framebufferColorSampleCounts
= sample_counts
,
964 .framebufferDepthSampleCounts
= sample_counts
,
965 .framebufferStencilSampleCounts
= sample_counts
,
966 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
967 .maxColorAttachments
= MAX_RTS
,
968 .sampledImageColorSampleCounts
= sample_counts
,
969 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
970 .sampledImageDepthSampleCounts
= sample_counts
,
971 .sampledImageStencilSampleCounts
= sample_counts
,
972 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
973 .maxSampleMaskWords
= 1,
974 .timestampComputeAndGraphics
= true,
975 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
976 .maxClipDistances
= 8,
977 .maxCullDistances
= 8,
978 .maxCombinedClipAndCullDistances
= 8,
979 .discreteQueuePriorities
= 2,
980 .pointSizeRange
= { 0.125, 255.875 },
981 .lineWidthRange
= { 0.0, 7.9921875 },
982 .pointSizeGranularity
= (1.0 / 8.0),
983 .lineWidthGranularity
= (1.0 / 128.0),
984 .strictLines
= false, /* FINISHME */
985 .standardSampleLocations
= true,
986 .optimalBufferCopyOffsetAlignment
= 128,
987 .optimalBufferCopyRowPitchAlignment
= 128,
988 .nonCoherentAtomSize
= 64,
991 *pProperties
= (VkPhysicalDeviceProperties
) {
992 .apiVersion
= radv_physical_device_api_version(pdevice
),
993 .driverVersion
= vk_get_driver_version(),
994 .vendorID
= ATI_VENDOR_ID
,
995 .deviceID
= pdevice
->rad_info
.pci_id
,
996 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
998 .sparseProperties
= {0},
1001 strcpy(pProperties
->deviceName
, pdevice
->name
);
1002 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1005 void radv_GetPhysicalDeviceProperties2(
1006 VkPhysicalDevice physicalDevice
,
1007 VkPhysicalDeviceProperties2KHR
*pProperties
)
1009 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1010 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1012 vk_foreach_struct(ext
, pProperties
->pNext
) {
1013 switch (ext
->sType
) {
1014 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1015 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1016 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1017 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR
: {
1021 VkPhysicalDeviceIDPropertiesKHR
*properties
= (VkPhysicalDeviceIDPropertiesKHR
*)ext
;
1022 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1023 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1024 properties
->deviceLUIDValid
= false;
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR
: {
1028 VkPhysicalDeviceMultiviewPropertiesKHR
*properties
= (VkPhysicalDeviceMultiviewPropertiesKHR
*)ext
;
1029 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1030 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1033 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR
: {
1034 VkPhysicalDevicePointClippingPropertiesKHR
*properties
=
1035 (VkPhysicalDevicePointClippingPropertiesKHR
*)ext
;
1036 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR
;
1039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1040 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1041 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1042 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1046 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1047 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1048 properties
->minImportedHostPointerAlignment
= 4096;
1051 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1052 VkPhysicalDeviceSubgroupProperties
*properties
=
1053 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1054 properties
->subgroupSize
= 64;
1055 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1056 properties
->supportedOperations
=
1057 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1058 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1059 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1060 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1061 if (pdevice
->rad_info
.chip_class
>= VI
) {
1062 properties
->supportedOperations
|=
1063 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1064 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1065 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1067 properties
->quadOperationsInAllStages
= true;
1070 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1071 VkPhysicalDeviceMaintenance3Properties
*properties
=
1072 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1073 /* Make sure everything is addressable by a signed 32-bit int, and
1074 * our largest descriptors are 96 bytes. */
1075 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1076 /* Our buffer size fields allow only this much */
1077 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1080 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1081 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1082 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1083 /* GFX6-8 only support single channel min/max filter. */
1084 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1085 properties
->filterMinmaxSingleComponentFormats
= true;
1088 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1089 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1090 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1092 /* Shader engines. */
1093 properties
->shaderEngineCount
=
1094 pdevice
->rad_info
.max_se
;
1095 properties
->shaderArraysPerEngineCount
=
1096 pdevice
->rad_info
.max_sh_per_se
;
1097 properties
->computeUnitsPerShaderArray
=
1098 pdevice
->rad_info
.num_good_cu_per_sh
;
1099 properties
->simdPerComputeUnit
= 4;
1100 properties
->wavefrontsPerSimd
=
1101 pdevice
->rad_info
.family
== CHIP_TONGA
||
1102 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1103 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1104 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1105 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1106 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1107 properties
->wavefrontSize
= 64;
1110 properties
->sgprsPerSimd
=
1111 radv_get_num_physical_sgprs(pdevice
);
1112 properties
->minSgprAllocation
=
1113 pdevice
->rad_info
.chip_class
>= VI
? 16 : 8;
1114 properties
->maxSgprAllocation
=
1115 pdevice
->rad_info
.family
== CHIP_TONGA
||
1116 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1117 properties
->sgprAllocationGranularity
=
1118 pdevice
->rad_info
.chip_class
>= VI
? 16 : 8;
1121 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1122 properties
->minVgprAllocation
= 4;
1123 properties
->maxVgprAllocation
= 256;
1124 properties
->vgprAllocationGranularity
= 4;
1127 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1128 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1129 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1130 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1133 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1134 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1135 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1136 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1137 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1138 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1139 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1140 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1141 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1142 properties
->robustBufferAccessUpdateAfterBind
= false;
1143 properties
->quadDivergentImplicitLod
= false;
1145 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1146 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1147 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1148 32 /* sampler, largest when combined with image */ +
1149 64 /* sampled image */ +
1150 64 /* storage image */);
1151 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1152 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1153 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1154 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1155 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1156 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1157 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1158 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1159 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1160 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1161 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1162 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1163 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1164 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1165 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1168 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1169 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1170 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1171 properties
->protectedNoFault
= false;
1174 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1175 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1176 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1177 properties
->primitiveOverestimationSize
= 0;
1178 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1179 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1180 properties
->primitiveUnderestimation
= VK_FALSE
;
1181 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1182 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1183 properties
->degenerateLinesRasterized
= VK_FALSE
;
1184 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1185 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1188 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1189 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1190 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1191 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1192 properties
->pciBus
= pdevice
->bus_info
.bus
;
1193 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1194 properties
->pciFunction
= pdevice
->bus_info
.func
;
1197 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1198 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1199 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1201 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1202 memset(driver_props
->driverName
, 0, VK_MAX_DRIVER_NAME_SIZE_KHR
);
1203 strcpy(driver_props
->driverName
, "radv");
1205 memset(driver_props
->driverInfo
, 0, VK_MAX_DRIVER_INFO_SIZE_KHR
);
1206 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1207 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1209 (HAVE_LLVM
>> 8) & 0xff, HAVE_LLVM
& 0xff,
1210 MESA_LLVM_VERSION_PATCH
);
1212 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1221 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1222 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1223 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1224 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1225 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1226 properties
->maxTransformFeedbackStreamDataSize
= 512;
1227 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1228 properties
->maxTransformFeedbackBufferDataStride
= 512;
1229 properties
->transformFeedbackQueries
= true;
1230 properties
->transformFeedbackStreamsLinesTriangles
= false;
1231 properties
->transformFeedbackRasterizationStreamSelect
= false;
1232 properties
->transformFeedbackDraw
= true;
1241 static void radv_get_physical_device_queue_family_properties(
1242 struct radv_physical_device
* pdevice
,
1244 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1246 int num_queue_families
= 1;
1248 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1249 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1250 num_queue_families
++;
1252 if (pQueueFamilyProperties
== NULL
) {
1253 *pCount
= num_queue_families
;
1262 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1263 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1264 VK_QUEUE_COMPUTE_BIT
|
1265 VK_QUEUE_TRANSFER_BIT
|
1266 VK_QUEUE_SPARSE_BINDING_BIT
,
1268 .timestampValidBits
= 64,
1269 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1274 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1275 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1276 if (*pCount
> idx
) {
1277 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1278 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1279 VK_QUEUE_TRANSFER_BIT
|
1280 VK_QUEUE_SPARSE_BINDING_BIT
,
1281 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1282 .timestampValidBits
= 64,
1283 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1291 void radv_GetPhysicalDeviceQueueFamilyProperties(
1292 VkPhysicalDevice physicalDevice
,
1294 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1296 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1297 if (!pQueueFamilyProperties
) {
1298 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1301 VkQueueFamilyProperties
*properties
[] = {
1302 pQueueFamilyProperties
+ 0,
1303 pQueueFamilyProperties
+ 1,
1304 pQueueFamilyProperties
+ 2,
1306 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1307 assert(*pCount
<= 3);
1310 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1311 VkPhysicalDevice physicalDevice
,
1313 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
1315 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1316 if (!pQueueFamilyProperties
) {
1317 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1320 VkQueueFamilyProperties
*properties
[] = {
1321 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1322 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1323 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1325 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1326 assert(*pCount
<= 3);
1329 void radv_GetPhysicalDeviceMemoryProperties(
1330 VkPhysicalDevice physicalDevice
,
1331 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1333 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1335 *pMemoryProperties
= physical_device
->memory_properties
;
1338 void radv_GetPhysicalDeviceMemoryProperties2(
1339 VkPhysicalDevice physicalDevice
,
1340 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
1342 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1343 &pMemoryProperties
->memoryProperties
);
1346 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1348 VkExternalMemoryHandleTypeFlagBitsKHR handleType
,
1349 const void *pHostPointer
,
1350 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1352 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1356 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1357 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1358 uint32_t memoryTypeBits
= 0;
1359 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1360 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1361 memoryTypeBits
= (1 << i
);
1365 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1369 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
1373 static enum radeon_ctx_priority
1374 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1376 /* Default to MEDIUM when a specific global priority isn't requested */
1378 return RADEON_CTX_PRIORITY_MEDIUM
;
1380 switch(pObj
->globalPriority
) {
1381 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1382 return RADEON_CTX_PRIORITY_REALTIME
;
1383 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1384 return RADEON_CTX_PRIORITY_HIGH
;
1385 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1386 return RADEON_CTX_PRIORITY_MEDIUM
;
1387 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1388 return RADEON_CTX_PRIORITY_LOW
;
1390 unreachable("Illegal global priority value");
1391 return RADEON_CTX_PRIORITY_INVALID
;
1396 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1397 uint32_t queue_family_index
, int idx
,
1398 VkDeviceQueueCreateFlags flags
,
1399 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1401 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1402 queue
->device
= device
;
1403 queue
->queue_family_index
= queue_family_index
;
1404 queue
->queue_idx
= idx
;
1405 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1406 queue
->flags
= flags
;
1408 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1410 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1416 radv_queue_finish(struct radv_queue
*queue
)
1419 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1421 if (queue
->initial_full_flush_preamble_cs
)
1422 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1423 if (queue
->initial_preamble_cs
)
1424 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1425 if (queue
->continue_preamble_cs
)
1426 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1427 if (queue
->descriptor_bo
)
1428 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1429 if (queue
->scratch_bo
)
1430 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1431 if (queue
->esgs_ring_bo
)
1432 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1433 if (queue
->gsvs_ring_bo
)
1434 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1435 if (queue
->tess_rings_bo
)
1436 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1437 if (queue
->compute_scratch_bo
)
1438 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1442 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1444 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1445 bo_list
->list
.count
= bo_list
->capacity
= 0;
1446 bo_list
->list
.bos
= NULL
;
1450 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1452 free(bo_list
->list
.bos
);
1453 pthread_mutex_destroy(&bo_list
->mutex
);
1456 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1457 struct radeon_winsys_bo
*bo
)
1459 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1461 if (unlikely(!device
->use_global_bo_list
))
1464 pthread_mutex_lock(&bo_list
->mutex
);
1465 if (bo_list
->list
.count
== bo_list
->capacity
) {
1466 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1467 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1470 pthread_mutex_unlock(&bo_list
->mutex
);
1471 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1474 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1475 bo_list
->capacity
= capacity
;
1478 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1479 pthread_mutex_unlock(&bo_list
->mutex
);
1483 static void radv_bo_list_remove(struct radv_device
*device
,
1484 struct radeon_winsys_bo
*bo
)
1486 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1488 if (unlikely(!device
->use_global_bo_list
))
1491 pthread_mutex_lock(&bo_list
->mutex
);
1492 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1493 if (bo_list
->list
.bos
[i
] == bo
) {
1494 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1495 --bo_list
->list
.count
;
1499 pthread_mutex_unlock(&bo_list
->mutex
);
1503 radv_device_init_gs_info(struct radv_device
*device
)
1505 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1506 device
->physical_device
->rad_info
.family
);
1509 static int radv_get_device_extension_index(const char *name
)
1511 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1512 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1519 radv_get_int_debug_option(const char *name
, int default_value
)
1526 result
= default_value
;
1530 result
= strtol(str
, &endptr
, 0);
1531 if (str
== endptr
) {
1532 /* No digits founs. */
1533 result
= default_value
;
1540 VkResult
radv_CreateDevice(
1541 VkPhysicalDevice physicalDevice
,
1542 const VkDeviceCreateInfo
* pCreateInfo
,
1543 const VkAllocationCallbacks
* pAllocator
,
1546 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1548 struct radv_device
*device
;
1550 bool keep_shader_info
= false;
1552 /* Check enabled features */
1553 if (pCreateInfo
->pEnabledFeatures
) {
1554 VkPhysicalDeviceFeatures supported_features
;
1555 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
1556 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
1557 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
1558 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
1559 for (uint32_t i
= 0; i
< num_features
; i
++) {
1560 if (enabled_feature
[i
] && !supported_feature
[i
])
1561 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
1565 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
1567 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1569 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1571 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1572 device
->instance
= physical_device
->instance
;
1573 device
->physical_device
= physical_device
;
1575 device
->ws
= physical_device
->ws
;
1577 device
->alloc
= *pAllocator
;
1579 device
->alloc
= physical_device
->instance
->alloc
;
1581 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
1582 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
1583 int index
= radv_get_device_extension_index(ext_name
);
1584 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
1585 vk_free(&device
->alloc
, device
);
1586 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
1589 device
->enabled_extensions
.extensions
[index
] = true;
1592 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
1594 /* With update after bind we can't attach bo's to the command buffer
1595 * from the descriptor set anymore, so we have to use a global BO list.
1597 device
->use_global_bo_list
=
1598 device
->enabled_extensions
.EXT_descriptor_indexing
;
1600 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
1601 list_inithead(&device
->shader_slabs
);
1603 radv_bo_list_init(&device
->bo_list
);
1605 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
1606 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
1607 uint32_t qfi
= queue_create
->queueFamilyIndex
;
1608 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
1609 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
1611 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1613 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1614 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1615 if (!device
->queues
[qfi
]) {
1616 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1620 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1622 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1624 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1625 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
1626 qfi
, q
, queue_create
->flags
,
1628 if (result
!= VK_SUCCESS
)
1633 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1634 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
1636 /* Disabled and not implemented for now. */
1637 device
->dfsm_allowed
= device
->pbb_allowed
&&
1638 (device
->physical_device
->rad_info
.family
== CHIP_RAVEN
||
1639 device
->physical_device
->rad_info
.family
== CHIP_RAVEN2
);
1642 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
1645 /* The maximum number of scratch waves. Scratch space isn't divided
1646 * evenly between CUs. The number is only a function of the number of CUs.
1647 * We can decrease the constant to decrease the scratch buffer size.
1649 * sctx->scratch_waves must be >= the maximum possible size of
1650 * 1 threadgroup, so that the hw doesn't hang from being unable
1653 * The recommended value is 4 per CU at most. Higher numbers don't
1654 * bring much benefit, but they still occupy chip resources (think
1655 * async compute). I've seen ~2% performance difference between 4 and 32.
1657 uint32_t max_threads_per_block
= 2048;
1658 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1659 max_threads_per_block
/ 64);
1661 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1);
1663 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1664 /* If the KMD allows it (there is a KMD hw register for it),
1665 * allow launching waves out-of-order.
1667 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
1670 radv_device_init_gs_info(device
);
1672 device
->tess_offchip_block_dw_size
=
1673 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1674 device
->has_distributed_tess
=
1675 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1676 device
->physical_device
->rad_info
.max_se
>= 2;
1678 if (getenv("RADV_TRACE_FILE")) {
1679 const char *filename
= getenv("RADV_TRACE_FILE");
1681 keep_shader_info
= true;
1683 if (!radv_init_trace(device
))
1686 fprintf(stderr
, "*****************************************************************************\n");
1687 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1688 fprintf(stderr
, "*****************************************************************************\n");
1690 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
1691 radv_dump_enabled_options(device
, stderr
);
1694 device
->keep_shader_info
= keep_shader_info
;
1696 result
= radv_device_init_meta(device
);
1697 if (result
!= VK_SUCCESS
)
1700 radv_device_init_msaa(device
);
1702 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1703 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1705 case RADV_QUEUE_GENERAL
:
1706 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1707 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1708 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1710 case RADV_QUEUE_COMPUTE
:
1711 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1712 radeon_emit(device
->empty_cs
[family
], 0);
1715 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1718 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1719 cik_create_gfx_config(device
);
1721 VkPipelineCacheCreateInfo ci
;
1722 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1725 ci
.pInitialData
= NULL
;
1726 ci
.initialDataSize
= 0;
1728 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1730 if (result
!= VK_SUCCESS
)
1733 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1735 device
->force_aniso
=
1736 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1737 if (device
->force_aniso
>= 0) {
1738 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
1739 1 << util_logbase2(device
->force_aniso
));
1742 *pDevice
= radv_device_to_handle(device
);
1746 radv_device_finish_meta(device
);
1748 radv_bo_list_finish(&device
->bo_list
);
1750 if (device
->trace_bo
)
1751 device
->ws
->buffer_destroy(device
->trace_bo
);
1753 if (device
->gfx_init
)
1754 device
->ws
->buffer_destroy(device
->gfx_init
);
1756 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1757 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1758 radv_queue_finish(&device
->queues
[i
][q
]);
1759 if (device
->queue_count
[i
])
1760 vk_free(&device
->alloc
, device
->queues
[i
]);
1763 vk_free(&device
->alloc
, device
);
1767 void radv_DestroyDevice(
1769 const VkAllocationCallbacks
* pAllocator
)
1771 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1776 if (device
->trace_bo
)
1777 device
->ws
->buffer_destroy(device
->trace_bo
);
1779 if (device
->gfx_init
)
1780 device
->ws
->buffer_destroy(device
->gfx_init
);
1782 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1783 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1784 radv_queue_finish(&device
->queues
[i
][q
]);
1785 if (device
->queue_count
[i
])
1786 vk_free(&device
->alloc
, device
->queues
[i
]);
1787 if (device
->empty_cs
[i
])
1788 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1790 radv_device_finish_meta(device
);
1792 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1793 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1795 radv_destroy_shader_slabs(device
);
1797 radv_bo_list_finish(&device
->bo_list
);
1798 vk_free(&device
->alloc
, device
);
1801 VkResult
radv_EnumerateInstanceLayerProperties(
1802 uint32_t* pPropertyCount
,
1803 VkLayerProperties
* pProperties
)
1805 if (pProperties
== NULL
) {
1806 *pPropertyCount
= 0;
1810 /* None supported at this time */
1811 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
1814 VkResult
radv_EnumerateDeviceLayerProperties(
1815 VkPhysicalDevice physicalDevice
,
1816 uint32_t* pPropertyCount
,
1817 VkLayerProperties
* pProperties
)
1819 if (pProperties
== NULL
) {
1820 *pPropertyCount
= 0;
1824 /* None supported at this time */
1825 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
1828 void radv_GetDeviceQueue2(
1830 const VkDeviceQueueInfo2
* pQueueInfo
,
1833 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1834 struct radv_queue
*queue
;
1836 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
1837 if (pQueueInfo
->flags
!= queue
->flags
) {
1838 /* From the Vulkan 1.1.70 spec:
1840 * "The queue returned by vkGetDeviceQueue2 must have the same
1841 * flags value from this structure as that used at device
1842 * creation time in a VkDeviceQueueCreateInfo instance. If no
1843 * matching flags were specified at device creation time then
1844 * pQueue will return VK_NULL_HANDLE."
1846 *pQueue
= VK_NULL_HANDLE
;
1850 *pQueue
= radv_queue_to_handle(queue
);
1853 void radv_GetDeviceQueue(
1855 uint32_t queueFamilyIndex
,
1856 uint32_t queueIndex
,
1859 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
1860 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
1861 .queueFamilyIndex
= queueFamilyIndex
,
1862 .queueIndex
= queueIndex
1865 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
1869 fill_geom_tess_rings(struct radv_queue
*queue
,
1871 bool add_sample_positions
,
1872 uint32_t esgs_ring_size
,
1873 struct radeon_winsys_bo
*esgs_ring_bo
,
1874 uint32_t gsvs_ring_size
,
1875 struct radeon_winsys_bo
*gsvs_ring_bo
,
1876 uint32_t tess_factor_ring_size
,
1877 uint32_t tess_offchip_ring_offset
,
1878 uint32_t tess_offchip_ring_size
,
1879 struct radeon_winsys_bo
*tess_rings_bo
)
1881 uint64_t esgs_va
= 0, gsvs_va
= 0;
1882 uint64_t tess_va
= 0, tess_offchip_va
= 0;
1883 uint32_t *desc
= &map
[4];
1886 esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
1888 gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
1889 if (tess_rings_bo
) {
1890 tess_va
= radv_buffer_get_va(tess_rings_bo
);
1891 tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
1894 /* stride 0, num records - size, add tid, swizzle, elsize4,
1897 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1898 S_008F04_STRIDE(0) |
1899 S_008F04_SWIZZLE_ENABLE(true);
1900 desc
[2] = esgs_ring_size
;
1901 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1902 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1903 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1904 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1905 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1906 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1907 S_008F0C_ELEMENT_SIZE(1) |
1908 S_008F0C_INDEX_STRIDE(3) |
1909 S_008F0C_ADD_TID_ENABLE(true);
1912 /* GS entry for ES->GS ring */
1913 /* stride 0, num records - size, elsize0,
1916 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1917 S_008F04_STRIDE(0) |
1918 S_008F04_SWIZZLE_ENABLE(false);
1919 desc
[2] = esgs_ring_size
;
1920 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1921 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1922 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1923 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1924 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1925 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1926 S_008F0C_ELEMENT_SIZE(0) |
1927 S_008F0C_INDEX_STRIDE(0) |
1928 S_008F0C_ADD_TID_ENABLE(false);
1931 /* VS entry for GS->VS ring */
1932 /* stride 0, num records - size, elsize0,
1935 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1936 S_008F04_STRIDE(0) |
1937 S_008F04_SWIZZLE_ENABLE(false);
1938 desc
[2] = gsvs_ring_size
;
1939 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1940 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1941 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1942 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1943 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1944 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1945 S_008F0C_ELEMENT_SIZE(0) |
1946 S_008F0C_INDEX_STRIDE(0) |
1947 S_008F0C_ADD_TID_ENABLE(false);
1950 /* stride gsvs_itemsize, num records 64
1951 elsize 4, index stride 16 */
1952 /* shader will patch stride and desc[2] */
1954 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1955 S_008F04_STRIDE(0) |
1956 S_008F04_SWIZZLE_ENABLE(true);
1958 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1959 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1960 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1961 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1962 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1963 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1964 S_008F0C_ELEMENT_SIZE(1) |
1965 S_008F0C_INDEX_STRIDE(1) |
1966 S_008F0C_ADD_TID_ENABLE(true);
1970 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32) |
1971 S_008F04_STRIDE(0) |
1972 S_008F04_SWIZZLE_ENABLE(false);
1973 desc
[2] = tess_factor_ring_size
;
1974 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1975 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1976 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1977 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1978 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1979 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1980 S_008F0C_ELEMENT_SIZE(0) |
1981 S_008F0C_INDEX_STRIDE(0) |
1982 S_008F0C_ADD_TID_ENABLE(false);
1985 desc
[0] = tess_offchip_va
;
1986 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1987 S_008F04_STRIDE(0) |
1988 S_008F04_SWIZZLE_ENABLE(false);
1989 desc
[2] = tess_offchip_ring_size
;
1990 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1991 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1992 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1993 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1994 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1995 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1996 S_008F0C_ELEMENT_SIZE(0) |
1997 S_008F0C_INDEX_STRIDE(0) |
1998 S_008F0C_ADD_TID_ENABLE(false);
2001 /* add sample positions after all rings */
2002 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2004 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2006 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2008 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2010 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
2014 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2016 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
2017 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2018 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2019 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2020 unsigned max_offchip_buffers
;
2021 unsigned offchip_granularity
;
2022 unsigned hs_offchip_param
;
2026 * This must be one less than the maximum number due to a hw limitation.
2027 * Various hardware bugs in SI, CIK, and GFX9 need this.
2030 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2031 * Gfx7 should limit max_offchip_buffers to 508
2032 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2034 * Follow AMDVLK here.
2036 if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2037 device
->physical_device
->rad_info
.chip_class
== CIK
||
2038 device
->physical_device
->rad_info
.chip_class
== SI
)
2039 --max_offchip_buffers_per_se
;
2041 max_offchip_buffers
= max_offchip_buffers_per_se
*
2042 device
->physical_device
->rad_info
.max_se
;
2044 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2045 * around by setting 4K granularity.
2047 if (device
->tess_offchip_block_dw_size
== 4096) {
2048 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2049 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2051 assert(device
->tess_offchip_block_dw_size
== 8192);
2052 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2055 switch (device
->physical_device
->rad_info
.chip_class
) {
2057 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2063 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2067 *max_offchip_buffers_p
= max_offchip_buffers
;
2068 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2069 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
2070 --max_offchip_buffers
;
2072 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2073 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2076 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2078 return hs_offchip_param
;
2082 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2083 struct radeon_winsys_bo
*esgs_ring_bo
,
2084 uint32_t esgs_ring_size
,
2085 struct radeon_winsys_bo
*gsvs_ring_bo
,
2086 uint32_t gsvs_ring_size
)
2088 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2092 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2095 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2097 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2098 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2099 radeon_emit(cs
, esgs_ring_size
>> 8);
2100 radeon_emit(cs
, gsvs_ring_size
>> 8);
2102 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2103 radeon_emit(cs
, esgs_ring_size
>> 8);
2104 radeon_emit(cs
, gsvs_ring_size
>> 8);
2109 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2110 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2111 struct radeon_winsys_bo
*tess_rings_bo
)
2118 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2120 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2122 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
2123 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2124 S_030938_SIZE(tf_ring_size
/ 4));
2125 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2127 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2128 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2129 S_030944_BASE_HI(tf_va
>> 40));
2131 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2134 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2135 S_008988_SIZE(tf_ring_size
/ 4));
2136 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2138 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2144 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2145 struct radeon_winsys_bo
*compute_scratch_bo
)
2147 uint64_t scratch_va
;
2149 if (!compute_scratch_bo
)
2152 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2154 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2156 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2157 radeon_emit(cs
, scratch_va
);
2158 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2159 S_008F04_SWIZZLE_ENABLE(1));
2163 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2164 struct radeon_cmdbuf
*cs
,
2165 struct radeon_winsys_bo
*descriptor_bo
)
2172 va
= radv_buffer_get_va(descriptor_bo
);
2174 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2176 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2177 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2178 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2179 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2180 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2182 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2183 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2187 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2188 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2189 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2190 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2191 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2192 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2194 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2195 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2202 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2204 struct radv_device
*device
= queue
->device
;
2206 if (device
->gfx_init
) {
2207 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
2209 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
2210 radeon_emit(cs
, va
);
2211 radeon_emit(cs
, va
>> 32);
2212 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
2214 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
2216 struct radv_physical_device
*physical_device
= device
->physical_device
;
2217 si_emit_graphics(physical_device
, cs
);
2222 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
2224 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
2225 si_emit_compute(physical_device
, cs
);
2229 radv_get_preamble_cs(struct radv_queue
*queue
,
2230 uint32_t scratch_size
,
2231 uint32_t compute_scratch_size
,
2232 uint32_t esgs_ring_size
,
2233 uint32_t gsvs_ring_size
,
2234 bool needs_tess_rings
,
2235 bool needs_sample_positions
,
2236 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
2237 struct radeon_cmdbuf
**initial_preamble_cs
,
2238 struct radeon_cmdbuf
**continue_preamble_cs
)
2240 struct radeon_winsys_bo
*scratch_bo
= NULL
;
2241 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
2242 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
2243 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
2244 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
2245 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
2246 struct radeon_cmdbuf
*dest_cs
[3] = {0};
2247 bool add_tess_rings
= false, add_sample_positions
= false;
2248 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
2249 unsigned max_offchip_buffers
;
2250 unsigned hs_offchip_param
= 0;
2251 unsigned tess_offchip_ring_offset
;
2252 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2253 if (!queue
->has_tess_rings
) {
2254 if (needs_tess_rings
)
2255 add_tess_rings
= true;
2257 if (!queue
->has_sample_positions
) {
2258 if (needs_sample_positions
)
2259 add_sample_positions
= true;
2261 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
2262 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
2263 &max_offchip_buffers
);
2264 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
2265 tess_offchip_ring_size
= max_offchip_buffers
*
2266 queue
->device
->tess_offchip_block_dw_size
* 4;
2268 if (scratch_size
<= queue
->scratch_size
&&
2269 compute_scratch_size
<= queue
->compute_scratch_size
&&
2270 esgs_ring_size
<= queue
->esgs_ring_size
&&
2271 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
2272 !add_tess_rings
&& !add_sample_positions
&&
2273 queue
->initial_preamble_cs
) {
2274 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2275 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2276 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2277 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2278 *continue_preamble_cs
= NULL
;
2282 if (scratch_size
> queue
->scratch_size
) {
2283 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2291 scratch_bo
= queue
->scratch_bo
;
2293 if (compute_scratch_size
> queue
->compute_scratch_size
) {
2294 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2295 compute_scratch_size
,
2299 if (!compute_scratch_bo
)
2303 compute_scratch_bo
= queue
->compute_scratch_bo
;
2305 if (esgs_ring_size
> queue
->esgs_ring_size
) {
2306 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2314 esgs_ring_bo
= queue
->esgs_ring_bo
;
2315 esgs_ring_size
= queue
->esgs_ring_size
;
2318 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
2319 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2327 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
2328 gsvs_ring_size
= queue
->gsvs_ring_size
;
2331 if (add_tess_rings
) {
2332 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2333 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
2340 tess_rings_bo
= queue
->tess_rings_bo
;
2343 if (scratch_bo
!= queue
->scratch_bo
||
2344 esgs_ring_bo
!= queue
->esgs_ring_bo
||
2345 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
2346 tess_rings_bo
!= queue
->tess_rings_bo
||
2347 add_sample_positions
) {
2349 if (gsvs_ring_bo
|| esgs_ring_bo
||
2350 tess_rings_bo
|| add_sample_positions
) {
2351 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
2352 if (add_sample_positions
)
2353 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2355 else if (scratch_bo
)
2356 size
= 8; /* 2 dword */
2358 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
2362 RADEON_FLAG_CPU_ACCESS
|
2363 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
2364 RADEON_FLAG_READ_ONLY
);
2368 descriptor_bo
= queue
->descriptor_bo
;
2370 for(int i
= 0; i
< 3; ++i
) {
2371 struct radeon_cmdbuf
*cs
= NULL
;
2372 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
2373 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
2380 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
2382 /* Emit initial configuration. */
2383 switch (queue
->queue_family_index
) {
2384 case RADV_QUEUE_GENERAL
:
2385 radv_init_graphics_state(cs
, queue
);
2387 case RADV_QUEUE_COMPUTE
:
2388 radv_init_compute_state(cs
, queue
);
2390 case RADV_QUEUE_TRANSFER
:
2394 if (descriptor_bo
!= queue
->descriptor_bo
) {
2395 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
2398 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
2399 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2400 S_008F04_SWIZZLE_ENABLE(1);
2401 map
[0] = scratch_va
;
2405 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
||
2406 add_sample_positions
)
2407 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
2408 esgs_ring_size
, esgs_ring_bo
,
2409 gsvs_ring_size
, gsvs_ring_bo
,
2410 tess_factor_ring_size
,
2411 tess_offchip_ring_offset
,
2412 tess_offchip_ring_size
,
2415 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
2418 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
2419 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2420 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
2421 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
2422 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
2425 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
2426 gsvs_ring_bo
, gsvs_ring_size
);
2427 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
2428 tess_factor_ring_size
, tess_rings_bo
);
2429 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
2430 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
2433 si_cs_emit_cache_flush(cs
,
2434 queue
->device
->physical_device
->rad_info
.chip_class
,
2436 queue
->queue_family_index
== RING_COMPUTE
&&
2437 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
2438 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
2439 RADV_CMD_FLAG_INV_ICACHE
|
2440 RADV_CMD_FLAG_INV_SMEM_L1
|
2441 RADV_CMD_FLAG_INV_VMEM_L1
|
2442 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2443 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2444 } else if (i
== 1) {
2445 si_cs_emit_cache_flush(cs
,
2446 queue
->device
->physical_device
->rad_info
.chip_class
,
2448 queue
->queue_family_index
== RING_COMPUTE
&&
2449 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
2450 RADV_CMD_FLAG_INV_ICACHE
|
2451 RADV_CMD_FLAG_INV_SMEM_L1
|
2452 RADV_CMD_FLAG_INV_VMEM_L1
|
2453 RADV_CMD_FLAG_INV_GLOBAL_L2
|
2454 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
2457 if (!queue
->device
->ws
->cs_finalize(cs
))
2461 if (queue
->initial_full_flush_preamble_cs
)
2462 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
2464 if (queue
->initial_preamble_cs
)
2465 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
2467 if (queue
->continue_preamble_cs
)
2468 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
2470 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
2471 queue
->initial_preamble_cs
= dest_cs
[1];
2472 queue
->continue_preamble_cs
= dest_cs
[2];
2474 if (scratch_bo
!= queue
->scratch_bo
) {
2475 if (queue
->scratch_bo
)
2476 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
2477 queue
->scratch_bo
= scratch_bo
;
2478 queue
->scratch_size
= scratch_size
;
2481 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
2482 if (queue
->compute_scratch_bo
)
2483 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
2484 queue
->compute_scratch_bo
= compute_scratch_bo
;
2485 queue
->compute_scratch_size
= compute_scratch_size
;
2488 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
2489 if (queue
->esgs_ring_bo
)
2490 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
2491 queue
->esgs_ring_bo
= esgs_ring_bo
;
2492 queue
->esgs_ring_size
= esgs_ring_size
;
2495 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
2496 if (queue
->gsvs_ring_bo
)
2497 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
2498 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
2499 queue
->gsvs_ring_size
= gsvs_ring_size
;
2502 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
2503 queue
->tess_rings_bo
= tess_rings_bo
;
2504 queue
->has_tess_rings
= true;
2507 if (descriptor_bo
!= queue
->descriptor_bo
) {
2508 if (queue
->descriptor_bo
)
2509 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
2511 queue
->descriptor_bo
= descriptor_bo
;
2514 if (add_sample_positions
)
2515 queue
->has_sample_positions
= true;
2517 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
2518 *initial_preamble_cs
= queue
->initial_preamble_cs
;
2519 *continue_preamble_cs
= queue
->continue_preamble_cs
;
2520 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
2521 *continue_preamble_cs
= NULL
;
2524 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
2526 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
2527 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
2528 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
2529 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
2530 queue
->device
->ws
->buffer_destroy(scratch_bo
);
2531 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
2532 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
2533 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
2534 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
2535 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
2536 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
2537 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
2538 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
2539 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2542 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
2543 struct radv_winsys_sem_counts
*counts
,
2545 const VkSemaphore
*sems
,
2549 int syncobj_idx
= 0, sem_idx
= 0;
2551 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
2554 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2555 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2557 if (sem
->temp_syncobj
|| sem
->syncobj
)
2558 counts
->syncobj_count
++;
2560 counts
->sem_count
++;
2563 if (_fence
!= VK_NULL_HANDLE
) {
2564 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2565 if (fence
->temp_syncobj
|| fence
->syncobj
)
2566 counts
->syncobj_count
++;
2569 if (counts
->syncobj_count
) {
2570 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
2571 if (!counts
->syncobj
)
2572 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2575 if (counts
->sem_count
) {
2576 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
2578 free(counts
->syncobj
);
2579 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2583 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2584 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2586 if (sem
->temp_syncobj
) {
2587 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
2589 else if (sem
->syncobj
)
2590 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
2593 counts
->sem
[sem_idx
++] = sem
->sem
;
2597 if (_fence
!= VK_NULL_HANDLE
) {
2598 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2599 if (fence
->temp_syncobj
)
2600 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
2601 else if (fence
->syncobj
)
2602 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
2609 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
2611 free(sem_info
->wait
.syncobj
);
2612 free(sem_info
->wait
.sem
);
2613 free(sem_info
->signal
.syncobj
);
2614 free(sem_info
->signal
.sem
);
2618 static void radv_free_temp_syncobjs(struct radv_device
*device
,
2620 const VkSemaphore
*sems
)
2622 for (uint32_t i
= 0; i
< num_sems
; i
++) {
2623 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
2625 if (sem
->temp_syncobj
) {
2626 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
2627 sem
->temp_syncobj
= 0;
2633 radv_alloc_sem_info(struct radv_instance
*instance
,
2634 struct radv_winsys_sem_info
*sem_info
,
2636 const VkSemaphore
*wait_sems
,
2637 int num_signal_sems
,
2638 const VkSemaphore
*signal_sems
,
2642 memset(sem_info
, 0, sizeof(*sem_info
));
2644 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
, true);
2647 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
, false);
2649 radv_free_sem_info(sem_info
);
2651 /* caller can override these */
2652 sem_info
->cs_emit_wait
= true;
2653 sem_info
->cs_emit_signal
= true;
2657 /* Signals fence as soon as all the work currently put on queue is done. */
2658 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
2659 struct radv_fence
*fence
)
2663 struct radv_winsys_sem_info sem_info
;
2665 result
= radv_alloc_sem_info(queue
->device
->instance
, &sem_info
, 0, NULL
, 0, NULL
,
2666 radv_fence_to_handle(fence
));
2667 if (result
!= VK_SUCCESS
)
2670 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2671 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2672 1, NULL
, NULL
, &sem_info
, NULL
,
2673 false, fence
->fence
);
2674 radv_free_sem_info(&sem_info
);
2677 return vk_error(queue
->device
->instance
, VK_ERROR_DEVICE_LOST
);
2682 VkResult
radv_QueueSubmit(
2684 uint32_t submitCount
,
2685 const VkSubmitInfo
* pSubmits
,
2688 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2689 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2690 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2691 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
2693 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
2694 uint32_t scratch_size
= 0;
2695 uint32_t compute_scratch_size
= 0;
2696 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
2697 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
2699 bool fence_emitted
= false;
2700 bool tess_rings_needed
= false;
2701 bool sample_positions_needed
= false;
2703 /* Do this first so failing to allocate scratch buffers can't result in
2704 * partially executed submissions. */
2705 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2706 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2707 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2708 pSubmits
[i
].pCommandBuffers
[j
]);
2710 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
2711 compute_scratch_size
= MAX2(compute_scratch_size
,
2712 cmd_buffer
->compute_scratch_size_needed
);
2713 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
2714 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
2715 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
2716 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
2720 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
2721 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
2722 sample_positions_needed
, &initial_flush_preamble_cs
,
2723 &initial_preamble_cs
, &continue_preamble_cs
);
2724 if (result
!= VK_SUCCESS
)
2727 for (uint32_t i
= 0; i
< submitCount
; i
++) {
2728 struct radeon_cmdbuf
**cs_array
;
2729 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
2730 bool can_patch
= true;
2732 struct radv_winsys_sem_info sem_info
;
2734 result
= radv_alloc_sem_info(queue
->device
->instance
,
2736 pSubmits
[i
].waitSemaphoreCount
,
2737 pSubmits
[i
].pWaitSemaphores
,
2738 pSubmits
[i
].signalSemaphoreCount
,
2739 pSubmits
[i
].pSignalSemaphores
,
2741 if (result
!= VK_SUCCESS
)
2744 if (!pSubmits
[i
].commandBufferCount
) {
2745 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
2746 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
2747 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2752 radv_loge("failed to submit CS %d\n", i
);
2755 fence_emitted
= true;
2757 radv_free_sem_info(&sem_info
);
2761 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
2762 (pSubmits
[i
].commandBufferCount
));
2764 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
2765 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
2766 pSubmits
[i
].pCommandBuffers
[j
]);
2767 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
2769 cs_array
[j
] = cmd_buffer
->cs
;
2770 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
2773 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
2776 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
2777 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
2778 const struct radv_winsys_bo_list
*bo_list
= NULL
;
2780 advance
= MIN2(max_cs_submission
,
2781 pSubmits
[i
].commandBufferCount
- j
);
2783 if (queue
->device
->trace_bo
)
2784 *queue
->device
->trace_id_ptr
= 0;
2786 sem_info
.cs_emit_wait
= j
== 0;
2787 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
2789 if (unlikely(queue
->device
->use_global_bo_list
)) {
2790 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
2791 bo_list
= &queue
->device
->bo_list
.list
;
2794 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
2795 advance
, initial_preamble
, continue_preamble_cs
,
2797 can_patch
, base_fence
);
2799 if (unlikely(queue
->device
->use_global_bo_list
))
2800 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
2803 radv_loge("failed to submit CS %d\n", i
);
2806 fence_emitted
= true;
2807 if (queue
->device
->trace_bo
) {
2808 radv_check_gpu_hangs(queue
, cs_array
[j
]);
2812 radv_free_temp_syncobjs(queue
->device
,
2813 pSubmits
[i
].waitSemaphoreCount
,
2814 pSubmits
[i
].pWaitSemaphores
);
2815 radv_free_sem_info(&sem_info
);
2820 if (!fence_emitted
) {
2821 result
= radv_signal_fence(queue
, fence
);
2822 if (result
!= VK_SUCCESS
)
2825 fence
->submitted
= true;
2831 VkResult
radv_QueueWaitIdle(
2834 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2836 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
2837 radv_queue_family_to_ring(queue
->queue_family_index
),
2842 VkResult
radv_DeviceWaitIdle(
2845 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2847 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2848 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2849 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2855 VkResult
radv_EnumerateInstanceExtensionProperties(
2856 const char* pLayerName
,
2857 uint32_t* pPropertyCount
,
2858 VkExtensionProperties
* pProperties
)
2860 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
2862 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
2863 if (radv_supported_instance_extensions
.extensions
[i
]) {
2864 vk_outarray_append(&out
, prop
) {
2865 *prop
= radv_instance_extensions
[i
];
2870 return vk_outarray_status(&out
);
2873 VkResult
radv_EnumerateDeviceExtensionProperties(
2874 VkPhysicalDevice physicalDevice
,
2875 const char* pLayerName
,
2876 uint32_t* pPropertyCount
,
2877 VkExtensionProperties
* pProperties
)
2879 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
2880 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
2882 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
2883 if (device
->supported_extensions
.extensions
[i
]) {
2884 vk_outarray_append(&out
, prop
) {
2885 *prop
= radv_device_extensions
[i
];
2890 return vk_outarray_status(&out
);
2893 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2894 VkInstance _instance
,
2897 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
2899 return radv_lookup_entrypoint_checked(pName
,
2900 instance
? instance
->apiVersion
: 0,
2901 instance
? &instance
->enabled_extensions
: NULL
,
2905 /* The loader wants us to expose a second GetInstanceProcAddr function
2906 * to work around certain LD_PRELOAD issues seen in apps.
2909 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2910 VkInstance instance
,
2914 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2915 VkInstance instance
,
2918 return radv_GetInstanceProcAddr(instance
, pName
);
2921 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2925 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2927 return radv_lookup_entrypoint_checked(pName
,
2928 device
->instance
->apiVersion
,
2929 &device
->instance
->enabled_extensions
,
2930 &device
->enabled_extensions
);
2933 bool radv_get_memory_fd(struct radv_device
*device
,
2934 struct radv_device_memory
*memory
,
2937 struct radeon_bo_metadata metadata
;
2939 if (memory
->image
) {
2940 radv_init_metadata(device
, memory
->image
, &metadata
);
2941 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2944 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2948 static VkResult
radv_alloc_memory(struct radv_device
*device
,
2949 const VkMemoryAllocateInfo
* pAllocateInfo
,
2950 const VkAllocationCallbacks
* pAllocator
,
2951 VkDeviceMemory
* pMem
)
2953 struct radv_device_memory
*mem
;
2955 enum radeon_bo_domain domain
;
2957 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
2959 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2961 if (pAllocateInfo
->allocationSize
== 0) {
2962 /* Apparently, this is allowed */
2963 *pMem
= VK_NULL_HANDLE
;
2967 const VkImportMemoryFdInfoKHR
*import_info
=
2968 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
2969 const VkMemoryDedicatedAllocateInfoKHR
*dedicate_info
=
2970 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO_KHR
);
2971 const VkExportMemoryAllocateInfoKHR
*export_info
=
2972 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO_KHR
);
2973 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
2974 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
2976 const struct wsi_memory_allocate_info
*wsi_info
=
2977 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
2979 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2980 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2982 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2984 if (wsi_info
&& wsi_info
->implicit_sync
)
2985 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
2987 if (dedicate_info
) {
2988 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2989 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2995 mem
->user_ptr
= NULL
;
2998 assert(import_info
->handleType
==
2999 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
||
3000 import_info
->handleType
==
3001 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
3002 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
3005 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3008 close(import_info
->fd
);
3010 } else if (host_ptr_info
) {
3011 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
3012 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
3013 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
3014 pAllocateInfo
->allocationSize
);
3016 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3019 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
3022 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
3023 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
3024 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
3025 domain
= RADEON_DOMAIN_GTT
;
3027 domain
= RADEON_DOMAIN_VRAM
;
3029 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
3030 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
3032 flags
|= RADEON_FLAG_CPU_ACCESS
;
3034 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
3035 flags
|= RADEON_FLAG_GTT_WC
;
3037 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
))
3038 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3040 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
3044 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3047 mem
->type_index
= mem_type_index
;
3050 result
= radv_bo_list_add(device
, mem
->bo
);
3051 if (result
!= VK_SUCCESS
)
3054 *pMem
= radv_device_memory_to_handle(mem
);
3059 device
->ws
->buffer_destroy(mem
->bo
);
3061 vk_free2(&device
->alloc
, pAllocator
, mem
);
3066 VkResult
radv_AllocateMemory(
3068 const VkMemoryAllocateInfo
* pAllocateInfo
,
3069 const VkAllocationCallbacks
* pAllocator
,
3070 VkDeviceMemory
* pMem
)
3072 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3073 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
3076 void radv_FreeMemory(
3078 VkDeviceMemory _mem
,
3079 const VkAllocationCallbacks
* pAllocator
)
3081 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3082 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
3087 radv_bo_list_remove(device
, mem
->bo
);
3088 device
->ws
->buffer_destroy(mem
->bo
);
3091 vk_free2(&device
->alloc
, pAllocator
, mem
);
3094 VkResult
radv_MapMemory(
3096 VkDeviceMemory _memory
,
3097 VkDeviceSize offset
,
3099 VkMemoryMapFlags flags
,
3102 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3103 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3111 *ppData
= mem
->user_ptr
;
3113 *ppData
= device
->ws
->buffer_map(mem
->bo
);
3120 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
3123 void radv_UnmapMemory(
3125 VkDeviceMemory _memory
)
3127 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3128 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
3133 if (mem
->user_ptr
== NULL
)
3134 device
->ws
->buffer_unmap(mem
->bo
);
3137 VkResult
radv_FlushMappedMemoryRanges(
3139 uint32_t memoryRangeCount
,
3140 const VkMappedMemoryRange
* pMemoryRanges
)
3145 VkResult
radv_InvalidateMappedMemoryRanges(
3147 uint32_t memoryRangeCount
,
3148 const VkMappedMemoryRange
* pMemoryRanges
)
3153 void radv_GetBufferMemoryRequirements(
3156 VkMemoryRequirements
* pMemoryRequirements
)
3158 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3159 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3161 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3163 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3164 pMemoryRequirements
->alignment
= 4096;
3166 pMemoryRequirements
->alignment
= 16;
3168 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
3171 void radv_GetBufferMemoryRequirements2(
3173 const VkBufferMemoryRequirementsInfo2KHR
* pInfo
,
3174 VkMemoryRequirements2KHR
* pMemoryRequirements
)
3176 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
3177 &pMemoryRequirements
->memoryRequirements
);
3178 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
3179 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3180 switch (ext
->sType
) {
3181 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
3182 VkMemoryDedicatedRequirementsKHR
*req
=
3183 (VkMemoryDedicatedRequirementsKHR
*) ext
;
3184 req
->requiresDedicatedAllocation
= buffer
->shareable
;
3185 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3194 void radv_GetImageMemoryRequirements(
3197 VkMemoryRequirements
* pMemoryRequirements
)
3199 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3200 RADV_FROM_HANDLE(radv_image
, image
, _image
);
3202 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
3204 pMemoryRequirements
->size
= image
->size
;
3205 pMemoryRequirements
->alignment
= image
->alignment
;
3208 void radv_GetImageMemoryRequirements2(
3210 const VkImageMemoryRequirementsInfo2KHR
* pInfo
,
3211 VkMemoryRequirements2KHR
* pMemoryRequirements
)
3213 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
3214 &pMemoryRequirements
->memoryRequirements
);
3216 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
3218 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
3219 switch (ext
->sType
) {
3220 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
3221 VkMemoryDedicatedRequirementsKHR
*req
=
3222 (VkMemoryDedicatedRequirementsKHR
*) ext
;
3223 req
->requiresDedicatedAllocation
= image
->shareable
;
3224 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
3233 void radv_GetImageSparseMemoryRequirements(
3236 uint32_t* pSparseMemoryRequirementCount
,
3237 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
3242 void radv_GetImageSparseMemoryRequirements2(
3244 const VkImageSparseMemoryRequirementsInfo2KHR
* pInfo
,
3245 uint32_t* pSparseMemoryRequirementCount
,
3246 VkSparseImageMemoryRequirements2KHR
* pSparseMemoryRequirements
)
3251 void radv_GetDeviceMemoryCommitment(
3253 VkDeviceMemory memory
,
3254 VkDeviceSize
* pCommittedMemoryInBytes
)
3256 *pCommittedMemoryInBytes
= 0;
3259 VkResult
radv_BindBufferMemory2(VkDevice device
,
3260 uint32_t bindInfoCount
,
3261 const VkBindBufferMemoryInfoKHR
*pBindInfos
)
3263 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3264 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3265 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
3268 buffer
->bo
= mem
->bo
;
3269 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
3277 VkResult
radv_BindBufferMemory(
3280 VkDeviceMemory memory
,
3281 VkDeviceSize memoryOffset
)
3283 const VkBindBufferMemoryInfoKHR info
= {
3284 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
3287 .memoryOffset
= memoryOffset
3290 return radv_BindBufferMemory2(device
, 1, &info
);
3293 VkResult
radv_BindImageMemory2(VkDevice device
,
3294 uint32_t bindInfoCount
,
3295 const VkBindImageMemoryInfoKHR
*pBindInfos
)
3297 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3298 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
3299 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
3302 image
->bo
= mem
->bo
;
3303 image
->offset
= pBindInfos
[i
].memoryOffset
;
3313 VkResult
radv_BindImageMemory(
3316 VkDeviceMemory memory
,
3317 VkDeviceSize memoryOffset
)
3319 const VkBindImageMemoryInfoKHR info
= {
3320 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
3323 .memoryOffset
= memoryOffset
3326 return radv_BindImageMemory2(device
, 1, &info
);
3331 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3332 const VkSparseBufferMemoryBindInfo
*bind
)
3334 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3336 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3337 struct radv_device_memory
*mem
= NULL
;
3339 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3340 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3342 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3343 bind
->pBinds
[i
].resourceOffset
,
3344 bind
->pBinds
[i
].size
,
3345 mem
? mem
->bo
: NULL
,
3346 bind
->pBinds
[i
].memoryOffset
);
3351 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3352 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3354 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3356 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3357 struct radv_device_memory
*mem
= NULL
;
3359 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3360 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3362 device
->ws
->buffer_virtual_bind(image
->bo
,
3363 bind
->pBinds
[i
].resourceOffset
,
3364 bind
->pBinds
[i
].size
,
3365 mem
? mem
->bo
: NULL
,
3366 bind
->pBinds
[i
].memoryOffset
);
3370 VkResult
radv_QueueBindSparse(
3372 uint32_t bindInfoCount
,
3373 const VkBindSparseInfo
* pBindInfo
,
3376 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3377 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3378 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3379 bool fence_emitted
= false;
3383 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
3384 struct radv_winsys_sem_info sem_info
;
3385 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
3386 radv_sparse_buffer_bind_memory(queue
->device
,
3387 pBindInfo
[i
].pBufferBinds
+ j
);
3390 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
3391 radv_sparse_image_opaque_bind_memory(queue
->device
,
3392 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
3396 result
= radv_alloc_sem_info(queue
->device
->instance
,
3398 pBindInfo
[i
].waitSemaphoreCount
,
3399 pBindInfo
[i
].pWaitSemaphores
,
3400 pBindInfo
[i
].signalSemaphoreCount
,
3401 pBindInfo
[i
].pSignalSemaphores
,
3403 if (result
!= VK_SUCCESS
)
3406 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
3407 ret
= queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
3408 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3413 radv_loge("failed to submit CS %d\n", i
);
3417 fence_emitted
= true;
3419 fence
->submitted
= true;
3422 radv_free_sem_info(&sem_info
);
3427 if (!fence_emitted
) {
3428 result
= radv_signal_fence(queue
, fence
);
3429 if (result
!= VK_SUCCESS
)
3432 fence
->submitted
= true;
3438 VkResult
radv_CreateFence(
3440 const VkFenceCreateInfo
* pCreateInfo
,
3441 const VkAllocationCallbacks
* pAllocator
,
3444 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3445 const VkExportFenceCreateInfoKHR
*export
=
3446 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO_KHR
);
3447 VkExternalFenceHandleTypeFlagsKHR handleTypes
=
3448 export
? export
->handleTypes
: 0;
3450 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
3452 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3455 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3457 fence
->fence_wsi
= NULL
;
3458 fence
->submitted
= false;
3459 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
3460 fence
->temp_syncobj
= 0;
3461 if (device
->always_use_syncobj
|| handleTypes
) {
3462 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
3464 vk_free2(&device
->alloc
, pAllocator
, fence
);
3465 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3467 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
3468 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
3470 fence
->fence
= NULL
;
3472 fence
->fence
= device
->ws
->create_fence();
3473 if (!fence
->fence
) {
3474 vk_free2(&device
->alloc
, pAllocator
, fence
);
3475 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3480 *pFence
= radv_fence_to_handle(fence
);
3485 void radv_DestroyFence(
3488 const VkAllocationCallbacks
* pAllocator
)
3490 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3491 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3496 if (fence
->temp_syncobj
)
3497 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3499 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
3501 device
->ws
->destroy_fence(fence
->fence
);
3502 if (fence
->fence_wsi
)
3503 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
3504 vk_free2(&device
->alloc
, pAllocator
, fence
);
3508 static uint64_t radv_get_current_time()
3511 clock_gettime(CLOCK_MONOTONIC
, &tv
);
3512 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
3515 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
3517 uint64_t current_time
= radv_get_current_time();
3519 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
3521 return current_time
+ timeout
;
3525 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount
, const VkFence
*pFences
)
3527 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3528 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3529 if (fence
->fence
== NULL
|| fence
->syncobj
||
3530 fence
->temp_syncobj
||
3531 (!fence
->signalled
&& !fence
->submitted
))
3537 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
3539 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3540 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3541 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
3547 VkResult
radv_WaitForFences(
3549 uint32_t fenceCount
,
3550 const VkFence
* pFences
,
3554 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3555 timeout
= radv_get_absolute_timeout(timeout
);
3557 if (device
->always_use_syncobj
&&
3558 radv_all_fences_syncobj(fenceCount
, pFences
))
3560 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
3562 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3564 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3565 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3566 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
3569 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
3572 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3575 if (!waitAll
&& fenceCount
> 1) {
3576 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3577 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(fenceCount
, pFences
)) {
3578 uint32_t wait_count
= 0;
3579 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
3581 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3583 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3584 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3586 if (fence
->signalled
) {
3591 fences
[wait_count
++] = fence
->fence
;
3594 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
3595 waitAll
, timeout
- radv_get_current_time());
3598 return success
? VK_SUCCESS
: VK_TIMEOUT
;
3601 while(radv_get_current_time() <= timeout
) {
3602 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3603 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
3610 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
3611 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3612 bool expired
= false;
3614 if (fence
->temp_syncobj
) {
3615 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
3620 if (fence
->syncobj
) {
3621 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
3626 if (fence
->signalled
)
3630 if (!fence
->submitted
) {
3631 while(radv_get_current_time() <= timeout
&&
3635 if (!fence
->submitted
)
3638 /* Recheck as it may have been set by
3639 * submitting operations. */
3641 if (fence
->signalled
)
3645 expired
= device
->ws
->fence_wait(device
->ws
,
3652 if (fence
->fence_wsi
) {
3653 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
3654 if (result
!= VK_SUCCESS
)
3658 fence
->signalled
= true;
3664 VkResult
radv_ResetFences(VkDevice _device
,
3665 uint32_t fenceCount
,
3666 const VkFence
*pFences
)
3668 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3670 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
3671 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
3672 fence
->submitted
= fence
->signalled
= false;
3674 /* Per spec, we first restore the permanent payload, and then reset, so
3675 * having a temp syncobj should not skip resetting the permanent syncobj. */
3676 if (fence
->temp_syncobj
) {
3677 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
3678 fence
->temp_syncobj
= 0;
3681 if (fence
->syncobj
) {
3682 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
3689 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
3691 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3692 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3694 if (fence
->temp_syncobj
) {
3695 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
3696 return success
? VK_SUCCESS
: VK_NOT_READY
;
3699 if (fence
->syncobj
) {
3700 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
3701 return success
? VK_SUCCESS
: VK_NOT_READY
;
3704 if (fence
->signalled
)
3706 if (!fence
->submitted
)
3707 return VK_NOT_READY
;
3709 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
3710 return VK_NOT_READY
;
3712 if (fence
->fence_wsi
) {
3713 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
3715 if (result
!= VK_SUCCESS
) {
3716 if (result
== VK_TIMEOUT
)
3717 return VK_NOT_READY
;
3725 // Queue semaphore functions
3727 VkResult
radv_CreateSemaphore(
3729 const VkSemaphoreCreateInfo
* pCreateInfo
,
3730 const VkAllocationCallbacks
* pAllocator
,
3731 VkSemaphore
* pSemaphore
)
3733 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3734 const VkExportSemaphoreCreateInfoKHR
*export
=
3735 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO_KHR
);
3736 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes
=
3737 export
? export
->handleTypes
: 0;
3739 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
3741 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3743 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3745 sem
->temp_syncobj
= 0;
3746 /* create a syncobject if we are going to export this semaphore */
3747 if (device
->always_use_syncobj
|| handleTypes
) {
3748 assert (device
->physical_device
->rad_info
.has_syncobj
);
3749 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
3751 vk_free2(&device
->alloc
, pAllocator
, sem
);
3752 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3756 sem
->sem
= device
->ws
->create_sem(device
->ws
);
3758 vk_free2(&device
->alloc
, pAllocator
, sem
);
3759 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3764 *pSemaphore
= radv_semaphore_to_handle(sem
);
3768 void radv_DestroySemaphore(
3770 VkSemaphore _semaphore
,
3771 const VkAllocationCallbacks
* pAllocator
)
3773 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3774 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
3779 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
3781 device
->ws
->destroy_sem(sem
->sem
);
3782 vk_free2(&device
->alloc
, pAllocator
, sem
);
3785 VkResult
radv_CreateEvent(
3787 const VkEventCreateInfo
* pCreateInfo
,
3788 const VkAllocationCallbacks
* pAllocator
,
3791 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3792 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
3794 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3797 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3799 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
3801 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
);
3803 vk_free2(&device
->alloc
, pAllocator
, event
);
3804 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3807 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
3809 *pEvent
= radv_event_to_handle(event
);
3814 void radv_DestroyEvent(
3817 const VkAllocationCallbacks
* pAllocator
)
3819 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3820 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3824 device
->ws
->buffer_destroy(event
->bo
);
3825 vk_free2(&device
->alloc
, pAllocator
, event
);
3828 VkResult
radv_GetEventStatus(
3832 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3834 if (*event
->map
== 1)
3835 return VK_EVENT_SET
;
3836 return VK_EVENT_RESET
;
3839 VkResult
radv_SetEvent(
3843 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3849 VkResult
radv_ResetEvent(
3853 RADV_FROM_HANDLE(radv_event
, event
, _event
);
3859 VkResult
radv_CreateBuffer(
3861 const VkBufferCreateInfo
* pCreateInfo
,
3862 const VkAllocationCallbacks
* pAllocator
,
3865 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3866 struct radv_buffer
*buffer
;
3868 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
3870 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
3871 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3873 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3875 buffer
->size
= pCreateInfo
->size
;
3876 buffer
->usage
= pCreateInfo
->usage
;
3879 buffer
->flags
= pCreateInfo
->flags
;
3881 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
3882 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR
) != NULL
;
3884 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
3885 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
3886 align64(buffer
->size
, 4096),
3887 4096, 0, RADEON_FLAG_VIRTUAL
);
3889 vk_free2(&device
->alloc
, pAllocator
, buffer
);
3890 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3894 *pBuffer
= radv_buffer_to_handle(buffer
);
3899 void radv_DestroyBuffer(
3902 const VkAllocationCallbacks
* pAllocator
)
3904 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3905 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
3910 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
3911 device
->ws
->buffer_destroy(buffer
->bo
);
3913 vk_free2(&device
->alloc
, pAllocator
, buffer
);
3916 static inline unsigned
3917 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
3920 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
3922 return image
->surface
.u
.legacy
.tiling_index
[level
];
3925 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
3927 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
3931 radv_init_dcc_control_reg(struct radv_device
*device
,
3932 struct radv_image_view
*iview
)
3934 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
3935 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
3936 unsigned max_compressed_block_size
;
3937 unsigned independent_64b_blocks
;
3939 if (!radv_image_has_dcc(iview
->image
))
3942 if (iview
->image
->info
.samples
> 1) {
3943 if (iview
->image
->surface
.bpe
== 1)
3944 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
3945 else if (iview
->image
->surface
.bpe
== 2)
3946 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
3949 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
3950 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3951 * dGPU and 64 for APU because all of our APUs to date use
3952 * DIMMs which have a request granularity size of 64B while all
3953 * other chips have a 32B request size.
3955 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
3958 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
3959 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
3960 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
3961 /* If this DCC image is potentially going to be used in texture
3962 * fetches, we need some special settings.
3964 independent_64b_blocks
= 1;
3965 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
3967 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3968 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3969 * big as possible for better compression state.
3971 independent_64b_blocks
= 0;
3972 max_compressed_block_size
= max_uncompressed_block_size
;
3975 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
3976 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
3977 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
3978 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
);
3982 radv_initialise_color_surface(struct radv_device
*device
,
3983 struct radv_color_buffer_info
*cb
,
3984 struct radv_image_view
*iview
)
3986 const struct vk_format_description
*desc
;
3987 unsigned ntype
, format
, swap
, endian
;
3988 unsigned blend_clamp
= 0, blend_bypass
= 0;
3990 const struct radeon_surf
*surf
= &iview
->image
->surface
;
3992 desc
= vk_format_description(iview
->vk_format
);
3994 memset(cb
, 0, sizeof(*cb
));
3996 /* Intensity is implemented as Red, so treat it that way. */
3997 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
3999 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4001 cb
->cb_color_base
= va
>> 8;
4003 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4004 struct gfx9_surf_meta_flags meta
;
4005 if (iview
->image
->dcc_offset
)
4006 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
4008 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
4010 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
4011 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
4012 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
4013 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
4015 cb
->cb_color_base
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
4016 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
4018 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
4019 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
4021 cb
->cb_color_base
+= level_info
->offset
>> 8;
4022 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
4023 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
4025 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
4026 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
4027 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
4029 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
4030 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
4031 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
4033 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
4035 if (radv_image_has_fmask(iview
->image
)) {
4036 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
4037 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
4038 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
4039 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
4041 /* This must be set for fast clear to work without FMASK. */
4042 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
4043 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
4044 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
4045 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
4049 /* CMASK variables */
4050 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4051 va
+= iview
->image
->cmask
.offset
;
4052 cb
->cb_color_cmask
= va
>> 8;
4054 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4055 va
+= iview
->image
->dcc_offset
;
4056 cb
->cb_dcc_base
= va
>> 8;
4057 cb
->cb_dcc_base
|= iview
->image
->surface
.tile_swizzle
;
4059 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4060 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
4061 S_028C6C_SLICE_MAX(max_slice
);
4063 if (iview
->image
->info
.samples
> 1) {
4064 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
4066 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
4067 S_028C74_NUM_FRAGMENTS(log_samples
);
4070 if (radv_image_has_fmask(iview
->image
)) {
4071 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
4072 cb
->cb_color_fmask
= va
>> 8;
4073 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
4075 cb
->cb_color_fmask
= cb
->cb_color_base
;
4078 ntype
= radv_translate_color_numformat(iview
->vk_format
,
4080 vk_format_get_first_non_void_channel(iview
->vk_format
));
4081 format
= radv_translate_colorformat(iview
->vk_format
);
4082 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
4083 radv_finishme("Illegal color\n");
4084 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
4085 endian
= radv_colorformat_endian_swap(format
);
4087 /* blend clamp should be set for all NORM/SRGB types */
4088 if (ntype
== V_028C70_NUMBER_UNORM
||
4089 ntype
== V_028C70_NUMBER_SNORM
||
4090 ntype
== V_028C70_NUMBER_SRGB
)
4093 /* set blend bypass according to docs if SINT/UINT or
4094 8/24 COLOR variants */
4095 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
4096 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
4097 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
4102 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
4103 (format
== V_028C70_COLOR_8
||
4104 format
== V_028C70_COLOR_8_8
||
4105 format
== V_028C70_COLOR_8_8_8_8
))
4106 ->color_is_int8
= true;
4108 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
4109 S_028C70_COMP_SWAP(swap
) |
4110 S_028C70_BLEND_CLAMP(blend_clamp
) |
4111 S_028C70_BLEND_BYPASS(blend_bypass
) |
4112 S_028C70_SIMPLE_FLOAT(1) |
4113 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
4114 ntype
!= V_028C70_NUMBER_SNORM
&&
4115 ntype
!= V_028C70_NUMBER_SRGB
&&
4116 format
!= V_028C70_COLOR_8_24
&&
4117 format
!= V_028C70_COLOR_24_8
) |
4118 S_028C70_NUMBER_TYPE(ntype
) |
4119 S_028C70_ENDIAN(endian
);
4120 if (radv_image_has_fmask(iview
->image
)) {
4121 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
4122 if (device
->physical_device
->rad_info
.chip_class
== SI
) {
4123 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
4124 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
4128 if (radv_image_has_cmask(iview
->image
) &&
4129 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
4130 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
4132 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4133 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
4135 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
4137 /* This must be set for fast clear to work without FMASK. */
4138 if (!radv_image_has_fmask(iview
->image
) &&
4139 device
->physical_device
->rad_info
.chip_class
== SI
) {
4140 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
4141 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
4144 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4145 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
4146 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
4148 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
4149 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
4150 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
4151 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->extent
.width
- 1) |
4152 S_028C68_MIP0_HEIGHT(iview
->extent
.height
- 1) |
4153 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
4158 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
4159 struct radv_image_view
*iview
)
4161 unsigned max_zplanes
= 0;
4163 assert(radv_image_is_tc_compat_htile(iview
->image
));
4165 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4166 /* Default value for 32-bit depth surfaces. */
4169 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
4170 iview
->image
->info
.samples
> 1)
4173 max_zplanes
= max_zplanes
+ 1;
4175 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
4176 /* Do not enable Z plane compression for 16-bit depth
4177 * surfaces because isn't supported on GFX8. Only
4178 * 32-bit depth surfaces are supported by the hardware.
4179 * This allows to maintain shader compatibility and to
4180 * reduce the number of depth decompressions.
4184 if (iview
->image
->info
.samples
<= 1)
4186 else if (iview
->image
->info
.samples
<= 4)
4197 radv_initialise_ds_surface(struct radv_device
*device
,
4198 struct radv_ds_buffer_info
*ds
,
4199 struct radv_image_view
*iview
)
4201 unsigned level
= iview
->base_mip
;
4202 unsigned format
, stencil_format
;
4203 uint64_t va
, s_offs
, z_offs
;
4204 bool stencil_only
= false;
4205 memset(ds
, 0, sizeof(*ds
));
4206 switch (iview
->image
->vk_format
) {
4207 case VK_FORMAT_D24_UNORM_S8_UINT
:
4208 case VK_FORMAT_X8_D24_UNORM_PACK32
:
4209 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4210 ds
->offset_scale
= 2.0f
;
4212 case VK_FORMAT_D16_UNORM
:
4213 case VK_FORMAT_D16_UNORM_S8_UINT
:
4214 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4215 ds
->offset_scale
= 4.0f
;
4217 case VK_FORMAT_D32_SFLOAT
:
4218 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
4219 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4220 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4221 ds
->offset_scale
= 1.0f
;
4223 case VK_FORMAT_S8_UINT
:
4224 stencil_only
= true;
4230 format
= radv_translate_dbformat(iview
->image
->vk_format
);
4231 stencil_format
= iview
->image
->surface
.has_stencil
?
4232 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
4234 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
4235 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
4236 S_028008_SLICE_MAX(max_slice
);
4238 ds
->db_htile_data_base
= 0;
4239 ds
->db_htile_surface
= 0;
4241 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
4242 s_offs
= z_offs
= va
;
4244 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4245 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
4246 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
4248 ds
->db_z_info
= S_028038_FORMAT(format
) |
4249 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
4250 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
4251 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
4252 S_028038_ZRANGE_PRECISION(1);
4253 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
4254 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
4256 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
4257 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
4258 ds
->db_depth_view
|= S_028008_MIPID(level
);
4260 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
4261 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
4263 if (radv_htile_enabled(iview
->image
, level
)) {
4264 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
4266 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4267 unsigned max_zplanes
=
4268 radv_calc_decompress_on_z_planes(device
, iview
);
4270 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
) |
4271 S_028038_ITERATE_FLUSH(1);
4272 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
4275 if (!iview
->image
->surface
.has_stencil
)
4276 /* Use all of the htile_buffer for depth if there's no stencil. */
4277 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
4278 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4279 iview
->image
->htile_offset
;
4280 ds
->db_htile_data_base
= va
>> 8;
4281 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
4282 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
4283 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
4286 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
4289 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
4291 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
4292 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
4294 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
4295 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
4296 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
4298 if (iview
->image
->info
.samples
> 1)
4299 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
4301 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
4302 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
4303 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
4304 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4305 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
4306 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
4307 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
4308 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
4311 tile_mode
= stencil_tile_mode
;
4313 ds
->db_depth_info
|=
4314 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
4315 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
4316 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
4317 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
4318 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
4319 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
4320 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
4321 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
4323 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
4324 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4325 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
4326 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
4328 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
4331 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
4332 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
4333 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
4335 if (radv_htile_enabled(iview
->image
, level
)) {
4336 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
4338 if (!iview
->image
->surface
.has_stencil
&&
4339 !radv_image_is_tc_compat_htile(iview
->image
))
4340 /* Use all of the htile_buffer for depth if there's no stencil. */
4341 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
4343 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
4344 iview
->image
->htile_offset
;
4345 ds
->db_htile_data_base
= va
>> 8;
4346 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
4348 if (radv_image_is_tc_compat_htile(iview
->image
)) {
4349 unsigned max_zplanes
=
4350 radv_calc_decompress_on_z_planes(device
, iview
);
4352 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
4353 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
4358 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
4359 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
4362 VkResult
radv_CreateFramebuffer(
4364 const VkFramebufferCreateInfo
* pCreateInfo
,
4365 const VkAllocationCallbacks
* pAllocator
,
4366 VkFramebuffer
* pFramebuffer
)
4368 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4369 struct radv_framebuffer
*framebuffer
;
4371 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
4373 size_t size
= sizeof(*framebuffer
) +
4374 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
4375 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
4376 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4377 if (framebuffer
== NULL
)
4378 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4380 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
4381 framebuffer
->width
= pCreateInfo
->width
;
4382 framebuffer
->height
= pCreateInfo
->height
;
4383 framebuffer
->layers
= pCreateInfo
->layers
;
4384 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
4385 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
4386 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
4387 framebuffer
->attachments
[i
].attachment
= iview
;
4388 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
4389 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
4390 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
4391 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
4393 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
4394 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
4395 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
4398 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
4402 void radv_DestroyFramebuffer(
4405 const VkAllocationCallbacks
* pAllocator
)
4407 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4408 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
4412 vk_free2(&device
->alloc
, pAllocator
, fb
);
4415 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
4417 switch (address_mode
) {
4418 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
4419 return V_008F30_SQ_TEX_WRAP
;
4420 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
4421 return V_008F30_SQ_TEX_MIRROR
;
4422 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
4423 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
4424 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
4425 return V_008F30_SQ_TEX_CLAMP_BORDER
;
4426 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
4427 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
4429 unreachable("illegal tex wrap mode");
4435 radv_tex_compare(VkCompareOp op
)
4438 case VK_COMPARE_OP_NEVER
:
4439 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
4440 case VK_COMPARE_OP_LESS
:
4441 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
4442 case VK_COMPARE_OP_EQUAL
:
4443 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
4444 case VK_COMPARE_OP_LESS_OR_EQUAL
:
4445 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
4446 case VK_COMPARE_OP_GREATER
:
4447 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
4448 case VK_COMPARE_OP_NOT_EQUAL
:
4449 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
4450 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
4451 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
4452 case VK_COMPARE_OP_ALWAYS
:
4453 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
4455 unreachable("illegal compare mode");
4461 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
4464 case VK_FILTER_NEAREST
:
4465 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
4466 V_008F38_SQ_TEX_XY_FILTER_POINT
);
4467 case VK_FILTER_LINEAR
:
4468 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
4469 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
4470 case VK_FILTER_CUBIC_IMG
:
4472 fprintf(stderr
, "illegal texture filter");
4478 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
4481 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
4482 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
4483 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
4484 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
4486 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
4491 radv_tex_bordercolor(VkBorderColor bcolor
)
4494 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
4495 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
4496 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
4497 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
4498 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
4499 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
4500 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
4501 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
4502 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
4510 radv_tex_aniso_filter(unsigned filter
)
4524 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
4527 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
4528 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4529 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
4530 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
4531 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
4532 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
4540 radv_get_max_anisotropy(struct radv_device
*device
,
4541 const VkSamplerCreateInfo
*pCreateInfo
)
4543 if (device
->force_aniso
>= 0)
4544 return device
->force_aniso
;
4546 if (pCreateInfo
->anisotropyEnable
&&
4547 pCreateInfo
->maxAnisotropy
> 1.0f
)
4548 return (uint32_t)pCreateInfo
->maxAnisotropy
;
4554 radv_init_sampler(struct radv_device
*device
,
4555 struct radv_sampler
*sampler
,
4556 const VkSamplerCreateInfo
*pCreateInfo
)
4558 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
4559 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
4560 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
4561 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
4563 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
4564 vk_find_struct_const(pCreateInfo
->pNext
,
4565 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
4566 if (sampler_reduction
)
4567 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
4569 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
4570 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
4571 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
4572 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
4573 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
4574 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
4575 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
4576 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
4577 S_008F30_DISABLE_CUBE_WRAP(0) |
4578 S_008F30_COMPAT_MODE(is_vi
) |
4579 S_008F30_FILTER_MODE(filter_mode
));
4580 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
4581 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
4582 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
4583 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
4584 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
4585 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
4586 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
4587 S_008F38_MIP_POINT_PRECLAMP(0) |
4588 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= VI
) |
4589 S_008F38_FILTER_PREC_FIX(1) |
4590 S_008F38_ANISO_OVERRIDE(is_vi
));
4591 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4592 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
4595 VkResult
radv_CreateSampler(
4597 const VkSamplerCreateInfo
* pCreateInfo
,
4598 const VkAllocationCallbacks
* pAllocator
,
4599 VkSampler
* pSampler
)
4601 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4602 struct radv_sampler
*sampler
;
4604 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
4606 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
4607 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4609 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4611 radv_init_sampler(device
, sampler
, pCreateInfo
);
4612 *pSampler
= radv_sampler_to_handle(sampler
);
4617 void radv_DestroySampler(
4620 const VkAllocationCallbacks
* pAllocator
)
4622 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4623 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
4627 vk_free2(&device
->alloc
, pAllocator
, sampler
);
4630 /* vk_icd.h does not declare this function, so we declare it here to
4631 * suppress Wmissing-prototypes.
4633 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4634 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
4636 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4637 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
4639 /* For the full details on loader interface versioning, see
4640 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4641 * What follows is a condensed summary, to help you navigate the large and
4642 * confusing official doc.
4644 * - Loader interface v0 is incompatible with later versions. We don't
4647 * - In loader interface v1:
4648 * - The first ICD entrypoint called by the loader is
4649 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4651 * - The ICD must statically expose no other Vulkan symbol unless it is
4652 * linked with -Bsymbolic.
4653 * - Each dispatchable Vulkan handle created by the ICD must be
4654 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4655 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4656 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4657 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4658 * such loader-managed surfaces.
4660 * - Loader interface v2 differs from v1 in:
4661 * - The first ICD entrypoint called by the loader is
4662 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4663 * statically expose this entrypoint.
4665 * - Loader interface v3 differs from v2 in:
4666 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4667 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4668 * because the loader no longer does so.
4670 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
4674 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
4675 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
4678 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4679 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
4681 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
4683 /* At the moment, we support only the below handle types. */
4684 assert(pGetFdInfo
->handleType
==
4685 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
||
4686 pGetFdInfo
->handleType
==
4687 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4689 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
4691 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4695 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
4696 VkExternalMemoryHandleTypeFlagBitsKHR handleType
,
4698 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
4700 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4702 switch (handleType
) {
4703 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
4704 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
4708 /* The valid usage section for this function says:
4710 * "handleType must not be one of the handle types defined as
4713 * So opaque handle types fall into the default "unsupported" case.
4715 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
4719 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
4723 uint32_t syncobj_handle
= 0;
4724 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
4726 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
4729 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
4731 *syncobj
= syncobj_handle
;
4737 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
4741 /* If we create a syncobj we do it locally so that if we have an error, we don't
4742 * leave a syncobj in an undetermined state in the fence. */
4743 uint32_t syncobj_handle
= *syncobj
;
4744 if (!syncobj_handle
) {
4745 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
4747 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
4752 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
4754 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
4756 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
4759 *syncobj
= syncobj_handle
;
4766 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
4767 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
4769 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4770 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
4771 uint32_t *syncobj_dst
= NULL
;
4773 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR
) {
4774 syncobj_dst
= &sem
->temp_syncobj
;
4776 syncobj_dst
= &sem
->syncobj
;
4779 switch(pImportSemaphoreFdInfo
->handleType
) {
4780 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
:
4781 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
4782 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR
:
4783 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
4785 unreachable("Unhandled semaphore handle type");
4789 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
4790 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
4793 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4794 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
4796 uint32_t syncobj_handle
;
4798 if (sem
->temp_syncobj
)
4799 syncobj_handle
= sem
->temp_syncobj
;
4801 syncobj_handle
= sem
->syncobj
;
4803 switch(pGetFdInfo
->handleType
) {
4804 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
:
4805 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
4807 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR
:
4808 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
4810 if (sem
->temp_syncobj
) {
4811 close (sem
->temp_syncobj
);
4812 sem
->temp_syncobj
= 0;
4814 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
4819 unreachable("Unhandled semaphore handle type");
4823 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
4827 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4828 VkPhysicalDevice physicalDevice
,
4829 const VkPhysicalDeviceExternalSemaphoreInfoKHR
* pExternalSemaphoreInfo
,
4830 VkExternalSemaphorePropertiesKHR
* pExternalSemaphoreProperties
)
4832 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
4834 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4835 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
4836 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
||
4837 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR
)) {
4838 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR
;
4839 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR
;
4840 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR
|
4841 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
4842 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
) {
4843 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
4844 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
4845 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR
|
4846 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
4848 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
4849 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
4850 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
4854 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
4855 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
4857 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4858 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
4859 uint32_t *syncobj_dst
= NULL
;
4862 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT_KHR
) {
4863 syncobj_dst
= &fence
->temp_syncobj
;
4865 syncobj_dst
= &fence
->syncobj
;
4868 switch(pImportFenceFdInfo
->handleType
) {
4869 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
:
4870 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
4871 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR
:
4872 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
4874 unreachable("Unhandled fence handle type");
4878 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
4879 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
4882 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4883 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
4885 uint32_t syncobj_handle
;
4887 if (fence
->temp_syncobj
)
4888 syncobj_handle
= fence
->temp_syncobj
;
4890 syncobj_handle
= fence
->syncobj
;
4892 switch(pGetFdInfo
->handleType
) {
4893 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
:
4894 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
4896 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR
:
4897 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
4899 if (fence
->temp_syncobj
) {
4900 close (fence
->temp_syncobj
);
4901 fence
->temp_syncobj
= 0;
4903 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
4908 unreachable("Unhandled fence handle type");
4912 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
4916 void radv_GetPhysicalDeviceExternalFenceProperties(
4917 VkPhysicalDevice physicalDevice
,
4918 const VkPhysicalDeviceExternalFenceInfoKHR
* pExternalFenceInfo
,
4919 VkExternalFencePropertiesKHR
* pExternalFenceProperties
)
4921 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
4923 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
4924 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
||
4925 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR
)) {
4926 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR
;
4927 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR
;
4928 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR
|
4929 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
4931 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
4932 pExternalFenceProperties
->compatibleHandleTypes
= 0;
4933 pExternalFenceProperties
->externalFenceFeatures
= 0;
4938 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
4939 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
4940 const VkAllocationCallbacks
* pAllocator
,
4941 VkDebugReportCallbackEXT
* pCallback
)
4943 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4944 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
4945 pCreateInfo
, pAllocator
, &instance
->alloc
,
4950 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
4951 VkDebugReportCallbackEXT _callback
,
4952 const VkAllocationCallbacks
* pAllocator
)
4954 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4955 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
4956 _callback
, pAllocator
, &instance
->alloc
);
4960 radv_DebugReportMessageEXT(VkInstance _instance
,
4961 VkDebugReportFlagsEXT flags
,
4962 VkDebugReportObjectTypeEXT objectType
,
4965 int32_t messageCode
,
4966 const char* pLayerPrefix
,
4967 const char* pMessage
)
4969 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
4970 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
4971 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
4975 radv_GetDeviceGroupPeerMemoryFeatures(
4978 uint32_t localDeviceIndex
,
4979 uint32_t remoteDeviceIndex
,
4980 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
4982 assert(localDeviceIndex
== remoteDeviceIndex
);
4984 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
4985 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
4986 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
4987 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
4990 static const VkTimeDomainEXT radv_time_domains
[] = {
4991 VK_TIME_DOMAIN_DEVICE_EXT
,
4992 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
4993 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
4996 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
4997 VkPhysicalDevice physicalDevice
,
4998 uint32_t *pTimeDomainCount
,
4999 VkTimeDomainEXT
*pTimeDomains
)
5002 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
5004 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
5005 vk_outarray_append(&out
, i
) {
5006 *i
= radv_time_domains
[d
];
5010 return vk_outarray_status(&out
);
5014 radv_clock_gettime(clockid_t clock_id
)
5016 struct timespec current
;
5019 ret
= clock_gettime(clock_id
, ¤t
);
5020 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
5021 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
5025 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
5028 VkResult
radv_GetCalibratedTimestampsEXT(
5030 uint32_t timestampCount
,
5031 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
5032 uint64_t *pTimestamps
,
5033 uint64_t *pMaxDeviation
)
5035 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5036 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
5038 uint64_t begin
, end
;
5039 uint64_t max_clock_period
= 0;
5041 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5043 for (d
= 0; d
< timestampCount
; d
++) {
5044 switch (pTimestampInfos
[d
].timeDomain
) {
5045 case VK_TIME_DOMAIN_DEVICE_EXT
:
5046 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
5048 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
5049 max_clock_period
= MAX2(max_clock_period
, device_period
);
5051 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
5052 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
5053 max_clock_period
= MAX2(max_clock_period
, 1);
5056 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
5057 pTimestamps
[d
] = begin
;
5065 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
5068 * The maximum deviation is the sum of the interval over which we
5069 * perform the sampling and the maximum period of any sampled
5070 * clock. That's because the maximum skew between any two sampled
5071 * clock edges is when the sampled clock with the largest period is
5072 * sampled at the end of that period but right at the beginning of the
5073 * sampling interval and some other clock is sampled right at the
5074 * begining of its sampling period and right at the end of the
5075 * sampling interval. Let's assume the GPU has the longest clock
5076 * period and that the application is sampling GPU and monotonic:
5079 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5080 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5084 * GPU -----_____-----_____-----_____-----_____
5087 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5088 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5090 * Interval <----------------->
5091 * Deviation <-------------------------->
5095 * m = read(monotonic) 2
5098 * We round the sample interval up by one tick to cover sampling error
5099 * in the interval clock
5102 uint64_t sample_interval
= end
- begin
+ 1;
5104 *pMaxDeviation
= sample_interval
+ max_clock_period
;