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radv: Sync ETC2 whitelisted devices.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51
52 static int
53 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
54 {
55 struct mesa_sha1 ctx;
56 unsigned char sha1[20];
57 unsigned ptr_size = sizeof(void*);
58
59 memset(uuid, 0, VK_UUID_SIZE);
60 _mesa_sha1_init(&ctx);
61
62 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
63 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
64 return -1;
65
66 _mesa_sha1_update(&ctx, &family, sizeof(family));
67 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
68 _mesa_sha1_final(&ctx, sha1);
69
70 memcpy(uuid, sha1, VK_UUID_SIZE);
71 return 0;
72 }
73
74 static void
75 radv_get_driver_uuid(void *uuid)
76 {
77 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
78 }
79
80 static void
81 radv_get_device_uuid(struct radeon_info *info, void *uuid)
82 {
83 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
84 }
85
86 static void
87 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
88 {
89 const char *chip_string;
90 char llvm_string[32] = {};
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
103 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
104 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
105 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
106 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
107 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
108 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
109 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
110 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
111 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
112 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
113 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(llvm_string, sizeof(llvm_string),
120 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
121 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
122 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_VEGA10)
222 device->rad_info.chip_class = GFX9;
223 else if (i >= CHIP_TONGA)
224 device->rad_info.chip_class = VI;
225 else if (i >= CHIP_BONAIRE)
226 device->rad_info.chip_class = CIK;
227 else
228 device->rad_info.chip_class = SI;
229
230 return;
231 }
232 }
233
234 fprintf(stderr, "radv: Unknown family: %s\n", family);
235 exit(1);
236 }
237
238 static VkResult
239 radv_physical_device_init(struct radv_physical_device *device,
240 struct radv_instance *instance,
241 drmDevicePtr drm_device)
242 {
243 const char *path = drm_device->nodes[DRM_NODE_RENDER];
244 VkResult result;
245 drmVersionPtr version;
246 int fd;
247 int master_fd = -1;
248
249 fd = open(path, O_RDWR | O_CLOEXEC);
250 if (fd < 0) {
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not open device '%s'", path);
253
254 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
255 }
256
257 version = drmGetVersion(fd);
258 if (!version) {
259 close(fd);
260
261 if (instance->debug_flags & RADV_DEBUG_STARTUP)
262 radv_logi("Could not get the kernel driver version for device '%s'", path);
263
264 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
265 "failed to get version %s: %m", path);
266 }
267
268 if (strcmp(version->name, "amdgpu")) {
269 drmFreeVersion(version);
270 close(fd);
271
272 if (instance->debug_flags & RADV_DEBUG_STARTUP)
273 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
274
275 return VK_ERROR_INCOMPATIBLE_DRIVER;
276 }
277 drmFreeVersion(version);
278
279 if (instance->debug_flags & RADV_DEBUG_STARTUP)
280 radv_logi("Found compatible device '%s'.", path);
281
282 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
283 device->instance = instance;
284
285 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
286 instance->perftest_flags);
287 if (!device->ws) {
288 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
289 goto fail;
290 }
291
292 if (instance->enabled_extensions.KHR_display) {
293 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
294 if (master_fd >= 0) {
295 uint32_t accel_working = 0;
296 struct drm_amdgpu_info request = {
297 .return_pointer = (uintptr_t)&accel_working,
298 .return_size = sizeof(accel_working),
299 .query = AMDGPU_INFO_ACCEL_WORKING
300 };
301
302 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
303 close(master_fd);
304 master_fd = -1;
305 }
306 }
307 }
308
309 device->master_fd = master_fd;
310 device->local_fd = fd;
311 device->ws->query_info(device->ws, &device->rad_info);
312
313 radv_handle_env_var_force_family(device);
314
315 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
316
317 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
318 device->ws->destroy(device->ws);
319 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
320 "cannot generate UUID");
321 goto fail;
322 }
323
324 /* These flags affect shader compilation. */
325 uint64_t shader_env_flags =
326 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
327 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
328
329 /* The gpu id is already embedded in the uuid so we just pass "radv"
330 * when creating the cache.
331 */
332 char buf[VK_UUID_SIZE * 2 + 1];
333 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
334 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
335
336 if (device->rad_info.chip_class < VI ||
337 device->rad_info.chip_class > GFX9)
338 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339
340 radv_get_driver_uuid(&device->device_uuid);
341 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
342
343 if (device->rad_info.family == CHIP_STONEY ||
344 device->rad_info.chip_class >= GFX9) {
345 device->has_rbplus = true;
346 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
347 device->rad_info.family == CHIP_VEGA12 ||
348 device->rad_info.family == CHIP_RAVEN ||
349 device->rad_info.family == CHIP_RAVEN2;
350 }
351
352 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
353 * on SI.
354 */
355 device->has_clear_state = device->rad_info.chip_class >= CIK;
356
357 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
358
359 /* Vega10/Raven need a special workaround for a hardware bug. */
360 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
361 device->rad_info.family == CHIP_RAVEN;
362
363 /* Out-of-order primitive rasterization. */
364 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
365 device->rad_info.max_se >= 2;
366 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
367 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
368
369 device->dcc_msaa_allowed =
370 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
371
372 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
373 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
374 (device->rad_info.chip_class >= VI &&
375 device->rad_info.me_fw_feature >= 41);
376
377 radv_physical_device_init_mem_types(device);
378 radv_fill_device_extension_table(device, &device->supported_extensions);
379
380 device->bus_info = *drm_device->businfo.pci;
381
382 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
383 ac_print_gpu_info(&device->rad_info);
384
385 /* The WSI is structured as a layer on top of the driver, so this has
386 * to be the last part of initialization (at least until we get other
387 * semi-layers).
388 */
389 result = radv_init_wsi(device);
390 if (result != VK_SUCCESS) {
391 device->ws->destroy(device->ws);
392 vk_error(instance, result);
393 goto fail;
394 }
395
396 return VK_SUCCESS;
397
398 fail:
399 close(fd);
400 if (master_fd != -1)
401 close(master_fd);
402 return result;
403 }
404
405 static void
406 radv_physical_device_finish(struct radv_physical_device *device)
407 {
408 radv_finish_wsi(device);
409 device->ws->destroy(device->ws);
410 disk_cache_destroy(device->disk_cache);
411 close(device->local_fd);
412 if (device->master_fd != -1)
413 close(device->master_fd);
414 }
415
416 static void *
417 default_alloc_func(void *pUserData, size_t size, size_t align,
418 VkSystemAllocationScope allocationScope)
419 {
420 return malloc(size);
421 }
422
423 static void *
424 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
425 size_t align, VkSystemAllocationScope allocationScope)
426 {
427 return realloc(pOriginal, size);
428 }
429
430 static void
431 default_free_func(void *pUserData, void *pMemory)
432 {
433 free(pMemory);
434 }
435
436 static const VkAllocationCallbacks default_alloc = {
437 .pUserData = NULL,
438 .pfnAllocation = default_alloc_func,
439 .pfnReallocation = default_realloc_func,
440 .pfnFree = default_free_func,
441 };
442
443 static const struct debug_control radv_debug_options[] = {
444 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
445 {"nodcc", RADV_DEBUG_NO_DCC},
446 {"shaders", RADV_DEBUG_DUMP_SHADERS},
447 {"nocache", RADV_DEBUG_NO_CACHE},
448 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
449 {"nohiz", RADV_DEBUG_NO_HIZ},
450 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
451 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
452 {"allbos", RADV_DEBUG_ALL_BOS},
453 {"noibs", RADV_DEBUG_NO_IBS},
454 {"spirv", RADV_DEBUG_DUMP_SPIRV},
455 {"vmfaults", RADV_DEBUG_VM_FAULTS},
456 {"zerovram", RADV_DEBUG_ZERO_VRAM},
457 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
458 {"nosisched", RADV_DEBUG_NO_SISCHED},
459 {"preoptir", RADV_DEBUG_PREOPTIR},
460 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
461 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
462 {"info", RADV_DEBUG_INFO},
463 {"errors", RADV_DEBUG_ERRORS},
464 {"startup", RADV_DEBUG_STARTUP},
465 {"checkir", RADV_DEBUG_CHECKIR},
466 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
467 {"nobinning", RADV_DEBUG_NOBINNING},
468 {NULL, 0}
469 };
470
471 const char *
472 radv_get_debug_option_name(int id)
473 {
474 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
475 return radv_debug_options[id].string;
476 }
477
478 static const struct debug_control radv_perftest_options[] = {
479 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
480 {"sisched", RADV_PERFTEST_SISCHED},
481 {"localbos", RADV_PERFTEST_LOCAL_BOS},
482 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
483 {NULL, 0}
484 };
485
486 const char *
487 radv_get_perftest_option_name(int id)
488 {
489 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
490 return radv_perftest_options[id].string;
491 }
492
493 static void
494 radv_handle_per_app_options(struct radv_instance *instance,
495 const VkApplicationInfo *info)
496 {
497 const char *name = info ? info->pApplicationName : NULL;
498
499 if (!name)
500 return;
501
502 if (!strcmp(name, "Talos - Linux - 32bit") ||
503 !strcmp(name, "Talos - Linux - 64bit")) {
504 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
505 /* Force enable LLVM sisched for Talos because it looks
506 * safe and it gives few more FPS.
507 */
508 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
509 }
510 } else if (!strcmp(name, "DOOM_VFR")) {
511 /* Work around a Doom VFR game bug */
512 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
513 }
514 }
515
516 static int radv_get_instance_extension_index(const char *name)
517 {
518 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
519 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
520 return i;
521 }
522 return -1;
523 }
524
525
526 VkResult radv_CreateInstance(
527 const VkInstanceCreateInfo* pCreateInfo,
528 const VkAllocationCallbacks* pAllocator,
529 VkInstance* pInstance)
530 {
531 struct radv_instance *instance;
532 VkResult result;
533
534 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
535
536 uint32_t client_version;
537 if (pCreateInfo->pApplicationInfo &&
538 pCreateInfo->pApplicationInfo->apiVersion != 0) {
539 client_version = pCreateInfo->pApplicationInfo->apiVersion;
540 } else {
541 client_version = VK_API_VERSION_1_0;
542 }
543
544 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
545 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
546 if (!instance)
547 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
548
549 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
550
551 if (pAllocator)
552 instance->alloc = *pAllocator;
553 else
554 instance->alloc = default_alloc;
555
556 instance->apiVersion = client_version;
557 instance->physicalDeviceCount = -1;
558
559 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
560 radv_debug_options);
561
562 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
563 radv_perftest_options);
564
565
566 if (instance->debug_flags & RADV_DEBUG_STARTUP)
567 radv_logi("Created an instance");
568
569 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
570 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
571 int index = radv_get_instance_extension_index(ext_name);
572
573 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
574 vk_free2(&default_alloc, pAllocator, instance);
575 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
576 }
577
578 instance->enabled_extensions.extensions[index] = true;
579 }
580
581 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
582 if (result != VK_SUCCESS) {
583 vk_free2(&default_alloc, pAllocator, instance);
584 return vk_error(instance, result);
585 }
586
587 _mesa_locale_init();
588
589 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
590
591 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
592
593 *pInstance = radv_instance_to_handle(instance);
594
595 return VK_SUCCESS;
596 }
597
598 void radv_DestroyInstance(
599 VkInstance _instance,
600 const VkAllocationCallbacks* pAllocator)
601 {
602 RADV_FROM_HANDLE(radv_instance, instance, _instance);
603
604 if (!instance)
605 return;
606
607 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
608 radv_physical_device_finish(instance->physicalDevices + i);
609 }
610
611 VG(VALGRIND_DESTROY_MEMPOOL(instance));
612
613 _mesa_locale_fini();
614
615 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
616
617 vk_free(&instance->alloc, instance);
618 }
619
620 static VkResult
621 radv_enumerate_devices(struct radv_instance *instance)
622 {
623 /* TODO: Check for more devices ? */
624 drmDevicePtr devices[8];
625 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
626 int max_devices;
627
628 instance->physicalDeviceCount = 0;
629
630 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
631
632 if (instance->debug_flags & RADV_DEBUG_STARTUP)
633 radv_logi("Found %d drm nodes", max_devices);
634
635 if (max_devices < 1)
636 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
637
638 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
639 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
640 devices[i]->bustype == DRM_BUS_PCI &&
641 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
642
643 result = radv_physical_device_init(instance->physicalDevices +
644 instance->physicalDeviceCount,
645 instance,
646 devices[i]);
647 if (result == VK_SUCCESS)
648 ++instance->physicalDeviceCount;
649 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
650 break;
651 }
652 }
653 drmFreeDevices(devices, max_devices);
654
655 return result;
656 }
657
658 VkResult radv_EnumeratePhysicalDevices(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceCount,
661 VkPhysicalDevice* pPhysicalDevices)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDevices) {
674 *pPhysicalDeviceCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
678 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
679 }
680
681 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
682 : VK_SUCCESS;
683 }
684
685 VkResult radv_EnumeratePhysicalDeviceGroups(
686 VkInstance _instance,
687 uint32_t* pPhysicalDeviceGroupCount,
688 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
689 {
690 RADV_FROM_HANDLE(radv_instance, instance, _instance);
691 VkResult result;
692
693 if (instance->physicalDeviceCount < 0) {
694 result = radv_enumerate_devices(instance);
695 if (result != VK_SUCCESS &&
696 result != VK_ERROR_INCOMPATIBLE_DRIVER)
697 return result;
698 }
699
700 if (!pPhysicalDeviceGroupProperties) {
701 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
702 } else {
703 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
704 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
705 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
706 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
707 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
708 }
709 }
710 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
711 : VK_SUCCESS;
712 }
713
714 void radv_GetPhysicalDeviceFeatures(
715 VkPhysicalDevice physicalDevice,
716 VkPhysicalDeviceFeatures* pFeatures)
717 {
718 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
719 memset(pFeatures, 0, sizeof(*pFeatures));
720
721 *pFeatures = (VkPhysicalDeviceFeatures) {
722 .robustBufferAccess = true,
723 .fullDrawIndexUint32 = true,
724 .imageCubeArray = true,
725 .independentBlend = true,
726 .geometryShader = true,
727 .tessellationShader = true,
728 .sampleRateShading = true,
729 .dualSrcBlend = true,
730 .logicOp = true,
731 .multiDrawIndirect = true,
732 .drawIndirectFirstInstance = true,
733 .depthClamp = true,
734 .depthBiasClamp = true,
735 .fillModeNonSolid = true,
736 .depthBounds = true,
737 .wideLines = true,
738 .largePoints = true,
739 .alphaToOne = true,
740 .multiViewport = true,
741 .samplerAnisotropy = true,
742 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
743 .textureCompressionASTC_LDR = false,
744 .textureCompressionBC = true,
745 .occlusionQueryPrecise = true,
746 .pipelineStatisticsQuery = true,
747 .vertexPipelineStoresAndAtomics = true,
748 .fragmentStoresAndAtomics = true,
749 .shaderTessellationAndGeometryPointSize = true,
750 .shaderImageGatherExtended = true,
751 .shaderStorageImageExtendedFormats = true,
752 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
753 .shaderUniformBufferArrayDynamicIndexing = true,
754 .shaderSampledImageArrayDynamicIndexing = true,
755 .shaderStorageBufferArrayDynamicIndexing = true,
756 .shaderStorageImageArrayDynamicIndexing = true,
757 .shaderStorageImageReadWithoutFormat = true,
758 .shaderStorageImageWriteWithoutFormat = true,
759 .shaderClipDistance = true,
760 .shaderCullDistance = true,
761 .shaderFloat64 = true,
762 .shaderInt64 = true,
763 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
764 .sparseBinding = true,
765 .variableMultisampleRate = true,
766 .inheritedQueries = true,
767 };
768 }
769
770 void radv_GetPhysicalDeviceFeatures2(
771 VkPhysicalDevice physicalDevice,
772 VkPhysicalDeviceFeatures2 *pFeatures)
773 {
774 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
775 vk_foreach_struct(ext, pFeatures->pNext) {
776 switch (ext->sType) {
777 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
778 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
779 features->variablePointersStorageBuffer = true;
780 features->variablePointers = true;
781 break;
782 }
783 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
784 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
785 features->multiview = true;
786 features->multiviewGeometryShader = true;
787 features->multiviewTessellationShader = true;
788 break;
789 }
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
791 VkPhysicalDeviceShaderDrawParameterFeatures *features =
792 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
793 features->shaderDrawParameters = true;
794 break;
795 }
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
797 VkPhysicalDeviceProtectedMemoryFeatures *features =
798 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
799 features->protectedMemory = false;
800 break;
801 }
802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
803 VkPhysicalDevice16BitStorageFeatures *features =
804 (VkPhysicalDevice16BitStorageFeatures*)ext;
805 bool enabled = pdevice->rad_info.chip_class >= VI;
806 features->storageBuffer16BitAccess = enabled;
807 features->uniformAndStorageBuffer16BitAccess = enabled;
808 features->storagePushConstant16 = enabled;
809 features->storageInputOutput16 = enabled;
810 break;
811 }
812 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
813 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
814 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
815 features->samplerYcbcrConversion = false;
816 break;
817 }
818 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
819 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
820 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
821 features->shaderInputAttachmentArrayDynamicIndexing = true;
822 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
823 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
824 features->shaderUniformBufferArrayNonUniformIndexing = false;
825 features->shaderSampledImageArrayNonUniformIndexing = false;
826 features->shaderStorageBufferArrayNonUniformIndexing = false;
827 features->shaderStorageImageArrayNonUniformIndexing = false;
828 features->shaderInputAttachmentArrayNonUniformIndexing = false;
829 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
830 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
831 features->descriptorBindingUniformBufferUpdateAfterBind = true;
832 features->descriptorBindingSampledImageUpdateAfterBind = true;
833 features->descriptorBindingStorageImageUpdateAfterBind = true;
834 features->descriptorBindingStorageBufferUpdateAfterBind = true;
835 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
836 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
837 features->descriptorBindingUpdateUnusedWhilePending = true;
838 features->descriptorBindingPartiallyBound = true;
839 features->descriptorBindingVariableDescriptorCount = true;
840 features->runtimeDescriptorArray = true;
841 break;
842 }
843 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
844 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
845 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
846 features->conditionalRendering = true;
847 features->inheritedConditionalRendering = false;
848 break;
849 }
850 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
851 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
852 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
853 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
854 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
858 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
859 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
860 features->transformFeedback = true;
861 features->geometryStreams = true;
862 break;
863 }
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
865 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
866 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
867 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
868 break;
869 }
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
871 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
872 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
873 features->memoryPriority = VK_TRUE;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
877 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
878 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
879 features->bufferDeviceAddress = true;
880 features->bufferDeviceAddressCaptureReplay = false;
881 features->bufferDeviceAddressMultiDevice = false;
882 break;
883 }
884 default:
885 break;
886 }
887 }
888 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
889 }
890
891 void radv_GetPhysicalDeviceProperties(
892 VkPhysicalDevice physicalDevice,
893 VkPhysicalDeviceProperties* pProperties)
894 {
895 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
896 VkSampleCountFlags sample_counts = 0xf;
897
898 /* make sure that the entire descriptor set is addressable with a signed
899 * 32-bit int. So the sum of all limits scaled by descriptor size has to
900 * be at most 2 GiB. the combined image & samples object count as one of
901 * both. This limit is for the pipeline layout, not for the set layout, but
902 * there is no set limit, so we just set a pipeline limit. I don't think
903 * any app is going to hit this soon. */
904 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
905 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
906 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
907 32 /* sampler, largest when combined with image */ +
908 64 /* sampled image */ +
909 64 /* storage image */);
910
911 VkPhysicalDeviceLimits limits = {
912 .maxImageDimension1D = (1 << 14),
913 .maxImageDimension2D = (1 << 14),
914 .maxImageDimension3D = (1 << 11),
915 .maxImageDimensionCube = (1 << 14),
916 .maxImageArrayLayers = (1 << 11),
917 .maxTexelBufferElements = 128 * 1024 * 1024,
918 .maxUniformBufferRange = UINT32_MAX,
919 .maxStorageBufferRange = UINT32_MAX,
920 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
921 .maxMemoryAllocationCount = UINT32_MAX,
922 .maxSamplerAllocationCount = 64 * 1024,
923 .bufferImageGranularity = 64, /* A cache line */
924 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
925 .maxBoundDescriptorSets = MAX_SETS,
926 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
927 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
928 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
929 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
930 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
931 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
932 .maxPerStageResources = max_descriptor_set_size,
933 .maxDescriptorSetSamplers = max_descriptor_set_size,
934 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
935 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
936 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
937 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
938 .maxDescriptorSetSampledImages = max_descriptor_set_size,
939 .maxDescriptorSetStorageImages = max_descriptor_set_size,
940 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
941 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
942 .maxVertexInputBindings = MAX_VBS,
943 .maxVertexInputAttributeOffset = 2047,
944 .maxVertexInputBindingStride = 2048,
945 .maxVertexOutputComponents = 128,
946 .maxTessellationGenerationLevel = 64,
947 .maxTessellationPatchSize = 32,
948 .maxTessellationControlPerVertexInputComponents = 128,
949 .maxTessellationControlPerVertexOutputComponents = 128,
950 .maxTessellationControlPerPatchOutputComponents = 120,
951 .maxTessellationControlTotalOutputComponents = 4096,
952 .maxTessellationEvaluationInputComponents = 128,
953 .maxTessellationEvaluationOutputComponents = 128,
954 .maxGeometryShaderInvocations = 127,
955 .maxGeometryInputComponents = 64,
956 .maxGeometryOutputComponents = 128,
957 .maxGeometryOutputVertices = 256,
958 .maxGeometryTotalOutputComponents = 1024,
959 .maxFragmentInputComponents = 128,
960 .maxFragmentOutputAttachments = 8,
961 .maxFragmentDualSrcAttachments = 1,
962 .maxFragmentCombinedOutputResources = 8,
963 .maxComputeSharedMemorySize = 32768,
964 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
965 .maxComputeWorkGroupInvocations = 2048,
966 .maxComputeWorkGroupSize = {
967 2048,
968 2048,
969 2048
970 },
971 .subPixelPrecisionBits = 8,
972 .subTexelPrecisionBits = 8,
973 .mipmapPrecisionBits = 8,
974 .maxDrawIndexedIndexValue = UINT32_MAX,
975 .maxDrawIndirectCount = UINT32_MAX,
976 .maxSamplerLodBias = 16,
977 .maxSamplerAnisotropy = 16,
978 .maxViewports = MAX_VIEWPORTS,
979 .maxViewportDimensions = { (1 << 14), (1 << 14) },
980 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
981 .viewportSubPixelBits = 8,
982 .minMemoryMapAlignment = 4096, /* A page */
983 .minTexelBufferOffsetAlignment = 1,
984 .minUniformBufferOffsetAlignment = 4,
985 .minStorageBufferOffsetAlignment = 4,
986 .minTexelOffset = -32,
987 .maxTexelOffset = 31,
988 .minTexelGatherOffset = -32,
989 .maxTexelGatherOffset = 31,
990 .minInterpolationOffset = -2,
991 .maxInterpolationOffset = 2,
992 .subPixelInterpolationOffsetBits = 8,
993 .maxFramebufferWidth = (1 << 14),
994 .maxFramebufferHeight = (1 << 14),
995 .maxFramebufferLayers = (1 << 10),
996 .framebufferColorSampleCounts = sample_counts,
997 .framebufferDepthSampleCounts = sample_counts,
998 .framebufferStencilSampleCounts = sample_counts,
999 .framebufferNoAttachmentsSampleCounts = sample_counts,
1000 .maxColorAttachments = MAX_RTS,
1001 .sampledImageColorSampleCounts = sample_counts,
1002 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1003 .sampledImageDepthSampleCounts = sample_counts,
1004 .sampledImageStencilSampleCounts = sample_counts,
1005 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1006 .maxSampleMaskWords = 1,
1007 .timestampComputeAndGraphics = true,
1008 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1009 .maxClipDistances = 8,
1010 .maxCullDistances = 8,
1011 .maxCombinedClipAndCullDistances = 8,
1012 .discreteQueuePriorities = 2,
1013 .pointSizeRange = { 0.125, 255.875 },
1014 .lineWidthRange = { 0.0, 7.9921875 },
1015 .pointSizeGranularity = (1.0 / 8.0),
1016 .lineWidthGranularity = (1.0 / 128.0),
1017 .strictLines = false, /* FINISHME */
1018 .standardSampleLocations = true,
1019 .optimalBufferCopyOffsetAlignment = 128,
1020 .optimalBufferCopyRowPitchAlignment = 128,
1021 .nonCoherentAtomSize = 64,
1022 };
1023
1024 *pProperties = (VkPhysicalDeviceProperties) {
1025 .apiVersion = radv_physical_device_api_version(pdevice),
1026 .driverVersion = vk_get_driver_version(),
1027 .vendorID = ATI_VENDOR_ID,
1028 .deviceID = pdevice->rad_info.pci_id,
1029 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1030 .limits = limits,
1031 .sparseProperties = {0},
1032 };
1033
1034 strcpy(pProperties->deviceName, pdevice->name);
1035 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1036 }
1037
1038 void radv_GetPhysicalDeviceProperties2(
1039 VkPhysicalDevice physicalDevice,
1040 VkPhysicalDeviceProperties2 *pProperties)
1041 {
1042 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1043 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1044
1045 vk_foreach_struct(ext, pProperties->pNext) {
1046 switch (ext->sType) {
1047 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1048 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1049 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1050 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1051 break;
1052 }
1053 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1054 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1055 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1056 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1057 properties->deviceLUIDValid = false;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1061 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1062 properties->maxMultiviewViewCount = MAX_VIEWS;
1063 properties->maxMultiviewInstanceIndex = INT_MAX;
1064 break;
1065 }
1066 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1067 VkPhysicalDevicePointClippingProperties *properties =
1068 (VkPhysicalDevicePointClippingProperties*)ext;
1069 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1070 break;
1071 }
1072 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1073 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1074 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1075 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1076 break;
1077 }
1078 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1079 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1080 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1081 properties->minImportedHostPointerAlignment = 4096;
1082 break;
1083 }
1084 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1085 VkPhysicalDeviceSubgroupProperties *properties =
1086 (VkPhysicalDeviceSubgroupProperties*)ext;
1087 properties->subgroupSize = 64;
1088 properties->supportedStages = VK_SHADER_STAGE_ALL;
1089 properties->supportedOperations =
1090 VK_SUBGROUP_FEATURE_BASIC_BIT |
1091 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1092 VK_SUBGROUP_FEATURE_QUAD_BIT |
1093 VK_SUBGROUP_FEATURE_VOTE_BIT;
1094 if (pdevice->rad_info.chip_class >= VI) {
1095 properties->supportedOperations |=
1096 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1097 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1098 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1099 }
1100 properties->quadOperationsInAllStages = true;
1101 break;
1102 }
1103 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1104 VkPhysicalDeviceMaintenance3Properties *properties =
1105 (VkPhysicalDeviceMaintenance3Properties*)ext;
1106 /* Make sure everything is addressable by a signed 32-bit int, and
1107 * our largest descriptors are 96 bytes. */
1108 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1109 /* Our buffer size fields allow only this much */
1110 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1111 break;
1112 }
1113 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1114 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1115 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1116 /* GFX6-8 only support single channel min/max filter. */
1117 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1118 properties->filterMinmaxSingleComponentFormats = true;
1119 break;
1120 }
1121 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1122 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1123 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1124
1125 /* Shader engines. */
1126 properties->shaderEngineCount =
1127 pdevice->rad_info.max_se;
1128 properties->shaderArraysPerEngineCount =
1129 pdevice->rad_info.max_sh_per_se;
1130 properties->computeUnitsPerShaderArray =
1131 pdevice->rad_info.num_good_cu_per_sh;
1132 properties->simdPerComputeUnit = 4;
1133 properties->wavefrontsPerSimd =
1134 pdevice->rad_info.family == CHIP_TONGA ||
1135 pdevice->rad_info.family == CHIP_ICELAND ||
1136 pdevice->rad_info.family == CHIP_POLARIS10 ||
1137 pdevice->rad_info.family == CHIP_POLARIS11 ||
1138 pdevice->rad_info.family == CHIP_POLARIS12 ||
1139 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1140 properties->wavefrontSize = 64;
1141
1142 /* SGPR. */
1143 properties->sgprsPerSimd =
1144 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1145 properties->minSgprAllocation =
1146 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1147 properties->maxSgprAllocation =
1148 pdevice->rad_info.family == CHIP_TONGA ||
1149 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1150 properties->sgprAllocationGranularity =
1151 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1152
1153 /* VGPR. */
1154 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1155 properties->minVgprAllocation = 4;
1156 properties->maxVgprAllocation = 256;
1157 properties->vgprAllocationGranularity = 4;
1158 break;
1159 }
1160 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1161 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1162 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1163 properties->maxVertexAttribDivisor = UINT32_MAX;
1164 break;
1165 }
1166 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1167 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1168 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1169 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1170 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1171 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1172 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1173 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1174 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1175 properties->robustBufferAccessUpdateAfterBind = false;
1176 properties->quadDivergentImplicitLod = false;
1177
1178 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1179 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1180 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1181 32 /* sampler, largest when combined with image */ +
1182 64 /* sampled image */ +
1183 64 /* storage image */);
1184 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1185 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1186 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1187 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1188 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1189 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1190 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1191 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1192 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1193 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1194 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1195 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1196 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1197 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1198 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1199 break;
1200 }
1201 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1202 VkPhysicalDeviceProtectedMemoryProperties *properties =
1203 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1204 properties->protectedNoFault = false;
1205 break;
1206 }
1207 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1208 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1209 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1210 properties->primitiveOverestimationSize = 0;
1211 properties->maxExtraPrimitiveOverestimationSize = 0;
1212 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1213 properties->primitiveUnderestimation = VK_FALSE;
1214 properties->conservativePointAndLineRasterization = VK_FALSE;
1215 properties->degenerateTrianglesRasterized = VK_FALSE;
1216 properties->degenerateLinesRasterized = VK_FALSE;
1217 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1218 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1219 break;
1220 }
1221 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1222 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1223 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1224 properties->pciDomain = pdevice->bus_info.domain;
1225 properties->pciBus = pdevice->bus_info.bus;
1226 properties->pciDevice = pdevice->bus_info.dev;
1227 properties->pciFunction = pdevice->bus_info.func;
1228 break;
1229 }
1230 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1231 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1232 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1233
1234 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1235 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1236 strcpy(driver_props->driverName, "radv");
1237
1238 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1239 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1240 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1241 " (LLVM %d.%d.%d)",
1242 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1243 MESA_LLVM_VERSION_PATCH);
1244
1245 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1246 .major = 1,
1247 .minor = 1,
1248 .subminor = 2,
1249 .patch = 0,
1250 };
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1254 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1255 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1256 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1257 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1258 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1259 properties->maxTransformFeedbackStreamDataSize = 512;
1260 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1261 properties->maxTransformFeedbackBufferDataStride = 512;
1262 properties->transformFeedbackQueries = true;
1263 properties->transformFeedbackStreamsLinesTriangles = false;
1264 properties->transformFeedbackRasterizationStreamSelect = false;
1265 properties->transformFeedbackDraw = true;
1266 break;
1267 }
1268 default:
1269 break;
1270 }
1271 }
1272 }
1273
1274 static void radv_get_physical_device_queue_family_properties(
1275 struct radv_physical_device* pdevice,
1276 uint32_t* pCount,
1277 VkQueueFamilyProperties** pQueueFamilyProperties)
1278 {
1279 int num_queue_families = 1;
1280 int idx;
1281 if (pdevice->rad_info.num_compute_rings > 0 &&
1282 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1283 num_queue_families++;
1284
1285 if (pQueueFamilyProperties == NULL) {
1286 *pCount = num_queue_families;
1287 return;
1288 }
1289
1290 if (!*pCount)
1291 return;
1292
1293 idx = 0;
1294 if (*pCount >= 1) {
1295 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1296 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1297 VK_QUEUE_COMPUTE_BIT |
1298 VK_QUEUE_TRANSFER_BIT |
1299 VK_QUEUE_SPARSE_BINDING_BIT,
1300 .queueCount = 1,
1301 .timestampValidBits = 64,
1302 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1303 };
1304 idx++;
1305 }
1306
1307 if (pdevice->rad_info.num_compute_rings > 0 &&
1308 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1309 if (*pCount > idx) {
1310 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1311 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1312 VK_QUEUE_TRANSFER_BIT |
1313 VK_QUEUE_SPARSE_BINDING_BIT,
1314 .queueCount = pdevice->rad_info.num_compute_rings,
1315 .timestampValidBits = 64,
1316 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1317 };
1318 idx++;
1319 }
1320 }
1321 *pCount = idx;
1322 }
1323
1324 void radv_GetPhysicalDeviceQueueFamilyProperties(
1325 VkPhysicalDevice physicalDevice,
1326 uint32_t* pCount,
1327 VkQueueFamilyProperties* pQueueFamilyProperties)
1328 {
1329 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1330 if (!pQueueFamilyProperties) {
1331 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1332 return;
1333 }
1334 VkQueueFamilyProperties *properties[] = {
1335 pQueueFamilyProperties + 0,
1336 pQueueFamilyProperties + 1,
1337 pQueueFamilyProperties + 2,
1338 };
1339 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1340 assert(*pCount <= 3);
1341 }
1342
1343 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1344 VkPhysicalDevice physicalDevice,
1345 uint32_t* pCount,
1346 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1347 {
1348 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1349 if (!pQueueFamilyProperties) {
1350 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1351 return;
1352 }
1353 VkQueueFamilyProperties *properties[] = {
1354 &pQueueFamilyProperties[0].queueFamilyProperties,
1355 &pQueueFamilyProperties[1].queueFamilyProperties,
1356 &pQueueFamilyProperties[2].queueFamilyProperties,
1357 };
1358 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1359 assert(*pCount <= 3);
1360 }
1361
1362 void radv_GetPhysicalDeviceMemoryProperties(
1363 VkPhysicalDevice physicalDevice,
1364 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1365 {
1366 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1367
1368 *pMemoryProperties = physical_device->memory_properties;
1369 }
1370
1371 static void
1372 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1373 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1374 {
1375 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1376 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1377 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1378 uint64_t vram_size = radv_get_vram_size(device);
1379 uint64_t gtt_size = device->rad_info.gart_size;
1380 uint64_t heap_budget, heap_usage;
1381
1382 /* For all memory heaps, the computation of budget is as follow:
1383 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1384 *
1385 * The Vulkan spec 1.1.97 says that the budget should include any
1386 * currently allocated device memory.
1387 *
1388 * Note that the application heap usages are not really accurate (eg.
1389 * in presence of shared buffers).
1390 */
1391 if (vram_size) {
1392 heap_usage = device->ws->query_value(device->ws,
1393 RADEON_ALLOCATED_VRAM);
1394
1395 heap_budget = vram_size -
1396 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1397 heap_usage;
1398
1399 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1400 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1401 }
1402
1403 if (visible_vram_size) {
1404 heap_usage = device->ws->query_value(device->ws,
1405 RADEON_ALLOCATED_VRAM_VIS);
1406
1407 heap_budget = visible_vram_size -
1408 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1409 heap_usage;
1410
1411 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1412 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1413 }
1414
1415 if (gtt_size) {
1416 heap_usage = device->ws->query_value(device->ws,
1417 RADEON_ALLOCATED_GTT);
1418
1419 heap_budget = gtt_size -
1420 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1421 heap_usage;
1422
1423 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1424 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1425 }
1426
1427 /* The heapBudget and heapUsage values must be zero for array elements
1428 * greater than or equal to
1429 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1430 */
1431 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1432 memoryBudget->heapBudget[i] = 0;
1433 memoryBudget->heapUsage[i] = 0;
1434 }
1435 }
1436
1437 void radv_GetPhysicalDeviceMemoryProperties2(
1438 VkPhysicalDevice physicalDevice,
1439 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1440 {
1441 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1442 &pMemoryProperties->memoryProperties);
1443
1444 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1445 vk_find_struct(pMemoryProperties->pNext,
1446 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1447 if (memory_budget)
1448 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1449 }
1450
1451 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1452 VkDevice _device,
1453 VkExternalMemoryHandleTypeFlagBits handleType,
1454 const void *pHostPointer,
1455 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1456 {
1457 RADV_FROM_HANDLE(radv_device, device, _device);
1458
1459 switch (handleType)
1460 {
1461 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1462 const struct radv_physical_device *physical_device = device->physical_device;
1463 uint32_t memoryTypeBits = 0;
1464 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1465 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1466 memoryTypeBits = (1 << i);
1467 break;
1468 }
1469 }
1470 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1471 return VK_SUCCESS;
1472 }
1473 default:
1474 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1475 }
1476 }
1477
1478 static enum radeon_ctx_priority
1479 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1480 {
1481 /* Default to MEDIUM when a specific global priority isn't requested */
1482 if (!pObj)
1483 return RADEON_CTX_PRIORITY_MEDIUM;
1484
1485 switch(pObj->globalPriority) {
1486 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1487 return RADEON_CTX_PRIORITY_REALTIME;
1488 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1489 return RADEON_CTX_PRIORITY_HIGH;
1490 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1491 return RADEON_CTX_PRIORITY_MEDIUM;
1492 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1493 return RADEON_CTX_PRIORITY_LOW;
1494 default:
1495 unreachable("Illegal global priority value");
1496 return RADEON_CTX_PRIORITY_INVALID;
1497 }
1498 }
1499
1500 static int
1501 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1502 uint32_t queue_family_index, int idx,
1503 VkDeviceQueueCreateFlags flags,
1504 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1505 {
1506 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1507 queue->device = device;
1508 queue->queue_family_index = queue_family_index;
1509 queue->queue_idx = idx;
1510 queue->priority = radv_get_queue_global_priority(global_priority);
1511 queue->flags = flags;
1512
1513 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1514 if (!queue->hw_ctx)
1515 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1516
1517 return VK_SUCCESS;
1518 }
1519
1520 static void
1521 radv_queue_finish(struct radv_queue *queue)
1522 {
1523 if (queue->hw_ctx)
1524 queue->device->ws->ctx_destroy(queue->hw_ctx);
1525
1526 if (queue->initial_full_flush_preamble_cs)
1527 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1528 if (queue->initial_preamble_cs)
1529 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1530 if (queue->continue_preamble_cs)
1531 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1532 if (queue->descriptor_bo)
1533 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1534 if (queue->scratch_bo)
1535 queue->device->ws->buffer_destroy(queue->scratch_bo);
1536 if (queue->esgs_ring_bo)
1537 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1538 if (queue->gsvs_ring_bo)
1539 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1540 if (queue->tess_rings_bo)
1541 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1542 if (queue->compute_scratch_bo)
1543 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1544 }
1545
1546 static void
1547 radv_bo_list_init(struct radv_bo_list *bo_list)
1548 {
1549 pthread_mutex_init(&bo_list->mutex, NULL);
1550 bo_list->list.count = bo_list->capacity = 0;
1551 bo_list->list.bos = NULL;
1552 }
1553
1554 static void
1555 radv_bo_list_finish(struct radv_bo_list *bo_list)
1556 {
1557 free(bo_list->list.bos);
1558 pthread_mutex_destroy(&bo_list->mutex);
1559 }
1560
1561 static VkResult radv_bo_list_add(struct radv_device *device,
1562 struct radeon_winsys_bo *bo)
1563 {
1564 struct radv_bo_list *bo_list = &device->bo_list;
1565
1566 if (bo->is_local)
1567 return VK_SUCCESS;
1568
1569 if (unlikely(!device->use_global_bo_list))
1570 return VK_SUCCESS;
1571
1572 pthread_mutex_lock(&bo_list->mutex);
1573 if (bo_list->list.count == bo_list->capacity) {
1574 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1575 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1576
1577 if (!data) {
1578 pthread_mutex_unlock(&bo_list->mutex);
1579 return VK_ERROR_OUT_OF_HOST_MEMORY;
1580 }
1581
1582 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1583 bo_list->capacity = capacity;
1584 }
1585
1586 bo_list->list.bos[bo_list->list.count++] = bo;
1587 pthread_mutex_unlock(&bo_list->mutex);
1588 return VK_SUCCESS;
1589 }
1590
1591 static void radv_bo_list_remove(struct radv_device *device,
1592 struct radeon_winsys_bo *bo)
1593 {
1594 struct radv_bo_list *bo_list = &device->bo_list;
1595
1596 if (bo->is_local)
1597 return;
1598
1599 if (unlikely(!device->use_global_bo_list))
1600 return;
1601
1602 pthread_mutex_lock(&bo_list->mutex);
1603 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1604 if (bo_list->list.bos[i] == bo) {
1605 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1606 --bo_list->list.count;
1607 break;
1608 }
1609 }
1610 pthread_mutex_unlock(&bo_list->mutex);
1611 }
1612
1613 static void
1614 radv_device_init_gs_info(struct radv_device *device)
1615 {
1616 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1617 device->physical_device->rad_info.family);
1618 }
1619
1620 static int radv_get_device_extension_index(const char *name)
1621 {
1622 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1623 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1624 return i;
1625 }
1626 return -1;
1627 }
1628
1629 static int
1630 radv_get_int_debug_option(const char *name, int default_value)
1631 {
1632 const char *str;
1633 int result;
1634
1635 str = getenv(name);
1636 if (!str) {
1637 result = default_value;
1638 } else {
1639 char *endptr;
1640
1641 result = strtol(str, &endptr, 0);
1642 if (str == endptr) {
1643 /* No digits founs. */
1644 result = default_value;
1645 }
1646 }
1647
1648 return result;
1649 }
1650
1651 VkResult radv_CreateDevice(
1652 VkPhysicalDevice physicalDevice,
1653 const VkDeviceCreateInfo* pCreateInfo,
1654 const VkAllocationCallbacks* pAllocator,
1655 VkDevice* pDevice)
1656 {
1657 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1658 VkResult result;
1659 struct radv_device *device;
1660
1661 bool keep_shader_info = false;
1662
1663 /* Check enabled features */
1664 if (pCreateInfo->pEnabledFeatures) {
1665 VkPhysicalDeviceFeatures supported_features;
1666 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1667 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1668 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1669 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1670 for (uint32_t i = 0; i < num_features; i++) {
1671 if (enabled_feature[i] && !supported_feature[i])
1672 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1673 }
1674 }
1675
1676 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1677 sizeof(*device), 8,
1678 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1679 if (!device)
1680 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1681
1682 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1683 device->instance = physical_device->instance;
1684 device->physical_device = physical_device;
1685
1686 device->ws = physical_device->ws;
1687 if (pAllocator)
1688 device->alloc = *pAllocator;
1689 else
1690 device->alloc = physical_device->instance->alloc;
1691
1692 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1693 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1694 int index = radv_get_device_extension_index(ext_name);
1695 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1696 vk_free(&device->alloc, device);
1697 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1698 }
1699
1700 device->enabled_extensions.extensions[index] = true;
1701 }
1702
1703 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1704
1705 /* With update after bind we can't attach bo's to the command buffer
1706 * from the descriptor set anymore, so we have to use a global BO list.
1707 */
1708 device->use_global_bo_list =
1709 device->enabled_extensions.EXT_descriptor_indexing ||
1710 device->enabled_extensions.EXT_buffer_device_address;
1711
1712 mtx_init(&device->shader_slab_mutex, mtx_plain);
1713 list_inithead(&device->shader_slabs);
1714
1715 radv_bo_list_init(&device->bo_list);
1716
1717 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1718 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1719 uint32_t qfi = queue_create->queueFamilyIndex;
1720 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1721 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1722
1723 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1724
1725 device->queues[qfi] = vk_alloc(&device->alloc,
1726 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1727 if (!device->queues[qfi]) {
1728 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1729 goto fail;
1730 }
1731
1732 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1733
1734 device->queue_count[qfi] = queue_create->queueCount;
1735
1736 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1737 result = radv_queue_init(device, &device->queues[qfi][q],
1738 qfi, q, queue_create->flags,
1739 global_priority);
1740 if (result != VK_SUCCESS)
1741 goto fail;
1742 }
1743 }
1744
1745 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1746 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1747
1748 /* Disabled and not implemented for now. */
1749 device->dfsm_allowed = device->pbb_allowed &&
1750 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1751 device->physical_device->rad_info.family == CHIP_RAVEN2);
1752
1753 #ifdef ANDROID
1754 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1755 #endif
1756
1757 /* The maximum number of scratch waves. Scratch space isn't divided
1758 * evenly between CUs. The number is only a function of the number of CUs.
1759 * We can decrease the constant to decrease the scratch buffer size.
1760 *
1761 * sctx->scratch_waves must be >= the maximum possible size of
1762 * 1 threadgroup, so that the hw doesn't hang from being unable
1763 * to start any.
1764 *
1765 * The recommended value is 4 per CU at most. Higher numbers don't
1766 * bring much benefit, but they still occupy chip resources (think
1767 * async compute). I've seen ~2% performance difference between 4 and 32.
1768 */
1769 uint32_t max_threads_per_block = 2048;
1770 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1771 max_threads_per_block / 64);
1772
1773 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1774
1775 if (device->physical_device->rad_info.chip_class >= CIK) {
1776 /* If the KMD allows it (there is a KMD hw register for it),
1777 * allow launching waves out-of-order.
1778 */
1779 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1780 }
1781
1782 radv_device_init_gs_info(device);
1783
1784 device->tess_offchip_block_dw_size =
1785 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1786 device->has_distributed_tess =
1787 device->physical_device->rad_info.chip_class >= VI &&
1788 device->physical_device->rad_info.max_se >= 2;
1789
1790 if (getenv("RADV_TRACE_FILE")) {
1791 const char *filename = getenv("RADV_TRACE_FILE");
1792
1793 keep_shader_info = true;
1794
1795 if (!radv_init_trace(device))
1796 goto fail;
1797
1798 fprintf(stderr, "*****************************************************************************\n");
1799 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1800 fprintf(stderr, "*****************************************************************************\n");
1801
1802 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1803 radv_dump_enabled_options(device, stderr);
1804 }
1805
1806 device->keep_shader_info = keep_shader_info;
1807
1808 result = radv_device_init_meta(device);
1809 if (result != VK_SUCCESS)
1810 goto fail;
1811
1812 radv_device_init_msaa(device);
1813
1814 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1815 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1816 switch (family) {
1817 case RADV_QUEUE_GENERAL:
1818 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1819 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1820 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1821 break;
1822 case RADV_QUEUE_COMPUTE:
1823 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1824 radeon_emit(device->empty_cs[family], 0);
1825 break;
1826 }
1827 device->ws->cs_finalize(device->empty_cs[family]);
1828 }
1829
1830 if (device->physical_device->rad_info.chip_class >= CIK)
1831 cik_create_gfx_config(device);
1832
1833 VkPipelineCacheCreateInfo ci;
1834 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1835 ci.pNext = NULL;
1836 ci.flags = 0;
1837 ci.pInitialData = NULL;
1838 ci.initialDataSize = 0;
1839 VkPipelineCache pc;
1840 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1841 &ci, NULL, &pc);
1842 if (result != VK_SUCCESS)
1843 goto fail_meta;
1844
1845 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1846
1847 device->force_aniso =
1848 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1849 if (device->force_aniso >= 0) {
1850 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1851 1 << util_logbase2(device->force_aniso));
1852 }
1853
1854 *pDevice = radv_device_to_handle(device);
1855 return VK_SUCCESS;
1856
1857 fail_meta:
1858 radv_device_finish_meta(device);
1859 fail:
1860 radv_bo_list_finish(&device->bo_list);
1861
1862 if (device->trace_bo)
1863 device->ws->buffer_destroy(device->trace_bo);
1864
1865 if (device->gfx_init)
1866 device->ws->buffer_destroy(device->gfx_init);
1867
1868 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1869 for (unsigned q = 0; q < device->queue_count[i]; q++)
1870 radv_queue_finish(&device->queues[i][q]);
1871 if (device->queue_count[i])
1872 vk_free(&device->alloc, device->queues[i]);
1873 }
1874
1875 vk_free(&device->alloc, device);
1876 return result;
1877 }
1878
1879 void radv_DestroyDevice(
1880 VkDevice _device,
1881 const VkAllocationCallbacks* pAllocator)
1882 {
1883 RADV_FROM_HANDLE(radv_device, device, _device);
1884
1885 if (!device)
1886 return;
1887
1888 if (device->trace_bo)
1889 device->ws->buffer_destroy(device->trace_bo);
1890
1891 if (device->gfx_init)
1892 device->ws->buffer_destroy(device->gfx_init);
1893
1894 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1895 for (unsigned q = 0; q < device->queue_count[i]; q++)
1896 radv_queue_finish(&device->queues[i][q]);
1897 if (device->queue_count[i])
1898 vk_free(&device->alloc, device->queues[i]);
1899 if (device->empty_cs[i])
1900 device->ws->cs_destroy(device->empty_cs[i]);
1901 }
1902 radv_device_finish_meta(device);
1903
1904 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1905 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1906
1907 radv_destroy_shader_slabs(device);
1908
1909 radv_bo_list_finish(&device->bo_list);
1910 vk_free(&device->alloc, device);
1911 }
1912
1913 VkResult radv_EnumerateInstanceLayerProperties(
1914 uint32_t* pPropertyCount,
1915 VkLayerProperties* pProperties)
1916 {
1917 if (pProperties == NULL) {
1918 *pPropertyCount = 0;
1919 return VK_SUCCESS;
1920 }
1921
1922 /* None supported at this time */
1923 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1924 }
1925
1926 VkResult radv_EnumerateDeviceLayerProperties(
1927 VkPhysicalDevice physicalDevice,
1928 uint32_t* pPropertyCount,
1929 VkLayerProperties* pProperties)
1930 {
1931 if (pProperties == NULL) {
1932 *pPropertyCount = 0;
1933 return VK_SUCCESS;
1934 }
1935
1936 /* None supported at this time */
1937 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1938 }
1939
1940 void radv_GetDeviceQueue2(
1941 VkDevice _device,
1942 const VkDeviceQueueInfo2* pQueueInfo,
1943 VkQueue* pQueue)
1944 {
1945 RADV_FROM_HANDLE(radv_device, device, _device);
1946 struct radv_queue *queue;
1947
1948 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1949 if (pQueueInfo->flags != queue->flags) {
1950 /* From the Vulkan 1.1.70 spec:
1951 *
1952 * "The queue returned by vkGetDeviceQueue2 must have the same
1953 * flags value from this structure as that used at device
1954 * creation time in a VkDeviceQueueCreateInfo instance. If no
1955 * matching flags were specified at device creation time then
1956 * pQueue will return VK_NULL_HANDLE."
1957 */
1958 *pQueue = VK_NULL_HANDLE;
1959 return;
1960 }
1961
1962 *pQueue = radv_queue_to_handle(queue);
1963 }
1964
1965 void radv_GetDeviceQueue(
1966 VkDevice _device,
1967 uint32_t queueFamilyIndex,
1968 uint32_t queueIndex,
1969 VkQueue* pQueue)
1970 {
1971 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1972 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1973 .queueFamilyIndex = queueFamilyIndex,
1974 .queueIndex = queueIndex
1975 };
1976
1977 radv_GetDeviceQueue2(_device, &info, pQueue);
1978 }
1979
1980 static void
1981 fill_geom_tess_rings(struct radv_queue *queue,
1982 uint32_t *map,
1983 bool add_sample_positions,
1984 uint32_t esgs_ring_size,
1985 struct radeon_winsys_bo *esgs_ring_bo,
1986 uint32_t gsvs_ring_size,
1987 struct radeon_winsys_bo *gsvs_ring_bo,
1988 uint32_t tess_factor_ring_size,
1989 uint32_t tess_offchip_ring_offset,
1990 uint32_t tess_offchip_ring_size,
1991 struct radeon_winsys_bo *tess_rings_bo)
1992 {
1993 uint32_t *desc = &map[4];
1994
1995 if (esgs_ring_bo) {
1996 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
1997
1998 /* stride 0, num records - size, add tid, swizzle, elsize4,
1999 index stride 64 */
2000 desc[0] = esgs_va;
2001 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2002 S_008F04_STRIDE(0) |
2003 S_008F04_SWIZZLE_ENABLE(true);
2004 desc[2] = esgs_ring_size;
2005 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2006 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2007 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2008 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2009 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2010 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2011 S_008F0C_ELEMENT_SIZE(1) |
2012 S_008F0C_INDEX_STRIDE(3) |
2013 S_008F0C_ADD_TID_ENABLE(true);
2014
2015 /* GS entry for ES->GS ring */
2016 /* stride 0, num records - size, elsize0,
2017 index stride 0 */
2018 desc[4] = esgs_va;
2019 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2020 S_008F04_STRIDE(0) |
2021 S_008F04_SWIZZLE_ENABLE(false);
2022 desc[6] = esgs_ring_size;
2023 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2024 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2025 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2026 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2027 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2028 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2029 S_008F0C_ELEMENT_SIZE(0) |
2030 S_008F0C_INDEX_STRIDE(0) |
2031 S_008F0C_ADD_TID_ENABLE(false);
2032 }
2033
2034 desc += 8;
2035
2036 if (gsvs_ring_bo) {
2037 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2038
2039 /* VS entry for GS->VS ring */
2040 /* stride 0, num records - size, elsize0,
2041 index stride 0 */
2042 desc[0] = gsvs_va;
2043 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2044 S_008F04_STRIDE(0) |
2045 S_008F04_SWIZZLE_ENABLE(false);
2046 desc[2] = gsvs_ring_size;
2047 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2048 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2049 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2050 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2051 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2052 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2053 S_008F0C_ELEMENT_SIZE(0) |
2054 S_008F0C_INDEX_STRIDE(0) |
2055 S_008F0C_ADD_TID_ENABLE(false);
2056
2057 /* stride gsvs_itemsize, num records 64
2058 elsize 4, index stride 16 */
2059 /* shader will patch stride and desc[2] */
2060 desc[4] = gsvs_va;
2061 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2062 S_008F04_STRIDE(0) |
2063 S_008F04_SWIZZLE_ENABLE(true);
2064 desc[6] = 0;
2065 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2066 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2067 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2068 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2069 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2070 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2071 S_008F0C_ELEMENT_SIZE(1) |
2072 S_008F0C_INDEX_STRIDE(1) |
2073 S_008F0C_ADD_TID_ENABLE(true);
2074 }
2075
2076 desc += 8;
2077
2078 if (tess_rings_bo) {
2079 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2080 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2081
2082 desc[0] = tess_va;
2083 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2084 S_008F04_STRIDE(0) |
2085 S_008F04_SWIZZLE_ENABLE(false);
2086 desc[2] = tess_factor_ring_size;
2087 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2088 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2089 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2090 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2091 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2092 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2093 S_008F0C_ELEMENT_SIZE(0) |
2094 S_008F0C_INDEX_STRIDE(0) |
2095 S_008F0C_ADD_TID_ENABLE(false);
2096
2097 desc[4] = tess_offchip_va;
2098 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2099 S_008F04_STRIDE(0) |
2100 S_008F04_SWIZZLE_ENABLE(false);
2101 desc[6] = tess_offchip_ring_size;
2102 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2103 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2104 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2105 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2106 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2107 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2108 S_008F0C_ELEMENT_SIZE(0) |
2109 S_008F0C_INDEX_STRIDE(0) |
2110 S_008F0C_ADD_TID_ENABLE(false);
2111 }
2112
2113 desc += 8;
2114
2115 if (add_sample_positions) {
2116 /* add sample positions after all rings */
2117 memcpy(desc, queue->device->sample_locations_1x, 8);
2118 desc += 2;
2119 memcpy(desc, queue->device->sample_locations_2x, 16);
2120 desc += 4;
2121 memcpy(desc, queue->device->sample_locations_4x, 32);
2122 desc += 8;
2123 memcpy(desc, queue->device->sample_locations_8x, 64);
2124 }
2125 }
2126
2127 static unsigned
2128 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2129 {
2130 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2131 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2132 device->physical_device->rad_info.family != CHIP_STONEY;
2133 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2134 unsigned max_offchip_buffers;
2135 unsigned offchip_granularity;
2136 unsigned hs_offchip_param;
2137
2138 /*
2139 * Per RadeonSI:
2140 * This must be one less than the maximum number due to a hw limitation.
2141 * Various hardware bugs in SI, CIK, and GFX9 need this.
2142 *
2143 * Per AMDVLK:
2144 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2145 * Gfx7 should limit max_offchip_buffers to 508
2146 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2147 *
2148 * Follow AMDVLK here.
2149 */
2150 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2151 device->physical_device->rad_info.chip_class == CIK ||
2152 device->physical_device->rad_info.chip_class == SI)
2153 --max_offchip_buffers_per_se;
2154
2155 max_offchip_buffers = max_offchip_buffers_per_se *
2156 device->physical_device->rad_info.max_se;
2157
2158 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2159 * around by setting 4K granularity.
2160 */
2161 if (device->tess_offchip_block_dw_size == 4096) {
2162 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2163 offchip_granularity = V_03093C_X_4K_DWORDS;
2164 } else {
2165 assert(device->tess_offchip_block_dw_size == 8192);
2166 offchip_granularity = V_03093C_X_8K_DWORDS;
2167 }
2168
2169 switch (device->physical_device->rad_info.chip_class) {
2170 case SI:
2171 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2172 break;
2173 case CIK:
2174 case VI:
2175 case GFX9:
2176 default:
2177 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2178 break;
2179 }
2180
2181 *max_offchip_buffers_p = max_offchip_buffers;
2182 if (device->physical_device->rad_info.chip_class >= CIK) {
2183 if (device->physical_device->rad_info.chip_class >= VI)
2184 --max_offchip_buffers;
2185 hs_offchip_param =
2186 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2187 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2188 } else {
2189 hs_offchip_param =
2190 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2191 }
2192 return hs_offchip_param;
2193 }
2194
2195 static void
2196 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2197 struct radeon_winsys_bo *esgs_ring_bo,
2198 uint32_t esgs_ring_size,
2199 struct radeon_winsys_bo *gsvs_ring_bo,
2200 uint32_t gsvs_ring_size)
2201 {
2202 if (!esgs_ring_bo && !gsvs_ring_bo)
2203 return;
2204
2205 if (esgs_ring_bo)
2206 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2207
2208 if (gsvs_ring_bo)
2209 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2210
2211 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2212 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2213 radeon_emit(cs, esgs_ring_size >> 8);
2214 radeon_emit(cs, gsvs_ring_size >> 8);
2215 } else {
2216 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2217 radeon_emit(cs, esgs_ring_size >> 8);
2218 radeon_emit(cs, gsvs_ring_size >> 8);
2219 }
2220 }
2221
2222 static void
2223 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2224 unsigned hs_offchip_param, unsigned tf_ring_size,
2225 struct radeon_winsys_bo *tess_rings_bo)
2226 {
2227 uint64_t tf_va;
2228
2229 if (!tess_rings_bo)
2230 return;
2231
2232 tf_va = radv_buffer_get_va(tess_rings_bo);
2233
2234 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2235
2236 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2237 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2238 S_030938_SIZE(tf_ring_size / 4));
2239 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2240 tf_va >> 8);
2241 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2242 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2243 S_030944_BASE_HI(tf_va >> 40));
2244 }
2245 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2246 hs_offchip_param);
2247 } else {
2248 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2249 S_008988_SIZE(tf_ring_size / 4));
2250 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2251 tf_va >> 8);
2252 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2253 hs_offchip_param);
2254 }
2255 }
2256
2257 static void
2258 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2259 struct radeon_winsys_bo *compute_scratch_bo)
2260 {
2261 uint64_t scratch_va;
2262
2263 if (!compute_scratch_bo)
2264 return;
2265
2266 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2267
2268 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2269
2270 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2271 radeon_emit(cs, scratch_va);
2272 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2273 S_008F04_SWIZZLE_ENABLE(1));
2274 }
2275
2276 static void
2277 radv_emit_global_shader_pointers(struct radv_queue *queue,
2278 struct radeon_cmdbuf *cs,
2279 struct radeon_winsys_bo *descriptor_bo)
2280 {
2281 uint64_t va;
2282
2283 if (!descriptor_bo)
2284 return;
2285
2286 va = radv_buffer_get_va(descriptor_bo);
2287
2288 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2289
2290 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2291 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2292 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2293 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2294 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2295
2296 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2297 radv_emit_shader_pointer(queue->device, cs, regs[i],
2298 va, true);
2299 }
2300 } else {
2301 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2302 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2303 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2304 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2305 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2306 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2307
2308 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2309 radv_emit_shader_pointer(queue->device, cs, regs[i],
2310 va, true);
2311 }
2312 }
2313 }
2314
2315 static void
2316 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2317 {
2318 struct radv_device *device = queue->device;
2319
2320 if (device->gfx_init) {
2321 uint64_t va = radv_buffer_get_va(device->gfx_init);
2322
2323 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2324 radeon_emit(cs, va);
2325 radeon_emit(cs, va >> 32);
2326 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2327
2328 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2329 } else {
2330 struct radv_physical_device *physical_device = device->physical_device;
2331 si_emit_graphics(physical_device, cs);
2332 }
2333 }
2334
2335 static void
2336 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2337 {
2338 struct radv_physical_device *physical_device = queue->device->physical_device;
2339 si_emit_compute(physical_device, cs);
2340 }
2341
2342 static VkResult
2343 radv_get_preamble_cs(struct radv_queue *queue,
2344 uint32_t scratch_size,
2345 uint32_t compute_scratch_size,
2346 uint32_t esgs_ring_size,
2347 uint32_t gsvs_ring_size,
2348 bool needs_tess_rings,
2349 bool needs_sample_positions,
2350 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2351 struct radeon_cmdbuf **initial_preamble_cs,
2352 struct radeon_cmdbuf **continue_preamble_cs)
2353 {
2354 struct radeon_winsys_bo *scratch_bo = NULL;
2355 struct radeon_winsys_bo *descriptor_bo = NULL;
2356 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2357 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2358 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2359 struct radeon_winsys_bo *tess_rings_bo = NULL;
2360 struct radeon_cmdbuf *dest_cs[3] = {0};
2361 bool add_tess_rings = false, add_sample_positions = false;
2362 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2363 unsigned max_offchip_buffers;
2364 unsigned hs_offchip_param = 0;
2365 unsigned tess_offchip_ring_offset;
2366 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2367 if (!queue->has_tess_rings) {
2368 if (needs_tess_rings)
2369 add_tess_rings = true;
2370 }
2371 if (!queue->has_sample_positions) {
2372 if (needs_sample_positions)
2373 add_sample_positions = true;
2374 }
2375 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2376 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2377 &max_offchip_buffers);
2378 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2379 tess_offchip_ring_size = max_offchip_buffers *
2380 queue->device->tess_offchip_block_dw_size * 4;
2381
2382 if (scratch_size <= queue->scratch_size &&
2383 compute_scratch_size <= queue->compute_scratch_size &&
2384 esgs_ring_size <= queue->esgs_ring_size &&
2385 gsvs_ring_size <= queue->gsvs_ring_size &&
2386 !add_tess_rings && !add_sample_positions &&
2387 queue->initial_preamble_cs) {
2388 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2389 *initial_preamble_cs = queue->initial_preamble_cs;
2390 *continue_preamble_cs = queue->continue_preamble_cs;
2391 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2392 *continue_preamble_cs = NULL;
2393 return VK_SUCCESS;
2394 }
2395
2396 if (scratch_size > queue->scratch_size) {
2397 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2398 scratch_size,
2399 4096,
2400 RADEON_DOMAIN_VRAM,
2401 ring_bo_flags,
2402 RADV_BO_PRIORITY_SCRATCH);
2403 if (!scratch_bo)
2404 goto fail;
2405 } else
2406 scratch_bo = queue->scratch_bo;
2407
2408 if (compute_scratch_size > queue->compute_scratch_size) {
2409 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2410 compute_scratch_size,
2411 4096,
2412 RADEON_DOMAIN_VRAM,
2413 ring_bo_flags,
2414 RADV_BO_PRIORITY_SCRATCH);
2415 if (!compute_scratch_bo)
2416 goto fail;
2417
2418 } else
2419 compute_scratch_bo = queue->compute_scratch_bo;
2420
2421 if (esgs_ring_size > queue->esgs_ring_size) {
2422 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2423 esgs_ring_size,
2424 4096,
2425 RADEON_DOMAIN_VRAM,
2426 ring_bo_flags,
2427 RADV_BO_PRIORITY_SCRATCH);
2428 if (!esgs_ring_bo)
2429 goto fail;
2430 } else {
2431 esgs_ring_bo = queue->esgs_ring_bo;
2432 esgs_ring_size = queue->esgs_ring_size;
2433 }
2434
2435 if (gsvs_ring_size > queue->gsvs_ring_size) {
2436 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2437 gsvs_ring_size,
2438 4096,
2439 RADEON_DOMAIN_VRAM,
2440 ring_bo_flags,
2441 RADV_BO_PRIORITY_SCRATCH);
2442 if (!gsvs_ring_bo)
2443 goto fail;
2444 } else {
2445 gsvs_ring_bo = queue->gsvs_ring_bo;
2446 gsvs_ring_size = queue->gsvs_ring_size;
2447 }
2448
2449 if (add_tess_rings) {
2450 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2451 tess_offchip_ring_offset + tess_offchip_ring_size,
2452 256,
2453 RADEON_DOMAIN_VRAM,
2454 ring_bo_flags,
2455 RADV_BO_PRIORITY_SCRATCH);
2456 if (!tess_rings_bo)
2457 goto fail;
2458 } else {
2459 tess_rings_bo = queue->tess_rings_bo;
2460 }
2461
2462 if (scratch_bo != queue->scratch_bo ||
2463 esgs_ring_bo != queue->esgs_ring_bo ||
2464 gsvs_ring_bo != queue->gsvs_ring_bo ||
2465 tess_rings_bo != queue->tess_rings_bo ||
2466 add_sample_positions) {
2467 uint32_t size = 0;
2468 if (gsvs_ring_bo || esgs_ring_bo ||
2469 tess_rings_bo || add_sample_positions) {
2470 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2471 if (add_sample_positions)
2472 size += 128; /* 64+32+16+8 = 120 bytes */
2473 }
2474 else if (scratch_bo)
2475 size = 8; /* 2 dword */
2476
2477 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2478 size,
2479 4096,
2480 RADEON_DOMAIN_VRAM,
2481 RADEON_FLAG_CPU_ACCESS |
2482 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2483 RADEON_FLAG_READ_ONLY,
2484 RADV_BO_PRIORITY_DESCRIPTOR);
2485 if (!descriptor_bo)
2486 goto fail;
2487 } else
2488 descriptor_bo = queue->descriptor_bo;
2489
2490 if (descriptor_bo != queue->descriptor_bo) {
2491 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2492
2493 if (scratch_bo) {
2494 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2495 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2496 S_008F04_SWIZZLE_ENABLE(1);
2497 map[0] = scratch_va;
2498 map[1] = rsrc1;
2499 }
2500
2501 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2502 fill_geom_tess_rings(queue, map, add_sample_positions,
2503 esgs_ring_size, esgs_ring_bo,
2504 gsvs_ring_size, gsvs_ring_bo,
2505 tess_factor_ring_size,
2506 tess_offchip_ring_offset,
2507 tess_offchip_ring_size,
2508 tess_rings_bo);
2509
2510 queue->device->ws->buffer_unmap(descriptor_bo);
2511 }
2512
2513 for(int i = 0; i < 3; ++i) {
2514 struct radeon_cmdbuf *cs = NULL;
2515 cs = queue->device->ws->cs_create(queue->device->ws,
2516 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2517 if (!cs)
2518 goto fail;
2519
2520 dest_cs[i] = cs;
2521
2522 if (scratch_bo)
2523 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2524
2525 /* Emit initial configuration. */
2526 switch (queue->queue_family_index) {
2527 case RADV_QUEUE_GENERAL:
2528 radv_init_graphics_state(cs, queue);
2529 break;
2530 case RADV_QUEUE_COMPUTE:
2531 radv_init_compute_state(cs, queue);
2532 break;
2533 case RADV_QUEUE_TRANSFER:
2534 break;
2535 }
2536
2537 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2538 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2539 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2540 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2541 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2542 }
2543
2544 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2545 gsvs_ring_bo, gsvs_ring_size);
2546 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2547 tess_factor_ring_size, tess_rings_bo);
2548 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2549 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2550
2551 if (i == 0) {
2552 si_cs_emit_cache_flush(cs,
2553 queue->device->physical_device->rad_info.chip_class,
2554 NULL, 0,
2555 queue->queue_family_index == RING_COMPUTE &&
2556 queue->device->physical_device->rad_info.chip_class >= CIK,
2557 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2558 RADV_CMD_FLAG_INV_ICACHE |
2559 RADV_CMD_FLAG_INV_SMEM_L1 |
2560 RADV_CMD_FLAG_INV_VMEM_L1 |
2561 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2562 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2563 } else if (i == 1) {
2564 si_cs_emit_cache_flush(cs,
2565 queue->device->physical_device->rad_info.chip_class,
2566 NULL, 0,
2567 queue->queue_family_index == RING_COMPUTE &&
2568 queue->device->physical_device->rad_info.chip_class >= CIK,
2569 RADV_CMD_FLAG_INV_ICACHE |
2570 RADV_CMD_FLAG_INV_SMEM_L1 |
2571 RADV_CMD_FLAG_INV_VMEM_L1 |
2572 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2573 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2574 }
2575
2576 if (!queue->device->ws->cs_finalize(cs))
2577 goto fail;
2578 }
2579
2580 if (queue->initial_full_flush_preamble_cs)
2581 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2582
2583 if (queue->initial_preamble_cs)
2584 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2585
2586 if (queue->continue_preamble_cs)
2587 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2588
2589 queue->initial_full_flush_preamble_cs = dest_cs[0];
2590 queue->initial_preamble_cs = dest_cs[1];
2591 queue->continue_preamble_cs = dest_cs[2];
2592
2593 if (scratch_bo != queue->scratch_bo) {
2594 if (queue->scratch_bo)
2595 queue->device->ws->buffer_destroy(queue->scratch_bo);
2596 queue->scratch_bo = scratch_bo;
2597 queue->scratch_size = scratch_size;
2598 }
2599
2600 if (compute_scratch_bo != queue->compute_scratch_bo) {
2601 if (queue->compute_scratch_bo)
2602 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2603 queue->compute_scratch_bo = compute_scratch_bo;
2604 queue->compute_scratch_size = compute_scratch_size;
2605 }
2606
2607 if (esgs_ring_bo != queue->esgs_ring_bo) {
2608 if (queue->esgs_ring_bo)
2609 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2610 queue->esgs_ring_bo = esgs_ring_bo;
2611 queue->esgs_ring_size = esgs_ring_size;
2612 }
2613
2614 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2615 if (queue->gsvs_ring_bo)
2616 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2617 queue->gsvs_ring_bo = gsvs_ring_bo;
2618 queue->gsvs_ring_size = gsvs_ring_size;
2619 }
2620
2621 if (tess_rings_bo != queue->tess_rings_bo) {
2622 queue->tess_rings_bo = tess_rings_bo;
2623 queue->has_tess_rings = true;
2624 }
2625
2626 if (descriptor_bo != queue->descriptor_bo) {
2627 if (queue->descriptor_bo)
2628 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2629
2630 queue->descriptor_bo = descriptor_bo;
2631 }
2632
2633 if (add_sample_positions)
2634 queue->has_sample_positions = true;
2635
2636 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2637 *initial_preamble_cs = queue->initial_preamble_cs;
2638 *continue_preamble_cs = queue->continue_preamble_cs;
2639 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2640 *continue_preamble_cs = NULL;
2641 return VK_SUCCESS;
2642 fail:
2643 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2644 if (dest_cs[i])
2645 queue->device->ws->cs_destroy(dest_cs[i]);
2646 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2647 queue->device->ws->buffer_destroy(descriptor_bo);
2648 if (scratch_bo && scratch_bo != queue->scratch_bo)
2649 queue->device->ws->buffer_destroy(scratch_bo);
2650 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2651 queue->device->ws->buffer_destroy(compute_scratch_bo);
2652 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2653 queue->device->ws->buffer_destroy(esgs_ring_bo);
2654 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2655 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2656 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2657 queue->device->ws->buffer_destroy(tess_rings_bo);
2658 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2659 }
2660
2661 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2662 struct radv_winsys_sem_counts *counts,
2663 int num_sems,
2664 const VkSemaphore *sems,
2665 VkFence _fence,
2666 bool reset_temp)
2667 {
2668 int syncobj_idx = 0, sem_idx = 0;
2669
2670 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2671 return VK_SUCCESS;
2672
2673 for (uint32_t i = 0; i < num_sems; i++) {
2674 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2675
2676 if (sem->temp_syncobj || sem->syncobj)
2677 counts->syncobj_count++;
2678 else
2679 counts->sem_count++;
2680 }
2681
2682 if (_fence != VK_NULL_HANDLE) {
2683 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2684 if (fence->temp_syncobj || fence->syncobj)
2685 counts->syncobj_count++;
2686 }
2687
2688 if (counts->syncobj_count) {
2689 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2690 if (!counts->syncobj)
2691 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2692 }
2693
2694 if (counts->sem_count) {
2695 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2696 if (!counts->sem) {
2697 free(counts->syncobj);
2698 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2699 }
2700 }
2701
2702 for (uint32_t i = 0; i < num_sems; i++) {
2703 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2704
2705 if (sem->temp_syncobj) {
2706 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2707 }
2708 else if (sem->syncobj)
2709 counts->syncobj[syncobj_idx++] = sem->syncobj;
2710 else {
2711 assert(sem->sem);
2712 counts->sem[sem_idx++] = sem->sem;
2713 }
2714 }
2715
2716 if (_fence != VK_NULL_HANDLE) {
2717 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2718 if (fence->temp_syncobj)
2719 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2720 else if (fence->syncobj)
2721 counts->syncobj[syncobj_idx++] = fence->syncobj;
2722 }
2723
2724 return VK_SUCCESS;
2725 }
2726
2727 static void
2728 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2729 {
2730 free(sem_info->wait.syncobj);
2731 free(sem_info->wait.sem);
2732 free(sem_info->signal.syncobj);
2733 free(sem_info->signal.sem);
2734 }
2735
2736
2737 static void radv_free_temp_syncobjs(struct radv_device *device,
2738 int num_sems,
2739 const VkSemaphore *sems)
2740 {
2741 for (uint32_t i = 0; i < num_sems; i++) {
2742 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2743
2744 if (sem->temp_syncobj) {
2745 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2746 sem->temp_syncobj = 0;
2747 }
2748 }
2749 }
2750
2751 static VkResult
2752 radv_alloc_sem_info(struct radv_instance *instance,
2753 struct radv_winsys_sem_info *sem_info,
2754 int num_wait_sems,
2755 const VkSemaphore *wait_sems,
2756 int num_signal_sems,
2757 const VkSemaphore *signal_sems,
2758 VkFence fence)
2759 {
2760 VkResult ret;
2761 memset(sem_info, 0, sizeof(*sem_info));
2762
2763 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2764 if (ret)
2765 return ret;
2766 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2767 if (ret)
2768 radv_free_sem_info(sem_info);
2769
2770 /* caller can override these */
2771 sem_info->cs_emit_wait = true;
2772 sem_info->cs_emit_signal = true;
2773 return ret;
2774 }
2775
2776 /* Signals fence as soon as all the work currently put on queue is done. */
2777 static VkResult radv_signal_fence(struct radv_queue *queue,
2778 struct radv_fence *fence)
2779 {
2780 int ret;
2781 VkResult result;
2782 struct radv_winsys_sem_info sem_info;
2783
2784 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2785 radv_fence_to_handle(fence));
2786 if (result != VK_SUCCESS)
2787 return result;
2788
2789 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2790 &queue->device->empty_cs[queue->queue_family_index],
2791 1, NULL, NULL, &sem_info, NULL,
2792 false, fence->fence);
2793 radv_free_sem_info(&sem_info);
2794
2795 if (ret)
2796 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2797
2798 return VK_SUCCESS;
2799 }
2800
2801 VkResult radv_QueueSubmit(
2802 VkQueue _queue,
2803 uint32_t submitCount,
2804 const VkSubmitInfo* pSubmits,
2805 VkFence _fence)
2806 {
2807 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2808 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2809 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2810 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2811 int ret;
2812 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2813 uint32_t scratch_size = 0;
2814 uint32_t compute_scratch_size = 0;
2815 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2816 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2817 VkResult result;
2818 bool fence_emitted = false;
2819 bool tess_rings_needed = false;
2820 bool sample_positions_needed = false;
2821
2822 /* Do this first so failing to allocate scratch buffers can't result in
2823 * partially executed submissions. */
2824 for (uint32_t i = 0; i < submitCount; i++) {
2825 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2826 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2827 pSubmits[i].pCommandBuffers[j]);
2828
2829 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2830 compute_scratch_size = MAX2(compute_scratch_size,
2831 cmd_buffer->compute_scratch_size_needed);
2832 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2833 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2834 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2835 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2836 }
2837 }
2838
2839 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2840 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2841 sample_positions_needed, &initial_flush_preamble_cs,
2842 &initial_preamble_cs, &continue_preamble_cs);
2843 if (result != VK_SUCCESS)
2844 return result;
2845
2846 for (uint32_t i = 0; i < submitCount; i++) {
2847 struct radeon_cmdbuf **cs_array;
2848 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2849 bool can_patch = true;
2850 uint32_t advance;
2851 struct radv_winsys_sem_info sem_info;
2852
2853 result = radv_alloc_sem_info(queue->device->instance,
2854 &sem_info,
2855 pSubmits[i].waitSemaphoreCount,
2856 pSubmits[i].pWaitSemaphores,
2857 pSubmits[i].signalSemaphoreCount,
2858 pSubmits[i].pSignalSemaphores,
2859 _fence);
2860 if (result != VK_SUCCESS)
2861 return result;
2862
2863 if (!pSubmits[i].commandBufferCount) {
2864 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2865 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2866 &queue->device->empty_cs[queue->queue_family_index],
2867 1, NULL, NULL,
2868 &sem_info, NULL,
2869 false, base_fence);
2870 if (ret) {
2871 radv_loge("failed to submit CS %d\n", i);
2872 abort();
2873 }
2874 fence_emitted = true;
2875 }
2876 radv_free_sem_info(&sem_info);
2877 continue;
2878 }
2879
2880 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2881 (pSubmits[i].commandBufferCount));
2882
2883 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2884 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2885 pSubmits[i].pCommandBuffers[j]);
2886 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2887
2888 cs_array[j] = cmd_buffer->cs;
2889 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2890 can_patch = false;
2891
2892 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2893 }
2894
2895 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2896 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2897 const struct radv_winsys_bo_list *bo_list = NULL;
2898
2899 advance = MIN2(max_cs_submission,
2900 pSubmits[i].commandBufferCount - j);
2901
2902 if (queue->device->trace_bo)
2903 *queue->device->trace_id_ptr = 0;
2904
2905 sem_info.cs_emit_wait = j == 0;
2906 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2907
2908 if (unlikely(queue->device->use_global_bo_list)) {
2909 pthread_mutex_lock(&queue->device->bo_list.mutex);
2910 bo_list = &queue->device->bo_list.list;
2911 }
2912
2913 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2914 advance, initial_preamble, continue_preamble_cs,
2915 &sem_info, bo_list,
2916 can_patch, base_fence);
2917
2918 if (unlikely(queue->device->use_global_bo_list))
2919 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2920
2921 if (ret) {
2922 radv_loge("failed to submit CS %d\n", i);
2923 abort();
2924 }
2925 fence_emitted = true;
2926 if (queue->device->trace_bo) {
2927 radv_check_gpu_hangs(queue, cs_array[j]);
2928 }
2929 }
2930
2931 radv_free_temp_syncobjs(queue->device,
2932 pSubmits[i].waitSemaphoreCount,
2933 pSubmits[i].pWaitSemaphores);
2934 radv_free_sem_info(&sem_info);
2935 free(cs_array);
2936 }
2937
2938 if (fence) {
2939 if (!fence_emitted) {
2940 result = radv_signal_fence(queue, fence);
2941 if (result != VK_SUCCESS)
2942 return result;
2943 }
2944 fence->submitted = true;
2945 }
2946
2947 return VK_SUCCESS;
2948 }
2949
2950 VkResult radv_QueueWaitIdle(
2951 VkQueue _queue)
2952 {
2953 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2954
2955 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2956 radv_queue_family_to_ring(queue->queue_family_index),
2957 queue->queue_idx);
2958 return VK_SUCCESS;
2959 }
2960
2961 VkResult radv_DeviceWaitIdle(
2962 VkDevice _device)
2963 {
2964 RADV_FROM_HANDLE(radv_device, device, _device);
2965
2966 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2967 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2968 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2969 }
2970 }
2971 return VK_SUCCESS;
2972 }
2973
2974 VkResult radv_EnumerateInstanceExtensionProperties(
2975 const char* pLayerName,
2976 uint32_t* pPropertyCount,
2977 VkExtensionProperties* pProperties)
2978 {
2979 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2980
2981 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2982 if (radv_supported_instance_extensions.extensions[i]) {
2983 vk_outarray_append(&out, prop) {
2984 *prop = radv_instance_extensions[i];
2985 }
2986 }
2987 }
2988
2989 return vk_outarray_status(&out);
2990 }
2991
2992 VkResult radv_EnumerateDeviceExtensionProperties(
2993 VkPhysicalDevice physicalDevice,
2994 const char* pLayerName,
2995 uint32_t* pPropertyCount,
2996 VkExtensionProperties* pProperties)
2997 {
2998 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2999 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3000
3001 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3002 if (device->supported_extensions.extensions[i]) {
3003 vk_outarray_append(&out, prop) {
3004 *prop = radv_device_extensions[i];
3005 }
3006 }
3007 }
3008
3009 return vk_outarray_status(&out);
3010 }
3011
3012 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3013 VkInstance _instance,
3014 const char* pName)
3015 {
3016 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3017
3018 return radv_lookup_entrypoint_checked(pName,
3019 instance ? instance->apiVersion : 0,
3020 instance ? &instance->enabled_extensions : NULL,
3021 NULL);
3022 }
3023
3024 /* The loader wants us to expose a second GetInstanceProcAddr function
3025 * to work around certain LD_PRELOAD issues seen in apps.
3026 */
3027 PUBLIC
3028 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3029 VkInstance instance,
3030 const char* pName);
3031
3032 PUBLIC
3033 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3034 VkInstance instance,
3035 const char* pName)
3036 {
3037 return radv_GetInstanceProcAddr(instance, pName);
3038 }
3039
3040 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3041 VkDevice _device,
3042 const char* pName)
3043 {
3044 RADV_FROM_HANDLE(radv_device, device, _device);
3045
3046 return radv_lookup_entrypoint_checked(pName,
3047 device->instance->apiVersion,
3048 &device->instance->enabled_extensions,
3049 &device->enabled_extensions);
3050 }
3051
3052 bool radv_get_memory_fd(struct radv_device *device,
3053 struct radv_device_memory *memory,
3054 int *pFD)
3055 {
3056 struct radeon_bo_metadata metadata;
3057
3058 if (memory->image) {
3059 radv_init_metadata(device, memory->image, &metadata);
3060 device->ws->buffer_set_metadata(memory->bo, &metadata);
3061 }
3062
3063 return device->ws->buffer_get_fd(device->ws, memory->bo,
3064 pFD);
3065 }
3066
3067 static VkResult radv_alloc_memory(struct radv_device *device,
3068 const VkMemoryAllocateInfo* pAllocateInfo,
3069 const VkAllocationCallbacks* pAllocator,
3070 VkDeviceMemory* pMem)
3071 {
3072 struct radv_device_memory *mem;
3073 VkResult result;
3074 enum radeon_bo_domain domain;
3075 uint32_t flags = 0;
3076 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3077
3078 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3079
3080 if (pAllocateInfo->allocationSize == 0) {
3081 /* Apparently, this is allowed */
3082 *pMem = VK_NULL_HANDLE;
3083 return VK_SUCCESS;
3084 }
3085
3086 const VkImportMemoryFdInfoKHR *import_info =
3087 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3088 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3089 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3090 const VkExportMemoryAllocateInfo *export_info =
3091 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3092 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3093 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3094
3095 const struct wsi_memory_allocate_info *wsi_info =
3096 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3097
3098 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3099 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3100 if (mem == NULL)
3101 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3102
3103 if (wsi_info && wsi_info->implicit_sync)
3104 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3105
3106 if (dedicate_info) {
3107 mem->image = radv_image_from_handle(dedicate_info->image);
3108 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3109 } else {
3110 mem->image = NULL;
3111 mem->buffer = NULL;
3112 }
3113
3114 float priority_float = 0.5;
3115 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3116 vk_find_struct_const(pAllocateInfo->pNext,
3117 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3118 if (priority_ext)
3119 priority_float = priority_ext->priority;
3120
3121 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3122 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3123
3124 mem->user_ptr = NULL;
3125
3126 if (import_info) {
3127 assert(import_info->handleType ==
3128 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3129 import_info->handleType ==
3130 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3131 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3132 priority, NULL, NULL);
3133 if (!mem->bo) {
3134 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3135 goto fail;
3136 } else {
3137 close(import_info->fd);
3138 }
3139 } else if (host_ptr_info) {
3140 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3141 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3142 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3143 pAllocateInfo->allocationSize,
3144 priority);
3145 if (!mem->bo) {
3146 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3147 goto fail;
3148 } else {
3149 mem->user_ptr = host_ptr_info->pHostPointer;
3150 }
3151 } else {
3152 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3153 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3154 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3155 domain = RADEON_DOMAIN_GTT;
3156 else
3157 domain = RADEON_DOMAIN_VRAM;
3158
3159 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3160 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3161 else
3162 flags |= RADEON_FLAG_CPU_ACCESS;
3163
3164 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3165 flags |= RADEON_FLAG_GTT_WC;
3166
3167 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3168 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3169
3170 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3171 domain, flags, priority);
3172
3173 if (!mem->bo) {
3174 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3175 goto fail;
3176 }
3177 mem->type_index = mem_type_index;
3178 }
3179
3180 result = radv_bo_list_add(device, mem->bo);
3181 if (result != VK_SUCCESS)
3182 goto fail_bo;
3183
3184 *pMem = radv_device_memory_to_handle(mem);
3185
3186 return VK_SUCCESS;
3187
3188 fail_bo:
3189 device->ws->buffer_destroy(mem->bo);
3190 fail:
3191 vk_free2(&device->alloc, pAllocator, mem);
3192
3193 return result;
3194 }
3195
3196 VkResult radv_AllocateMemory(
3197 VkDevice _device,
3198 const VkMemoryAllocateInfo* pAllocateInfo,
3199 const VkAllocationCallbacks* pAllocator,
3200 VkDeviceMemory* pMem)
3201 {
3202 RADV_FROM_HANDLE(radv_device, device, _device);
3203 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3204 }
3205
3206 void radv_FreeMemory(
3207 VkDevice _device,
3208 VkDeviceMemory _mem,
3209 const VkAllocationCallbacks* pAllocator)
3210 {
3211 RADV_FROM_HANDLE(radv_device, device, _device);
3212 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3213
3214 if (mem == NULL)
3215 return;
3216
3217 radv_bo_list_remove(device, mem->bo);
3218 device->ws->buffer_destroy(mem->bo);
3219 mem->bo = NULL;
3220
3221 vk_free2(&device->alloc, pAllocator, mem);
3222 }
3223
3224 VkResult radv_MapMemory(
3225 VkDevice _device,
3226 VkDeviceMemory _memory,
3227 VkDeviceSize offset,
3228 VkDeviceSize size,
3229 VkMemoryMapFlags flags,
3230 void** ppData)
3231 {
3232 RADV_FROM_HANDLE(radv_device, device, _device);
3233 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3234
3235 if (mem == NULL) {
3236 *ppData = NULL;
3237 return VK_SUCCESS;
3238 }
3239
3240 if (mem->user_ptr)
3241 *ppData = mem->user_ptr;
3242 else
3243 *ppData = device->ws->buffer_map(mem->bo);
3244
3245 if (*ppData) {
3246 *ppData += offset;
3247 return VK_SUCCESS;
3248 }
3249
3250 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3251 }
3252
3253 void radv_UnmapMemory(
3254 VkDevice _device,
3255 VkDeviceMemory _memory)
3256 {
3257 RADV_FROM_HANDLE(radv_device, device, _device);
3258 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3259
3260 if (mem == NULL)
3261 return;
3262
3263 if (mem->user_ptr == NULL)
3264 device->ws->buffer_unmap(mem->bo);
3265 }
3266
3267 VkResult radv_FlushMappedMemoryRanges(
3268 VkDevice _device,
3269 uint32_t memoryRangeCount,
3270 const VkMappedMemoryRange* pMemoryRanges)
3271 {
3272 return VK_SUCCESS;
3273 }
3274
3275 VkResult radv_InvalidateMappedMemoryRanges(
3276 VkDevice _device,
3277 uint32_t memoryRangeCount,
3278 const VkMappedMemoryRange* pMemoryRanges)
3279 {
3280 return VK_SUCCESS;
3281 }
3282
3283 void radv_GetBufferMemoryRequirements(
3284 VkDevice _device,
3285 VkBuffer _buffer,
3286 VkMemoryRequirements* pMemoryRequirements)
3287 {
3288 RADV_FROM_HANDLE(radv_device, device, _device);
3289 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3290
3291 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3292
3293 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3294 pMemoryRequirements->alignment = 4096;
3295 else
3296 pMemoryRequirements->alignment = 16;
3297
3298 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3299 }
3300
3301 void radv_GetBufferMemoryRequirements2(
3302 VkDevice device,
3303 const VkBufferMemoryRequirementsInfo2 *pInfo,
3304 VkMemoryRequirements2 *pMemoryRequirements)
3305 {
3306 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3307 &pMemoryRequirements->memoryRequirements);
3308 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3309 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3310 switch (ext->sType) {
3311 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3312 VkMemoryDedicatedRequirements *req =
3313 (VkMemoryDedicatedRequirements *) ext;
3314 req->requiresDedicatedAllocation = buffer->shareable;
3315 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3316 break;
3317 }
3318 default:
3319 break;
3320 }
3321 }
3322 }
3323
3324 void radv_GetImageMemoryRequirements(
3325 VkDevice _device,
3326 VkImage _image,
3327 VkMemoryRequirements* pMemoryRequirements)
3328 {
3329 RADV_FROM_HANDLE(radv_device, device, _device);
3330 RADV_FROM_HANDLE(radv_image, image, _image);
3331
3332 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3333
3334 pMemoryRequirements->size = image->size;
3335 pMemoryRequirements->alignment = image->alignment;
3336 }
3337
3338 void radv_GetImageMemoryRequirements2(
3339 VkDevice device,
3340 const VkImageMemoryRequirementsInfo2 *pInfo,
3341 VkMemoryRequirements2 *pMemoryRequirements)
3342 {
3343 radv_GetImageMemoryRequirements(device, pInfo->image,
3344 &pMemoryRequirements->memoryRequirements);
3345
3346 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3347
3348 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3349 switch (ext->sType) {
3350 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3351 VkMemoryDedicatedRequirements *req =
3352 (VkMemoryDedicatedRequirements *) ext;
3353 req->requiresDedicatedAllocation = image->shareable;
3354 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3355 break;
3356 }
3357 default:
3358 break;
3359 }
3360 }
3361 }
3362
3363 void radv_GetImageSparseMemoryRequirements(
3364 VkDevice device,
3365 VkImage image,
3366 uint32_t* pSparseMemoryRequirementCount,
3367 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3368 {
3369 stub();
3370 }
3371
3372 void radv_GetImageSparseMemoryRequirements2(
3373 VkDevice device,
3374 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3375 uint32_t* pSparseMemoryRequirementCount,
3376 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3377 {
3378 stub();
3379 }
3380
3381 void radv_GetDeviceMemoryCommitment(
3382 VkDevice device,
3383 VkDeviceMemory memory,
3384 VkDeviceSize* pCommittedMemoryInBytes)
3385 {
3386 *pCommittedMemoryInBytes = 0;
3387 }
3388
3389 VkResult radv_BindBufferMemory2(VkDevice device,
3390 uint32_t bindInfoCount,
3391 const VkBindBufferMemoryInfo *pBindInfos)
3392 {
3393 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3394 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3395 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3396
3397 if (mem) {
3398 buffer->bo = mem->bo;
3399 buffer->offset = pBindInfos[i].memoryOffset;
3400 } else {
3401 buffer->bo = NULL;
3402 }
3403 }
3404 return VK_SUCCESS;
3405 }
3406
3407 VkResult radv_BindBufferMemory(
3408 VkDevice device,
3409 VkBuffer buffer,
3410 VkDeviceMemory memory,
3411 VkDeviceSize memoryOffset)
3412 {
3413 const VkBindBufferMemoryInfo info = {
3414 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3415 .buffer = buffer,
3416 .memory = memory,
3417 .memoryOffset = memoryOffset
3418 };
3419
3420 return radv_BindBufferMemory2(device, 1, &info);
3421 }
3422
3423 VkResult radv_BindImageMemory2(VkDevice device,
3424 uint32_t bindInfoCount,
3425 const VkBindImageMemoryInfo *pBindInfos)
3426 {
3427 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3428 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3429 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3430
3431 if (mem) {
3432 image->bo = mem->bo;
3433 image->offset = pBindInfos[i].memoryOffset;
3434 } else {
3435 image->bo = NULL;
3436 image->offset = 0;
3437 }
3438 }
3439 return VK_SUCCESS;
3440 }
3441
3442
3443 VkResult radv_BindImageMemory(
3444 VkDevice device,
3445 VkImage image,
3446 VkDeviceMemory memory,
3447 VkDeviceSize memoryOffset)
3448 {
3449 const VkBindImageMemoryInfo info = {
3450 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3451 .image = image,
3452 .memory = memory,
3453 .memoryOffset = memoryOffset
3454 };
3455
3456 return radv_BindImageMemory2(device, 1, &info);
3457 }
3458
3459
3460 static void
3461 radv_sparse_buffer_bind_memory(struct radv_device *device,
3462 const VkSparseBufferMemoryBindInfo *bind)
3463 {
3464 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3465
3466 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3467 struct radv_device_memory *mem = NULL;
3468
3469 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3470 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3471
3472 device->ws->buffer_virtual_bind(buffer->bo,
3473 bind->pBinds[i].resourceOffset,
3474 bind->pBinds[i].size,
3475 mem ? mem->bo : NULL,
3476 bind->pBinds[i].memoryOffset);
3477 }
3478 }
3479
3480 static void
3481 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3482 const VkSparseImageOpaqueMemoryBindInfo *bind)
3483 {
3484 RADV_FROM_HANDLE(radv_image, image, bind->image);
3485
3486 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3487 struct radv_device_memory *mem = NULL;
3488
3489 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3490 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3491
3492 device->ws->buffer_virtual_bind(image->bo,
3493 bind->pBinds[i].resourceOffset,
3494 bind->pBinds[i].size,
3495 mem ? mem->bo : NULL,
3496 bind->pBinds[i].memoryOffset);
3497 }
3498 }
3499
3500 VkResult radv_QueueBindSparse(
3501 VkQueue _queue,
3502 uint32_t bindInfoCount,
3503 const VkBindSparseInfo* pBindInfo,
3504 VkFence _fence)
3505 {
3506 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3507 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3508 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3509 bool fence_emitted = false;
3510 VkResult result;
3511 int ret;
3512
3513 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3514 struct radv_winsys_sem_info sem_info;
3515 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3516 radv_sparse_buffer_bind_memory(queue->device,
3517 pBindInfo[i].pBufferBinds + j);
3518 }
3519
3520 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3521 radv_sparse_image_opaque_bind_memory(queue->device,
3522 pBindInfo[i].pImageOpaqueBinds + j);
3523 }
3524
3525 VkResult result;
3526 result = radv_alloc_sem_info(queue->device->instance,
3527 &sem_info,
3528 pBindInfo[i].waitSemaphoreCount,
3529 pBindInfo[i].pWaitSemaphores,
3530 pBindInfo[i].signalSemaphoreCount,
3531 pBindInfo[i].pSignalSemaphores,
3532 _fence);
3533 if (result != VK_SUCCESS)
3534 return result;
3535
3536 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3537 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3538 &queue->device->empty_cs[queue->queue_family_index],
3539 1, NULL, NULL,
3540 &sem_info, NULL,
3541 false, base_fence);
3542 if (ret) {
3543 radv_loge("failed to submit CS %d\n", i);
3544 abort();
3545 }
3546
3547 fence_emitted = true;
3548 if (fence)
3549 fence->submitted = true;
3550 }
3551
3552 radv_free_sem_info(&sem_info);
3553
3554 }
3555
3556 if (fence) {
3557 if (!fence_emitted) {
3558 result = radv_signal_fence(queue, fence);
3559 if (result != VK_SUCCESS)
3560 return result;
3561 }
3562 fence->submitted = true;
3563 }
3564
3565 return VK_SUCCESS;
3566 }
3567
3568 VkResult radv_CreateFence(
3569 VkDevice _device,
3570 const VkFenceCreateInfo* pCreateInfo,
3571 const VkAllocationCallbacks* pAllocator,
3572 VkFence* pFence)
3573 {
3574 RADV_FROM_HANDLE(radv_device, device, _device);
3575 const VkExportFenceCreateInfo *export =
3576 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3577 VkExternalFenceHandleTypeFlags handleTypes =
3578 export ? export->handleTypes : 0;
3579
3580 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3581 sizeof(*fence), 8,
3582 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3583
3584 if (!fence)
3585 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3586
3587 fence->fence_wsi = NULL;
3588 fence->submitted = false;
3589 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3590 fence->temp_syncobj = 0;
3591 if (device->always_use_syncobj || handleTypes) {
3592 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3593 if (ret) {
3594 vk_free2(&device->alloc, pAllocator, fence);
3595 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3596 }
3597 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3598 device->ws->signal_syncobj(device->ws, fence->syncobj);
3599 }
3600 fence->fence = NULL;
3601 } else {
3602 fence->fence = device->ws->create_fence();
3603 if (!fence->fence) {
3604 vk_free2(&device->alloc, pAllocator, fence);
3605 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3606 }
3607 fence->syncobj = 0;
3608 }
3609
3610 *pFence = radv_fence_to_handle(fence);
3611
3612 return VK_SUCCESS;
3613 }
3614
3615 void radv_DestroyFence(
3616 VkDevice _device,
3617 VkFence _fence,
3618 const VkAllocationCallbacks* pAllocator)
3619 {
3620 RADV_FROM_HANDLE(radv_device, device, _device);
3621 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3622
3623 if (!fence)
3624 return;
3625
3626 if (fence->temp_syncobj)
3627 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3628 if (fence->syncobj)
3629 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3630 if (fence->fence)
3631 device->ws->destroy_fence(fence->fence);
3632 if (fence->fence_wsi)
3633 fence->fence_wsi->destroy(fence->fence_wsi);
3634 vk_free2(&device->alloc, pAllocator, fence);
3635 }
3636
3637
3638 static uint64_t radv_get_current_time()
3639 {
3640 struct timespec tv;
3641 clock_gettime(CLOCK_MONOTONIC, &tv);
3642 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3643 }
3644
3645 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3646 {
3647 uint64_t current_time = radv_get_current_time();
3648
3649 timeout = MIN2(UINT64_MAX - current_time, timeout);
3650
3651 return current_time + timeout;
3652 }
3653
3654
3655 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3656 {
3657 for (uint32_t i = 0; i < fenceCount; ++i) {
3658 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3659 if (fence->fence == NULL || fence->syncobj ||
3660 fence->temp_syncobj ||
3661 (!fence->signalled && !fence->submitted))
3662 return false;
3663 }
3664 return true;
3665 }
3666
3667 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3668 {
3669 for (uint32_t i = 0; i < fenceCount; ++i) {
3670 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3671 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3672 return false;
3673 }
3674 return true;
3675 }
3676
3677 VkResult radv_WaitForFences(
3678 VkDevice _device,
3679 uint32_t fenceCount,
3680 const VkFence* pFences,
3681 VkBool32 waitAll,
3682 uint64_t timeout)
3683 {
3684 RADV_FROM_HANDLE(radv_device, device, _device);
3685 timeout = radv_get_absolute_timeout(timeout);
3686
3687 if (device->always_use_syncobj &&
3688 radv_all_fences_syncobj(fenceCount, pFences))
3689 {
3690 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3691 if (!handles)
3692 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3693
3694 for (uint32_t i = 0; i < fenceCount; ++i) {
3695 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3696 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3697 }
3698
3699 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3700
3701 free(handles);
3702 return success ? VK_SUCCESS : VK_TIMEOUT;
3703 }
3704
3705 if (!waitAll && fenceCount > 1) {
3706 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3707 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3708 uint32_t wait_count = 0;
3709 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3710 if (!fences)
3711 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3712
3713 for (uint32_t i = 0; i < fenceCount; ++i) {
3714 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3715
3716 if (fence->signalled) {
3717 free(fences);
3718 return VK_SUCCESS;
3719 }
3720
3721 fences[wait_count++] = fence->fence;
3722 }
3723
3724 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3725 waitAll, timeout - radv_get_current_time());
3726
3727 free(fences);
3728 return success ? VK_SUCCESS : VK_TIMEOUT;
3729 }
3730
3731 while(radv_get_current_time() <= timeout) {
3732 for (uint32_t i = 0; i < fenceCount; ++i) {
3733 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3734 return VK_SUCCESS;
3735 }
3736 }
3737 return VK_TIMEOUT;
3738 }
3739
3740 for (uint32_t i = 0; i < fenceCount; ++i) {
3741 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3742 bool expired = false;
3743
3744 if (fence->temp_syncobj) {
3745 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3746 return VK_TIMEOUT;
3747 continue;
3748 }
3749
3750 if (fence->syncobj) {
3751 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3752 return VK_TIMEOUT;
3753 continue;
3754 }
3755
3756 if (fence->signalled)
3757 continue;
3758
3759 if (fence->fence) {
3760 if (!fence->submitted) {
3761 while(radv_get_current_time() <= timeout &&
3762 !fence->submitted)
3763 /* Do nothing */;
3764
3765 if (!fence->submitted)
3766 return VK_TIMEOUT;
3767
3768 /* Recheck as it may have been set by
3769 * submitting operations. */
3770
3771 if (fence->signalled)
3772 continue;
3773 }
3774
3775 expired = device->ws->fence_wait(device->ws,
3776 fence->fence,
3777 true, timeout);
3778 if (!expired)
3779 return VK_TIMEOUT;
3780 }
3781
3782 if (fence->fence_wsi) {
3783 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3784 if (result != VK_SUCCESS)
3785 return result;
3786 }
3787
3788 fence->signalled = true;
3789 }
3790
3791 return VK_SUCCESS;
3792 }
3793
3794 VkResult radv_ResetFences(VkDevice _device,
3795 uint32_t fenceCount,
3796 const VkFence *pFences)
3797 {
3798 RADV_FROM_HANDLE(radv_device, device, _device);
3799
3800 for (unsigned i = 0; i < fenceCount; ++i) {
3801 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3802 fence->submitted = fence->signalled = false;
3803
3804 /* Per spec, we first restore the permanent payload, and then reset, so
3805 * having a temp syncobj should not skip resetting the permanent syncobj. */
3806 if (fence->temp_syncobj) {
3807 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3808 fence->temp_syncobj = 0;
3809 }
3810
3811 if (fence->syncobj) {
3812 device->ws->reset_syncobj(device->ws, fence->syncobj);
3813 }
3814 }
3815
3816 return VK_SUCCESS;
3817 }
3818
3819 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3820 {
3821 RADV_FROM_HANDLE(radv_device, device, _device);
3822 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3823
3824 if (fence->temp_syncobj) {
3825 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3826 return success ? VK_SUCCESS : VK_NOT_READY;
3827 }
3828
3829 if (fence->syncobj) {
3830 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3831 return success ? VK_SUCCESS : VK_NOT_READY;
3832 }
3833
3834 if (fence->signalled)
3835 return VK_SUCCESS;
3836 if (!fence->submitted)
3837 return VK_NOT_READY;
3838 if (fence->fence) {
3839 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3840 return VK_NOT_READY;
3841 }
3842 if (fence->fence_wsi) {
3843 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3844
3845 if (result != VK_SUCCESS) {
3846 if (result == VK_TIMEOUT)
3847 return VK_NOT_READY;
3848 return result;
3849 }
3850 }
3851 return VK_SUCCESS;
3852 }
3853
3854
3855 // Queue semaphore functions
3856
3857 VkResult radv_CreateSemaphore(
3858 VkDevice _device,
3859 const VkSemaphoreCreateInfo* pCreateInfo,
3860 const VkAllocationCallbacks* pAllocator,
3861 VkSemaphore* pSemaphore)
3862 {
3863 RADV_FROM_HANDLE(radv_device, device, _device);
3864 const VkExportSemaphoreCreateInfo *export =
3865 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3866 VkExternalSemaphoreHandleTypeFlags handleTypes =
3867 export ? export->handleTypes : 0;
3868
3869 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3870 sizeof(*sem), 8,
3871 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3872 if (!sem)
3873 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3874
3875 sem->temp_syncobj = 0;
3876 /* create a syncobject if we are going to export this semaphore */
3877 if (device->always_use_syncobj || handleTypes) {
3878 assert (device->physical_device->rad_info.has_syncobj);
3879 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3880 if (ret) {
3881 vk_free2(&device->alloc, pAllocator, sem);
3882 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3883 }
3884 sem->sem = NULL;
3885 } else {
3886 sem->sem = device->ws->create_sem(device->ws);
3887 if (!sem->sem) {
3888 vk_free2(&device->alloc, pAllocator, sem);
3889 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3890 }
3891 sem->syncobj = 0;
3892 }
3893
3894 *pSemaphore = radv_semaphore_to_handle(sem);
3895 return VK_SUCCESS;
3896 }
3897
3898 void radv_DestroySemaphore(
3899 VkDevice _device,
3900 VkSemaphore _semaphore,
3901 const VkAllocationCallbacks* pAllocator)
3902 {
3903 RADV_FROM_HANDLE(radv_device, device, _device);
3904 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3905 if (!_semaphore)
3906 return;
3907
3908 if (sem->syncobj)
3909 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3910 else
3911 device->ws->destroy_sem(sem->sem);
3912 vk_free2(&device->alloc, pAllocator, sem);
3913 }
3914
3915 VkResult radv_CreateEvent(
3916 VkDevice _device,
3917 const VkEventCreateInfo* pCreateInfo,
3918 const VkAllocationCallbacks* pAllocator,
3919 VkEvent* pEvent)
3920 {
3921 RADV_FROM_HANDLE(radv_device, device, _device);
3922 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3923 sizeof(*event), 8,
3924 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3925
3926 if (!event)
3927 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3928
3929 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3930 RADEON_DOMAIN_GTT,
3931 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
3932 RADV_BO_PRIORITY_FENCE);
3933 if (!event->bo) {
3934 vk_free2(&device->alloc, pAllocator, event);
3935 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3936 }
3937
3938 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3939
3940 *pEvent = radv_event_to_handle(event);
3941
3942 return VK_SUCCESS;
3943 }
3944
3945 void radv_DestroyEvent(
3946 VkDevice _device,
3947 VkEvent _event,
3948 const VkAllocationCallbacks* pAllocator)
3949 {
3950 RADV_FROM_HANDLE(radv_device, device, _device);
3951 RADV_FROM_HANDLE(radv_event, event, _event);
3952
3953 if (!event)
3954 return;
3955 device->ws->buffer_destroy(event->bo);
3956 vk_free2(&device->alloc, pAllocator, event);
3957 }
3958
3959 VkResult radv_GetEventStatus(
3960 VkDevice _device,
3961 VkEvent _event)
3962 {
3963 RADV_FROM_HANDLE(radv_event, event, _event);
3964
3965 if (*event->map == 1)
3966 return VK_EVENT_SET;
3967 return VK_EVENT_RESET;
3968 }
3969
3970 VkResult radv_SetEvent(
3971 VkDevice _device,
3972 VkEvent _event)
3973 {
3974 RADV_FROM_HANDLE(radv_event, event, _event);
3975 *event->map = 1;
3976
3977 return VK_SUCCESS;
3978 }
3979
3980 VkResult radv_ResetEvent(
3981 VkDevice _device,
3982 VkEvent _event)
3983 {
3984 RADV_FROM_HANDLE(radv_event, event, _event);
3985 *event->map = 0;
3986
3987 return VK_SUCCESS;
3988 }
3989
3990 VkResult radv_CreateBuffer(
3991 VkDevice _device,
3992 const VkBufferCreateInfo* pCreateInfo,
3993 const VkAllocationCallbacks* pAllocator,
3994 VkBuffer* pBuffer)
3995 {
3996 RADV_FROM_HANDLE(radv_device, device, _device);
3997 struct radv_buffer *buffer;
3998
3999 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4000
4001 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4002 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4003 if (buffer == NULL)
4004 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4005
4006 buffer->size = pCreateInfo->size;
4007 buffer->usage = pCreateInfo->usage;
4008 buffer->bo = NULL;
4009 buffer->offset = 0;
4010 buffer->flags = pCreateInfo->flags;
4011
4012 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4013 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4014
4015 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4016 buffer->bo = device->ws->buffer_create(device->ws,
4017 align64(buffer->size, 4096),
4018 4096, 0, RADEON_FLAG_VIRTUAL,
4019 RADV_BO_PRIORITY_VIRTUAL);
4020 if (!buffer->bo) {
4021 vk_free2(&device->alloc, pAllocator, buffer);
4022 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4023 }
4024 }
4025
4026 *pBuffer = radv_buffer_to_handle(buffer);
4027
4028 return VK_SUCCESS;
4029 }
4030
4031 void radv_DestroyBuffer(
4032 VkDevice _device,
4033 VkBuffer _buffer,
4034 const VkAllocationCallbacks* pAllocator)
4035 {
4036 RADV_FROM_HANDLE(radv_device, device, _device);
4037 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4038
4039 if (!buffer)
4040 return;
4041
4042 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4043 device->ws->buffer_destroy(buffer->bo);
4044
4045 vk_free2(&device->alloc, pAllocator, buffer);
4046 }
4047
4048 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4049 VkDevice device,
4050 const VkBufferDeviceAddressInfoEXT* pInfo)
4051 {
4052 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4053 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4054 }
4055
4056
4057 static inline unsigned
4058 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
4059 {
4060 if (stencil)
4061 return image->surface.u.legacy.stencil_tiling_index[level];
4062 else
4063 return image->surface.u.legacy.tiling_index[level];
4064 }
4065
4066 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4067 {
4068 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4069 }
4070
4071 static uint32_t
4072 radv_init_dcc_control_reg(struct radv_device *device,
4073 struct radv_image_view *iview)
4074 {
4075 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4076 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4077 unsigned max_compressed_block_size;
4078 unsigned independent_64b_blocks;
4079
4080 if (!radv_image_has_dcc(iview->image))
4081 return 0;
4082
4083 if (iview->image->info.samples > 1) {
4084 if (iview->image->surface.bpe == 1)
4085 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4086 else if (iview->image->surface.bpe == 2)
4087 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4088 }
4089
4090 if (!device->physical_device->rad_info.has_dedicated_vram) {
4091 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4092 * dGPU and 64 for APU because all of our APUs to date use
4093 * DIMMs which have a request granularity size of 64B while all
4094 * other chips have a 32B request size.
4095 */
4096 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4097 }
4098
4099 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4100 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4101 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4102 /* If this DCC image is potentially going to be used in texture
4103 * fetches, we need some special settings.
4104 */
4105 independent_64b_blocks = 1;
4106 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4107 } else {
4108 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4109 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4110 * big as possible for better compression state.
4111 */
4112 independent_64b_blocks = 0;
4113 max_compressed_block_size = max_uncompressed_block_size;
4114 }
4115
4116 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4117 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4118 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4119 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4120 }
4121
4122 static void
4123 radv_initialise_color_surface(struct radv_device *device,
4124 struct radv_color_buffer_info *cb,
4125 struct radv_image_view *iview)
4126 {
4127 const struct vk_format_description *desc;
4128 unsigned ntype, format, swap, endian;
4129 unsigned blend_clamp = 0, blend_bypass = 0;
4130 uint64_t va;
4131 const struct radeon_surf *surf = &iview->image->surface;
4132
4133 desc = vk_format_description(iview->vk_format);
4134
4135 memset(cb, 0, sizeof(*cb));
4136
4137 /* Intensity is implemented as Red, so treat it that way. */
4138 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4139
4140 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4141
4142 cb->cb_color_base = va >> 8;
4143
4144 if (device->physical_device->rad_info.chip_class >= GFX9) {
4145 struct gfx9_surf_meta_flags meta;
4146 if (iview->image->dcc_offset)
4147 meta = iview->image->surface.u.gfx9.dcc;
4148 else
4149 meta = iview->image->surface.u.gfx9.cmask;
4150
4151 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4152 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4153 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4154 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4155
4156 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4157 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4158 } else {
4159 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4160 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4161
4162 cb->cb_color_base += level_info->offset >> 8;
4163 if (level_info->mode == RADEON_SURF_MODE_2D)
4164 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4165
4166 pitch_tile_max = level_info->nblk_x / 8 - 1;
4167 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4168 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4169
4170 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4171 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4172 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4173
4174 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4175
4176 if (radv_image_has_fmask(iview->image)) {
4177 if (device->physical_device->rad_info.chip_class >= CIK)
4178 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4179 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4180 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4181 } else {
4182 /* This must be set for fast clear to work without FMASK. */
4183 if (device->physical_device->rad_info.chip_class >= CIK)
4184 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4185 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4186 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4187 }
4188 }
4189
4190 /* CMASK variables */
4191 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4192 va += iview->image->cmask.offset;
4193 cb->cb_color_cmask = va >> 8;
4194
4195 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4196 va += iview->image->dcc_offset;
4197 cb->cb_dcc_base = va >> 8;
4198 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4199
4200 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4201 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4202 S_028C6C_SLICE_MAX(max_slice);
4203
4204 if (iview->image->info.samples > 1) {
4205 unsigned log_samples = util_logbase2(iview->image->info.samples);
4206
4207 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4208 S_028C74_NUM_FRAGMENTS(log_samples);
4209 }
4210
4211 if (radv_image_has_fmask(iview->image)) {
4212 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4213 cb->cb_color_fmask = va >> 8;
4214 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4215 } else {
4216 cb->cb_color_fmask = cb->cb_color_base;
4217 }
4218
4219 ntype = radv_translate_color_numformat(iview->vk_format,
4220 desc,
4221 vk_format_get_first_non_void_channel(iview->vk_format));
4222 format = radv_translate_colorformat(iview->vk_format);
4223 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4224 radv_finishme("Illegal color\n");
4225 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4226 endian = radv_colorformat_endian_swap(format);
4227
4228 /* blend clamp should be set for all NORM/SRGB types */
4229 if (ntype == V_028C70_NUMBER_UNORM ||
4230 ntype == V_028C70_NUMBER_SNORM ||
4231 ntype == V_028C70_NUMBER_SRGB)
4232 blend_clamp = 1;
4233
4234 /* set blend bypass according to docs if SINT/UINT or
4235 8/24 COLOR variants */
4236 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4237 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4238 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4239 blend_clamp = 0;
4240 blend_bypass = 1;
4241 }
4242 #if 0
4243 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4244 (format == V_028C70_COLOR_8 ||
4245 format == V_028C70_COLOR_8_8 ||
4246 format == V_028C70_COLOR_8_8_8_8))
4247 ->color_is_int8 = true;
4248 #endif
4249 cb->cb_color_info = S_028C70_FORMAT(format) |
4250 S_028C70_COMP_SWAP(swap) |
4251 S_028C70_BLEND_CLAMP(blend_clamp) |
4252 S_028C70_BLEND_BYPASS(blend_bypass) |
4253 S_028C70_SIMPLE_FLOAT(1) |
4254 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4255 ntype != V_028C70_NUMBER_SNORM &&
4256 ntype != V_028C70_NUMBER_SRGB &&
4257 format != V_028C70_COLOR_8_24 &&
4258 format != V_028C70_COLOR_24_8) |
4259 S_028C70_NUMBER_TYPE(ntype) |
4260 S_028C70_ENDIAN(endian);
4261 if (radv_image_has_fmask(iview->image)) {
4262 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4263 if (device->physical_device->rad_info.chip_class == SI) {
4264 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4265 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4266 }
4267 }
4268
4269 if (radv_image_has_cmask(iview->image) &&
4270 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4271 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4272
4273 if (radv_dcc_enabled(iview->image, iview->base_mip))
4274 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4275
4276 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4277
4278 /* This must be set for fast clear to work without FMASK. */
4279 if (!radv_image_has_fmask(iview->image) &&
4280 device->physical_device->rad_info.chip_class == SI) {
4281 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4282 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4283 }
4284
4285 if (device->physical_device->rad_info.chip_class >= GFX9) {
4286 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4287 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4288
4289 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4290 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4291 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4292 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4293 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4294 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4295 }
4296 }
4297
4298 static unsigned
4299 radv_calc_decompress_on_z_planes(struct radv_device *device,
4300 struct radv_image_view *iview)
4301 {
4302 unsigned max_zplanes = 0;
4303
4304 assert(radv_image_is_tc_compat_htile(iview->image));
4305
4306 if (device->physical_device->rad_info.chip_class >= GFX9) {
4307 /* Default value for 32-bit depth surfaces. */
4308 max_zplanes = 4;
4309
4310 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4311 iview->image->info.samples > 1)
4312 max_zplanes = 2;
4313
4314 max_zplanes = max_zplanes + 1;
4315 } else {
4316 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4317 /* Do not enable Z plane compression for 16-bit depth
4318 * surfaces because isn't supported on GFX8. Only
4319 * 32-bit depth surfaces are supported by the hardware.
4320 * This allows to maintain shader compatibility and to
4321 * reduce the number of depth decompressions.
4322 */
4323 max_zplanes = 1;
4324 } else {
4325 if (iview->image->info.samples <= 1)
4326 max_zplanes = 5;
4327 else if (iview->image->info.samples <= 4)
4328 max_zplanes = 3;
4329 else
4330 max_zplanes = 2;
4331 }
4332 }
4333
4334 return max_zplanes;
4335 }
4336
4337 static void
4338 radv_initialise_ds_surface(struct radv_device *device,
4339 struct radv_ds_buffer_info *ds,
4340 struct radv_image_view *iview)
4341 {
4342 unsigned level = iview->base_mip;
4343 unsigned format, stencil_format;
4344 uint64_t va, s_offs, z_offs;
4345 bool stencil_only = false;
4346 memset(ds, 0, sizeof(*ds));
4347 switch (iview->image->vk_format) {
4348 case VK_FORMAT_D24_UNORM_S8_UINT:
4349 case VK_FORMAT_X8_D24_UNORM_PACK32:
4350 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4351 ds->offset_scale = 2.0f;
4352 break;
4353 case VK_FORMAT_D16_UNORM:
4354 case VK_FORMAT_D16_UNORM_S8_UINT:
4355 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4356 ds->offset_scale = 4.0f;
4357 break;
4358 case VK_FORMAT_D32_SFLOAT:
4359 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4360 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4361 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4362 ds->offset_scale = 1.0f;
4363 break;
4364 case VK_FORMAT_S8_UINT:
4365 stencil_only = true;
4366 break;
4367 default:
4368 break;
4369 }
4370
4371 format = radv_translate_dbformat(iview->image->vk_format);
4372 stencil_format = iview->image->surface.has_stencil ?
4373 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4374
4375 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4376 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4377 S_028008_SLICE_MAX(max_slice);
4378
4379 ds->db_htile_data_base = 0;
4380 ds->db_htile_surface = 0;
4381
4382 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4383 s_offs = z_offs = va;
4384
4385 if (device->physical_device->rad_info.chip_class >= GFX9) {
4386 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4387 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4388
4389 ds->db_z_info = S_028038_FORMAT(format) |
4390 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4391 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4392 S_028038_MAXMIP(iview->image->info.levels - 1) |
4393 S_028038_ZRANGE_PRECISION(1);
4394 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4395 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4396
4397 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4398 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4399 ds->db_depth_view |= S_028008_MIPID(level);
4400
4401 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4402 S_02801C_Y_MAX(iview->image->info.height - 1);
4403
4404 if (radv_htile_enabled(iview->image, level)) {
4405 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4406
4407 if (radv_image_is_tc_compat_htile(iview->image)) {
4408 unsigned max_zplanes =
4409 radv_calc_decompress_on_z_planes(device, iview);
4410
4411 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4412 S_028038_ITERATE_FLUSH(1);
4413 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4414 }
4415
4416 if (!iview->image->surface.has_stencil)
4417 /* Use all of the htile_buffer for depth if there's no stencil. */
4418 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4419 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4420 iview->image->htile_offset;
4421 ds->db_htile_data_base = va >> 8;
4422 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4423 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4424 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4425 }
4426 } else {
4427 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4428
4429 if (stencil_only)
4430 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4431
4432 z_offs += iview->image->surface.u.legacy.level[level].offset;
4433 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4434
4435 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4436 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4437 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4438
4439 if (iview->image->info.samples > 1)
4440 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4441
4442 if (device->physical_device->rad_info.chip_class >= CIK) {
4443 struct radeon_info *info = &device->physical_device->rad_info;
4444 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4445 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4446 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4447 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4448 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4449 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4450
4451 if (stencil_only)
4452 tile_mode = stencil_tile_mode;
4453
4454 ds->db_depth_info |=
4455 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4456 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4457 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4458 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4459 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4460 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4461 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4462 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4463 } else {
4464 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4465 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4466 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4467 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4468 if (stencil_only)
4469 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4470 }
4471
4472 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4473 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4474 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4475
4476 if (radv_htile_enabled(iview->image, level)) {
4477 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4478
4479 if (!iview->image->surface.has_stencil &&
4480 !radv_image_is_tc_compat_htile(iview->image))
4481 /* Use all of the htile_buffer for depth if there's no stencil. */
4482 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4483
4484 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4485 iview->image->htile_offset;
4486 ds->db_htile_data_base = va >> 8;
4487 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4488
4489 if (radv_image_is_tc_compat_htile(iview->image)) {
4490 unsigned max_zplanes =
4491 radv_calc_decompress_on_z_planes(device, iview);
4492
4493 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4494 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4495 }
4496 }
4497 }
4498
4499 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4500 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4501 }
4502
4503 VkResult radv_CreateFramebuffer(
4504 VkDevice _device,
4505 const VkFramebufferCreateInfo* pCreateInfo,
4506 const VkAllocationCallbacks* pAllocator,
4507 VkFramebuffer* pFramebuffer)
4508 {
4509 RADV_FROM_HANDLE(radv_device, device, _device);
4510 struct radv_framebuffer *framebuffer;
4511
4512 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4513
4514 size_t size = sizeof(*framebuffer) +
4515 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4516 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4517 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4518 if (framebuffer == NULL)
4519 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4520
4521 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4522 framebuffer->width = pCreateInfo->width;
4523 framebuffer->height = pCreateInfo->height;
4524 framebuffer->layers = pCreateInfo->layers;
4525 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4526 VkImageView _iview = pCreateInfo->pAttachments[i];
4527 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4528 framebuffer->attachments[i].attachment = iview;
4529 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4530 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4531 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4532 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4533 }
4534 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4535 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4536 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4537 }
4538
4539 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4540 return VK_SUCCESS;
4541 }
4542
4543 void radv_DestroyFramebuffer(
4544 VkDevice _device,
4545 VkFramebuffer _fb,
4546 const VkAllocationCallbacks* pAllocator)
4547 {
4548 RADV_FROM_HANDLE(radv_device, device, _device);
4549 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4550
4551 if (!fb)
4552 return;
4553 vk_free2(&device->alloc, pAllocator, fb);
4554 }
4555
4556 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4557 {
4558 switch (address_mode) {
4559 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4560 return V_008F30_SQ_TEX_WRAP;
4561 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4562 return V_008F30_SQ_TEX_MIRROR;
4563 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4564 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4565 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4566 return V_008F30_SQ_TEX_CLAMP_BORDER;
4567 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4568 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4569 default:
4570 unreachable("illegal tex wrap mode");
4571 break;
4572 }
4573 }
4574
4575 static unsigned
4576 radv_tex_compare(VkCompareOp op)
4577 {
4578 switch (op) {
4579 case VK_COMPARE_OP_NEVER:
4580 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4581 case VK_COMPARE_OP_LESS:
4582 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4583 case VK_COMPARE_OP_EQUAL:
4584 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4585 case VK_COMPARE_OP_LESS_OR_EQUAL:
4586 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4587 case VK_COMPARE_OP_GREATER:
4588 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4589 case VK_COMPARE_OP_NOT_EQUAL:
4590 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4591 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4592 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4593 case VK_COMPARE_OP_ALWAYS:
4594 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4595 default:
4596 unreachable("illegal compare mode");
4597 break;
4598 }
4599 }
4600
4601 static unsigned
4602 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4603 {
4604 switch (filter) {
4605 case VK_FILTER_NEAREST:
4606 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4607 V_008F38_SQ_TEX_XY_FILTER_POINT);
4608 case VK_FILTER_LINEAR:
4609 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4610 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4611 case VK_FILTER_CUBIC_IMG:
4612 default:
4613 fprintf(stderr, "illegal texture filter");
4614 return 0;
4615 }
4616 }
4617
4618 static unsigned
4619 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4620 {
4621 switch (mode) {
4622 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4623 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4624 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4625 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4626 default:
4627 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4628 }
4629 }
4630
4631 static unsigned
4632 radv_tex_bordercolor(VkBorderColor bcolor)
4633 {
4634 switch (bcolor) {
4635 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4636 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4637 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4638 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4639 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4640 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4641 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4642 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4643 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4644 default:
4645 break;
4646 }
4647 return 0;
4648 }
4649
4650 static unsigned
4651 radv_tex_aniso_filter(unsigned filter)
4652 {
4653 if (filter < 2)
4654 return 0;
4655 if (filter < 4)
4656 return 1;
4657 if (filter < 8)
4658 return 2;
4659 if (filter < 16)
4660 return 3;
4661 return 4;
4662 }
4663
4664 static unsigned
4665 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4666 {
4667 switch (mode) {
4668 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4669 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4670 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4671 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4672 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4673 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4674 default:
4675 break;
4676 }
4677 return 0;
4678 }
4679
4680 static uint32_t
4681 radv_get_max_anisotropy(struct radv_device *device,
4682 const VkSamplerCreateInfo *pCreateInfo)
4683 {
4684 if (device->force_aniso >= 0)
4685 return device->force_aniso;
4686
4687 if (pCreateInfo->anisotropyEnable &&
4688 pCreateInfo->maxAnisotropy > 1.0f)
4689 return (uint32_t)pCreateInfo->maxAnisotropy;
4690
4691 return 0;
4692 }
4693
4694 static void
4695 radv_init_sampler(struct radv_device *device,
4696 struct radv_sampler *sampler,
4697 const VkSamplerCreateInfo *pCreateInfo)
4698 {
4699 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4700 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4701 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4702 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4703
4704 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4705 vk_find_struct_const(pCreateInfo->pNext,
4706 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4707 if (sampler_reduction)
4708 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4709
4710 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4711 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4712 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4713 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4714 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4715 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4716 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4717 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4718 S_008F30_DISABLE_CUBE_WRAP(0) |
4719 S_008F30_COMPAT_MODE(is_vi) |
4720 S_008F30_FILTER_MODE(filter_mode));
4721 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4722 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4723 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4724 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4725 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4726 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4727 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4728 S_008F38_MIP_POINT_PRECLAMP(0) |
4729 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4730 S_008F38_FILTER_PREC_FIX(1) |
4731 S_008F38_ANISO_OVERRIDE(is_vi));
4732 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4733 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4734 }
4735
4736 VkResult radv_CreateSampler(
4737 VkDevice _device,
4738 const VkSamplerCreateInfo* pCreateInfo,
4739 const VkAllocationCallbacks* pAllocator,
4740 VkSampler* pSampler)
4741 {
4742 RADV_FROM_HANDLE(radv_device, device, _device);
4743 struct radv_sampler *sampler;
4744
4745 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4746
4747 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4748 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4749 if (!sampler)
4750 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4751
4752 radv_init_sampler(device, sampler, pCreateInfo);
4753 *pSampler = radv_sampler_to_handle(sampler);
4754
4755 return VK_SUCCESS;
4756 }
4757
4758 void radv_DestroySampler(
4759 VkDevice _device,
4760 VkSampler _sampler,
4761 const VkAllocationCallbacks* pAllocator)
4762 {
4763 RADV_FROM_HANDLE(radv_device, device, _device);
4764 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4765
4766 if (!sampler)
4767 return;
4768 vk_free2(&device->alloc, pAllocator, sampler);
4769 }
4770
4771 /* vk_icd.h does not declare this function, so we declare it here to
4772 * suppress Wmissing-prototypes.
4773 */
4774 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4775 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4776
4777 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4778 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4779 {
4780 /* For the full details on loader interface versioning, see
4781 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4782 * What follows is a condensed summary, to help you navigate the large and
4783 * confusing official doc.
4784 *
4785 * - Loader interface v0 is incompatible with later versions. We don't
4786 * support it.
4787 *
4788 * - In loader interface v1:
4789 * - The first ICD entrypoint called by the loader is
4790 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4791 * entrypoint.
4792 * - The ICD must statically expose no other Vulkan symbol unless it is
4793 * linked with -Bsymbolic.
4794 * - Each dispatchable Vulkan handle created by the ICD must be
4795 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4796 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4797 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4798 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4799 * such loader-managed surfaces.
4800 *
4801 * - Loader interface v2 differs from v1 in:
4802 * - The first ICD entrypoint called by the loader is
4803 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4804 * statically expose this entrypoint.
4805 *
4806 * - Loader interface v3 differs from v2 in:
4807 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4808 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4809 * because the loader no longer does so.
4810 */
4811 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4812 return VK_SUCCESS;
4813 }
4814
4815 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4816 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4817 int *pFD)
4818 {
4819 RADV_FROM_HANDLE(radv_device, device, _device);
4820 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4821
4822 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4823
4824 /* At the moment, we support only the below handle types. */
4825 assert(pGetFdInfo->handleType ==
4826 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4827 pGetFdInfo->handleType ==
4828 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4829
4830 bool ret = radv_get_memory_fd(device, memory, pFD);
4831 if (ret == false)
4832 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4833 return VK_SUCCESS;
4834 }
4835
4836 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4837 VkExternalMemoryHandleTypeFlagBits handleType,
4838 int fd,
4839 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4840 {
4841 RADV_FROM_HANDLE(radv_device, device, _device);
4842
4843 switch (handleType) {
4844 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4845 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4846 return VK_SUCCESS;
4847
4848 default:
4849 /* The valid usage section for this function says:
4850 *
4851 * "handleType must not be one of the handle types defined as
4852 * opaque."
4853 *
4854 * So opaque handle types fall into the default "unsupported" case.
4855 */
4856 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4857 }
4858 }
4859
4860 static VkResult radv_import_opaque_fd(struct radv_device *device,
4861 int fd,
4862 uint32_t *syncobj)
4863 {
4864 uint32_t syncobj_handle = 0;
4865 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4866 if (ret != 0)
4867 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4868
4869 if (*syncobj)
4870 device->ws->destroy_syncobj(device->ws, *syncobj);
4871
4872 *syncobj = syncobj_handle;
4873 close(fd);
4874
4875 return VK_SUCCESS;
4876 }
4877
4878 static VkResult radv_import_sync_fd(struct radv_device *device,
4879 int fd,
4880 uint32_t *syncobj)
4881 {
4882 /* If we create a syncobj we do it locally so that if we have an error, we don't
4883 * leave a syncobj in an undetermined state in the fence. */
4884 uint32_t syncobj_handle = *syncobj;
4885 if (!syncobj_handle) {
4886 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4887 if (ret) {
4888 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4889 }
4890 }
4891
4892 if (fd == -1) {
4893 device->ws->signal_syncobj(device->ws, syncobj_handle);
4894 } else {
4895 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4896 if (ret != 0)
4897 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4898 }
4899
4900 *syncobj = syncobj_handle;
4901 if (fd != -1)
4902 close(fd);
4903
4904 return VK_SUCCESS;
4905 }
4906
4907 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4908 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4909 {
4910 RADV_FROM_HANDLE(radv_device, device, _device);
4911 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4912 uint32_t *syncobj_dst = NULL;
4913
4914 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
4915 syncobj_dst = &sem->temp_syncobj;
4916 } else {
4917 syncobj_dst = &sem->syncobj;
4918 }
4919
4920 switch(pImportSemaphoreFdInfo->handleType) {
4921 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4922 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4923 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4924 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4925 default:
4926 unreachable("Unhandled semaphore handle type");
4927 }
4928 }
4929
4930 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4931 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4932 int *pFd)
4933 {
4934 RADV_FROM_HANDLE(radv_device, device, _device);
4935 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4936 int ret;
4937 uint32_t syncobj_handle;
4938
4939 if (sem->temp_syncobj)
4940 syncobj_handle = sem->temp_syncobj;
4941 else
4942 syncobj_handle = sem->syncobj;
4943
4944 switch(pGetFdInfo->handleType) {
4945 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
4946 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4947 break;
4948 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
4949 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4950 if (!ret) {
4951 if (sem->temp_syncobj) {
4952 close (sem->temp_syncobj);
4953 sem->temp_syncobj = 0;
4954 } else {
4955 device->ws->reset_syncobj(device->ws, syncobj_handle);
4956 }
4957 }
4958 break;
4959 default:
4960 unreachable("Unhandled semaphore handle type");
4961 }
4962
4963 if (ret)
4964 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4965 return VK_SUCCESS;
4966 }
4967
4968 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4969 VkPhysicalDevice physicalDevice,
4970 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
4971 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
4972 {
4973 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4974
4975 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4976 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4977 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
4978 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
4979 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4980 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
4981 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4982 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4983 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
4984 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4985 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
4986 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
4987 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
4988 } else {
4989 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4990 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4991 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4992 }
4993 }
4994
4995 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4996 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4997 {
4998 RADV_FROM_HANDLE(radv_device, device, _device);
4999 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5000 uint32_t *syncobj_dst = NULL;
5001
5002
5003 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5004 syncobj_dst = &fence->temp_syncobj;
5005 } else {
5006 syncobj_dst = &fence->syncobj;
5007 }
5008
5009 switch(pImportFenceFdInfo->handleType) {
5010 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5011 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5012 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5013 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5014 default:
5015 unreachable("Unhandled fence handle type");
5016 }
5017 }
5018
5019 VkResult radv_GetFenceFdKHR(VkDevice _device,
5020 const VkFenceGetFdInfoKHR *pGetFdInfo,
5021 int *pFd)
5022 {
5023 RADV_FROM_HANDLE(radv_device, device, _device);
5024 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5025 int ret;
5026 uint32_t syncobj_handle;
5027
5028 if (fence->temp_syncobj)
5029 syncobj_handle = fence->temp_syncobj;
5030 else
5031 syncobj_handle = fence->syncobj;
5032
5033 switch(pGetFdInfo->handleType) {
5034 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5035 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5036 break;
5037 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5038 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5039 if (!ret) {
5040 if (fence->temp_syncobj) {
5041 close (fence->temp_syncobj);
5042 fence->temp_syncobj = 0;
5043 } else {
5044 device->ws->reset_syncobj(device->ws, syncobj_handle);
5045 }
5046 }
5047 break;
5048 default:
5049 unreachable("Unhandled fence handle type");
5050 }
5051
5052 if (ret)
5053 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5054 return VK_SUCCESS;
5055 }
5056
5057 void radv_GetPhysicalDeviceExternalFenceProperties(
5058 VkPhysicalDevice physicalDevice,
5059 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5060 VkExternalFenceProperties *pExternalFenceProperties)
5061 {
5062 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5063
5064 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5065 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5066 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5067 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5068 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5069 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5070 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5071 } else {
5072 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5073 pExternalFenceProperties->compatibleHandleTypes = 0;
5074 pExternalFenceProperties->externalFenceFeatures = 0;
5075 }
5076 }
5077
5078 VkResult
5079 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5080 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5081 const VkAllocationCallbacks* pAllocator,
5082 VkDebugReportCallbackEXT* pCallback)
5083 {
5084 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5085 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5086 pCreateInfo, pAllocator, &instance->alloc,
5087 pCallback);
5088 }
5089
5090 void
5091 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5092 VkDebugReportCallbackEXT _callback,
5093 const VkAllocationCallbacks* pAllocator)
5094 {
5095 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5096 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5097 _callback, pAllocator, &instance->alloc);
5098 }
5099
5100 void
5101 radv_DebugReportMessageEXT(VkInstance _instance,
5102 VkDebugReportFlagsEXT flags,
5103 VkDebugReportObjectTypeEXT objectType,
5104 uint64_t object,
5105 size_t location,
5106 int32_t messageCode,
5107 const char* pLayerPrefix,
5108 const char* pMessage)
5109 {
5110 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5111 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5112 object, location, messageCode, pLayerPrefix, pMessage);
5113 }
5114
5115 void
5116 radv_GetDeviceGroupPeerMemoryFeatures(
5117 VkDevice device,
5118 uint32_t heapIndex,
5119 uint32_t localDeviceIndex,
5120 uint32_t remoteDeviceIndex,
5121 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5122 {
5123 assert(localDeviceIndex == remoteDeviceIndex);
5124
5125 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5126 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5127 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5128 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5129 }
5130
5131 static const VkTimeDomainEXT radv_time_domains[] = {
5132 VK_TIME_DOMAIN_DEVICE_EXT,
5133 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5134 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5135 };
5136
5137 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5138 VkPhysicalDevice physicalDevice,
5139 uint32_t *pTimeDomainCount,
5140 VkTimeDomainEXT *pTimeDomains)
5141 {
5142 int d;
5143 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5144
5145 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5146 vk_outarray_append(&out, i) {
5147 *i = radv_time_domains[d];
5148 }
5149 }
5150
5151 return vk_outarray_status(&out);
5152 }
5153
5154 static uint64_t
5155 radv_clock_gettime(clockid_t clock_id)
5156 {
5157 struct timespec current;
5158 int ret;
5159
5160 ret = clock_gettime(clock_id, &current);
5161 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5162 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5163 if (ret < 0)
5164 return 0;
5165
5166 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5167 }
5168
5169 VkResult radv_GetCalibratedTimestampsEXT(
5170 VkDevice _device,
5171 uint32_t timestampCount,
5172 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5173 uint64_t *pTimestamps,
5174 uint64_t *pMaxDeviation)
5175 {
5176 RADV_FROM_HANDLE(radv_device, device, _device);
5177 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5178 int d;
5179 uint64_t begin, end;
5180 uint64_t max_clock_period = 0;
5181
5182 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5183
5184 for (d = 0; d < timestampCount; d++) {
5185 switch (pTimestampInfos[d].timeDomain) {
5186 case VK_TIME_DOMAIN_DEVICE_EXT:
5187 pTimestamps[d] = device->ws->query_value(device->ws,
5188 RADEON_TIMESTAMP);
5189 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5190 max_clock_period = MAX2(max_clock_period, device_period);
5191 break;
5192 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5193 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5194 max_clock_period = MAX2(max_clock_period, 1);
5195 break;
5196
5197 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5198 pTimestamps[d] = begin;
5199 break;
5200 default:
5201 pTimestamps[d] = 0;
5202 break;
5203 }
5204 }
5205
5206 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5207
5208 /*
5209 * The maximum deviation is the sum of the interval over which we
5210 * perform the sampling and the maximum period of any sampled
5211 * clock. That's because the maximum skew between any two sampled
5212 * clock edges is when the sampled clock with the largest period is
5213 * sampled at the end of that period but right at the beginning of the
5214 * sampling interval and some other clock is sampled right at the
5215 * begining of its sampling period and right at the end of the
5216 * sampling interval. Let's assume the GPU has the longest clock
5217 * period and that the application is sampling GPU and monotonic:
5218 *
5219 * s e
5220 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5221 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5222 *
5223 * g
5224 * 0 1 2 3
5225 * GPU -----_____-----_____-----_____-----_____
5226 *
5227 * m
5228 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5229 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5230 *
5231 * Interval <----------------->
5232 * Deviation <-------------------------->
5233 *
5234 * s = read(raw) 2
5235 * g = read(GPU) 1
5236 * m = read(monotonic) 2
5237 * e = read(raw) b
5238 *
5239 * We round the sample interval up by one tick to cover sampling error
5240 * in the interval clock
5241 */
5242
5243 uint64_t sample_interval = end - begin + 1;
5244
5245 *pMaxDeviation = sample_interval + max_clock_period;
5246
5247 return VK_SUCCESS;
5248 }