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radv: add support for Raven2
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "addrlib/gfx9/chip/gfx9_enum.h"
49 #include "util/build_id.h"
50 #include "util/debug.h"
51 #include "util/mesa-sha1.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91 char llvm_string[32] = {};
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 default: chip_string = "AMD RADV unknown"; break;
118 }
119
120 snprintf(llvm_string, sizeof(llvm_string),
121 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
122 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
123 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
124 }
125
126 static void
127 radv_physical_device_init_mem_types(struct radv_physical_device *device)
128 {
129 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
130 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
131 device->rad_info.vram_vis_size);
132
133 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
134 device->memory_properties.memoryHeapCount = 0;
135 if (device->rad_info.vram_size - visible_vram_size > 0) {
136 vram_index = device->memory_properties.memoryHeapCount++;
137 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
138 .size = device->rad_info.vram_size - visible_vram_size,
139 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
140 };
141 }
142 if (visible_vram_size) {
143 visible_vram_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
145 .size = visible_vram_size,
146 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
147 };
148 }
149 if (device->rad_info.gart_size > 0) {
150 gart_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
152 .size = device->rad_info.gart_size,
153 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156
157 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
158 unsigned type_count = 0;
159 if (vram_index >= 0) {
160 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
161 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
162 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
163 .heapIndex = vram_index,
164 };
165 }
166 if (gart_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
170 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
171 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
172 .heapIndex = gart_index,
173 };
174 }
175 if (visible_vram_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
179 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
181 .heapIndex = visible_vram_index,
182 };
183 }
184 if (gart_index >= 0) {
185 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
186 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
187 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
189 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
190 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
191 .heapIndex = gart_index,
192 };
193 }
194 device->memory_properties.memoryTypeCount = type_count;
195 }
196
197 static void
198 radv_handle_env_var_force_family(struct radv_physical_device *device)
199 {
200 const char *family = getenv("RADV_FORCE_FAMILY");
201 unsigned i;
202
203 if (!family)
204 return;
205
206 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
207 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
208 /* Override family and chip_class. */
209 device->rad_info.family = i;
210
211 if (i >= CHIP_VEGA10)
212 device->rad_info.chip_class = GFX9;
213 else if (i >= CHIP_TONGA)
214 device->rad_info.chip_class = VI;
215 else if (i >= CHIP_BONAIRE)
216 device->rad_info.chip_class = CIK;
217 else
218 device->rad_info.chip_class = SI;
219
220 return;
221 }
222 }
223
224 fprintf(stderr, "radv: Unknown family: %s\n", family);
225 exit(1);
226 }
227
228 static VkResult
229 radv_physical_device_init(struct radv_physical_device *device,
230 struct radv_instance *instance,
231 drmDevicePtr drm_device)
232 {
233 const char *path = drm_device->nodes[DRM_NODE_RENDER];
234 VkResult result;
235 drmVersionPtr version;
236 int fd;
237 int master_fd = -1;
238
239 fd = open(path, O_RDWR | O_CLOEXEC);
240 if (fd < 0) {
241 if (instance->debug_flags & RADV_DEBUG_STARTUP)
242 radv_logi("Could not open device '%s'", path);
243
244 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
245 }
246
247 version = drmGetVersion(fd);
248 if (!version) {
249 close(fd);
250
251 if (instance->debug_flags & RADV_DEBUG_STARTUP)
252 radv_logi("Could not get the kernel driver version for device '%s'", path);
253
254 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
255 "failed to get version %s: %m", path);
256 }
257
258 if (strcmp(version->name, "amdgpu")) {
259 drmFreeVersion(version);
260 close(fd);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
264
265 return VK_ERROR_INCOMPATIBLE_DRIVER;
266 }
267 drmFreeVersion(version);
268
269 if (instance->debug_flags & RADV_DEBUG_STARTUP)
270 radv_logi("Found compatible device '%s'.", path);
271
272 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
273 device->instance = instance;
274 assert(strlen(path) < ARRAY_SIZE(device->path));
275 strncpy(device->path, path, ARRAY_SIZE(device->path));
276
277 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
278 instance->perftest_flags);
279 if (!device->ws) {
280 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
281 goto fail;
282 }
283
284 if (instance->enabled_extensions.KHR_display) {
285 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
286 if (master_fd >= 0) {
287 uint32_t accel_working = 0;
288 struct drm_amdgpu_info request = {
289 .return_pointer = (uintptr_t)&accel_working,
290 .return_size = sizeof(accel_working),
291 .query = AMDGPU_INFO_ACCEL_WORKING
292 };
293
294 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
295 close(master_fd);
296 master_fd = -1;
297 }
298 }
299 }
300
301 device->master_fd = master_fd;
302 device->local_fd = fd;
303 device->ws->query_info(device->ws, &device->rad_info);
304
305 radv_handle_env_var_force_family(device);
306
307 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
308
309 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
310 device->ws->destroy(device->ws);
311 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
312 "cannot generate UUID");
313 goto fail;
314 }
315
316 /* These flags affect shader compilation. */
317 uint64_t shader_env_flags =
318 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
319 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
320
321 /* The gpu id is already embedded in the uuid so we just pass "radv"
322 * when creating the cache.
323 */
324 char buf[VK_UUID_SIZE * 2 + 1];
325 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
326 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
327
328 if (device->rad_info.chip_class < VI ||
329 device->rad_info.chip_class > GFX9)
330 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
331
332 radv_get_driver_uuid(&device->device_uuid);
333 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
334
335 if (device->rad_info.family == CHIP_STONEY ||
336 device->rad_info.chip_class >= GFX9) {
337 device->has_rbplus = true;
338 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
339 device->rad_info.family == CHIP_VEGA12 ||
340 device->rad_info.family == CHIP_RAVEN ||
341 device->rad_info.family == CHIP_RAVEN2;
342 }
343
344 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
345 * on SI.
346 */
347 device->has_clear_state = device->rad_info.chip_class >= CIK;
348
349 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
350
351 /* Vega10/Raven need a special workaround for a hardware bug. */
352 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
353 device->rad_info.family == CHIP_RAVEN;
354
355 /* Out-of-order primitive rasterization. */
356 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
357 device->rad_info.max_se >= 2;
358 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
359 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
360
361 device->dcc_msaa_allowed =
362 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
363
364 radv_physical_device_init_mem_types(device);
365 radv_fill_device_extension_table(device, &device->supported_extensions);
366
367 device->bus_info = *drm_device->businfo.pci;
368
369 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
370 ac_print_gpu_info(&device->rad_info);
371
372 /* The WSI is structured as a layer on top of the driver, so this has
373 * to be the last part of initialization (at least until we get other
374 * semi-layers).
375 */
376 result = radv_init_wsi(device);
377 if (result != VK_SUCCESS) {
378 device->ws->destroy(device->ws);
379 vk_error(instance, result);
380 goto fail;
381 }
382
383 return VK_SUCCESS;
384
385 fail:
386 close(fd);
387 if (master_fd != -1)
388 close(master_fd);
389 return result;
390 }
391
392 static void
393 radv_physical_device_finish(struct radv_physical_device *device)
394 {
395 radv_finish_wsi(device);
396 device->ws->destroy(device->ws);
397 disk_cache_destroy(device->disk_cache);
398 close(device->local_fd);
399 if (device->master_fd != -1)
400 close(device->master_fd);
401 }
402
403 static void *
404 default_alloc_func(void *pUserData, size_t size, size_t align,
405 VkSystemAllocationScope allocationScope)
406 {
407 return malloc(size);
408 }
409
410 static void *
411 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
412 size_t align, VkSystemAllocationScope allocationScope)
413 {
414 return realloc(pOriginal, size);
415 }
416
417 static void
418 default_free_func(void *pUserData, void *pMemory)
419 {
420 free(pMemory);
421 }
422
423 static const VkAllocationCallbacks default_alloc = {
424 .pUserData = NULL,
425 .pfnAllocation = default_alloc_func,
426 .pfnReallocation = default_realloc_func,
427 .pfnFree = default_free_func,
428 };
429
430 static const struct debug_control radv_debug_options[] = {
431 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
432 {"nodcc", RADV_DEBUG_NO_DCC},
433 {"shaders", RADV_DEBUG_DUMP_SHADERS},
434 {"nocache", RADV_DEBUG_NO_CACHE},
435 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
436 {"nohiz", RADV_DEBUG_NO_HIZ},
437 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
438 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
439 {"allbos", RADV_DEBUG_ALL_BOS},
440 {"noibs", RADV_DEBUG_NO_IBS},
441 {"spirv", RADV_DEBUG_DUMP_SPIRV},
442 {"vmfaults", RADV_DEBUG_VM_FAULTS},
443 {"zerovram", RADV_DEBUG_ZERO_VRAM},
444 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
445 {"nosisched", RADV_DEBUG_NO_SISCHED},
446 {"preoptir", RADV_DEBUG_PREOPTIR},
447 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
448 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
449 {"info", RADV_DEBUG_INFO},
450 {"errors", RADV_DEBUG_ERRORS},
451 {"startup", RADV_DEBUG_STARTUP},
452 {"checkir", RADV_DEBUG_CHECKIR},
453 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
454 {NULL, 0}
455 };
456
457 const char *
458 radv_get_debug_option_name(int id)
459 {
460 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
461 return radv_debug_options[id].string;
462 }
463
464 static const struct debug_control radv_perftest_options[] = {
465 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
466 {"sisched", RADV_PERFTEST_SISCHED},
467 {"localbos", RADV_PERFTEST_LOCAL_BOS},
468 {"binning", RADV_PERFTEST_BINNING},
469 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
470 {NULL, 0}
471 };
472
473 const char *
474 radv_get_perftest_option_name(int id)
475 {
476 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
477 return radv_perftest_options[id].string;
478 }
479
480 static void
481 radv_handle_per_app_options(struct radv_instance *instance,
482 const VkApplicationInfo *info)
483 {
484 const char *name = info ? info->pApplicationName : NULL;
485
486 if (!name)
487 return;
488
489 if (!strcmp(name, "Talos - Linux - 32bit") ||
490 !strcmp(name, "Talos - Linux - 64bit")) {
491 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
492 /* Force enable LLVM sisched for Talos because it looks
493 * safe and it gives few more FPS.
494 */
495 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
496 }
497 } else if (!strcmp(name, "DOOM_VFR")) {
498 /* Work around a Doom VFR game bug */
499 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
500 }
501 }
502
503 static int radv_get_instance_extension_index(const char *name)
504 {
505 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
506 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
507 return i;
508 }
509 return -1;
510 }
511
512
513 VkResult radv_CreateInstance(
514 const VkInstanceCreateInfo* pCreateInfo,
515 const VkAllocationCallbacks* pAllocator,
516 VkInstance* pInstance)
517 {
518 struct radv_instance *instance;
519 VkResult result;
520
521 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
522
523 uint32_t client_version;
524 if (pCreateInfo->pApplicationInfo &&
525 pCreateInfo->pApplicationInfo->apiVersion != 0) {
526 client_version = pCreateInfo->pApplicationInfo->apiVersion;
527 } else {
528 radv_EnumerateInstanceVersion(&client_version);
529 }
530
531 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
532 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
533 if (!instance)
534 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
535
536 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
537
538 if (pAllocator)
539 instance->alloc = *pAllocator;
540 else
541 instance->alloc = default_alloc;
542
543 instance->apiVersion = client_version;
544 instance->physicalDeviceCount = -1;
545
546 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
547 radv_debug_options);
548
549 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
550 radv_perftest_options);
551
552
553 if (instance->debug_flags & RADV_DEBUG_STARTUP)
554 radv_logi("Created an instance");
555
556 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
557 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
558 int index = radv_get_instance_extension_index(ext_name);
559
560 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
561 vk_free2(&default_alloc, pAllocator, instance);
562 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
563 }
564
565 instance->enabled_extensions.extensions[index] = true;
566 }
567
568 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
569 if (result != VK_SUCCESS) {
570 vk_free2(&default_alloc, pAllocator, instance);
571 return vk_error(instance, result);
572 }
573
574 _mesa_locale_init();
575
576 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
577
578 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
579
580 *pInstance = radv_instance_to_handle(instance);
581
582 return VK_SUCCESS;
583 }
584
585 void radv_DestroyInstance(
586 VkInstance _instance,
587 const VkAllocationCallbacks* pAllocator)
588 {
589 RADV_FROM_HANDLE(radv_instance, instance, _instance);
590
591 if (!instance)
592 return;
593
594 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
595 radv_physical_device_finish(instance->physicalDevices + i);
596 }
597
598 VG(VALGRIND_DESTROY_MEMPOOL(instance));
599
600 _mesa_locale_fini();
601
602 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
603
604 vk_free(&instance->alloc, instance);
605 }
606
607 static VkResult
608 radv_enumerate_devices(struct radv_instance *instance)
609 {
610 /* TODO: Check for more devices ? */
611 drmDevicePtr devices[8];
612 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
613 int max_devices;
614
615 instance->physicalDeviceCount = 0;
616
617 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
618
619 if (instance->debug_flags & RADV_DEBUG_STARTUP)
620 radv_logi("Found %d drm nodes", max_devices);
621
622 if (max_devices < 1)
623 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
624
625 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
626 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
627 devices[i]->bustype == DRM_BUS_PCI &&
628 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
629
630 result = radv_physical_device_init(instance->physicalDevices +
631 instance->physicalDeviceCount,
632 instance,
633 devices[i]);
634 if (result == VK_SUCCESS)
635 ++instance->physicalDeviceCount;
636 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
637 break;
638 }
639 }
640 drmFreeDevices(devices, max_devices);
641
642 return result;
643 }
644
645 VkResult radv_EnumeratePhysicalDevices(
646 VkInstance _instance,
647 uint32_t* pPhysicalDeviceCount,
648 VkPhysicalDevice* pPhysicalDevices)
649 {
650 RADV_FROM_HANDLE(radv_instance, instance, _instance);
651 VkResult result;
652
653 if (instance->physicalDeviceCount < 0) {
654 result = radv_enumerate_devices(instance);
655 if (result != VK_SUCCESS &&
656 result != VK_ERROR_INCOMPATIBLE_DRIVER)
657 return result;
658 }
659
660 if (!pPhysicalDevices) {
661 *pPhysicalDeviceCount = instance->physicalDeviceCount;
662 } else {
663 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
664 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
665 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
666 }
667
668 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
669 : VK_SUCCESS;
670 }
671
672 VkResult radv_EnumeratePhysicalDeviceGroups(
673 VkInstance _instance,
674 uint32_t* pPhysicalDeviceGroupCount,
675 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
676 {
677 RADV_FROM_HANDLE(radv_instance, instance, _instance);
678 VkResult result;
679
680 if (instance->physicalDeviceCount < 0) {
681 result = radv_enumerate_devices(instance);
682 if (result != VK_SUCCESS &&
683 result != VK_ERROR_INCOMPATIBLE_DRIVER)
684 return result;
685 }
686
687 if (!pPhysicalDeviceGroupProperties) {
688 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
689 } else {
690 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
691 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
692 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
693 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
694 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
695 }
696 }
697 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
698 : VK_SUCCESS;
699 }
700
701 void radv_GetPhysicalDeviceFeatures(
702 VkPhysicalDevice physicalDevice,
703 VkPhysicalDeviceFeatures* pFeatures)
704 {
705 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
706 memset(pFeatures, 0, sizeof(*pFeatures));
707
708 *pFeatures = (VkPhysicalDeviceFeatures) {
709 .robustBufferAccess = true,
710 .fullDrawIndexUint32 = true,
711 .imageCubeArray = true,
712 .independentBlend = true,
713 .geometryShader = true,
714 .tessellationShader = true,
715 .sampleRateShading = true,
716 .dualSrcBlend = true,
717 .logicOp = true,
718 .multiDrawIndirect = true,
719 .drawIndirectFirstInstance = true,
720 .depthClamp = true,
721 .depthBiasClamp = true,
722 .fillModeNonSolid = true,
723 .depthBounds = true,
724 .wideLines = true,
725 .largePoints = true,
726 .alphaToOne = true,
727 .multiViewport = true,
728 .samplerAnisotropy = true,
729 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
730 pdevice->rad_info.family == CHIP_STONEY,
731 .textureCompressionASTC_LDR = false,
732 .textureCompressionBC = true,
733 .occlusionQueryPrecise = true,
734 .pipelineStatisticsQuery = true,
735 .vertexPipelineStoresAndAtomics = true,
736 .fragmentStoresAndAtomics = true,
737 .shaderTessellationAndGeometryPointSize = true,
738 .shaderImageGatherExtended = true,
739 .shaderStorageImageExtendedFormats = true,
740 .shaderStorageImageMultisample = false,
741 .shaderUniformBufferArrayDynamicIndexing = true,
742 .shaderSampledImageArrayDynamicIndexing = true,
743 .shaderStorageBufferArrayDynamicIndexing = true,
744 .shaderStorageImageArrayDynamicIndexing = true,
745 .shaderStorageImageReadWithoutFormat = true,
746 .shaderStorageImageWriteWithoutFormat = true,
747 .shaderClipDistance = true,
748 .shaderCullDistance = true,
749 .shaderFloat64 = true,
750 .shaderInt64 = true,
751 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && HAVE_LLVM >= 0x700,
752 .sparseBinding = true,
753 .variableMultisampleRate = true,
754 .inheritedQueries = true,
755 };
756 }
757
758 void radv_GetPhysicalDeviceFeatures2(
759 VkPhysicalDevice physicalDevice,
760 VkPhysicalDeviceFeatures2KHR *pFeatures)
761 {
762 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
763 vk_foreach_struct(ext, pFeatures->pNext) {
764 switch (ext->sType) {
765 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
766 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
767 features->variablePointersStorageBuffer = true;
768 features->variablePointers = false;
769 break;
770 }
771 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
772 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
773 features->multiview = true;
774 features->multiviewGeometryShader = true;
775 features->multiviewTessellationShader = true;
776 break;
777 }
778 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
779 VkPhysicalDeviceShaderDrawParameterFeatures *features =
780 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
781 features->shaderDrawParameters = true;
782 break;
783 }
784 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
785 VkPhysicalDeviceProtectedMemoryFeatures *features =
786 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
787 features->protectedMemory = false;
788 break;
789 }
790 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
791 VkPhysicalDevice16BitStorageFeatures *features =
792 (VkPhysicalDevice16BitStorageFeatures*)ext;
793 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
794 features->storageBuffer16BitAccess = enabled;
795 features->uniformAndStorageBuffer16BitAccess = enabled;
796 features->storagePushConstant16 = enabled;
797 features->storageInputOutput16 = enabled;
798 break;
799 }
800 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
801 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
802 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
803 features->samplerYcbcrConversion = false;
804 break;
805 }
806 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
807 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
808 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
809 features->shaderInputAttachmentArrayDynamicIndexing = true;
810 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
811 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
812 features->shaderUniformBufferArrayNonUniformIndexing = false;
813 features->shaderSampledImageArrayNonUniformIndexing = false;
814 features->shaderStorageBufferArrayNonUniformIndexing = false;
815 features->shaderStorageImageArrayNonUniformIndexing = false;
816 features->shaderInputAttachmentArrayNonUniformIndexing = false;
817 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
818 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
819 features->descriptorBindingUniformBufferUpdateAfterBind = true;
820 features->descriptorBindingSampledImageUpdateAfterBind = true;
821 features->descriptorBindingStorageImageUpdateAfterBind = true;
822 features->descriptorBindingStorageBufferUpdateAfterBind = true;
823 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
824 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
825 features->descriptorBindingUpdateUnusedWhilePending = true;
826 features->descriptorBindingPartiallyBound = true;
827 features->descriptorBindingVariableDescriptorCount = true;
828 features->runtimeDescriptorArray = true;
829 break;
830 }
831 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
832 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
833 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
834 features->conditionalRendering = true;
835 features->inheritedConditionalRendering = false;
836 break;
837 }
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
839 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
840 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
841 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
842 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
843 break;
844 }
845 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
846 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
847 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
848 features->transformFeedback = true;
849 features->geometryStreams = true;
850 break;
851 }
852 default:
853 break;
854 }
855 }
856 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
857 }
858
859 void radv_GetPhysicalDeviceProperties(
860 VkPhysicalDevice physicalDevice,
861 VkPhysicalDeviceProperties* pProperties)
862 {
863 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
864 VkSampleCountFlags sample_counts = 0xf;
865
866 /* make sure that the entire descriptor set is addressable with a signed
867 * 32-bit int. So the sum of all limits scaled by descriptor size has to
868 * be at most 2 GiB. the combined image & samples object count as one of
869 * both. This limit is for the pipeline layout, not for the set layout, but
870 * there is no set limit, so we just set a pipeline limit. I don't think
871 * any app is going to hit this soon. */
872 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
873 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
874 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
875 32 /* sampler, largest when combined with image */ +
876 64 /* sampled image */ +
877 64 /* storage image */);
878
879 VkPhysicalDeviceLimits limits = {
880 .maxImageDimension1D = (1 << 14),
881 .maxImageDimension2D = (1 << 14),
882 .maxImageDimension3D = (1 << 11),
883 .maxImageDimensionCube = (1 << 14),
884 .maxImageArrayLayers = (1 << 11),
885 .maxTexelBufferElements = 128 * 1024 * 1024,
886 .maxUniformBufferRange = UINT32_MAX,
887 .maxStorageBufferRange = UINT32_MAX,
888 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
889 .maxMemoryAllocationCount = UINT32_MAX,
890 .maxSamplerAllocationCount = 64 * 1024,
891 .bufferImageGranularity = 64, /* A cache line */
892 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
893 .maxBoundDescriptorSets = MAX_SETS,
894 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
895 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
896 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
897 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
898 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
899 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
900 .maxPerStageResources = max_descriptor_set_size,
901 .maxDescriptorSetSamplers = max_descriptor_set_size,
902 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
903 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
904 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
905 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
906 .maxDescriptorSetSampledImages = max_descriptor_set_size,
907 .maxDescriptorSetStorageImages = max_descriptor_set_size,
908 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
909 .maxVertexInputAttributes = 32,
910 .maxVertexInputBindings = 32,
911 .maxVertexInputAttributeOffset = 2047,
912 .maxVertexInputBindingStride = 2048,
913 .maxVertexOutputComponents = 128,
914 .maxTessellationGenerationLevel = 64,
915 .maxTessellationPatchSize = 32,
916 .maxTessellationControlPerVertexInputComponents = 128,
917 .maxTessellationControlPerVertexOutputComponents = 128,
918 .maxTessellationControlPerPatchOutputComponents = 120,
919 .maxTessellationControlTotalOutputComponents = 4096,
920 .maxTessellationEvaluationInputComponents = 128,
921 .maxTessellationEvaluationOutputComponents = 128,
922 .maxGeometryShaderInvocations = 127,
923 .maxGeometryInputComponents = 64,
924 .maxGeometryOutputComponents = 128,
925 .maxGeometryOutputVertices = 256,
926 .maxGeometryTotalOutputComponents = 1024,
927 .maxFragmentInputComponents = 128,
928 .maxFragmentOutputAttachments = 8,
929 .maxFragmentDualSrcAttachments = 1,
930 .maxFragmentCombinedOutputResources = 8,
931 .maxComputeSharedMemorySize = 32768,
932 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
933 .maxComputeWorkGroupInvocations = 2048,
934 .maxComputeWorkGroupSize = {
935 2048,
936 2048,
937 2048
938 },
939 .subPixelPrecisionBits = 4 /* FIXME */,
940 .subTexelPrecisionBits = 4 /* FIXME */,
941 .mipmapPrecisionBits = 4 /* FIXME */,
942 .maxDrawIndexedIndexValue = UINT32_MAX,
943 .maxDrawIndirectCount = UINT32_MAX,
944 .maxSamplerLodBias = 16,
945 .maxSamplerAnisotropy = 16,
946 .maxViewports = MAX_VIEWPORTS,
947 .maxViewportDimensions = { (1 << 14), (1 << 14) },
948 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
949 .viewportSubPixelBits = 8,
950 .minMemoryMapAlignment = 4096, /* A page */
951 .minTexelBufferOffsetAlignment = 1,
952 .minUniformBufferOffsetAlignment = 4,
953 .minStorageBufferOffsetAlignment = 4,
954 .minTexelOffset = -32,
955 .maxTexelOffset = 31,
956 .minTexelGatherOffset = -32,
957 .maxTexelGatherOffset = 31,
958 .minInterpolationOffset = -2,
959 .maxInterpolationOffset = 2,
960 .subPixelInterpolationOffsetBits = 8,
961 .maxFramebufferWidth = (1 << 14),
962 .maxFramebufferHeight = (1 << 14),
963 .maxFramebufferLayers = (1 << 10),
964 .framebufferColorSampleCounts = sample_counts,
965 .framebufferDepthSampleCounts = sample_counts,
966 .framebufferStencilSampleCounts = sample_counts,
967 .framebufferNoAttachmentsSampleCounts = sample_counts,
968 .maxColorAttachments = MAX_RTS,
969 .sampledImageColorSampleCounts = sample_counts,
970 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
971 .sampledImageDepthSampleCounts = sample_counts,
972 .sampledImageStencilSampleCounts = sample_counts,
973 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
974 .maxSampleMaskWords = 1,
975 .timestampComputeAndGraphics = true,
976 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
977 .maxClipDistances = 8,
978 .maxCullDistances = 8,
979 .maxCombinedClipAndCullDistances = 8,
980 .discreteQueuePriorities = 2,
981 .pointSizeRange = { 0.125, 255.875 },
982 .lineWidthRange = { 0.0, 7.9921875 },
983 .pointSizeGranularity = (1.0 / 8.0),
984 .lineWidthGranularity = (1.0 / 128.0),
985 .strictLines = false, /* FINISHME */
986 .standardSampleLocations = true,
987 .optimalBufferCopyOffsetAlignment = 128,
988 .optimalBufferCopyRowPitchAlignment = 128,
989 .nonCoherentAtomSize = 64,
990 };
991
992 *pProperties = (VkPhysicalDeviceProperties) {
993 .apiVersion = radv_physical_device_api_version(pdevice),
994 .driverVersion = vk_get_driver_version(),
995 .vendorID = ATI_VENDOR_ID,
996 .deviceID = pdevice->rad_info.pci_id,
997 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
998 .limits = limits,
999 .sparseProperties = {0},
1000 };
1001
1002 strcpy(pProperties->deviceName, pdevice->name);
1003 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1004 }
1005
1006 void radv_GetPhysicalDeviceProperties2(
1007 VkPhysicalDevice physicalDevice,
1008 VkPhysicalDeviceProperties2KHR *pProperties)
1009 {
1010 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1011 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1012
1013 vk_foreach_struct(ext, pProperties->pNext) {
1014 switch (ext->sType) {
1015 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1016 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1017 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1018 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1019 break;
1020 }
1021 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
1022 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
1023 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1024 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1025 properties->deviceLUIDValid = false;
1026 break;
1027 }
1028 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1029 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1030 properties->maxMultiviewViewCount = MAX_VIEWS;
1031 properties->maxMultiviewInstanceIndex = INT_MAX;
1032 break;
1033 }
1034 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1035 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1036 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1037 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1038 break;
1039 }
1040 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1041 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1042 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1043 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1044 break;
1045 }
1046 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1047 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1048 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1049 properties->minImportedHostPointerAlignment = 4096;
1050 break;
1051 }
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1053 VkPhysicalDeviceSubgroupProperties *properties =
1054 (VkPhysicalDeviceSubgroupProperties*)ext;
1055 properties->subgroupSize = 64;
1056 properties->supportedStages = VK_SHADER_STAGE_ALL;
1057 /* TODO: Enable VK_SUBGROUP_FEATURE_VOTE_BIT when wwm
1058 * is fixed in LLVM.
1059 */
1060 properties->supportedOperations =
1061 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1062 VK_SUBGROUP_FEATURE_BASIC_BIT |
1063 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1064 VK_SUBGROUP_FEATURE_QUAD_BIT;
1065 if (pdevice->rad_info.chip_class >= VI) {
1066 properties->supportedOperations |=
1067 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1068 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1069 }
1070 properties->quadOperationsInAllStages = true;
1071 break;
1072 }
1073 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1074 VkPhysicalDeviceMaintenance3Properties *properties =
1075 (VkPhysicalDeviceMaintenance3Properties*)ext;
1076 /* Make sure everything is addressable by a signed 32-bit int, and
1077 * our largest descriptors are 96 bytes. */
1078 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1079 /* Our buffer size fields allow only this much */
1080 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1081 break;
1082 }
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1084 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1085 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1086 /* GFX6-8 only support single channel min/max filter. */
1087 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1088 properties->filterMinmaxSingleComponentFormats = true;
1089 break;
1090 }
1091 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1092 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1093 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1094
1095 /* Shader engines. */
1096 properties->shaderEngineCount =
1097 pdevice->rad_info.max_se;
1098 properties->shaderArraysPerEngineCount =
1099 pdevice->rad_info.max_sh_per_se;
1100 properties->computeUnitsPerShaderArray =
1101 pdevice->rad_info.num_good_compute_units /
1102 (pdevice->rad_info.max_se *
1103 pdevice->rad_info.max_sh_per_se);
1104 properties->simdPerComputeUnit = 4;
1105 properties->wavefrontsPerSimd =
1106 pdevice->rad_info.family == CHIP_TONGA ||
1107 pdevice->rad_info.family == CHIP_ICELAND ||
1108 pdevice->rad_info.family == CHIP_POLARIS10 ||
1109 pdevice->rad_info.family == CHIP_POLARIS11 ||
1110 pdevice->rad_info.family == CHIP_POLARIS12 ||
1111 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1112 properties->wavefrontSize = 64;
1113
1114 /* SGPR. */
1115 properties->sgprsPerSimd =
1116 radv_get_num_physical_sgprs(pdevice);
1117 properties->minSgprAllocation =
1118 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1119 properties->maxSgprAllocation =
1120 pdevice->rad_info.family == CHIP_TONGA ||
1121 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1122 properties->sgprAllocationGranularity =
1123 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1124
1125 /* VGPR. */
1126 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1127 properties->minVgprAllocation = 4;
1128 properties->maxVgprAllocation = 256;
1129 properties->vgprAllocationGranularity = 4;
1130 break;
1131 }
1132 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1133 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1134 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1135 properties->maxVertexAttribDivisor = UINT32_MAX;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1139 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1140 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1141 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1142 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1143 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1144 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1145 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1146 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1147 properties->robustBufferAccessUpdateAfterBind = false;
1148 properties->quadDivergentImplicitLod = false;
1149
1150 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1151 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1152 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1153 32 /* sampler, largest when combined with image */ +
1154 64 /* sampled image */ +
1155 64 /* storage image */);
1156 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1157 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1158 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1159 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1160 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1161 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1162 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1163 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1164 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1165 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1166 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1167 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1168 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1169 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1170 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1171 break;
1172 }
1173 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1174 VkPhysicalDeviceProtectedMemoryProperties *properties =
1175 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1176 properties->protectedNoFault = false;
1177 break;
1178 }
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1180 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1181 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1182 properties->primitiveOverestimationSize = 0;
1183 properties->maxExtraPrimitiveOverestimationSize = 0;
1184 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1185 properties->primitiveUnderestimation = VK_FALSE;
1186 properties->conservativePointAndLineRasterization = VK_FALSE;
1187 properties->degenerateTrianglesRasterized = VK_FALSE;
1188 properties->degenerateLinesRasterized = VK_FALSE;
1189 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1190 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1191 break;
1192 }
1193 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1194 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1195 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1196 properties->pciDomain = pdevice->bus_info.domain;
1197 properties->pciBus = pdevice->bus_info.bus;
1198 properties->pciDevice = pdevice->bus_info.dev;
1199 properties->pciFunction = pdevice->bus_info.func;
1200 break;
1201 }
1202 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1203 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1204 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1205
1206 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1207 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1208 strcpy(driver_props->driverName, "radv");
1209
1210 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1211 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1212 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1213 " (LLVM %d.%d.%d)",
1214 (HAVE_LLVM >> 8) & 0xff, HAVE_LLVM & 0xff,
1215 MESA_LLVM_VERSION_PATCH);
1216
1217 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1218 .major = 1,
1219 .minor = 1,
1220 .subminor = 2,
1221 .patch = 0,
1222 };
1223 break;
1224 }
1225 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1226 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1227 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1228 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1229 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1230 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1231 properties->maxTransformFeedbackStreamDataSize = 512;
1232 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1233 properties->maxTransformFeedbackBufferDataStride = 512;
1234 properties->transformFeedbackQueries = true;
1235 properties->transformFeedbackStreamsLinesTriangles = false;
1236 properties->transformFeedbackRasterizationStreamSelect = false;
1237 properties->transformFeedbackDraw = true;
1238 break;
1239 }
1240 default:
1241 break;
1242 }
1243 }
1244 }
1245
1246 static void radv_get_physical_device_queue_family_properties(
1247 struct radv_physical_device* pdevice,
1248 uint32_t* pCount,
1249 VkQueueFamilyProperties** pQueueFamilyProperties)
1250 {
1251 int num_queue_families = 1;
1252 int idx;
1253 if (pdevice->rad_info.num_compute_rings > 0 &&
1254 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1255 num_queue_families++;
1256
1257 if (pQueueFamilyProperties == NULL) {
1258 *pCount = num_queue_families;
1259 return;
1260 }
1261
1262 if (!*pCount)
1263 return;
1264
1265 idx = 0;
1266 if (*pCount >= 1) {
1267 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1268 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1269 VK_QUEUE_COMPUTE_BIT |
1270 VK_QUEUE_TRANSFER_BIT |
1271 VK_QUEUE_SPARSE_BINDING_BIT,
1272 .queueCount = 1,
1273 .timestampValidBits = 64,
1274 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1275 };
1276 idx++;
1277 }
1278
1279 if (pdevice->rad_info.num_compute_rings > 0 &&
1280 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1281 if (*pCount > idx) {
1282 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1283 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1284 VK_QUEUE_TRANSFER_BIT |
1285 VK_QUEUE_SPARSE_BINDING_BIT,
1286 .queueCount = pdevice->rad_info.num_compute_rings,
1287 .timestampValidBits = 64,
1288 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1289 };
1290 idx++;
1291 }
1292 }
1293 *pCount = idx;
1294 }
1295
1296 void radv_GetPhysicalDeviceQueueFamilyProperties(
1297 VkPhysicalDevice physicalDevice,
1298 uint32_t* pCount,
1299 VkQueueFamilyProperties* pQueueFamilyProperties)
1300 {
1301 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1302 if (!pQueueFamilyProperties) {
1303 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1304 return;
1305 }
1306 VkQueueFamilyProperties *properties[] = {
1307 pQueueFamilyProperties + 0,
1308 pQueueFamilyProperties + 1,
1309 pQueueFamilyProperties + 2,
1310 };
1311 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1312 assert(*pCount <= 3);
1313 }
1314
1315 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1316 VkPhysicalDevice physicalDevice,
1317 uint32_t* pCount,
1318 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1319 {
1320 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1321 if (!pQueueFamilyProperties) {
1322 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1323 return;
1324 }
1325 VkQueueFamilyProperties *properties[] = {
1326 &pQueueFamilyProperties[0].queueFamilyProperties,
1327 &pQueueFamilyProperties[1].queueFamilyProperties,
1328 &pQueueFamilyProperties[2].queueFamilyProperties,
1329 };
1330 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1331 assert(*pCount <= 3);
1332 }
1333
1334 void radv_GetPhysicalDeviceMemoryProperties(
1335 VkPhysicalDevice physicalDevice,
1336 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1337 {
1338 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1339
1340 *pMemoryProperties = physical_device->memory_properties;
1341 }
1342
1343 void radv_GetPhysicalDeviceMemoryProperties2(
1344 VkPhysicalDevice physicalDevice,
1345 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1346 {
1347 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1348 &pMemoryProperties->memoryProperties);
1349 }
1350
1351 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1352 VkDevice _device,
1353 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1354 const void *pHostPointer,
1355 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1356 {
1357 RADV_FROM_HANDLE(radv_device, device, _device);
1358
1359 switch (handleType)
1360 {
1361 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1362 const struct radv_physical_device *physical_device = device->physical_device;
1363 uint32_t memoryTypeBits = 0;
1364 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1365 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1366 memoryTypeBits = (1 << i);
1367 break;
1368 }
1369 }
1370 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1371 return VK_SUCCESS;
1372 }
1373 default:
1374 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1375 }
1376 }
1377
1378 static enum radeon_ctx_priority
1379 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1380 {
1381 /* Default to MEDIUM when a specific global priority isn't requested */
1382 if (!pObj)
1383 return RADEON_CTX_PRIORITY_MEDIUM;
1384
1385 switch(pObj->globalPriority) {
1386 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1387 return RADEON_CTX_PRIORITY_REALTIME;
1388 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1389 return RADEON_CTX_PRIORITY_HIGH;
1390 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1391 return RADEON_CTX_PRIORITY_MEDIUM;
1392 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1393 return RADEON_CTX_PRIORITY_LOW;
1394 default:
1395 unreachable("Illegal global priority value");
1396 return RADEON_CTX_PRIORITY_INVALID;
1397 }
1398 }
1399
1400 static int
1401 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1402 uint32_t queue_family_index, int idx,
1403 VkDeviceQueueCreateFlags flags,
1404 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1405 {
1406 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1407 queue->device = device;
1408 queue->queue_family_index = queue_family_index;
1409 queue->queue_idx = idx;
1410 queue->priority = radv_get_queue_global_priority(global_priority);
1411 queue->flags = flags;
1412
1413 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1414 if (!queue->hw_ctx)
1415 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1416
1417 return VK_SUCCESS;
1418 }
1419
1420 static void
1421 radv_queue_finish(struct radv_queue *queue)
1422 {
1423 if (queue->hw_ctx)
1424 queue->device->ws->ctx_destroy(queue->hw_ctx);
1425
1426 if (queue->initial_full_flush_preamble_cs)
1427 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1428 if (queue->initial_preamble_cs)
1429 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1430 if (queue->continue_preamble_cs)
1431 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1432 if (queue->descriptor_bo)
1433 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1434 if (queue->scratch_bo)
1435 queue->device->ws->buffer_destroy(queue->scratch_bo);
1436 if (queue->esgs_ring_bo)
1437 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1438 if (queue->gsvs_ring_bo)
1439 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1440 if (queue->tess_rings_bo)
1441 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1442 if (queue->compute_scratch_bo)
1443 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1444 }
1445
1446 static void
1447 radv_bo_list_init(struct radv_bo_list *bo_list)
1448 {
1449 pthread_mutex_init(&bo_list->mutex, NULL);
1450 bo_list->list.count = bo_list->capacity = 0;
1451 bo_list->list.bos = NULL;
1452 }
1453
1454 static void
1455 radv_bo_list_finish(struct radv_bo_list *bo_list)
1456 {
1457 free(bo_list->list.bos);
1458 pthread_mutex_destroy(&bo_list->mutex);
1459 }
1460
1461 static VkResult radv_bo_list_add(struct radv_device *device,
1462 struct radeon_winsys_bo *bo)
1463 {
1464 struct radv_bo_list *bo_list = &device->bo_list;
1465
1466 if (unlikely(!device->use_global_bo_list))
1467 return VK_SUCCESS;
1468
1469 pthread_mutex_lock(&bo_list->mutex);
1470 if (bo_list->list.count == bo_list->capacity) {
1471 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1472 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1473
1474 if (!data) {
1475 pthread_mutex_unlock(&bo_list->mutex);
1476 return VK_ERROR_OUT_OF_HOST_MEMORY;
1477 }
1478
1479 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1480 bo_list->capacity = capacity;
1481 }
1482
1483 bo_list->list.bos[bo_list->list.count++] = bo;
1484 pthread_mutex_unlock(&bo_list->mutex);
1485 return VK_SUCCESS;
1486 }
1487
1488 static void radv_bo_list_remove(struct radv_device *device,
1489 struct radeon_winsys_bo *bo)
1490 {
1491 struct radv_bo_list *bo_list = &device->bo_list;
1492
1493 if (unlikely(!device->use_global_bo_list))
1494 return;
1495
1496 pthread_mutex_lock(&bo_list->mutex);
1497 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1498 if (bo_list->list.bos[i] == bo) {
1499 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1500 --bo_list->list.count;
1501 break;
1502 }
1503 }
1504 pthread_mutex_unlock(&bo_list->mutex);
1505 }
1506
1507 static void
1508 radv_device_init_gs_info(struct radv_device *device)
1509 {
1510 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1511 device->physical_device->rad_info.family);
1512 }
1513
1514 static int radv_get_device_extension_index(const char *name)
1515 {
1516 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1517 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1518 return i;
1519 }
1520 return -1;
1521 }
1522
1523 static int
1524 radv_get_int_debug_option(const char *name, int default_value)
1525 {
1526 const char *str;
1527 int result;
1528
1529 str = getenv(name);
1530 if (!str) {
1531 result = default_value;
1532 } else {
1533 char *endptr;
1534
1535 result = strtol(str, &endptr, 0);
1536 if (str == endptr) {
1537 /* No digits founs. */
1538 result = default_value;
1539 }
1540 }
1541
1542 return result;
1543 }
1544
1545 VkResult radv_CreateDevice(
1546 VkPhysicalDevice physicalDevice,
1547 const VkDeviceCreateInfo* pCreateInfo,
1548 const VkAllocationCallbacks* pAllocator,
1549 VkDevice* pDevice)
1550 {
1551 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1552 VkResult result;
1553 struct radv_device *device;
1554
1555 bool keep_shader_info = false;
1556
1557 /* Check enabled features */
1558 if (pCreateInfo->pEnabledFeatures) {
1559 VkPhysicalDeviceFeatures supported_features;
1560 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1561 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1562 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1563 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1564 for (uint32_t i = 0; i < num_features; i++) {
1565 if (enabled_feature[i] && !supported_feature[i])
1566 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1567 }
1568 }
1569
1570 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1571 sizeof(*device), 8,
1572 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1573 if (!device)
1574 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1575
1576 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1577 device->instance = physical_device->instance;
1578 device->physical_device = physical_device;
1579
1580 device->ws = physical_device->ws;
1581 if (pAllocator)
1582 device->alloc = *pAllocator;
1583 else
1584 device->alloc = physical_device->instance->alloc;
1585
1586 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1587 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1588 int index = radv_get_device_extension_index(ext_name);
1589 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1590 vk_free(&device->alloc, device);
1591 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1592 }
1593
1594 device->enabled_extensions.extensions[index] = true;
1595 }
1596
1597 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1598
1599 /* With update after bind we can't attach bo's to the command buffer
1600 * from the descriptor set anymore, so we have to use a global BO list.
1601 */
1602 device->use_global_bo_list =
1603 device->enabled_extensions.EXT_descriptor_indexing;
1604
1605 mtx_init(&device->shader_slab_mutex, mtx_plain);
1606 list_inithead(&device->shader_slabs);
1607
1608 radv_bo_list_init(&device->bo_list);
1609
1610 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1611 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1612 uint32_t qfi = queue_create->queueFamilyIndex;
1613 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1614 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1615
1616 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1617
1618 device->queues[qfi] = vk_alloc(&device->alloc,
1619 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1620 if (!device->queues[qfi]) {
1621 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1622 goto fail;
1623 }
1624
1625 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1626
1627 device->queue_count[qfi] = queue_create->queueCount;
1628
1629 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1630 result = radv_queue_init(device, &device->queues[qfi][q],
1631 qfi, q, queue_create->flags,
1632 global_priority);
1633 if (result != VK_SUCCESS)
1634 goto fail;
1635 }
1636 }
1637
1638 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1639 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1640 device->physical_device->rad_info.family == CHIP_RAVEN ||
1641 device->physical_device->rad_info.family == CHIP_RAVEN2);
1642
1643 /* Disabled and not implemented for now. */
1644 device->dfsm_allowed = device->pbb_allowed &&
1645 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1646 device->physical_device->rad_info.family == CHIP_RAVEN2);
1647
1648 #ifdef ANDROID
1649 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1650 #endif
1651
1652 /* The maximum number of scratch waves. Scratch space isn't divided
1653 * evenly between CUs. The number is only a function of the number of CUs.
1654 * We can decrease the constant to decrease the scratch buffer size.
1655 *
1656 * sctx->scratch_waves must be >= the maximum possible size of
1657 * 1 threadgroup, so that the hw doesn't hang from being unable
1658 * to start any.
1659 *
1660 * The recommended value is 4 per CU at most. Higher numbers don't
1661 * bring much benefit, but they still occupy chip resources (think
1662 * async compute). I've seen ~2% performance difference between 4 and 32.
1663 */
1664 uint32_t max_threads_per_block = 2048;
1665 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1666 max_threads_per_block / 64);
1667
1668 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1669
1670 if (device->physical_device->rad_info.chip_class >= CIK) {
1671 /* If the KMD allows it (there is a KMD hw register for it),
1672 * allow launching waves out-of-order.
1673 */
1674 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1675 }
1676
1677 radv_device_init_gs_info(device);
1678
1679 device->tess_offchip_block_dw_size =
1680 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1681 device->has_distributed_tess =
1682 device->physical_device->rad_info.chip_class >= VI &&
1683 device->physical_device->rad_info.max_se >= 2;
1684
1685 if (getenv("RADV_TRACE_FILE")) {
1686 const char *filename = getenv("RADV_TRACE_FILE");
1687
1688 keep_shader_info = true;
1689
1690 if (!radv_init_trace(device))
1691 goto fail;
1692
1693 fprintf(stderr, "*****************************************************************************\n");
1694 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1695 fprintf(stderr, "*****************************************************************************\n");
1696
1697 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1698 radv_dump_enabled_options(device, stderr);
1699 }
1700
1701 device->keep_shader_info = keep_shader_info;
1702
1703 result = radv_device_init_meta(device);
1704 if (result != VK_SUCCESS)
1705 goto fail;
1706
1707 radv_device_init_msaa(device);
1708
1709 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1710 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1711 switch (family) {
1712 case RADV_QUEUE_GENERAL:
1713 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1714 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1715 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1716 break;
1717 case RADV_QUEUE_COMPUTE:
1718 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1719 radeon_emit(device->empty_cs[family], 0);
1720 break;
1721 }
1722 device->ws->cs_finalize(device->empty_cs[family]);
1723 }
1724
1725 if (device->physical_device->rad_info.chip_class >= CIK)
1726 cik_create_gfx_config(device);
1727
1728 VkPipelineCacheCreateInfo ci;
1729 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1730 ci.pNext = NULL;
1731 ci.flags = 0;
1732 ci.pInitialData = NULL;
1733 ci.initialDataSize = 0;
1734 VkPipelineCache pc;
1735 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1736 &ci, NULL, &pc);
1737 if (result != VK_SUCCESS)
1738 goto fail_meta;
1739
1740 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1741
1742 device->force_aniso =
1743 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1744 if (device->force_aniso >= 0) {
1745 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1746 1 << util_logbase2(device->force_aniso));
1747 }
1748
1749 *pDevice = radv_device_to_handle(device);
1750 return VK_SUCCESS;
1751
1752 fail_meta:
1753 radv_device_finish_meta(device);
1754 fail:
1755 radv_bo_list_finish(&device->bo_list);
1756
1757 if (device->trace_bo)
1758 device->ws->buffer_destroy(device->trace_bo);
1759
1760 if (device->gfx_init)
1761 device->ws->buffer_destroy(device->gfx_init);
1762
1763 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1764 for (unsigned q = 0; q < device->queue_count[i]; q++)
1765 radv_queue_finish(&device->queues[i][q]);
1766 if (device->queue_count[i])
1767 vk_free(&device->alloc, device->queues[i]);
1768 }
1769
1770 vk_free(&device->alloc, device);
1771 return result;
1772 }
1773
1774 void radv_DestroyDevice(
1775 VkDevice _device,
1776 const VkAllocationCallbacks* pAllocator)
1777 {
1778 RADV_FROM_HANDLE(radv_device, device, _device);
1779
1780 if (!device)
1781 return;
1782
1783 if (device->trace_bo)
1784 device->ws->buffer_destroy(device->trace_bo);
1785
1786 if (device->gfx_init)
1787 device->ws->buffer_destroy(device->gfx_init);
1788
1789 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1790 for (unsigned q = 0; q < device->queue_count[i]; q++)
1791 radv_queue_finish(&device->queues[i][q]);
1792 if (device->queue_count[i])
1793 vk_free(&device->alloc, device->queues[i]);
1794 if (device->empty_cs[i])
1795 device->ws->cs_destroy(device->empty_cs[i]);
1796 }
1797 radv_device_finish_meta(device);
1798
1799 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1800 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1801
1802 radv_destroy_shader_slabs(device);
1803
1804 radv_bo_list_finish(&device->bo_list);
1805 vk_free(&device->alloc, device);
1806 }
1807
1808 VkResult radv_EnumerateInstanceLayerProperties(
1809 uint32_t* pPropertyCount,
1810 VkLayerProperties* pProperties)
1811 {
1812 if (pProperties == NULL) {
1813 *pPropertyCount = 0;
1814 return VK_SUCCESS;
1815 }
1816
1817 /* None supported at this time */
1818 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1819 }
1820
1821 VkResult radv_EnumerateDeviceLayerProperties(
1822 VkPhysicalDevice physicalDevice,
1823 uint32_t* pPropertyCount,
1824 VkLayerProperties* pProperties)
1825 {
1826 if (pProperties == NULL) {
1827 *pPropertyCount = 0;
1828 return VK_SUCCESS;
1829 }
1830
1831 /* None supported at this time */
1832 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1833 }
1834
1835 void radv_GetDeviceQueue2(
1836 VkDevice _device,
1837 const VkDeviceQueueInfo2* pQueueInfo,
1838 VkQueue* pQueue)
1839 {
1840 RADV_FROM_HANDLE(radv_device, device, _device);
1841 struct radv_queue *queue;
1842
1843 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1844 if (pQueueInfo->flags != queue->flags) {
1845 /* From the Vulkan 1.1.70 spec:
1846 *
1847 * "The queue returned by vkGetDeviceQueue2 must have the same
1848 * flags value from this structure as that used at device
1849 * creation time in a VkDeviceQueueCreateInfo instance. If no
1850 * matching flags were specified at device creation time then
1851 * pQueue will return VK_NULL_HANDLE."
1852 */
1853 *pQueue = VK_NULL_HANDLE;
1854 return;
1855 }
1856
1857 *pQueue = radv_queue_to_handle(queue);
1858 }
1859
1860 void radv_GetDeviceQueue(
1861 VkDevice _device,
1862 uint32_t queueFamilyIndex,
1863 uint32_t queueIndex,
1864 VkQueue* pQueue)
1865 {
1866 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1867 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1868 .queueFamilyIndex = queueFamilyIndex,
1869 .queueIndex = queueIndex
1870 };
1871
1872 radv_GetDeviceQueue2(_device, &info, pQueue);
1873 }
1874
1875 static void
1876 fill_geom_tess_rings(struct radv_queue *queue,
1877 uint32_t *map,
1878 bool add_sample_positions,
1879 uint32_t esgs_ring_size,
1880 struct radeon_winsys_bo *esgs_ring_bo,
1881 uint32_t gsvs_ring_size,
1882 struct radeon_winsys_bo *gsvs_ring_bo,
1883 uint32_t tess_factor_ring_size,
1884 uint32_t tess_offchip_ring_offset,
1885 uint32_t tess_offchip_ring_size,
1886 struct radeon_winsys_bo *tess_rings_bo)
1887 {
1888 uint64_t esgs_va = 0, gsvs_va = 0;
1889 uint64_t tess_va = 0, tess_offchip_va = 0;
1890 uint32_t *desc = &map[4];
1891
1892 if (esgs_ring_bo)
1893 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1894 if (gsvs_ring_bo)
1895 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1896 if (tess_rings_bo) {
1897 tess_va = radv_buffer_get_va(tess_rings_bo);
1898 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1899 }
1900
1901 /* stride 0, num records - size, add tid, swizzle, elsize4,
1902 index stride 64 */
1903 desc[0] = esgs_va;
1904 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1905 S_008F04_STRIDE(0) |
1906 S_008F04_SWIZZLE_ENABLE(true);
1907 desc[2] = esgs_ring_size;
1908 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1909 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1910 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1911 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1912 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1913 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1914 S_008F0C_ELEMENT_SIZE(1) |
1915 S_008F0C_INDEX_STRIDE(3) |
1916 S_008F0C_ADD_TID_ENABLE(true);
1917
1918 desc += 4;
1919 /* GS entry for ES->GS ring */
1920 /* stride 0, num records - size, elsize0,
1921 index stride 0 */
1922 desc[0] = esgs_va;
1923 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1924 S_008F04_STRIDE(0) |
1925 S_008F04_SWIZZLE_ENABLE(false);
1926 desc[2] = esgs_ring_size;
1927 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1928 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1929 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1930 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1931 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1932 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1933 S_008F0C_ELEMENT_SIZE(0) |
1934 S_008F0C_INDEX_STRIDE(0) |
1935 S_008F0C_ADD_TID_ENABLE(false);
1936
1937 desc += 4;
1938 /* VS entry for GS->VS ring */
1939 /* stride 0, num records - size, elsize0,
1940 index stride 0 */
1941 desc[0] = gsvs_va;
1942 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1943 S_008F04_STRIDE(0) |
1944 S_008F04_SWIZZLE_ENABLE(false);
1945 desc[2] = gsvs_ring_size;
1946 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1947 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1948 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1949 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1950 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1951 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1952 S_008F0C_ELEMENT_SIZE(0) |
1953 S_008F0C_INDEX_STRIDE(0) |
1954 S_008F0C_ADD_TID_ENABLE(false);
1955 desc += 4;
1956
1957 /* stride gsvs_itemsize, num records 64
1958 elsize 4, index stride 16 */
1959 /* shader will patch stride and desc[2] */
1960 desc[0] = gsvs_va;
1961 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1962 S_008F04_STRIDE(0) |
1963 S_008F04_SWIZZLE_ENABLE(true);
1964 desc[2] = 0;
1965 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1966 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1967 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1968 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1969 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1970 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1971 S_008F0C_ELEMENT_SIZE(1) |
1972 S_008F0C_INDEX_STRIDE(1) |
1973 S_008F0C_ADD_TID_ENABLE(true);
1974 desc += 4;
1975
1976 desc[0] = tess_va;
1977 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1978 S_008F04_STRIDE(0) |
1979 S_008F04_SWIZZLE_ENABLE(false);
1980 desc[2] = tess_factor_ring_size;
1981 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1982 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1983 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1984 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1985 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1986 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1987 S_008F0C_ELEMENT_SIZE(0) |
1988 S_008F0C_INDEX_STRIDE(0) |
1989 S_008F0C_ADD_TID_ENABLE(false);
1990 desc += 4;
1991
1992 desc[0] = tess_offchip_va;
1993 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1994 S_008F04_STRIDE(0) |
1995 S_008F04_SWIZZLE_ENABLE(false);
1996 desc[2] = tess_offchip_ring_size;
1997 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1998 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1999 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2000 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2001 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2002 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2003 S_008F0C_ELEMENT_SIZE(0) |
2004 S_008F0C_INDEX_STRIDE(0) |
2005 S_008F0C_ADD_TID_ENABLE(false);
2006 desc += 4;
2007
2008 /* add sample positions after all rings */
2009 memcpy(desc, queue->device->sample_locations_1x, 8);
2010 desc += 2;
2011 memcpy(desc, queue->device->sample_locations_2x, 16);
2012 desc += 4;
2013 memcpy(desc, queue->device->sample_locations_4x, 32);
2014 desc += 8;
2015 memcpy(desc, queue->device->sample_locations_8x, 64);
2016 desc += 16;
2017 memcpy(desc, queue->device->sample_locations_16x, 128);
2018 }
2019
2020 static unsigned
2021 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2022 {
2023 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2024 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2025 device->physical_device->rad_info.family != CHIP_STONEY;
2026 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2027 unsigned max_offchip_buffers;
2028 unsigned offchip_granularity;
2029 unsigned hs_offchip_param;
2030
2031 /*
2032 * Per RadeonSI:
2033 * This must be one less than the maximum number due to a hw limitation.
2034 * Various hardware bugs in SI, CIK, and GFX9 need this.
2035 *
2036 * Per AMDVLK:
2037 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2038 * Gfx7 should limit max_offchip_buffers to 508
2039 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2040 *
2041 * Follow AMDVLK here.
2042 */
2043 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2044 device->physical_device->rad_info.chip_class == CIK ||
2045 device->physical_device->rad_info.chip_class == SI)
2046 --max_offchip_buffers_per_se;
2047
2048 max_offchip_buffers = max_offchip_buffers_per_se *
2049 device->physical_device->rad_info.max_se;
2050
2051 switch (device->tess_offchip_block_dw_size) {
2052 default:
2053 assert(0);
2054 /* fall through */
2055 case 8192:
2056 offchip_granularity = V_03093C_X_8K_DWORDS;
2057 break;
2058 case 4096:
2059 offchip_granularity = V_03093C_X_4K_DWORDS;
2060 break;
2061 }
2062
2063 switch (device->physical_device->rad_info.chip_class) {
2064 case SI:
2065 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2066 break;
2067 case CIK:
2068 case VI:
2069 case GFX9:
2070 default:
2071 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2072 break;
2073 }
2074
2075 *max_offchip_buffers_p = max_offchip_buffers;
2076 if (device->physical_device->rad_info.chip_class >= CIK) {
2077 if (device->physical_device->rad_info.chip_class >= VI)
2078 --max_offchip_buffers;
2079 hs_offchip_param =
2080 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2081 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2082 } else {
2083 hs_offchip_param =
2084 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2085 }
2086 return hs_offchip_param;
2087 }
2088
2089 static void
2090 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2091 struct radeon_winsys_bo *esgs_ring_bo,
2092 uint32_t esgs_ring_size,
2093 struct radeon_winsys_bo *gsvs_ring_bo,
2094 uint32_t gsvs_ring_size)
2095 {
2096 if (!esgs_ring_bo && !gsvs_ring_bo)
2097 return;
2098
2099 if (esgs_ring_bo)
2100 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2101
2102 if (gsvs_ring_bo)
2103 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2104
2105 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2106 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2107 radeon_emit(cs, esgs_ring_size >> 8);
2108 radeon_emit(cs, gsvs_ring_size >> 8);
2109 } else {
2110 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2111 radeon_emit(cs, esgs_ring_size >> 8);
2112 radeon_emit(cs, gsvs_ring_size >> 8);
2113 }
2114 }
2115
2116 static void
2117 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2118 unsigned hs_offchip_param, unsigned tf_ring_size,
2119 struct radeon_winsys_bo *tess_rings_bo)
2120 {
2121 uint64_t tf_va;
2122
2123 if (!tess_rings_bo)
2124 return;
2125
2126 tf_va = radv_buffer_get_va(tess_rings_bo);
2127
2128 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2129
2130 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2131 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2132 S_030938_SIZE(tf_ring_size / 4));
2133 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2134 tf_va >> 8);
2135 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2136 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2137 S_030944_BASE_HI(tf_va >> 40));
2138 }
2139 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2140 hs_offchip_param);
2141 } else {
2142 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2143 S_008988_SIZE(tf_ring_size / 4));
2144 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2145 tf_va >> 8);
2146 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2147 hs_offchip_param);
2148 }
2149 }
2150
2151 static void
2152 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2153 struct radeon_winsys_bo *compute_scratch_bo)
2154 {
2155 uint64_t scratch_va;
2156
2157 if (!compute_scratch_bo)
2158 return;
2159
2160 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2161
2162 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2163
2164 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2165 radeon_emit(cs, scratch_va);
2166 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2167 S_008F04_SWIZZLE_ENABLE(1));
2168 }
2169
2170 static void
2171 radv_emit_global_shader_pointers(struct radv_queue *queue,
2172 struct radeon_cmdbuf *cs,
2173 struct radeon_winsys_bo *descriptor_bo)
2174 {
2175 uint64_t va;
2176
2177 if (!descriptor_bo)
2178 return;
2179
2180 va = radv_buffer_get_va(descriptor_bo);
2181
2182 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2183
2184 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2185 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2186 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2187 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2188 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2189
2190 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2191 radv_emit_shader_pointer(queue->device, cs, regs[i],
2192 va, true);
2193 }
2194 } else {
2195 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2196 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2197 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2198 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2199 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2200 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2201
2202 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2203 radv_emit_shader_pointer(queue->device, cs, regs[i],
2204 va, true);
2205 }
2206 }
2207 }
2208
2209 static void
2210 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2211 {
2212 struct radv_device *device = queue->device;
2213
2214 if (device->gfx_init) {
2215 uint64_t va = radv_buffer_get_va(device->gfx_init);
2216
2217 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2218 radeon_emit(cs, va);
2219 radeon_emit(cs, va >> 32);
2220 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2221
2222 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2223 } else {
2224 struct radv_physical_device *physical_device = device->physical_device;
2225 si_emit_graphics(physical_device, cs);
2226 }
2227 }
2228
2229 static void
2230 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2231 {
2232 struct radv_physical_device *physical_device = queue->device->physical_device;
2233 si_emit_compute(physical_device, cs);
2234 }
2235
2236 static VkResult
2237 radv_get_preamble_cs(struct radv_queue *queue,
2238 uint32_t scratch_size,
2239 uint32_t compute_scratch_size,
2240 uint32_t esgs_ring_size,
2241 uint32_t gsvs_ring_size,
2242 bool needs_tess_rings,
2243 bool needs_sample_positions,
2244 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2245 struct radeon_cmdbuf **initial_preamble_cs,
2246 struct radeon_cmdbuf **continue_preamble_cs)
2247 {
2248 struct radeon_winsys_bo *scratch_bo = NULL;
2249 struct radeon_winsys_bo *descriptor_bo = NULL;
2250 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2251 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2252 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2253 struct radeon_winsys_bo *tess_rings_bo = NULL;
2254 struct radeon_cmdbuf *dest_cs[3] = {0};
2255 bool add_tess_rings = false, add_sample_positions = false;
2256 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2257 unsigned max_offchip_buffers;
2258 unsigned hs_offchip_param = 0;
2259 unsigned tess_offchip_ring_offset;
2260 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2261 if (!queue->has_tess_rings) {
2262 if (needs_tess_rings)
2263 add_tess_rings = true;
2264 }
2265 if (!queue->has_sample_positions) {
2266 if (needs_sample_positions)
2267 add_sample_positions = true;
2268 }
2269 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2270 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2271 &max_offchip_buffers);
2272 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2273 tess_offchip_ring_size = max_offchip_buffers *
2274 queue->device->tess_offchip_block_dw_size * 4;
2275
2276 if (scratch_size <= queue->scratch_size &&
2277 compute_scratch_size <= queue->compute_scratch_size &&
2278 esgs_ring_size <= queue->esgs_ring_size &&
2279 gsvs_ring_size <= queue->gsvs_ring_size &&
2280 !add_tess_rings && !add_sample_positions &&
2281 queue->initial_preamble_cs) {
2282 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2283 *initial_preamble_cs = queue->initial_preamble_cs;
2284 *continue_preamble_cs = queue->continue_preamble_cs;
2285 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2286 *continue_preamble_cs = NULL;
2287 return VK_SUCCESS;
2288 }
2289
2290 if (scratch_size > queue->scratch_size) {
2291 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2292 scratch_size,
2293 4096,
2294 RADEON_DOMAIN_VRAM,
2295 ring_bo_flags);
2296 if (!scratch_bo)
2297 goto fail;
2298 } else
2299 scratch_bo = queue->scratch_bo;
2300
2301 if (compute_scratch_size > queue->compute_scratch_size) {
2302 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2303 compute_scratch_size,
2304 4096,
2305 RADEON_DOMAIN_VRAM,
2306 ring_bo_flags);
2307 if (!compute_scratch_bo)
2308 goto fail;
2309
2310 } else
2311 compute_scratch_bo = queue->compute_scratch_bo;
2312
2313 if (esgs_ring_size > queue->esgs_ring_size) {
2314 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2315 esgs_ring_size,
2316 4096,
2317 RADEON_DOMAIN_VRAM,
2318 ring_bo_flags);
2319 if (!esgs_ring_bo)
2320 goto fail;
2321 } else {
2322 esgs_ring_bo = queue->esgs_ring_bo;
2323 esgs_ring_size = queue->esgs_ring_size;
2324 }
2325
2326 if (gsvs_ring_size > queue->gsvs_ring_size) {
2327 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2328 gsvs_ring_size,
2329 4096,
2330 RADEON_DOMAIN_VRAM,
2331 ring_bo_flags);
2332 if (!gsvs_ring_bo)
2333 goto fail;
2334 } else {
2335 gsvs_ring_bo = queue->gsvs_ring_bo;
2336 gsvs_ring_size = queue->gsvs_ring_size;
2337 }
2338
2339 if (add_tess_rings) {
2340 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2341 tess_offchip_ring_offset + tess_offchip_ring_size,
2342 256,
2343 RADEON_DOMAIN_VRAM,
2344 ring_bo_flags);
2345 if (!tess_rings_bo)
2346 goto fail;
2347 } else {
2348 tess_rings_bo = queue->tess_rings_bo;
2349 }
2350
2351 if (scratch_bo != queue->scratch_bo ||
2352 esgs_ring_bo != queue->esgs_ring_bo ||
2353 gsvs_ring_bo != queue->gsvs_ring_bo ||
2354 tess_rings_bo != queue->tess_rings_bo ||
2355 add_sample_positions) {
2356 uint32_t size = 0;
2357 if (gsvs_ring_bo || esgs_ring_bo ||
2358 tess_rings_bo || add_sample_positions) {
2359 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2360 if (add_sample_positions)
2361 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2362 }
2363 else if (scratch_bo)
2364 size = 8; /* 2 dword */
2365
2366 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2367 size,
2368 4096,
2369 RADEON_DOMAIN_VRAM,
2370 RADEON_FLAG_CPU_ACCESS |
2371 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2372 RADEON_FLAG_READ_ONLY);
2373 if (!descriptor_bo)
2374 goto fail;
2375 } else
2376 descriptor_bo = queue->descriptor_bo;
2377
2378 for(int i = 0; i < 3; ++i) {
2379 struct radeon_cmdbuf *cs = NULL;
2380 cs = queue->device->ws->cs_create(queue->device->ws,
2381 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2382 if (!cs)
2383 goto fail;
2384
2385 dest_cs[i] = cs;
2386
2387 if (scratch_bo)
2388 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2389
2390 /* Emit initial configuration. */
2391 switch (queue->queue_family_index) {
2392 case RADV_QUEUE_GENERAL:
2393 radv_init_graphics_state(cs, queue);
2394 break;
2395 case RADV_QUEUE_COMPUTE:
2396 radv_init_compute_state(cs, queue);
2397 break;
2398 case RADV_QUEUE_TRANSFER:
2399 break;
2400 }
2401
2402 if (descriptor_bo != queue->descriptor_bo) {
2403 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2404
2405 if (scratch_bo) {
2406 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2407 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2408 S_008F04_SWIZZLE_ENABLE(1);
2409 map[0] = scratch_va;
2410 map[1] = rsrc1;
2411 }
2412
2413 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2414 add_sample_positions)
2415 fill_geom_tess_rings(queue, map, add_sample_positions,
2416 esgs_ring_size, esgs_ring_bo,
2417 gsvs_ring_size, gsvs_ring_bo,
2418 tess_factor_ring_size,
2419 tess_offchip_ring_offset,
2420 tess_offchip_ring_size,
2421 tess_rings_bo);
2422
2423 queue->device->ws->buffer_unmap(descriptor_bo);
2424 }
2425
2426 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2427 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2428 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2429 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2430 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2431 }
2432
2433 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2434 gsvs_ring_bo, gsvs_ring_size);
2435 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2436 tess_factor_ring_size, tess_rings_bo);
2437 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2438 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2439
2440 if (i == 0) {
2441 si_cs_emit_cache_flush(cs,
2442 queue->device->physical_device->rad_info.chip_class,
2443 NULL, 0,
2444 queue->queue_family_index == RING_COMPUTE &&
2445 queue->device->physical_device->rad_info.chip_class >= CIK,
2446 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2447 RADV_CMD_FLAG_INV_ICACHE |
2448 RADV_CMD_FLAG_INV_SMEM_L1 |
2449 RADV_CMD_FLAG_INV_VMEM_L1 |
2450 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2451 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2452 } else if (i == 1) {
2453 si_cs_emit_cache_flush(cs,
2454 queue->device->physical_device->rad_info.chip_class,
2455 NULL, 0,
2456 queue->queue_family_index == RING_COMPUTE &&
2457 queue->device->physical_device->rad_info.chip_class >= CIK,
2458 RADV_CMD_FLAG_INV_ICACHE |
2459 RADV_CMD_FLAG_INV_SMEM_L1 |
2460 RADV_CMD_FLAG_INV_VMEM_L1 |
2461 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2462 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2463 }
2464
2465 if (!queue->device->ws->cs_finalize(cs))
2466 goto fail;
2467 }
2468
2469 if (queue->initial_full_flush_preamble_cs)
2470 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2471
2472 if (queue->initial_preamble_cs)
2473 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2474
2475 if (queue->continue_preamble_cs)
2476 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2477
2478 queue->initial_full_flush_preamble_cs = dest_cs[0];
2479 queue->initial_preamble_cs = dest_cs[1];
2480 queue->continue_preamble_cs = dest_cs[2];
2481
2482 if (scratch_bo != queue->scratch_bo) {
2483 if (queue->scratch_bo)
2484 queue->device->ws->buffer_destroy(queue->scratch_bo);
2485 queue->scratch_bo = scratch_bo;
2486 queue->scratch_size = scratch_size;
2487 }
2488
2489 if (compute_scratch_bo != queue->compute_scratch_bo) {
2490 if (queue->compute_scratch_bo)
2491 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2492 queue->compute_scratch_bo = compute_scratch_bo;
2493 queue->compute_scratch_size = compute_scratch_size;
2494 }
2495
2496 if (esgs_ring_bo != queue->esgs_ring_bo) {
2497 if (queue->esgs_ring_bo)
2498 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2499 queue->esgs_ring_bo = esgs_ring_bo;
2500 queue->esgs_ring_size = esgs_ring_size;
2501 }
2502
2503 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2504 if (queue->gsvs_ring_bo)
2505 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2506 queue->gsvs_ring_bo = gsvs_ring_bo;
2507 queue->gsvs_ring_size = gsvs_ring_size;
2508 }
2509
2510 if (tess_rings_bo != queue->tess_rings_bo) {
2511 queue->tess_rings_bo = tess_rings_bo;
2512 queue->has_tess_rings = true;
2513 }
2514
2515 if (descriptor_bo != queue->descriptor_bo) {
2516 if (queue->descriptor_bo)
2517 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2518
2519 queue->descriptor_bo = descriptor_bo;
2520 }
2521
2522 if (add_sample_positions)
2523 queue->has_sample_positions = true;
2524
2525 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2526 *initial_preamble_cs = queue->initial_preamble_cs;
2527 *continue_preamble_cs = queue->continue_preamble_cs;
2528 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2529 *continue_preamble_cs = NULL;
2530 return VK_SUCCESS;
2531 fail:
2532 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2533 if (dest_cs[i])
2534 queue->device->ws->cs_destroy(dest_cs[i]);
2535 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2536 queue->device->ws->buffer_destroy(descriptor_bo);
2537 if (scratch_bo && scratch_bo != queue->scratch_bo)
2538 queue->device->ws->buffer_destroy(scratch_bo);
2539 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2540 queue->device->ws->buffer_destroy(compute_scratch_bo);
2541 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2542 queue->device->ws->buffer_destroy(esgs_ring_bo);
2543 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2544 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2545 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2546 queue->device->ws->buffer_destroy(tess_rings_bo);
2547 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2548 }
2549
2550 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2551 struct radv_winsys_sem_counts *counts,
2552 int num_sems,
2553 const VkSemaphore *sems,
2554 VkFence _fence,
2555 bool reset_temp)
2556 {
2557 int syncobj_idx = 0, sem_idx = 0;
2558
2559 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2560 return VK_SUCCESS;
2561
2562 for (uint32_t i = 0; i < num_sems; i++) {
2563 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2564
2565 if (sem->temp_syncobj || sem->syncobj)
2566 counts->syncobj_count++;
2567 else
2568 counts->sem_count++;
2569 }
2570
2571 if (_fence != VK_NULL_HANDLE) {
2572 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2573 if (fence->temp_syncobj || fence->syncobj)
2574 counts->syncobj_count++;
2575 }
2576
2577 if (counts->syncobj_count) {
2578 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2579 if (!counts->syncobj)
2580 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2581 }
2582
2583 if (counts->sem_count) {
2584 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2585 if (!counts->sem) {
2586 free(counts->syncobj);
2587 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2588 }
2589 }
2590
2591 for (uint32_t i = 0; i < num_sems; i++) {
2592 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2593
2594 if (sem->temp_syncobj) {
2595 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2596 }
2597 else if (sem->syncobj)
2598 counts->syncobj[syncobj_idx++] = sem->syncobj;
2599 else {
2600 assert(sem->sem);
2601 counts->sem[sem_idx++] = sem->sem;
2602 }
2603 }
2604
2605 if (_fence != VK_NULL_HANDLE) {
2606 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2607 if (fence->temp_syncobj)
2608 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2609 else if (fence->syncobj)
2610 counts->syncobj[syncobj_idx++] = fence->syncobj;
2611 }
2612
2613 return VK_SUCCESS;
2614 }
2615
2616 static void
2617 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2618 {
2619 free(sem_info->wait.syncobj);
2620 free(sem_info->wait.sem);
2621 free(sem_info->signal.syncobj);
2622 free(sem_info->signal.sem);
2623 }
2624
2625
2626 static void radv_free_temp_syncobjs(struct radv_device *device,
2627 int num_sems,
2628 const VkSemaphore *sems)
2629 {
2630 for (uint32_t i = 0; i < num_sems; i++) {
2631 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2632
2633 if (sem->temp_syncobj) {
2634 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2635 sem->temp_syncobj = 0;
2636 }
2637 }
2638 }
2639
2640 static VkResult
2641 radv_alloc_sem_info(struct radv_instance *instance,
2642 struct radv_winsys_sem_info *sem_info,
2643 int num_wait_sems,
2644 const VkSemaphore *wait_sems,
2645 int num_signal_sems,
2646 const VkSemaphore *signal_sems,
2647 VkFence fence)
2648 {
2649 VkResult ret;
2650 memset(sem_info, 0, sizeof(*sem_info));
2651
2652 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2653 if (ret)
2654 return ret;
2655 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2656 if (ret)
2657 radv_free_sem_info(sem_info);
2658
2659 /* caller can override these */
2660 sem_info->cs_emit_wait = true;
2661 sem_info->cs_emit_signal = true;
2662 return ret;
2663 }
2664
2665 /* Signals fence as soon as all the work currently put on queue is done. */
2666 static VkResult radv_signal_fence(struct radv_queue *queue,
2667 struct radv_fence *fence)
2668 {
2669 int ret;
2670 VkResult result;
2671 struct radv_winsys_sem_info sem_info;
2672
2673 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2674 radv_fence_to_handle(fence));
2675 if (result != VK_SUCCESS)
2676 return result;
2677
2678 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2679 &queue->device->empty_cs[queue->queue_family_index],
2680 1, NULL, NULL, &sem_info, NULL,
2681 false, fence->fence);
2682 radv_free_sem_info(&sem_info);
2683
2684 if (ret)
2685 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2686
2687 return VK_SUCCESS;
2688 }
2689
2690 VkResult radv_QueueSubmit(
2691 VkQueue _queue,
2692 uint32_t submitCount,
2693 const VkSubmitInfo* pSubmits,
2694 VkFence _fence)
2695 {
2696 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2697 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2698 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2699 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2700 int ret;
2701 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2702 uint32_t scratch_size = 0;
2703 uint32_t compute_scratch_size = 0;
2704 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2705 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2706 VkResult result;
2707 bool fence_emitted = false;
2708 bool tess_rings_needed = false;
2709 bool sample_positions_needed = false;
2710
2711 /* Do this first so failing to allocate scratch buffers can't result in
2712 * partially executed submissions. */
2713 for (uint32_t i = 0; i < submitCount; i++) {
2714 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2715 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2716 pSubmits[i].pCommandBuffers[j]);
2717
2718 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2719 compute_scratch_size = MAX2(compute_scratch_size,
2720 cmd_buffer->compute_scratch_size_needed);
2721 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2722 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2723 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2724 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2725 }
2726 }
2727
2728 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2729 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2730 sample_positions_needed, &initial_flush_preamble_cs,
2731 &initial_preamble_cs, &continue_preamble_cs);
2732 if (result != VK_SUCCESS)
2733 return result;
2734
2735 for (uint32_t i = 0; i < submitCount; i++) {
2736 struct radeon_cmdbuf **cs_array;
2737 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2738 bool can_patch = true;
2739 uint32_t advance;
2740 struct radv_winsys_sem_info sem_info;
2741
2742 result = radv_alloc_sem_info(queue->device->instance,
2743 &sem_info,
2744 pSubmits[i].waitSemaphoreCount,
2745 pSubmits[i].pWaitSemaphores,
2746 pSubmits[i].signalSemaphoreCount,
2747 pSubmits[i].pSignalSemaphores,
2748 _fence);
2749 if (result != VK_SUCCESS)
2750 return result;
2751
2752 if (!pSubmits[i].commandBufferCount) {
2753 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2754 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2755 &queue->device->empty_cs[queue->queue_family_index],
2756 1, NULL, NULL,
2757 &sem_info, NULL,
2758 false, base_fence);
2759 if (ret) {
2760 radv_loge("failed to submit CS %d\n", i);
2761 abort();
2762 }
2763 fence_emitted = true;
2764 }
2765 radv_free_sem_info(&sem_info);
2766 continue;
2767 }
2768
2769 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2770 (pSubmits[i].commandBufferCount));
2771
2772 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2773 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2774 pSubmits[i].pCommandBuffers[j]);
2775 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2776
2777 cs_array[j] = cmd_buffer->cs;
2778 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2779 can_patch = false;
2780
2781 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2782 }
2783
2784 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2785 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2786 const struct radv_winsys_bo_list *bo_list = NULL;
2787
2788 advance = MIN2(max_cs_submission,
2789 pSubmits[i].commandBufferCount - j);
2790
2791 if (queue->device->trace_bo)
2792 *queue->device->trace_id_ptr = 0;
2793
2794 sem_info.cs_emit_wait = j == 0;
2795 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2796
2797 if (unlikely(queue->device->use_global_bo_list)) {
2798 pthread_mutex_lock(&queue->device->bo_list.mutex);
2799 bo_list = &queue->device->bo_list.list;
2800 }
2801
2802 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2803 advance, initial_preamble, continue_preamble_cs,
2804 &sem_info, bo_list,
2805 can_patch, base_fence);
2806
2807 if (unlikely(queue->device->use_global_bo_list))
2808 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2809
2810 if (ret) {
2811 radv_loge("failed to submit CS %d\n", i);
2812 abort();
2813 }
2814 fence_emitted = true;
2815 if (queue->device->trace_bo) {
2816 radv_check_gpu_hangs(queue, cs_array[j]);
2817 }
2818 }
2819
2820 radv_free_temp_syncobjs(queue->device,
2821 pSubmits[i].waitSemaphoreCount,
2822 pSubmits[i].pWaitSemaphores);
2823 radv_free_sem_info(&sem_info);
2824 free(cs_array);
2825 }
2826
2827 if (fence) {
2828 if (!fence_emitted) {
2829 result = radv_signal_fence(queue, fence);
2830 if (result != VK_SUCCESS)
2831 return result;
2832 }
2833 fence->submitted = true;
2834 }
2835
2836 return VK_SUCCESS;
2837 }
2838
2839 VkResult radv_QueueWaitIdle(
2840 VkQueue _queue)
2841 {
2842 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2843
2844 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2845 radv_queue_family_to_ring(queue->queue_family_index),
2846 queue->queue_idx);
2847 return VK_SUCCESS;
2848 }
2849
2850 VkResult radv_DeviceWaitIdle(
2851 VkDevice _device)
2852 {
2853 RADV_FROM_HANDLE(radv_device, device, _device);
2854
2855 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2856 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2857 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2858 }
2859 }
2860 return VK_SUCCESS;
2861 }
2862
2863 VkResult radv_EnumerateInstanceExtensionProperties(
2864 const char* pLayerName,
2865 uint32_t* pPropertyCount,
2866 VkExtensionProperties* pProperties)
2867 {
2868 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2869
2870 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2871 if (radv_supported_instance_extensions.extensions[i]) {
2872 vk_outarray_append(&out, prop) {
2873 *prop = radv_instance_extensions[i];
2874 }
2875 }
2876 }
2877
2878 return vk_outarray_status(&out);
2879 }
2880
2881 VkResult radv_EnumerateDeviceExtensionProperties(
2882 VkPhysicalDevice physicalDevice,
2883 const char* pLayerName,
2884 uint32_t* pPropertyCount,
2885 VkExtensionProperties* pProperties)
2886 {
2887 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2888 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2889
2890 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2891 if (device->supported_extensions.extensions[i]) {
2892 vk_outarray_append(&out, prop) {
2893 *prop = radv_device_extensions[i];
2894 }
2895 }
2896 }
2897
2898 return vk_outarray_status(&out);
2899 }
2900
2901 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2902 VkInstance _instance,
2903 const char* pName)
2904 {
2905 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2906
2907 return radv_lookup_entrypoint_checked(pName,
2908 instance ? instance->apiVersion : 0,
2909 instance ? &instance->enabled_extensions : NULL,
2910 NULL);
2911 }
2912
2913 /* The loader wants us to expose a second GetInstanceProcAddr function
2914 * to work around certain LD_PRELOAD issues seen in apps.
2915 */
2916 PUBLIC
2917 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2918 VkInstance instance,
2919 const char* pName);
2920
2921 PUBLIC
2922 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2923 VkInstance instance,
2924 const char* pName)
2925 {
2926 return radv_GetInstanceProcAddr(instance, pName);
2927 }
2928
2929 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2930 VkDevice _device,
2931 const char* pName)
2932 {
2933 RADV_FROM_HANDLE(radv_device, device, _device);
2934
2935 return radv_lookup_entrypoint_checked(pName,
2936 device->instance->apiVersion,
2937 &device->instance->enabled_extensions,
2938 &device->enabled_extensions);
2939 }
2940
2941 bool radv_get_memory_fd(struct radv_device *device,
2942 struct radv_device_memory *memory,
2943 int *pFD)
2944 {
2945 struct radeon_bo_metadata metadata;
2946
2947 if (memory->image) {
2948 radv_init_metadata(device, memory->image, &metadata);
2949 device->ws->buffer_set_metadata(memory->bo, &metadata);
2950 }
2951
2952 return device->ws->buffer_get_fd(device->ws, memory->bo,
2953 pFD);
2954 }
2955
2956 static VkResult radv_alloc_memory(struct radv_device *device,
2957 const VkMemoryAllocateInfo* pAllocateInfo,
2958 const VkAllocationCallbacks* pAllocator,
2959 VkDeviceMemory* pMem)
2960 {
2961 struct radv_device_memory *mem;
2962 VkResult result;
2963 enum radeon_bo_domain domain;
2964 uint32_t flags = 0;
2965 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2966
2967 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2968
2969 if (pAllocateInfo->allocationSize == 0) {
2970 /* Apparently, this is allowed */
2971 *pMem = VK_NULL_HANDLE;
2972 return VK_SUCCESS;
2973 }
2974
2975 const VkImportMemoryFdInfoKHR *import_info =
2976 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2977 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2978 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2979 const VkExportMemoryAllocateInfoKHR *export_info =
2980 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2981 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2982 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2983
2984 const struct wsi_memory_allocate_info *wsi_info =
2985 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2986
2987 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2988 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2989 if (mem == NULL)
2990 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2991
2992 if (wsi_info && wsi_info->implicit_sync)
2993 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2994
2995 if (dedicate_info) {
2996 mem->image = radv_image_from_handle(dedicate_info->image);
2997 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2998 } else {
2999 mem->image = NULL;
3000 mem->buffer = NULL;
3001 }
3002
3003 mem->user_ptr = NULL;
3004
3005 if (import_info) {
3006 assert(import_info->handleType ==
3007 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
3008 import_info->handleType ==
3009 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3010 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3011 NULL, NULL);
3012 if (!mem->bo) {
3013 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3014 goto fail;
3015 } else {
3016 close(import_info->fd);
3017 }
3018 } else if (host_ptr_info) {
3019 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3020 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3021 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3022 pAllocateInfo->allocationSize);
3023 if (!mem->bo) {
3024 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3025 goto fail;
3026 } else {
3027 mem->user_ptr = host_ptr_info->pHostPointer;
3028 }
3029 } else {
3030 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3031 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3032 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3033 domain = RADEON_DOMAIN_GTT;
3034 else
3035 domain = RADEON_DOMAIN_VRAM;
3036
3037 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3038 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3039 else
3040 flags |= RADEON_FLAG_CPU_ACCESS;
3041
3042 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3043 flags |= RADEON_FLAG_GTT_WC;
3044
3045 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
3046 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3047
3048 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3049 domain, flags);
3050
3051 if (!mem->bo) {
3052 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3053 goto fail;
3054 }
3055 mem->type_index = mem_type_index;
3056 }
3057
3058 result = radv_bo_list_add(device, mem->bo);
3059 if (result != VK_SUCCESS)
3060 goto fail_bo;
3061
3062 *pMem = radv_device_memory_to_handle(mem);
3063
3064 return VK_SUCCESS;
3065
3066 fail_bo:
3067 device->ws->buffer_destroy(mem->bo);
3068 fail:
3069 vk_free2(&device->alloc, pAllocator, mem);
3070
3071 return result;
3072 }
3073
3074 VkResult radv_AllocateMemory(
3075 VkDevice _device,
3076 const VkMemoryAllocateInfo* pAllocateInfo,
3077 const VkAllocationCallbacks* pAllocator,
3078 VkDeviceMemory* pMem)
3079 {
3080 RADV_FROM_HANDLE(radv_device, device, _device);
3081 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3082 }
3083
3084 void radv_FreeMemory(
3085 VkDevice _device,
3086 VkDeviceMemory _mem,
3087 const VkAllocationCallbacks* pAllocator)
3088 {
3089 RADV_FROM_HANDLE(radv_device, device, _device);
3090 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3091
3092 if (mem == NULL)
3093 return;
3094
3095 radv_bo_list_remove(device, mem->bo);
3096 device->ws->buffer_destroy(mem->bo);
3097 mem->bo = NULL;
3098
3099 vk_free2(&device->alloc, pAllocator, mem);
3100 }
3101
3102 VkResult radv_MapMemory(
3103 VkDevice _device,
3104 VkDeviceMemory _memory,
3105 VkDeviceSize offset,
3106 VkDeviceSize size,
3107 VkMemoryMapFlags flags,
3108 void** ppData)
3109 {
3110 RADV_FROM_HANDLE(radv_device, device, _device);
3111 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3112
3113 if (mem == NULL) {
3114 *ppData = NULL;
3115 return VK_SUCCESS;
3116 }
3117
3118 if (mem->user_ptr)
3119 *ppData = mem->user_ptr;
3120 else
3121 *ppData = device->ws->buffer_map(mem->bo);
3122
3123 if (*ppData) {
3124 *ppData += offset;
3125 return VK_SUCCESS;
3126 }
3127
3128 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3129 }
3130
3131 void radv_UnmapMemory(
3132 VkDevice _device,
3133 VkDeviceMemory _memory)
3134 {
3135 RADV_FROM_HANDLE(radv_device, device, _device);
3136 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3137
3138 if (mem == NULL)
3139 return;
3140
3141 if (mem->user_ptr == NULL)
3142 device->ws->buffer_unmap(mem->bo);
3143 }
3144
3145 VkResult radv_FlushMappedMemoryRanges(
3146 VkDevice _device,
3147 uint32_t memoryRangeCount,
3148 const VkMappedMemoryRange* pMemoryRanges)
3149 {
3150 return VK_SUCCESS;
3151 }
3152
3153 VkResult radv_InvalidateMappedMemoryRanges(
3154 VkDevice _device,
3155 uint32_t memoryRangeCount,
3156 const VkMappedMemoryRange* pMemoryRanges)
3157 {
3158 return VK_SUCCESS;
3159 }
3160
3161 void radv_GetBufferMemoryRequirements(
3162 VkDevice _device,
3163 VkBuffer _buffer,
3164 VkMemoryRequirements* pMemoryRequirements)
3165 {
3166 RADV_FROM_HANDLE(radv_device, device, _device);
3167 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3168
3169 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3170
3171 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3172 pMemoryRequirements->alignment = 4096;
3173 else
3174 pMemoryRequirements->alignment = 16;
3175
3176 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3177 }
3178
3179 void radv_GetBufferMemoryRequirements2(
3180 VkDevice device,
3181 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3182 VkMemoryRequirements2KHR* pMemoryRequirements)
3183 {
3184 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3185 &pMemoryRequirements->memoryRequirements);
3186 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3187 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3188 switch (ext->sType) {
3189 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3190 VkMemoryDedicatedRequirementsKHR *req =
3191 (VkMemoryDedicatedRequirementsKHR *) ext;
3192 req->requiresDedicatedAllocation = buffer->shareable;
3193 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3194 break;
3195 }
3196 default:
3197 break;
3198 }
3199 }
3200 }
3201
3202 void radv_GetImageMemoryRequirements(
3203 VkDevice _device,
3204 VkImage _image,
3205 VkMemoryRequirements* pMemoryRequirements)
3206 {
3207 RADV_FROM_HANDLE(radv_device, device, _device);
3208 RADV_FROM_HANDLE(radv_image, image, _image);
3209
3210 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3211
3212 pMemoryRequirements->size = image->size;
3213 pMemoryRequirements->alignment = image->alignment;
3214 }
3215
3216 void radv_GetImageMemoryRequirements2(
3217 VkDevice device,
3218 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3219 VkMemoryRequirements2KHR* pMemoryRequirements)
3220 {
3221 radv_GetImageMemoryRequirements(device, pInfo->image,
3222 &pMemoryRequirements->memoryRequirements);
3223
3224 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3225
3226 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3227 switch (ext->sType) {
3228 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3229 VkMemoryDedicatedRequirementsKHR *req =
3230 (VkMemoryDedicatedRequirementsKHR *) ext;
3231 req->requiresDedicatedAllocation = image->shareable;
3232 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3233 break;
3234 }
3235 default:
3236 break;
3237 }
3238 }
3239 }
3240
3241 void radv_GetImageSparseMemoryRequirements(
3242 VkDevice device,
3243 VkImage image,
3244 uint32_t* pSparseMemoryRequirementCount,
3245 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3246 {
3247 stub();
3248 }
3249
3250 void radv_GetImageSparseMemoryRequirements2(
3251 VkDevice device,
3252 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3253 uint32_t* pSparseMemoryRequirementCount,
3254 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3255 {
3256 stub();
3257 }
3258
3259 void radv_GetDeviceMemoryCommitment(
3260 VkDevice device,
3261 VkDeviceMemory memory,
3262 VkDeviceSize* pCommittedMemoryInBytes)
3263 {
3264 *pCommittedMemoryInBytes = 0;
3265 }
3266
3267 VkResult radv_BindBufferMemory2(VkDevice device,
3268 uint32_t bindInfoCount,
3269 const VkBindBufferMemoryInfoKHR *pBindInfos)
3270 {
3271 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3272 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3273 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3274
3275 if (mem) {
3276 buffer->bo = mem->bo;
3277 buffer->offset = pBindInfos[i].memoryOffset;
3278 } else {
3279 buffer->bo = NULL;
3280 }
3281 }
3282 return VK_SUCCESS;
3283 }
3284
3285 VkResult radv_BindBufferMemory(
3286 VkDevice device,
3287 VkBuffer buffer,
3288 VkDeviceMemory memory,
3289 VkDeviceSize memoryOffset)
3290 {
3291 const VkBindBufferMemoryInfoKHR info = {
3292 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3293 .buffer = buffer,
3294 .memory = memory,
3295 .memoryOffset = memoryOffset
3296 };
3297
3298 return radv_BindBufferMemory2(device, 1, &info);
3299 }
3300
3301 VkResult radv_BindImageMemory2(VkDevice device,
3302 uint32_t bindInfoCount,
3303 const VkBindImageMemoryInfoKHR *pBindInfos)
3304 {
3305 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3306 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3307 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3308
3309 if (mem) {
3310 image->bo = mem->bo;
3311 image->offset = pBindInfos[i].memoryOffset;
3312 } else {
3313 image->bo = NULL;
3314 image->offset = 0;
3315 }
3316 }
3317 return VK_SUCCESS;
3318 }
3319
3320
3321 VkResult radv_BindImageMemory(
3322 VkDevice device,
3323 VkImage image,
3324 VkDeviceMemory memory,
3325 VkDeviceSize memoryOffset)
3326 {
3327 const VkBindImageMemoryInfoKHR info = {
3328 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3329 .image = image,
3330 .memory = memory,
3331 .memoryOffset = memoryOffset
3332 };
3333
3334 return radv_BindImageMemory2(device, 1, &info);
3335 }
3336
3337
3338 static void
3339 radv_sparse_buffer_bind_memory(struct radv_device *device,
3340 const VkSparseBufferMemoryBindInfo *bind)
3341 {
3342 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3343
3344 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3345 struct radv_device_memory *mem = NULL;
3346
3347 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3348 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3349
3350 device->ws->buffer_virtual_bind(buffer->bo,
3351 bind->pBinds[i].resourceOffset,
3352 bind->pBinds[i].size,
3353 mem ? mem->bo : NULL,
3354 bind->pBinds[i].memoryOffset);
3355 }
3356 }
3357
3358 static void
3359 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3360 const VkSparseImageOpaqueMemoryBindInfo *bind)
3361 {
3362 RADV_FROM_HANDLE(radv_image, image, bind->image);
3363
3364 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3365 struct radv_device_memory *mem = NULL;
3366
3367 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3368 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3369
3370 device->ws->buffer_virtual_bind(image->bo,
3371 bind->pBinds[i].resourceOffset,
3372 bind->pBinds[i].size,
3373 mem ? mem->bo : NULL,
3374 bind->pBinds[i].memoryOffset);
3375 }
3376 }
3377
3378 VkResult radv_QueueBindSparse(
3379 VkQueue _queue,
3380 uint32_t bindInfoCount,
3381 const VkBindSparseInfo* pBindInfo,
3382 VkFence _fence)
3383 {
3384 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3385 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3386 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3387 bool fence_emitted = false;
3388 VkResult result;
3389 int ret;
3390
3391 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3392 struct radv_winsys_sem_info sem_info;
3393 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3394 radv_sparse_buffer_bind_memory(queue->device,
3395 pBindInfo[i].pBufferBinds + j);
3396 }
3397
3398 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3399 radv_sparse_image_opaque_bind_memory(queue->device,
3400 pBindInfo[i].pImageOpaqueBinds + j);
3401 }
3402
3403 VkResult result;
3404 result = radv_alloc_sem_info(queue->device->instance,
3405 &sem_info,
3406 pBindInfo[i].waitSemaphoreCount,
3407 pBindInfo[i].pWaitSemaphores,
3408 pBindInfo[i].signalSemaphoreCount,
3409 pBindInfo[i].pSignalSemaphores,
3410 _fence);
3411 if (result != VK_SUCCESS)
3412 return result;
3413
3414 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3415 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3416 &queue->device->empty_cs[queue->queue_family_index],
3417 1, NULL, NULL,
3418 &sem_info, NULL,
3419 false, base_fence);
3420 if (ret) {
3421 radv_loge("failed to submit CS %d\n", i);
3422 abort();
3423 }
3424
3425 fence_emitted = true;
3426 if (fence)
3427 fence->submitted = true;
3428 }
3429
3430 radv_free_sem_info(&sem_info);
3431
3432 }
3433
3434 if (fence) {
3435 if (!fence_emitted) {
3436 result = radv_signal_fence(queue, fence);
3437 if (result != VK_SUCCESS)
3438 return result;
3439 }
3440 fence->submitted = true;
3441 }
3442
3443 return VK_SUCCESS;
3444 }
3445
3446 VkResult radv_CreateFence(
3447 VkDevice _device,
3448 const VkFenceCreateInfo* pCreateInfo,
3449 const VkAllocationCallbacks* pAllocator,
3450 VkFence* pFence)
3451 {
3452 RADV_FROM_HANDLE(radv_device, device, _device);
3453 const VkExportFenceCreateInfoKHR *export =
3454 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3455 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3456 export ? export->handleTypes : 0;
3457
3458 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3459 sizeof(*fence), 8,
3460 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3461
3462 if (!fence)
3463 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3464
3465 fence->fence_wsi = NULL;
3466 fence->submitted = false;
3467 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3468 fence->temp_syncobj = 0;
3469 if (device->always_use_syncobj || handleTypes) {
3470 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3471 if (ret) {
3472 vk_free2(&device->alloc, pAllocator, fence);
3473 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3474 }
3475 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3476 device->ws->signal_syncobj(device->ws, fence->syncobj);
3477 }
3478 fence->fence = NULL;
3479 } else {
3480 fence->fence = device->ws->create_fence();
3481 if (!fence->fence) {
3482 vk_free2(&device->alloc, pAllocator, fence);
3483 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3484 }
3485 fence->syncobj = 0;
3486 }
3487
3488 *pFence = radv_fence_to_handle(fence);
3489
3490 return VK_SUCCESS;
3491 }
3492
3493 void radv_DestroyFence(
3494 VkDevice _device,
3495 VkFence _fence,
3496 const VkAllocationCallbacks* pAllocator)
3497 {
3498 RADV_FROM_HANDLE(radv_device, device, _device);
3499 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3500
3501 if (!fence)
3502 return;
3503
3504 if (fence->temp_syncobj)
3505 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3506 if (fence->syncobj)
3507 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3508 if (fence->fence)
3509 device->ws->destroy_fence(fence->fence);
3510 if (fence->fence_wsi)
3511 fence->fence_wsi->destroy(fence->fence_wsi);
3512 vk_free2(&device->alloc, pAllocator, fence);
3513 }
3514
3515
3516 static uint64_t radv_get_current_time()
3517 {
3518 struct timespec tv;
3519 clock_gettime(CLOCK_MONOTONIC, &tv);
3520 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3521 }
3522
3523 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3524 {
3525 uint64_t current_time = radv_get_current_time();
3526
3527 timeout = MIN2(UINT64_MAX - current_time, timeout);
3528
3529 return current_time + timeout;
3530 }
3531
3532
3533 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3534 {
3535 for (uint32_t i = 0; i < fenceCount; ++i) {
3536 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3537 if (fence->fence == NULL || fence->syncobj ||
3538 fence->temp_syncobj ||
3539 (!fence->signalled && !fence->submitted))
3540 return false;
3541 }
3542 return true;
3543 }
3544
3545 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3546 {
3547 for (uint32_t i = 0; i < fenceCount; ++i) {
3548 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3549 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3550 return false;
3551 }
3552 return true;
3553 }
3554
3555 VkResult radv_WaitForFences(
3556 VkDevice _device,
3557 uint32_t fenceCount,
3558 const VkFence* pFences,
3559 VkBool32 waitAll,
3560 uint64_t timeout)
3561 {
3562 RADV_FROM_HANDLE(radv_device, device, _device);
3563 timeout = radv_get_absolute_timeout(timeout);
3564
3565 if (device->always_use_syncobj &&
3566 radv_all_fences_syncobj(fenceCount, pFences))
3567 {
3568 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3569 if (!handles)
3570 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3571
3572 for (uint32_t i = 0; i < fenceCount; ++i) {
3573 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3574 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3575 }
3576
3577 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3578
3579 free(handles);
3580 return success ? VK_SUCCESS : VK_TIMEOUT;
3581 }
3582
3583 if (!waitAll && fenceCount > 1) {
3584 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3585 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3586 uint32_t wait_count = 0;
3587 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3588 if (!fences)
3589 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3590
3591 for (uint32_t i = 0; i < fenceCount; ++i) {
3592 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3593
3594 if (fence->signalled) {
3595 free(fences);
3596 return VK_SUCCESS;
3597 }
3598
3599 fences[wait_count++] = fence->fence;
3600 }
3601
3602 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3603 waitAll, timeout - radv_get_current_time());
3604
3605 free(fences);
3606 return success ? VK_SUCCESS : VK_TIMEOUT;
3607 }
3608
3609 while(radv_get_current_time() <= timeout) {
3610 for (uint32_t i = 0; i < fenceCount; ++i) {
3611 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3612 return VK_SUCCESS;
3613 }
3614 }
3615 return VK_TIMEOUT;
3616 }
3617
3618 for (uint32_t i = 0; i < fenceCount; ++i) {
3619 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3620 bool expired = false;
3621
3622 if (fence->temp_syncobj) {
3623 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3624 return VK_TIMEOUT;
3625 continue;
3626 }
3627
3628 if (fence->syncobj) {
3629 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3630 return VK_TIMEOUT;
3631 continue;
3632 }
3633
3634 if (fence->signalled)
3635 continue;
3636
3637 if (fence->fence) {
3638 if (!fence->submitted) {
3639 while(radv_get_current_time() <= timeout &&
3640 !fence->submitted)
3641 /* Do nothing */;
3642
3643 if (!fence->submitted)
3644 return VK_TIMEOUT;
3645
3646 /* Recheck as it may have been set by
3647 * submitting operations. */
3648
3649 if (fence->signalled)
3650 continue;
3651 }
3652
3653 expired = device->ws->fence_wait(device->ws,
3654 fence->fence,
3655 true, timeout);
3656 if (!expired)
3657 return VK_TIMEOUT;
3658 }
3659
3660 if (fence->fence_wsi) {
3661 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3662 if (result != VK_SUCCESS)
3663 return result;
3664 }
3665
3666 fence->signalled = true;
3667 }
3668
3669 return VK_SUCCESS;
3670 }
3671
3672 VkResult radv_ResetFences(VkDevice _device,
3673 uint32_t fenceCount,
3674 const VkFence *pFences)
3675 {
3676 RADV_FROM_HANDLE(radv_device, device, _device);
3677
3678 for (unsigned i = 0; i < fenceCount; ++i) {
3679 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3680 fence->submitted = fence->signalled = false;
3681
3682 /* Per spec, we first restore the permanent payload, and then reset, so
3683 * having a temp syncobj should not skip resetting the permanent syncobj. */
3684 if (fence->temp_syncobj) {
3685 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3686 fence->temp_syncobj = 0;
3687 }
3688
3689 if (fence->syncobj) {
3690 device->ws->reset_syncobj(device->ws, fence->syncobj);
3691 }
3692 }
3693
3694 return VK_SUCCESS;
3695 }
3696
3697 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3698 {
3699 RADV_FROM_HANDLE(radv_device, device, _device);
3700 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3701
3702 if (fence->temp_syncobj) {
3703 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3704 return success ? VK_SUCCESS : VK_NOT_READY;
3705 }
3706
3707 if (fence->syncobj) {
3708 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3709 return success ? VK_SUCCESS : VK_NOT_READY;
3710 }
3711
3712 if (fence->signalled)
3713 return VK_SUCCESS;
3714 if (!fence->submitted)
3715 return VK_NOT_READY;
3716 if (fence->fence) {
3717 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3718 return VK_NOT_READY;
3719 }
3720 if (fence->fence_wsi) {
3721 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3722
3723 if (result != VK_SUCCESS) {
3724 if (result == VK_TIMEOUT)
3725 return VK_NOT_READY;
3726 return result;
3727 }
3728 }
3729 return VK_SUCCESS;
3730 }
3731
3732
3733 // Queue semaphore functions
3734
3735 VkResult radv_CreateSemaphore(
3736 VkDevice _device,
3737 const VkSemaphoreCreateInfo* pCreateInfo,
3738 const VkAllocationCallbacks* pAllocator,
3739 VkSemaphore* pSemaphore)
3740 {
3741 RADV_FROM_HANDLE(radv_device, device, _device);
3742 const VkExportSemaphoreCreateInfoKHR *export =
3743 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3744 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3745 export ? export->handleTypes : 0;
3746
3747 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3748 sizeof(*sem), 8,
3749 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3750 if (!sem)
3751 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3752
3753 sem->temp_syncobj = 0;
3754 /* create a syncobject if we are going to export this semaphore */
3755 if (device->always_use_syncobj || handleTypes) {
3756 assert (device->physical_device->rad_info.has_syncobj);
3757 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3758 if (ret) {
3759 vk_free2(&device->alloc, pAllocator, sem);
3760 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3761 }
3762 sem->sem = NULL;
3763 } else {
3764 sem->sem = device->ws->create_sem(device->ws);
3765 if (!sem->sem) {
3766 vk_free2(&device->alloc, pAllocator, sem);
3767 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3768 }
3769 sem->syncobj = 0;
3770 }
3771
3772 *pSemaphore = radv_semaphore_to_handle(sem);
3773 return VK_SUCCESS;
3774 }
3775
3776 void radv_DestroySemaphore(
3777 VkDevice _device,
3778 VkSemaphore _semaphore,
3779 const VkAllocationCallbacks* pAllocator)
3780 {
3781 RADV_FROM_HANDLE(radv_device, device, _device);
3782 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3783 if (!_semaphore)
3784 return;
3785
3786 if (sem->syncobj)
3787 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3788 else
3789 device->ws->destroy_sem(sem->sem);
3790 vk_free2(&device->alloc, pAllocator, sem);
3791 }
3792
3793 VkResult radv_CreateEvent(
3794 VkDevice _device,
3795 const VkEventCreateInfo* pCreateInfo,
3796 const VkAllocationCallbacks* pAllocator,
3797 VkEvent* pEvent)
3798 {
3799 RADV_FROM_HANDLE(radv_device, device, _device);
3800 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3801 sizeof(*event), 8,
3802 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3803
3804 if (!event)
3805 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3806
3807 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3808 RADEON_DOMAIN_GTT,
3809 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3810 if (!event->bo) {
3811 vk_free2(&device->alloc, pAllocator, event);
3812 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3813 }
3814
3815 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3816
3817 *pEvent = radv_event_to_handle(event);
3818
3819 return VK_SUCCESS;
3820 }
3821
3822 void radv_DestroyEvent(
3823 VkDevice _device,
3824 VkEvent _event,
3825 const VkAllocationCallbacks* pAllocator)
3826 {
3827 RADV_FROM_HANDLE(radv_device, device, _device);
3828 RADV_FROM_HANDLE(radv_event, event, _event);
3829
3830 if (!event)
3831 return;
3832 device->ws->buffer_destroy(event->bo);
3833 vk_free2(&device->alloc, pAllocator, event);
3834 }
3835
3836 VkResult radv_GetEventStatus(
3837 VkDevice _device,
3838 VkEvent _event)
3839 {
3840 RADV_FROM_HANDLE(radv_event, event, _event);
3841
3842 if (*event->map == 1)
3843 return VK_EVENT_SET;
3844 return VK_EVENT_RESET;
3845 }
3846
3847 VkResult radv_SetEvent(
3848 VkDevice _device,
3849 VkEvent _event)
3850 {
3851 RADV_FROM_HANDLE(radv_event, event, _event);
3852 *event->map = 1;
3853
3854 return VK_SUCCESS;
3855 }
3856
3857 VkResult radv_ResetEvent(
3858 VkDevice _device,
3859 VkEvent _event)
3860 {
3861 RADV_FROM_HANDLE(radv_event, event, _event);
3862 *event->map = 0;
3863
3864 return VK_SUCCESS;
3865 }
3866
3867 VkResult radv_CreateBuffer(
3868 VkDevice _device,
3869 const VkBufferCreateInfo* pCreateInfo,
3870 const VkAllocationCallbacks* pAllocator,
3871 VkBuffer* pBuffer)
3872 {
3873 RADV_FROM_HANDLE(radv_device, device, _device);
3874 struct radv_buffer *buffer;
3875
3876 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3877
3878 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3879 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3880 if (buffer == NULL)
3881 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3882
3883 buffer->size = pCreateInfo->size;
3884 buffer->usage = pCreateInfo->usage;
3885 buffer->bo = NULL;
3886 buffer->offset = 0;
3887 buffer->flags = pCreateInfo->flags;
3888
3889 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3890 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3891
3892 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3893 buffer->bo = device->ws->buffer_create(device->ws,
3894 align64(buffer->size, 4096),
3895 4096, 0, RADEON_FLAG_VIRTUAL);
3896 if (!buffer->bo) {
3897 vk_free2(&device->alloc, pAllocator, buffer);
3898 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3899 }
3900 }
3901
3902 *pBuffer = radv_buffer_to_handle(buffer);
3903
3904 return VK_SUCCESS;
3905 }
3906
3907 void radv_DestroyBuffer(
3908 VkDevice _device,
3909 VkBuffer _buffer,
3910 const VkAllocationCallbacks* pAllocator)
3911 {
3912 RADV_FROM_HANDLE(radv_device, device, _device);
3913 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3914
3915 if (!buffer)
3916 return;
3917
3918 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3919 device->ws->buffer_destroy(buffer->bo);
3920
3921 vk_free2(&device->alloc, pAllocator, buffer);
3922 }
3923
3924 static inline unsigned
3925 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3926 {
3927 if (stencil)
3928 return image->surface.u.legacy.stencil_tiling_index[level];
3929 else
3930 return image->surface.u.legacy.tiling_index[level];
3931 }
3932
3933 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3934 {
3935 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3936 }
3937
3938 static uint32_t
3939 radv_init_dcc_control_reg(struct radv_device *device,
3940 struct radv_image_view *iview)
3941 {
3942 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3943 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3944 unsigned max_compressed_block_size;
3945 unsigned independent_64b_blocks;
3946
3947 if (!radv_image_has_dcc(iview->image))
3948 return 0;
3949
3950 if (iview->image->info.samples > 1) {
3951 if (iview->image->surface.bpe == 1)
3952 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3953 else if (iview->image->surface.bpe == 2)
3954 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3955 }
3956
3957 if (!device->physical_device->rad_info.has_dedicated_vram) {
3958 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3959 * dGPU and 64 for APU because all of our APUs to date use
3960 * DIMMs which have a request granularity size of 64B while all
3961 * other chips have a 32B request size.
3962 */
3963 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3964 }
3965
3966 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3967 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3968 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3969 /* If this DCC image is potentially going to be used in texture
3970 * fetches, we need some special settings.
3971 */
3972 independent_64b_blocks = 1;
3973 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3974 } else {
3975 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3976 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3977 * big as possible for better compression state.
3978 */
3979 independent_64b_blocks = 0;
3980 max_compressed_block_size = max_uncompressed_block_size;
3981 }
3982
3983 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3984 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3985 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3986 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3987 }
3988
3989 static void
3990 radv_initialise_color_surface(struct radv_device *device,
3991 struct radv_color_buffer_info *cb,
3992 struct radv_image_view *iview)
3993 {
3994 const struct vk_format_description *desc;
3995 unsigned ntype, format, swap, endian;
3996 unsigned blend_clamp = 0, blend_bypass = 0;
3997 uint64_t va;
3998 const struct radeon_surf *surf = &iview->image->surface;
3999
4000 desc = vk_format_description(iview->vk_format);
4001
4002 memset(cb, 0, sizeof(*cb));
4003
4004 /* Intensity is implemented as Red, so treat it that way. */
4005 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4006
4007 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4008
4009 cb->cb_color_base = va >> 8;
4010
4011 if (device->physical_device->rad_info.chip_class >= GFX9) {
4012 struct gfx9_surf_meta_flags meta;
4013 if (iview->image->dcc_offset)
4014 meta = iview->image->surface.u.gfx9.dcc;
4015 else
4016 meta = iview->image->surface.u.gfx9.cmask;
4017
4018 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4019 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
4020 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4021 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4022
4023 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
4024 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4025 } else {
4026 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4027 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4028
4029 cb->cb_color_base += level_info->offset >> 8;
4030 if (level_info->mode == RADEON_SURF_MODE_2D)
4031 cb->cb_color_base |= iview->image->surface.tile_swizzle;
4032
4033 pitch_tile_max = level_info->nblk_x / 8 - 1;
4034 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4035 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
4036
4037 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4038 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4039 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4040
4041 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4042
4043 if (radv_image_has_fmask(iview->image)) {
4044 if (device->physical_device->rad_info.chip_class >= CIK)
4045 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4046 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4047 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4048 } else {
4049 /* This must be set for fast clear to work without FMASK. */
4050 if (device->physical_device->rad_info.chip_class >= CIK)
4051 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4052 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4053 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4054 }
4055 }
4056
4057 /* CMASK variables */
4058 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4059 va += iview->image->cmask.offset;
4060 cb->cb_color_cmask = va >> 8;
4061
4062 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4063 va += iview->image->dcc_offset;
4064 cb->cb_dcc_base = va >> 8;
4065 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
4066
4067 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4068 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4069 S_028C6C_SLICE_MAX(max_slice);
4070
4071 if (iview->image->info.samples > 1) {
4072 unsigned log_samples = util_logbase2(iview->image->info.samples);
4073
4074 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4075 S_028C74_NUM_FRAGMENTS(log_samples);
4076 }
4077
4078 if (radv_image_has_fmask(iview->image)) {
4079 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4080 cb->cb_color_fmask = va >> 8;
4081 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4082 } else {
4083 cb->cb_color_fmask = cb->cb_color_base;
4084 }
4085
4086 ntype = radv_translate_color_numformat(iview->vk_format,
4087 desc,
4088 vk_format_get_first_non_void_channel(iview->vk_format));
4089 format = radv_translate_colorformat(iview->vk_format);
4090 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4091 radv_finishme("Illegal color\n");
4092 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4093 endian = radv_colorformat_endian_swap(format);
4094
4095 /* blend clamp should be set for all NORM/SRGB types */
4096 if (ntype == V_028C70_NUMBER_UNORM ||
4097 ntype == V_028C70_NUMBER_SNORM ||
4098 ntype == V_028C70_NUMBER_SRGB)
4099 blend_clamp = 1;
4100
4101 /* set blend bypass according to docs if SINT/UINT or
4102 8/24 COLOR variants */
4103 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4104 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4105 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4106 blend_clamp = 0;
4107 blend_bypass = 1;
4108 }
4109 #if 0
4110 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4111 (format == V_028C70_COLOR_8 ||
4112 format == V_028C70_COLOR_8_8 ||
4113 format == V_028C70_COLOR_8_8_8_8))
4114 ->color_is_int8 = true;
4115 #endif
4116 cb->cb_color_info = S_028C70_FORMAT(format) |
4117 S_028C70_COMP_SWAP(swap) |
4118 S_028C70_BLEND_CLAMP(blend_clamp) |
4119 S_028C70_BLEND_BYPASS(blend_bypass) |
4120 S_028C70_SIMPLE_FLOAT(1) |
4121 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4122 ntype != V_028C70_NUMBER_SNORM &&
4123 ntype != V_028C70_NUMBER_SRGB &&
4124 format != V_028C70_COLOR_8_24 &&
4125 format != V_028C70_COLOR_24_8) |
4126 S_028C70_NUMBER_TYPE(ntype) |
4127 S_028C70_ENDIAN(endian);
4128 if (radv_image_has_fmask(iview->image)) {
4129 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4130 if (device->physical_device->rad_info.chip_class == SI) {
4131 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4132 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4133 }
4134 }
4135
4136 if (radv_image_has_cmask(iview->image) &&
4137 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4138 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4139
4140 if (radv_dcc_enabled(iview->image, iview->base_mip))
4141 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4142
4143 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4144
4145 /* This must be set for fast clear to work without FMASK. */
4146 if (!radv_image_has_fmask(iview->image) &&
4147 device->physical_device->rad_info.chip_class == SI) {
4148 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
4149 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4150 }
4151
4152 if (device->physical_device->rad_info.chip_class >= GFX9) {
4153 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4154 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4155
4156 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4157 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4158 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
4159 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4160 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4161 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4162 }
4163 }
4164
4165 static unsigned
4166 radv_calc_decompress_on_z_planes(struct radv_device *device,
4167 struct radv_image_view *iview)
4168 {
4169 unsigned max_zplanes = 0;
4170
4171 assert(radv_image_is_tc_compat_htile(iview->image));
4172
4173 if (device->physical_device->rad_info.chip_class >= GFX9) {
4174 /* Default value for 32-bit depth surfaces. */
4175 max_zplanes = 4;
4176
4177 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4178 iview->image->info.samples > 1)
4179 max_zplanes = 2;
4180
4181 max_zplanes = max_zplanes + 1;
4182 } else {
4183 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4184 /* Do not enable Z plane compression for 16-bit depth
4185 * surfaces because isn't supported on GFX8. Only
4186 * 32-bit depth surfaces are supported by the hardware.
4187 * This allows to maintain shader compatibility and to
4188 * reduce the number of depth decompressions.
4189 */
4190 max_zplanes = 1;
4191 } else {
4192 if (iview->image->info.samples <= 1)
4193 max_zplanes = 5;
4194 else if (iview->image->info.samples <= 4)
4195 max_zplanes = 3;
4196 else
4197 max_zplanes = 2;
4198 }
4199 }
4200
4201 return max_zplanes;
4202 }
4203
4204 static void
4205 radv_initialise_ds_surface(struct radv_device *device,
4206 struct radv_ds_buffer_info *ds,
4207 struct radv_image_view *iview)
4208 {
4209 unsigned level = iview->base_mip;
4210 unsigned format, stencil_format;
4211 uint64_t va, s_offs, z_offs;
4212 bool stencil_only = false;
4213 memset(ds, 0, sizeof(*ds));
4214 switch (iview->image->vk_format) {
4215 case VK_FORMAT_D24_UNORM_S8_UINT:
4216 case VK_FORMAT_X8_D24_UNORM_PACK32:
4217 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4218 ds->offset_scale = 2.0f;
4219 break;
4220 case VK_FORMAT_D16_UNORM:
4221 case VK_FORMAT_D16_UNORM_S8_UINT:
4222 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4223 ds->offset_scale = 4.0f;
4224 break;
4225 case VK_FORMAT_D32_SFLOAT:
4226 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4227 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4228 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4229 ds->offset_scale = 1.0f;
4230 break;
4231 case VK_FORMAT_S8_UINT:
4232 stencil_only = true;
4233 break;
4234 default:
4235 break;
4236 }
4237
4238 format = radv_translate_dbformat(iview->image->vk_format);
4239 stencil_format = iview->image->surface.has_stencil ?
4240 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4241
4242 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4243 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4244 S_028008_SLICE_MAX(max_slice);
4245
4246 ds->db_htile_data_base = 0;
4247 ds->db_htile_surface = 0;
4248
4249 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4250 s_offs = z_offs = va;
4251
4252 if (device->physical_device->rad_info.chip_class >= GFX9) {
4253 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4254 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4255
4256 ds->db_z_info = S_028038_FORMAT(format) |
4257 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4258 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4259 S_028038_MAXMIP(iview->image->info.levels - 1) |
4260 S_028038_ZRANGE_PRECISION(1);
4261 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4262 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4263
4264 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4265 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4266 ds->db_depth_view |= S_028008_MIPID(level);
4267
4268 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4269 S_02801C_Y_MAX(iview->image->info.height - 1);
4270
4271 if (radv_htile_enabled(iview->image, level)) {
4272 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4273
4274 if (radv_image_is_tc_compat_htile(iview->image)) {
4275 unsigned max_zplanes =
4276 radv_calc_decompress_on_z_planes(device, iview);
4277
4278 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4279 S_028038_ITERATE_FLUSH(1);
4280 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4281 }
4282
4283 if (!iview->image->surface.has_stencil)
4284 /* Use all of the htile_buffer for depth if there's no stencil. */
4285 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4286 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4287 iview->image->htile_offset;
4288 ds->db_htile_data_base = va >> 8;
4289 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4290 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4291 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4292 }
4293 } else {
4294 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4295
4296 if (stencil_only)
4297 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4298
4299 z_offs += iview->image->surface.u.legacy.level[level].offset;
4300 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4301
4302 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4303 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4304 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4305
4306 if (iview->image->info.samples > 1)
4307 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4308
4309 if (device->physical_device->rad_info.chip_class >= CIK) {
4310 struct radeon_info *info = &device->physical_device->rad_info;
4311 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4312 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4313 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4314 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4315 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4316 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4317
4318 if (stencil_only)
4319 tile_mode = stencil_tile_mode;
4320
4321 ds->db_depth_info |=
4322 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4323 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4324 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4325 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4326 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4327 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4328 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4329 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4330 } else {
4331 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4332 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4333 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4334 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4335 if (stencil_only)
4336 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4337 }
4338
4339 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4340 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4341 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4342
4343 if (radv_htile_enabled(iview->image, level)) {
4344 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4345
4346 if (!iview->image->surface.has_stencil &&
4347 !radv_image_is_tc_compat_htile(iview->image))
4348 /* Use all of the htile_buffer for depth if there's no stencil. */
4349 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4350
4351 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4352 iview->image->htile_offset;
4353 ds->db_htile_data_base = va >> 8;
4354 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4355
4356 if (radv_image_is_tc_compat_htile(iview->image)) {
4357 unsigned max_zplanes =
4358 radv_calc_decompress_on_z_planes(device, iview);
4359
4360 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4361 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4362 }
4363 }
4364 }
4365
4366 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4367 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4368 }
4369
4370 VkResult radv_CreateFramebuffer(
4371 VkDevice _device,
4372 const VkFramebufferCreateInfo* pCreateInfo,
4373 const VkAllocationCallbacks* pAllocator,
4374 VkFramebuffer* pFramebuffer)
4375 {
4376 RADV_FROM_HANDLE(radv_device, device, _device);
4377 struct radv_framebuffer *framebuffer;
4378
4379 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4380
4381 size_t size = sizeof(*framebuffer) +
4382 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4383 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4384 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4385 if (framebuffer == NULL)
4386 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4387
4388 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4389 framebuffer->width = pCreateInfo->width;
4390 framebuffer->height = pCreateInfo->height;
4391 framebuffer->layers = pCreateInfo->layers;
4392 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4393 VkImageView _iview = pCreateInfo->pAttachments[i];
4394 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4395 framebuffer->attachments[i].attachment = iview;
4396 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4397 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4398 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4399 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4400 }
4401 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4402 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4403 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4404 }
4405
4406 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4407 return VK_SUCCESS;
4408 }
4409
4410 void radv_DestroyFramebuffer(
4411 VkDevice _device,
4412 VkFramebuffer _fb,
4413 const VkAllocationCallbacks* pAllocator)
4414 {
4415 RADV_FROM_HANDLE(radv_device, device, _device);
4416 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4417
4418 if (!fb)
4419 return;
4420 vk_free2(&device->alloc, pAllocator, fb);
4421 }
4422
4423 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4424 {
4425 switch (address_mode) {
4426 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4427 return V_008F30_SQ_TEX_WRAP;
4428 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4429 return V_008F30_SQ_TEX_MIRROR;
4430 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4431 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4432 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4433 return V_008F30_SQ_TEX_CLAMP_BORDER;
4434 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4435 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4436 default:
4437 unreachable("illegal tex wrap mode");
4438 break;
4439 }
4440 }
4441
4442 static unsigned
4443 radv_tex_compare(VkCompareOp op)
4444 {
4445 switch (op) {
4446 case VK_COMPARE_OP_NEVER:
4447 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4448 case VK_COMPARE_OP_LESS:
4449 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4450 case VK_COMPARE_OP_EQUAL:
4451 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4452 case VK_COMPARE_OP_LESS_OR_EQUAL:
4453 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4454 case VK_COMPARE_OP_GREATER:
4455 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4456 case VK_COMPARE_OP_NOT_EQUAL:
4457 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4458 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4459 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4460 case VK_COMPARE_OP_ALWAYS:
4461 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4462 default:
4463 unreachable("illegal compare mode");
4464 break;
4465 }
4466 }
4467
4468 static unsigned
4469 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4470 {
4471 switch (filter) {
4472 case VK_FILTER_NEAREST:
4473 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4474 V_008F38_SQ_TEX_XY_FILTER_POINT);
4475 case VK_FILTER_LINEAR:
4476 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4477 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4478 case VK_FILTER_CUBIC_IMG:
4479 default:
4480 fprintf(stderr, "illegal texture filter");
4481 return 0;
4482 }
4483 }
4484
4485 static unsigned
4486 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4487 {
4488 switch (mode) {
4489 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4490 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4491 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4492 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4493 default:
4494 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4495 }
4496 }
4497
4498 static unsigned
4499 radv_tex_bordercolor(VkBorderColor bcolor)
4500 {
4501 switch (bcolor) {
4502 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4503 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4504 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4505 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4506 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4507 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4508 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4509 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4510 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4511 default:
4512 break;
4513 }
4514 return 0;
4515 }
4516
4517 static unsigned
4518 radv_tex_aniso_filter(unsigned filter)
4519 {
4520 if (filter < 2)
4521 return 0;
4522 if (filter < 4)
4523 return 1;
4524 if (filter < 8)
4525 return 2;
4526 if (filter < 16)
4527 return 3;
4528 return 4;
4529 }
4530
4531 static unsigned
4532 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4533 {
4534 switch (mode) {
4535 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4536 return SQ_IMG_FILTER_MODE_BLEND;
4537 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4538 return SQ_IMG_FILTER_MODE_MIN;
4539 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4540 return SQ_IMG_FILTER_MODE_MAX;
4541 default:
4542 break;
4543 }
4544 return 0;
4545 }
4546
4547 static uint32_t
4548 radv_get_max_anisotropy(struct radv_device *device,
4549 const VkSamplerCreateInfo *pCreateInfo)
4550 {
4551 if (device->force_aniso >= 0)
4552 return device->force_aniso;
4553
4554 if (pCreateInfo->anisotropyEnable &&
4555 pCreateInfo->maxAnisotropy > 1.0f)
4556 return (uint32_t)pCreateInfo->maxAnisotropy;
4557
4558 return 0;
4559 }
4560
4561 static void
4562 radv_init_sampler(struct radv_device *device,
4563 struct radv_sampler *sampler,
4564 const VkSamplerCreateInfo *pCreateInfo)
4565 {
4566 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4567 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4568 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4569 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4570
4571 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4572 vk_find_struct_const(pCreateInfo->pNext,
4573 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4574 if (sampler_reduction)
4575 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4576
4577 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4578 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4579 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4580 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4581 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4582 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4583 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4584 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4585 S_008F30_DISABLE_CUBE_WRAP(0) |
4586 S_008F30_COMPAT_MODE(is_vi) |
4587 S_008F30_FILTER_MODE(filter_mode));
4588 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4589 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4590 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4591 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4592 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4593 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4594 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4595 S_008F38_MIP_POINT_PRECLAMP(0) |
4596 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4597 S_008F38_FILTER_PREC_FIX(1) |
4598 S_008F38_ANISO_OVERRIDE(is_vi));
4599 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4600 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4601 }
4602
4603 VkResult radv_CreateSampler(
4604 VkDevice _device,
4605 const VkSamplerCreateInfo* pCreateInfo,
4606 const VkAllocationCallbacks* pAllocator,
4607 VkSampler* pSampler)
4608 {
4609 RADV_FROM_HANDLE(radv_device, device, _device);
4610 struct radv_sampler *sampler;
4611
4612 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4613
4614 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4615 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4616 if (!sampler)
4617 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4618
4619 radv_init_sampler(device, sampler, pCreateInfo);
4620 *pSampler = radv_sampler_to_handle(sampler);
4621
4622 return VK_SUCCESS;
4623 }
4624
4625 void radv_DestroySampler(
4626 VkDevice _device,
4627 VkSampler _sampler,
4628 const VkAllocationCallbacks* pAllocator)
4629 {
4630 RADV_FROM_HANDLE(radv_device, device, _device);
4631 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4632
4633 if (!sampler)
4634 return;
4635 vk_free2(&device->alloc, pAllocator, sampler);
4636 }
4637
4638 /* vk_icd.h does not declare this function, so we declare it here to
4639 * suppress Wmissing-prototypes.
4640 */
4641 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4642 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4643
4644 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4645 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4646 {
4647 /* For the full details on loader interface versioning, see
4648 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4649 * What follows is a condensed summary, to help you navigate the large and
4650 * confusing official doc.
4651 *
4652 * - Loader interface v0 is incompatible with later versions. We don't
4653 * support it.
4654 *
4655 * - In loader interface v1:
4656 * - The first ICD entrypoint called by the loader is
4657 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4658 * entrypoint.
4659 * - The ICD must statically expose no other Vulkan symbol unless it is
4660 * linked with -Bsymbolic.
4661 * - Each dispatchable Vulkan handle created by the ICD must be
4662 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4663 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4664 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4665 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4666 * such loader-managed surfaces.
4667 *
4668 * - Loader interface v2 differs from v1 in:
4669 * - The first ICD entrypoint called by the loader is
4670 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4671 * statically expose this entrypoint.
4672 *
4673 * - Loader interface v3 differs from v2 in:
4674 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4675 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4676 * because the loader no longer does so.
4677 */
4678 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4679 return VK_SUCCESS;
4680 }
4681
4682 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4683 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4684 int *pFD)
4685 {
4686 RADV_FROM_HANDLE(radv_device, device, _device);
4687 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4688
4689 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4690
4691 /* At the moment, we support only the below handle types. */
4692 assert(pGetFdInfo->handleType ==
4693 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4694 pGetFdInfo->handleType ==
4695 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4696
4697 bool ret = radv_get_memory_fd(device, memory, pFD);
4698 if (ret == false)
4699 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4700 return VK_SUCCESS;
4701 }
4702
4703 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4704 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4705 int fd,
4706 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4707 {
4708 RADV_FROM_HANDLE(radv_device, device, _device);
4709
4710 switch (handleType) {
4711 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4712 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4713 return VK_SUCCESS;
4714
4715 default:
4716 /* The valid usage section for this function says:
4717 *
4718 * "handleType must not be one of the handle types defined as
4719 * opaque."
4720 *
4721 * So opaque handle types fall into the default "unsupported" case.
4722 */
4723 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4724 }
4725 }
4726
4727 static VkResult radv_import_opaque_fd(struct radv_device *device,
4728 int fd,
4729 uint32_t *syncobj)
4730 {
4731 uint32_t syncobj_handle = 0;
4732 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4733 if (ret != 0)
4734 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4735
4736 if (*syncobj)
4737 device->ws->destroy_syncobj(device->ws, *syncobj);
4738
4739 *syncobj = syncobj_handle;
4740 close(fd);
4741
4742 return VK_SUCCESS;
4743 }
4744
4745 static VkResult radv_import_sync_fd(struct radv_device *device,
4746 int fd,
4747 uint32_t *syncobj)
4748 {
4749 /* If we create a syncobj we do it locally so that if we have an error, we don't
4750 * leave a syncobj in an undetermined state in the fence. */
4751 uint32_t syncobj_handle = *syncobj;
4752 if (!syncobj_handle) {
4753 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4754 if (ret) {
4755 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4756 }
4757 }
4758
4759 if (fd == -1) {
4760 device->ws->signal_syncobj(device->ws, syncobj_handle);
4761 } else {
4762 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4763 if (ret != 0)
4764 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4765 }
4766
4767 *syncobj = syncobj_handle;
4768 if (fd != -1)
4769 close(fd);
4770
4771 return VK_SUCCESS;
4772 }
4773
4774 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4775 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4776 {
4777 RADV_FROM_HANDLE(radv_device, device, _device);
4778 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4779 uint32_t *syncobj_dst = NULL;
4780
4781 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4782 syncobj_dst = &sem->temp_syncobj;
4783 } else {
4784 syncobj_dst = &sem->syncobj;
4785 }
4786
4787 switch(pImportSemaphoreFdInfo->handleType) {
4788 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4789 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4790 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4791 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4792 default:
4793 unreachable("Unhandled semaphore handle type");
4794 }
4795 }
4796
4797 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4798 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4799 int *pFd)
4800 {
4801 RADV_FROM_HANDLE(radv_device, device, _device);
4802 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4803 int ret;
4804 uint32_t syncobj_handle;
4805
4806 if (sem->temp_syncobj)
4807 syncobj_handle = sem->temp_syncobj;
4808 else
4809 syncobj_handle = sem->syncobj;
4810
4811 switch(pGetFdInfo->handleType) {
4812 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4813 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4814 break;
4815 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4816 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4817 if (!ret) {
4818 if (sem->temp_syncobj) {
4819 close (sem->temp_syncobj);
4820 sem->temp_syncobj = 0;
4821 } else {
4822 device->ws->reset_syncobj(device->ws, syncobj_handle);
4823 }
4824 }
4825 break;
4826 default:
4827 unreachable("Unhandled semaphore handle type");
4828 }
4829
4830 if (ret)
4831 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4832 return VK_SUCCESS;
4833 }
4834
4835 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4836 VkPhysicalDevice physicalDevice,
4837 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4838 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4839 {
4840 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4841
4842 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4843 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4844 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4845 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4846 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4847 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4848 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4849 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4850 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4851 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4852 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4853 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4854 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4855 } else {
4856 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4857 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4858 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4859 }
4860 }
4861
4862 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4863 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4864 {
4865 RADV_FROM_HANDLE(radv_device, device, _device);
4866 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4867 uint32_t *syncobj_dst = NULL;
4868
4869
4870 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4871 syncobj_dst = &fence->temp_syncobj;
4872 } else {
4873 syncobj_dst = &fence->syncobj;
4874 }
4875
4876 switch(pImportFenceFdInfo->handleType) {
4877 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4878 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4879 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4880 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4881 default:
4882 unreachable("Unhandled fence handle type");
4883 }
4884 }
4885
4886 VkResult radv_GetFenceFdKHR(VkDevice _device,
4887 const VkFenceGetFdInfoKHR *pGetFdInfo,
4888 int *pFd)
4889 {
4890 RADV_FROM_HANDLE(radv_device, device, _device);
4891 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4892 int ret;
4893 uint32_t syncobj_handle;
4894
4895 if (fence->temp_syncobj)
4896 syncobj_handle = fence->temp_syncobj;
4897 else
4898 syncobj_handle = fence->syncobj;
4899
4900 switch(pGetFdInfo->handleType) {
4901 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4902 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4903 break;
4904 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4905 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4906 if (!ret) {
4907 if (fence->temp_syncobj) {
4908 close (fence->temp_syncobj);
4909 fence->temp_syncobj = 0;
4910 } else {
4911 device->ws->reset_syncobj(device->ws, syncobj_handle);
4912 }
4913 }
4914 break;
4915 default:
4916 unreachable("Unhandled fence handle type");
4917 }
4918
4919 if (ret)
4920 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4921 return VK_SUCCESS;
4922 }
4923
4924 void radv_GetPhysicalDeviceExternalFenceProperties(
4925 VkPhysicalDevice physicalDevice,
4926 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4927 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4928 {
4929 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4930
4931 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4932 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4933 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4934 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4935 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4936 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4937 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4938 } else {
4939 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4940 pExternalFenceProperties->compatibleHandleTypes = 0;
4941 pExternalFenceProperties->externalFenceFeatures = 0;
4942 }
4943 }
4944
4945 VkResult
4946 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4947 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4948 const VkAllocationCallbacks* pAllocator,
4949 VkDebugReportCallbackEXT* pCallback)
4950 {
4951 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4952 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4953 pCreateInfo, pAllocator, &instance->alloc,
4954 pCallback);
4955 }
4956
4957 void
4958 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4959 VkDebugReportCallbackEXT _callback,
4960 const VkAllocationCallbacks* pAllocator)
4961 {
4962 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4963 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4964 _callback, pAllocator, &instance->alloc);
4965 }
4966
4967 void
4968 radv_DebugReportMessageEXT(VkInstance _instance,
4969 VkDebugReportFlagsEXT flags,
4970 VkDebugReportObjectTypeEXT objectType,
4971 uint64_t object,
4972 size_t location,
4973 int32_t messageCode,
4974 const char* pLayerPrefix,
4975 const char* pMessage)
4976 {
4977 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4978 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4979 object, location, messageCode, pLayerPrefix, pMessage);
4980 }
4981
4982 void
4983 radv_GetDeviceGroupPeerMemoryFeatures(
4984 VkDevice device,
4985 uint32_t heapIndex,
4986 uint32_t localDeviceIndex,
4987 uint32_t remoteDeviceIndex,
4988 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4989 {
4990 assert(localDeviceIndex == remoteDeviceIndex);
4991
4992 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4993 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4994 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4995 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4996 }
4997
4998 static const VkTimeDomainEXT radv_time_domains[] = {
4999 VK_TIME_DOMAIN_DEVICE_EXT,
5000 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5001 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5002 };
5003
5004 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5005 VkPhysicalDevice physicalDevice,
5006 uint32_t *pTimeDomainCount,
5007 VkTimeDomainEXT *pTimeDomains)
5008 {
5009 int d;
5010 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5011
5012 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5013 vk_outarray_append(&out, i) {
5014 *i = radv_time_domains[d];
5015 }
5016 }
5017
5018 return vk_outarray_status(&out);
5019 }
5020
5021 static uint64_t
5022 radv_clock_gettime(clockid_t clock_id)
5023 {
5024 struct timespec current;
5025 int ret;
5026
5027 ret = clock_gettime(clock_id, &current);
5028 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5029 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5030 if (ret < 0)
5031 return 0;
5032
5033 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5034 }
5035
5036 VkResult radv_GetCalibratedTimestampsEXT(
5037 VkDevice _device,
5038 uint32_t timestampCount,
5039 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5040 uint64_t *pTimestamps,
5041 uint64_t *pMaxDeviation)
5042 {
5043 RADV_FROM_HANDLE(radv_device, device, _device);
5044 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5045 int d;
5046 uint64_t begin, end;
5047 uint64_t max_clock_period = 0;
5048
5049 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5050
5051 for (d = 0; d < timestampCount; d++) {
5052 switch (pTimestampInfos[d].timeDomain) {
5053 case VK_TIME_DOMAIN_DEVICE_EXT:
5054 pTimestamps[d] = device->ws->query_value(device->ws,
5055 RADEON_TIMESTAMP);
5056 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5057 max_clock_period = MAX2(max_clock_period, device_period);
5058 break;
5059 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5060 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5061 max_clock_period = MAX2(max_clock_period, 1);
5062 break;
5063
5064 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5065 pTimestamps[d] = begin;
5066 break;
5067 default:
5068 pTimestamps[d] = 0;
5069 break;
5070 }
5071 }
5072
5073 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5074
5075 /*
5076 * The maximum deviation is the sum of the interval over which we
5077 * perform the sampling and the maximum period of any sampled
5078 * clock. That's because the maximum skew between any two sampled
5079 * clock edges is when the sampled clock with the largest period is
5080 * sampled at the end of that period but right at the beginning of the
5081 * sampling interval and some other clock is sampled right at the
5082 * begining of its sampling period and right at the end of the
5083 * sampling interval. Let's assume the GPU has the longest clock
5084 * period and that the application is sampling GPU and monotonic:
5085 *
5086 * s e
5087 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5088 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5089 *
5090 * g
5091 * 0 1 2 3
5092 * GPU -----_____-----_____-----_____-----_____
5093 *
5094 * m
5095 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5096 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5097 *
5098 * Interval <----------------->
5099 * Deviation <-------------------------->
5100 *
5101 * s = read(raw) 2
5102 * g = read(GPU) 1
5103 * m = read(monotonic) 2
5104 * e = read(raw) b
5105 *
5106 * We round the sample interval up by one tick to cover sampling error
5107 * in the interval clock
5108 */
5109
5110 uint64_t sample_interval = end - begin + 1;
5111
5112 *pMaxDeviation = sample_interval + max_clock_period;
5113
5114 return VK_SUCCESS;
5115 }