2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
48 #include "util/debug.h"
51 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
53 uint32_t mesa_timestamp
, llvm_timestamp
;
55 memset(uuid
, 0, VK_UUID_SIZE
);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid
, &mesa_timestamp
) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo
, &llvm_timestamp
))
60 memcpy(uuid
, &mesa_timestamp
, 4);
61 memcpy((char*)uuid
+ 4, &llvm_timestamp
, 4);
62 memcpy((char*)uuid
+ 8, &f
, 2);
63 snprintf((char*)uuid
+ 10, VK_UUID_SIZE
- 10, "radv");
68 radv_get_driver_uuid(void *uuid
)
70 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
74 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
76 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
80 get_chip_name(enum radeon_family family
)
83 case CHIP_TAHITI
: return "AMD RADV TAHITI";
84 case CHIP_PITCAIRN
: return "AMD RADV PITCAIRN";
85 case CHIP_VERDE
: return "AMD RADV CAPE VERDE";
86 case CHIP_OLAND
: return "AMD RADV OLAND";
87 case CHIP_HAINAN
: return "AMD RADV HAINAN";
88 case CHIP_BONAIRE
: return "AMD RADV BONAIRE";
89 case CHIP_KAVERI
: return "AMD RADV KAVERI";
90 case CHIP_KABINI
: return "AMD RADV KABINI";
91 case CHIP_HAWAII
: return "AMD RADV HAWAII";
92 case CHIP_MULLINS
: return "AMD RADV MULLINS";
93 case CHIP_TONGA
: return "AMD RADV TONGA";
94 case CHIP_ICELAND
: return "AMD RADV ICELAND";
95 case CHIP_CARRIZO
: return "AMD RADV CARRIZO";
96 case CHIP_FIJI
: return "AMD RADV FIJI";
97 case CHIP_POLARIS10
: return "AMD RADV POLARIS10";
98 case CHIP_POLARIS11
: return "AMD RADV POLARIS11";
99 case CHIP_POLARIS12
: return "AMD RADV POLARIS12";
100 case CHIP_STONEY
: return "AMD RADV STONEY";
101 case CHIP_VEGA10
: return "AMD RADV VEGA";
102 case CHIP_RAVEN
: return "AMD RADV RAVEN";
103 default: return "AMD RADV unknown";
108 radv_physical_device_init(struct radv_physical_device
*device
,
109 struct radv_instance
*instance
,
110 drmDevicePtr drm_device
)
112 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
114 drmVersionPtr version
;
117 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
119 return VK_ERROR_INCOMPATIBLE_DRIVER
;
121 version
= drmGetVersion(fd
);
124 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
125 "failed to get version %s: %m", path
);
128 if (strcmp(version
->name
, "amdgpu")) {
129 drmFreeVersion(version
);
131 return VK_ERROR_INCOMPATIBLE_DRIVER
;
133 drmFreeVersion(version
);
135 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
136 device
->instance
= instance
;
137 assert(strlen(path
) < ARRAY_SIZE(device
->path
));
138 strncpy(device
->path
, path
, ARRAY_SIZE(device
->path
));
140 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
141 instance
->perftest_flags
);
143 result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
147 device
->local_fd
= fd
;
148 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
149 result
= radv_init_wsi(device
);
150 if (result
!= VK_SUCCESS
) {
151 device
->ws
->destroy(device
->ws
);
155 device
->name
= get_chip_name(device
->rad_info
.family
);
157 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
158 radv_finish_wsi(device
);
159 device
->ws
->destroy(device
->ws
);
160 result
= vk_errorf(VK_ERROR_INITIALIZATION_FAILED
,
161 "cannot generate UUID");
165 /* These flags affect shader compilation. */
166 uint64_t shader_env_flags
=
167 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
168 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0);
170 /* The gpu id is already embeded in the uuid so we just pass "radv"
171 * when creating the cache.
173 char buf
[VK_UUID_SIZE
* 2 + 1];
174 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
175 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
177 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
179 radv_get_driver_uuid(&device
->device_uuid
);
180 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
182 if (device
->rad_info
.family
== CHIP_STONEY
||
183 device
->rad_info
.chip_class
>= GFX9
) {
184 device
->has_rbplus
= true;
185 device
->rbplus_allowed
= device
->rad_info
.family
== CHIP_STONEY
;
188 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
191 device
->has_clear_state
= device
->rad_info
.chip_class
>= CIK
;
201 radv_physical_device_finish(struct radv_physical_device
*device
)
203 radv_finish_wsi(device
);
204 device
->ws
->destroy(device
->ws
);
205 disk_cache_destroy(device
->disk_cache
);
206 close(device
->local_fd
);
210 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
211 VkSystemAllocationScope allocationScope
)
217 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
218 size_t align
, VkSystemAllocationScope allocationScope
)
220 return realloc(pOriginal
, size
);
224 default_free_func(void *pUserData
, void *pMemory
)
229 static const VkAllocationCallbacks default_alloc
= {
231 .pfnAllocation
= default_alloc_func
,
232 .pfnReallocation
= default_realloc_func
,
233 .pfnFree
= default_free_func
,
236 static const struct debug_control radv_debug_options
[] = {
237 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
238 {"nodcc", RADV_DEBUG_NO_DCC
},
239 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
240 {"nocache", RADV_DEBUG_NO_CACHE
},
241 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
242 {"nohiz", RADV_DEBUG_NO_HIZ
},
243 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
244 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
245 {"allbos", RADV_DEBUG_ALL_BOS
},
246 {"noibs", RADV_DEBUG_NO_IBS
},
247 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
248 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
249 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
250 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
255 radv_get_debug_option_name(int id
)
257 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
258 return radv_debug_options
[id
].string
;
261 static const struct debug_control radv_perftest_options
[] = {
262 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
263 {"sisched", RADV_PERFTEST_SISCHED
},
268 radv_get_perftest_option_name(int id
)
270 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
271 return radv_perftest_options
[id
].string
;
274 VkResult
radv_CreateInstance(
275 const VkInstanceCreateInfo
* pCreateInfo
,
276 const VkAllocationCallbacks
* pAllocator
,
277 VkInstance
* pInstance
)
279 struct radv_instance
*instance
;
281 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
283 uint32_t client_version
;
284 if (pCreateInfo
->pApplicationInfo
&&
285 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
286 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
288 client_version
= VK_MAKE_VERSION(1, 0, 0);
291 if (VK_MAKE_VERSION(1, 0, 0) > client_version
||
292 client_version
> VK_MAKE_VERSION(1, 0, 0xfff)) {
293 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER
,
294 "Client requested version %d.%d.%d",
295 VK_VERSION_MAJOR(client_version
),
296 VK_VERSION_MINOR(client_version
),
297 VK_VERSION_PATCH(client_version
));
300 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
301 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
302 if (!radv_instance_extension_supported(ext_name
))
303 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
306 instance
= vk_alloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
307 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
309 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
311 memset(instance
, 0, sizeof(*instance
));
313 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
316 instance
->alloc
= *pAllocator
;
318 instance
->alloc
= default_alloc
;
320 instance
->apiVersion
= client_version
;
321 instance
->physicalDeviceCount
= -1;
325 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
327 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
330 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
331 radv_perftest_options
);
333 *pInstance
= radv_instance_to_handle(instance
);
338 void radv_DestroyInstance(
339 VkInstance _instance
,
340 const VkAllocationCallbacks
* pAllocator
)
342 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
347 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
348 radv_physical_device_finish(instance
->physicalDevices
+ i
);
351 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
355 vk_free(&instance
->alloc
, instance
);
359 radv_enumerate_devices(struct radv_instance
*instance
)
361 /* TODO: Check for more devices ? */
362 drmDevicePtr devices
[8];
363 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
366 instance
->physicalDeviceCount
= 0;
368 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
370 return VK_ERROR_INCOMPATIBLE_DRIVER
;
372 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
373 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
374 devices
[i
]->bustype
== DRM_BUS_PCI
&&
375 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
377 result
= radv_physical_device_init(instance
->physicalDevices
+
378 instance
->physicalDeviceCount
,
381 if (result
== VK_SUCCESS
)
382 ++instance
->physicalDeviceCount
;
383 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
387 drmFreeDevices(devices
, max_devices
);
392 VkResult
radv_EnumeratePhysicalDevices(
393 VkInstance _instance
,
394 uint32_t* pPhysicalDeviceCount
,
395 VkPhysicalDevice
* pPhysicalDevices
)
397 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
400 if (instance
->physicalDeviceCount
< 0) {
401 result
= radv_enumerate_devices(instance
);
402 if (result
!= VK_SUCCESS
&&
403 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
407 if (!pPhysicalDevices
) {
408 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
410 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
411 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
412 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
415 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
419 void radv_GetPhysicalDeviceFeatures(
420 VkPhysicalDevice physicalDevice
,
421 VkPhysicalDeviceFeatures
* pFeatures
)
423 memset(pFeatures
, 0, sizeof(*pFeatures
));
425 *pFeatures
= (VkPhysicalDeviceFeatures
) {
426 .robustBufferAccess
= true,
427 .fullDrawIndexUint32
= true,
428 .imageCubeArray
= true,
429 .independentBlend
= true,
430 .geometryShader
= true,
431 .tessellationShader
= true,
432 .sampleRateShading
= true,
433 .dualSrcBlend
= true,
435 .multiDrawIndirect
= true,
436 .drawIndirectFirstInstance
= true,
438 .depthBiasClamp
= true,
439 .fillModeNonSolid
= true,
444 .multiViewport
= true,
445 .samplerAnisotropy
= true,
446 .textureCompressionETC2
= false,
447 .textureCompressionASTC_LDR
= false,
448 .textureCompressionBC
= true,
449 .occlusionQueryPrecise
= true,
450 .pipelineStatisticsQuery
= true,
451 .vertexPipelineStoresAndAtomics
= true,
452 .fragmentStoresAndAtomics
= true,
453 .shaderTessellationAndGeometryPointSize
= true,
454 .shaderImageGatherExtended
= true,
455 .shaderStorageImageExtendedFormats
= true,
456 .shaderStorageImageMultisample
= false,
457 .shaderUniformBufferArrayDynamicIndexing
= true,
458 .shaderSampledImageArrayDynamicIndexing
= true,
459 .shaderStorageBufferArrayDynamicIndexing
= true,
460 .shaderStorageImageArrayDynamicIndexing
= true,
461 .shaderStorageImageReadWithoutFormat
= true,
462 .shaderStorageImageWriteWithoutFormat
= true,
463 .shaderClipDistance
= true,
464 .shaderCullDistance
= true,
465 .shaderFloat64
= true,
467 .shaderInt16
= false,
468 .sparseBinding
= true,
469 .variableMultisampleRate
= true,
470 .inheritedQueries
= true,
474 void radv_GetPhysicalDeviceFeatures2KHR(
475 VkPhysicalDevice physicalDevice
,
476 VkPhysicalDeviceFeatures2KHR
*pFeatures
)
478 vk_foreach_struct(ext
, pFeatures
->pNext
) {
479 switch (ext
->sType
) {
480 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR
: {
481 VkPhysicalDeviceVariablePointerFeaturesKHR
*features
= (void *)ext
;
482 features
->variablePointersStorageBuffer
= true;
483 features
->variablePointers
= false;
486 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX
: {
487 VkPhysicalDeviceMultiviewFeaturesKHX
*features
= (VkPhysicalDeviceMultiviewFeaturesKHX
*)ext
;
488 features
->multiview
= true;
489 features
->multiviewGeometryShader
= true;
490 features
->multiviewTessellationShader
= true;
497 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
500 void radv_GetPhysicalDeviceProperties(
501 VkPhysicalDevice physicalDevice
,
502 VkPhysicalDeviceProperties
* pProperties
)
504 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
505 VkSampleCountFlags sample_counts
= 0xf;
507 /* make sure that the entire descriptor set is addressable with a signed
508 * 32-bit int. So the sum of all limits scaled by descriptor size has to
509 * be at most 2 GiB. the combined image & samples object count as one of
510 * both. This limit is for the pipeline layout, not for the set layout, but
511 * there is no set limit, so we just set a pipeline limit. I don't think
512 * any app is going to hit this soon. */
513 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
514 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
515 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
516 32 /* sampler, largest when combined with image */ +
517 64 /* sampled image */ +
518 64 /* storage image */);
520 VkPhysicalDeviceLimits limits
= {
521 .maxImageDimension1D
= (1 << 14),
522 .maxImageDimension2D
= (1 << 14),
523 .maxImageDimension3D
= (1 << 11),
524 .maxImageDimensionCube
= (1 << 14),
525 .maxImageArrayLayers
= (1 << 11),
526 .maxTexelBufferElements
= 128 * 1024 * 1024,
527 .maxUniformBufferRange
= UINT32_MAX
,
528 .maxStorageBufferRange
= UINT32_MAX
,
529 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
530 .maxMemoryAllocationCount
= UINT32_MAX
,
531 .maxSamplerAllocationCount
= 64 * 1024,
532 .bufferImageGranularity
= 64, /* A cache line */
533 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
534 .maxBoundDescriptorSets
= MAX_SETS
,
535 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
536 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
537 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
538 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
539 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
540 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
541 .maxPerStageResources
= max_descriptor_set_size
,
542 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
543 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
544 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
545 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
546 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_BUFFERS
/ 2,
547 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
548 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
549 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
550 .maxVertexInputAttributes
= 32,
551 .maxVertexInputBindings
= 32,
552 .maxVertexInputAttributeOffset
= 2047,
553 .maxVertexInputBindingStride
= 2048,
554 .maxVertexOutputComponents
= 128,
555 .maxTessellationGenerationLevel
= 64,
556 .maxTessellationPatchSize
= 32,
557 .maxTessellationControlPerVertexInputComponents
= 128,
558 .maxTessellationControlPerVertexOutputComponents
= 128,
559 .maxTessellationControlPerPatchOutputComponents
= 120,
560 .maxTessellationControlTotalOutputComponents
= 4096,
561 .maxTessellationEvaluationInputComponents
= 128,
562 .maxTessellationEvaluationOutputComponents
= 128,
563 .maxGeometryShaderInvocations
= 127,
564 .maxGeometryInputComponents
= 64,
565 .maxGeometryOutputComponents
= 128,
566 .maxGeometryOutputVertices
= 256,
567 .maxGeometryTotalOutputComponents
= 1024,
568 .maxFragmentInputComponents
= 128,
569 .maxFragmentOutputAttachments
= 8,
570 .maxFragmentDualSrcAttachments
= 1,
571 .maxFragmentCombinedOutputResources
= 8,
572 .maxComputeSharedMemorySize
= 32768,
573 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
574 .maxComputeWorkGroupInvocations
= 2048,
575 .maxComputeWorkGroupSize
= {
580 .subPixelPrecisionBits
= 4 /* FIXME */,
581 .subTexelPrecisionBits
= 4 /* FIXME */,
582 .mipmapPrecisionBits
= 4 /* FIXME */,
583 .maxDrawIndexedIndexValue
= UINT32_MAX
,
584 .maxDrawIndirectCount
= UINT32_MAX
,
585 .maxSamplerLodBias
= 16,
586 .maxSamplerAnisotropy
= 16,
587 .maxViewports
= MAX_VIEWPORTS
,
588 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
589 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
590 .viewportSubPixelBits
= 13, /* We take a float? */
591 .minMemoryMapAlignment
= 4096, /* A page */
592 .minTexelBufferOffsetAlignment
= 1,
593 .minUniformBufferOffsetAlignment
= 4,
594 .minStorageBufferOffsetAlignment
= 4,
595 .minTexelOffset
= -32,
596 .maxTexelOffset
= 31,
597 .minTexelGatherOffset
= -32,
598 .maxTexelGatherOffset
= 31,
599 .minInterpolationOffset
= -2,
600 .maxInterpolationOffset
= 2,
601 .subPixelInterpolationOffsetBits
= 8,
602 .maxFramebufferWidth
= (1 << 14),
603 .maxFramebufferHeight
= (1 << 14),
604 .maxFramebufferLayers
= (1 << 10),
605 .framebufferColorSampleCounts
= sample_counts
,
606 .framebufferDepthSampleCounts
= sample_counts
,
607 .framebufferStencilSampleCounts
= sample_counts
,
608 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
609 .maxColorAttachments
= MAX_RTS
,
610 .sampledImageColorSampleCounts
= sample_counts
,
611 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
612 .sampledImageDepthSampleCounts
= sample_counts
,
613 .sampledImageStencilSampleCounts
= sample_counts
,
614 .storageImageSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
615 .maxSampleMaskWords
= 1,
616 .timestampComputeAndGraphics
= true,
617 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
618 .maxClipDistances
= 8,
619 .maxCullDistances
= 8,
620 .maxCombinedClipAndCullDistances
= 8,
621 .discreteQueuePriorities
= 1,
622 .pointSizeRange
= { 0.125, 255.875 },
623 .lineWidthRange
= { 0.0, 7.9921875 },
624 .pointSizeGranularity
= (1.0 / 8.0),
625 .lineWidthGranularity
= (1.0 / 128.0),
626 .strictLines
= false, /* FINISHME */
627 .standardSampleLocations
= true,
628 .optimalBufferCopyOffsetAlignment
= 128,
629 .optimalBufferCopyRowPitchAlignment
= 128,
630 .nonCoherentAtomSize
= 64,
633 *pProperties
= (VkPhysicalDeviceProperties
) {
634 .apiVersion
= radv_physical_device_api_version(pdevice
),
635 .driverVersion
= vk_get_driver_version(),
636 .vendorID
= ATI_VENDOR_ID
,
637 .deviceID
= pdevice
->rad_info
.pci_id
,
638 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
640 .sparseProperties
= {0},
643 strcpy(pProperties
->deviceName
, pdevice
->name
);
644 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
647 void radv_GetPhysicalDeviceProperties2KHR(
648 VkPhysicalDevice physicalDevice
,
649 VkPhysicalDeviceProperties2KHR
*pProperties
)
651 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
652 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
654 vk_foreach_struct(ext
, pProperties
->pNext
) {
655 switch (ext
->sType
) {
656 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
657 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
658 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
659 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
662 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR
: {
663 VkPhysicalDeviceIDPropertiesKHR
*properties
= (VkPhysicalDeviceIDPropertiesKHR
*)ext
;
664 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
665 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
666 properties
->deviceLUIDValid
= false;
669 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX
: {
670 VkPhysicalDeviceMultiviewPropertiesKHX
*properties
= (VkPhysicalDeviceMultiviewPropertiesKHX
*)ext
;
671 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
672 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
675 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR
: {
676 VkPhysicalDevicePointClippingPropertiesKHR
*properties
=
677 (VkPhysicalDevicePointClippingPropertiesKHR
*)ext
;
678 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR
;
687 static void radv_get_physical_device_queue_family_properties(
688 struct radv_physical_device
* pdevice
,
690 VkQueueFamilyProperties
** pQueueFamilyProperties
)
692 int num_queue_families
= 1;
694 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
695 pdevice
->rad_info
.chip_class
>= CIK
&&
696 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
697 num_queue_families
++;
699 if (pQueueFamilyProperties
== NULL
) {
700 *pCount
= num_queue_families
;
709 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
710 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
711 VK_QUEUE_COMPUTE_BIT
|
712 VK_QUEUE_TRANSFER_BIT
|
713 VK_QUEUE_SPARSE_BINDING_BIT
,
715 .timestampValidBits
= 64,
716 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
721 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
722 pdevice
->rad_info
.chip_class
>= CIK
&&
723 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
725 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
726 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
727 VK_QUEUE_TRANSFER_BIT
|
728 VK_QUEUE_SPARSE_BINDING_BIT
,
729 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
730 .timestampValidBits
= 64,
731 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
739 void radv_GetPhysicalDeviceQueueFamilyProperties(
740 VkPhysicalDevice physicalDevice
,
742 VkQueueFamilyProperties
* pQueueFamilyProperties
)
744 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
745 if (!pQueueFamilyProperties
) {
746 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
749 VkQueueFamilyProperties
*properties
[] = {
750 pQueueFamilyProperties
+ 0,
751 pQueueFamilyProperties
+ 1,
752 pQueueFamilyProperties
+ 2,
754 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
755 assert(*pCount
<= 3);
758 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
759 VkPhysicalDevice physicalDevice
,
761 VkQueueFamilyProperties2KHR
*pQueueFamilyProperties
)
763 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
764 if (!pQueueFamilyProperties
) {
765 return radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
768 VkQueueFamilyProperties
*properties
[] = {
769 &pQueueFamilyProperties
[0].queueFamilyProperties
,
770 &pQueueFamilyProperties
[1].queueFamilyProperties
,
771 &pQueueFamilyProperties
[2].queueFamilyProperties
,
773 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
774 assert(*pCount
<= 3);
777 void radv_GetPhysicalDeviceMemoryProperties(
778 VkPhysicalDevice physicalDevice
,
779 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
781 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
783 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
785 pMemoryProperties
->memoryTypeCount
= RADV_MEM_TYPE_COUNT
;
786 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM
] = (VkMemoryType
) {
787 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
788 .heapIndex
= RADV_MEM_HEAP_VRAM
,
790 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_WRITE_COMBINE
] = (VkMemoryType
) {
791 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
792 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
793 .heapIndex
= RADV_MEM_HEAP_GTT
,
795 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_VRAM_CPU_ACCESS
] = (VkMemoryType
) {
796 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
797 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
798 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
799 .heapIndex
= RADV_MEM_HEAP_VRAM_CPU_ACCESS
,
801 pMemoryProperties
->memoryTypes
[RADV_MEM_TYPE_GTT_CACHED
] = (VkMemoryType
) {
802 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
803 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
804 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
,
805 .heapIndex
= RADV_MEM_HEAP_GTT
,
808 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
809 uint64_t visible_vram_size
= MIN2(physical_device
->rad_info
.vram_size
,
810 physical_device
->rad_info
.vram_vis_size
);
812 pMemoryProperties
->memoryHeapCount
= RADV_MEM_HEAP_COUNT
;
813 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM
] = (VkMemoryHeap
) {
814 .size
= physical_device
->rad_info
.vram_size
-
816 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
818 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_VRAM_CPU_ACCESS
] = (VkMemoryHeap
) {
819 .size
= visible_vram_size
,
820 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
822 pMemoryProperties
->memoryHeaps
[RADV_MEM_HEAP_GTT
] = (VkMemoryHeap
) {
823 .size
= physical_device
->rad_info
.gart_size
,
828 void radv_GetPhysicalDeviceMemoryProperties2KHR(
829 VkPhysicalDevice physicalDevice
,
830 VkPhysicalDeviceMemoryProperties2KHR
*pMemoryProperties
)
832 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
833 &pMemoryProperties
->memoryProperties
);
836 static enum radeon_ctx_priority
837 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
839 /* Default to MEDIUM when a specific global priority isn't requested */
841 return RADEON_CTX_PRIORITY_MEDIUM
;
843 switch(pObj
->globalPriority
) {
844 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME
:
845 return RADEON_CTX_PRIORITY_REALTIME
;
846 case VK_QUEUE_GLOBAL_PRIORITY_HIGH
:
847 return RADEON_CTX_PRIORITY_HIGH
;
848 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM
:
849 return RADEON_CTX_PRIORITY_MEDIUM
;
850 case VK_QUEUE_GLOBAL_PRIORITY_LOW
:
851 return RADEON_CTX_PRIORITY_LOW
;
853 unreachable("Illegal global priority value");
854 return RADEON_CTX_PRIORITY_INVALID
;
859 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
860 int queue_family_index
, int idx
,
861 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
863 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
864 queue
->device
= device
;
865 queue
->queue_family_index
= queue_family_index
;
866 queue
->queue_idx
= idx
;
867 queue
->priority
= radv_get_queue_global_priority(global_priority
);
869 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
871 return VK_ERROR_OUT_OF_HOST_MEMORY
;
877 radv_queue_finish(struct radv_queue
*queue
)
880 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
882 if (queue
->initial_full_flush_preamble_cs
)
883 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
884 if (queue
->initial_preamble_cs
)
885 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
886 if (queue
->continue_preamble_cs
)
887 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
888 if (queue
->descriptor_bo
)
889 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
890 if (queue
->scratch_bo
)
891 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
892 if (queue
->esgs_ring_bo
)
893 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
894 if (queue
->gsvs_ring_bo
)
895 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
896 if (queue
->tess_factor_ring_bo
)
897 queue
->device
->ws
->buffer_destroy(queue
->tess_factor_ring_bo
);
898 if (queue
->tess_offchip_ring_bo
)
899 queue
->device
->ws
->buffer_destroy(queue
->tess_offchip_ring_bo
);
900 if (queue
->compute_scratch_bo
)
901 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
905 radv_device_init_gs_info(struct radv_device
*device
)
907 switch (device
->physical_device
->rad_info
.family
) {
916 device
->gs_table_depth
= 16;
930 device
->gs_table_depth
= 32;
933 unreachable("unknown GPU");
937 VkResult
radv_CreateDevice(
938 VkPhysicalDevice physicalDevice
,
939 const VkDeviceCreateInfo
* pCreateInfo
,
940 const VkAllocationCallbacks
* pAllocator
,
943 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
945 struct radv_device
*device
;
947 bool keep_shader_info
= false;
949 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
950 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
951 if (!radv_physical_device_extension_supported(physical_device
, ext_name
))
952 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT
);
954 if (strcmp(ext_name
, VK_AMD_SHADER_INFO_EXTENSION_NAME
) == 0)
955 keep_shader_info
= true;
958 /* Check enabled features */
959 if (pCreateInfo
->pEnabledFeatures
) {
960 VkPhysicalDeviceFeatures supported_features
;
961 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
962 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
963 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
964 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
965 for (uint32_t i
= 0; i
< num_features
; i
++) {
966 if (enabled_feature
[i
] && !supported_feature
[i
])
967 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT
);
971 device
= vk_alloc2(&physical_device
->instance
->alloc
, pAllocator
,
973 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
975 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
977 memset(device
, 0, sizeof(*device
));
979 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
980 device
->instance
= physical_device
->instance
;
981 device
->physical_device
= physical_device
;
983 device
->ws
= physical_device
->ws
;
985 device
->alloc
= *pAllocator
;
987 device
->alloc
= physical_device
->instance
->alloc
;
989 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
990 list_inithead(&device
->shader_slabs
);
992 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
993 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
994 uint32_t qfi
= queue_create
->queueFamilyIndex
;
995 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
996 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
998 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
1000 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
1001 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
1002 if (!device
->queues
[qfi
]) {
1003 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1007 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
1009 device
->queue_count
[qfi
] = queue_create
->queueCount
;
1011 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
1012 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
], qfi
, q
, global_priority
);
1013 if (result
!= VK_SUCCESS
)
1018 #if HAVE_LLVM < 0x0400
1019 device
->llvm_supports_spill
= false;
1021 device
->llvm_supports_spill
= true;
1024 /* The maximum number of scratch waves. Scratch space isn't divided
1025 * evenly between CUs. The number is only a function of the number of CUs.
1026 * We can decrease the constant to decrease the scratch buffer size.
1028 * sctx->scratch_waves must be >= the maximum posible size of
1029 * 1 threadgroup, so that the hw doesn't hang from being unable
1032 * The recommended value is 4 per CU at most. Higher numbers don't
1033 * bring much benefit, but they still occupy chip resources (think
1034 * async compute). I've seen ~2% performance difference between 4 and 32.
1036 uint32_t max_threads_per_block
= 2048;
1037 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
1038 max_threads_per_block
/ 64);
1040 radv_device_init_gs_info(device
);
1042 device
->tess_offchip_block_dw_size
=
1043 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
1044 device
->has_distributed_tess
=
1045 device
->physical_device
->rad_info
.chip_class
>= VI
&&
1046 device
->physical_device
->rad_info
.max_se
>= 2;
1048 if (getenv("RADV_TRACE_FILE")) {
1049 keep_shader_info
= true;
1051 if (!radv_init_trace(device
))
1055 device
->keep_shader_info
= keep_shader_info
;
1057 result
= radv_device_init_meta(device
);
1058 if (result
!= VK_SUCCESS
)
1061 radv_device_init_msaa(device
);
1063 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
1064 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
1066 case RADV_QUEUE_GENERAL
:
1067 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
1068 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
1069 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1071 case RADV_QUEUE_COMPUTE
:
1072 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
1073 radeon_emit(device
->empty_cs
[family
], 0);
1076 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
1079 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
1080 cik_create_gfx_config(device
);
1082 VkPipelineCacheCreateInfo ci
;
1083 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
1086 ci
.pInitialData
= NULL
;
1087 ci
.initialDataSize
= 0;
1089 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
1091 if (result
!= VK_SUCCESS
)
1094 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
1096 *pDevice
= radv_device_to_handle(device
);
1100 if (device
->trace_bo
)
1101 device
->ws
->buffer_destroy(device
->trace_bo
);
1103 if (device
->gfx_init
)
1104 device
->ws
->buffer_destroy(device
->gfx_init
);
1106 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1107 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1108 radv_queue_finish(&device
->queues
[i
][q
]);
1109 if (device
->queue_count
[i
])
1110 vk_free(&device
->alloc
, device
->queues
[i
]);
1113 vk_free(&device
->alloc
, device
);
1117 void radv_DestroyDevice(
1119 const VkAllocationCallbacks
* pAllocator
)
1121 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1126 if (device
->trace_bo
)
1127 device
->ws
->buffer_destroy(device
->trace_bo
);
1129 if (device
->gfx_init
)
1130 device
->ws
->buffer_destroy(device
->gfx_init
);
1132 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
1133 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
1134 radv_queue_finish(&device
->queues
[i
][q
]);
1135 if (device
->queue_count
[i
])
1136 vk_free(&device
->alloc
, device
->queues
[i
]);
1137 if (device
->empty_cs
[i
])
1138 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
1140 radv_device_finish_meta(device
);
1142 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
1143 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
1145 radv_destroy_shader_slabs(device
);
1147 vk_free(&device
->alloc
, device
);
1150 VkResult
radv_EnumerateInstanceLayerProperties(
1151 uint32_t* pPropertyCount
,
1152 VkLayerProperties
* pProperties
)
1154 if (pProperties
== NULL
) {
1155 *pPropertyCount
= 0;
1159 /* None supported at this time */
1160 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1163 VkResult
radv_EnumerateDeviceLayerProperties(
1164 VkPhysicalDevice physicalDevice
,
1165 uint32_t* pPropertyCount
,
1166 VkLayerProperties
* pProperties
)
1168 if (pProperties
== NULL
) {
1169 *pPropertyCount
= 0;
1173 /* None supported at this time */
1174 return vk_error(VK_ERROR_LAYER_NOT_PRESENT
);
1177 void radv_GetDeviceQueue(
1179 uint32_t queueFamilyIndex
,
1180 uint32_t queueIndex
,
1183 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1185 *pQueue
= radv_queue_to_handle(&device
->queues
[queueFamilyIndex
][queueIndex
]);
1189 fill_geom_tess_rings(struct radv_queue
*queue
,
1191 bool add_sample_positions
,
1192 uint32_t esgs_ring_size
,
1193 struct radeon_winsys_bo
*esgs_ring_bo
,
1194 uint32_t gsvs_ring_size
,
1195 struct radeon_winsys_bo
*gsvs_ring_bo
,
1196 uint32_t tess_factor_ring_size
,
1197 struct radeon_winsys_bo
*tess_factor_ring_bo
,
1198 uint32_t tess_offchip_ring_size
,
1199 struct radeon_winsys_bo
*tess_offchip_ring_bo
)
1201 uint64_t esgs_va
= 0, gsvs_va
= 0;
1202 uint64_t tess_factor_va
= 0, tess_offchip_va
= 0;
1203 uint32_t *desc
= &map
[4];
1206 esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
1208 gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
1209 if (tess_factor_ring_bo
)
1210 tess_factor_va
= radv_buffer_get_va(tess_factor_ring_bo
);
1211 if (tess_offchip_ring_bo
)
1212 tess_offchip_va
= radv_buffer_get_va(tess_offchip_ring_bo
);
1214 /* stride 0, num records - size, add tid, swizzle, elsize4,
1217 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
1218 S_008F04_STRIDE(0) |
1219 S_008F04_SWIZZLE_ENABLE(true);
1220 desc
[2] = esgs_ring_size
;
1221 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1222 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1223 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1224 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1225 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1226 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1227 S_008F0C_ELEMENT_SIZE(1) |
1228 S_008F0C_INDEX_STRIDE(3) |
1229 S_008F0C_ADD_TID_ENABLE(true);
1232 /* GS entry for ES->GS ring */
1233 /* stride 0, num records - size, elsize0,
1236 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32)|
1237 S_008F04_STRIDE(0) |
1238 S_008F04_SWIZZLE_ENABLE(false);
1239 desc
[2] = esgs_ring_size
;
1240 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1241 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1242 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1243 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1244 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1245 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1246 S_008F0C_ELEMENT_SIZE(0) |
1247 S_008F0C_INDEX_STRIDE(0) |
1248 S_008F0C_ADD_TID_ENABLE(false);
1251 /* VS entry for GS->VS ring */
1252 /* stride 0, num records - size, elsize0,
1255 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1256 S_008F04_STRIDE(0) |
1257 S_008F04_SWIZZLE_ENABLE(false);
1258 desc
[2] = gsvs_ring_size
;
1259 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1260 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1261 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1262 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1263 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1264 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1265 S_008F0C_ELEMENT_SIZE(0) |
1266 S_008F0C_INDEX_STRIDE(0) |
1267 S_008F0C_ADD_TID_ENABLE(false);
1270 /* stride gsvs_itemsize, num records 64
1271 elsize 4, index stride 16 */
1272 /* shader will patch stride and desc[2] */
1274 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32)|
1275 S_008F04_STRIDE(0) |
1276 S_008F04_SWIZZLE_ENABLE(true);
1278 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1279 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1280 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1281 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1282 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1283 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1284 S_008F0C_ELEMENT_SIZE(1) |
1285 S_008F0C_INDEX_STRIDE(1) |
1286 S_008F0C_ADD_TID_ENABLE(true);
1289 desc
[0] = tess_factor_va
;
1290 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va
>> 32) |
1291 S_008F04_STRIDE(0) |
1292 S_008F04_SWIZZLE_ENABLE(false);
1293 desc
[2] = tess_factor_ring_size
;
1294 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1295 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1296 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1297 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1298 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1299 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1300 S_008F0C_ELEMENT_SIZE(0) |
1301 S_008F0C_INDEX_STRIDE(0) |
1302 S_008F0C_ADD_TID_ENABLE(false);
1305 desc
[0] = tess_offchip_va
;
1306 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32) |
1307 S_008F04_STRIDE(0) |
1308 S_008F04_SWIZZLE_ENABLE(false);
1309 desc
[2] = tess_offchip_ring_size
;
1310 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1311 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1312 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1313 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
1314 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1315 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
1316 S_008F0C_ELEMENT_SIZE(0) |
1317 S_008F0C_INDEX_STRIDE(0) |
1318 S_008F0C_ADD_TID_ENABLE(false);
1321 /* add sample positions after all rings */
1322 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
1324 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
1326 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
1328 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
1330 memcpy(desc
, queue
->device
->sample_locations_16x
, 128);
1334 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
1336 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= CIK
&&
1337 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
1338 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
1339 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
1340 unsigned max_offchip_buffers
= max_offchip_buffers_per_se
*
1341 device
->physical_device
->rad_info
.max_se
;
1342 unsigned offchip_granularity
;
1343 unsigned hs_offchip_param
;
1344 switch (device
->tess_offchip_block_dw_size
) {
1349 offchip_granularity
= V_03093C_X_8K_DWORDS
;
1352 offchip_granularity
= V_03093C_X_4K_DWORDS
;
1356 switch (device
->physical_device
->rad_info
.chip_class
) {
1358 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
1364 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
1368 *max_offchip_buffers_p
= max_offchip_buffers
;
1369 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1370 if (device
->physical_device
->rad_info
.chip_class
>= VI
)
1371 --max_offchip_buffers
;
1373 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
1374 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
1377 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
1379 return hs_offchip_param
;
1383 radv_get_preamble_cs(struct radv_queue
*queue
,
1384 uint32_t scratch_size
,
1385 uint32_t compute_scratch_size
,
1386 uint32_t esgs_ring_size
,
1387 uint32_t gsvs_ring_size
,
1388 bool needs_tess_rings
,
1389 bool needs_sample_positions
,
1390 struct radeon_winsys_cs
**initial_full_flush_preamble_cs
,
1391 struct radeon_winsys_cs
**initial_preamble_cs
,
1392 struct radeon_winsys_cs
**continue_preamble_cs
)
1394 struct radeon_winsys_bo
*scratch_bo
= NULL
;
1395 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
1396 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
1397 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
1398 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
1399 struct radeon_winsys_bo
*tess_factor_ring_bo
= NULL
;
1400 struct radeon_winsys_bo
*tess_offchip_ring_bo
= NULL
;
1401 struct radeon_winsys_cs
*dest_cs
[3] = {0};
1402 bool add_tess_rings
= false, add_sample_positions
= false;
1403 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
1404 unsigned max_offchip_buffers
;
1405 unsigned hs_offchip_param
= 0;
1406 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
1407 if (!queue
->has_tess_rings
) {
1408 if (needs_tess_rings
)
1409 add_tess_rings
= true;
1411 if (!queue
->has_sample_positions
) {
1412 if (needs_sample_positions
)
1413 add_sample_positions
= true;
1415 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
1416 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
1417 &max_offchip_buffers
);
1418 tess_offchip_ring_size
= max_offchip_buffers
*
1419 queue
->device
->tess_offchip_block_dw_size
* 4;
1421 if (scratch_size
<= queue
->scratch_size
&&
1422 compute_scratch_size
<= queue
->compute_scratch_size
&&
1423 esgs_ring_size
<= queue
->esgs_ring_size
&&
1424 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
1425 !add_tess_rings
&& !add_sample_positions
&&
1426 queue
->initial_preamble_cs
) {
1427 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
1428 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1429 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1430 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1431 *continue_preamble_cs
= NULL
;
1435 if (scratch_size
> queue
->scratch_size
) {
1436 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1444 scratch_bo
= queue
->scratch_bo
;
1446 if (compute_scratch_size
> queue
->compute_scratch_size
) {
1447 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1448 compute_scratch_size
,
1452 if (!compute_scratch_bo
)
1456 compute_scratch_bo
= queue
->compute_scratch_bo
;
1458 if (esgs_ring_size
> queue
->esgs_ring_size
) {
1459 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1467 esgs_ring_bo
= queue
->esgs_ring_bo
;
1468 esgs_ring_size
= queue
->esgs_ring_size
;
1471 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
1472 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1480 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
1481 gsvs_ring_size
= queue
->gsvs_ring_size
;
1484 if (add_tess_rings
) {
1485 tess_factor_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1486 tess_factor_ring_size
,
1490 if (!tess_factor_ring_bo
)
1492 tess_offchip_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1493 tess_offchip_ring_size
,
1497 if (!tess_offchip_ring_bo
)
1500 tess_factor_ring_bo
= queue
->tess_factor_ring_bo
;
1501 tess_offchip_ring_bo
= queue
->tess_offchip_ring_bo
;
1504 if (scratch_bo
!= queue
->scratch_bo
||
1505 esgs_ring_bo
!= queue
->esgs_ring_bo
||
1506 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
1507 tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
||
1508 tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
|| add_sample_positions
) {
1510 if (gsvs_ring_bo
|| esgs_ring_bo
||
1511 tess_factor_ring_bo
|| tess_offchip_ring_bo
|| add_sample_positions
) {
1512 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
1513 if (add_sample_positions
)
1514 size
+= 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1516 else if (scratch_bo
)
1517 size
= 8; /* 2 dword */
1519 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
1523 RADEON_FLAG_CPU_ACCESS
|RADEON_FLAG_NO_INTERPROCESS_SHARING
);
1527 descriptor_bo
= queue
->descriptor_bo
;
1529 for(int i
= 0; i
< 3; ++i
) {
1530 struct radeon_winsys_cs
*cs
= NULL
;
1531 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
1532 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
1539 queue
->device
->ws
->cs_add_buffer(cs
, scratch_bo
, 8);
1542 queue
->device
->ws
->cs_add_buffer(cs
, esgs_ring_bo
, 8);
1545 queue
->device
->ws
->cs_add_buffer(cs
, gsvs_ring_bo
, 8);
1547 if (tess_factor_ring_bo
)
1548 queue
->device
->ws
->cs_add_buffer(cs
, tess_factor_ring_bo
, 8);
1550 if (tess_offchip_ring_bo
)
1551 queue
->device
->ws
->cs_add_buffer(cs
, tess_offchip_ring_bo
, 8);
1554 queue
->device
->ws
->cs_add_buffer(cs
, descriptor_bo
, 8);
1556 if (descriptor_bo
!= queue
->descriptor_bo
) {
1557 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
1560 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
1561 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1562 S_008F04_SWIZZLE_ENABLE(1);
1563 map
[0] = scratch_va
;
1567 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
||
1568 add_sample_positions
)
1569 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
1570 esgs_ring_size
, esgs_ring_bo
,
1571 gsvs_ring_size
, gsvs_ring_bo
,
1572 tess_factor_ring_size
, tess_factor_ring_bo
,
1573 tess_offchip_ring_size
, tess_offchip_ring_bo
);
1575 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
1578 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_factor_ring_bo
|| tess_offchip_ring_bo
) {
1579 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1580 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
1581 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
1582 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
1585 if (esgs_ring_bo
|| gsvs_ring_bo
) {
1586 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1587 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
1588 radeon_emit(cs
, esgs_ring_size
>> 8);
1589 radeon_emit(cs
, gsvs_ring_size
>> 8);
1591 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
1592 radeon_emit(cs
, esgs_ring_size
>> 8);
1593 radeon_emit(cs
, gsvs_ring_size
>> 8);
1597 if (tess_factor_ring_bo
) {
1598 uint64_t tf_va
= radv_buffer_get_va(tess_factor_ring_bo
);
1599 if (queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
) {
1600 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
1601 S_030938_SIZE(tess_factor_ring_size
/ 4));
1602 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
1604 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1605 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
1608 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
, hs_offchip_param
);
1610 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
1611 S_008988_SIZE(tess_factor_ring_size
/ 4));
1612 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
1614 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
1619 if (descriptor_bo
) {
1620 uint64_t va
= radv_buffer_get_va(descriptor_bo
);
1621 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1622 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1623 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1624 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
1625 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
1627 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1628 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1629 radeon_emit(cs
, va
);
1630 radeon_emit(cs
, va
>> 32);
1633 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
1634 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
1635 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
1636 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
1637 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
1638 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
1640 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
1641 radeon_set_sh_reg_seq(cs
, regs
[i
], 2);
1642 radeon_emit(cs
, va
);
1643 radeon_emit(cs
, va
>> 32);
1648 if (compute_scratch_bo
) {
1649 uint64_t scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
1650 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
1651 S_008F04_SWIZZLE_ENABLE(1);
1653 queue
->device
->ws
->cs_add_buffer(cs
, compute_scratch_bo
, 8);
1655 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
1656 radeon_emit(cs
, scratch_va
);
1657 radeon_emit(cs
, rsrc1
);
1661 si_cs_emit_cache_flush(cs
,
1663 queue
->device
->physical_device
->rad_info
.chip_class
,
1665 queue
->queue_family_index
== RING_COMPUTE
&&
1666 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1667 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
1668 RADV_CMD_FLAG_INV_ICACHE
|
1669 RADV_CMD_FLAG_INV_SMEM_L1
|
1670 RADV_CMD_FLAG_INV_VMEM_L1
|
1671 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1672 } else if (i
== 1) {
1673 si_cs_emit_cache_flush(cs
,
1675 queue
->device
->physical_device
->rad_info
.chip_class
,
1677 queue
->queue_family_index
== RING_COMPUTE
&&
1678 queue
->device
->physical_device
->rad_info
.chip_class
>= CIK
,
1679 RADV_CMD_FLAG_INV_ICACHE
|
1680 RADV_CMD_FLAG_INV_SMEM_L1
|
1681 RADV_CMD_FLAG_INV_VMEM_L1
|
1682 RADV_CMD_FLAG_INV_GLOBAL_L2
);
1685 if (!queue
->device
->ws
->cs_finalize(cs
))
1689 if (queue
->initial_full_flush_preamble_cs
)
1690 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1692 if (queue
->initial_preamble_cs
)
1693 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1695 if (queue
->continue_preamble_cs
)
1696 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1698 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
1699 queue
->initial_preamble_cs
= dest_cs
[1];
1700 queue
->continue_preamble_cs
= dest_cs
[2];
1702 if (scratch_bo
!= queue
->scratch_bo
) {
1703 if (queue
->scratch_bo
)
1704 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1705 queue
->scratch_bo
= scratch_bo
;
1706 queue
->scratch_size
= scratch_size
;
1709 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
1710 if (queue
->compute_scratch_bo
)
1711 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1712 queue
->compute_scratch_bo
= compute_scratch_bo
;
1713 queue
->compute_scratch_size
= compute_scratch_size
;
1716 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
1717 if (queue
->esgs_ring_bo
)
1718 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1719 queue
->esgs_ring_bo
= esgs_ring_bo
;
1720 queue
->esgs_ring_size
= esgs_ring_size
;
1723 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
1724 if (queue
->gsvs_ring_bo
)
1725 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1726 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
1727 queue
->gsvs_ring_size
= gsvs_ring_size
;
1730 if (tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
) {
1731 queue
->tess_factor_ring_bo
= tess_factor_ring_bo
;
1734 if (tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
) {
1735 queue
->tess_offchip_ring_bo
= tess_offchip_ring_bo
;
1736 queue
->has_tess_rings
= true;
1739 if (descriptor_bo
!= queue
->descriptor_bo
) {
1740 if (queue
->descriptor_bo
)
1741 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1743 queue
->descriptor_bo
= descriptor_bo
;
1746 if (add_sample_positions
)
1747 queue
->has_sample_positions
= true;
1749 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
1750 *initial_preamble_cs
= queue
->initial_preamble_cs
;
1751 *continue_preamble_cs
= queue
->continue_preamble_cs
;
1752 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
1753 *continue_preamble_cs
= NULL
;
1756 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
1758 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
1759 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
1760 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
1761 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
1762 queue
->device
->ws
->buffer_destroy(scratch_bo
);
1763 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
1764 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
1765 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
1766 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
1767 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
1768 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
1769 if (tess_factor_ring_bo
&& tess_factor_ring_bo
!= queue
->tess_factor_ring_bo
)
1770 queue
->device
->ws
->buffer_destroy(tess_factor_ring_bo
);
1771 if (tess_offchip_ring_bo
&& tess_offchip_ring_bo
!= queue
->tess_offchip_ring_bo
)
1772 queue
->device
->ws
->buffer_destroy(tess_offchip_ring_bo
);
1773 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
1776 static VkResult
radv_alloc_sem_counts(struct radv_winsys_sem_counts
*counts
,
1778 const VkSemaphore
*sems
,
1781 int syncobj_idx
= 0, sem_idx
= 0;
1785 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1786 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1788 if (sem
->temp_syncobj
|| sem
->syncobj
)
1789 counts
->syncobj_count
++;
1791 counts
->sem_count
++;
1794 if (counts
->syncobj_count
) {
1795 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
1796 if (!counts
->syncobj
)
1797 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1800 if (counts
->sem_count
) {
1801 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
1803 free(counts
->syncobj
);
1804 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1808 for (uint32_t i
= 0; i
< num_sems
; i
++) {
1809 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
1811 if (sem
->temp_syncobj
) {
1812 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
1814 /* after we wait on a temp import - drop it */
1815 sem
->temp_syncobj
= 0;
1818 else if (sem
->syncobj
)
1819 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
1822 counts
->sem
[sem_idx
++] = sem
->sem
;
1829 void radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
1831 free(sem_info
->wait
.syncobj
);
1832 free(sem_info
->wait
.sem
);
1833 free(sem_info
->signal
.syncobj
);
1834 free(sem_info
->signal
.sem
);
1837 VkResult
radv_alloc_sem_info(struct radv_winsys_sem_info
*sem_info
,
1839 const VkSemaphore
*wait_sems
,
1840 int num_signal_sems
,
1841 const VkSemaphore
*signal_sems
)
1844 memset(sem_info
, 0, sizeof(*sem_info
));
1846 ret
= radv_alloc_sem_counts(&sem_info
->wait
, num_wait_sems
, wait_sems
, true);
1849 ret
= radv_alloc_sem_counts(&sem_info
->signal
, num_signal_sems
, signal_sems
, false);
1851 radv_free_sem_info(sem_info
);
1853 /* caller can override these */
1854 sem_info
->cs_emit_wait
= true;
1855 sem_info
->cs_emit_signal
= true;
1859 VkResult
radv_QueueSubmit(
1861 uint32_t submitCount
,
1862 const VkSubmitInfo
* pSubmits
,
1865 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1866 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
1867 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
1868 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
1870 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : UINT32_MAX
;
1871 uint32_t scratch_size
= 0;
1872 uint32_t compute_scratch_size
= 0;
1873 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
1874 struct radeon_winsys_cs
*initial_preamble_cs
= NULL
, *initial_flush_preamble_cs
= NULL
, *continue_preamble_cs
= NULL
;
1876 bool fence_emitted
= false;
1877 bool tess_rings_needed
= false;
1878 bool sample_positions_needed
= false;
1880 /* Do this first so failing to allocate scratch buffers can't result in
1881 * partially executed submissions. */
1882 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1883 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1884 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1885 pSubmits
[i
].pCommandBuffers
[j
]);
1887 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
1888 compute_scratch_size
= MAX2(compute_scratch_size
,
1889 cmd_buffer
->compute_scratch_size_needed
);
1890 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
1891 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
1892 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
1893 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
1897 result
= radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
1898 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
1899 sample_positions_needed
, &initial_flush_preamble_cs
,
1900 &initial_preamble_cs
, &continue_preamble_cs
);
1901 if (result
!= VK_SUCCESS
)
1904 for (uint32_t i
= 0; i
< submitCount
; i
++) {
1905 struct radeon_winsys_cs
**cs_array
;
1906 bool do_flush
= !i
|| pSubmits
[i
].pWaitDstStageMask
;
1907 bool can_patch
= true;
1909 struct radv_winsys_sem_info sem_info
;
1911 result
= radv_alloc_sem_info(&sem_info
,
1912 pSubmits
[i
].waitSemaphoreCount
,
1913 pSubmits
[i
].pWaitSemaphores
,
1914 pSubmits
[i
].signalSemaphoreCount
,
1915 pSubmits
[i
].pSignalSemaphores
);
1916 if (result
!= VK_SUCCESS
)
1919 if (!pSubmits
[i
].commandBufferCount
) {
1920 if (pSubmits
[i
].waitSemaphoreCount
|| pSubmits
[i
].signalSemaphoreCount
) {
1921 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1922 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1927 radv_loge("failed to submit CS %d\n", i
);
1930 fence_emitted
= true;
1932 radv_free_sem_info(&sem_info
);
1936 cs_array
= malloc(sizeof(struct radeon_winsys_cs
*) *
1937 (pSubmits
[i
].commandBufferCount
));
1939 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
++) {
1940 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
1941 pSubmits
[i
].pCommandBuffers
[j
]);
1942 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
1944 cs_array
[j
] = cmd_buffer
->cs
;
1945 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
1949 for (uint32_t j
= 0; j
< pSubmits
[i
].commandBufferCount
; j
+= advance
) {
1950 struct radeon_winsys_cs
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
1951 advance
= MIN2(max_cs_submission
,
1952 pSubmits
[i
].commandBufferCount
- j
);
1954 if (queue
->device
->trace_bo
)
1955 *queue
->device
->trace_id_ptr
= 0;
1957 sem_info
.cs_emit_wait
= j
== 0;
1958 sem_info
.cs_emit_signal
= j
+ advance
== pSubmits
[i
].commandBufferCount
;
1960 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
1961 advance
, initial_preamble
, continue_preamble_cs
,
1963 can_patch
, base_fence
);
1966 radv_loge("failed to submit CS %d\n", i
);
1969 fence_emitted
= true;
1970 if (queue
->device
->trace_bo
) {
1971 radv_check_gpu_hangs(queue
, cs_array
[j
]);
1975 radv_free_sem_info(&sem_info
);
1980 if (!fence_emitted
) {
1981 struct radv_winsys_sem_info sem_info
= {0};
1982 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
1983 &queue
->device
->empty_cs
[queue
->queue_family_index
],
1984 1, NULL
, NULL
, &sem_info
,
1987 fence
->submitted
= true;
1993 VkResult
radv_QueueWaitIdle(
1996 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
1998 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
1999 radv_queue_family_to_ring(queue
->queue_family_index
),
2004 VkResult
radv_DeviceWaitIdle(
2007 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2009 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2010 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
2011 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
2017 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
2018 VkInstance instance
,
2021 return radv_lookup_entrypoint(pName
);
2024 /* The loader wants us to expose a second GetInstanceProcAddr function
2025 * to work around certain LD_PRELOAD issues seen in apps.
2028 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2029 VkInstance instance
,
2033 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
2034 VkInstance instance
,
2037 return radv_GetInstanceProcAddr(instance
, pName
);
2040 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
2044 return radv_lookup_entrypoint(pName
);
2047 bool radv_get_memory_fd(struct radv_device
*device
,
2048 struct radv_device_memory
*memory
,
2051 struct radeon_bo_metadata metadata
;
2053 if (memory
->image
) {
2054 radv_init_metadata(device
, memory
->image
, &metadata
);
2055 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
2058 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
2062 VkResult
radv_alloc_memory(VkDevice _device
,
2063 const VkMemoryAllocateInfo
* pAllocateInfo
,
2064 const VkAllocationCallbacks
* pAllocator
,
2065 enum radv_mem_flags_bits mem_flags
,
2066 VkDeviceMemory
* pMem
)
2068 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2069 struct radv_device_memory
*mem
;
2071 enum radeon_bo_domain domain
;
2074 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
2076 if (pAllocateInfo
->allocationSize
== 0) {
2077 /* Apparently, this is allowed */
2078 *pMem
= VK_NULL_HANDLE
;
2082 const VkImportMemoryFdInfoKHR
*import_info
=
2083 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
2084 const VkMemoryDedicatedAllocateInfoKHR
*dedicate_info
=
2085 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO_KHR
);
2087 mem
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
2088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2090 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2092 if (dedicate_info
) {
2093 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
2094 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
2101 assert(import_info
->handleType
==
2102 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2103 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
2106 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
2109 close(import_info
->fd
);
2114 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
2115 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
2116 pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_CACHED
)
2117 domain
= RADEON_DOMAIN_GTT
;
2119 domain
= RADEON_DOMAIN_VRAM
;
2121 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_VRAM
)
2122 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
2124 flags
|= RADEON_FLAG_CPU_ACCESS
;
2126 if (pAllocateInfo
->memoryTypeIndex
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
2127 flags
|= RADEON_FLAG_GTT_WC
;
2129 if (mem_flags
& RADV_MEM_IMPLICIT_SYNC
)
2130 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
2132 if (!dedicate_info
&& !import_info
)
2133 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
2135 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
2139 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2142 mem
->type_index
= pAllocateInfo
->memoryTypeIndex
;
2144 *pMem
= radv_device_memory_to_handle(mem
);
2149 vk_free2(&device
->alloc
, pAllocator
, mem
);
2154 VkResult
radv_AllocateMemory(
2156 const VkMemoryAllocateInfo
* pAllocateInfo
,
2157 const VkAllocationCallbacks
* pAllocator
,
2158 VkDeviceMemory
* pMem
)
2160 return radv_alloc_memory(_device
, pAllocateInfo
, pAllocator
, 0, pMem
);
2163 void radv_FreeMemory(
2165 VkDeviceMemory _mem
,
2166 const VkAllocationCallbacks
* pAllocator
)
2168 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2169 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
2174 device
->ws
->buffer_destroy(mem
->bo
);
2177 vk_free2(&device
->alloc
, pAllocator
, mem
);
2180 VkResult
radv_MapMemory(
2182 VkDeviceMemory _memory
,
2183 VkDeviceSize offset
,
2185 VkMemoryMapFlags flags
,
2188 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2189 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2196 *ppData
= device
->ws
->buffer_map(mem
->bo
);
2202 return VK_ERROR_MEMORY_MAP_FAILED
;
2205 void radv_UnmapMemory(
2207 VkDeviceMemory _memory
)
2209 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2210 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
2215 device
->ws
->buffer_unmap(mem
->bo
);
2218 VkResult
radv_FlushMappedMemoryRanges(
2220 uint32_t memoryRangeCount
,
2221 const VkMappedMemoryRange
* pMemoryRanges
)
2226 VkResult
radv_InvalidateMappedMemoryRanges(
2228 uint32_t memoryRangeCount
,
2229 const VkMappedMemoryRange
* pMemoryRanges
)
2234 void radv_GetBufferMemoryRequirements(
2237 VkMemoryRequirements
* pMemoryRequirements
)
2239 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2241 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2243 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2244 pMemoryRequirements
->alignment
= 4096;
2246 pMemoryRequirements
->alignment
= 16;
2248 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
2251 void radv_GetBufferMemoryRequirements2KHR(
2253 const VkBufferMemoryRequirementsInfo2KHR
* pInfo
,
2254 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2256 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
2257 &pMemoryRequirements
->memoryRequirements
);
2258 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
2259 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2260 switch (ext
->sType
) {
2261 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2262 VkMemoryDedicatedRequirementsKHR
*req
=
2263 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2264 req
->requiresDedicatedAllocation
= buffer
->shareable
;
2265 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2274 void radv_GetImageMemoryRequirements(
2277 VkMemoryRequirements
* pMemoryRequirements
)
2279 RADV_FROM_HANDLE(radv_image
, image
, _image
);
2281 pMemoryRequirements
->memoryTypeBits
= (1u << RADV_MEM_TYPE_COUNT
) - 1;
2283 pMemoryRequirements
->size
= image
->size
;
2284 pMemoryRequirements
->alignment
= image
->alignment
;
2287 void radv_GetImageMemoryRequirements2KHR(
2289 const VkImageMemoryRequirementsInfo2KHR
* pInfo
,
2290 VkMemoryRequirements2KHR
* pMemoryRequirements
)
2292 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
2293 &pMemoryRequirements
->memoryRequirements
);
2295 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
2297 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
2298 switch (ext
->sType
) {
2299 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR
: {
2300 VkMemoryDedicatedRequirementsKHR
*req
=
2301 (VkMemoryDedicatedRequirementsKHR
*) ext
;
2302 req
->requiresDedicatedAllocation
= image
->shareable
;
2303 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
2312 void radv_GetImageSparseMemoryRequirements(
2315 uint32_t* pSparseMemoryRequirementCount
,
2316 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
2321 void radv_GetImageSparseMemoryRequirements2KHR(
2323 const VkImageSparseMemoryRequirementsInfo2KHR
* pInfo
,
2324 uint32_t* pSparseMemoryRequirementCount
,
2325 VkSparseImageMemoryRequirements2KHR
* pSparseMemoryRequirements
)
2330 void radv_GetDeviceMemoryCommitment(
2332 VkDeviceMemory memory
,
2333 VkDeviceSize
* pCommittedMemoryInBytes
)
2335 *pCommittedMemoryInBytes
= 0;
2338 VkResult
radv_BindBufferMemory2KHR(VkDevice device
,
2339 uint32_t bindInfoCount
,
2340 const VkBindBufferMemoryInfoKHR
*pBindInfos
)
2342 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2343 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
2344 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
2347 buffer
->bo
= mem
->bo
;
2348 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
2356 VkResult
radv_BindBufferMemory(
2359 VkDeviceMemory memory
,
2360 VkDeviceSize memoryOffset
)
2362 const VkBindBufferMemoryInfoKHR info
= {
2363 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
2366 .memoryOffset
= memoryOffset
2369 return radv_BindBufferMemory2KHR(device
, 1, &info
);
2372 VkResult
radv_BindImageMemory2KHR(VkDevice device
,
2373 uint32_t bindInfoCount
,
2374 const VkBindImageMemoryInfoKHR
*pBindInfos
)
2376 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2377 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
2378 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
2381 image
->bo
= mem
->bo
;
2382 image
->offset
= pBindInfos
[i
].memoryOffset
;
2392 VkResult
radv_BindImageMemory(
2395 VkDeviceMemory memory
,
2396 VkDeviceSize memoryOffset
)
2398 const VkBindImageMemoryInfoKHR info
= {
2399 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR
,
2402 .memoryOffset
= memoryOffset
2405 return radv_BindImageMemory2KHR(device
, 1, &info
);
2410 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
2411 const VkSparseBufferMemoryBindInfo
*bind
)
2413 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
2415 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2416 struct radv_device_memory
*mem
= NULL
;
2418 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2419 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2421 device
->ws
->buffer_virtual_bind(buffer
->bo
,
2422 bind
->pBinds
[i
].resourceOffset
,
2423 bind
->pBinds
[i
].size
,
2424 mem
? mem
->bo
: NULL
,
2425 bind
->pBinds
[i
].memoryOffset
);
2430 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
2431 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
2433 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
2435 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
2436 struct radv_device_memory
*mem
= NULL
;
2438 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
2439 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
2441 device
->ws
->buffer_virtual_bind(image
->bo
,
2442 bind
->pBinds
[i
].resourceOffset
,
2443 bind
->pBinds
[i
].size
,
2444 mem
? mem
->bo
: NULL
,
2445 bind
->pBinds
[i
].memoryOffset
);
2449 VkResult
radv_QueueBindSparse(
2451 uint32_t bindInfoCount
,
2452 const VkBindSparseInfo
* pBindInfo
,
2455 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2456 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
2457 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
2458 bool fence_emitted
= false;
2460 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
2461 struct radv_winsys_sem_info sem_info
;
2462 for (uint32_t j
= 0; j
< pBindInfo
[i
].bufferBindCount
; ++j
) {
2463 radv_sparse_buffer_bind_memory(queue
->device
,
2464 pBindInfo
[i
].pBufferBinds
+ j
);
2467 for (uint32_t j
= 0; j
< pBindInfo
[i
].imageOpaqueBindCount
; ++j
) {
2468 radv_sparse_image_opaque_bind_memory(queue
->device
,
2469 pBindInfo
[i
].pImageOpaqueBinds
+ j
);
2473 result
= radv_alloc_sem_info(&sem_info
,
2474 pBindInfo
[i
].waitSemaphoreCount
,
2475 pBindInfo
[i
].pWaitSemaphores
,
2476 pBindInfo
[i
].signalSemaphoreCount
,
2477 pBindInfo
[i
].pSignalSemaphores
);
2478 if (result
!= VK_SUCCESS
)
2481 if (pBindInfo
[i
].waitSemaphoreCount
|| pBindInfo
[i
].signalSemaphoreCount
) {
2482 queue
->device
->ws
->cs_submit(queue
->hw_ctx
, queue
->queue_idx
,
2483 &queue
->device
->empty_cs
[queue
->queue_family_index
],
2487 fence_emitted
= true;
2489 fence
->submitted
= true;
2492 radv_free_sem_info(&sem_info
);
2496 if (fence
&& !fence_emitted
) {
2497 fence
->signalled
= true;
2503 VkResult
radv_CreateFence(
2505 const VkFenceCreateInfo
* pCreateInfo
,
2506 const VkAllocationCallbacks
* pAllocator
,
2509 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2510 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
2512 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2515 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2517 memset(fence
, 0, sizeof(*fence
));
2518 fence
->submitted
= false;
2519 fence
->signalled
= !!(pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
);
2520 fence
->fence
= device
->ws
->create_fence();
2521 if (!fence
->fence
) {
2522 vk_free2(&device
->alloc
, pAllocator
, fence
);
2523 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2526 *pFence
= radv_fence_to_handle(fence
);
2531 void radv_DestroyFence(
2534 const VkAllocationCallbacks
* pAllocator
)
2536 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2537 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2541 device
->ws
->destroy_fence(fence
->fence
);
2542 vk_free2(&device
->alloc
, pAllocator
, fence
);
2545 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
2547 uint64_t current_time
;
2550 clock_gettime(CLOCK_MONOTONIC
, &tv
);
2551 current_time
= tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
2553 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
2555 return current_time
+ timeout
;
2558 VkResult
radv_WaitForFences(
2560 uint32_t fenceCount
,
2561 const VkFence
* pFences
,
2565 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2566 timeout
= radv_get_absolute_timeout(timeout
);
2568 if (!waitAll
&& fenceCount
> 1) {
2569 fprintf(stderr
, "radv: WaitForFences without waitAll not implemented yet\n");
2572 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
2573 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2574 bool expired
= false;
2576 if (fence
->signalled
)
2579 if (!fence
->submitted
)
2582 expired
= device
->ws
->fence_wait(device
->ws
, fence
->fence
, true, timeout
);
2586 fence
->signalled
= true;
2592 VkResult
radv_ResetFences(VkDevice device
,
2593 uint32_t fenceCount
,
2594 const VkFence
*pFences
)
2596 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
2597 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
2598 fence
->submitted
= fence
->signalled
= false;
2604 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
2606 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2607 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
2609 if (fence
->signalled
)
2611 if (!fence
->submitted
)
2612 return VK_NOT_READY
;
2614 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
2615 return VK_NOT_READY
;
2621 // Queue semaphore functions
2623 VkResult
radv_CreateSemaphore(
2625 const VkSemaphoreCreateInfo
* pCreateInfo
,
2626 const VkAllocationCallbacks
* pAllocator
,
2627 VkSemaphore
* pSemaphore
)
2629 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2630 const VkExportSemaphoreCreateInfoKHR
*export
=
2631 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO_KHR
);
2632 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes
=
2633 export
? export
->handleTypes
: 0;
2635 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
2637 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2639 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2641 sem
->temp_syncobj
= 0;
2642 /* create a syncobject if we are going to export this semaphore */
2644 assert (device
->physical_device
->rad_info
.has_syncobj
);
2645 assert (handleTypes
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
2646 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
2648 vk_free2(&device
->alloc
, pAllocator
, sem
);
2649 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2653 sem
->sem
= device
->ws
->create_sem(device
->ws
);
2655 vk_free2(&device
->alloc
, pAllocator
, sem
);
2656 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2661 *pSemaphore
= radv_semaphore_to_handle(sem
);
2665 void radv_DestroySemaphore(
2667 VkSemaphore _semaphore
,
2668 const VkAllocationCallbacks
* pAllocator
)
2670 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2671 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
2676 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
2678 device
->ws
->destroy_sem(sem
->sem
);
2679 vk_free2(&device
->alloc
, pAllocator
, sem
);
2682 VkResult
radv_CreateEvent(
2684 const VkEventCreateInfo
* pCreateInfo
,
2685 const VkAllocationCallbacks
* pAllocator
,
2688 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2689 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
2691 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2694 return VK_ERROR_OUT_OF_HOST_MEMORY
;
2696 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
2698 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
);
2700 vk_free2(&device
->alloc
, pAllocator
, event
);
2701 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
2704 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
2706 *pEvent
= radv_event_to_handle(event
);
2711 void radv_DestroyEvent(
2714 const VkAllocationCallbacks
* pAllocator
)
2716 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2717 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2721 device
->ws
->buffer_destroy(event
->bo
);
2722 vk_free2(&device
->alloc
, pAllocator
, event
);
2725 VkResult
radv_GetEventStatus(
2729 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2731 if (*event
->map
== 1)
2732 return VK_EVENT_SET
;
2733 return VK_EVENT_RESET
;
2736 VkResult
radv_SetEvent(
2740 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2746 VkResult
radv_ResetEvent(
2750 RADV_FROM_HANDLE(radv_event
, event
, _event
);
2756 VkResult
radv_CreateBuffer(
2758 const VkBufferCreateInfo
* pCreateInfo
,
2759 const VkAllocationCallbacks
* pAllocator
,
2762 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2763 struct radv_buffer
*buffer
;
2765 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
2767 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
2768 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2770 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
2772 buffer
->size
= pCreateInfo
->size
;
2773 buffer
->usage
= pCreateInfo
->usage
;
2776 buffer
->flags
= pCreateInfo
->flags
;
2778 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
2779 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR
) != NULL
;
2781 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
2782 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
2783 align64(buffer
->size
, 4096),
2784 4096, 0, RADEON_FLAG_VIRTUAL
);
2786 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2787 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY
);
2791 *pBuffer
= radv_buffer_to_handle(buffer
);
2796 void radv_DestroyBuffer(
2799 const VkAllocationCallbacks
* pAllocator
)
2801 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2802 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
2807 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
2808 device
->ws
->buffer_destroy(buffer
->bo
);
2810 vk_free2(&device
->alloc
, pAllocator
, buffer
);
2813 static inline unsigned
2814 si_tile_mode_index(const struct radv_image
*image
, unsigned level
, bool stencil
)
2817 return image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
2819 return image
->surface
.u
.legacy
.tiling_index
[level
];
2822 static uint32_t radv_surface_layer_count(struct radv_image_view
*iview
)
2824 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: iview
->layer_count
;
2828 radv_initialise_color_surface(struct radv_device
*device
,
2829 struct radv_color_buffer_info
*cb
,
2830 struct radv_image_view
*iview
)
2832 const struct vk_format_description
*desc
;
2833 unsigned ntype
, format
, swap
, endian
;
2834 unsigned blend_clamp
= 0, blend_bypass
= 0;
2836 const struct radeon_surf
*surf
= &iview
->image
->surface
;
2838 desc
= vk_format_description(iview
->vk_format
);
2840 memset(cb
, 0, sizeof(*cb
));
2842 /* Intensity is implemented as Red, so treat it that way. */
2843 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
2845 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2847 cb
->cb_color_base
= va
>> 8;
2849 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2850 struct gfx9_surf_meta_flags meta
;
2851 if (iview
->image
->dcc_offset
)
2852 meta
= iview
->image
->surface
.u
.gfx9
.dcc
;
2854 meta
= iview
->image
->surface
.u
.gfx9
.cmask
;
2856 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
2857 S_028C74_FMASK_SW_MODE(iview
->image
->surface
.u
.gfx9
.fmask
.swizzle_mode
) |
2858 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
2859 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
2861 cb
->cb_color_base
+= iview
->image
->surface
.u
.gfx9
.surf_offset
>> 8;
2862 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
2864 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
2865 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
2867 cb
->cb_color_base
+= level_info
->offset
>> 8;
2868 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
2869 cb
->cb_color_base
|= iview
->image
->surface
.tile_swizzle
;
2871 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
2872 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
2873 tile_mode_index
= si_tile_mode_index(iview
->image
, iview
->base_mip
, false);
2875 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
2876 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
2877 cb
->cb_color_cmask_slice
= iview
->image
->cmask
.slice_tile_max
;
2879 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
2880 cb
->micro_tile_mode
= iview
->image
->surface
.micro_tile_mode
;
2882 if (iview
->image
->fmask
.size
) {
2883 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2884 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(iview
->image
->fmask
.pitch_in_pixels
/ 8 - 1);
2885 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(iview
->image
->fmask
.tile_mode_index
);
2886 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(iview
->image
->fmask
.slice_tile_max
);
2888 /* This must be set for fast clear to work without FMASK. */
2889 if (device
->physical_device
->rad_info
.chip_class
>= CIK
)
2890 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
2891 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
2892 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
2896 /* CMASK variables */
2897 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2898 va
+= iview
->image
->cmask
.offset
;
2899 cb
->cb_color_cmask
= va
>> 8;
2901 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
2902 va
+= iview
->image
->dcc_offset
;
2903 cb
->cb_dcc_base
= va
>> 8;
2904 cb
->cb_dcc_base
|= iview
->image
->surface
.tile_swizzle
;
2906 uint32_t max_slice
= radv_surface_layer_count(iview
);
2907 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
2908 S_028C6C_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
2910 if (iview
->image
->info
.samples
> 1) {
2911 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
2913 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
2914 S_028C74_NUM_FRAGMENTS(log_samples
);
2917 if (iview
->image
->fmask
.size
) {
2918 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask
.offset
;
2919 cb
->cb_color_fmask
= va
>> 8;
2920 cb
->cb_color_fmask
|= iview
->image
->fmask
.tile_swizzle
;
2922 cb
->cb_color_fmask
= cb
->cb_color_base
;
2925 ntype
= radv_translate_color_numformat(iview
->vk_format
,
2927 vk_format_get_first_non_void_channel(iview
->vk_format
));
2928 format
= radv_translate_colorformat(iview
->vk_format
);
2929 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
2930 radv_finishme("Illegal color\n");
2931 swap
= radv_translate_colorswap(iview
->vk_format
, FALSE
);
2932 endian
= radv_colorformat_endian_swap(format
);
2934 /* blend clamp should be set for all NORM/SRGB types */
2935 if (ntype
== V_028C70_NUMBER_UNORM
||
2936 ntype
== V_028C70_NUMBER_SNORM
||
2937 ntype
== V_028C70_NUMBER_SRGB
)
2940 /* set blend bypass according to docs if SINT/UINT or
2941 8/24 COLOR variants */
2942 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
2943 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
2944 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
2949 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
2950 (format
== V_028C70_COLOR_8
||
2951 format
== V_028C70_COLOR_8_8
||
2952 format
== V_028C70_COLOR_8_8_8_8
))
2953 ->color_is_int8
= true;
2955 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
2956 S_028C70_COMP_SWAP(swap
) |
2957 S_028C70_BLEND_CLAMP(blend_clamp
) |
2958 S_028C70_BLEND_BYPASS(blend_bypass
) |
2959 S_028C70_SIMPLE_FLOAT(1) |
2960 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
2961 ntype
!= V_028C70_NUMBER_SNORM
&&
2962 ntype
!= V_028C70_NUMBER_SRGB
&&
2963 format
!= V_028C70_COLOR_8_24
&&
2964 format
!= V_028C70_COLOR_24_8
) |
2965 S_028C70_NUMBER_TYPE(ntype
) |
2966 S_028C70_ENDIAN(endian
);
2967 if ((iview
->image
->info
.samples
> 1) && iview
->image
->fmask
.size
) {
2968 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
2969 if (device
->physical_device
->rad_info
.chip_class
== SI
) {
2970 unsigned fmask_bankh
= util_logbase2(iview
->image
->fmask
.bank_height
);
2971 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
2975 if (iview
->image
->cmask
.size
&&
2976 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
2977 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
2979 if (radv_vi_dcc_enabled(iview
->image
, iview
->base_mip
))
2980 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
2982 if (device
->physical_device
->rad_info
.chip_class
>= VI
) {
2983 unsigned max_uncompressed_block_size
= 2;
2984 if (iview
->image
->info
.samples
> 1) {
2985 if (iview
->image
->surface
.bpe
== 1)
2986 max_uncompressed_block_size
= 0;
2987 else if (iview
->image
->surface
.bpe
== 2)
2988 max_uncompressed_block_size
= 1;
2991 cb
->cb_dcc_control
= S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
2992 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2995 /* This must be set for fast clear to work without FMASK. */
2996 if (!iview
->image
->fmask
.size
&&
2997 device
->physical_device
->rad_info
.chip_class
== SI
) {
2998 unsigned bankh
= util_logbase2(iview
->image
->surface
.u
.legacy
.bankh
);
2999 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
3002 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3003 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
3004 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
3006 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL(iview
->base_mip
);
3007 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
3008 S_028C74_RESOURCE_TYPE(iview
->image
->surface
.u
.gfx9
.resource_type
);
3009 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(iview
->extent
.width
- 1) |
3010 S_028C68_MIP0_HEIGHT(iview
->extent
.height
- 1) |
3011 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
3013 cb
->gfx9_epitch
= S_0287A0_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3019 radv_initialise_ds_surface(struct radv_device
*device
,
3020 struct radv_ds_buffer_info
*ds
,
3021 struct radv_image_view
*iview
)
3023 unsigned level
= iview
->base_mip
;
3024 unsigned format
, stencil_format
;
3025 uint64_t va
, s_offs
, z_offs
;
3026 bool stencil_only
= false;
3027 memset(ds
, 0, sizeof(*ds
));
3028 switch (iview
->image
->vk_format
) {
3029 case VK_FORMAT_D24_UNORM_S8_UINT
:
3030 case VK_FORMAT_X8_D24_UNORM_PACK32
:
3031 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3032 ds
->offset_scale
= 2.0f
;
3034 case VK_FORMAT_D16_UNORM
:
3035 case VK_FORMAT_D16_UNORM_S8_UINT
:
3036 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3037 ds
->offset_scale
= 4.0f
;
3039 case VK_FORMAT_D32_SFLOAT
:
3040 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
3041 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3042 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3043 ds
->offset_scale
= 1.0f
;
3045 case VK_FORMAT_S8_UINT
:
3046 stencil_only
= true;
3052 format
= radv_translate_dbformat(iview
->image
->vk_format
);
3053 stencil_format
= iview
->image
->surface
.has_stencil
?
3054 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
3056 uint32_t max_slice
= radv_surface_layer_count(iview
);
3057 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
3058 S_028008_SLICE_MAX(iview
->base_layer
+ max_slice
- 1);
3060 ds
->db_htile_data_base
= 0;
3061 ds
->db_htile_surface
= 0;
3063 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
3064 s_offs
= z_offs
= va
;
3066 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3067 assert(iview
->image
->surface
.u
.gfx9
.surf_offset
== 0);
3068 s_offs
+= iview
->image
->surface
.u
.gfx9
.stencil_offset
;
3070 ds
->db_z_info
= S_028038_FORMAT(format
) |
3071 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
3072 S_028038_SW_MODE(iview
->image
->surface
.u
.gfx9
.surf
.swizzle_mode
) |
3073 S_028038_MAXMIP(iview
->image
->info
.levels
- 1);
3074 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
3075 S_02803C_SW_MODE(iview
->image
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
3077 ds
->db_z_info2
= S_028068_EPITCH(iview
->image
->surface
.u
.gfx9
.surf
.epitch
);
3078 ds
->db_stencil_info2
= S_02806C_EPITCH(iview
->image
->surface
.u
.gfx9
.stencil
.epitch
);
3079 ds
->db_depth_view
|= S_028008_MIPID(level
);
3081 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
3082 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
3084 if (radv_htile_enabled(iview
->image
, level
)) {
3085 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
3087 if (iview
->image
->tc_compatible_htile
) {
3088 unsigned max_zplanes
= 4;
3090 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
3091 iview
->image
->info
.samples
> 1)
3094 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
+ 1) |
3095 S_028038_ITERATE_FLUSH(1);
3096 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
3099 if (!iview
->image
->surface
.has_stencil
)
3100 /* Use all of the htile_buffer for depth if there's no stencil. */
3101 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
3102 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3103 iview
->image
->htile_offset
;
3104 ds
->db_htile_data_base
= va
>> 8;
3105 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
3106 S_028ABC_PIPE_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.pipe_aligned
) |
3107 S_028ABC_RB_ALIGNED(iview
->image
->surface
.u
.gfx9
.htile
.rb_aligned
);
3110 const struct legacy_surf_level
*level_info
= &iview
->image
->surface
.u
.legacy
.level
[level
];
3113 level_info
= &iview
->image
->surface
.u
.legacy
.stencil_level
[level
];
3115 z_offs
+= iview
->image
->surface
.u
.legacy
.level
[level
].offset
;
3116 s_offs
+= iview
->image
->surface
.u
.legacy
.stencil_level
[level
].offset
;
3118 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!iview
->image
->tc_compatible_htile
);
3119 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
3120 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
3122 if (iview
->image
->info
.samples
> 1)
3123 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
3125 if (device
->physical_device
->rad_info
.chip_class
>= CIK
) {
3126 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
3127 unsigned tiling_index
= iview
->image
->surface
.u
.legacy
.tiling_index
[level
];
3128 unsigned stencil_index
= iview
->image
->surface
.u
.legacy
.stencil_tiling_index
[level
];
3129 unsigned macro_index
= iview
->image
->surface
.u
.legacy
.macro_tile_index
;
3130 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
3131 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
3132 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
3135 tile_mode
= stencil_tile_mode
;
3137 ds
->db_depth_info
|=
3138 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
3139 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
3140 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
3141 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
3142 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
3143 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
3144 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
3145 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
3147 unsigned tile_mode_index
= si_tile_mode_index(iview
->image
, level
, false);
3148 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3149 tile_mode_index
= si_tile_mode_index(iview
->image
, level
, true);
3150 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
3152 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
3155 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
3156 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
3157 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
3159 if (radv_htile_enabled(iview
->image
, level
)) {
3160 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
3162 if (!iview
->image
->surface
.has_stencil
&&
3163 !iview
->image
->tc_compatible_htile
)
3164 /* Use all of the htile_buffer for depth if there's no stencil. */
3165 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
3167 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
3168 iview
->image
->htile_offset
;
3169 ds
->db_htile_data_base
= va
>> 8;
3170 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
3172 if (iview
->image
->tc_compatible_htile
) {
3173 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
3175 if (iview
->image
->info
.samples
<= 1)
3176 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3177 else if (iview
->image
->info
.samples
<= 4)
3178 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3180 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3185 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
3186 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
3189 VkResult
radv_CreateFramebuffer(
3191 const VkFramebufferCreateInfo
* pCreateInfo
,
3192 const VkAllocationCallbacks
* pAllocator
,
3193 VkFramebuffer
* pFramebuffer
)
3195 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3196 struct radv_framebuffer
*framebuffer
;
3198 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
3200 size_t size
= sizeof(*framebuffer
) +
3201 sizeof(struct radv_attachment_info
) * pCreateInfo
->attachmentCount
;
3202 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
3203 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3204 if (framebuffer
== NULL
)
3205 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3207 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
3208 framebuffer
->width
= pCreateInfo
->width
;
3209 framebuffer
->height
= pCreateInfo
->height
;
3210 framebuffer
->layers
= pCreateInfo
->layers
;
3211 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
3212 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
3213 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
3214 framebuffer
->attachments
[i
].attachment
= iview
;
3215 if (iview
->aspect_mask
& VK_IMAGE_ASPECT_COLOR_BIT
) {
3216 radv_initialise_color_surface(device
, &framebuffer
->attachments
[i
].cb
, iview
);
3217 } else if (iview
->aspect_mask
& (VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
)) {
3218 radv_initialise_ds_surface(device
, &framebuffer
->attachments
[i
].ds
, iview
);
3220 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
3221 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
3222 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_layer_count(iview
));
3225 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
3229 void radv_DestroyFramebuffer(
3232 const VkAllocationCallbacks
* pAllocator
)
3234 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3235 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
3239 vk_free2(&device
->alloc
, pAllocator
, fb
);
3242 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
3244 switch (address_mode
) {
3245 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
3246 return V_008F30_SQ_TEX_WRAP
;
3247 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
3248 return V_008F30_SQ_TEX_MIRROR
;
3249 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
3250 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
3251 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
3252 return V_008F30_SQ_TEX_CLAMP_BORDER
;
3253 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
3254 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
3256 unreachable("illegal tex wrap mode");
3262 radv_tex_compare(VkCompareOp op
)
3265 case VK_COMPARE_OP_NEVER
:
3266 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
3267 case VK_COMPARE_OP_LESS
:
3268 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
3269 case VK_COMPARE_OP_EQUAL
:
3270 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
3271 case VK_COMPARE_OP_LESS_OR_EQUAL
:
3272 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
3273 case VK_COMPARE_OP_GREATER
:
3274 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
3275 case VK_COMPARE_OP_NOT_EQUAL
:
3276 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
3277 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
3278 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
3279 case VK_COMPARE_OP_ALWAYS
:
3280 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
3282 unreachable("illegal compare mode");
3288 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
3291 case VK_FILTER_NEAREST
:
3292 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
3293 V_008F38_SQ_TEX_XY_FILTER_POINT
);
3294 case VK_FILTER_LINEAR
:
3295 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
3296 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
3297 case VK_FILTER_CUBIC_IMG
:
3299 fprintf(stderr
, "illegal texture filter");
3305 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
3308 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
3309 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
3310 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
3311 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
3313 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
3318 radv_tex_bordercolor(VkBorderColor bcolor
)
3321 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
3322 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
3323 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
3324 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
3325 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
3326 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
3327 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
3328 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
3329 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
3337 radv_tex_aniso_filter(unsigned filter
)
3351 radv_init_sampler(struct radv_device
*device
,
3352 struct radv_sampler
*sampler
,
3353 const VkSamplerCreateInfo
*pCreateInfo
)
3355 uint32_t max_aniso
= pCreateInfo
->anisotropyEnable
&& pCreateInfo
->maxAnisotropy
> 1.0 ?
3356 (uint32_t) pCreateInfo
->maxAnisotropy
: 0;
3357 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
3358 bool is_vi
= (device
->physical_device
->rad_info
.chip_class
>= VI
);
3360 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
3361 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
3362 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
3363 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
3364 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
3365 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
3366 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
3367 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
3368 S_008F30_DISABLE_CUBE_WRAP(0) |
3369 S_008F30_COMPAT_MODE(is_vi
));
3370 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
3371 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
3372 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
3373 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
3374 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
3375 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
3376 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
3377 S_008F38_MIP_POINT_PRECLAMP(0) |
3378 S_008F38_DISABLE_LSB_CEIL(1) |
3379 S_008F38_FILTER_PREC_FIX(1) |
3380 S_008F38_ANISO_OVERRIDE(is_vi
));
3381 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3382 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
3385 VkResult
radv_CreateSampler(
3387 const VkSamplerCreateInfo
* pCreateInfo
,
3388 const VkAllocationCallbacks
* pAllocator
,
3389 VkSampler
* pSampler
)
3391 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3392 struct radv_sampler
*sampler
;
3394 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
3396 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
3397 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
3399 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY
);
3401 radv_init_sampler(device
, sampler
, pCreateInfo
);
3402 *pSampler
= radv_sampler_to_handle(sampler
);
3407 void radv_DestroySampler(
3410 const VkAllocationCallbacks
* pAllocator
)
3412 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3413 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
3417 vk_free2(&device
->alloc
, pAllocator
, sampler
);
3420 /* vk_icd.h does not declare this function, so we declare it here to
3421 * suppress Wmissing-prototypes.
3423 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3424 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
3426 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3427 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
3429 /* For the full details on loader interface versioning, see
3430 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3431 * What follows is a condensed summary, to help you navigate the large and
3432 * confusing official doc.
3434 * - Loader interface v0 is incompatible with later versions. We don't
3437 * - In loader interface v1:
3438 * - The first ICD entrypoint called by the loader is
3439 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3441 * - The ICD must statically expose no other Vulkan symbol unless it is
3442 * linked with -Bsymbolic.
3443 * - Each dispatchable Vulkan handle created by the ICD must be
3444 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3445 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3446 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3447 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3448 * such loader-managed surfaces.
3450 * - Loader interface v2 differs from v1 in:
3451 * - The first ICD entrypoint called by the loader is
3452 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3453 * statically expose this entrypoint.
3455 * - Loader interface v3 differs from v2 in:
3456 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3457 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3458 * because the loader no longer does so.
3460 *pSupportedVersion
= MIN2(*pSupportedVersion
, 3u);
3464 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
3465 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
3468 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3469 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
3471 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
3473 /* We support only one handle type. */
3474 assert(pGetFdInfo
->handleType
==
3475 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3477 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
3479 return VK_ERROR_OUT_OF_DEVICE_MEMORY
;
3483 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
3484 VkExternalMemoryHandleTypeFlagBitsKHR handleType
,
3486 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
3488 /* The valid usage section for this function says:
3490 * "handleType must not be one of the handle types defined as opaque."
3492 * Since we only handle opaque handles for now, there are no FD properties.
3494 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3497 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
3498 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
3500 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3501 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
3502 uint32_t syncobj_handle
= 0;
3503 assert(pImportSemaphoreFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3505 int ret
= device
->ws
->import_syncobj(device
->ws
, pImportSemaphoreFdInfo
->fd
, &syncobj_handle
);
3507 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
;
3509 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR
) {
3510 sem
->temp_syncobj
= syncobj_handle
;
3512 sem
->syncobj
= syncobj_handle
;
3514 close(pImportSemaphoreFdInfo
->fd
);
3518 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
3519 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
3522 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3523 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
3525 uint32_t syncobj_handle
;
3527 assert(pGetFdInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
);
3528 if (sem
->temp_syncobj
)
3529 syncobj_handle
= sem
->temp_syncobj
;
3531 syncobj_handle
= sem
->syncobj
;
3532 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
3534 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR
);
3538 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3539 VkPhysicalDevice physicalDevice
,
3540 const VkPhysicalDeviceExternalSemaphoreInfoKHR
* pExternalSemaphoreInfo
,
3541 VkExternalSemaphorePropertiesKHR
* pExternalSemaphoreProperties
)
3543 if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
) {
3544 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3545 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR
;
3546 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR
|
3547 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR
;
3549 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
3550 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
3551 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;