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radv: Enable ACO on GFX7 (Sea Islands)
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "dirent.h"
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <linux/audit.h>
32 #include <linux/bpf.h>
33 #include <linux/filter.h>
34 #include <linux/seccomp.h>
35 #include <linux/unistd.h>
36 #include <stdbool.h>
37 #include <stddef.h>
38 #include <stdio.h>
39 #include <string.h>
40 #include <sys/prctl.h>
41 #include <sys/wait.h>
42 #include <unistd.h>
43 #include <fcntl.h>
44 #include <llvm/Config/llvm-config.h>
45
46 #include "radv_debug.h"
47 #include "radv_private.h"
48 #include "radv_shader.h"
49 #include "radv_cs.h"
50 #include "util/disk_cache.h"
51 #include "vk_util.h"
52 #include <xf86drm.h>
53 #include <amdgpu.h>
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
58 #include "sid.h"
59 #include "git_sha1.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "util/timespec.h"
64 #include "util/u_atomic.h"
65 #include "compiler/glsl_types.h"
66 #include "util/xmlpool.h"
67
68 static struct radv_timeline_point *
69 radv_timeline_find_point_at_least_locked(struct radv_device *device,
70 struct radv_timeline *timeline,
71 uint64_t p);
72
73 static struct radv_timeline_point *
74 radv_timeline_add_point_locked(struct radv_device *device,
75 struct radv_timeline *timeline,
76 uint64_t p);
77
78 static void
79 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
80 struct list_head *processing_list);
81
82 static
83 void radv_destroy_semaphore_part(struct radv_device *device,
84 struct radv_semaphore_part *part);
85
86 static int
87 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
88 {
89 struct mesa_sha1 ctx;
90 unsigned char sha1[20];
91 unsigned ptr_size = sizeof(void*);
92
93 memset(uuid, 0, VK_UUID_SIZE);
94 _mesa_sha1_init(&ctx);
95
96 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
97 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
98 return -1;
99
100 _mesa_sha1_update(&ctx, &family, sizeof(family));
101 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
102 _mesa_sha1_final(&ctx, sha1);
103
104 memcpy(uuid, sha1, VK_UUID_SIZE);
105 return 0;
106 }
107
108 static void
109 radv_get_driver_uuid(void *uuid)
110 {
111 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
112 }
113
114 static void
115 radv_get_device_uuid(struct radeon_info *info, void *uuid)
116 {
117 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
118 }
119
120 static uint64_t
121 radv_get_visible_vram_size(struct radv_physical_device *device)
122 {
123 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
124 }
125
126 static uint64_t
127 radv_get_vram_size(struct radv_physical_device *device)
128 {
129 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
130 }
131
132 static bool
133 radv_is_mem_type_vram(enum radv_mem_type type)
134 {
135 return type == RADV_MEM_TYPE_VRAM ||
136 type == RADV_MEM_TYPE_VRAM_UNCACHED;
137 }
138
139 static bool
140 radv_is_mem_type_vram_visible(enum radv_mem_type type)
141 {
142 return type == RADV_MEM_TYPE_VRAM_CPU_ACCESS ||
143 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
144 }
145 static bool
146 radv_is_mem_type_gtt_wc(enum radv_mem_type type)
147 {
148 return type == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
149 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
150 }
151
152 static bool
153 radv_is_mem_type_gtt_cached(enum radv_mem_type type)
154 {
155 return type == RADV_MEM_TYPE_GTT_CACHED ||
156 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
157 }
158
159 static bool
160 radv_is_mem_type_uncached(enum radv_mem_type type)
161 {
162 return type == RADV_MEM_TYPE_VRAM_UNCACHED ||
163 type == RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED ||
164 type == RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED ||
165 type == RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
166 }
167
168 static void
169 radv_physical_device_init_mem_types(struct radv_physical_device *device)
170 {
171 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
172 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
173 uint64_t vram_size = radv_get_vram_size(device);
174 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
175 device->memory_properties.memoryHeapCount = 0;
176 if (vram_size > 0) {
177 vram_index = device->memory_properties.memoryHeapCount++;
178 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
179 .size = vram_size,
180 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
181 };
182 }
183 if (visible_vram_size) {
184 visible_vram_index = device->memory_properties.memoryHeapCount++;
185 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
186 .size = visible_vram_size,
187 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
188 };
189 }
190 if (device->rad_info.gart_size > 0) {
191 gart_index = device->memory_properties.memoryHeapCount++;
192 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
193 .size = device->rad_info.gart_size,
194 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
195 };
196 }
197
198 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
199 unsigned type_count = 0;
200 if (vram_index >= 0) {
201 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
202 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
203 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
204 .heapIndex = vram_index,
205 };
206 }
207 if (gart_index >= 0 && device->rad_info.has_dedicated_vram) {
208 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
209 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
210 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
211 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
212 .heapIndex = gart_index,
213 };
214 }
215 if (visible_vram_index >= 0) {
216 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
217 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
218 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
219 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
220 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
221 .heapIndex = visible_vram_index,
222 };
223 }
224 if (gart_index >= 0 && !device->rad_info.has_dedicated_vram) {
225 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
226 * as they have identical property flags, and according to the
227 * spec, for types with identical flags, the one with greater
228 * performance must be given a lower index. */
229 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
230 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
231 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
232 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
233 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
234 .heapIndex = gart_index,
235 };
236 }
237 if (gart_index >= 0) {
238 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
239 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
240 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
241 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
242 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
243 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
244 .heapIndex = gart_index,
245 };
246 }
247 device->memory_properties.memoryTypeCount = type_count;
248
249 if (device->rad_info.has_l2_uncached) {
250 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
251 VkMemoryType mem_type = device->memory_properties.memoryTypes[i];
252
253 if ((mem_type.propertyFlags & (VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
254 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT)) ||
255 mem_type.propertyFlags == VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT) {
256 enum radv_mem_type mem_type_id;
257
258 switch (device->mem_type_indices[i]) {
259 case RADV_MEM_TYPE_VRAM:
260 mem_type_id = RADV_MEM_TYPE_VRAM_UNCACHED;
261 break;
262 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
263 mem_type_id = RADV_MEM_TYPE_VRAM_CPU_ACCESS_UNCACHED;
264 break;
265 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
266 mem_type_id = RADV_MEM_TYPE_GTT_WRITE_COMBINE_VRAM_UNCACHED;
267 break;
268 case RADV_MEM_TYPE_GTT_CACHED:
269 mem_type_id = RADV_MEM_TYPE_GTT_CACHED_VRAM_UNCACHED;
270 break;
271 default:
272 unreachable("invalid memory type");
273 }
274
275 VkMemoryPropertyFlags property_flags = mem_type.propertyFlags |
276 VK_MEMORY_PROPERTY_DEVICE_COHERENT_BIT_AMD |
277 VK_MEMORY_PROPERTY_DEVICE_UNCACHED_BIT_AMD;
278
279 device->mem_type_indices[type_count] = mem_type_id;
280 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
281 .propertyFlags = property_flags,
282 .heapIndex = mem_type.heapIndex,
283 };
284 }
285 }
286 device->memory_properties.memoryTypeCount = type_count;
287 }
288 }
289
290 static void
291 radv_handle_env_var_force_family(struct radv_physical_device *device)
292 {
293 const char *family = getenv("RADV_FORCE_FAMILY");
294 unsigned i;
295
296 if (!family)
297 return;
298
299 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
300 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
301 /* Override family and chip_class. */
302 device->rad_info.family = i;
303
304 if (i >= CHIP_NAVI10)
305 device->rad_info.chip_class = GFX10;
306 else if (i >= CHIP_VEGA10)
307 device->rad_info.chip_class = GFX9;
308 else if (i >= CHIP_TONGA)
309 device->rad_info.chip_class = GFX8;
310 else if (i >= CHIP_BONAIRE)
311 device->rad_info.chip_class = GFX7;
312 else
313 device->rad_info.chip_class = GFX6;
314
315 return;
316 }
317 }
318
319 fprintf(stderr, "radv: Unknown family: %s\n", family);
320 exit(1);
321 }
322
323 static VkResult
324 radv_physical_device_init(struct radv_physical_device *device,
325 struct radv_instance *instance,
326 drmDevicePtr drm_device)
327 {
328 const char *path = drm_device->nodes[DRM_NODE_RENDER];
329 VkResult result;
330 drmVersionPtr version;
331 int fd;
332 int master_fd = -1;
333
334 fd = open(path, O_RDWR | O_CLOEXEC);
335 if (fd < 0) {
336 if (instance->debug_flags & RADV_DEBUG_STARTUP)
337 radv_logi("Could not open device '%s'", path);
338
339 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
340 }
341
342 version = drmGetVersion(fd);
343 if (!version) {
344 close(fd);
345
346 if (instance->debug_flags & RADV_DEBUG_STARTUP)
347 radv_logi("Could not get the kernel driver version for device '%s'", path);
348
349 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
350 "failed to get version %s: %m", path);
351 }
352
353 if (strcmp(version->name, "amdgpu")) {
354 drmFreeVersion(version);
355 close(fd);
356
357 if (instance->debug_flags & RADV_DEBUG_STARTUP)
358 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
359
360 return VK_ERROR_INCOMPATIBLE_DRIVER;
361 }
362 drmFreeVersion(version);
363
364 if (instance->debug_flags & RADV_DEBUG_STARTUP)
365 radv_logi("Found compatible device '%s'.", path);
366
367 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
368 device->instance = instance;
369
370 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
371 instance->perftest_flags);
372 if (!device->ws) {
373 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
374 goto fail;
375 }
376
377 if (instance->enabled_extensions.KHR_display) {
378 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
379 if (master_fd >= 0) {
380 uint32_t accel_working = 0;
381 struct drm_amdgpu_info request = {
382 .return_pointer = (uintptr_t)&accel_working,
383 .return_size = sizeof(accel_working),
384 .query = AMDGPU_INFO_ACCEL_WORKING
385 };
386
387 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
388 close(master_fd);
389 master_fd = -1;
390 }
391 }
392 }
393
394 device->master_fd = master_fd;
395 device->local_fd = fd;
396 device->ws->query_info(device->ws, &device->rad_info);
397
398 radv_handle_env_var_force_family(device);
399
400 device->use_aco = instance->perftest_flags & RADV_PERFTEST_ACO;
401 if (device->rad_info.chip_class < GFX7 && device->use_aco) {
402 fprintf(stderr, "WARNING: disabling ACO on unsupported GPUs.\n");
403 device->use_aco = false;
404 }
405
406 snprintf(device->name, sizeof(device->name),
407 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING ")", device->use_aco ? "/ACO" : "",
408 device->rad_info.name);
409
410 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
411 device->ws->destroy(device->ws);
412 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
413 "cannot generate UUID");
414 goto fail;
415 }
416
417 /* These flags affect shader compilation. */
418 uint64_t shader_env_flags =
419 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
420 (device->use_aco ? 0x2 : 0);
421
422 /* The gpu id is already embedded in the uuid so we just pass "radv"
423 * when creating the cache.
424 */
425 char buf[VK_UUID_SIZE * 2 + 1];
426 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
427 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
428
429 if (device->rad_info.chip_class < GFX8 ||
430 device->rad_info.chip_class > GFX9)
431 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
432
433 radv_get_driver_uuid(&device->driver_uuid);
434 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
435
436 device->out_of_order_rast_allowed = device->rad_info.has_out_of_order_rast &&
437 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
438
439 device->dcc_msaa_allowed =
440 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
441
442 device->use_shader_ballot = (device->use_aco && device->rad_info.chip_class >= GFX8) ||
443 (device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT);
444
445 device->use_ngg = device->rad_info.chip_class >= GFX10 &&
446 device->rad_info.family != CHIP_NAVI14 &&
447 !(device->instance->debug_flags & RADV_DEBUG_NO_NGG);
448 if (device->use_aco && device->use_ngg) {
449 fprintf(stderr, "WARNING: disabling NGG because ACO is used.\n");
450 device->use_ngg = false;
451 }
452
453 device->use_ngg_streamout = false;
454
455 /* Determine the number of threads per wave for all stages. */
456 device->cs_wave_size = 64;
457 device->ps_wave_size = 64;
458 device->ge_wave_size = 64;
459
460 if (device->rad_info.chip_class >= GFX10) {
461 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
462 device->cs_wave_size = 32;
463
464 /* For pixel shaders, wave64 is recommanded. */
465 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
466 device->ps_wave_size = 32;
467
468 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
469 device->ge_wave_size = 32;
470 }
471
472 radv_physical_device_init_mem_types(device);
473 radv_fill_device_extension_table(device, &device->supported_extensions);
474
475 device->bus_info = *drm_device->businfo.pci;
476
477 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
478 ac_print_gpu_info(&device->rad_info);
479
480 /* The WSI is structured as a layer on top of the driver, so this has
481 * to be the last part of initialization (at least until we get other
482 * semi-layers).
483 */
484 result = radv_init_wsi(device);
485 if (result != VK_SUCCESS) {
486 device->ws->destroy(device->ws);
487 vk_error(instance, result);
488 goto fail;
489 }
490
491 return VK_SUCCESS;
492
493 fail:
494 close(fd);
495 if (master_fd != -1)
496 close(master_fd);
497 return result;
498 }
499
500 static void
501 radv_physical_device_finish(struct radv_physical_device *device)
502 {
503 radv_finish_wsi(device);
504 device->ws->destroy(device->ws);
505 disk_cache_destroy(device->disk_cache);
506 close(device->local_fd);
507 if (device->master_fd != -1)
508 close(device->master_fd);
509 }
510
511 static void *
512 default_alloc_func(void *pUserData, size_t size, size_t align,
513 VkSystemAllocationScope allocationScope)
514 {
515 return malloc(size);
516 }
517
518 static void *
519 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
520 size_t align, VkSystemAllocationScope allocationScope)
521 {
522 return realloc(pOriginal, size);
523 }
524
525 static void
526 default_free_func(void *pUserData, void *pMemory)
527 {
528 free(pMemory);
529 }
530
531 static const VkAllocationCallbacks default_alloc = {
532 .pUserData = NULL,
533 .pfnAllocation = default_alloc_func,
534 .pfnReallocation = default_realloc_func,
535 .pfnFree = default_free_func,
536 };
537
538 static const struct debug_control radv_debug_options[] = {
539 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
540 {"nodcc", RADV_DEBUG_NO_DCC},
541 {"shaders", RADV_DEBUG_DUMP_SHADERS},
542 {"nocache", RADV_DEBUG_NO_CACHE},
543 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
544 {"nohiz", RADV_DEBUG_NO_HIZ},
545 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
546 {"allbos", RADV_DEBUG_ALL_BOS},
547 {"noibs", RADV_DEBUG_NO_IBS},
548 {"spirv", RADV_DEBUG_DUMP_SPIRV},
549 {"vmfaults", RADV_DEBUG_VM_FAULTS},
550 {"zerovram", RADV_DEBUG_ZERO_VRAM},
551 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
552 {"nosisched", RADV_DEBUG_NO_SISCHED},
553 {"preoptir", RADV_DEBUG_PREOPTIR},
554 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
555 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
556 {"info", RADV_DEBUG_INFO},
557 {"errors", RADV_DEBUG_ERRORS},
558 {"startup", RADV_DEBUG_STARTUP},
559 {"checkir", RADV_DEBUG_CHECKIR},
560 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
561 {"nobinning", RADV_DEBUG_NOBINNING},
562 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
563 {"nongg", RADV_DEBUG_NO_NGG},
564 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT},
565 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS},
566 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS},
567 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE},
568 {NULL, 0}
569 };
570
571 const char *
572 radv_get_debug_option_name(int id)
573 {
574 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
575 return radv_debug_options[id].string;
576 }
577
578 static const struct debug_control radv_perftest_options[] = {
579 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
580 {"sisched", RADV_PERFTEST_SISCHED},
581 {"localbos", RADV_PERFTEST_LOCAL_BOS},
582 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
583 {"bolist", RADV_PERFTEST_BO_LIST},
584 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
585 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
586 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
587 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
588 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
589 {"dfsm", RADV_PERFTEST_DFSM},
590 {"aco", RADV_PERFTEST_ACO},
591 {NULL, 0}
592 };
593
594 const char *
595 radv_get_perftest_option_name(int id)
596 {
597 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
598 return radv_perftest_options[id].string;
599 }
600
601 static void
602 radv_handle_per_app_options(struct radv_instance *instance,
603 const VkApplicationInfo *info)
604 {
605 const char *name = info ? info->pApplicationName : NULL;
606
607 if (!name)
608 return;
609
610 if (!strcmp(name, "Talos - Linux - 32bit") ||
611 !strcmp(name, "Talos - Linux - 64bit")) {
612 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
613 /* Force enable LLVM sisched for Talos because it looks
614 * safe and it gives few more FPS.
615 */
616 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
617 }
618 } else if (!strcmp(name, "DOOM_VFR")) {
619 /* Work around a Doom VFR game bug */
620 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
621 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
622 /* Workaround for a WaW hazard when LLVM moves/merges
623 * load/store memory operations.
624 * See https://reviews.llvm.org/D61313
625 */
626 if (LLVM_VERSION_MAJOR < 9)
627 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
628 } else if (!strcmp(name, "Wolfenstein: Youngblood")) {
629 if (!(instance->debug_flags & RADV_DEBUG_NO_SHADER_BALLOT) &&
630 !(instance->perftest_flags & RADV_PERFTEST_ACO)) {
631 /* Force enable VK_AMD_shader_ballot because it looks
632 * safe and it gives a nice boost (+20% on Vega 56 at
633 * this time). It also prevents corruption on LLVM.
634 */
635 instance->perftest_flags |= RADV_PERFTEST_SHADER_BALLOT;
636 }
637 } else if (!strcmp(name, "Fledge")) {
638 /*
639 * Zero VRAM for "The Surge 2"
640 *
641 * This avoid a hang when when rendering any level. Likely
642 * uninitialized data in an indirect draw.
643 */
644 instance->debug_flags |= RADV_DEBUG_ZERO_VRAM;
645 }
646 }
647
648 static int radv_get_instance_extension_index(const char *name)
649 {
650 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
651 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
652 return i;
653 }
654 return -1;
655 }
656
657 static const char radv_dri_options_xml[] =
658 DRI_CONF_BEGIN
659 DRI_CONF_SECTION_PERFORMANCE
660 DRI_CONF_ADAPTIVE_SYNC("true")
661 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
662 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
663 DRI_CONF_SECTION_END
664 DRI_CONF_END;
665
666 static void radv_init_dri_options(struct radv_instance *instance)
667 {
668 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
669 driParseConfigFiles(&instance->dri_options,
670 &instance->available_dri_options,
671 0, "radv", NULL,
672 instance->engineName,
673 instance->engineVersion);
674 }
675
676 VkResult radv_CreateInstance(
677 const VkInstanceCreateInfo* pCreateInfo,
678 const VkAllocationCallbacks* pAllocator,
679 VkInstance* pInstance)
680 {
681 struct radv_instance *instance;
682 VkResult result;
683
684 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
685
686 uint32_t client_version;
687 if (pCreateInfo->pApplicationInfo &&
688 pCreateInfo->pApplicationInfo->apiVersion != 0) {
689 client_version = pCreateInfo->pApplicationInfo->apiVersion;
690 } else {
691 client_version = VK_API_VERSION_1_0;
692 }
693
694 const char *engine_name = NULL;
695 uint32_t engine_version = 0;
696 if (pCreateInfo->pApplicationInfo) {
697 engine_name = pCreateInfo->pApplicationInfo->pEngineName;
698 engine_version = pCreateInfo->pApplicationInfo->engineVersion;
699 }
700
701 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
702 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
703 if (!instance)
704 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
705
706 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
707
708 if (pAllocator)
709 instance->alloc = *pAllocator;
710 else
711 instance->alloc = default_alloc;
712
713 instance->apiVersion = client_version;
714 instance->physicalDeviceCount = -1;
715
716 /* Get secure compile thread count. NOTE: We cap this at 32 */
717 #define MAX_SC_PROCS 32
718 char *num_sc_threads = getenv("RADV_SECURE_COMPILE_THREADS");
719 if (num_sc_threads)
720 instance->num_sc_threads = MIN2(strtoul(num_sc_threads, NULL, 10), MAX_SC_PROCS);
721
722 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
723 radv_debug_options);
724
725 /* Disable memory cache when secure compile is set */
726 if (radv_device_use_secure_compile(instance))
727 instance->debug_flags |= RADV_DEBUG_NO_MEMORY_CACHE;
728
729 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
730 radv_perftest_options);
731
732 if (instance->perftest_flags & RADV_PERFTEST_ACO)
733 fprintf(stderr, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
734
735 if (instance->debug_flags & RADV_DEBUG_STARTUP)
736 radv_logi("Created an instance");
737
738 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
739 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
740 int index = radv_get_instance_extension_index(ext_name);
741
742 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
743 vk_free2(&default_alloc, pAllocator, instance);
744 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
745 }
746
747 instance->enabled_extensions.extensions[index] = true;
748 }
749
750 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
751 if (result != VK_SUCCESS) {
752 vk_free2(&default_alloc, pAllocator, instance);
753 return vk_error(instance, result);
754 }
755
756 instance->engineName = vk_strdup(&instance->alloc, engine_name,
757 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
758 instance->engineVersion = engine_version;
759
760 glsl_type_singleton_init_or_ref();
761
762 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
763
764 radv_init_dri_options(instance);
765 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
766
767 *pInstance = radv_instance_to_handle(instance);
768
769 return VK_SUCCESS;
770 }
771
772 void radv_DestroyInstance(
773 VkInstance _instance,
774 const VkAllocationCallbacks* pAllocator)
775 {
776 RADV_FROM_HANDLE(radv_instance, instance, _instance);
777
778 if (!instance)
779 return;
780
781 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
782 radv_physical_device_finish(instance->physicalDevices + i);
783 }
784
785 vk_free(&instance->alloc, instance->engineName);
786
787 VG(VALGRIND_DESTROY_MEMPOOL(instance));
788
789 glsl_type_singleton_decref();
790
791 driDestroyOptionCache(&instance->dri_options);
792 driDestroyOptionInfo(&instance->available_dri_options);
793
794 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
795
796 vk_free(&instance->alloc, instance);
797 }
798
799 static VkResult
800 radv_enumerate_devices(struct radv_instance *instance)
801 {
802 /* TODO: Check for more devices ? */
803 drmDevicePtr devices[8];
804 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
805 int max_devices;
806
807 instance->physicalDeviceCount = 0;
808
809 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
810
811 if (instance->debug_flags & RADV_DEBUG_STARTUP)
812 radv_logi("Found %d drm nodes", max_devices);
813
814 if (max_devices < 1)
815 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
816
817 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
818 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
819 devices[i]->bustype == DRM_BUS_PCI &&
820 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
821
822 result = radv_physical_device_init(instance->physicalDevices +
823 instance->physicalDeviceCount,
824 instance,
825 devices[i]);
826 if (result == VK_SUCCESS)
827 ++instance->physicalDeviceCount;
828 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
829 break;
830 }
831 }
832 drmFreeDevices(devices, max_devices);
833
834 return result;
835 }
836
837 VkResult radv_EnumeratePhysicalDevices(
838 VkInstance _instance,
839 uint32_t* pPhysicalDeviceCount,
840 VkPhysicalDevice* pPhysicalDevices)
841 {
842 RADV_FROM_HANDLE(radv_instance, instance, _instance);
843 VkResult result;
844
845 if (instance->physicalDeviceCount < 0) {
846 result = radv_enumerate_devices(instance);
847 if (result != VK_SUCCESS &&
848 result != VK_ERROR_INCOMPATIBLE_DRIVER)
849 return result;
850 }
851
852 if (!pPhysicalDevices) {
853 *pPhysicalDeviceCount = instance->physicalDeviceCount;
854 } else {
855 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
856 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
857 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
858 }
859
860 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
861 : VK_SUCCESS;
862 }
863
864 VkResult radv_EnumeratePhysicalDeviceGroups(
865 VkInstance _instance,
866 uint32_t* pPhysicalDeviceGroupCount,
867 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
868 {
869 RADV_FROM_HANDLE(radv_instance, instance, _instance);
870 VkResult result;
871
872 if (instance->physicalDeviceCount < 0) {
873 result = radv_enumerate_devices(instance);
874 if (result != VK_SUCCESS &&
875 result != VK_ERROR_INCOMPATIBLE_DRIVER)
876 return result;
877 }
878
879 if (!pPhysicalDeviceGroupProperties) {
880 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
881 } else {
882 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
883 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
884 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
885 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
886 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
887 }
888 }
889 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
890 : VK_SUCCESS;
891 }
892
893 void radv_GetPhysicalDeviceFeatures(
894 VkPhysicalDevice physicalDevice,
895 VkPhysicalDeviceFeatures* pFeatures)
896 {
897 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
898 memset(pFeatures, 0, sizeof(*pFeatures));
899
900 *pFeatures = (VkPhysicalDeviceFeatures) {
901 .robustBufferAccess = true,
902 .fullDrawIndexUint32 = true,
903 .imageCubeArray = true,
904 .independentBlend = true,
905 .geometryShader = true,
906 .tessellationShader = true,
907 .sampleRateShading = true,
908 .dualSrcBlend = true,
909 .logicOp = true,
910 .multiDrawIndirect = true,
911 .drawIndirectFirstInstance = true,
912 .depthClamp = true,
913 .depthBiasClamp = true,
914 .fillModeNonSolid = true,
915 .depthBounds = true,
916 .wideLines = true,
917 .largePoints = true,
918 .alphaToOne = true,
919 .multiViewport = true,
920 .samplerAnisotropy = true,
921 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
922 .textureCompressionASTC_LDR = false,
923 .textureCompressionBC = true,
924 .occlusionQueryPrecise = true,
925 .pipelineStatisticsQuery = true,
926 .vertexPipelineStoresAndAtomics = true,
927 .fragmentStoresAndAtomics = true,
928 .shaderTessellationAndGeometryPointSize = true,
929 .shaderImageGatherExtended = true,
930 .shaderStorageImageExtendedFormats = true,
931 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
932 .shaderUniformBufferArrayDynamicIndexing = true,
933 .shaderSampledImageArrayDynamicIndexing = true,
934 .shaderStorageBufferArrayDynamicIndexing = true,
935 .shaderStorageImageArrayDynamicIndexing = true,
936 .shaderStorageImageReadWithoutFormat = true,
937 .shaderStorageImageWriteWithoutFormat = true,
938 .shaderClipDistance = true,
939 .shaderCullDistance = true,
940 .shaderFloat64 = true,
941 .shaderInt64 = true,
942 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9 && !pdevice->use_aco,
943 .sparseBinding = true,
944 .variableMultisampleRate = true,
945 .inheritedQueries = true,
946 };
947 }
948
949 void radv_GetPhysicalDeviceFeatures2(
950 VkPhysicalDevice physicalDevice,
951 VkPhysicalDeviceFeatures2 *pFeatures)
952 {
953 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
954 vk_foreach_struct(ext, pFeatures->pNext) {
955 switch (ext->sType) {
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
957 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
958 features->variablePointersStorageBuffer = true;
959 features->variablePointers = true;
960 break;
961 }
962 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
963 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
964 features->multiview = true;
965 features->multiviewGeometryShader = true;
966 features->multiviewTessellationShader = true;
967 break;
968 }
969 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
970 VkPhysicalDeviceShaderDrawParametersFeatures *features =
971 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
972 features->shaderDrawParameters = true;
973 break;
974 }
975 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
976 VkPhysicalDeviceProtectedMemoryFeatures *features =
977 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
978 features->protectedMemory = false;
979 break;
980 }
981 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
982 VkPhysicalDevice16BitStorageFeatures *features =
983 (VkPhysicalDevice16BitStorageFeatures*)ext;
984 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
985 features->storageBuffer16BitAccess = enabled;
986 features->uniformAndStorageBuffer16BitAccess = enabled;
987 features->storagePushConstant16 = enabled;
988 features->storageInputOutput16 = enabled && LLVM_VERSION_MAJOR >= 9;
989 break;
990 }
991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
992 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
993 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
994 features->samplerYcbcrConversion = true;
995 break;
996 }
997 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
998 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
999 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
1000 features->shaderInputAttachmentArrayDynamicIndexing = true;
1001 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
1002 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
1003 features->shaderUniformBufferArrayNonUniformIndexing = true;
1004 features->shaderSampledImageArrayNonUniformIndexing = true;
1005 features->shaderStorageBufferArrayNonUniformIndexing = true;
1006 features->shaderStorageImageArrayNonUniformIndexing = true;
1007 features->shaderInputAttachmentArrayNonUniformIndexing = true;
1008 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
1009 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
1010 features->descriptorBindingUniformBufferUpdateAfterBind = true;
1011 features->descriptorBindingSampledImageUpdateAfterBind = true;
1012 features->descriptorBindingStorageImageUpdateAfterBind = true;
1013 features->descriptorBindingStorageBufferUpdateAfterBind = true;
1014 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
1015 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
1016 features->descriptorBindingUpdateUnusedWhilePending = true;
1017 features->descriptorBindingPartiallyBound = true;
1018 features->descriptorBindingVariableDescriptorCount = true;
1019 features->runtimeDescriptorArray = true;
1020 break;
1021 }
1022 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
1023 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
1024 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
1025 features->conditionalRendering = true;
1026 features->inheritedConditionalRendering = false;
1027 break;
1028 }
1029 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
1030 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
1031 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
1032 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
1033 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
1034 break;
1035 }
1036 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
1037 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
1038 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
1039 features->transformFeedback = true;
1040 features->geometryStreams = !pdevice->use_ngg_streamout;
1041 break;
1042 }
1043 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
1044 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
1045 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
1046 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
1047 break;
1048 }
1049 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
1050 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
1051 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
1052 features->memoryPriority = VK_TRUE;
1053 break;
1054 }
1055 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
1056 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
1057 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
1058 features->bufferDeviceAddress = true;
1059 features->bufferDeviceAddressCaptureReplay = false;
1060 features->bufferDeviceAddressMultiDevice = false;
1061 break;
1062 }
1063 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_KHR: {
1064 VkPhysicalDeviceBufferDeviceAddressFeaturesKHR *features =
1065 (VkPhysicalDeviceBufferDeviceAddressFeaturesKHR *)ext;
1066 features->bufferDeviceAddress = true;
1067 features->bufferDeviceAddressCaptureReplay = false;
1068 features->bufferDeviceAddressMultiDevice = false;
1069 break;
1070 }
1071 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
1072 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
1073 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
1074 features->depthClipEnable = true;
1075 break;
1076 }
1077 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
1078 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
1079 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
1080 features->hostQueryReset = true;
1081 break;
1082 }
1083 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
1084 VkPhysicalDevice8BitStorageFeaturesKHR *features =
1085 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
1086 bool enabled = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1087 features->storageBuffer8BitAccess = enabled;
1088 features->uniformAndStorageBuffer8BitAccess = enabled;
1089 features->storagePushConstant8 = enabled;
1090 break;
1091 }
1092 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES_KHR: {
1093 VkPhysicalDeviceShaderFloat16Int8FeaturesKHR *features =
1094 (VkPhysicalDeviceShaderFloat16Int8FeaturesKHR*)ext;
1095 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && !pdevice->use_aco;
1096 features->shaderInt8 = !pdevice->use_aco;
1097 break;
1098 }
1099 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
1100 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
1101 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
1102 features->shaderBufferInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1103 features->shaderSharedInt64Atomics = LLVM_VERSION_MAJOR >= 9;
1104 break;
1105 }
1106 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT: {
1107 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *features =
1108 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT *)ext;
1109 features->shaderDemoteToHelperInvocation = pdevice->use_aco;
1110 break;
1111 }
1112 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
1113 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
1114 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
1115
1116 features->inlineUniformBlock = true;
1117 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
1118 break;
1119 }
1120 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
1121 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
1122 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
1123 features->computeDerivativeGroupQuads = false;
1124 features->computeDerivativeGroupLinear = true;
1125 break;
1126 }
1127 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
1128 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1129 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1130 features->ycbcrImageArrays = true;
1131 break;
1132 }
1133 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1134 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1135 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1136 features->uniformBufferStandardLayout = true;
1137 break;
1138 }
1139 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1140 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1141 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1142 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1143 break;
1144 }
1145 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR: {
1146 VkPhysicalDeviceImagelessFramebufferFeaturesKHR *features =
1147 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR *)ext;
1148 features->imagelessFramebuffer = true;
1149 break;
1150 }
1151 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR: {
1152 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *features =
1153 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR *)ext;
1154 features->pipelineExecutableInfo = true;
1155 break;
1156 }
1157 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR: {
1158 VkPhysicalDeviceShaderClockFeaturesKHR *features =
1159 (VkPhysicalDeviceShaderClockFeaturesKHR *)ext;
1160 features->shaderSubgroupClock = true;
1161 features->shaderDeviceClock = false;
1162 break;
1163 }
1164 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT: {
1165 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *features =
1166 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT *)ext;
1167 features->texelBufferAlignment = true;
1168 break;
1169 }
1170 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_FEATURES_KHR: {
1171 VkPhysicalDeviceTimelineSemaphoreFeaturesKHR *features =
1172 (VkPhysicalDeviceTimelineSemaphoreFeaturesKHR *) ext;
1173 features->timelineSemaphore = true;
1174 break;
1175 }
1176 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_FEATURES_EXT: {
1177 VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *features =
1178 (VkPhysicalDeviceSubgroupSizeControlFeaturesEXT *)ext;
1179 features->subgroupSizeControl = true;
1180 features->computeFullSubgroups = true;
1181 break;
1182 }
1183 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COHERENT_MEMORY_FEATURES_AMD: {
1184 VkPhysicalDeviceCoherentMemoryFeaturesAMD *features =
1185 (VkPhysicalDeviceCoherentMemoryFeaturesAMD *)ext;
1186 features->deviceCoherentMemory = pdevice->rad_info.has_l2_uncached;
1187 break;
1188 }
1189 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_SUBGROUP_EXTENDED_TYPES_FEATURES_KHR: {
1190 VkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesKHR *features =
1191 (VkPhysicalDeviceShaderSubgroupExtendedTypesFeaturesKHR *)ext;
1192 features->shaderSubgroupExtendedTypes = true;
1193 break;
1194 }
1195 default:
1196 break;
1197 }
1198 }
1199 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1200 }
1201
1202 static size_t
1203 radv_max_descriptor_set_size()
1204 {
1205 /* make sure that the entire descriptor set is addressable with a signed
1206 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1207 * be at most 2 GiB. the combined image & samples object count as one of
1208 * both. This limit is for the pipeline layout, not for the set layout, but
1209 * there is no set limit, so we just set a pipeline limit. I don't think
1210 * any app is going to hit this soon. */
1211 return ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
1212 - MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1213 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1214 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1215 32 /* sampler, largest when combined with image */ +
1216 64 /* sampled image */ +
1217 64 /* storage image */);
1218 }
1219
1220 void radv_GetPhysicalDeviceProperties(
1221 VkPhysicalDevice physicalDevice,
1222 VkPhysicalDeviceProperties* pProperties)
1223 {
1224 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1225 VkSampleCountFlags sample_counts = 0xf;
1226
1227 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1228
1229 VkPhysicalDeviceLimits limits = {
1230 .maxImageDimension1D = (1 << 14),
1231 .maxImageDimension2D = (1 << 14),
1232 .maxImageDimension3D = (1 << 11),
1233 .maxImageDimensionCube = (1 << 14),
1234 .maxImageArrayLayers = (1 << 11),
1235 .maxTexelBufferElements = 128 * 1024 * 1024,
1236 .maxUniformBufferRange = UINT32_MAX,
1237 .maxStorageBufferRange = UINT32_MAX,
1238 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1239 .maxMemoryAllocationCount = UINT32_MAX,
1240 .maxSamplerAllocationCount = 64 * 1024,
1241 .bufferImageGranularity = 64, /* A cache line */
1242 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1243 .maxBoundDescriptorSets = MAX_SETS,
1244 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1245 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1246 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1247 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1248 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1249 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1250 .maxPerStageResources = max_descriptor_set_size,
1251 .maxDescriptorSetSamplers = max_descriptor_set_size,
1252 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1253 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1254 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1255 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1256 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1257 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1258 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1259 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1260 .maxVertexInputBindings = MAX_VBS,
1261 .maxVertexInputAttributeOffset = 2047,
1262 .maxVertexInputBindingStride = 2048,
1263 .maxVertexOutputComponents = 128,
1264 .maxTessellationGenerationLevel = 64,
1265 .maxTessellationPatchSize = 32,
1266 .maxTessellationControlPerVertexInputComponents = 128,
1267 .maxTessellationControlPerVertexOutputComponents = 128,
1268 .maxTessellationControlPerPatchOutputComponents = 120,
1269 .maxTessellationControlTotalOutputComponents = 4096,
1270 .maxTessellationEvaluationInputComponents = 128,
1271 .maxTessellationEvaluationOutputComponents = 128,
1272 .maxGeometryShaderInvocations = 127,
1273 .maxGeometryInputComponents = 64,
1274 .maxGeometryOutputComponents = 128,
1275 .maxGeometryOutputVertices = 256,
1276 .maxGeometryTotalOutputComponents = 1024,
1277 .maxFragmentInputComponents = 128,
1278 .maxFragmentOutputAttachments = 8,
1279 .maxFragmentDualSrcAttachments = 1,
1280 .maxFragmentCombinedOutputResources = 8,
1281 .maxComputeSharedMemorySize = 32768,
1282 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1283 .maxComputeWorkGroupInvocations = 2048,
1284 .maxComputeWorkGroupSize = {
1285 2048,
1286 2048,
1287 2048
1288 },
1289 .subPixelPrecisionBits = 8,
1290 .subTexelPrecisionBits = 8,
1291 .mipmapPrecisionBits = 8,
1292 .maxDrawIndexedIndexValue = UINT32_MAX,
1293 .maxDrawIndirectCount = UINT32_MAX,
1294 .maxSamplerLodBias = 16,
1295 .maxSamplerAnisotropy = 16,
1296 .maxViewports = MAX_VIEWPORTS,
1297 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1298 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1299 .viewportSubPixelBits = 8,
1300 .minMemoryMapAlignment = 4096, /* A page */
1301 .minTexelBufferOffsetAlignment = 4,
1302 .minUniformBufferOffsetAlignment = 4,
1303 .minStorageBufferOffsetAlignment = 4,
1304 .minTexelOffset = -32,
1305 .maxTexelOffset = 31,
1306 .minTexelGatherOffset = -32,
1307 .maxTexelGatherOffset = 31,
1308 .minInterpolationOffset = -2,
1309 .maxInterpolationOffset = 2,
1310 .subPixelInterpolationOffsetBits = 8,
1311 .maxFramebufferWidth = (1 << 14),
1312 .maxFramebufferHeight = (1 << 14),
1313 .maxFramebufferLayers = (1 << 10),
1314 .framebufferColorSampleCounts = sample_counts,
1315 .framebufferDepthSampleCounts = sample_counts,
1316 .framebufferStencilSampleCounts = sample_counts,
1317 .framebufferNoAttachmentsSampleCounts = sample_counts,
1318 .maxColorAttachments = MAX_RTS,
1319 .sampledImageColorSampleCounts = sample_counts,
1320 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1321 .sampledImageDepthSampleCounts = sample_counts,
1322 .sampledImageStencilSampleCounts = sample_counts,
1323 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1324 .maxSampleMaskWords = 1,
1325 .timestampComputeAndGraphics = true,
1326 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1327 .maxClipDistances = 8,
1328 .maxCullDistances = 8,
1329 .maxCombinedClipAndCullDistances = 8,
1330 .discreteQueuePriorities = 2,
1331 .pointSizeRange = { 0.0, 8192.0 },
1332 .lineWidthRange = { 0.0, 7.9921875 },
1333 .pointSizeGranularity = (1.0 / 8.0),
1334 .lineWidthGranularity = (1.0 / 128.0),
1335 .strictLines = false, /* FINISHME */
1336 .standardSampleLocations = true,
1337 .optimalBufferCopyOffsetAlignment = 128,
1338 .optimalBufferCopyRowPitchAlignment = 128,
1339 .nonCoherentAtomSize = 64,
1340 };
1341
1342 *pProperties = (VkPhysicalDeviceProperties) {
1343 .apiVersion = radv_physical_device_api_version(pdevice),
1344 .driverVersion = vk_get_driver_version(),
1345 .vendorID = ATI_VENDOR_ID,
1346 .deviceID = pdevice->rad_info.pci_id,
1347 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1348 .limits = limits,
1349 .sparseProperties = {0},
1350 };
1351
1352 strcpy(pProperties->deviceName, pdevice->name);
1353 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1354 }
1355
1356 void radv_GetPhysicalDeviceProperties2(
1357 VkPhysicalDevice physicalDevice,
1358 VkPhysicalDeviceProperties2 *pProperties)
1359 {
1360 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1361 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1362
1363 vk_foreach_struct(ext, pProperties->pNext) {
1364 switch (ext->sType) {
1365 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1366 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1367 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1368 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1369 break;
1370 }
1371 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1372 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1373 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1374 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1375 properties->deviceLUIDValid = false;
1376 break;
1377 }
1378 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1379 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1380 properties->maxMultiviewViewCount = MAX_VIEWS;
1381 properties->maxMultiviewInstanceIndex = INT_MAX;
1382 break;
1383 }
1384 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1385 VkPhysicalDevicePointClippingProperties *properties =
1386 (VkPhysicalDevicePointClippingProperties*)ext;
1387 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1388 break;
1389 }
1390 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1391 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1392 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1393 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1394 break;
1395 }
1396 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1397 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1398 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1399 properties->minImportedHostPointerAlignment = 4096;
1400 break;
1401 }
1402 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1403 VkPhysicalDeviceSubgroupProperties *properties =
1404 (VkPhysicalDeviceSubgroupProperties*)ext;
1405 properties->subgroupSize = RADV_SUBGROUP_SIZE;
1406 properties->supportedStages = VK_SHADER_STAGE_ALL;
1407 properties->supportedOperations =
1408 VK_SUBGROUP_FEATURE_BASIC_BIT |
1409 VK_SUBGROUP_FEATURE_VOTE_BIT |
1410 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1411 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1412 VK_SUBGROUP_FEATURE_CLUSTERED_BIT |
1413 VK_SUBGROUP_FEATURE_QUAD_BIT;
1414 if (pdevice->rad_info.chip_class == GFX8 ||
1415 pdevice->rad_info.chip_class == GFX9) {
1416 properties->supportedOperations |=
1417 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1418 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1419 }
1420 properties->quadOperationsInAllStages = true;
1421 break;
1422 }
1423 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1424 VkPhysicalDeviceMaintenance3Properties *properties =
1425 (VkPhysicalDeviceMaintenance3Properties*)ext;
1426 properties->maxPerSetDescriptors = RADV_MAX_PER_SET_DESCRIPTORS;
1427 properties->maxMemoryAllocationSize = RADV_MAX_MEMORY_ALLOCATION_SIZE;
1428 break;
1429 }
1430 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1431 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1432 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1433 /* GFX6-8 only support single channel min/max filter. */
1434 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1435 properties->filterMinmaxSingleComponentFormats = true;
1436 break;
1437 }
1438 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1439 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1440 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1441
1442 /* Shader engines. */
1443 properties->shaderEngineCount =
1444 pdevice->rad_info.max_se;
1445 properties->shaderArraysPerEngineCount =
1446 pdevice->rad_info.max_sh_per_se;
1447 properties->computeUnitsPerShaderArray =
1448 pdevice->rad_info.num_good_cu_per_sh;
1449 properties->simdPerComputeUnit = 4;
1450 properties->wavefrontsPerSimd =
1451 pdevice->rad_info.family == CHIP_TONGA ||
1452 pdevice->rad_info.family == CHIP_ICELAND ||
1453 pdevice->rad_info.family == CHIP_POLARIS10 ||
1454 pdevice->rad_info.family == CHIP_POLARIS11 ||
1455 pdevice->rad_info.family == CHIP_POLARIS12 ||
1456 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1457 properties->wavefrontSize = 64;
1458
1459 /* SGPR. */
1460 properties->sgprsPerSimd =
1461 pdevice->rad_info.num_physical_sgprs_per_simd;
1462 properties->minSgprAllocation =
1463 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1464 properties->maxSgprAllocation =
1465 pdevice->rad_info.family == CHIP_TONGA ||
1466 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1467 properties->sgprAllocationGranularity =
1468 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1469
1470 /* VGPR. */
1471 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1472 properties->minVgprAllocation = 4;
1473 properties->maxVgprAllocation = 256;
1474 properties->vgprAllocationGranularity = 4;
1475 break;
1476 }
1477 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD: {
1478 VkPhysicalDeviceShaderCoreProperties2AMD *properties =
1479 (VkPhysicalDeviceShaderCoreProperties2AMD *)ext;
1480
1481 properties->shaderCoreFeatures = 0;
1482 properties->activeComputeUnitCount =
1483 pdevice->rad_info.num_good_compute_units;
1484 break;
1485 }
1486 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1487 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1488 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1489 properties->maxVertexAttribDivisor = UINT32_MAX;
1490 break;
1491 }
1492 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1493 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1494 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1495 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1496 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1497 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1498 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1499 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1500 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1501 properties->robustBufferAccessUpdateAfterBind = false;
1502 properties->quadDivergentImplicitLod = false;
1503
1504 size_t max_descriptor_set_size = radv_max_descriptor_set_size();
1505 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1506 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1507 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1508 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1509 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1510 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1511 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1512 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1513 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1514 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1515 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1516 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1517 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1518 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1519 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1520 break;
1521 }
1522 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1523 VkPhysicalDeviceProtectedMemoryProperties *properties =
1524 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1525 properties->protectedNoFault = false;
1526 break;
1527 }
1528 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1529 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1530 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1531 properties->primitiveOverestimationSize = 0;
1532 properties->maxExtraPrimitiveOverestimationSize = 0;
1533 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1534 properties->primitiveUnderestimation = VK_FALSE;
1535 properties->conservativePointAndLineRasterization = VK_FALSE;
1536 properties->degenerateTrianglesRasterized = VK_FALSE;
1537 properties->degenerateLinesRasterized = VK_FALSE;
1538 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1539 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1540 break;
1541 }
1542 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1543 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1544 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1545 properties->pciDomain = pdevice->bus_info.domain;
1546 properties->pciBus = pdevice->bus_info.bus;
1547 properties->pciDevice = pdevice->bus_info.dev;
1548 properties->pciFunction = pdevice->bus_info.func;
1549 break;
1550 }
1551 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1552 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1553 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1554
1555 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1556 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1557 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1558 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1559 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1560
1561 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1562 .major = 1,
1563 .minor = 1,
1564 .subminor = 2,
1565 .patch = 0,
1566 };
1567 break;
1568 }
1569 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1570 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1571 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1572 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1573 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1574 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1575 properties->maxTransformFeedbackStreamDataSize = 512;
1576 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1577 properties->maxTransformFeedbackBufferDataStride = 512;
1578 properties->transformFeedbackQueries = !pdevice->use_ngg_streamout;
1579 properties->transformFeedbackStreamsLinesTriangles = !pdevice->use_ngg_streamout;
1580 properties->transformFeedbackRasterizationStreamSelect = false;
1581 properties->transformFeedbackDraw = true;
1582 break;
1583 }
1584 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1585 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1586 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1587
1588 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1589 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1590 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1591 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1592 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1593 break;
1594 }
1595 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1596 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1597 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1598 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1599 VK_SAMPLE_COUNT_4_BIT |
1600 VK_SAMPLE_COUNT_8_BIT;
1601 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1602 properties->sampleLocationCoordinateRange[0] = 0.0f;
1603 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1604 properties->sampleLocationSubPixelBits = 4;
1605 properties->variableSampleLocations = VK_FALSE;
1606 break;
1607 }
1608 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1609 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1610 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1611
1612 /* We support all of the depth resolve modes */
1613 properties->supportedDepthResolveModes =
1614 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1615 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1616 VK_RESOLVE_MODE_MIN_BIT_KHR |
1617 VK_RESOLVE_MODE_MAX_BIT_KHR;
1618
1619 /* Average doesn't make sense for stencil so we don't support that */
1620 properties->supportedStencilResolveModes =
1621 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1622 VK_RESOLVE_MODE_MIN_BIT_KHR |
1623 VK_RESOLVE_MODE_MAX_BIT_KHR;
1624
1625 properties->independentResolveNone = VK_TRUE;
1626 properties->independentResolve = VK_TRUE;
1627 break;
1628 }
1629 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT: {
1630 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *properties =
1631 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT *)ext;
1632 properties->storageTexelBufferOffsetAlignmentBytes = 4;
1633 properties->storageTexelBufferOffsetSingleTexelAlignment = true;
1634 properties->uniformTexelBufferOffsetAlignmentBytes = 4;
1635 properties->uniformTexelBufferOffsetSingleTexelAlignment = true;
1636 break;
1637 }
1638 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR : {
1639 VkPhysicalDeviceFloatControlsPropertiesKHR *properties =
1640 (VkPhysicalDeviceFloatControlsPropertiesKHR *)ext;
1641
1642 /* On AMD hardware, denormals and rounding modes for
1643 * fp16/fp64 are controlled by the same config
1644 * register.
1645 */
1646 properties->denormBehaviorIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1647 properties->roundingModeIndependence = VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR;
1648
1649 /* Do not allow both preserving and flushing denorms
1650 * because different shaders in the same pipeline can
1651 * have different settings and this won't work for
1652 * merged shaders. To make it work, this requires LLVM
1653 * support for changing the register. The same logic
1654 * applies for the rounding modes because they are
1655 * configured with the same config register.
1656 * TODO: we can enable a lot of these for ACO when it
1657 * supports all stages
1658 */
1659 properties->shaderDenormFlushToZeroFloat32 = true;
1660 properties->shaderDenormPreserveFloat32 = false;
1661 properties->shaderRoundingModeRTEFloat32 = true;
1662 properties->shaderRoundingModeRTZFloat32 = false;
1663 properties->shaderSignedZeroInfNanPreserveFloat32 = true;
1664
1665 properties->shaderDenormFlushToZeroFloat16 = false;
1666 properties->shaderDenormPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1667 properties->shaderRoundingModeRTEFloat16 = pdevice->rad_info.chip_class >= GFX8;
1668 properties->shaderRoundingModeRTZFloat16 = false;
1669 properties->shaderSignedZeroInfNanPreserveFloat16 = pdevice->rad_info.chip_class >= GFX8;
1670
1671 properties->shaderDenormFlushToZeroFloat64 = false;
1672 properties->shaderDenormPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1673 properties->shaderRoundingModeRTEFloat64 = pdevice->rad_info.chip_class >= GFX8;
1674 properties->shaderRoundingModeRTZFloat64 = false;
1675 properties->shaderSignedZeroInfNanPreserveFloat64 = pdevice->rad_info.chip_class >= GFX8;
1676 break;
1677 }
1678 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TIMELINE_SEMAPHORE_PROPERTIES_KHR: {
1679 VkPhysicalDeviceTimelineSemaphorePropertiesKHR *props =
1680 (VkPhysicalDeviceTimelineSemaphorePropertiesKHR *) ext;
1681 props->maxTimelineSemaphoreValueDifference = UINT64_MAX;
1682 break;
1683 }
1684 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_SIZE_CONTROL_PROPERTIES_EXT: {
1685 VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *props =
1686 (VkPhysicalDeviceSubgroupSizeControlPropertiesEXT *)ext;
1687 props->minSubgroupSize = 64;
1688 props->maxSubgroupSize = 64;
1689 props->maxComputeWorkgroupSubgroups = UINT32_MAX;
1690 props->requiredSubgroupSizeStages = 0;
1691
1692 if (pdevice->rad_info.chip_class >= GFX10) {
1693 /* Only GFX10+ supports wave32. */
1694 props->minSubgroupSize = 32;
1695 props->requiredSubgroupSizeStages = VK_SHADER_STAGE_COMPUTE_BIT;
1696 }
1697 break;
1698 }
1699 default:
1700 break;
1701 }
1702 }
1703 }
1704
1705 static void radv_get_physical_device_queue_family_properties(
1706 struct radv_physical_device* pdevice,
1707 uint32_t* pCount,
1708 VkQueueFamilyProperties** pQueueFamilyProperties)
1709 {
1710 int num_queue_families = 1;
1711 int idx;
1712 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1713 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1714 num_queue_families++;
1715
1716 if (pQueueFamilyProperties == NULL) {
1717 *pCount = num_queue_families;
1718 return;
1719 }
1720
1721 if (!*pCount)
1722 return;
1723
1724 idx = 0;
1725 if (*pCount >= 1) {
1726 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1727 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1728 VK_QUEUE_COMPUTE_BIT |
1729 VK_QUEUE_TRANSFER_BIT |
1730 VK_QUEUE_SPARSE_BINDING_BIT,
1731 .queueCount = 1,
1732 .timestampValidBits = 64,
1733 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1734 };
1735 idx++;
1736 }
1737
1738 if (pdevice->rad_info.num_rings[RING_COMPUTE] > 0 &&
1739 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1740 if (*pCount > idx) {
1741 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1742 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1743 VK_QUEUE_TRANSFER_BIT |
1744 VK_QUEUE_SPARSE_BINDING_BIT,
1745 .queueCount = pdevice->rad_info.num_rings[RING_COMPUTE],
1746 .timestampValidBits = 64,
1747 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1748 };
1749 idx++;
1750 }
1751 }
1752 *pCount = idx;
1753 }
1754
1755 void radv_GetPhysicalDeviceQueueFamilyProperties(
1756 VkPhysicalDevice physicalDevice,
1757 uint32_t* pCount,
1758 VkQueueFamilyProperties* pQueueFamilyProperties)
1759 {
1760 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1761 if (!pQueueFamilyProperties) {
1762 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1763 return;
1764 }
1765 VkQueueFamilyProperties *properties[] = {
1766 pQueueFamilyProperties + 0,
1767 pQueueFamilyProperties + 1,
1768 pQueueFamilyProperties + 2,
1769 };
1770 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1771 assert(*pCount <= 3);
1772 }
1773
1774 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1775 VkPhysicalDevice physicalDevice,
1776 uint32_t* pCount,
1777 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1778 {
1779 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1780 if (!pQueueFamilyProperties) {
1781 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1782 return;
1783 }
1784 VkQueueFamilyProperties *properties[] = {
1785 &pQueueFamilyProperties[0].queueFamilyProperties,
1786 &pQueueFamilyProperties[1].queueFamilyProperties,
1787 &pQueueFamilyProperties[2].queueFamilyProperties,
1788 };
1789 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1790 assert(*pCount <= 3);
1791 }
1792
1793 void radv_GetPhysicalDeviceMemoryProperties(
1794 VkPhysicalDevice physicalDevice,
1795 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1796 {
1797 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1798
1799 *pMemoryProperties = physical_device->memory_properties;
1800 }
1801
1802 static void
1803 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1804 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1805 {
1806 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1807 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1808 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1809 uint64_t vram_size = radv_get_vram_size(device);
1810 uint64_t gtt_size = device->rad_info.gart_size;
1811 uint64_t heap_budget, heap_usage;
1812
1813 /* For all memory heaps, the computation of budget is as follow:
1814 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1815 *
1816 * The Vulkan spec 1.1.97 says that the budget should include any
1817 * currently allocated device memory.
1818 *
1819 * Note that the application heap usages are not really accurate (eg.
1820 * in presence of shared buffers).
1821 */
1822 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1823 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1824
1825 if (radv_is_mem_type_vram(device->mem_type_indices[i])) {
1826 heap_usage = device->ws->query_value(device->ws,
1827 RADEON_ALLOCATED_VRAM);
1828
1829 heap_budget = vram_size -
1830 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1831 heap_usage;
1832
1833 memoryBudget->heapBudget[heap_index] = heap_budget;
1834 memoryBudget->heapUsage[heap_index] = heap_usage;
1835 } else if (radv_is_mem_type_vram_visible(device->mem_type_indices[i])) {
1836 heap_usage = device->ws->query_value(device->ws,
1837 RADEON_ALLOCATED_VRAM_VIS);
1838
1839 heap_budget = visible_vram_size -
1840 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1841 heap_usage;
1842
1843 memoryBudget->heapBudget[heap_index] = heap_budget;
1844 memoryBudget->heapUsage[heap_index] = heap_usage;
1845 } else if (radv_is_mem_type_gtt_wc(device->mem_type_indices[i])) {
1846 heap_usage = device->ws->query_value(device->ws,
1847 RADEON_ALLOCATED_GTT);
1848
1849 heap_budget = gtt_size -
1850 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1851 heap_usage;
1852
1853 memoryBudget->heapBudget[heap_index] = heap_budget;
1854 memoryBudget->heapUsage[heap_index] = heap_usage;
1855 }
1856 }
1857
1858 /* The heapBudget and heapUsage values must be zero for array elements
1859 * greater than or equal to
1860 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1861 */
1862 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1863 memoryBudget->heapBudget[i] = 0;
1864 memoryBudget->heapUsage[i] = 0;
1865 }
1866 }
1867
1868 void radv_GetPhysicalDeviceMemoryProperties2(
1869 VkPhysicalDevice physicalDevice,
1870 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1871 {
1872 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1873 &pMemoryProperties->memoryProperties);
1874
1875 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1876 vk_find_struct(pMemoryProperties->pNext,
1877 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1878 if (memory_budget)
1879 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1880 }
1881
1882 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1883 VkDevice _device,
1884 VkExternalMemoryHandleTypeFlagBits handleType,
1885 const void *pHostPointer,
1886 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1887 {
1888 RADV_FROM_HANDLE(radv_device, device, _device);
1889
1890 switch (handleType)
1891 {
1892 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1893 const struct radv_physical_device *physical_device = device->physical_device;
1894 uint32_t memoryTypeBits = 0;
1895 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1896 if (radv_is_mem_type_gtt_cached(physical_device->mem_type_indices[i])) {
1897 memoryTypeBits = (1 << i);
1898 break;
1899 }
1900 }
1901 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1902 return VK_SUCCESS;
1903 }
1904 default:
1905 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1906 }
1907 }
1908
1909 static enum radeon_ctx_priority
1910 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1911 {
1912 /* Default to MEDIUM when a specific global priority isn't requested */
1913 if (!pObj)
1914 return RADEON_CTX_PRIORITY_MEDIUM;
1915
1916 switch(pObj->globalPriority) {
1917 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1918 return RADEON_CTX_PRIORITY_REALTIME;
1919 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1920 return RADEON_CTX_PRIORITY_HIGH;
1921 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1922 return RADEON_CTX_PRIORITY_MEDIUM;
1923 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1924 return RADEON_CTX_PRIORITY_LOW;
1925 default:
1926 unreachable("Illegal global priority value");
1927 return RADEON_CTX_PRIORITY_INVALID;
1928 }
1929 }
1930
1931 static int
1932 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1933 uint32_t queue_family_index, int idx,
1934 VkDeviceQueueCreateFlags flags,
1935 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1936 {
1937 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1938 queue->device = device;
1939 queue->queue_family_index = queue_family_index;
1940 queue->queue_idx = idx;
1941 queue->priority = radv_get_queue_global_priority(global_priority);
1942 queue->flags = flags;
1943
1944 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1945 if (!queue->hw_ctx)
1946 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1947
1948 list_inithead(&queue->pending_submissions);
1949 pthread_mutex_init(&queue->pending_mutex, NULL);
1950
1951 return VK_SUCCESS;
1952 }
1953
1954 static void
1955 radv_queue_finish(struct radv_queue *queue)
1956 {
1957 pthread_mutex_destroy(&queue->pending_mutex);
1958
1959 if (queue->hw_ctx)
1960 queue->device->ws->ctx_destroy(queue->hw_ctx);
1961
1962 if (queue->initial_full_flush_preamble_cs)
1963 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1964 if (queue->initial_preamble_cs)
1965 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1966 if (queue->continue_preamble_cs)
1967 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1968 if (queue->descriptor_bo)
1969 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1970 if (queue->scratch_bo)
1971 queue->device->ws->buffer_destroy(queue->scratch_bo);
1972 if (queue->esgs_ring_bo)
1973 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1974 if (queue->gsvs_ring_bo)
1975 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1976 if (queue->tess_rings_bo)
1977 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1978 if (queue->gds_bo)
1979 queue->device->ws->buffer_destroy(queue->gds_bo);
1980 if (queue->gds_oa_bo)
1981 queue->device->ws->buffer_destroy(queue->gds_oa_bo);
1982 if (queue->compute_scratch_bo)
1983 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1984 }
1985
1986 static void
1987 radv_bo_list_init(struct radv_bo_list *bo_list)
1988 {
1989 pthread_mutex_init(&bo_list->mutex, NULL);
1990 bo_list->list.count = bo_list->capacity = 0;
1991 bo_list->list.bos = NULL;
1992 }
1993
1994 static void
1995 radv_bo_list_finish(struct radv_bo_list *bo_list)
1996 {
1997 free(bo_list->list.bos);
1998 pthread_mutex_destroy(&bo_list->mutex);
1999 }
2000
2001 static VkResult radv_bo_list_add(struct radv_device *device,
2002 struct radeon_winsys_bo *bo)
2003 {
2004 struct radv_bo_list *bo_list = &device->bo_list;
2005
2006 if (bo->is_local)
2007 return VK_SUCCESS;
2008
2009 if (unlikely(!device->use_global_bo_list))
2010 return VK_SUCCESS;
2011
2012 pthread_mutex_lock(&bo_list->mutex);
2013 if (bo_list->list.count == bo_list->capacity) {
2014 unsigned capacity = MAX2(4, bo_list->capacity * 2);
2015 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
2016
2017 if (!data) {
2018 pthread_mutex_unlock(&bo_list->mutex);
2019 return VK_ERROR_OUT_OF_HOST_MEMORY;
2020 }
2021
2022 bo_list->list.bos = (struct radeon_winsys_bo**)data;
2023 bo_list->capacity = capacity;
2024 }
2025
2026 bo_list->list.bos[bo_list->list.count++] = bo;
2027 pthread_mutex_unlock(&bo_list->mutex);
2028 return VK_SUCCESS;
2029 }
2030
2031 static void radv_bo_list_remove(struct radv_device *device,
2032 struct radeon_winsys_bo *bo)
2033 {
2034 struct radv_bo_list *bo_list = &device->bo_list;
2035
2036 if (bo->is_local)
2037 return;
2038
2039 if (unlikely(!device->use_global_bo_list))
2040 return;
2041
2042 pthread_mutex_lock(&bo_list->mutex);
2043 for(unsigned i = 0; i < bo_list->list.count; ++i) {
2044 if (bo_list->list.bos[i] == bo) {
2045 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
2046 --bo_list->list.count;
2047 break;
2048 }
2049 }
2050 pthread_mutex_unlock(&bo_list->mutex);
2051 }
2052
2053 static void
2054 radv_device_init_gs_info(struct radv_device *device)
2055 {
2056 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
2057 device->physical_device->rad_info.family);
2058 }
2059
2060 static int radv_get_device_extension_index(const char *name)
2061 {
2062 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
2063 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
2064 return i;
2065 }
2066 return -1;
2067 }
2068
2069 static int
2070 radv_get_int_debug_option(const char *name, int default_value)
2071 {
2072 const char *str;
2073 int result;
2074
2075 str = getenv(name);
2076 if (!str) {
2077 result = default_value;
2078 } else {
2079 char *endptr;
2080
2081 result = strtol(str, &endptr, 0);
2082 if (str == endptr) {
2083 /* No digits founs. */
2084 result = default_value;
2085 }
2086 }
2087
2088 return result;
2089 }
2090
2091 static int install_seccomp_filter() {
2092
2093 struct sock_filter filter[] = {
2094 /* Check arch is 64bit x86 */
2095 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, arch))),
2096 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, AUDIT_ARCH_X86_64, 0, 12),
2097
2098 /* Futex is required for mutex locks */
2099 #if defined __NR__newselect
2100 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2101 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR__newselect, 11, 0),
2102 #elif defined __NR_select
2103 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2104 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_select, 11, 0),
2105 #else
2106 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2107 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_pselect6, 11, 0),
2108 #endif
2109
2110 /* Allow system exit calls for the forked process */
2111 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2112 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_exit_group, 9, 0),
2113
2114 /* Allow system read calls */
2115 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2116 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_read, 7, 0),
2117
2118 /* Allow system write calls */
2119 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2120 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_write, 5, 0),
2121
2122 /* Allow system brk calls (we need this for malloc) */
2123 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2124 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_brk, 3, 0),
2125
2126 /* Futex is required for mutex locks */
2127 BPF_STMT(BPF_LD + BPF_W + BPF_ABS, (offsetof(struct seccomp_data, nr))),
2128 BPF_JUMP(BPF_JMP + BPF_JEQ + BPF_K, __NR_futex, 1, 0),
2129
2130 /* Return error if we hit a system call not on the whitelist */
2131 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ERRNO | (EPERM & SECCOMP_RET_DATA)),
2132
2133 /* Allow whitelisted system calls */
2134 BPF_STMT(BPF_RET + BPF_K, SECCOMP_RET_ALLOW),
2135 };
2136
2137 struct sock_fprog prog = {
2138 .len = (unsigned short)(sizeof(filter) / sizeof(filter[0])),
2139 .filter = filter,
2140 };
2141
2142 if (prctl(PR_SET_NO_NEW_PRIVS, 1, 0, 0, 0))
2143 return -1;
2144
2145 if (prctl(PR_SET_SECCOMP, SECCOMP_MODE_FILTER, &prog))
2146 return -1;
2147
2148 return 0;
2149 }
2150
2151 /* Helper function with timeout support for reading from the pipe between
2152 * processes used for secure compile.
2153 */
2154 bool radv_sc_read(int fd, void *buf, size_t size, bool timeout)
2155 {
2156 fd_set fds;
2157 struct timeval tv;
2158
2159 FD_ZERO(&fds);
2160 FD_SET(fd, &fds);
2161
2162 while (true) {
2163 /* We can't rely on the value of tv after calling select() so
2164 * we must reset it on each iteration of the loop.
2165 */
2166 tv.tv_sec = 5;
2167 tv.tv_usec = 0;
2168
2169 int rval = select(fd + 1, &fds, NULL, NULL, timeout ? &tv : NULL);
2170
2171 if (rval == -1) {
2172 /* select error */
2173 return false;
2174 } else if (rval) {
2175 ssize_t bytes_read = read(fd, buf, size);
2176 if (bytes_read < 0)
2177 return false;
2178
2179 buf += bytes_read;
2180 size -= bytes_read;
2181 if (size == 0)
2182 return true;
2183 } else {
2184 /* select timeout */
2185 return false;
2186 }
2187 }
2188 }
2189
2190 static bool radv_close_all_fds(const int *keep_fds, int keep_fd_count)
2191 {
2192 DIR *d;
2193 struct dirent *dir;
2194 d = opendir("/proc/self/fd");
2195 if (!d)
2196 return false;
2197 int dir_fd = dirfd(d);
2198
2199 while ((dir = readdir(d)) != NULL) {
2200 if (dir->d_name[0] == '.')
2201 continue;
2202
2203 int fd = atoi(dir->d_name);
2204 if (fd == dir_fd)
2205 continue;
2206
2207 bool keep = false;
2208 for (int i = 0; !keep && i < keep_fd_count; ++i)
2209 if (keep_fds[i] == fd)
2210 keep = true;
2211
2212 if (keep)
2213 continue;
2214
2215 close(fd);
2216 }
2217 closedir(d);
2218 return true;
2219 }
2220
2221 static bool secure_compile_open_fifo_fds(struct radv_secure_compile_state *sc,
2222 int *fd_server, int *fd_client,
2223 unsigned process, bool make_fifo)
2224 {
2225 bool result = false;
2226 char *fifo_server_path = NULL;
2227 char *fifo_client_path = NULL;
2228
2229 if (asprintf(&fifo_server_path, "/tmp/radv_server_%s_%u", sc->uid, process) == -1)
2230 goto open_fifo_exit;
2231
2232 if (asprintf(&fifo_client_path, "/tmp/radv_client_%s_%u", sc->uid, process) == -1)
2233 goto open_fifo_exit;
2234
2235 if (make_fifo) {
2236 int file1 = mkfifo(fifo_server_path, 0666);
2237 if(file1 < 0)
2238 goto open_fifo_exit;
2239
2240 int file2 = mkfifo(fifo_client_path, 0666);
2241 if(file2 < 0)
2242 goto open_fifo_exit;
2243 }
2244
2245 *fd_server = open(fifo_server_path, O_RDWR);
2246 if(*fd_server < 1)
2247 goto open_fifo_exit;
2248
2249 *fd_client = open(fifo_client_path, O_RDWR);
2250 if(*fd_client < 1) {
2251 close(*fd_server);
2252 goto open_fifo_exit;
2253 }
2254
2255 result = true;
2256
2257 open_fifo_exit:
2258 free(fifo_server_path);
2259 free(fifo_client_path);
2260
2261 return result;
2262 }
2263
2264 static void run_secure_compile_device(struct radv_device *device, unsigned process,
2265 int fd_idle_device_output)
2266 {
2267 int fd_secure_input;
2268 int fd_secure_output;
2269 bool fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2270 &fd_secure_input,
2271 &fd_secure_output,
2272 process, false);
2273
2274 enum radv_secure_compile_type sc_type;
2275
2276 const int needed_fds[] = {
2277 fd_secure_input,
2278 fd_secure_output,
2279 fd_idle_device_output,
2280 };
2281
2282 if (!fifo_result || !radv_close_all_fds(needed_fds, ARRAY_SIZE(needed_fds)) ||
2283 install_seccomp_filter() == -1) {
2284 sc_type = RADV_SC_TYPE_INIT_FAILURE;
2285 } else {
2286 sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2287 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2288 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2289 }
2290
2291 write(fd_idle_device_output, &sc_type, sizeof(sc_type));
2292
2293 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2294 goto secure_compile_exit;
2295
2296 while (true) {
2297 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2298
2299 if (sc_type == RADV_SC_TYPE_COMPILE_PIPELINE) {
2300 struct radv_pipeline *pipeline;
2301 bool sc_read = true;
2302
2303 pipeline = vk_zalloc2(&device->alloc, NULL, sizeof(*pipeline), 8,
2304 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2305
2306 pipeline->device = device;
2307
2308 /* Read pipeline layout */
2309 struct radv_pipeline_layout layout;
2310 sc_read = radv_sc_read(fd_secure_input, &layout, sizeof(struct radv_pipeline_layout), true);
2311 sc_read &= radv_sc_read(fd_secure_input, &layout.num_sets, sizeof(uint32_t), true);
2312 if (!sc_read)
2313 goto secure_compile_exit;
2314
2315 for (uint32_t set = 0; set < layout.num_sets; set++) {
2316 uint32_t layout_size;
2317 sc_read &= radv_sc_read(fd_secure_input, &layout_size, sizeof(uint32_t), true);
2318 if (!sc_read)
2319 goto secure_compile_exit;
2320
2321 layout.set[set].layout = malloc(layout_size);
2322 layout.set[set].layout->layout_size = layout_size;
2323 sc_read &= radv_sc_read(fd_secure_input, layout.set[set].layout,
2324 layout.set[set].layout->layout_size, true);
2325 }
2326
2327 pipeline->layout = &layout;
2328
2329 /* Read pipeline key */
2330 struct radv_pipeline_key key;
2331 sc_read &= radv_sc_read(fd_secure_input, &key, sizeof(struct radv_pipeline_key), true);
2332
2333 /* Read pipeline create flags */
2334 VkPipelineCreateFlags flags;
2335 sc_read &= radv_sc_read(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags), true);
2336
2337 /* Read stage and shader information */
2338 uint32_t num_stages;
2339 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
2340 sc_read &= radv_sc_read(fd_secure_input, &num_stages, sizeof(uint32_t), true);
2341 if (!sc_read)
2342 goto secure_compile_exit;
2343
2344 for (uint32_t i = 0; i < num_stages; i++) {
2345
2346 /* Read stage */
2347 gl_shader_stage stage;
2348 sc_read &= radv_sc_read(fd_secure_input, &stage, sizeof(gl_shader_stage), true);
2349
2350 VkPipelineShaderStageCreateInfo *pStage = calloc(1, sizeof(VkPipelineShaderStageCreateInfo));
2351
2352 /* Read entry point name */
2353 size_t name_size;
2354 sc_read &= radv_sc_read(fd_secure_input, &name_size, sizeof(size_t), true);
2355 if (!sc_read)
2356 goto secure_compile_exit;
2357
2358 char *ep_name = malloc(name_size);
2359 sc_read &= radv_sc_read(fd_secure_input, ep_name, name_size, true);
2360 pStage->pName = ep_name;
2361
2362 /* Read shader module */
2363 size_t module_size;
2364 sc_read &= radv_sc_read(fd_secure_input, &module_size, sizeof(size_t), true);
2365 if (!sc_read)
2366 goto secure_compile_exit;
2367
2368 struct radv_shader_module *module = malloc(module_size);
2369 sc_read &= radv_sc_read(fd_secure_input, module, module_size, true);
2370 pStage->module = radv_shader_module_to_handle(module);
2371
2372 /* Read specialization info */
2373 bool has_spec_info;
2374 sc_read &= radv_sc_read(fd_secure_input, &has_spec_info, sizeof(bool), true);
2375 if (!sc_read)
2376 goto secure_compile_exit;
2377
2378 if (has_spec_info) {
2379 VkSpecializationInfo *specInfo = malloc(sizeof(VkSpecializationInfo));
2380 pStage->pSpecializationInfo = specInfo;
2381
2382 sc_read &= radv_sc_read(fd_secure_input, &specInfo->dataSize, sizeof(size_t), true);
2383 if (!sc_read)
2384 goto secure_compile_exit;
2385
2386 void *si_data = malloc(specInfo->dataSize);
2387 sc_read &= radv_sc_read(fd_secure_input, si_data, specInfo->dataSize, true);
2388 specInfo->pData = si_data;
2389
2390 sc_read &= radv_sc_read(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t), true);
2391 if (!sc_read)
2392 goto secure_compile_exit;
2393
2394 VkSpecializationMapEntry *mapEntries = malloc(sizeof(VkSpecializationMapEntry) * specInfo->mapEntryCount);
2395 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++) {
2396 sc_read &= radv_sc_read(fd_secure_input, &mapEntries[j], sizeof(VkSpecializationMapEntry), true);
2397 if (!sc_read)
2398 goto secure_compile_exit;
2399 }
2400
2401 specInfo->pMapEntries = mapEntries;
2402 }
2403
2404 pStages[stage] = pStage;
2405 }
2406
2407 /* Compile the shaders */
2408 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
2409 radv_create_shaders(pipeline, device, NULL, &key, pStages, flags, NULL, stage_feedbacks);
2410
2411 /* free memory allocated above */
2412 for (uint32_t set = 0; set < layout.num_sets; set++)
2413 free(layout.set[set].layout);
2414
2415 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
2416 if (!pStages[i])
2417 continue;
2418
2419 free((void *) pStages[i]->pName);
2420 free(radv_shader_module_from_handle(pStages[i]->module));
2421 if (pStages[i]->pSpecializationInfo) {
2422 free((void *) pStages[i]->pSpecializationInfo->pData);
2423 free((void *) pStages[i]->pSpecializationInfo->pMapEntries);
2424 free((void *) pStages[i]->pSpecializationInfo);
2425 }
2426 free((void *) pStages[i]);
2427 }
2428
2429 vk_free(&device->alloc, pipeline);
2430
2431 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED;
2432 write(fd_secure_output, &sc_type, sizeof(sc_type));
2433
2434 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2435 goto secure_compile_exit;
2436 }
2437 }
2438
2439 secure_compile_exit:
2440 close(fd_secure_input);
2441 close(fd_secure_output);
2442 close(fd_idle_device_output);
2443 _exit(0);
2444 }
2445
2446 static enum radv_secure_compile_type fork_secure_compile_device(struct radv_device *device, unsigned process)
2447 {
2448 int fd_secure_input[2];
2449 int fd_secure_output[2];
2450
2451 /* create pipe descriptors (used to communicate between processes) */
2452 if (pipe(fd_secure_input) == -1 || pipe(fd_secure_output) == -1)
2453 return RADV_SC_TYPE_INIT_FAILURE;
2454
2455
2456 int sc_pid;
2457 if ((sc_pid = fork()) == 0) {
2458 device->sc_state->secure_compile_thread_counter = process;
2459 run_secure_compile_device(device, process, fd_secure_output[1]);
2460 } else {
2461 if (sc_pid == -1)
2462 return RADV_SC_TYPE_INIT_FAILURE;
2463
2464 /* Read the init result returned from the secure process */
2465 enum radv_secure_compile_type sc_type;
2466 bool sc_read = radv_sc_read(fd_secure_output[0], &sc_type, sizeof(sc_type), true);
2467
2468 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read) {
2469 close(fd_secure_input[0]);
2470 close(fd_secure_input[1]);
2471 close(fd_secure_output[1]);
2472 close(fd_secure_output[0]);
2473 int status;
2474 waitpid(sc_pid, &status, 0);
2475
2476 return RADV_SC_TYPE_INIT_FAILURE;
2477 } else {
2478 assert(sc_type == RADV_SC_TYPE_INIT_SUCCESS);
2479 write(device->sc_state->secure_compile_processes[process].fd_secure_output, &sc_type, sizeof(sc_type));
2480
2481 close(fd_secure_input[0]);
2482 close(fd_secure_input[1]);
2483 close(fd_secure_output[1]);
2484 close(fd_secure_output[0]);
2485
2486 int status;
2487 waitpid(sc_pid, &status, 0);
2488 }
2489 }
2490
2491 return RADV_SC_TYPE_INIT_SUCCESS;
2492 }
2493
2494 /* Run a bare bones fork of a device that was forked right after its creation.
2495 * This device will have low overhead when it is forked again before each
2496 * pipeline compilation. This device sits idle and its only job is to fork
2497 * itself.
2498 */
2499 static void run_secure_compile_idle_device(struct radv_device *device, unsigned process,
2500 int fd_secure_input, int fd_secure_output)
2501 {
2502 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_INIT_SUCCESS;
2503 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input;
2504 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output;
2505
2506 write(fd_secure_output, &sc_type, sizeof(sc_type));
2507
2508 while (true) {
2509 radv_sc_read(fd_secure_input, &sc_type, sizeof(sc_type), false);
2510
2511 if (sc_type == RADV_SC_TYPE_FORK_DEVICE) {
2512 sc_type = fork_secure_compile_device(device, process);
2513
2514 if (sc_type == RADV_SC_TYPE_INIT_FAILURE)
2515 goto secure_compile_exit;
2516
2517 } else if (sc_type == RADV_SC_TYPE_DESTROY_DEVICE) {
2518 goto secure_compile_exit;
2519 }
2520 }
2521
2522 secure_compile_exit:
2523 close(fd_secure_input);
2524 close(fd_secure_output);
2525 _exit(0);
2526 }
2527
2528 static void destroy_secure_compile_device(struct radv_device *device, unsigned process)
2529 {
2530 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
2531
2532 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
2533 write(fd_secure_input, &sc_type, sizeof(sc_type));
2534
2535 close(device->sc_state->secure_compile_processes[process].fd_secure_input);
2536 close(device->sc_state->secure_compile_processes[process].fd_secure_output);
2537
2538 int status;
2539 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2540 }
2541
2542 static VkResult fork_secure_compile_idle_device(struct radv_device *device)
2543 {
2544 device->sc_state = vk_zalloc(&device->alloc,
2545 sizeof(struct radv_secure_compile_state),
2546 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2547
2548 mtx_init(&device->sc_state->secure_compile_mutex, mtx_plain);
2549
2550 pid_t upid = getpid();
2551 time_t seconds = time(NULL);
2552
2553 char *uid;
2554 if (asprintf(&uid, "%ld_%ld", (long) upid, (long) seconds) == -1)
2555 return VK_ERROR_INITIALIZATION_FAILED;
2556
2557 device->sc_state->uid = uid;
2558
2559 uint8_t sc_threads = device->instance->num_sc_threads;
2560 int fd_secure_input[MAX_SC_PROCS][2];
2561 int fd_secure_output[MAX_SC_PROCS][2];
2562
2563 /* create pipe descriptors (used to communicate between processes) */
2564 for (unsigned i = 0; i < sc_threads; i++) {
2565 if (pipe(fd_secure_input[i]) == -1 ||
2566 pipe(fd_secure_output[i]) == -1) {
2567 return VK_ERROR_INITIALIZATION_FAILED;
2568 }
2569 }
2570
2571 device->sc_state->secure_compile_processes = vk_zalloc(&device->alloc,
2572 sizeof(struct radv_secure_compile_process) * sc_threads, 8,
2573 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2574
2575 for (unsigned process = 0; process < sc_threads; process++) {
2576 if ((device->sc_state->secure_compile_processes[process].sc_pid = fork()) == 0) {
2577 device->sc_state->secure_compile_thread_counter = process;
2578 run_secure_compile_idle_device(device, process, fd_secure_input[process][0], fd_secure_output[process][1]);
2579 } else {
2580 if (device->sc_state->secure_compile_processes[process].sc_pid == -1)
2581 return VK_ERROR_INITIALIZATION_FAILED;
2582
2583 /* Read the init result returned from the secure process */
2584 enum radv_secure_compile_type sc_type;
2585 bool sc_read = radv_sc_read(fd_secure_output[process][0], &sc_type, sizeof(sc_type), true);
2586
2587 bool fifo_result;
2588 if (sc_read && sc_type == RADV_SC_TYPE_INIT_SUCCESS) {
2589 fifo_result = secure_compile_open_fifo_fds(device->sc_state,
2590 &device->sc_state->secure_compile_processes[process].fd_server,
2591 &device->sc_state->secure_compile_processes[process].fd_client,
2592 process, true);
2593
2594 device->sc_state->secure_compile_processes[process].fd_secure_input = fd_secure_input[process][1];
2595 device->sc_state->secure_compile_processes[process].fd_secure_output = fd_secure_output[process][0];
2596 }
2597
2598 if (sc_type == RADV_SC_TYPE_INIT_FAILURE || !sc_read || !fifo_result) {
2599 close(fd_secure_input[process][0]);
2600 close(fd_secure_input[process][1]);
2601 close(fd_secure_output[process][1]);
2602 close(fd_secure_output[process][0]);
2603 int status;
2604 waitpid(device->sc_state->secure_compile_processes[process].sc_pid, &status, 0);
2605
2606 /* Destroy any forks that were created sucessfully */
2607 for (unsigned i = 0; i < process; i++) {
2608 destroy_secure_compile_device(device, i);
2609 }
2610
2611 return VK_ERROR_INITIALIZATION_FAILED;
2612 }
2613 }
2614 }
2615 return VK_SUCCESS;
2616 }
2617
2618 static VkResult
2619 radv_create_pthread_cond(pthread_cond_t *cond)
2620 {
2621 pthread_condattr_t condattr;
2622 if (pthread_condattr_init(&condattr)) {
2623 return VK_ERROR_INITIALIZATION_FAILED;
2624 }
2625
2626 if (pthread_condattr_setclock(&condattr, CLOCK_MONOTONIC)) {
2627 pthread_condattr_destroy(&condattr);
2628 return VK_ERROR_INITIALIZATION_FAILED;
2629 }
2630 if (pthread_cond_init(cond, &condattr)) {
2631 pthread_condattr_destroy(&condattr);
2632 return VK_ERROR_INITIALIZATION_FAILED;
2633 }
2634 pthread_condattr_destroy(&condattr);
2635 return VK_SUCCESS;
2636 }
2637
2638 VkResult radv_CreateDevice(
2639 VkPhysicalDevice physicalDevice,
2640 const VkDeviceCreateInfo* pCreateInfo,
2641 const VkAllocationCallbacks* pAllocator,
2642 VkDevice* pDevice)
2643 {
2644 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
2645 VkResult result;
2646 struct radv_device *device;
2647
2648 bool keep_shader_info = false;
2649
2650 /* Check enabled features */
2651 if (pCreateInfo->pEnabledFeatures) {
2652 VkPhysicalDeviceFeatures supported_features;
2653 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
2654 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
2655 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
2656 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
2657 for (uint32_t i = 0; i < num_features; i++) {
2658 if (enabled_feature[i] && !supported_feature[i])
2659 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
2660 }
2661 }
2662
2663 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
2664 sizeof(*device), 8,
2665 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2666 if (!device)
2667 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2668
2669 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
2670 device->instance = physical_device->instance;
2671 device->physical_device = physical_device;
2672
2673 device->ws = physical_device->ws;
2674 if (pAllocator)
2675 device->alloc = *pAllocator;
2676 else
2677 device->alloc = physical_device->instance->alloc;
2678
2679 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
2680 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
2681 int index = radv_get_device_extension_index(ext_name);
2682 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
2683 vk_free(&device->alloc, device);
2684 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
2685 }
2686
2687 device->enabled_extensions.extensions[index] = true;
2688 }
2689
2690 keep_shader_info = device->enabled_extensions.AMD_shader_info;
2691
2692 /* With update after bind we can't attach bo's to the command buffer
2693 * from the descriptor set anymore, so we have to use a global BO list.
2694 */
2695 device->use_global_bo_list =
2696 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
2697 device->enabled_extensions.EXT_descriptor_indexing ||
2698 device->enabled_extensions.EXT_buffer_device_address ||
2699 device->enabled_extensions.KHR_buffer_device_address;
2700
2701 device->robust_buffer_access = pCreateInfo->pEnabledFeatures &&
2702 pCreateInfo->pEnabledFeatures->robustBufferAccess;
2703
2704 mtx_init(&device->shader_slab_mutex, mtx_plain);
2705 list_inithead(&device->shader_slabs);
2706
2707 radv_bo_list_init(&device->bo_list);
2708
2709 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
2710 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
2711 uint32_t qfi = queue_create->queueFamilyIndex;
2712 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
2713 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
2714
2715 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
2716
2717 device->queues[qfi] = vk_alloc(&device->alloc,
2718 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
2719 if (!device->queues[qfi]) {
2720 result = VK_ERROR_OUT_OF_HOST_MEMORY;
2721 goto fail;
2722 }
2723
2724 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
2725
2726 device->queue_count[qfi] = queue_create->queueCount;
2727
2728 for (unsigned q = 0; q < queue_create->queueCount; q++) {
2729 result = radv_queue_init(device, &device->queues[qfi][q],
2730 qfi, q, queue_create->flags,
2731 global_priority);
2732 if (result != VK_SUCCESS)
2733 goto fail;
2734 }
2735 }
2736
2737 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
2738 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
2739
2740 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2741 device->dfsm_allowed = device->pbb_allowed &&
2742 (device->instance->perftest_flags & RADV_PERFTEST_DFSM);
2743
2744 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
2745
2746 /* The maximum number of scratch waves. Scratch space isn't divided
2747 * evenly between CUs. The number is only a function of the number of CUs.
2748 * We can decrease the constant to decrease the scratch buffer size.
2749 *
2750 * sctx->scratch_waves must be >= the maximum possible size of
2751 * 1 threadgroup, so that the hw doesn't hang from being unable
2752 * to start any.
2753 *
2754 * The recommended value is 4 per CU at most. Higher numbers don't
2755 * bring much benefit, but they still occupy chip resources (think
2756 * async compute). I've seen ~2% performance difference between 4 and 32.
2757 */
2758 uint32_t max_threads_per_block = 2048;
2759 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
2760 max_threads_per_block / 64);
2761
2762 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
2763
2764 if (device->physical_device->rad_info.chip_class >= GFX7) {
2765 /* If the KMD allows it (there is a KMD hw register for it),
2766 * allow launching waves out-of-order.
2767 */
2768 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
2769 }
2770
2771 radv_device_init_gs_info(device);
2772
2773 device->tess_offchip_block_dw_size =
2774 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
2775
2776 if (getenv("RADV_TRACE_FILE")) {
2777 const char *filename = getenv("RADV_TRACE_FILE");
2778
2779 keep_shader_info = true;
2780
2781 if (!radv_init_trace(device))
2782 goto fail;
2783
2784 fprintf(stderr, "*****************************************************************************\n");
2785 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2786 fprintf(stderr, "*****************************************************************************\n");
2787
2788 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
2789 radv_dump_enabled_options(device, stderr);
2790 }
2791
2792 /* Temporarily disable secure compile while we create meta shaders, etc */
2793 uint8_t sc_threads = device->instance->num_sc_threads;
2794 if (sc_threads)
2795 device->instance->num_sc_threads = 0;
2796
2797 device->keep_shader_info = keep_shader_info;
2798 result = radv_device_init_meta(device);
2799 if (result != VK_SUCCESS)
2800 goto fail;
2801
2802 radv_device_init_msaa(device);
2803
2804 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
2805 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
2806 switch (family) {
2807 case RADV_QUEUE_GENERAL:
2808 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2809 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2810 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2811 break;
2812 case RADV_QUEUE_COMPUTE:
2813 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2814 radeon_emit(device->empty_cs[family], 0);
2815 break;
2816 }
2817 device->ws->cs_finalize(device->empty_cs[family]);
2818 }
2819
2820 if (device->physical_device->rad_info.chip_class >= GFX7)
2821 cik_create_gfx_config(device);
2822
2823 VkPipelineCacheCreateInfo ci;
2824 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2825 ci.pNext = NULL;
2826 ci.flags = 0;
2827 ci.pInitialData = NULL;
2828 ci.initialDataSize = 0;
2829 VkPipelineCache pc;
2830 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2831 &ci, NULL, &pc);
2832 if (result != VK_SUCCESS)
2833 goto fail_meta;
2834
2835 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2836
2837 result = radv_create_pthread_cond(&device->timeline_cond);
2838 if (result != VK_SUCCESS)
2839 goto fail_mem_cache;
2840
2841 device->force_aniso =
2842 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2843 if (device->force_aniso >= 0) {
2844 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2845 1 << util_logbase2(device->force_aniso));
2846 }
2847
2848 /* Fork device for secure compile as required */
2849 device->instance->num_sc_threads = sc_threads;
2850 if (radv_device_use_secure_compile(device->instance)) {
2851
2852 result = fork_secure_compile_idle_device(device);
2853 if (result != VK_SUCCESS)
2854 goto fail_meta;
2855 }
2856
2857 *pDevice = radv_device_to_handle(device);
2858 return VK_SUCCESS;
2859
2860 fail_mem_cache:
2861 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2862 fail_meta:
2863 radv_device_finish_meta(device);
2864 fail:
2865 radv_bo_list_finish(&device->bo_list);
2866
2867 if (device->trace_bo)
2868 device->ws->buffer_destroy(device->trace_bo);
2869
2870 if (device->gfx_init)
2871 device->ws->buffer_destroy(device->gfx_init);
2872
2873 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2874 for (unsigned q = 0; q < device->queue_count[i]; q++)
2875 radv_queue_finish(&device->queues[i][q]);
2876 if (device->queue_count[i])
2877 vk_free(&device->alloc, device->queues[i]);
2878 }
2879
2880 vk_free(&device->alloc, device);
2881 return result;
2882 }
2883
2884 void radv_DestroyDevice(
2885 VkDevice _device,
2886 const VkAllocationCallbacks* pAllocator)
2887 {
2888 RADV_FROM_HANDLE(radv_device, device, _device);
2889
2890 if (!device)
2891 return;
2892
2893 if (device->trace_bo)
2894 device->ws->buffer_destroy(device->trace_bo);
2895
2896 if (device->gfx_init)
2897 device->ws->buffer_destroy(device->gfx_init);
2898
2899 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2900 for (unsigned q = 0; q < device->queue_count[i]; q++)
2901 radv_queue_finish(&device->queues[i][q]);
2902 if (device->queue_count[i])
2903 vk_free(&device->alloc, device->queues[i]);
2904 if (device->empty_cs[i])
2905 device->ws->cs_destroy(device->empty_cs[i]);
2906 }
2907 radv_device_finish_meta(device);
2908
2909 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2910 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2911
2912 radv_destroy_shader_slabs(device);
2913
2914 pthread_cond_destroy(&device->timeline_cond);
2915 radv_bo_list_finish(&device->bo_list);
2916 if (radv_device_use_secure_compile(device->instance)) {
2917 for (unsigned i = 0; i < device->instance->num_sc_threads; i++ ) {
2918 destroy_secure_compile_device(device, i);
2919 }
2920 }
2921
2922 if (device->sc_state) {
2923 free(device->sc_state->uid);
2924 vk_free(&device->alloc, device->sc_state->secure_compile_processes);
2925 }
2926 vk_free(&device->alloc, device->sc_state);
2927 vk_free(&device->alloc, device);
2928 }
2929
2930 VkResult radv_EnumerateInstanceLayerProperties(
2931 uint32_t* pPropertyCount,
2932 VkLayerProperties* pProperties)
2933 {
2934 if (pProperties == NULL) {
2935 *pPropertyCount = 0;
2936 return VK_SUCCESS;
2937 }
2938
2939 /* None supported at this time */
2940 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2941 }
2942
2943 VkResult radv_EnumerateDeviceLayerProperties(
2944 VkPhysicalDevice physicalDevice,
2945 uint32_t* pPropertyCount,
2946 VkLayerProperties* pProperties)
2947 {
2948 if (pProperties == NULL) {
2949 *pPropertyCount = 0;
2950 return VK_SUCCESS;
2951 }
2952
2953 /* None supported at this time */
2954 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2955 }
2956
2957 void radv_GetDeviceQueue2(
2958 VkDevice _device,
2959 const VkDeviceQueueInfo2* pQueueInfo,
2960 VkQueue* pQueue)
2961 {
2962 RADV_FROM_HANDLE(radv_device, device, _device);
2963 struct radv_queue *queue;
2964
2965 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2966 if (pQueueInfo->flags != queue->flags) {
2967 /* From the Vulkan 1.1.70 spec:
2968 *
2969 * "The queue returned by vkGetDeviceQueue2 must have the same
2970 * flags value from this structure as that used at device
2971 * creation time in a VkDeviceQueueCreateInfo instance. If no
2972 * matching flags were specified at device creation time then
2973 * pQueue will return VK_NULL_HANDLE."
2974 */
2975 *pQueue = VK_NULL_HANDLE;
2976 return;
2977 }
2978
2979 *pQueue = radv_queue_to_handle(queue);
2980 }
2981
2982 void radv_GetDeviceQueue(
2983 VkDevice _device,
2984 uint32_t queueFamilyIndex,
2985 uint32_t queueIndex,
2986 VkQueue* pQueue)
2987 {
2988 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2989 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2990 .queueFamilyIndex = queueFamilyIndex,
2991 .queueIndex = queueIndex
2992 };
2993
2994 radv_GetDeviceQueue2(_device, &info, pQueue);
2995 }
2996
2997 static void
2998 fill_geom_tess_rings(struct radv_queue *queue,
2999 uint32_t *map,
3000 bool add_sample_positions,
3001 uint32_t esgs_ring_size,
3002 struct radeon_winsys_bo *esgs_ring_bo,
3003 uint32_t gsvs_ring_size,
3004 struct radeon_winsys_bo *gsvs_ring_bo,
3005 uint32_t tess_factor_ring_size,
3006 uint32_t tess_offchip_ring_offset,
3007 uint32_t tess_offchip_ring_size,
3008 struct radeon_winsys_bo *tess_rings_bo)
3009 {
3010 uint32_t *desc = &map[4];
3011
3012 if (esgs_ring_bo) {
3013 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
3014
3015 /* stride 0, num records - size, add tid, swizzle, elsize4,
3016 index stride 64 */
3017 desc[0] = esgs_va;
3018 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
3019 S_008F04_SWIZZLE_ENABLE(true);
3020 desc[2] = esgs_ring_size;
3021 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3022 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3023 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3024 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3025 S_008F0C_INDEX_STRIDE(3) |
3026 S_008F0C_ADD_TID_ENABLE(1);
3027
3028 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3029 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3030 S_008F0C_OOB_SELECT(2) |
3031 S_008F0C_RESOURCE_LEVEL(1);
3032 } else {
3033 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3034 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3035 S_008F0C_ELEMENT_SIZE(1);
3036 }
3037
3038 /* GS entry for ES->GS ring */
3039 /* stride 0, num records - size, elsize0,
3040 index stride 0 */
3041 desc[4] = esgs_va;
3042 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
3043 desc[6] = esgs_ring_size;
3044 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3045 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3046 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3047 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3048
3049 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3050 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3051 S_008F0C_OOB_SELECT(2) |
3052 S_008F0C_RESOURCE_LEVEL(1);
3053 } else {
3054 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3055 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3056 }
3057 }
3058
3059 desc += 8;
3060
3061 if (gsvs_ring_bo) {
3062 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
3063
3064 /* VS entry for GS->VS ring */
3065 /* stride 0, num records - size, elsize0,
3066 index stride 0 */
3067 desc[0] = gsvs_va;
3068 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
3069 desc[2] = gsvs_ring_size;
3070 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3071 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3072 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3073 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3074
3075 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3076 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3077 S_008F0C_OOB_SELECT(2) |
3078 S_008F0C_RESOURCE_LEVEL(1);
3079 } else {
3080 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3081 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3082 }
3083
3084 /* stride gsvs_itemsize, num records 64
3085 elsize 4, index stride 16 */
3086 /* shader will patch stride and desc[2] */
3087 desc[4] = gsvs_va;
3088 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
3089 S_008F04_SWIZZLE_ENABLE(1);
3090 desc[6] = 0;
3091 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3092 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3093 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3094 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
3095 S_008F0C_INDEX_STRIDE(1) |
3096 S_008F0C_ADD_TID_ENABLE(true);
3097
3098 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3099 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3100 S_008F0C_OOB_SELECT(2) |
3101 S_008F0C_RESOURCE_LEVEL(1);
3102 } else {
3103 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3104 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
3105 S_008F0C_ELEMENT_SIZE(1);
3106 }
3107
3108 }
3109
3110 desc += 8;
3111
3112 if (tess_rings_bo) {
3113 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
3114 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
3115
3116 desc[0] = tess_va;
3117 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
3118 desc[2] = tess_factor_ring_size;
3119 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3120 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3121 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3122 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3123
3124 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3125 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3126 S_008F0C_OOB_SELECT(3) |
3127 S_008F0C_RESOURCE_LEVEL(1);
3128 } else {
3129 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3130 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3131 }
3132
3133 desc[4] = tess_offchip_va;
3134 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
3135 desc[6] = tess_offchip_ring_size;
3136 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
3137 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
3138 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
3139 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
3140
3141 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3142 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
3143 S_008F0C_OOB_SELECT(3) |
3144 S_008F0C_RESOURCE_LEVEL(1);
3145 } else {
3146 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
3147 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
3148 }
3149 }
3150
3151 desc += 8;
3152
3153 if (add_sample_positions) {
3154 /* add sample positions after all rings */
3155 memcpy(desc, queue->device->sample_locations_1x, 8);
3156 desc += 2;
3157 memcpy(desc, queue->device->sample_locations_2x, 16);
3158 desc += 4;
3159 memcpy(desc, queue->device->sample_locations_4x, 32);
3160 desc += 8;
3161 memcpy(desc, queue->device->sample_locations_8x, 64);
3162 }
3163 }
3164
3165 static unsigned
3166 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
3167 {
3168 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
3169 device->physical_device->rad_info.family != CHIP_CARRIZO &&
3170 device->physical_device->rad_info.family != CHIP_STONEY;
3171 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
3172 unsigned max_offchip_buffers;
3173 unsigned offchip_granularity;
3174 unsigned hs_offchip_param;
3175
3176 /*
3177 * Per RadeonSI:
3178 * This must be one less than the maximum number due to a hw limitation.
3179 * Various hardware bugs need thGFX7
3180 *
3181 * Per AMDVLK:
3182 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
3183 * Gfx7 should limit max_offchip_buffers to 508
3184 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
3185 *
3186 * Follow AMDVLK here.
3187 */
3188 if (device->physical_device->rad_info.chip_class >= GFX10) {
3189 max_offchip_buffers_per_se = 256;
3190 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
3191 device->physical_device->rad_info.chip_class == GFX7 ||
3192 device->physical_device->rad_info.chip_class == GFX6)
3193 --max_offchip_buffers_per_se;
3194
3195 max_offchip_buffers = max_offchip_buffers_per_se *
3196 device->physical_device->rad_info.max_se;
3197
3198 /* Hawaii has a bug with offchip buffers > 256 that can be worked
3199 * around by setting 4K granularity.
3200 */
3201 if (device->tess_offchip_block_dw_size == 4096) {
3202 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
3203 offchip_granularity = V_03093C_X_4K_DWORDS;
3204 } else {
3205 assert(device->tess_offchip_block_dw_size == 8192);
3206 offchip_granularity = V_03093C_X_8K_DWORDS;
3207 }
3208
3209 switch (device->physical_device->rad_info.chip_class) {
3210 case GFX6:
3211 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
3212 break;
3213 case GFX7:
3214 case GFX8:
3215 case GFX9:
3216 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
3217 break;
3218 case GFX10:
3219 break;
3220 default:
3221 break;
3222 }
3223
3224 *max_offchip_buffers_p = max_offchip_buffers;
3225 if (device->physical_device->rad_info.chip_class >= GFX7) {
3226 if (device->physical_device->rad_info.chip_class >= GFX8)
3227 --max_offchip_buffers;
3228 hs_offchip_param =
3229 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
3230 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
3231 } else {
3232 hs_offchip_param =
3233 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
3234 }
3235 return hs_offchip_param;
3236 }
3237
3238 static void
3239 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3240 struct radeon_winsys_bo *esgs_ring_bo,
3241 uint32_t esgs_ring_size,
3242 struct radeon_winsys_bo *gsvs_ring_bo,
3243 uint32_t gsvs_ring_size)
3244 {
3245 if (!esgs_ring_bo && !gsvs_ring_bo)
3246 return;
3247
3248 if (esgs_ring_bo)
3249 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
3250
3251 if (gsvs_ring_bo)
3252 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
3253
3254 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3255 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
3256 radeon_emit(cs, esgs_ring_size >> 8);
3257 radeon_emit(cs, gsvs_ring_size >> 8);
3258 } else {
3259 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
3260 radeon_emit(cs, esgs_ring_size >> 8);
3261 radeon_emit(cs, gsvs_ring_size >> 8);
3262 }
3263 }
3264
3265 static void
3266 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3267 unsigned hs_offchip_param, unsigned tf_ring_size,
3268 struct radeon_winsys_bo *tess_rings_bo)
3269 {
3270 uint64_t tf_va;
3271
3272 if (!tess_rings_bo)
3273 return;
3274
3275 tf_va = radv_buffer_get_va(tess_rings_bo);
3276
3277 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
3278
3279 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
3280 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3281 S_030938_SIZE(tf_ring_size / 4));
3282 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
3283 tf_va >> 8);
3284
3285 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3286 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3287 S_030984_BASE_HI(tf_va >> 40));
3288 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3289 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3290 S_030944_BASE_HI(tf_va >> 40));
3291 }
3292 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3293 hs_offchip_param);
3294 } else {
3295 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
3296 S_008988_SIZE(tf_ring_size / 4));
3297 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
3298 tf_va >> 8);
3299 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3300 hs_offchip_param);
3301 }
3302 }
3303
3304 static void
3305 radv_emit_graphics_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3306 uint32_t size_per_wave, uint32_t waves,
3307 struct radeon_winsys_bo *scratch_bo)
3308 {
3309 if (queue->queue_family_index != RADV_QUEUE_GENERAL)
3310 return;
3311
3312 if (!scratch_bo)
3313 return;
3314
3315 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3316
3317 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
3318 S_0286E8_WAVES(waves) |
3319 S_0286E8_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3320 }
3321
3322 static void
3323 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
3324 uint32_t size_per_wave, uint32_t waves,
3325 struct radeon_winsys_bo *compute_scratch_bo)
3326 {
3327 uint64_t scratch_va;
3328
3329 if (!compute_scratch_bo)
3330 return;
3331
3332 scratch_va = radv_buffer_get_va(compute_scratch_bo);
3333
3334 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
3335
3336 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
3337 radeon_emit(cs, scratch_va);
3338 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3339 S_008F04_SWIZZLE_ENABLE(1));
3340
3341 radeon_set_sh_reg(cs, R_00B860_COMPUTE_TMPRING_SIZE,
3342 S_00B860_WAVES(waves) |
3343 S_00B860_WAVESIZE(round_up_u32(size_per_wave, 1024)));
3344 }
3345
3346 static void
3347 radv_emit_global_shader_pointers(struct radv_queue *queue,
3348 struct radeon_cmdbuf *cs,
3349 struct radeon_winsys_bo *descriptor_bo)
3350 {
3351 uint64_t va;
3352
3353 if (!descriptor_bo)
3354 return;
3355
3356 va = radv_buffer_get_va(descriptor_bo);
3357
3358 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
3359
3360 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
3361 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3362 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3363 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3364 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3365
3366 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3367 radv_emit_shader_pointer(queue->device, cs, regs[i],
3368 va, true);
3369 }
3370 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
3371 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3372 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3373 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
3374 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
3375
3376 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3377 radv_emit_shader_pointer(queue->device, cs, regs[i],
3378 va, true);
3379 }
3380 } else {
3381 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
3382 R_00B130_SPI_SHADER_USER_DATA_VS_0,
3383 R_00B230_SPI_SHADER_USER_DATA_GS_0,
3384 R_00B330_SPI_SHADER_USER_DATA_ES_0,
3385 R_00B430_SPI_SHADER_USER_DATA_HS_0,
3386 R_00B530_SPI_SHADER_USER_DATA_LS_0};
3387
3388 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
3389 radv_emit_shader_pointer(queue->device, cs, regs[i],
3390 va, true);
3391 }
3392 }
3393 }
3394
3395 static void
3396 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3397 {
3398 struct radv_device *device = queue->device;
3399
3400 if (device->gfx_init) {
3401 uint64_t va = radv_buffer_get_va(device->gfx_init);
3402
3403 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
3404 radeon_emit(cs, va);
3405 radeon_emit(cs, va >> 32);
3406 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
3407
3408 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
3409 } else {
3410 struct radv_physical_device *physical_device = device->physical_device;
3411 si_emit_graphics(physical_device, cs);
3412 }
3413 }
3414
3415 static void
3416 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
3417 {
3418 struct radv_physical_device *physical_device = queue->device->physical_device;
3419 si_emit_compute(physical_device, cs);
3420 }
3421
3422 static VkResult
3423 radv_get_preamble_cs(struct radv_queue *queue,
3424 uint32_t scratch_size_per_wave,
3425 uint32_t scratch_waves,
3426 uint32_t compute_scratch_size_per_wave,
3427 uint32_t compute_scratch_waves,
3428 uint32_t esgs_ring_size,
3429 uint32_t gsvs_ring_size,
3430 bool needs_tess_rings,
3431 bool needs_gds,
3432 bool needs_sample_positions,
3433 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
3434 struct radeon_cmdbuf **initial_preamble_cs,
3435 struct radeon_cmdbuf **continue_preamble_cs)
3436 {
3437 struct radeon_winsys_bo *scratch_bo = NULL;
3438 struct radeon_winsys_bo *descriptor_bo = NULL;
3439 struct radeon_winsys_bo *compute_scratch_bo = NULL;
3440 struct radeon_winsys_bo *esgs_ring_bo = NULL;
3441 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
3442 struct radeon_winsys_bo *tess_rings_bo = NULL;
3443 struct radeon_winsys_bo *gds_bo = NULL;
3444 struct radeon_winsys_bo *gds_oa_bo = NULL;
3445 struct radeon_cmdbuf *dest_cs[3] = {0};
3446 bool add_tess_rings = false, add_gds = false, add_sample_positions = false;
3447 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
3448 unsigned max_offchip_buffers;
3449 unsigned hs_offchip_param = 0;
3450 unsigned tess_offchip_ring_offset;
3451 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
3452 if (!queue->has_tess_rings) {
3453 if (needs_tess_rings)
3454 add_tess_rings = true;
3455 }
3456 if (!queue->has_gds) {
3457 if (needs_gds)
3458 add_gds = true;
3459 }
3460 if (!queue->has_sample_positions) {
3461 if (needs_sample_positions)
3462 add_sample_positions = true;
3463 }
3464 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
3465 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
3466 &max_offchip_buffers);
3467 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
3468 tess_offchip_ring_size = max_offchip_buffers *
3469 queue->device->tess_offchip_block_dw_size * 4;
3470
3471 scratch_size_per_wave = MAX2(scratch_size_per_wave, queue->scratch_size_per_wave);
3472 if (scratch_size_per_wave)
3473 scratch_waves = MIN2(scratch_waves, UINT32_MAX / scratch_size_per_wave);
3474 else
3475 scratch_waves = 0;
3476
3477 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave, queue->compute_scratch_size_per_wave);
3478 if (compute_scratch_size_per_wave)
3479 compute_scratch_waves = MIN2(compute_scratch_waves, UINT32_MAX / compute_scratch_size_per_wave);
3480 else
3481 compute_scratch_waves = 0;
3482
3483 if (scratch_size_per_wave <= queue->scratch_size_per_wave &&
3484 scratch_waves <= queue->scratch_waves &&
3485 compute_scratch_size_per_wave <= queue->compute_scratch_size_per_wave &&
3486 compute_scratch_waves <= queue->compute_scratch_waves &&
3487 esgs_ring_size <= queue->esgs_ring_size &&
3488 gsvs_ring_size <= queue->gsvs_ring_size &&
3489 !add_tess_rings && !add_gds && !add_sample_positions &&
3490 queue->initial_preamble_cs) {
3491 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3492 *initial_preamble_cs = queue->initial_preamble_cs;
3493 *continue_preamble_cs = queue->continue_preamble_cs;
3494 if (!scratch_size_per_wave && !compute_scratch_size_per_wave &&
3495 !esgs_ring_size && !gsvs_ring_size && !needs_tess_rings &&
3496 !needs_gds && !needs_sample_positions)
3497 *continue_preamble_cs = NULL;
3498 return VK_SUCCESS;
3499 }
3500
3501 uint32_t scratch_size = scratch_size_per_wave * scratch_waves;
3502 uint32_t queue_scratch_size = queue->scratch_size_per_wave * queue->scratch_waves;
3503 if (scratch_size > queue_scratch_size) {
3504 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3505 scratch_size,
3506 4096,
3507 RADEON_DOMAIN_VRAM,
3508 ring_bo_flags,
3509 RADV_BO_PRIORITY_SCRATCH);
3510 if (!scratch_bo)
3511 goto fail;
3512 } else
3513 scratch_bo = queue->scratch_bo;
3514
3515 uint32_t compute_scratch_size = compute_scratch_size_per_wave * compute_scratch_waves;
3516 uint32_t compute_queue_scratch_size = queue->compute_scratch_size_per_wave * queue->compute_scratch_waves;
3517 if (compute_scratch_size > compute_queue_scratch_size) {
3518 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
3519 compute_scratch_size,
3520 4096,
3521 RADEON_DOMAIN_VRAM,
3522 ring_bo_flags,
3523 RADV_BO_PRIORITY_SCRATCH);
3524 if (!compute_scratch_bo)
3525 goto fail;
3526
3527 } else
3528 compute_scratch_bo = queue->compute_scratch_bo;
3529
3530 if (esgs_ring_size > queue->esgs_ring_size) {
3531 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3532 esgs_ring_size,
3533 4096,
3534 RADEON_DOMAIN_VRAM,
3535 ring_bo_flags,
3536 RADV_BO_PRIORITY_SCRATCH);
3537 if (!esgs_ring_bo)
3538 goto fail;
3539 } else {
3540 esgs_ring_bo = queue->esgs_ring_bo;
3541 esgs_ring_size = queue->esgs_ring_size;
3542 }
3543
3544 if (gsvs_ring_size > queue->gsvs_ring_size) {
3545 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
3546 gsvs_ring_size,
3547 4096,
3548 RADEON_DOMAIN_VRAM,
3549 ring_bo_flags,
3550 RADV_BO_PRIORITY_SCRATCH);
3551 if (!gsvs_ring_bo)
3552 goto fail;
3553 } else {
3554 gsvs_ring_bo = queue->gsvs_ring_bo;
3555 gsvs_ring_size = queue->gsvs_ring_size;
3556 }
3557
3558 if (add_tess_rings) {
3559 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
3560 tess_offchip_ring_offset + tess_offchip_ring_size,
3561 256,
3562 RADEON_DOMAIN_VRAM,
3563 ring_bo_flags,
3564 RADV_BO_PRIORITY_SCRATCH);
3565 if (!tess_rings_bo)
3566 goto fail;
3567 } else {
3568 tess_rings_bo = queue->tess_rings_bo;
3569 }
3570
3571 if (add_gds) {
3572 assert(queue->device->physical_device->rad_info.chip_class >= GFX10);
3573
3574 /* 4 streamout GDS counters.
3575 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3576 */
3577 gds_bo = queue->device->ws->buffer_create(queue->device->ws,
3578 256, 4,
3579 RADEON_DOMAIN_GDS,
3580 ring_bo_flags,
3581 RADV_BO_PRIORITY_SCRATCH);
3582 if (!gds_bo)
3583 goto fail;
3584
3585 gds_oa_bo = queue->device->ws->buffer_create(queue->device->ws,
3586 4, 1,
3587 RADEON_DOMAIN_OA,
3588 ring_bo_flags,
3589 RADV_BO_PRIORITY_SCRATCH);
3590 if (!gds_oa_bo)
3591 goto fail;
3592 } else {
3593 gds_bo = queue->gds_bo;
3594 gds_oa_bo = queue->gds_oa_bo;
3595 }
3596
3597 if (scratch_bo != queue->scratch_bo ||
3598 esgs_ring_bo != queue->esgs_ring_bo ||
3599 gsvs_ring_bo != queue->gsvs_ring_bo ||
3600 tess_rings_bo != queue->tess_rings_bo ||
3601 add_sample_positions) {
3602 uint32_t size = 0;
3603 if (gsvs_ring_bo || esgs_ring_bo ||
3604 tess_rings_bo || add_sample_positions) {
3605 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
3606 if (add_sample_positions)
3607 size += 128; /* 64+32+16+8 = 120 bytes */
3608 }
3609 else if (scratch_bo)
3610 size = 8; /* 2 dword */
3611
3612 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
3613 size,
3614 4096,
3615 RADEON_DOMAIN_VRAM,
3616 RADEON_FLAG_CPU_ACCESS |
3617 RADEON_FLAG_NO_INTERPROCESS_SHARING |
3618 RADEON_FLAG_READ_ONLY,
3619 RADV_BO_PRIORITY_DESCRIPTOR);
3620 if (!descriptor_bo)
3621 goto fail;
3622 } else
3623 descriptor_bo = queue->descriptor_bo;
3624
3625 if (descriptor_bo != queue->descriptor_bo) {
3626 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
3627
3628 if (scratch_bo) {
3629 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
3630 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
3631 S_008F04_SWIZZLE_ENABLE(1);
3632 map[0] = scratch_va;
3633 map[1] = rsrc1;
3634 }
3635
3636 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
3637 fill_geom_tess_rings(queue, map, add_sample_positions,
3638 esgs_ring_size, esgs_ring_bo,
3639 gsvs_ring_size, gsvs_ring_bo,
3640 tess_factor_ring_size,
3641 tess_offchip_ring_offset,
3642 tess_offchip_ring_size,
3643 tess_rings_bo);
3644
3645 queue->device->ws->buffer_unmap(descriptor_bo);
3646 }
3647
3648 for(int i = 0; i < 3; ++i) {
3649 struct radeon_cmdbuf *cs = NULL;
3650 cs = queue->device->ws->cs_create(queue->device->ws,
3651 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
3652 if (!cs)
3653 goto fail;
3654
3655 dest_cs[i] = cs;
3656
3657 if (scratch_bo)
3658 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
3659
3660 /* Emit initial configuration. */
3661 switch (queue->queue_family_index) {
3662 case RADV_QUEUE_GENERAL:
3663 radv_init_graphics_state(cs, queue);
3664 break;
3665 case RADV_QUEUE_COMPUTE:
3666 radv_init_compute_state(cs, queue);
3667 break;
3668 case RADV_QUEUE_TRANSFER:
3669 break;
3670 }
3671
3672 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
3673 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3674 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3675
3676 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3677 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3678 }
3679
3680 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
3681 gsvs_ring_bo, gsvs_ring_size);
3682 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
3683 tess_factor_ring_size, tess_rings_bo);
3684 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
3685 radv_emit_compute_scratch(queue, cs, compute_scratch_size_per_wave,
3686 compute_scratch_waves, compute_scratch_bo);
3687 radv_emit_graphics_scratch(queue, cs, scratch_size_per_wave,
3688 scratch_waves, scratch_bo);
3689
3690 if (gds_bo)
3691 radv_cs_add_buffer(queue->device->ws, cs, gds_bo);
3692 if (gds_oa_bo)
3693 radv_cs_add_buffer(queue->device->ws, cs, gds_oa_bo);
3694
3695 if (i == 0) {
3696 si_cs_emit_cache_flush(cs,
3697 queue->device->physical_device->rad_info.chip_class,
3698 NULL, 0,
3699 queue->queue_family_index == RING_COMPUTE &&
3700 queue->device->physical_device->rad_info.chip_class >= GFX7,
3701 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
3702 RADV_CMD_FLAG_INV_ICACHE |
3703 RADV_CMD_FLAG_INV_SCACHE |
3704 RADV_CMD_FLAG_INV_VCACHE |
3705 RADV_CMD_FLAG_INV_L2 |
3706 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3707 } else if (i == 1) {
3708 si_cs_emit_cache_flush(cs,
3709 queue->device->physical_device->rad_info.chip_class,
3710 NULL, 0,
3711 queue->queue_family_index == RING_COMPUTE &&
3712 queue->device->physical_device->rad_info.chip_class >= GFX7,
3713 RADV_CMD_FLAG_INV_ICACHE |
3714 RADV_CMD_FLAG_INV_SCACHE |
3715 RADV_CMD_FLAG_INV_VCACHE |
3716 RADV_CMD_FLAG_INV_L2 |
3717 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
3718 }
3719
3720 if (!queue->device->ws->cs_finalize(cs))
3721 goto fail;
3722 }
3723
3724 if (queue->initial_full_flush_preamble_cs)
3725 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
3726
3727 if (queue->initial_preamble_cs)
3728 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
3729
3730 if (queue->continue_preamble_cs)
3731 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
3732
3733 queue->initial_full_flush_preamble_cs = dest_cs[0];
3734 queue->initial_preamble_cs = dest_cs[1];
3735 queue->continue_preamble_cs = dest_cs[2];
3736
3737 if (scratch_bo != queue->scratch_bo) {
3738 if (queue->scratch_bo)
3739 queue->device->ws->buffer_destroy(queue->scratch_bo);
3740 queue->scratch_bo = scratch_bo;
3741 }
3742 queue->scratch_size_per_wave = scratch_size_per_wave;
3743 queue->scratch_waves = scratch_waves;
3744
3745 if (compute_scratch_bo != queue->compute_scratch_bo) {
3746 if (queue->compute_scratch_bo)
3747 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
3748 queue->compute_scratch_bo = compute_scratch_bo;
3749 }
3750 queue->compute_scratch_size_per_wave = compute_scratch_size_per_wave;
3751 queue->compute_scratch_waves = compute_scratch_waves;
3752
3753 if (esgs_ring_bo != queue->esgs_ring_bo) {
3754 if (queue->esgs_ring_bo)
3755 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
3756 queue->esgs_ring_bo = esgs_ring_bo;
3757 queue->esgs_ring_size = esgs_ring_size;
3758 }
3759
3760 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
3761 if (queue->gsvs_ring_bo)
3762 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
3763 queue->gsvs_ring_bo = gsvs_ring_bo;
3764 queue->gsvs_ring_size = gsvs_ring_size;
3765 }
3766
3767 if (tess_rings_bo != queue->tess_rings_bo) {
3768 queue->tess_rings_bo = tess_rings_bo;
3769 queue->has_tess_rings = true;
3770 }
3771
3772 if (gds_bo != queue->gds_bo) {
3773 queue->gds_bo = gds_bo;
3774 queue->has_gds = true;
3775 }
3776
3777 if (gds_oa_bo != queue->gds_oa_bo)
3778 queue->gds_oa_bo = gds_oa_bo;
3779
3780 if (descriptor_bo != queue->descriptor_bo) {
3781 if (queue->descriptor_bo)
3782 queue->device->ws->buffer_destroy(queue->descriptor_bo);
3783
3784 queue->descriptor_bo = descriptor_bo;
3785 }
3786
3787 if (add_sample_positions)
3788 queue->has_sample_positions = true;
3789
3790 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
3791 *initial_preamble_cs = queue->initial_preamble_cs;
3792 *continue_preamble_cs = queue->continue_preamble_cs;
3793 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
3794 *continue_preamble_cs = NULL;
3795 return VK_SUCCESS;
3796 fail:
3797 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
3798 if (dest_cs[i])
3799 queue->device->ws->cs_destroy(dest_cs[i]);
3800 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
3801 queue->device->ws->buffer_destroy(descriptor_bo);
3802 if (scratch_bo && scratch_bo != queue->scratch_bo)
3803 queue->device->ws->buffer_destroy(scratch_bo);
3804 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
3805 queue->device->ws->buffer_destroy(compute_scratch_bo);
3806 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
3807 queue->device->ws->buffer_destroy(esgs_ring_bo);
3808 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
3809 queue->device->ws->buffer_destroy(gsvs_ring_bo);
3810 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
3811 queue->device->ws->buffer_destroy(tess_rings_bo);
3812 if (gds_bo && gds_bo != queue->gds_bo)
3813 queue->device->ws->buffer_destroy(gds_bo);
3814 if (gds_oa_bo && gds_oa_bo != queue->gds_oa_bo)
3815 queue->device->ws->buffer_destroy(gds_oa_bo);
3816
3817 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3818 }
3819
3820 static VkResult radv_alloc_sem_counts(struct radv_device *device,
3821 struct radv_winsys_sem_counts *counts,
3822 int num_sems,
3823 struct radv_semaphore_part **sems,
3824 const uint64_t *timeline_values,
3825 VkFence _fence,
3826 bool is_signal)
3827 {
3828 int syncobj_idx = 0, sem_idx = 0;
3829
3830 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
3831 return VK_SUCCESS;
3832
3833 for (uint32_t i = 0; i < num_sems; i++) {
3834 switch(sems[i]->kind) {
3835 case RADV_SEMAPHORE_SYNCOBJ:
3836 counts->syncobj_count++;
3837 break;
3838 case RADV_SEMAPHORE_WINSYS:
3839 counts->sem_count++;
3840 break;
3841 case RADV_SEMAPHORE_NONE:
3842 break;
3843 case RADV_SEMAPHORE_TIMELINE:
3844 counts->syncobj_count++;
3845 break;
3846 }
3847 }
3848
3849 if (_fence != VK_NULL_HANDLE) {
3850 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3851 if (fence->temp_syncobj || fence->syncobj)
3852 counts->syncobj_count++;
3853 }
3854
3855 if (counts->syncobj_count) {
3856 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
3857 if (!counts->syncobj)
3858 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3859 }
3860
3861 if (counts->sem_count) {
3862 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
3863 if (!counts->sem) {
3864 free(counts->syncobj);
3865 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3866 }
3867 }
3868
3869 for (uint32_t i = 0; i < num_sems; i++) {
3870 switch(sems[i]->kind) {
3871 case RADV_SEMAPHORE_NONE:
3872 unreachable("Empty semaphore");
3873 break;
3874 case RADV_SEMAPHORE_SYNCOBJ:
3875 counts->syncobj[syncobj_idx++] = sems[i]->syncobj;
3876 break;
3877 case RADV_SEMAPHORE_WINSYS:
3878 counts->sem[sem_idx++] = sems[i]->ws_sem;
3879 break;
3880 case RADV_SEMAPHORE_TIMELINE: {
3881 pthread_mutex_lock(&sems[i]->timeline.mutex);
3882 struct radv_timeline_point *point = NULL;
3883 if (is_signal) {
3884 point = radv_timeline_add_point_locked(device, &sems[i]->timeline, timeline_values[i]);
3885 } else {
3886 point = radv_timeline_find_point_at_least_locked(device, &sems[i]->timeline, timeline_values[i]);
3887 }
3888
3889 pthread_mutex_unlock(&sems[i]->timeline.mutex);
3890
3891 if (point) {
3892 counts->syncobj[syncobj_idx++] = point->syncobj;
3893 } else {
3894 /* Explicitly remove the semaphore so we might not find
3895 * a point later post-submit. */
3896 sems[i] = NULL;
3897 }
3898 break;
3899 }
3900 }
3901 }
3902
3903 if (_fence != VK_NULL_HANDLE) {
3904 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3905 if (fence->temp_syncobj)
3906 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
3907 else if (fence->syncobj)
3908 counts->syncobj[syncobj_idx++] = fence->syncobj;
3909 }
3910
3911 assert(syncobj_idx <= counts->syncobj_count);
3912 counts->syncobj_count = syncobj_idx;
3913
3914 return VK_SUCCESS;
3915 }
3916
3917 static void
3918 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
3919 {
3920 free(sem_info->wait.syncobj);
3921 free(sem_info->wait.sem);
3922 free(sem_info->signal.syncobj);
3923 free(sem_info->signal.sem);
3924 }
3925
3926
3927 static void radv_free_temp_syncobjs(struct radv_device *device,
3928 int num_sems,
3929 struct radv_semaphore_part *sems)
3930 {
3931 for (uint32_t i = 0; i < num_sems; i++) {
3932 radv_destroy_semaphore_part(device, sems + i);
3933 }
3934 }
3935
3936 static VkResult
3937 radv_alloc_sem_info(struct radv_device *device,
3938 struct radv_winsys_sem_info *sem_info,
3939 int num_wait_sems,
3940 struct radv_semaphore_part **wait_sems,
3941 const uint64_t *wait_values,
3942 int num_signal_sems,
3943 struct radv_semaphore_part **signal_sems,
3944 const uint64_t *signal_values,
3945 VkFence fence)
3946 {
3947 VkResult ret;
3948 memset(sem_info, 0, sizeof(*sem_info));
3949
3950 ret = radv_alloc_sem_counts(device, &sem_info->wait, num_wait_sems, wait_sems, wait_values, VK_NULL_HANDLE, false);
3951 if (ret)
3952 return ret;
3953 ret = radv_alloc_sem_counts(device, &sem_info->signal, num_signal_sems, signal_sems, signal_values, fence, true);
3954 if (ret)
3955 radv_free_sem_info(sem_info);
3956
3957 /* caller can override these */
3958 sem_info->cs_emit_wait = true;
3959 sem_info->cs_emit_signal = true;
3960 return ret;
3961 }
3962
3963 static void
3964 radv_finalize_timelines(struct radv_device *device,
3965 uint32_t num_wait_sems,
3966 struct radv_semaphore_part **wait_sems,
3967 const uint64_t *wait_values,
3968 uint32_t num_signal_sems,
3969 struct radv_semaphore_part **signal_sems,
3970 const uint64_t *signal_values,
3971 struct list_head *processing_list)
3972 {
3973 for (uint32_t i = 0; i < num_wait_sems; ++i) {
3974 if (wait_sems[i] && wait_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3975 pthread_mutex_lock(&wait_sems[i]->timeline.mutex);
3976 struct radv_timeline_point *point =
3977 radv_timeline_find_point_at_least_locked(device, &wait_sems[i]->timeline, wait_values[i]);
3978 point->wait_count -= 2;
3979 pthread_mutex_unlock(&wait_sems[i]->timeline.mutex);
3980 }
3981 }
3982 for (uint32_t i = 0; i < num_signal_sems; ++i) {
3983 if (signal_sems[i] && signal_sems[i]->kind == RADV_SEMAPHORE_TIMELINE) {
3984 pthread_mutex_lock(&signal_sems[i]->timeline.mutex);
3985 struct radv_timeline_point *point =
3986 radv_timeline_find_point_at_least_locked(device, &signal_sems[i]->timeline, signal_values[i]);
3987 signal_sems[i]->timeline.highest_submitted =
3988 MAX2(signal_sems[i]->timeline.highest_submitted, point->value);
3989 point->wait_count -= 2;
3990 radv_timeline_trigger_waiters_locked(&signal_sems[i]->timeline, processing_list);
3991 pthread_mutex_unlock(&signal_sems[i]->timeline.mutex);
3992 }
3993 }
3994 }
3995
3996 static void
3997 radv_sparse_buffer_bind_memory(struct radv_device *device,
3998 const VkSparseBufferMemoryBindInfo *bind)
3999 {
4000 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
4001
4002 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4003 struct radv_device_memory *mem = NULL;
4004
4005 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4006 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4007
4008 device->ws->buffer_virtual_bind(buffer->bo,
4009 bind->pBinds[i].resourceOffset,
4010 bind->pBinds[i].size,
4011 mem ? mem->bo : NULL,
4012 bind->pBinds[i].memoryOffset);
4013 }
4014 }
4015
4016 static void
4017 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
4018 const VkSparseImageOpaqueMemoryBindInfo *bind)
4019 {
4020 RADV_FROM_HANDLE(radv_image, image, bind->image);
4021
4022 for (uint32_t i = 0; i < bind->bindCount; ++i) {
4023 struct radv_device_memory *mem = NULL;
4024
4025 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
4026 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
4027
4028 device->ws->buffer_virtual_bind(image->bo,
4029 bind->pBinds[i].resourceOffset,
4030 bind->pBinds[i].size,
4031 mem ? mem->bo : NULL,
4032 bind->pBinds[i].memoryOffset);
4033 }
4034 }
4035
4036 static VkResult
4037 radv_get_preambles(struct radv_queue *queue,
4038 const VkCommandBuffer *cmd_buffers,
4039 uint32_t cmd_buffer_count,
4040 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
4041 struct radeon_cmdbuf **initial_preamble_cs,
4042 struct radeon_cmdbuf **continue_preamble_cs)
4043 {
4044 uint32_t scratch_size_per_wave = 0, waves_wanted = 0;
4045 uint32_t compute_scratch_size_per_wave = 0, compute_waves_wanted = 0;
4046 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
4047 bool tess_rings_needed = false;
4048 bool gds_needed = false;
4049 bool sample_positions_needed = false;
4050
4051 for (uint32_t j = 0; j < cmd_buffer_count; j++) {
4052 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
4053 cmd_buffers[j]);
4054
4055 scratch_size_per_wave = MAX2(scratch_size_per_wave, cmd_buffer->scratch_size_per_wave_needed);
4056 waves_wanted = MAX2(waves_wanted, cmd_buffer->scratch_waves_wanted);
4057 compute_scratch_size_per_wave = MAX2(compute_scratch_size_per_wave,
4058 cmd_buffer->compute_scratch_size_per_wave_needed);
4059 compute_waves_wanted = MAX2(compute_waves_wanted,
4060 cmd_buffer->compute_scratch_waves_wanted);
4061 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
4062 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
4063 tess_rings_needed |= cmd_buffer->tess_rings_needed;
4064 gds_needed |= cmd_buffer->gds_needed;
4065 sample_positions_needed |= cmd_buffer->sample_positions_needed;
4066 }
4067
4068 return radv_get_preamble_cs(queue, scratch_size_per_wave, waves_wanted,
4069 compute_scratch_size_per_wave, compute_waves_wanted,
4070 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
4071 gds_needed, sample_positions_needed,
4072 initial_full_flush_preamble_cs,
4073 initial_preamble_cs, continue_preamble_cs);
4074 }
4075
4076 struct radv_deferred_queue_submission {
4077 struct radv_queue *queue;
4078 VkCommandBuffer *cmd_buffers;
4079 uint32_t cmd_buffer_count;
4080
4081 /* Sparse bindings that happen on a queue. */
4082 VkSparseBufferMemoryBindInfo *buffer_binds;
4083 uint32_t buffer_bind_count;
4084 VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4085 uint32_t image_opaque_bind_count;
4086
4087 bool flush_caches;
4088 VkShaderStageFlags wait_dst_stage_mask;
4089 struct radv_semaphore_part **wait_semaphores;
4090 uint32_t wait_semaphore_count;
4091 struct radv_semaphore_part **signal_semaphores;
4092 uint32_t signal_semaphore_count;
4093 VkFence fence;
4094
4095 uint64_t *wait_values;
4096 uint64_t *signal_values;
4097
4098 struct radv_semaphore_part *temporary_semaphore_parts;
4099 uint32_t temporary_semaphore_part_count;
4100
4101 struct list_head queue_pending_list;
4102 uint32_t submission_wait_count;
4103 struct radv_timeline_waiter *wait_nodes;
4104
4105 struct list_head processing_list;
4106 };
4107
4108 struct radv_queue_submission {
4109 const VkCommandBuffer *cmd_buffers;
4110 uint32_t cmd_buffer_count;
4111
4112 /* Sparse bindings that happen on a queue. */
4113 const VkSparseBufferMemoryBindInfo *buffer_binds;
4114 uint32_t buffer_bind_count;
4115 const VkSparseImageOpaqueMemoryBindInfo *image_opaque_binds;
4116 uint32_t image_opaque_bind_count;
4117
4118 bool flush_caches;
4119 VkPipelineStageFlags wait_dst_stage_mask;
4120 const VkSemaphore *wait_semaphores;
4121 uint32_t wait_semaphore_count;
4122 const VkSemaphore *signal_semaphores;
4123 uint32_t signal_semaphore_count;
4124 VkFence fence;
4125
4126 const uint64_t *wait_values;
4127 uint32_t wait_value_count;
4128 const uint64_t *signal_values;
4129 uint32_t signal_value_count;
4130 };
4131
4132 static VkResult
4133 radv_create_deferred_submission(struct radv_queue *queue,
4134 const struct radv_queue_submission *submission,
4135 struct radv_deferred_queue_submission **out)
4136 {
4137 struct radv_deferred_queue_submission *deferred = NULL;
4138 size_t size = sizeof(struct radv_deferred_queue_submission);
4139
4140 uint32_t temporary_count = 0;
4141 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4142 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4143 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE)
4144 ++temporary_count;
4145 }
4146
4147 size += submission->cmd_buffer_count * sizeof(VkCommandBuffer);
4148 size += submission->buffer_bind_count * sizeof(VkSparseBufferMemoryBindInfo);
4149 size += submission->image_opaque_bind_count * sizeof(VkSparseImageOpaqueMemoryBindInfo);
4150 size += submission->wait_semaphore_count * sizeof(struct radv_semaphore_part *);
4151 size += temporary_count * sizeof(struct radv_semaphore_part);
4152 size += submission->signal_semaphore_count * sizeof(struct radv_semaphore_part *);
4153 size += submission->wait_value_count * sizeof(uint64_t);
4154 size += submission->signal_value_count * sizeof(uint64_t);
4155 size += submission->wait_semaphore_count * sizeof(struct radv_timeline_waiter);
4156
4157 deferred = calloc(1, size);
4158 if (!deferred)
4159 return VK_ERROR_OUT_OF_HOST_MEMORY;
4160
4161 deferred->queue = queue;
4162
4163 deferred->cmd_buffers = (void*)(deferred + 1);
4164 deferred->cmd_buffer_count = submission->cmd_buffer_count;
4165 memcpy(deferred->cmd_buffers, submission->cmd_buffers,
4166 submission->cmd_buffer_count * sizeof(*deferred->cmd_buffers));
4167
4168 deferred->buffer_binds = (void*)(deferred->cmd_buffers + submission->cmd_buffer_count);
4169 deferred->buffer_bind_count = submission->buffer_bind_count;
4170 memcpy(deferred->buffer_binds, submission->buffer_binds,
4171 submission->buffer_bind_count * sizeof(*deferred->buffer_binds));
4172
4173 deferred->image_opaque_binds = (void*)(deferred->buffer_binds + submission->buffer_bind_count);
4174 deferred->image_opaque_bind_count = submission->image_opaque_bind_count;
4175 memcpy(deferred->image_opaque_binds, submission->image_opaque_binds,
4176 submission->image_opaque_bind_count * sizeof(*deferred->image_opaque_binds));
4177
4178 deferred->flush_caches = submission->flush_caches;
4179 deferred->wait_dst_stage_mask = submission->wait_dst_stage_mask;
4180
4181 deferred->wait_semaphores = (void*)(deferred->image_opaque_binds + deferred->image_opaque_bind_count);
4182 deferred->wait_semaphore_count = submission->wait_semaphore_count;
4183
4184 deferred->signal_semaphores = (void*)(deferred->wait_semaphores + deferred->wait_semaphore_count);
4185 deferred->signal_semaphore_count = submission->signal_semaphore_count;
4186
4187 deferred->fence = submission->fence;
4188
4189 deferred->temporary_semaphore_parts = (void*)(deferred->signal_semaphores + deferred->signal_semaphore_count);
4190 deferred->temporary_semaphore_part_count = temporary_count;
4191
4192 uint32_t temporary_idx = 0;
4193 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4194 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->wait_semaphores[i]);
4195 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4196 deferred->wait_semaphores[i] = &deferred->temporary_semaphore_parts[temporary_idx];
4197 deferred->temporary_semaphore_parts[temporary_idx] = semaphore->temporary;
4198 semaphore->temporary.kind = RADV_SEMAPHORE_NONE;
4199 ++temporary_idx;
4200 } else
4201 deferred->wait_semaphores[i] = &semaphore->permanent;
4202 }
4203
4204 for (uint32_t i = 0; i < submission->signal_semaphore_count; ++i) {
4205 RADV_FROM_HANDLE(radv_semaphore, semaphore, submission->signal_semaphores[i]);
4206 if (semaphore->temporary.kind != RADV_SEMAPHORE_NONE) {
4207 deferred->signal_semaphores[i] = &semaphore->temporary;
4208 } else {
4209 deferred->signal_semaphores[i] = &semaphore->permanent;
4210 }
4211 }
4212
4213 deferred->wait_values = (void*)(deferred->temporary_semaphore_parts + temporary_count);
4214 memcpy(deferred->wait_values, submission->wait_values, submission->wait_value_count * sizeof(uint64_t));
4215 deferred->signal_values = deferred->wait_values + submission->wait_value_count;
4216 memcpy(deferred->signal_values, submission->signal_values, submission->signal_value_count * sizeof(uint64_t));
4217
4218 deferred->wait_nodes = (void*)(deferred->signal_values + submission->signal_value_count);
4219 /* This is worst-case. radv_queue_enqueue_submission will fill in further, but this
4220 * ensure the submission is not accidentally triggered early when adding wait timelines. */
4221 deferred->submission_wait_count = 1 + submission->wait_semaphore_count;
4222
4223 *out = deferred;
4224 return VK_SUCCESS;
4225 }
4226
4227 static void
4228 radv_queue_enqueue_submission(struct radv_deferred_queue_submission *submission,
4229 struct list_head *processing_list)
4230 {
4231 uint32_t wait_cnt = 0;
4232 struct radv_timeline_waiter *waiter = submission->wait_nodes;
4233 for (uint32_t i = 0; i < submission->wait_semaphore_count; ++i) {
4234 if (submission->wait_semaphores[i]->kind == RADV_SEMAPHORE_TIMELINE) {
4235 pthread_mutex_lock(&submission->wait_semaphores[i]->timeline.mutex);
4236 if (submission->wait_semaphores[i]->timeline.highest_submitted < submission->wait_values[i]) {
4237 ++wait_cnt;
4238 waiter->value = submission->wait_values[i];
4239 waiter->submission = submission;
4240 list_addtail(&waiter->list, &submission->wait_semaphores[i]->timeline.waiters);
4241 ++waiter;
4242 }
4243 pthread_mutex_unlock(&submission->wait_semaphores[i]->timeline.mutex);
4244 }
4245 }
4246
4247 pthread_mutex_lock(&submission->queue->pending_mutex);
4248
4249 bool is_first = list_is_empty(&submission->queue->pending_submissions);
4250 list_addtail(&submission->queue_pending_list, &submission->queue->pending_submissions);
4251
4252 pthread_mutex_unlock(&submission->queue->pending_mutex);
4253
4254 /* If there is already a submission in the queue, that will decrement the counter by 1 when
4255 * submitted, but if the queue was empty, we decrement ourselves as there is no previous
4256 * submission. */
4257 uint32_t decrement = submission->wait_semaphore_count - wait_cnt + (is_first ? 1 : 0);
4258 if (__atomic_sub_fetch(&submission->submission_wait_count, decrement, __ATOMIC_ACQ_REL) == 0) {
4259 list_addtail(&submission->processing_list, processing_list);
4260 }
4261 }
4262
4263 static void
4264 radv_queue_submission_update_queue(struct radv_deferred_queue_submission *submission,
4265 struct list_head *processing_list)
4266 {
4267 pthread_mutex_lock(&submission->queue->pending_mutex);
4268 list_del(&submission->queue_pending_list);
4269
4270 /* trigger the next submission in the queue. */
4271 if (!list_is_empty(&submission->queue->pending_submissions)) {
4272 struct radv_deferred_queue_submission *next_submission =
4273 list_first_entry(&submission->queue->pending_submissions,
4274 struct radv_deferred_queue_submission,
4275 queue_pending_list);
4276 if (p_atomic_dec_zero(&next_submission->submission_wait_count)) {
4277 list_addtail(&next_submission->processing_list, processing_list);
4278 }
4279 }
4280 pthread_mutex_unlock(&submission->queue->pending_mutex);
4281
4282 pthread_cond_broadcast(&submission->queue->device->timeline_cond);
4283 }
4284
4285 static VkResult
4286 radv_queue_submit_deferred(struct radv_deferred_queue_submission *submission,
4287 struct list_head *processing_list)
4288 {
4289 RADV_FROM_HANDLE(radv_fence, fence, submission->fence);
4290 struct radv_queue *queue = submission->queue;
4291 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
4292 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
4293 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
4294 bool do_flush = submission->flush_caches || submission->wait_dst_stage_mask;
4295 bool can_patch = true;
4296 uint32_t advance;
4297 struct radv_winsys_sem_info sem_info;
4298 VkResult result;
4299 int ret;
4300 struct radeon_cmdbuf *initial_preamble_cs = NULL;
4301 struct radeon_cmdbuf *initial_flush_preamble_cs = NULL;
4302 struct radeon_cmdbuf *continue_preamble_cs = NULL;
4303
4304 result = radv_get_preambles(queue, submission->cmd_buffers,
4305 submission->cmd_buffer_count,
4306 &initial_preamble_cs,
4307 &initial_flush_preamble_cs,
4308 &continue_preamble_cs);
4309 if (result != VK_SUCCESS)
4310 goto fail;
4311
4312 result = radv_alloc_sem_info(queue->device,
4313 &sem_info,
4314 submission->wait_semaphore_count,
4315 submission->wait_semaphores,
4316 submission->wait_values,
4317 submission->signal_semaphore_count,
4318 submission->signal_semaphores,
4319 submission->signal_values,
4320 submission->fence);
4321 if (result != VK_SUCCESS)
4322 goto fail;
4323
4324 for (uint32_t i = 0; i < submission->buffer_bind_count; ++i) {
4325 radv_sparse_buffer_bind_memory(queue->device,
4326 submission->buffer_binds + i);
4327 }
4328
4329 for (uint32_t i = 0; i < submission->image_opaque_bind_count; ++i) {
4330 radv_sparse_image_opaque_bind_memory(queue->device,
4331 submission->image_opaque_binds + i);
4332 }
4333
4334 if (!submission->cmd_buffer_count) {
4335 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
4336 &queue->device->empty_cs[queue->queue_family_index],
4337 1, NULL, NULL,
4338 &sem_info, NULL,
4339 false, base_fence);
4340 if (ret) {
4341 radv_loge("failed to submit CS\n");
4342 abort();
4343 }
4344
4345 goto success;
4346 } else {
4347 struct radeon_cmdbuf **cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
4348 (submission->cmd_buffer_count));
4349
4350 for (uint32_t j = 0; j < submission->cmd_buffer_count; j++) {
4351 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, submission->cmd_buffers[j]);
4352 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
4353
4354 cs_array[j] = cmd_buffer->cs;
4355 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
4356 can_patch = false;
4357
4358 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
4359 }
4360
4361 for (uint32_t j = 0; j < submission->cmd_buffer_count; j += advance) {
4362 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
4363 const struct radv_winsys_bo_list *bo_list = NULL;
4364
4365 advance = MIN2(max_cs_submission,
4366 submission->cmd_buffer_count - j);
4367
4368 if (queue->device->trace_bo)
4369 *queue->device->trace_id_ptr = 0;
4370
4371 sem_info.cs_emit_wait = j == 0;
4372 sem_info.cs_emit_signal = j + advance == submission->cmd_buffer_count;
4373
4374 if (unlikely(queue->device->use_global_bo_list)) {
4375 pthread_mutex_lock(&queue->device->bo_list.mutex);
4376 bo_list = &queue->device->bo_list.list;
4377 }
4378
4379 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
4380 advance, initial_preamble, continue_preamble_cs,
4381 &sem_info, bo_list,
4382 can_patch, base_fence);
4383
4384 if (unlikely(queue->device->use_global_bo_list))
4385 pthread_mutex_unlock(&queue->device->bo_list.mutex);
4386
4387 if (ret) {
4388 radv_loge("failed to submit CS\n");
4389 abort();
4390 }
4391 if (queue->device->trace_bo) {
4392 radv_check_gpu_hangs(queue, cs_array[j]);
4393 }
4394 }
4395
4396 free(cs_array);
4397 }
4398
4399 success:
4400 radv_free_temp_syncobjs(queue->device,
4401 submission->temporary_semaphore_part_count,
4402 submission->temporary_semaphore_parts);
4403 radv_finalize_timelines(queue->device,
4404 submission->wait_semaphore_count,
4405 submission->wait_semaphores,
4406 submission->wait_values,
4407 submission->signal_semaphore_count,
4408 submission->signal_semaphores,
4409 submission->signal_values,
4410 processing_list);
4411 /* Has to happen after timeline finalization to make sure the
4412 * condition variable is only triggered when timelines and queue have
4413 * been updated. */
4414 radv_queue_submission_update_queue(submission, processing_list);
4415 radv_free_sem_info(&sem_info);
4416 free(submission);
4417 return VK_SUCCESS;
4418
4419 fail:
4420 radv_free_temp_syncobjs(queue->device,
4421 submission->temporary_semaphore_part_count,
4422 submission->temporary_semaphore_parts);
4423 free(submission);
4424 return VK_ERROR_DEVICE_LOST;
4425 }
4426
4427 static VkResult
4428 radv_process_submissions(struct list_head *processing_list)
4429 {
4430 while(!list_is_empty(processing_list)) {
4431 struct radv_deferred_queue_submission *submission =
4432 list_first_entry(processing_list, struct radv_deferred_queue_submission, processing_list);
4433 list_del(&submission->processing_list);
4434
4435 VkResult result = radv_queue_submit_deferred(submission, processing_list);
4436 if (result != VK_SUCCESS)
4437 return result;
4438 }
4439 return VK_SUCCESS;
4440 }
4441
4442 static VkResult radv_queue_submit(struct radv_queue *queue,
4443 const struct radv_queue_submission *submission)
4444 {
4445 struct radv_deferred_queue_submission *deferred = NULL;
4446
4447 VkResult result = radv_create_deferred_submission(queue, submission, &deferred);
4448 if (result != VK_SUCCESS)
4449 return result;
4450
4451 struct list_head processing_list;
4452 list_inithead(&processing_list);
4453
4454 radv_queue_enqueue_submission(deferred, &processing_list);
4455 return radv_process_submissions(&processing_list);
4456 }
4457
4458 /* Signals fence as soon as all the work currently put on queue is done. */
4459 static VkResult radv_signal_fence(struct radv_queue *queue,
4460 VkFence fence)
4461 {
4462 return radv_queue_submit(queue, &(struct radv_queue_submission) {
4463 .fence = fence
4464 });
4465 }
4466
4467 static bool radv_submit_has_effects(const VkSubmitInfo *info)
4468 {
4469 return info->commandBufferCount ||
4470 info->waitSemaphoreCount ||
4471 info->signalSemaphoreCount;
4472 }
4473
4474 VkResult radv_QueueSubmit(
4475 VkQueue _queue,
4476 uint32_t submitCount,
4477 const VkSubmitInfo* pSubmits,
4478 VkFence fence)
4479 {
4480 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4481 VkResult result;
4482 uint32_t fence_idx = 0;
4483 bool flushed_caches = false;
4484
4485 if (fence != VK_NULL_HANDLE) {
4486 for (uint32_t i = 0; i < submitCount; ++i)
4487 if (radv_submit_has_effects(pSubmits + i))
4488 fence_idx = i;
4489 } else
4490 fence_idx = UINT32_MAX;
4491
4492 for (uint32_t i = 0; i < submitCount; i++) {
4493 if (!radv_submit_has_effects(pSubmits + i) && fence_idx != i)
4494 continue;
4495
4496 VkPipelineStageFlags wait_dst_stage_mask = 0;
4497 for (unsigned j = 0; j < pSubmits[i].waitSemaphoreCount; ++j) {
4498 wait_dst_stage_mask |= pSubmits[i].pWaitDstStageMask[j];
4499 }
4500
4501 const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
4502 vk_find_struct_const(pSubmits[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
4503
4504 result = radv_queue_submit(queue, &(struct radv_queue_submission) {
4505 .cmd_buffers = pSubmits[i].pCommandBuffers,
4506 .cmd_buffer_count = pSubmits[i].commandBufferCount,
4507 .wait_dst_stage_mask = wait_dst_stage_mask,
4508 .flush_caches = !flushed_caches,
4509 .wait_semaphores = pSubmits[i].pWaitSemaphores,
4510 .wait_semaphore_count = pSubmits[i].waitSemaphoreCount,
4511 .signal_semaphores = pSubmits[i].pSignalSemaphores,
4512 .signal_semaphore_count = pSubmits[i].signalSemaphoreCount,
4513 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
4514 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
4515 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
4516 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
4517 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
4518 });
4519 if (result != VK_SUCCESS)
4520 return result;
4521
4522 flushed_caches = true;
4523 }
4524
4525 if (fence != VK_NULL_HANDLE && !submitCount) {
4526 result = radv_signal_fence(queue, fence);
4527 if (result != VK_SUCCESS)
4528 return result;
4529 }
4530
4531 return VK_SUCCESS;
4532 }
4533
4534 VkResult radv_QueueWaitIdle(
4535 VkQueue _queue)
4536 {
4537 RADV_FROM_HANDLE(radv_queue, queue, _queue);
4538
4539 pthread_mutex_lock(&queue->pending_mutex);
4540 while (!list_is_empty(&queue->pending_submissions)) {
4541 pthread_cond_wait(&queue->device->timeline_cond, &queue->pending_mutex);
4542 }
4543 pthread_mutex_unlock(&queue->pending_mutex);
4544
4545 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
4546 radv_queue_family_to_ring(queue->queue_family_index),
4547 queue->queue_idx);
4548 return VK_SUCCESS;
4549 }
4550
4551 VkResult radv_DeviceWaitIdle(
4552 VkDevice _device)
4553 {
4554 RADV_FROM_HANDLE(radv_device, device, _device);
4555
4556 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
4557 for (unsigned q = 0; q < device->queue_count[i]; q++) {
4558 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
4559 }
4560 }
4561 return VK_SUCCESS;
4562 }
4563
4564 VkResult radv_EnumerateInstanceExtensionProperties(
4565 const char* pLayerName,
4566 uint32_t* pPropertyCount,
4567 VkExtensionProperties* pProperties)
4568 {
4569 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4570
4571 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
4572 if (radv_supported_instance_extensions.extensions[i]) {
4573 vk_outarray_append(&out, prop) {
4574 *prop = radv_instance_extensions[i];
4575 }
4576 }
4577 }
4578
4579 return vk_outarray_status(&out);
4580 }
4581
4582 VkResult radv_EnumerateDeviceExtensionProperties(
4583 VkPhysicalDevice physicalDevice,
4584 const char* pLayerName,
4585 uint32_t* pPropertyCount,
4586 VkExtensionProperties* pProperties)
4587 {
4588 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
4589 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
4590
4591 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
4592 if (device->supported_extensions.extensions[i]) {
4593 vk_outarray_append(&out, prop) {
4594 *prop = radv_device_extensions[i];
4595 }
4596 }
4597 }
4598
4599 return vk_outarray_status(&out);
4600 }
4601
4602 PFN_vkVoidFunction radv_GetInstanceProcAddr(
4603 VkInstance _instance,
4604 const char* pName)
4605 {
4606 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4607 bool unchecked = instance ? instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4608
4609 if (unchecked) {
4610 return radv_lookup_entrypoint_unchecked(pName);
4611 } else {
4612 return radv_lookup_entrypoint_checked(pName,
4613 instance ? instance->apiVersion : 0,
4614 instance ? &instance->enabled_extensions : NULL,
4615 NULL);
4616 }
4617 }
4618
4619 /* The loader wants us to expose a second GetInstanceProcAddr function
4620 * to work around certain LD_PRELOAD issues seen in apps.
4621 */
4622 PUBLIC
4623 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4624 VkInstance instance,
4625 const char* pName);
4626
4627 PUBLIC
4628 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
4629 VkInstance instance,
4630 const char* pName)
4631 {
4632 return radv_GetInstanceProcAddr(instance, pName);
4633 }
4634
4635 PUBLIC
4636 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4637 VkInstance _instance,
4638 const char* pName);
4639
4640 PUBLIC
4641 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
4642 VkInstance _instance,
4643 const char* pName)
4644 {
4645 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4646
4647 return radv_lookup_physical_device_entrypoint_checked(pName,
4648 instance ? instance->apiVersion : 0,
4649 instance ? &instance->enabled_extensions : NULL);
4650 }
4651
4652 PFN_vkVoidFunction radv_GetDeviceProcAddr(
4653 VkDevice _device,
4654 const char* pName)
4655 {
4656 RADV_FROM_HANDLE(radv_device, device, _device);
4657 bool unchecked = device ? device->instance->debug_flags & RADV_DEBUG_ALL_ENTRYPOINTS : false;
4658
4659 if (unchecked) {
4660 return radv_lookup_entrypoint_unchecked(pName);
4661 } else {
4662 return radv_lookup_entrypoint_checked(pName,
4663 device->instance->apiVersion,
4664 &device->instance->enabled_extensions,
4665 &device->enabled_extensions);
4666 }
4667 }
4668
4669 bool radv_get_memory_fd(struct radv_device *device,
4670 struct radv_device_memory *memory,
4671 int *pFD)
4672 {
4673 struct radeon_bo_metadata metadata;
4674
4675 if (memory->image) {
4676 radv_init_metadata(device, memory->image, &metadata);
4677 device->ws->buffer_set_metadata(memory->bo, &metadata);
4678 }
4679
4680 return device->ws->buffer_get_fd(device->ws, memory->bo,
4681 pFD);
4682 }
4683
4684
4685 static void radv_free_memory(struct radv_device *device,
4686 const VkAllocationCallbacks* pAllocator,
4687 struct radv_device_memory *mem)
4688 {
4689 if (mem == NULL)
4690 return;
4691
4692 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4693 if (mem->android_hardware_buffer)
4694 AHardwareBuffer_release(mem->android_hardware_buffer);
4695 #endif
4696
4697 if (mem->bo) {
4698 radv_bo_list_remove(device, mem->bo);
4699 device->ws->buffer_destroy(mem->bo);
4700 mem->bo = NULL;
4701 }
4702
4703 vk_free2(&device->alloc, pAllocator, mem);
4704 }
4705
4706 static VkResult radv_alloc_memory(struct radv_device *device,
4707 const VkMemoryAllocateInfo* pAllocateInfo,
4708 const VkAllocationCallbacks* pAllocator,
4709 VkDeviceMemory* pMem)
4710 {
4711 struct radv_device_memory *mem;
4712 VkResult result;
4713 enum radeon_bo_domain domain;
4714 uint32_t flags = 0;
4715 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
4716
4717 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
4718
4719 const VkImportMemoryFdInfoKHR *import_info =
4720 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
4721 const VkMemoryDedicatedAllocateInfo *dedicate_info =
4722 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
4723 const VkExportMemoryAllocateInfo *export_info =
4724 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
4725 const struct VkImportAndroidHardwareBufferInfoANDROID *ahb_import_info =
4726 vk_find_struct_const(pAllocateInfo->pNext,
4727 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID);
4728 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
4729 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
4730
4731 const struct wsi_memory_allocate_info *wsi_info =
4732 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
4733
4734 if (pAllocateInfo->allocationSize == 0 && !ahb_import_info &&
4735 !(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID))) {
4736 /* Apparently, this is allowed */
4737 *pMem = VK_NULL_HANDLE;
4738 return VK_SUCCESS;
4739 }
4740
4741 mem = vk_zalloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
4742 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4743 if (mem == NULL)
4744 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4745
4746 if (wsi_info && wsi_info->implicit_sync)
4747 flags |= RADEON_FLAG_IMPLICIT_SYNC;
4748
4749 if (dedicate_info) {
4750 mem->image = radv_image_from_handle(dedicate_info->image);
4751 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
4752 } else {
4753 mem->image = NULL;
4754 mem->buffer = NULL;
4755 }
4756
4757 float priority_float = 0.5;
4758 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
4759 vk_find_struct_const(pAllocateInfo->pNext,
4760 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
4761 if (priority_ext)
4762 priority_float = priority_ext->priority;
4763
4764 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
4765 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
4766
4767 mem->user_ptr = NULL;
4768 mem->bo = NULL;
4769
4770 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4771 mem->android_hardware_buffer = NULL;
4772 #endif
4773
4774 if (ahb_import_info) {
4775 result = radv_import_ahb_memory(device, mem, priority, ahb_import_info);
4776 if (result != VK_SUCCESS)
4777 goto fail;
4778 } else if(export_info && (export_info->handleTypes & VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID)) {
4779 result = radv_create_ahb_memory(device, mem, priority, pAllocateInfo);
4780 if (result != VK_SUCCESS)
4781 goto fail;
4782 } else if (import_info) {
4783 assert(import_info->handleType ==
4784 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4785 import_info->handleType ==
4786 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4787 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
4788 priority, NULL);
4789 if (!mem->bo) {
4790 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4791 goto fail;
4792 } else {
4793 close(import_info->fd);
4794 }
4795 } else if (host_ptr_info) {
4796 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
4797 assert(radv_is_mem_type_gtt_cached(mem_type_index));
4798 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
4799 pAllocateInfo->allocationSize,
4800 priority);
4801 if (!mem->bo) {
4802 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
4803 goto fail;
4804 } else {
4805 mem->user_ptr = host_ptr_info->pHostPointer;
4806 }
4807 } else {
4808 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
4809 if (radv_is_mem_type_gtt_wc(mem_type_index) ||
4810 radv_is_mem_type_gtt_cached(mem_type_index))
4811 domain = RADEON_DOMAIN_GTT;
4812 else
4813 domain = RADEON_DOMAIN_VRAM;
4814
4815 if (radv_is_mem_type_vram(mem_type_index))
4816 flags |= RADEON_FLAG_NO_CPU_ACCESS;
4817 else
4818 flags |= RADEON_FLAG_CPU_ACCESS;
4819
4820 if (radv_is_mem_type_gtt_wc(mem_type_index))
4821 flags |= RADEON_FLAG_GTT_WC;
4822
4823 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
4824 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
4825 if (device->use_global_bo_list) {
4826 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
4827 }
4828 }
4829
4830 if (radv_is_mem_type_uncached(mem_type_index)) {
4831 assert(device->physical_device->rad_info.has_l2_uncached);
4832 flags |= RADEON_FLAG_VA_UNCACHED;
4833 }
4834
4835 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
4836 domain, flags, priority);
4837
4838 if (!mem->bo) {
4839 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
4840 goto fail;
4841 }
4842 mem->type_index = mem_type_index;
4843 }
4844
4845 result = radv_bo_list_add(device, mem->bo);
4846 if (result != VK_SUCCESS)
4847 goto fail;
4848
4849 *pMem = radv_device_memory_to_handle(mem);
4850
4851 return VK_SUCCESS;
4852
4853 fail:
4854 radv_free_memory(device, pAllocator,mem);
4855 vk_free2(&device->alloc, pAllocator, mem);
4856
4857 return result;
4858 }
4859
4860 VkResult radv_AllocateMemory(
4861 VkDevice _device,
4862 const VkMemoryAllocateInfo* pAllocateInfo,
4863 const VkAllocationCallbacks* pAllocator,
4864 VkDeviceMemory* pMem)
4865 {
4866 RADV_FROM_HANDLE(radv_device, device, _device);
4867 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
4868 }
4869
4870 void radv_FreeMemory(
4871 VkDevice _device,
4872 VkDeviceMemory _mem,
4873 const VkAllocationCallbacks* pAllocator)
4874 {
4875 RADV_FROM_HANDLE(radv_device, device, _device);
4876 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
4877
4878 radv_free_memory(device, pAllocator, mem);
4879 }
4880
4881 VkResult radv_MapMemory(
4882 VkDevice _device,
4883 VkDeviceMemory _memory,
4884 VkDeviceSize offset,
4885 VkDeviceSize size,
4886 VkMemoryMapFlags flags,
4887 void** ppData)
4888 {
4889 RADV_FROM_HANDLE(radv_device, device, _device);
4890 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4891
4892 if (mem == NULL) {
4893 *ppData = NULL;
4894 return VK_SUCCESS;
4895 }
4896
4897 if (mem->user_ptr)
4898 *ppData = mem->user_ptr;
4899 else
4900 *ppData = device->ws->buffer_map(mem->bo);
4901
4902 if (*ppData) {
4903 *ppData += offset;
4904 return VK_SUCCESS;
4905 }
4906
4907 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
4908 }
4909
4910 void radv_UnmapMemory(
4911 VkDevice _device,
4912 VkDeviceMemory _memory)
4913 {
4914 RADV_FROM_HANDLE(radv_device, device, _device);
4915 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
4916
4917 if (mem == NULL)
4918 return;
4919
4920 if (mem->user_ptr == NULL)
4921 device->ws->buffer_unmap(mem->bo);
4922 }
4923
4924 VkResult radv_FlushMappedMemoryRanges(
4925 VkDevice _device,
4926 uint32_t memoryRangeCount,
4927 const VkMappedMemoryRange* pMemoryRanges)
4928 {
4929 return VK_SUCCESS;
4930 }
4931
4932 VkResult radv_InvalidateMappedMemoryRanges(
4933 VkDevice _device,
4934 uint32_t memoryRangeCount,
4935 const VkMappedMemoryRange* pMemoryRanges)
4936 {
4937 return VK_SUCCESS;
4938 }
4939
4940 void radv_GetBufferMemoryRequirements(
4941 VkDevice _device,
4942 VkBuffer _buffer,
4943 VkMemoryRequirements* pMemoryRequirements)
4944 {
4945 RADV_FROM_HANDLE(radv_device, device, _device);
4946 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4947
4948 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4949
4950 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4951 pMemoryRequirements->alignment = 4096;
4952 else
4953 pMemoryRequirements->alignment = 16;
4954
4955 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
4956 }
4957
4958 void radv_GetBufferMemoryRequirements2(
4959 VkDevice device,
4960 const VkBufferMemoryRequirementsInfo2 *pInfo,
4961 VkMemoryRequirements2 *pMemoryRequirements)
4962 {
4963 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
4964 &pMemoryRequirements->memoryRequirements);
4965 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4966 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
4967 switch (ext->sType) {
4968 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
4969 VkMemoryDedicatedRequirements *req =
4970 (VkMemoryDedicatedRequirements *) ext;
4971 req->requiresDedicatedAllocation = buffer->shareable;
4972 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
4973 break;
4974 }
4975 default:
4976 break;
4977 }
4978 }
4979 }
4980
4981 void radv_GetImageMemoryRequirements(
4982 VkDevice _device,
4983 VkImage _image,
4984 VkMemoryRequirements* pMemoryRequirements)
4985 {
4986 RADV_FROM_HANDLE(radv_device, device, _device);
4987 RADV_FROM_HANDLE(radv_image, image, _image);
4988
4989 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
4990
4991 pMemoryRequirements->size = image->size;
4992 pMemoryRequirements->alignment = image->alignment;
4993 }
4994
4995 void radv_GetImageMemoryRequirements2(
4996 VkDevice device,
4997 const VkImageMemoryRequirementsInfo2 *pInfo,
4998 VkMemoryRequirements2 *pMemoryRequirements)
4999 {
5000 radv_GetImageMemoryRequirements(device, pInfo->image,
5001 &pMemoryRequirements->memoryRequirements);
5002
5003 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
5004
5005 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
5006 switch (ext->sType) {
5007 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
5008 VkMemoryDedicatedRequirements *req =
5009 (VkMemoryDedicatedRequirements *) ext;
5010 req->requiresDedicatedAllocation = image->shareable;
5011 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
5012 break;
5013 }
5014 default:
5015 break;
5016 }
5017 }
5018 }
5019
5020 void radv_GetImageSparseMemoryRequirements(
5021 VkDevice device,
5022 VkImage image,
5023 uint32_t* pSparseMemoryRequirementCount,
5024 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
5025 {
5026 stub();
5027 }
5028
5029 void radv_GetImageSparseMemoryRequirements2(
5030 VkDevice device,
5031 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
5032 uint32_t* pSparseMemoryRequirementCount,
5033 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
5034 {
5035 stub();
5036 }
5037
5038 void radv_GetDeviceMemoryCommitment(
5039 VkDevice device,
5040 VkDeviceMemory memory,
5041 VkDeviceSize* pCommittedMemoryInBytes)
5042 {
5043 *pCommittedMemoryInBytes = 0;
5044 }
5045
5046 VkResult radv_BindBufferMemory2(VkDevice device,
5047 uint32_t bindInfoCount,
5048 const VkBindBufferMemoryInfo *pBindInfos)
5049 {
5050 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5051 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5052 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
5053
5054 if (mem) {
5055 buffer->bo = mem->bo;
5056 buffer->offset = pBindInfos[i].memoryOffset;
5057 } else {
5058 buffer->bo = NULL;
5059 }
5060 }
5061 return VK_SUCCESS;
5062 }
5063
5064 VkResult radv_BindBufferMemory(
5065 VkDevice device,
5066 VkBuffer buffer,
5067 VkDeviceMemory memory,
5068 VkDeviceSize memoryOffset)
5069 {
5070 const VkBindBufferMemoryInfo info = {
5071 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5072 .buffer = buffer,
5073 .memory = memory,
5074 .memoryOffset = memoryOffset
5075 };
5076
5077 return radv_BindBufferMemory2(device, 1, &info);
5078 }
5079
5080 VkResult radv_BindImageMemory2(VkDevice device,
5081 uint32_t bindInfoCount,
5082 const VkBindImageMemoryInfo *pBindInfos)
5083 {
5084 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5085 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
5086 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
5087
5088 if (mem) {
5089 image->bo = mem->bo;
5090 image->offset = pBindInfos[i].memoryOffset;
5091 } else {
5092 image->bo = NULL;
5093 image->offset = 0;
5094 }
5095 }
5096 return VK_SUCCESS;
5097 }
5098
5099
5100 VkResult radv_BindImageMemory(
5101 VkDevice device,
5102 VkImage image,
5103 VkDeviceMemory memory,
5104 VkDeviceSize memoryOffset)
5105 {
5106 const VkBindImageMemoryInfo info = {
5107 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
5108 .image = image,
5109 .memory = memory,
5110 .memoryOffset = memoryOffset
5111 };
5112
5113 return radv_BindImageMemory2(device, 1, &info);
5114 }
5115
5116 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo *info)
5117 {
5118 return info->bufferBindCount ||
5119 info->imageOpaqueBindCount ||
5120 info->imageBindCount ||
5121 info->waitSemaphoreCount ||
5122 info->signalSemaphoreCount;
5123 }
5124
5125 VkResult radv_QueueBindSparse(
5126 VkQueue _queue,
5127 uint32_t bindInfoCount,
5128 const VkBindSparseInfo* pBindInfo,
5129 VkFence fence)
5130 {
5131 RADV_FROM_HANDLE(radv_queue, queue, _queue);
5132 VkResult result;
5133 uint32_t fence_idx = 0;
5134
5135 if (fence != VK_NULL_HANDLE) {
5136 for (uint32_t i = 0; i < bindInfoCount; ++i)
5137 if (radv_sparse_bind_has_effects(pBindInfo + i))
5138 fence_idx = i;
5139 } else
5140 fence_idx = UINT32_MAX;
5141
5142 for (uint32_t i = 0; i < bindInfoCount; ++i) {
5143 if (i != fence_idx && !radv_sparse_bind_has_effects(pBindInfo + i))
5144 continue;
5145
5146 const VkTimelineSemaphoreSubmitInfoKHR *timeline_info =
5147 vk_find_struct_const(pBindInfo[i].pNext, TIMELINE_SEMAPHORE_SUBMIT_INFO_KHR);
5148
5149 VkResult result = radv_queue_submit(queue, &(struct radv_queue_submission) {
5150 .buffer_binds = pBindInfo[i].pBufferBinds,
5151 .buffer_bind_count = pBindInfo[i].bufferBindCount,
5152 .image_opaque_binds = pBindInfo[i].pImageOpaqueBinds,
5153 .image_opaque_bind_count = pBindInfo[i].imageOpaqueBindCount,
5154 .wait_semaphores = pBindInfo[i].pWaitSemaphores,
5155 .wait_semaphore_count = pBindInfo[i].waitSemaphoreCount,
5156 .signal_semaphores = pBindInfo[i].pSignalSemaphores,
5157 .signal_semaphore_count = pBindInfo[i].signalSemaphoreCount,
5158 .fence = i == fence_idx ? fence : VK_NULL_HANDLE,
5159 .wait_values = timeline_info ? timeline_info->pWaitSemaphoreValues : NULL,
5160 .wait_value_count = timeline_info && timeline_info->pWaitSemaphoreValues ? timeline_info->waitSemaphoreValueCount : 0,
5161 .signal_values = timeline_info ? timeline_info->pSignalSemaphoreValues : NULL,
5162 .signal_value_count = timeline_info && timeline_info->pSignalSemaphoreValues ? timeline_info->signalSemaphoreValueCount : 0,
5163 });
5164
5165 if (result != VK_SUCCESS)
5166 return result;
5167 }
5168
5169 if (fence != VK_NULL_HANDLE && !bindInfoCount) {
5170 result = radv_signal_fence(queue, fence);
5171 if (result != VK_SUCCESS)
5172 return result;
5173 }
5174
5175 return VK_SUCCESS;
5176 }
5177
5178 VkResult radv_CreateFence(
5179 VkDevice _device,
5180 const VkFenceCreateInfo* pCreateInfo,
5181 const VkAllocationCallbacks* pAllocator,
5182 VkFence* pFence)
5183 {
5184 RADV_FROM_HANDLE(radv_device, device, _device);
5185 const VkExportFenceCreateInfo *export =
5186 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
5187 VkExternalFenceHandleTypeFlags handleTypes =
5188 export ? export->handleTypes : 0;
5189
5190 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
5191 sizeof(*fence), 8,
5192 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5193
5194 if (!fence)
5195 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5196
5197 fence->fence_wsi = NULL;
5198 fence->temp_syncobj = 0;
5199 if (device->always_use_syncobj || handleTypes) {
5200 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
5201 if (ret) {
5202 vk_free2(&device->alloc, pAllocator, fence);
5203 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5204 }
5205 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
5206 device->ws->signal_syncobj(device->ws, fence->syncobj);
5207 }
5208 fence->fence = NULL;
5209 } else {
5210 fence->fence = device->ws->create_fence();
5211 if (!fence->fence) {
5212 vk_free2(&device->alloc, pAllocator, fence);
5213 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5214 }
5215 fence->syncobj = 0;
5216 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
5217 device->ws->signal_fence(fence->fence);
5218 }
5219
5220 *pFence = radv_fence_to_handle(fence);
5221
5222 return VK_SUCCESS;
5223 }
5224
5225 void radv_DestroyFence(
5226 VkDevice _device,
5227 VkFence _fence,
5228 const VkAllocationCallbacks* pAllocator)
5229 {
5230 RADV_FROM_HANDLE(radv_device, device, _device);
5231 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5232
5233 if (!fence)
5234 return;
5235
5236 if (fence->temp_syncobj)
5237 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5238 if (fence->syncobj)
5239 device->ws->destroy_syncobj(device->ws, fence->syncobj);
5240 if (fence->fence)
5241 device->ws->destroy_fence(fence->fence);
5242 if (fence->fence_wsi)
5243 fence->fence_wsi->destroy(fence->fence_wsi);
5244 vk_free2(&device->alloc, pAllocator, fence);
5245 }
5246
5247
5248 uint64_t radv_get_current_time(void)
5249 {
5250 struct timespec tv;
5251 clock_gettime(CLOCK_MONOTONIC, &tv);
5252 return tv.tv_nsec + tv.tv_sec*1000000000ull;
5253 }
5254
5255 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
5256 {
5257 uint64_t current_time = radv_get_current_time();
5258
5259 timeout = MIN2(UINT64_MAX - current_time, timeout);
5260
5261 return current_time + timeout;
5262 }
5263
5264
5265 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
5266 uint32_t fenceCount, const VkFence *pFences)
5267 {
5268 for (uint32_t i = 0; i < fenceCount; ++i) {
5269 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5270 if (fence->fence == NULL || fence->syncobj ||
5271 fence->temp_syncobj || fence->fence_wsi ||
5272 (!device->ws->is_fence_waitable(fence->fence)))
5273 return false;
5274 }
5275 return true;
5276 }
5277
5278 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
5279 {
5280 for (uint32_t i = 0; i < fenceCount; ++i) {
5281 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5282 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
5283 return false;
5284 }
5285 return true;
5286 }
5287
5288 VkResult radv_WaitForFences(
5289 VkDevice _device,
5290 uint32_t fenceCount,
5291 const VkFence* pFences,
5292 VkBool32 waitAll,
5293 uint64_t timeout)
5294 {
5295 RADV_FROM_HANDLE(radv_device, device, _device);
5296 timeout = radv_get_absolute_timeout(timeout);
5297
5298 if (device->always_use_syncobj &&
5299 radv_all_fences_syncobj(fenceCount, pFences))
5300 {
5301 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
5302 if (!handles)
5303 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5304
5305 for (uint32_t i = 0; i < fenceCount; ++i) {
5306 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5307 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
5308 }
5309
5310 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
5311
5312 free(handles);
5313 return success ? VK_SUCCESS : VK_TIMEOUT;
5314 }
5315
5316 if (!waitAll && fenceCount > 1) {
5317 /* Not doing this by default for waitAll, due to needing to allocate twice. */
5318 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
5319 uint32_t wait_count = 0;
5320 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
5321 if (!fences)
5322 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5323
5324 for (uint32_t i = 0; i < fenceCount; ++i) {
5325 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5326
5327 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
5328 free(fences);
5329 return VK_SUCCESS;
5330 }
5331
5332 fences[wait_count++] = fence->fence;
5333 }
5334
5335 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
5336 waitAll, timeout - radv_get_current_time());
5337
5338 free(fences);
5339 return success ? VK_SUCCESS : VK_TIMEOUT;
5340 }
5341
5342 while(radv_get_current_time() <= timeout) {
5343 for (uint32_t i = 0; i < fenceCount; ++i) {
5344 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
5345 return VK_SUCCESS;
5346 }
5347 }
5348 return VK_TIMEOUT;
5349 }
5350
5351 for (uint32_t i = 0; i < fenceCount; ++i) {
5352 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5353 bool expired = false;
5354
5355 if (fence->temp_syncobj) {
5356 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
5357 return VK_TIMEOUT;
5358 continue;
5359 }
5360
5361 if (fence->syncobj) {
5362 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
5363 return VK_TIMEOUT;
5364 continue;
5365 }
5366
5367 if (fence->fence) {
5368 if (!device->ws->is_fence_waitable(fence->fence)) {
5369 while(!device->ws->is_fence_waitable(fence->fence) &&
5370 radv_get_current_time() <= timeout)
5371 /* Do nothing */;
5372 }
5373
5374 expired = device->ws->fence_wait(device->ws,
5375 fence->fence,
5376 true, timeout);
5377 if (!expired)
5378 return VK_TIMEOUT;
5379 }
5380
5381 if (fence->fence_wsi) {
5382 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
5383 if (result != VK_SUCCESS)
5384 return result;
5385 }
5386 }
5387
5388 return VK_SUCCESS;
5389 }
5390
5391 VkResult radv_ResetFences(VkDevice _device,
5392 uint32_t fenceCount,
5393 const VkFence *pFences)
5394 {
5395 RADV_FROM_HANDLE(radv_device, device, _device);
5396
5397 for (unsigned i = 0; i < fenceCount; ++i) {
5398 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
5399 if (fence->fence)
5400 device->ws->reset_fence(fence->fence);
5401
5402 /* Per spec, we first restore the permanent payload, and then reset, so
5403 * having a temp syncobj should not skip resetting the permanent syncobj. */
5404 if (fence->temp_syncobj) {
5405 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
5406 fence->temp_syncobj = 0;
5407 }
5408
5409 if (fence->syncobj) {
5410 device->ws->reset_syncobj(device->ws, fence->syncobj);
5411 }
5412 }
5413
5414 return VK_SUCCESS;
5415 }
5416
5417 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
5418 {
5419 RADV_FROM_HANDLE(radv_device, device, _device);
5420 RADV_FROM_HANDLE(radv_fence, fence, _fence);
5421
5422 if (fence->temp_syncobj) {
5423 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
5424 return success ? VK_SUCCESS : VK_NOT_READY;
5425 }
5426
5427 if (fence->syncobj) {
5428 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
5429 return success ? VK_SUCCESS : VK_NOT_READY;
5430 }
5431
5432 if (fence->fence) {
5433 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
5434 return VK_NOT_READY;
5435 }
5436 if (fence->fence_wsi) {
5437 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
5438
5439 if (result != VK_SUCCESS) {
5440 if (result == VK_TIMEOUT)
5441 return VK_NOT_READY;
5442 return result;
5443 }
5444 }
5445 return VK_SUCCESS;
5446 }
5447
5448
5449 // Queue semaphore functions
5450
5451 static void
5452 radv_create_timeline(struct radv_timeline *timeline, uint64_t value)
5453 {
5454 timeline->highest_signaled = value;
5455 timeline->highest_submitted = value;
5456 list_inithead(&timeline->points);
5457 list_inithead(&timeline->free_points);
5458 list_inithead(&timeline->waiters);
5459 pthread_mutex_init(&timeline->mutex, NULL);
5460 }
5461
5462 static void
5463 radv_destroy_timeline(struct radv_device *device,
5464 struct radv_timeline *timeline)
5465 {
5466 list_for_each_entry_safe(struct radv_timeline_point, point,
5467 &timeline->free_points, list) {
5468 list_del(&point->list);
5469 device->ws->destroy_syncobj(device->ws, point->syncobj);
5470 free(point);
5471 }
5472 list_for_each_entry_safe(struct radv_timeline_point, point,
5473 &timeline->points, list) {
5474 list_del(&point->list);
5475 device->ws->destroy_syncobj(device->ws, point->syncobj);
5476 free(point);
5477 }
5478 pthread_mutex_destroy(&timeline->mutex);
5479 }
5480
5481 static void
5482 radv_timeline_gc_locked(struct radv_device *device,
5483 struct radv_timeline *timeline)
5484 {
5485 list_for_each_entry_safe(struct radv_timeline_point, point,
5486 &timeline->points, list) {
5487 if (point->wait_count || point->value > timeline->highest_submitted)
5488 return;
5489
5490 if (device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, 0)) {
5491 timeline->highest_signaled = point->value;
5492 list_del(&point->list);
5493 list_add(&point->list, &timeline->free_points);
5494 }
5495 }
5496 }
5497
5498 static struct radv_timeline_point *
5499 radv_timeline_find_point_at_least_locked(struct radv_device *device,
5500 struct radv_timeline *timeline,
5501 uint64_t p)
5502 {
5503 radv_timeline_gc_locked(device, timeline);
5504
5505 if (p <= timeline->highest_signaled)
5506 return NULL;
5507
5508 list_for_each_entry(struct radv_timeline_point, point,
5509 &timeline->points, list) {
5510 if (point->value >= p) {
5511 ++point->wait_count;
5512 return point;
5513 }
5514 }
5515 return NULL;
5516 }
5517
5518 static struct radv_timeline_point *
5519 radv_timeline_add_point_locked(struct radv_device *device,
5520 struct radv_timeline *timeline,
5521 uint64_t p)
5522 {
5523 radv_timeline_gc_locked(device, timeline);
5524
5525 struct radv_timeline_point *ret = NULL;
5526 struct radv_timeline_point *prev = NULL;
5527
5528 if (p <= timeline->highest_signaled)
5529 return NULL;
5530
5531 list_for_each_entry(struct radv_timeline_point, point,
5532 &timeline->points, list) {
5533 if (point->value == p) {
5534 return NULL;
5535 }
5536
5537 if (point->value < p)
5538 prev = point;
5539 }
5540
5541 if (list_is_empty(&timeline->free_points)) {
5542 ret = malloc(sizeof(struct radv_timeline_point));
5543 device->ws->create_syncobj(device->ws, &ret->syncobj);
5544 } else {
5545 ret = list_first_entry(&timeline->free_points, struct radv_timeline_point, list);
5546 list_del(&ret->list);
5547
5548 device->ws->reset_syncobj(device->ws, ret->syncobj);
5549 }
5550
5551 ret->value = p;
5552 ret->wait_count = 1;
5553
5554 if (prev) {
5555 list_add(&ret->list, &prev->list);
5556 } else {
5557 list_addtail(&ret->list, &timeline->points);
5558 }
5559 return ret;
5560 }
5561
5562
5563 static VkResult
5564 radv_timeline_wait_locked(struct radv_device *device,
5565 struct radv_timeline *timeline,
5566 uint64_t value,
5567 uint64_t abs_timeout)
5568 {
5569 while(timeline->highest_submitted < value) {
5570 struct timespec abstime;
5571 timespec_from_nsec(&abstime, abs_timeout);
5572
5573 pthread_cond_timedwait(&device->timeline_cond, &timeline->mutex, &abstime);
5574
5575 if (radv_get_current_time() >= abs_timeout && timeline->highest_submitted < value)
5576 return VK_TIMEOUT;
5577 }
5578
5579 struct radv_timeline_point *point = radv_timeline_find_point_at_least_locked(device, timeline, value);
5580 if (!point)
5581 return VK_SUCCESS;
5582
5583 pthread_mutex_unlock(&timeline->mutex);
5584
5585 bool success = device->ws->wait_syncobj(device->ws, &point->syncobj, 1, true, abs_timeout);
5586
5587 pthread_mutex_lock(&timeline->mutex);
5588 point->wait_count--;
5589 return success ? VK_SUCCESS : VK_TIMEOUT;
5590 }
5591
5592 static void
5593 radv_timeline_trigger_waiters_locked(struct radv_timeline *timeline,
5594 struct list_head *processing_list)
5595 {
5596 list_for_each_entry_safe(struct radv_timeline_waiter, waiter,
5597 &timeline->waiters, list) {
5598 if (waiter->value > timeline->highest_submitted)
5599 continue;
5600
5601 if (p_atomic_dec_zero(&waiter->submission->submission_wait_count)) {
5602 list_addtail(&waiter->submission->processing_list, processing_list);
5603 }
5604 list_del(&waiter->list);
5605 }
5606 }
5607
5608 static
5609 void radv_destroy_semaphore_part(struct radv_device *device,
5610 struct radv_semaphore_part *part)
5611 {
5612 switch(part->kind) {
5613 case RADV_SEMAPHORE_NONE:
5614 break;
5615 case RADV_SEMAPHORE_WINSYS:
5616 device->ws->destroy_sem(part->ws_sem);
5617 break;
5618 case RADV_SEMAPHORE_TIMELINE:
5619 radv_destroy_timeline(device, &part->timeline);
5620 break;
5621 case RADV_SEMAPHORE_SYNCOBJ:
5622 device->ws->destroy_syncobj(device->ws, part->syncobj);
5623 break;
5624 }
5625 part->kind = RADV_SEMAPHORE_NONE;
5626 }
5627
5628 static VkSemaphoreTypeKHR
5629 radv_get_semaphore_type(const void *pNext, uint64_t *initial_value)
5630 {
5631 const VkSemaphoreTypeCreateInfoKHR *type_info =
5632 vk_find_struct_const(pNext, SEMAPHORE_TYPE_CREATE_INFO_KHR);
5633
5634 if (!type_info)
5635 return VK_SEMAPHORE_TYPE_BINARY_KHR;
5636
5637 if (initial_value)
5638 *initial_value = type_info->initialValue;
5639 return type_info->semaphoreType;
5640 }
5641
5642 VkResult radv_CreateSemaphore(
5643 VkDevice _device,
5644 const VkSemaphoreCreateInfo* pCreateInfo,
5645 const VkAllocationCallbacks* pAllocator,
5646 VkSemaphore* pSemaphore)
5647 {
5648 RADV_FROM_HANDLE(radv_device, device, _device);
5649 const VkExportSemaphoreCreateInfo *export =
5650 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
5651 VkExternalSemaphoreHandleTypeFlags handleTypes =
5652 export ? export->handleTypes : 0;
5653 uint64_t initial_value = 0;
5654 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pCreateInfo->pNext, &initial_value);
5655
5656 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
5657 sizeof(*sem), 8,
5658 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5659 if (!sem)
5660 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5661
5662 sem->temporary.kind = RADV_SEMAPHORE_NONE;
5663 sem->permanent.kind = RADV_SEMAPHORE_NONE;
5664
5665 if (type == VK_SEMAPHORE_TYPE_TIMELINE_KHR) {
5666 radv_create_timeline(&sem->permanent.timeline, initial_value);
5667 sem->permanent.kind = RADV_SEMAPHORE_TIMELINE;
5668 } else if (device->always_use_syncobj || handleTypes) {
5669 assert (device->physical_device->rad_info.has_syncobj);
5670 int ret = device->ws->create_syncobj(device->ws, &sem->permanent.syncobj);
5671 if (ret) {
5672 vk_free2(&device->alloc, pAllocator, sem);
5673 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5674 }
5675 sem->permanent.kind = RADV_SEMAPHORE_SYNCOBJ;
5676 } else {
5677 sem->permanent.ws_sem = device->ws->create_sem(device->ws);
5678 if (!sem->permanent.ws_sem) {
5679 vk_free2(&device->alloc, pAllocator, sem);
5680 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5681 }
5682 sem->permanent.kind = RADV_SEMAPHORE_WINSYS;
5683 }
5684
5685 *pSemaphore = radv_semaphore_to_handle(sem);
5686 return VK_SUCCESS;
5687 }
5688
5689 void radv_DestroySemaphore(
5690 VkDevice _device,
5691 VkSemaphore _semaphore,
5692 const VkAllocationCallbacks* pAllocator)
5693 {
5694 RADV_FROM_HANDLE(radv_device, device, _device);
5695 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
5696 if (!_semaphore)
5697 return;
5698
5699 radv_destroy_semaphore_part(device, &sem->temporary);
5700 radv_destroy_semaphore_part(device, &sem->permanent);
5701 vk_free2(&device->alloc, pAllocator, sem);
5702 }
5703
5704 VkResult
5705 radv_GetSemaphoreCounterValueKHR(VkDevice _device,
5706 VkSemaphore _semaphore,
5707 uint64_t* pValue)
5708 {
5709 RADV_FROM_HANDLE(radv_device, device, _device);
5710 RADV_FROM_HANDLE(radv_semaphore, semaphore, _semaphore);
5711
5712 struct radv_semaphore_part *part =
5713 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5714
5715 switch (part->kind) {
5716 case RADV_SEMAPHORE_TIMELINE: {
5717 pthread_mutex_lock(&part->timeline.mutex);
5718 radv_timeline_gc_locked(device, &part->timeline);
5719 *pValue = part->timeline.highest_signaled;
5720 pthread_mutex_unlock(&part->timeline.mutex);
5721 return VK_SUCCESS;
5722 }
5723 case RADV_SEMAPHORE_NONE:
5724 case RADV_SEMAPHORE_SYNCOBJ:
5725 case RADV_SEMAPHORE_WINSYS:
5726 unreachable("Invalid semaphore type");
5727 }
5728 unreachable("Unhandled semaphore type");
5729 }
5730
5731
5732 static VkResult
5733 radv_wait_timelines(struct radv_device *device,
5734 const VkSemaphoreWaitInfoKHR* pWaitInfo,
5735 uint64_t abs_timeout)
5736 {
5737 if ((pWaitInfo->flags & VK_SEMAPHORE_WAIT_ANY_BIT_KHR) && pWaitInfo->semaphoreCount > 1) {
5738 for (;;) {
5739 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5740 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5741 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5742 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], 0);
5743 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5744
5745 if (result == VK_SUCCESS)
5746 return VK_SUCCESS;
5747 }
5748 if (radv_get_current_time() > abs_timeout)
5749 return VK_TIMEOUT;
5750 }
5751 }
5752
5753 for(uint32_t i = 0; i < pWaitInfo->semaphoreCount; ++i) {
5754 RADV_FROM_HANDLE(radv_semaphore, semaphore, pWaitInfo->pSemaphores[i]);
5755 pthread_mutex_lock(&semaphore->permanent.timeline.mutex);
5756 VkResult result = radv_timeline_wait_locked(device, &semaphore->permanent.timeline, pWaitInfo->pValues[i], abs_timeout);
5757 pthread_mutex_unlock(&semaphore->permanent.timeline.mutex);
5758
5759 if (result != VK_SUCCESS)
5760 return result;
5761 }
5762 return VK_SUCCESS;
5763 }
5764 VkResult
5765 radv_WaitSemaphoresKHR(VkDevice _device,
5766 const VkSemaphoreWaitInfoKHR* pWaitInfo,
5767 uint64_t timeout)
5768 {
5769 RADV_FROM_HANDLE(radv_device, device, _device);
5770 uint64_t abs_timeout = radv_get_absolute_timeout(timeout);
5771 return radv_wait_timelines(device, pWaitInfo, abs_timeout);
5772 }
5773
5774 VkResult
5775 radv_SignalSemaphoreKHR(VkDevice _device,
5776 const VkSemaphoreSignalInfoKHR* pSignalInfo)
5777 {
5778 RADV_FROM_HANDLE(radv_device, device, _device);
5779 RADV_FROM_HANDLE(radv_semaphore, semaphore, pSignalInfo->semaphore);
5780
5781 struct radv_semaphore_part *part =
5782 semaphore->temporary.kind != RADV_SEMAPHORE_NONE ? &semaphore->temporary : &semaphore->permanent;
5783
5784 switch(part->kind) {
5785 case RADV_SEMAPHORE_TIMELINE: {
5786 pthread_mutex_lock(&part->timeline.mutex);
5787 radv_timeline_gc_locked(device, &part->timeline);
5788 part->timeline.highest_submitted = MAX2(part->timeline.highest_submitted, pSignalInfo->value);
5789 part->timeline.highest_signaled = MAX2(part->timeline.highest_signaled, pSignalInfo->value);
5790
5791 struct list_head processing_list;
5792 list_inithead(&processing_list);
5793 radv_timeline_trigger_waiters_locked(&part->timeline, &processing_list);
5794 pthread_mutex_unlock(&part->timeline.mutex);
5795
5796 return radv_process_submissions(&processing_list);
5797 }
5798 case RADV_SEMAPHORE_NONE:
5799 case RADV_SEMAPHORE_SYNCOBJ:
5800 case RADV_SEMAPHORE_WINSYS:
5801 unreachable("Invalid semaphore type");
5802 }
5803 return VK_SUCCESS;
5804 }
5805
5806
5807
5808 VkResult radv_CreateEvent(
5809 VkDevice _device,
5810 const VkEventCreateInfo* pCreateInfo,
5811 const VkAllocationCallbacks* pAllocator,
5812 VkEvent* pEvent)
5813 {
5814 RADV_FROM_HANDLE(radv_device, device, _device);
5815 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
5816 sizeof(*event), 8,
5817 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5818
5819 if (!event)
5820 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5821
5822 event->bo = device->ws->buffer_create(device->ws, 8, 8,
5823 RADEON_DOMAIN_GTT,
5824 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
5825 RADV_BO_PRIORITY_FENCE);
5826 if (!event->bo) {
5827 vk_free2(&device->alloc, pAllocator, event);
5828 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5829 }
5830
5831 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
5832
5833 *pEvent = radv_event_to_handle(event);
5834
5835 return VK_SUCCESS;
5836 }
5837
5838 void radv_DestroyEvent(
5839 VkDevice _device,
5840 VkEvent _event,
5841 const VkAllocationCallbacks* pAllocator)
5842 {
5843 RADV_FROM_HANDLE(radv_device, device, _device);
5844 RADV_FROM_HANDLE(radv_event, event, _event);
5845
5846 if (!event)
5847 return;
5848 device->ws->buffer_destroy(event->bo);
5849 vk_free2(&device->alloc, pAllocator, event);
5850 }
5851
5852 VkResult radv_GetEventStatus(
5853 VkDevice _device,
5854 VkEvent _event)
5855 {
5856 RADV_FROM_HANDLE(radv_event, event, _event);
5857
5858 if (*event->map == 1)
5859 return VK_EVENT_SET;
5860 return VK_EVENT_RESET;
5861 }
5862
5863 VkResult radv_SetEvent(
5864 VkDevice _device,
5865 VkEvent _event)
5866 {
5867 RADV_FROM_HANDLE(radv_event, event, _event);
5868 *event->map = 1;
5869
5870 return VK_SUCCESS;
5871 }
5872
5873 VkResult radv_ResetEvent(
5874 VkDevice _device,
5875 VkEvent _event)
5876 {
5877 RADV_FROM_HANDLE(radv_event, event, _event);
5878 *event->map = 0;
5879
5880 return VK_SUCCESS;
5881 }
5882
5883 VkResult radv_CreateBuffer(
5884 VkDevice _device,
5885 const VkBufferCreateInfo* pCreateInfo,
5886 const VkAllocationCallbacks* pAllocator,
5887 VkBuffer* pBuffer)
5888 {
5889 RADV_FROM_HANDLE(radv_device, device, _device);
5890 struct radv_buffer *buffer;
5891
5892 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
5893
5894 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
5895 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5896 if (buffer == NULL)
5897 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5898
5899 buffer->size = pCreateInfo->size;
5900 buffer->usage = pCreateInfo->usage;
5901 buffer->bo = NULL;
5902 buffer->offset = 0;
5903 buffer->flags = pCreateInfo->flags;
5904
5905 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
5906 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
5907
5908 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
5909 buffer->bo = device->ws->buffer_create(device->ws,
5910 align64(buffer->size, 4096),
5911 4096, 0, RADEON_FLAG_VIRTUAL,
5912 RADV_BO_PRIORITY_VIRTUAL);
5913 if (!buffer->bo) {
5914 vk_free2(&device->alloc, pAllocator, buffer);
5915 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5916 }
5917 }
5918
5919 *pBuffer = radv_buffer_to_handle(buffer);
5920
5921 return VK_SUCCESS;
5922 }
5923
5924 void radv_DestroyBuffer(
5925 VkDevice _device,
5926 VkBuffer _buffer,
5927 const VkAllocationCallbacks* pAllocator)
5928 {
5929 RADV_FROM_HANDLE(radv_device, device, _device);
5930 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
5931
5932 if (!buffer)
5933 return;
5934
5935 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
5936 device->ws->buffer_destroy(buffer->bo);
5937
5938 vk_free2(&device->alloc, pAllocator, buffer);
5939 }
5940
5941 VkDeviceAddress radv_GetBufferDeviceAddressKHR(
5942 VkDevice device,
5943 const VkBufferDeviceAddressInfoKHR* pInfo)
5944 {
5945 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
5946 return radv_buffer_get_va(buffer->bo) + buffer->offset;
5947 }
5948
5949
5950 uint64_t radv_GetBufferOpaqueCaptureAddressKHR(VkDevice device,
5951 const VkBufferDeviceAddressInfoKHR* pInfo)
5952 {
5953 return 0;
5954 }
5955
5956 uint64_t radv_GetDeviceMemoryOpaqueCaptureAddressKHR(VkDevice device,
5957 const VkDeviceMemoryOpaqueCaptureAddressInfoKHR* pInfo)
5958 {
5959 return 0;
5960 }
5961
5962 static inline unsigned
5963 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
5964 {
5965 if (stencil)
5966 return plane->surface.u.legacy.stencil_tiling_index[level];
5967 else
5968 return plane->surface.u.legacy.tiling_index[level];
5969 }
5970
5971 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
5972 {
5973 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
5974 }
5975
5976 static uint32_t
5977 radv_init_dcc_control_reg(struct radv_device *device,
5978 struct radv_image_view *iview)
5979 {
5980 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
5981 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
5982 unsigned max_compressed_block_size;
5983 unsigned independent_128b_blocks;
5984 unsigned independent_64b_blocks;
5985
5986 if (!radv_dcc_enabled(iview->image, iview->base_mip))
5987 return 0;
5988
5989 if (!device->physical_device->rad_info.has_dedicated_vram) {
5990 /* amdvlk: [min-compressed-block-size] should be set to 32 for
5991 * dGPU and 64 for APU because all of our APUs to date use
5992 * DIMMs which have a request granularity size of 64B while all
5993 * other chips have a 32B request size.
5994 */
5995 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
5996 }
5997
5998 if (device->physical_device->rad_info.chip_class >= GFX10) {
5999 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6000 independent_64b_blocks = 0;
6001 independent_128b_blocks = 1;
6002 } else {
6003 independent_128b_blocks = 0;
6004
6005 if (iview->image->info.samples > 1) {
6006 if (iview->image->planes[0].surface.bpe == 1)
6007 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6008 else if (iview->image->planes[0].surface.bpe == 2)
6009 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
6010 }
6011
6012 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
6013 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
6014 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
6015 /* If this DCC image is potentially going to be used in texture
6016 * fetches, we need some special settings.
6017 */
6018 independent_64b_blocks = 1;
6019 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
6020 } else {
6021 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
6022 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
6023 * big as possible for better compression state.
6024 */
6025 independent_64b_blocks = 0;
6026 max_compressed_block_size = max_uncompressed_block_size;
6027 }
6028 }
6029
6030 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
6031 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
6032 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
6033 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
6034 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
6035 }
6036
6037 void
6038 radv_initialise_color_surface(struct radv_device *device,
6039 struct radv_color_buffer_info *cb,
6040 struct radv_image_view *iview)
6041 {
6042 const struct vk_format_description *desc;
6043 unsigned ntype, format, swap, endian;
6044 unsigned blend_clamp = 0, blend_bypass = 0;
6045 uint64_t va;
6046 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
6047 const struct radeon_surf *surf = &plane->surface;
6048
6049 desc = vk_format_description(iview->vk_format);
6050
6051 memset(cb, 0, sizeof(*cb));
6052
6053 /* Intensity is implemented as Red, so treat it that way. */
6054 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
6055
6056 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
6057
6058 cb->cb_color_base = va >> 8;
6059
6060 if (device->physical_device->rad_info.chip_class >= GFX9) {
6061 struct gfx9_surf_meta_flags meta;
6062 if (iview->image->dcc_offset)
6063 meta = surf->u.gfx9.dcc;
6064 else
6065 meta = surf->u.gfx9.cmask;
6066
6067 if (device->physical_device->rad_info.chip_class >= GFX10) {
6068 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6069 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6070 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
6071 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
6072 } else {
6073 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6074 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
6075 S_028C74_RB_ALIGNED(meta.rb_aligned) |
6076 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
6077 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
6078 }
6079
6080 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
6081 cb->cb_color_base |= surf->tile_swizzle;
6082 } else {
6083 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
6084 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
6085
6086 cb->cb_color_base += level_info->offset >> 8;
6087 if (level_info->mode == RADEON_SURF_MODE_2D)
6088 cb->cb_color_base |= surf->tile_swizzle;
6089
6090 pitch_tile_max = level_info->nblk_x / 8 - 1;
6091 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
6092 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
6093
6094 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
6095 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
6096 cb->cb_color_cmask_slice = surf->u.legacy.cmask_slice_tile_max;
6097
6098 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
6099
6100 if (radv_image_has_fmask(iview->image)) {
6101 if (device->physical_device->rad_info.chip_class >= GFX7)
6102 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(surf->u.legacy.fmask.pitch_in_pixels / 8 - 1);
6103 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(surf->u.legacy.fmask.tiling_index);
6104 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(surf->u.legacy.fmask.slice_tile_max);
6105 } else {
6106 /* This must be set for fast clear to work without FMASK. */
6107 if (device->physical_device->rad_info.chip_class >= GFX7)
6108 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
6109 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
6110 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
6111 }
6112 }
6113
6114 /* CMASK variables */
6115 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6116 va += iview->image->cmask_offset;
6117 cb->cb_color_cmask = va >> 8;
6118
6119 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6120 va += iview->image->dcc_offset;
6121
6122 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
6123 device->physical_device->rad_info.chip_class <= GFX8)
6124 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
6125
6126 unsigned dcc_tile_swizzle = surf->tile_swizzle;
6127 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
6128
6129 cb->cb_dcc_base = va >> 8;
6130 cb->cb_dcc_base |= dcc_tile_swizzle;
6131
6132 /* GFX10 field has the same base shift as the GFX6 field. */
6133 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6134 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
6135 S_028C6C_SLICE_MAX_GFX10(max_slice);
6136
6137 if (iview->image->info.samples > 1) {
6138 unsigned log_samples = util_logbase2(iview->image->info.samples);
6139
6140 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
6141 S_028C74_NUM_FRAGMENTS(log_samples);
6142 }
6143
6144 if (radv_image_has_fmask(iview->image)) {
6145 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask_offset;
6146 cb->cb_color_fmask = va >> 8;
6147 cb->cb_color_fmask |= surf->fmask_tile_swizzle;
6148 } else {
6149 cb->cb_color_fmask = cb->cb_color_base;
6150 }
6151
6152 ntype = radv_translate_color_numformat(iview->vk_format,
6153 desc,
6154 vk_format_get_first_non_void_channel(iview->vk_format));
6155 format = radv_translate_colorformat(iview->vk_format);
6156 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
6157 radv_finishme("Illegal color\n");
6158 swap = radv_translate_colorswap(iview->vk_format, false);
6159 endian = radv_colorformat_endian_swap(format);
6160
6161 /* blend clamp should be set for all NORM/SRGB types */
6162 if (ntype == V_028C70_NUMBER_UNORM ||
6163 ntype == V_028C70_NUMBER_SNORM ||
6164 ntype == V_028C70_NUMBER_SRGB)
6165 blend_clamp = 1;
6166
6167 /* set blend bypass according to docs if SINT/UINT or
6168 8/24 COLOR variants */
6169 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
6170 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
6171 format == V_028C70_COLOR_X24_8_32_FLOAT) {
6172 blend_clamp = 0;
6173 blend_bypass = 1;
6174 }
6175 #if 0
6176 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
6177 (format == V_028C70_COLOR_8 ||
6178 format == V_028C70_COLOR_8_8 ||
6179 format == V_028C70_COLOR_8_8_8_8))
6180 ->color_is_int8 = true;
6181 #endif
6182 cb->cb_color_info = S_028C70_FORMAT(format) |
6183 S_028C70_COMP_SWAP(swap) |
6184 S_028C70_BLEND_CLAMP(blend_clamp) |
6185 S_028C70_BLEND_BYPASS(blend_bypass) |
6186 S_028C70_SIMPLE_FLOAT(1) |
6187 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
6188 ntype != V_028C70_NUMBER_SNORM &&
6189 ntype != V_028C70_NUMBER_SRGB &&
6190 format != V_028C70_COLOR_8_24 &&
6191 format != V_028C70_COLOR_24_8) |
6192 S_028C70_NUMBER_TYPE(ntype) |
6193 S_028C70_ENDIAN(endian);
6194 if (radv_image_has_fmask(iview->image)) {
6195 cb->cb_color_info |= S_028C70_COMPRESSION(1);
6196 if (device->physical_device->rad_info.chip_class == GFX6) {
6197 unsigned fmask_bankh = util_logbase2(surf->u.legacy.fmask.bankh);
6198 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
6199 }
6200
6201 if (radv_image_is_tc_compat_cmask(iview->image)) {
6202 /* Allow the texture block to read FMASK directly
6203 * without decompressing it. This bit must be cleared
6204 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
6205 * otherwise the operation doesn't happen.
6206 */
6207 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
6208
6209 /* Set CMASK into a tiling format that allows the
6210 * texture block to read it.
6211 */
6212 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
6213 }
6214 }
6215
6216 if (radv_image_has_cmask(iview->image) &&
6217 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
6218 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
6219
6220 if (radv_dcc_enabled(iview->image, iview->base_mip))
6221 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
6222
6223 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
6224
6225 /* This must be set for fast clear to work without FMASK. */
6226 if (!radv_image_has_fmask(iview->image) &&
6227 device->physical_device->rad_info.chip_class == GFX6) {
6228 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
6229 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
6230 }
6231
6232 if (device->physical_device->rad_info.chip_class >= GFX9) {
6233 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
6234
6235 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
6236 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
6237 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
6238 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
6239
6240 if (device->physical_device->rad_info.chip_class >= GFX10) {
6241 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
6242
6243 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
6244 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
6245 S_028EE0_RESOURCE_LEVEL(1);
6246 } else {
6247 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
6248 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
6249 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
6250 }
6251
6252 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
6253 S_028C68_MIP0_HEIGHT(height - 1) |
6254 S_028C68_MAX_MIP(iview->image->info.levels - 1);
6255 }
6256 }
6257
6258 static unsigned
6259 radv_calc_decompress_on_z_planes(struct radv_device *device,
6260 struct radv_image_view *iview)
6261 {
6262 unsigned max_zplanes = 0;
6263
6264 assert(radv_image_is_tc_compat_htile(iview->image));
6265
6266 if (device->physical_device->rad_info.chip_class >= GFX9) {
6267 /* Default value for 32-bit depth surfaces. */
6268 max_zplanes = 4;
6269
6270 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
6271 iview->image->info.samples > 1)
6272 max_zplanes = 2;
6273
6274 max_zplanes = max_zplanes + 1;
6275 } else {
6276 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
6277 /* Do not enable Z plane compression for 16-bit depth
6278 * surfaces because isn't supported on GFX8. Only
6279 * 32-bit depth surfaces are supported by the hardware.
6280 * This allows to maintain shader compatibility and to
6281 * reduce the number of depth decompressions.
6282 */
6283 max_zplanes = 1;
6284 } else {
6285 if (iview->image->info.samples <= 1)
6286 max_zplanes = 5;
6287 else if (iview->image->info.samples <= 4)
6288 max_zplanes = 3;
6289 else
6290 max_zplanes = 2;
6291 }
6292 }
6293
6294 return max_zplanes;
6295 }
6296
6297 void
6298 radv_initialise_ds_surface(struct radv_device *device,
6299 struct radv_ds_buffer_info *ds,
6300 struct radv_image_view *iview)
6301 {
6302 unsigned level = iview->base_mip;
6303 unsigned format, stencil_format;
6304 uint64_t va, s_offs, z_offs;
6305 bool stencil_only = false;
6306 const struct radv_image_plane *plane = &iview->image->planes[0];
6307 const struct radeon_surf *surf = &plane->surface;
6308
6309 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
6310
6311 memset(ds, 0, sizeof(*ds));
6312 switch (iview->image->vk_format) {
6313 case VK_FORMAT_D24_UNORM_S8_UINT:
6314 case VK_FORMAT_X8_D24_UNORM_PACK32:
6315 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
6316 ds->offset_scale = 2.0f;
6317 break;
6318 case VK_FORMAT_D16_UNORM:
6319 case VK_FORMAT_D16_UNORM_S8_UINT:
6320 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
6321 ds->offset_scale = 4.0f;
6322 break;
6323 case VK_FORMAT_D32_SFLOAT:
6324 case VK_FORMAT_D32_SFLOAT_S8_UINT:
6325 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
6326 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
6327 ds->offset_scale = 1.0f;
6328 break;
6329 case VK_FORMAT_S8_UINT:
6330 stencil_only = true;
6331 break;
6332 default:
6333 break;
6334 }
6335
6336 format = radv_translate_dbformat(iview->image->vk_format);
6337 stencil_format = surf->has_stencil ?
6338 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
6339
6340 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
6341 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
6342 S_028008_SLICE_MAX(max_slice);
6343 if (device->physical_device->rad_info.chip_class >= GFX10) {
6344 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
6345 S_028008_SLICE_MAX_HI(max_slice >> 11);
6346 }
6347
6348 ds->db_htile_data_base = 0;
6349 ds->db_htile_surface = 0;
6350
6351 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
6352 s_offs = z_offs = va;
6353
6354 if (device->physical_device->rad_info.chip_class >= GFX9) {
6355 assert(surf->u.gfx9.surf_offset == 0);
6356 s_offs += surf->u.gfx9.stencil_offset;
6357
6358 ds->db_z_info = S_028038_FORMAT(format) |
6359 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
6360 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
6361 S_028038_MAXMIP(iview->image->info.levels - 1) |
6362 S_028038_ZRANGE_PRECISION(1);
6363 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
6364 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
6365
6366 if (device->physical_device->rad_info.chip_class == GFX9) {
6367 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
6368 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
6369 }
6370
6371 ds->db_depth_view |= S_028008_MIPID(level);
6372 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
6373 S_02801C_Y_MAX(iview->image->info.height - 1);
6374
6375 if (radv_htile_enabled(iview->image, level)) {
6376 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
6377
6378 if (radv_image_is_tc_compat_htile(iview->image)) {
6379 unsigned max_zplanes =
6380 radv_calc_decompress_on_z_planes(device, iview);
6381
6382 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6383
6384 if (device->physical_device->rad_info.chip_class >= GFX10) {
6385 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
6386 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
6387 } else {
6388 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
6389 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
6390 }
6391 }
6392
6393 if (!surf->has_stencil)
6394 /* Use all of the htile_buffer for depth if there's no stencil. */
6395 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
6396 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6397 iview->image->htile_offset;
6398 ds->db_htile_data_base = va >> 8;
6399 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
6400 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
6401
6402 if (device->physical_device->rad_info.chip_class == GFX9) {
6403 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
6404 }
6405 }
6406 } else {
6407 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
6408
6409 if (stencil_only)
6410 level_info = &surf->u.legacy.stencil_level[level];
6411
6412 z_offs += surf->u.legacy.level[level].offset;
6413 s_offs += surf->u.legacy.stencil_level[level].offset;
6414
6415 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
6416 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
6417 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
6418
6419 if (iview->image->info.samples > 1)
6420 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
6421
6422 if (device->physical_device->rad_info.chip_class >= GFX7) {
6423 struct radeon_info *info = &device->physical_device->rad_info;
6424 unsigned tiling_index = surf->u.legacy.tiling_index[level];
6425 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
6426 unsigned macro_index = surf->u.legacy.macro_tile_index;
6427 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
6428 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
6429 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
6430
6431 if (stencil_only)
6432 tile_mode = stencil_tile_mode;
6433
6434 ds->db_depth_info |=
6435 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
6436 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
6437 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
6438 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
6439 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
6440 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
6441 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
6442 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
6443 } else {
6444 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
6445 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6446 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
6447 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
6448 if (stencil_only)
6449 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
6450 }
6451
6452 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
6453 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
6454 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
6455
6456 if (radv_htile_enabled(iview->image, level)) {
6457 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
6458
6459 if (!surf->has_stencil &&
6460 !radv_image_is_tc_compat_htile(iview->image))
6461 /* Use all of the htile_buffer for depth if there's no stencil. */
6462 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
6463
6464 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
6465 iview->image->htile_offset;
6466 ds->db_htile_data_base = va >> 8;
6467 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
6468
6469 if (radv_image_is_tc_compat_htile(iview->image)) {
6470 unsigned max_zplanes =
6471 radv_calc_decompress_on_z_planes(device, iview);
6472
6473 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
6474 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
6475 }
6476 }
6477 }
6478
6479 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
6480 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
6481 }
6482
6483 VkResult radv_CreateFramebuffer(
6484 VkDevice _device,
6485 const VkFramebufferCreateInfo* pCreateInfo,
6486 const VkAllocationCallbacks* pAllocator,
6487 VkFramebuffer* pFramebuffer)
6488 {
6489 RADV_FROM_HANDLE(radv_device, device, _device);
6490 struct radv_framebuffer *framebuffer;
6491 const VkFramebufferAttachmentsCreateInfoKHR *imageless_create_info =
6492 vk_find_struct_const(pCreateInfo->pNext,
6493 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR);
6494
6495 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
6496
6497 size_t size = sizeof(*framebuffer);
6498 if (!imageless_create_info)
6499 size += sizeof(struct radv_image_view*) * pCreateInfo->attachmentCount;
6500 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
6501 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6502 if (framebuffer == NULL)
6503 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6504
6505 framebuffer->attachment_count = pCreateInfo->attachmentCount;
6506 framebuffer->width = pCreateInfo->width;
6507 framebuffer->height = pCreateInfo->height;
6508 framebuffer->layers = pCreateInfo->layers;
6509 if (imageless_create_info) {
6510 for (unsigned i = 0; i < imageless_create_info->attachmentImageInfoCount; ++i) {
6511 const VkFramebufferAttachmentImageInfoKHR *attachment =
6512 imageless_create_info->pAttachmentImageInfos + i;
6513 framebuffer->width = MIN2(framebuffer->width, attachment->width);
6514 framebuffer->height = MIN2(framebuffer->height, attachment->height);
6515 framebuffer->layers = MIN2(framebuffer->layers, attachment->layerCount);
6516 }
6517 } else {
6518 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
6519 VkImageView _iview = pCreateInfo->pAttachments[i];
6520 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
6521 framebuffer->attachments[i] = iview;
6522 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
6523 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
6524 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
6525 }
6526 }
6527
6528 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
6529 return VK_SUCCESS;
6530 }
6531
6532 void radv_DestroyFramebuffer(
6533 VkDevice _device,
6534 VkFramebuffer _fb,
6535 const VkAllocationCallbacks* pAllocator)
6536 {
6537 RADV_FROM_HANDLE(radv_device, device, _device);
6538 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
6539
6540 if (!fb)
6541 return;
6542 vk_free2(&device->alloc, pAllocator, fb);
6543 }
6544
6545 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
6546 {
6547 switch (address_mode) {
6548 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
6549 return V_008F30_SQ_TEX_WRAP;
6550 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
6551 return V_008F30_SQ_TEX_MIRROR;
6552 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
6553 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
6554 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
6555 return V_008F30_SQ_TEX_CLAMP_BORDER;
6556 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
6557 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
6558 default:
6559 unreachable("illegal tex wrap mode");
6560 break;
6561 }
6562 }
6563
6564 static unsigned
6565 radv_tex_compare(VkCompareOp op)
6566 {
6567 switch (op) {
6568 case VK_COMPARE_OP_NEVER:
6569 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
6570 case VK_COMPARE_OP_LESS:
6571 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
6572 case VK_COMPARE_OP_EQUAL:
6573 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
6574 case VK_COMPARE_OP_LESS_OR_EQUAL:
6575 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
6576 case VK_COMPARE_OP_GREATER:
6577 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
6578 case VK_COMPARE_OP_NOT_EQUAL:
6579 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
6580 case VK_COMPARE_OP_GREATER_OR_EQUAL:
6581 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
6582 case VK_COMPARE_OP_ALWAYS:
6583 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
6584 default:
6585 unreachable("illegal compare mode");
6586 break;
6587 }
6588 }
6589
6590 static unsigned
6591 radv_tex_filter(VkFilter filter, unsigned max_ansio)
6592 {
6593 switch (filter) {
6594 case VK_FILTER_NEAREST:
6595 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
6596 V_008F38_SQ_TEX_XY_FILTER_POINT);
6597 case VK_FILTER_LINEAR:
6598 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
6599 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
6600 case VK_FILTER_CUBIC_IMG:
6601 default:
6602 fprintf(stderr, "illegal texture filter");
6603 return 0;
6604 }
6605 }
6606
6607 static unsigned
6608 radv_tex_mipfilter(VkSamplerMipmapMode mode)
6609 {
6610 switch (mode) {
6611 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
6612 return V_008F38_SQ_TEX_Z_FILTER_POINT;
6613 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
6614 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
6615 default:
6616 return V_008F38_SQ_TEX_Z_FILTER_NONE;
6617 }
6618 }
6619
6620 static unsigned
6621 radv_tex_bordercolor(VkBorderColor bcolor)
6622 {
6623 switch (bcolor) {
6624 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
6625 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
6626 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
6627 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
6628 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
6629 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
6630 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
6631 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
6632 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
6633 default:
6634 break;
6635 }
6636 return 0;
6637 }
6638
6639 static unsigned
6640 radv_tex_aniso_filter(unsigned filter)
6641 {
6642 if (filter < 2)
6643 return 0;
6644 if (filter < 4)
6645 return 1;
6646 if (filter < 8)
6647 return 2;
6648 if (filter < 16)
6649 return 3;
6650 return 4;
6651 }
6652
6653 static unsigned
6654 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
6655 {
6656 switch (mode) {
6657 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
6658 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6659 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
6660 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
6661 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
6662 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
6663 default:
6664 break;
6665 }
6666 return 0;
6667 }
6668
6669 static uint32_t
6670 radv_get_max_anisotropy(struct radv_device *device,
6671 const VkSamplerCreateInfo *pCreateInfo)
6672 {
6673 if (device->force_aniso >= 0)
6674 return device->force_aniso;
6675
6676 if (pCreateInfo->anisotropyEnable &&
6677 pCreateInfo->maxAnisotropy > 1.0f)
6678 return (uint32_t)pCreateInfo->maxAnisotropy;
6679
6680 return 0;
6681 }
6682
6683 static void
6684 radv_init_sampler(struct radv_device *device,
6685 struct radv_sampler *sampler,
6686 const VkSamplerCreateInfo *pCreateInfo)
6687 {
6688 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
6689 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
6690 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
6691 device->physical_device->rad_info.chip_class == GFX9;
6692 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
6693
6694 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
6695 vk_find_struct_const(pCreateInfo->pNext,
6696 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
6697 if (sampler_reduction)
6698 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
6699
6700 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
6701 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
6702 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
6703 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
6704 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
6705 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
6706 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
6707 S_008F30_ANISO_BIAS(max_aniso_ratio) |
6708 S_008F30_DISABLE_CUBE_WRAP(0) |
6709 S_008F30_COMPAT_MODE(compat_mode) |
6710 S_008F30_FILTER_MODE(filter_mode));
6711 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
6712 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
6713 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
6714 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
6715 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
6716 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
6717 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
6718 S_008F38_MIP_POINT_PRECLAMP(0));
6719 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
6720 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
6721
6722 if (device->physical_device->rad_info.chip_class >= GFX10) {
6723 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
6724 } else {
6725 sampler->state[2] |=
6726 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
6727 S_008F38_FILTER_PREC_FIX(1) |
6728 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
6729 }
6730 }
6731
6732 VkResult radv_CreateSampler(
6733 VkDevice _device,
6734 const VkSamplerCreateInfo* pCreateInfo,
6735 const VkAllocationCallbacks* pAllocator,
6736 VkSampler* pSampler)
6737 {
6738 RADV_FROM_HANDLE(radv_device, device, _device);
6739 struct radv_sampler *sampler;
6740
6741 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
6742 vk_find_struct_const(pCreateInfo->pNext,
6743 SAMPLER_YCBCR_CONVERSION_INFO);
6744
6745 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
6746
6747 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
6748 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
6749 if (!sampler)
6750 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
6751
6752 radv_init_sampler(device, sampler, pCreateInfo);
6753
6754 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
6755 *pSampler = radv_sampler_to_handle(sampler);
6756
6757 return VK_SUCCESS;
6758 }
6759
6760 void radv_DestroySampler(
6761 VkDevice _device,
6762 VkSampler _sampler,
6763 const VkAllocationCallbacks* pAllocator)
6764 {
6765 RADV_FROM_HANDLE(radv_device, device, _device);
6766 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
6767
6768 if (!sampler)
6769 return;
6770 vk_free2(&device->alloc, pAllocator, sampler);
6771 }
6772
6773 /* vk_icd.h does not declare this function, so we declare it here to
6774 * suppress Wmissing-prototypes.
6775 */
6776 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6777 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
6778
6779 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
6780 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
6781 {
6782 /* For the full details on loader interface versioning, see
6783 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
6784 * What follows is a condensed summary, to help you navigate the large and
6785 * confusing official doc.
6786 *
6787 * - Loader interface v0 is incompatible with later versions. We don't
6788 * support it.
6789 *
6790 * - In loader interface v1:
6791 * - The first ICD entrypoint called by the loader is
6792 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
6793 * entrypoint.
6794 * - The ICD must statically expose no other Vulkan symbol unless it is
6795 * linked with -Bsymbolic.
6796 * - Each dispatchable Vulkan handle created by the ICD must be
6797 * a pointer to a struct whose first member is VK_LOADER_DATA. The
6798 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
6799 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
6800 * vkDestroySurfaceKHR(). The ICD must be capable of working with
6801 * such loader-managed surfaces.
6802 *
6803 * - Loader interface v2 differs from v1 in:
6804 * - The first ICD entrypoint called by the loader is
6805 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
6806 * statically expose this entrypoint.
6807 *
6808 * - Loader interface v3 differs from v2 in:
6809 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
6810 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
6811 * because the loader no longer does so.
6812 */
6813 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
6814 return VK_SUCCESS;
6815 }
6816
6817 VkResult radv_GetMemoryFdKHR(VkDevice _device,
6818 const VkMemoryGetFdInfoKHR *pGetFdInfo,
6819 int *pFD)
6820 {
6821 RADV_FROM_HANDLE(radv_device, device, _device);
6822 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
6823
6824 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
6825
6826 /* At the moment, we support only the below handle types. */
6827 assert(pGetFdInfo->handleType ==
6828 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
6829 pGetFdInfo->handleType ==
6830 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
6831
6832 bool ret = radv_get_memory_fd(device, memory, pFD);
6833 if (ret == false)
6834 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
6835 return VK_SUCCESS;
6836 }
6837
6838 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
6839 VkExternalMemoryHandleTypeFlagBits handleType,
6840 int fd,
6841 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
6842 {
6843 RADV_FROM_HANDLE(radv_device, device, _device);
6844
6845 switch (handleType) {
6846 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
6847 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
6848 return VK_SUCCESS;
6849
6850 default:
6851 /* The valid usage section for this function says:
6852 *
6853 * "handleType must not be one of the handle types defined as
6854 * opaque."
6855 *
6856 * So opaque handle types fall into the default "unsupported" case.
6857 */
6858 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6859 }
6860 }
6861
6862 static VkResult radv_import_opaque_fd(struct radv_device *device,
6863 int fd,
6864 uint32_t *syncobj)
6865 {
6866 uint32_t syncobj_handle = 0;
6867 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
6868 if (ret != 0)
6869 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6870
6871 if (*syncobj)
6872 device->ws->destroy_syncobj(device->ws, *syncobj);
6873
6874 *syncobj = syncobj_handle;
6875 close(fd);
6876
6877 return VK_SUCCESS;
6878 }
6879
6880 static VkResult radv_import_sync_fd(struct radv_device *device,
6881 int fd,
6882 uint32_t *syncobj)
6883 {
6884 /* If we create a syncobj we do it locally so that if we have an error, we don't
6885 * leave a syncobj in an undetermined state in the fence. */
6886 uint32_t syncobj_handle = *syncobj;
6887 if (!syncobj_handle) {
6888 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
6889 if (ret) {
6890 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6891 }
6892 }
6893
6894 if (fd == -1) {
6895 device->ws->signal_syncobj(device->ws, syncobj_handle);
6896 } else {
6897 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
6898 if (ret != 0)
6899 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6900 }
6901
6902 *syncobj = syncobj_handle;
6903 if (fd != -1)
6904 close(fd);
6905
6906 return VK_SUCCESS;
6907 }
6908
6909 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
6910 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
6911 {
6912 RADV_FROM_HANDLE(radv_device, device, _device);
6913 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
6914 VkResult result;
6915 struct radv_semaphore_part *dst = NULL;
6916
6917 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
6918 dst = &sem->temporary;
6919 } else {
6920 dst = &sem->permanent;
6921 }
6922
6923 uint32_t syncobj = dst->kind == RADV_SEMAPHORE_SYNCOBJ ? dst->syncobj : 0;
6924
6925 switch(pImportSemaphoreFdInfo->handleType) {
6926 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
6927 result = radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
6928 break;
6929 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
6930 result = radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, &syncobj);
6931 break;
6932 default:
6933 unreachable("Unhandled semaphore handle type");
6934 }
6935
6936 if (result == VK_SUCCESS) {
6937 dst->syncobj = syncobj;
6938 dst->kind = RADV_SEMAPHORE_SYNCOBJ;
6939 }
6940
6941 return result;
6942 }
6943
6944 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
6945 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
6946 int *pFd)
6947 {
6948 RADV_FROM_HANDLE(radv_device, device, _device);
6949 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
6950 int ret;
6951 uint32_t syncobj_handle;
6952
6953 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
6954 assert(sem->temporary.kind == RADV_SEMAPHORE_SYNCOBJ);
6955 syncobj_handle = sem->temporary.syncobj;
6956 } else {
6957 assert(sem->permanent.kind == RADV_SEMAPHORE_SYNCOBJ);
6958 syncobj_handle = sem->permanent.syncobj;
6959 }
6960
6961 switch(pGetFdInfo->handleType) {
6962 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
6963 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
6964 break;
6965 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
6966 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
6967 if (!ret) {
6968 if (sem->temporary.kind != RADV_SEMAPHORE_NONE) {
6969 radv_destroy_semaphore_part(device, &sem->temporary);
6970 } else {
6971 device->ws->reset_syncobj(device->ws, syncobj_handle);
6972 }
6973 }
6974 break;
6975 default:
6976 unreachable("Unhandled semaphore handle type");
6977 }
6978
6979 if (ret)
6980 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
6981 return VK_SUCCESS;
6982 }
6983
6984 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
6985 VkPhysicalDevice physicalDevice,
6986 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
6987 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
6988 {
6989 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
6990 VkSemaphoreTypeKHR type = radv_get_semaphore_type(pExternalSemaphoreInfo->pNext, NULL);
6991
6992 if (type == VK_SEMAPHORE_TYPE_TIMELINE_KHR) {
6993 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
6994 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
6995 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
6996
6997 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
6998 } else if (pdevice->rad_info.has_syncobj_wait_for_submit &&
6999 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7000 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
7001 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7002 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
7003 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7004 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7005 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
7006 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7007 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
7008 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
7009 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7010 } else {
7011 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
7012 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
7013 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
7014 }
7015 }
7016
7017 VkResult radv_ImportFenceFdKHR(VkDevice _device,
7018 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
7019 {
7020 RADV_FROM_HANDLE(radv_device, device, _device);
7021 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
7022 uint32_t *syncobj_dst = NULL;
7023
7024
7025 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
7026 syncobj_dst = &fence->temp_syncobj;
7027 } else {
7028 syncobj_dst = &fence->syncobj;
7029 }
7030
7031 switch(pImportFenceFdInfo->handleType) {
7032 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7033 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7034 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7035 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
7036 default:
7037 unreachable("Unhandled fence handle type");
7038 }
7039 }
7040
7041 VkResult radv_GetFenceFdKHR(VkDevice _device,
7042 const VkFenceGetFdInfoKHR *pGetFdInfo,
7043 int *pFd)
7044 {
7045 RADV_FROM_HANDLE(radv_device, device, _device);
7046 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
7047 int ret;
7048 uint32_t syncobj_handle;
7049
7050 if (fence->temp_syncobj)
7051 syncobj_handle = fence->temp_syncobj;
7052 else
7053 syncobj_handle = fence->syncobj;
7054
7055 switch(pGetFdInfo->handleType) {
7056 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
7057 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
7058 break;
7059 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
7060 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
7061 if (!ret) {
7062 if (fence->temp_syncobj) {
7063 close (fence->temp_syncobj);
7064 fence->temp_syncobj = 0;
7065 } else {
7066 device->ws->reset_syncobj(device->ws, syncobj_handle);
7067 }
7068 }
7069 break;
7070 default:
7071 unreachable("Unhandled fence handle type");
7072 }
7073
7074 if (ret)
7075 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
7076 return VK_SUCCESS;
7077 }
7078
7079 void radv_GetPhysicalDeviceExternalFenceProperties(
7080 VkPhysicalDevice physicalDevice,
7081 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
7082 VkExternalFenceProperties *pExternalFenceProperties)
7083 {
7084 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
7085
7086 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
7087 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
7088 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
7089 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7090 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
7091 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
7092 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
7093 } else {
7094 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
7095 pExternalFenceProperties->compatibleHandleTypes = 0;
7096 pExternalFenceProperties->externalFenceFeatures = 0;
7097 }
7098 }
7099
7100 VkResult
7101 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
7102 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
7103 const VkAllocationCallbacks* pAllocator,
7104 VkDebugReportCallbackEXT* pCallback)
7105 {
7106 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7107 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
7108 pCreateInfo, pAllocator, &instance->alloc,
7109 pCallback);
7110 }
7111
7112 void
7113 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
7114 VkDebugReportCallbackEXT _callback,
7115 const VkAllocationCallbacks* pAllocator)
7116 {
7117 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7118 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
7119 _callback, pAllocator, &instance->alloc);
7120 }
7121
7122 void
7123 radv_DebugReportMessageEXT(VkInstance _instance,
7124 VkDebugReportFlagsEXT flags,
7125 VkDebugReportObjectTypeEXT objectType,
7126 uint64_t object,
7127 size_t location,
7128 int32_t messageCode,
7129 const char* pLayerPrefix,
7130 const char* pMessage)
7131 {
7132 RADV_FROM_HANDLE(radv_instance, instance, _instance);
7133 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
7134 object, location, messageCode, pLayerPrefix, pMessage);
7135 }
7136
7137 void
7138 radv_GetDeviceGroupPeerMemoryFeatures(
7139 VkDevice device,
7140 uint32_t heapIndex,
7141 uint32_t localDeviceIndex,
7142 uint32_t remoteDeviceIndex,
7143 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
7144 {
7145 assert(localDeviceIndex == remoteDeviceIndex);
7146
7147 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
7148 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
7149 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
7150 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
7151 }
7152
7153 static const VkTimeDomainEXT radv_time_domains[] = {
7154 VK_TIME_DOMAIN_DEVICE_EXT,
7155 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
7156 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
7157 };
7158
7159 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
7160 VkPhysicalDevice physicalDevice,
7161 uint32_t *pTimeDomainCount,
7162 VkTimeDomainEXT *pTimeDomains)
7163 {
7164 int d;
7165 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
7166
7167 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
7168 vk_outarray_append(&out, i) {
7169 *i = radv_time_domains[d];
7170 }
7171 }
7172
7173 return vk_outarray_status(&out);
7174 }
7175
7176 static uint64_t
7177 radv_clock_gettime(clockid_t clock_id)
7178 {
7179 struct timespec current;
7180 int ret;
7181
7182 ret = clock_gettime(clock_id, &current);
7183 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
7184 ret = clock_gettime(CLOCK_MONOTONIC, &current);
7185 if (ret < 0)
7186 return 0;
7187
7188 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
7189 }
7190
7191 VkResult radv_GetCalibratedTimestampsEXT(
7192 VkDevice _device,
7193 uint32_t timestampCount,
7194 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
7195 uint64_t *pTimestamps,
7196 uint64_t *pMaxDeviation)
7197 {
7198 RADV_FROM_HANDLE(radv_device, device, _device);
7199 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
7200 int d;
7201 uint64_t begin, end;
7202 uint64_t max_clock_period = 0;
7203
7204 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7205
7206 for (d = 0; d < timestampCount; d++) {
7207 switch (pTimestampInfos[d].timeDomain) {
7208 case VK_TIME_DOMAIN_DEVICE_EXT:
7209 pTimestamps[d] = device->ws->query_value(device->ws,
7210 RADEON_TIMESTAMP);
7211 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
7212 max_clock_period = MAX2(max_clock_period, device_period);
7213 break;
7214 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
7215 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
7216 max_clock_period = MAX2(max_clock_period, 1);
7217 break;
7218
7219 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
7220 pTimestamps[d] = begin;
7221 break;
7222 default:
7223 pTimestamps[d] = 0;
7224 break;
7225 }
7226 }
7227
7228 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
7229
7230 /*
7231 * The maximum deviation is the sum of the interval over which we
7232 * perform the sampling and the maximum period of any sampled
7233 * clock. That's because the maximum skew between any two sampled
7234 * clock edges is when the sampled clock with the largest period is
7235 * sampled at the end of that period but right at the beginning of the
7236 * sampling interval and some other clock is sampled right at the
7237 * begining of its sampling period and right at the end of the
7238 * sampling interval. Let's assume the GPU has the longest clock
7239 * period and that the application is sampling GPU and monotonic:
7240 *
7241 * s e
7242 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
7243 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7244 *
7245 * g
7246 * 0 1 2 3
7247 * GPU -----_____-----_____-----_____-----_____
7248 *
7249 * m
7250 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
7251 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
7252 *
7253 * Interval <----------------->
7254 * Deviation <-------------------------->
7255 *
7256 * s = read(raw) 2
7257 * g = read(GPU) 1
7258 * m = read(monotonic) 2
7259 * e = read(raw) b
7260 *
7261 * We round the sample interval up by one tick to cover sampling error
7262 * in the interval clock
7263 */
7264
7265 uint64_t sample_interval = end - begin + 1;
7266
7267 *pMaxDeviation = sample_interval + max_clock_period;
7268
7269 return VK_SUCCESS;
7270 }
7271
7272 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
7273 VkPhysicalDevice physicalDevice,
7274 VkSampleCountFlagBits samples,
7275 VkMultisamplePropertiesEXT* pMultisampleProperties)
7276 {
7277 if (samples & (VK_SAMPLE_COUNT_2_BIT |
7278 VK_SAMPLE_COUNT_4_BIT |
7279 VK_SAMPLE_COUNT_8_BIT)) {
7280 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
7281 } else {
7282 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
7283 }
7284 }