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radv: Set correct registers for merged shader rings.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const char *
80 get_chip_name(enum radeon_family family)
81 {
82 switch (family) {
83 case CHIP_TAHITI: return "AMD RADV TAHITI";
84 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
85 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
86 case CHIP_OLAND: return "AMD RADV OLAND";
87 case CHIP_HAINAN: return "AMD RADV HAINAN";
88 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
89 case CHIP_KAVERI: return "AMD RADV KAVERI";
90 case CHIP_KABINI: return "AMD RADV KABINI";
91 case CHIP_HAWAII: return "AMD RADV HAWAII";
92 case CHIP_MULLINS: return "AMD RADV MULLINS";
93 case CHIP_TONGA: return "AMD RADV TONGA";
94 case CHIP_ICELAND: return "AMD RADV ICELAND";
95 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
96 case CHIP_FIJI: return "AMD RADV FIJI";
97 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
98 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
99 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
100 case CHIP_STONEY: return "AMD RADV STONEY";
101 case CHIP_VEGA10: return "AMD RADV VEGA";
102 case CHIP_RAVEN: return "AMD RADV RAVEN";
103 default: return "AMD RADV unknown";
104 }
105 }
106
107 static VkResult
108 radv_physical_device_init(struct radv_physical_device *device,
109 struct radv_instance *instance,
110 drmDevicePtr drm_device)
111 {
112 const char *path = drm_device->nodes[DRM_NODE_RENDER];
113 VkResult result;
114 drmVersionPtr version;
115 int fd;
116
117 fd = open(path, O_RDWR | O_CLOEXEC);
118 if (fd < 0)
119 return VK_ERROR_INCOMPATIBLE_DRIVER;
120
121 version = drmGetVersion(fd);
122 if (!version) {
123 close(fd);
124 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
125 "failed to get version %s: %m", path);
126 }
127
128 if (strcmp(version->name, "amdgpu")) {
129 drmFreeVersion(version);
130 close(fd);
131 return VK_ERROR_INCOMPATIBLE_DRIVER;
132 }
133 drmFreeVersion(version);
134
135 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
136 device->instance = instance;
137 assert(strlen(path) < ARRAY_SIZE(device->path));
138 strncpy(device->path, path, ARRAY_SIZE(device->path));
139
140 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
141 instance->perftest_flags);
142 if (!device->ws) {
143 result = VK_ERROR_INCOMPATIBLE_DRIVER;
144 goto fail;
145 }
146
147 device->local_fd = fd;
148 device->ws->query_info(device->ws, &device->rad_info);
149 result = radv_init_wsi(device);
150 if (result != VK_SUCCESS) {
151 device->ws->destroy(device->ws);
152 goto fail;
153 }
154
155 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
156 radv_finish_wsi(device);
157 device->ws->destroy(device->ws);
158 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
159 "cannot generate UUID");
160 goto fail;
161 }
162
163 /* These flags affect shader compilation. */
164 uint64_t shader_env_flags =
165 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
166 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
167
168 /* The gpu id is already embeded in the uuid so we just pass "radv"
169 * when creating the cache.
170 */
171 char buf[VK_UUID_SIZE + 1];
172 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE);
173 device->disk_cache = disk_cache_create("radv", buf, shader_env_flags);
174
175 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
176 device->name = get_chip_name(device->rad_info.family);
177
178 radv_get_driver_uuid(&device->device_uuid);
179 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
180
181 if (device->rad_info.family == CHIP_STONEY ||
182 device->rad_info.chip_class >= GFX9) {
183 device->has_rbplus = true;
184 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
185 }
186
187 /* The mere presense of CLEAR_STATE in the IB causes random GPU hangs
188 * on SI.
189 */
190 device->has_clear_state = device->rad_info.chip_class >= CIK;
191
192 return VK_SUCCESS;
193
194 fail:
195 close(fd);
196 return result;
197 }
198
199 static void
200 radv_physical_device_finish(struct radv_physical_device *device)
201 {
202 radv_finish_wsi(device);
203 device->ws->destroy(device->ws);
204 disk_cache_destroy(device->disk_cache);
205 close(device->local_fd);
206 }
207
208 static void *
209 default_alloc_func(void *pUserData, size_t size, size_t align,
210 VkSystemAllocationScope allocationScope)
211 {
212 return malloc(size);
213 }
214
215 static void *
216 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
217 size_t align, VkSystemAllocationScope allocationScope)
218 {
219 return realloc(pOriginal, size);
220 }
221
222 static void
223 default_free_func(void *pUserData, void *pMemory)
224 {
225 free(pMemory);
226 }
227
228 static const VkAllocationCallbacks default_alloc = {
229 .pUserData = NULL,
230 .pfnAllocation = default_alloc_func,
231 .pfnReallocation = default_realloc_func,
232 .pfnFree = default_free_func,
233 };
234
235 static const struct debug_control radv_debug_options[] = {
236 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
237 {"nodcc", RADV_DEBUG_NO_DCC},
238 {"shaders", RADV_DEBUG_DUMP_SHADERS},
239 {"nocache", RADV_DEBUG_NO_CACHE},
240 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
241 {"nohiz", RADV_DEBUG_NO_HIZ},
242 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
243 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
244 {"allbos", RADV_DEBUG_ALL_BOS},
245 {"noibs", RADV_DEBUG_NO_IBS},
246 {"spirv", RADV_DEBUG_DUMP_SPIRV},
247 {"vmfaults", RADV_DEBUG_VM_FAULTS},
248 {"zerovram", RADV_DEBUG_ZERO_VRAM},
249 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
250 {NULL, 0}
251 };
252
253 const char *
254 radv_get_debug_option_name(int id)
255 {
256 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
257 return radv_debug_options[id].string;
258 }
259
260 static const struct debug_control radv_perftest_options[] = {
261 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
262 {"sisched", RADV_PERFTEST_SISCHED},
263 {NULL, 0}
264 };
265
266 const char *
267 radv_get_perftest_option_name(int id)
268 {
269 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
270 return radv_perftest_options[id].string;
271 }
272
273 VkResult radv_CreateInstance(
274 const VkInstanceCreateInfo* pCreateInfo,
275 const VkAllocationCallbacks* pAllocator,
276 VkInstance* pInstance)
277 {
278 struct radv_instance *instance;
279
280 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
281
282 uint32_t client_version;
283 if (pCreateInfo->pApplicationInfo &&
284 pCreateInfo->pApplicationInfo->apiVersion != 0) {
285 client_version = pCreateInfo->pApplicationInfo->apiVersion;
286 } else {
287 client_version = VK_MAKE_VERSION(1, 0, 0);
288 }
289
290 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
291 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
292 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
293 "Client requested version %d.%d.%d",
294 VK_VERSION_MAJOR(client_version),
295 VK_VERSION_MINOR(client_version),
296 VK_VERSION_PATCH(client_version));
297 }
298
299 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
300 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
301 if (!radv_instance_extension_supported(ext_name))
302 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
303 }
304
305 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
306 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
307 if (!instance)
308 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
309
310 memset(instance, 0, sizeof(*instance));
311
312 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
313
314 if (pAllocator)
315 instance->alloc = *pAllocator;
316 else
317 instance->alloc = default_alloc;
318
319 instance->apiVersion = client_version;
320 instance->physicalDeviceCount = -1;
321
322 _mesa_locale_init();
323
324 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
325
326 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
327 radv_debug_options);
328
329 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
330 radv_perftest_options);
331
332 *pInstance = radv_instance_to_handle(instance);
333
334 return VK_SUCCESS;
335 }
336
337 void radv_DestroyInstance(
338 VkInstance _instance,
339 const VkAllocationCallbacks* pAllocator)
340 {
341 RADV_FROM_HANDLE(radv_instance, instance, _instance);
342
343 if (!instance)
344 return;
345
346 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
347 radv_physical_device_finish(instance->physicalDevices + i);
348 }
349
350 VG(VALGRIND_DESTROY_MEMPOOL(instance));
351
352 _mesa_locale_fini();
353
354 vk_free(&instance->alloc, instance);
355 }
356
357 static VkResult
358 radv_enumerate_devices(struct radv_instance *instance)
359 {
360 /* TODO: Check for more devices ? */
361 drmDevicePtr devices[8];
362 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
363 int max_devices;
364
365 instance->physicalDeviceCount = 0;
366
367 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
368 if (max_devices < 1)
369 return VK_ERROR_INCOMPATIBLE_DRIVER;
370
371 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
372 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
373 devices[i]->bustype == DRM_BUS_PCI &&
374 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
375
376 result = radv_physical_device_init(instance->physicalDevices +
377 instance->physicalDeviceCount,
378 instance,
379 devices[i]);
380 if (result == VK_SUCCESS)
381 ++instance->physicalDeviceCount;
382 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
383 break;
384 }
385 }
386 drmFreeDevices(devices, max_devices);
387
388 return result;
389 }
390
391 VkResult radv_EnumeratePhysicalDevices(
392 VkInstance _instance,
393 uint32_t* pPhysicalDeviceCount,
394 VkPhysicalDevice* pPhysicalDevices)
395 {
396 RADV_FROM_HANDLE(radv_instance, instance, _instance);
397 VkResult result;
398
399 if (instance->physicalDeviceCount < 0) {
400 result = radv_enumerate_devices(instance);
401 if (result != VK_SUCCESS &&
402 result != VK_ERROR_INCOMPATIBLE_DRIVER)
403 return result;
404 }
405
406 if (!pPhysicalDevices) {
407 *pPhysicalDeviceCount = instance->physicalDeviceCount;
408 } else {
409 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
410 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
411 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
412 }
413
414 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
415 : VK_SUCCESS;
416 }
417
418 void radv_GetPhysicalDeviceFeatures(
419 VkPhysicalDevice physicalDevice,
420 VkPhysicalDeviceFeatures* pFeatures)
421 {
422 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
423 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
424 memset(pFeatures, 0, sizeof(*pFeatures));
425
426 *pFeatures = (VkPhysicalDeviceFeatures) {
427 .robustBufferAccess = true,
428 .fullDrawIndexUint32 = true,
429 .imageCubeArray = true,
430 .independentBlend = true,
431 .geometryShader = !is_gfx9,
432 .tessellationShader = !is_gfx9,
433 .sampleRateShading = true,
434 .dualSrcBlend = true,
435 .logicOp = true,
436 .multiDrawIndirect = true,
437 .drawIndirectFirstInstance = true,
438 .depthClamp = true,
439 .depthBiasClamp = true,
440 .fillModeNonSolid = true,
441 .depthBounds = true,
442 .wideLines = true,
443 .largePoints = true,
444 .alphaToOne = true,
445 .multiViewport = true,
446 .samplerAnisotropy = true,
447 .textureCompressionETC2 = false,
448 .textureCompressionASTC_LDR = false,
449 .textureCompressionBC = true,
450 .occlusionQueryPrecise = true,
451 .pipelineStatisticsQuery = true,
452 .vertexPipelineStoresAndAtomics = true,
453 .fragmentStoresAndAtomics = true,
454 .shaderTessellationAndGeometryPointSize = true,
455 .shaderImageGatherExtended = true,
456 .shaderStorageImageExtendedFormats = true,
457 .shaderStorageImageMultisample = false,
458 .shaderUniformBufferArrayDynamicIndexing = true,
459 .shaderSampledImageArrayDynamicIndexing = true,
460 .shaderStorageBufferArrayDynamicIndexing = true,
461 .shaderStorageImageArrayDynamicIndexing = true,
462 .shaderStorageImageReadWithoutFormat = true,
463 .shaderStorageImageWriteWithoutFormat = true,
464 .shaderClipDistance = true,
465 .shaderCullDistance = true,
466 .shaderFloat64 = true,
467 .shaderInt64 = true,
468 .shaderInt16 = false,
469 .sparseBinding = true,
470 .variableMultisampleRate = true,
471 .inheritedQueries = true,
472 };
473 }
474
475 void radv_GetPhysicalDeviceFeatures2KHR(
476 VkPhysicalDevice physicalDevice,
477 VkPhysicalDeviceFeatures2KHR *pFeatures)
478 {
479 vk_foreach_struct(ext, pFeatures->pNext) {
480 switch (ext->sType) {
481 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
482 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
483 features->variablePointersStorageBuffer = true;
484 features->variablePointers = false;
485 break;
486 }
487 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
488 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
489 features->multiview = true;
490 features->multiviewGeometryShader = true;
491 features->multiviewTessellationShader = true;
492 break;
493 }
494 default:
495 break;
496 }
497 }
498 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
499 }
500
501 void radv_GetPhysicalDeviceProperties(
502 VkPhysicalDevice physicalDevice,
503 VkPhysicalDeviceProperties* pProperties)
504 {
505 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
506 VkSampleCountFlags sample_counts = 0xf;
507
508 /* make sure that the entire descriptor set is addressable with a signed
509 * 32-bit int. So the sum of all limits scaled by descriptor size has to
510 * be at most 2 GiB. the combined image & samples object count as one of
511 * both. This limit is for the pipeline layout, not for the set layout, but
512 * there is no set limit, so we just set a pipeline limit. I don't think
513 * any app is going to hit this soon. */
514 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
515 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
516 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
517 32 /* sampler, largest when combined with image */ +
518 64 /* sampled image */ +
519 64 /* storage image */);
520
521 VkPhysicalDeviceLimits limits = {
522 .maxImageDimension1D = (1 << 14),
523 .maxImageDimension2D = (1 << 14),
524 .maxImageDimension3D = (1 << 11),
525 .maxImageDimensionCube = (1 << 14),
526 .maxImageArrayLayers = (1 << 11),
527 .maxTexelBufferElements = 128 * 1024 * 1024,
528 .maxUniformBufferRange = UINT32_MAX,
529 .maxStorageBufferRange = UINT32_MAX,
530 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
531 .maxMemoryAllocationCount = UINT32_MAX,
532 .maxSamplerAllocationCount = 64 * 1024,
533 .bufferImageGranularity = 64, /* A cache line */
534 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
535 .maxBoundDescriptorSets = MAX_SETS,
536 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
537 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
538 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
539 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
540 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
541 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
542 .maxPerStageResources = max_descriptor_set_size,
543 .maxDescriptorSetSamplers = max_descriptor_set_size,
544 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
545 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
546 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
547 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
548 .maxDescriptorSetSampledImages = max_descriptor_set_size,
549 .maxDescriptorSetStorageImages = max_descriptor_set_size,
550 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
551 .maxVertexInputAttributes = 32,
552 .maxVertexInputBindings = 32,
553 .maxVertexInputAttributeOffset = 2047,
554 .maxVertexInputBindingStride = 2048,
555 .maxVertexOutputComponents = 128,
556 .maxTessellationGenerationLevel = 64,
557 .maxTessellationPatchSize = 32,
558 .maxTessellationControlPerVertexInputComponents = 128,
559 .maxTessellationControlPerVertexOutputComponents = 128,
560 .maxTessellationControlPerPatchOutputComponents = 120,
561 .maxTessellationControlTotalOutputComponents = 4096,
562 .maxTessellationEvaluationInputComponents = 128,
563 .maxTessellationEvaluationOutputComponents = 128,
564 .maxGeometryShaderInvocations = 127,
565 .maxGeometryInputComponents = 64,
566 .maxGeometryOutputComponents = 128,
567 .maxGeometryOutputVertices = 256,
568 .maxGeometryTotalOutputComponents = 1024,
569 .maxFragmentInputComponents = 128,
570 .maxFragmentOutputAttachments = 8,
571 .maxFragmentDualSrcAttachments = 1,
572 .maxFragmentCombinedOutputResources = 8,
573 .maxComputeSharedMemorySize = 32768,
574 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
575 .maxComputeWorkGroupInvocations = 2048,
576 .maxComputeWorkGroupSize = {
577 2048,
578 2048,
579 2048
580 },
581 .subPixelPrecisionBits = 4 /* FIXME */,
582 .subTexelPrecisionBits = 4 /* FIXME */,
583 .mipmapPrecisionBits = 4 /* FIXME */,
584 .maxDrawIndexedIndexValue = UINT32_MAX,
585 .maxDrawIndirectCount = UINT32_MAX,
586 .maxSamplerLodBias = 16,
587 .maxSamplerAnisotropy = 16,
588 .maxViewports = MAX_VIEWPORTS,
589 .maxViewportDimensions = { (1 << 14), (1 << 14) },
590 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
591 .viewportSubPixelBits = 13, /* We take a float? */
592 .minMemoryMapAlignment = 4096, /* A page */
593 .minTexelBufferOffsetAlignment = 1,
594 .minUniformBufferOffsetAlignment = 4,
595 .minStorageBufferOffsetAlignment = 4,
596 .minTexelOffset = -32,
597 .maxTexelOffset = 31,
598 .minTexelGatherOffset = -32,
599 .maxTexelGatherOffset = 31,
600 .minInterpolationOffset = -2,
601 .maxInterpolationOffset = 2,
602 .subPixelInterpolationOffsetBits = 8,
603 .maxFramebufferWidth = (1 << 14),
604 .maxFramebufferHeight = (1 << 14),
605 .maxFramebufferLayers = (1 << 10),
606 .framebufferColorSampleCounts = sample_counts,
607 .framebufferDepthSampleCounts = sample_counts,
608 .framebufferStencilSampleCounts = sample_counts,
609 .framebufferNoAttachmentsSampleCounts = sample_counts,
610 .maxColorAttachments = MAX_RTS,
611 .sampledImageColorSampleCounts = sample_counts,
612 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
613 .sampledImageDepthSampleCounts = sample_counts,
614 .sampledImageStencilSampleCounts = sample_counts,
615 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
616 .maxSampleMaskWords = 1,
617 .timestampComputeAndGraphics = true,
618 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
619 .maxClipDistances = 8,
620 .maxCullDistances = 8,
621 .maxCombinedClipAndCullDistances = 8,
622 .discreteQueuePriorities = 1,
623 .pointSizeRange = { 0.125, 255.875 },
624 .lineWidthRange = { 0.0, 7.9921875 },
625 .pointSizeGranularity = (1.0 / 8.0),
626 .lineWidthGranularity = (1.0 / 128.0),
627 .strictLines = false, /* FINISHME */
628 .standardSampleLocations = true,
629 .optimalBufferCopyOffsetAlignment = 128,
630 .optimalBufferCopyRowPitchAlignment = 128,
631 .nonCoherentAtomSize = 64,
632 };
633
634 *pProperties = (VkPhysicalDeviceProperties) {
635 .apiVersion = radv_physical_device_api_version(pdevice),
636 .driverVersion = vk_get_driver_version(),
637 .vendorID = ATI_VENDOR_ID,
638 .deviceID = pdevice->rad_info.pci_id,
639 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
640 .limits = limits,
641 .sparseProperties = {0},
642 };
643
644 strcpy(pProperties->deviceName, pdevice->name);
645 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
646 }
647
648 void radv_GetPhysicalDeviceProperties2KHR(
649 VkPhysicalDevice physicalDevice,
650 VkPhysicalDeviceProperties2KHR *pProperties)
651 {
652 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
653 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
654
655 vk_foreach_struct(ext, pProperties->pNext) {
656 switch (ext->sType) {
657 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
658 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
659 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
660 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
661 break;
662 }
663 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
664 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
665 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
666 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
667 properties->deviceLUIDValid = false;
668 break;
669 }
670 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
671 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
672 properties->maxMultiviewViewCount = MAX_VIEWS;
673 properties->maxMultiviewInstanceIndex = INT_MAX;
674 break;
675 }
676 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
677 VkPhysicalDevicePointClippingPropertiesKHR *properties =
678 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
679 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
680 break;
681 }
682 default:
683 break;
684 }
685 }
686 }
687
688 static void radv_get_physical_device_queue_family_properties(
689 struct radv_physical_device* pdevice,
690 uint32_t* pCount,
691 VkQueueFamilyProperties** pQueueFamilyProperties)
692 {
693 int num_queue_families = 1;
694 int idx;
695 if (pdevice->rad_info.num_compute_rings > 0 &&
696 pdevice->rad_info.chip_class >= CIK &&
697 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
698 num_queue_families++;
699
700 if (pQueueFamilyProperties == NULL) {
701 *pCount = num_queue_families;
702 return;
703 }
704
705 if (!*pCount)
706 return;
707
708 idx = 0;
709 if (*pCount >= 1) {
710 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
711 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
712 VK_QUEUE_COMPUTE_BIT |
713 VK_QUEUE_TRANSFER_BIT |
714 VK_QUEUE_SPARSE_BINDING_BIT,
715 .queueCount = 1,
716 .timestampValidBits = 64,
717 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
718 };
719 idx++;
720 }
721
722 if (pdevice->rad_info.num_compute_rings > 0 &&
723 pdevice->rad_info.chip_class >= CIK &&
724 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
725 if (*pCount > idx) {
726 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
727 .queueFlags = VK_QUEUE_COMPUTE_BIT |
728 VK_QUEUE_TRANSFER_BIT |
729 VK_QUEUE_SPARSE_BINDING_BIT,
730 .queueCount = pdevice->rad_info.num_compute_rings,
731 .timestampValidBits = 64,
732 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
733 };
734 idx++;
735 }
736 }
737 *pCount = idx;
738 }
739
740 void radv_GetPhysicalDeviceQueueFamilyProperties(
741 VkPhysicalDevice physicalDevice,
742 uint32_t* pCount,
743 VkQueueFamilyProperties* pQueueFamilyProperties)
744 {
745 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
746 if (!pQueueFamilyProperties) {
747 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
748 return;
749 }
750 VkQueueFamilyProperties *properties[] = {
751 pQueueFamilyProperties + 0,
752 pQueueFamilyProperties + 1,
753 pQueueFamilyProperties + 2,
754 };
755 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
756 assert(*pCount <= 3);
757 }
758
759 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
760 VkPhysicalDevice physicalDevice,
761 uint32_t* pCount,
762 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
763 {
764 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
765 if (!pQueueFamilyProperties) {
766 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
767 return;
768 }
769 VkQueueFamilyProperties *properties[] = {
770 &pQueueFamilyProperties[0].queueFamilyProperties,
771 &pQueueFamilyProperties[1].queueFamilyProperties,
772 &pQueueFamilyProperties[2].queueFamilyProperties,
773 };
774 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
775 assert(*pCount <= 3);
776 }
777
778 void radv_GetPhysicalDeviceMemoryProperties(
779 VkPhysicalDevice physicalDevice,
780 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
781 {
782 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
783
784 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
785
786 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
787 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
788 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
789 .heapIndex = RADV_MEM_HEAP_VRAM,
790 };
791 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
792 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
793 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
794 .heapIndex = RADV_MEM_HEAP_GTT,
795 };
796 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
797 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
798 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
799 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
800 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
801 };
802 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
803 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
804 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
805 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
806 .heapIndex = RADV_MEM_HEAP_GTT,
807 };
808
809 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
810 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
811 physical_device->rad_info.vram_vis_size);
812
813 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
814 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
815 .size = physical_device->rad_info.vram_size -
816 visible_vram_size,
817 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
818 };
819 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
820 .size = visible_vram_size,
821 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
822 };
823 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
824 .size = physical_device->rad_info.gart_size,
825 .flags = 0,
826 };
827 }
828
829 void radv_GetPhysicalDeviceMemoryProperties2KHR(
830 VkPhysicalDevice physicalDevice,
831 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
832 {
833 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
834 &pMemoryProperties->memoryProperties);
835 }
836
837 static int
838 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
839 int queue_family_index, int idx)
840 {
841 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
842 queue->device = device;
843 queue->queue_family_index = queue_family_index;
844 queue->queue_idx = idx;
845
846 queue->hw_ctx = device->ws->ctx_create(device->ws);
847 if (!queue->hw_ctx)
848 return VK_ERROR_OUT_OF_HOST_MEMORY;
849
850 return VK_SUCCESS;
851 }
852
853 static void
854 radv_queue_finish(struct radv_queue *queue)
855 {
856 if (queue->hw_ctx)
857 queue->device->ws->ctx_destroy(queue->hw_ctx);
858
859 if (queue->initial_full_flush_preamble_cs)
860 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
861 if (queue->initial_preamble_cs)
862 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
863 if (queue->continue_preamble_cs)
864 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
865 if (queue->descriptor_bo)
866 queue->device->ws->buffer_destroy(queue->descriptor_bo);
867 if (queue->scratch_bo)
868 queue->device->ws->buffer_destroy(queue->scratch_bo);
869 if (queue->esgs_ring_bo)
870 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
871 if (queue->gsvs_ring_bo)
872 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
873 if (queue->tess_factor_ring_bo)
874 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
875 if (queue->tess_offchip_ring_bo)
876 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
877 if (queue->compute_scratch_bo)
878 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
879 }
880
881 static void
882 radv_device_init_gs_info(struct radv_device *device)
883 {
884 switch (device->physical_device->rad_info.family) {
885 case CHIP_OLAND:
886 case CHIP_HAINAN:
887 case CHIP_KAVERI:
888 case CHIP_KABINI:
889 case CHIP_MULLINS:
890 case CHIP_ICELAND:
891 case CHIP_CARRIZO:
892 case CHIP_STONEY:
893 device->gs_table_depth = 16;
894 return;
895 case CHIP_TAHITI:
896 case CHIP_PITCAIRN:
897 case CHIP_VERDE:
898 case CHIP_BONAIRE:
899 case CHIP_HAWAII:
900 case CHIP_TONGA:
901 case CHIP_FIJI:
902 case CHIP_POLARIS10:
903 case CHIP_POLARIS11:
904 case CHIP_POLARIS12:
905 case CHIP_VEGA10:
906 case CHIP_RAVEN:
907 device->gs_table_depth = 32;
908 return;
909 default:
910 unreachable("unknown GPU");
911 }
912 }
913
914 VkResult radv_CreateDevice(
915 VkPhysicalDevice physicalDevice,
916 const VkDeviceCreateInfo* pCreateInfo,
917 const VkAllocationCallbacks* pAllocator,
918 VkDevice* pDevice)
919 {
920 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
921 VkResult result;
922 struct radv_device *device;
923
924 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
925 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
926 if (!radv_physical_device_extension_supported(physical_device, ext_name))
927 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
928 }
929
930 /* Check enabled features */
931 if (pCreateInfo->pEnabledFeatures) {
932 VkPhysicalDeviceFeatures supported_features;
933 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
934 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
935 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
936 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
937 for (uint32_t i = 0; i < num_features; i++) {
938 if (enabled_feature[i] && !supported_feature[i])
939 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
940 }
941 }
942
943 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
944 sizeof(*device), 8,
945 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
946 if (!device)
947 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
948
949 memset(device, 0, sizeof(*device));
950
951 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
952 device->instance = physical_device->instance;
953 device->physical_device = physical_device;
954
955 device->ws = physical_device->ws;
956 if (pAllocator)
957 device->alloc = *pAllocator;
958 else
959 device->alloc = physical_device->instance->alloc;
960
961 mtx_init(&device->shader_slab_mutex, mtx_plain);
962 list_inithead(&device->shader_slabs);
963
964 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
965 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
966 uint32_t qfi = queue_create->queueFamilyIndex;
967
968 device->queues[qfi] = vk_alloc(&device->alloc,
969 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
970 if (!device->queues[qfi]) {
971 result = VK_ERROR_OUT_OF_HOST_MEMORY;
972 goto fail;
973 }
974
975 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
976
977 device->queue_count[qfi] = queue_create->queueCount;
978
979 for (unsigned q = 0; q < queue_create->queueCount; q++) {
980 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
981 if (result != VK_SUCCESS)
982 goto fail;
983 }
984 }
985
986 #if HAVE_LLVM < 0x0400
987 device->llvm_supports_spill = false;
988 #else
989 device->llvm_supports_spill = true;
990 #endif
991
992 /* The maximum number of scratch waves. Scratch space isn't divided
993 * evenly between CUs. The number is only a function of the number of CUs.
994 * We can decrease the constant to decrease the scratch buffer size.
995 *
996 * sctx->scratch_waves must be >= the maximum posible size of
997 * 1 threadgroup, so that the hw doesn't hang from being unable
998 * to start any.
999 *
1000 * The recommended value is 4 per CU at most. Higher numbers don't
1001 * bring much benefit, but they still occupy chip resources (think
1002 * async compute). I've seen ~2% performance difference between 4 and 32.
1003 */
1004 uint32_t max_threads_per_block = 2048;
1005 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1006 max_threads_per_block / 64);
1007
1008 radv_device_init_gs_info(device);
1009
1010 device->tess_offchip_block_dw_size =
1011 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1012 device->has_distributed_tess =
1013 device->physical_device->rad_info.chip_class >= VI &&
1014 device->physical_device->rad_info.max_se >= 2;
1015
1016 if (getenv("RADV_TRACE_FILE")) {
1017 if (!radv_init_trace(device))
1018 goto fail;
1019 }
1020
1021 result = radv_device_init_meta(device);
1022 if (result != VK_SUCCESS)
1023 goto fail;
1024
1025 radv_device_init_msaa(device);
1026
1027 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1028 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1029 switch (family) {
1030 case RADV_QUEUE_GENERAL:
1031 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1032 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1033 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1034 break;
1035 case RADV_QUEUE_COMPUTE:
1036 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1037 radeon_emit(device->empty_cs[family], 0);
1038 break;
1039 }
1040 device->ws->cs_finalize(device->empty_cs[family]);
1041 }
1042
1043 if (device->physical_device->rad_info.chip_class >= CIK)
1044 cik_create_gfx_config(device);
1045
1046 VkPipelineCacheCreateInfo ci;
1047 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1048 ci.pNext = NULL;
1049 ci.flags = 0;
1050 ci.pInitialData = NULL;
1051 ci.initialDataSize = 0;
1052 VkPipelineCache pc;
1053 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1054 &ci, NULL, &pc);
1055 if (result != VK_SUCCESS)
1056 goto fail;
1057
1058 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1059
1060 *pDevice = radv_device_to_handle(device);
1061 return VK_SUCCESS;
1062
1063 fail:
1064 if (device->trace_bo)
1065 device->ws->buffer_destroy(device->trace_bo);
1066
1067 if (device->gfx_init)
1068 device->ws->buffer_destroy(device->gfx_init);
1069
1070 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1071 for (unsigned q = 0; q < device->queue_count[i]; q++)
1072 radv_queue_finish(&device->queues[i][q]);
1073 if (device->queue_count[i])
1074 vk_free(&device->alloc, device->queues[i]);
1075 }
1076
1077 vk_free(&device->alloc, device);
1078 return result;
1079 }
1080
1081 void radv_DestroyDevice(
1082 VkDevice _device,
1083 const VkAllocationCallbacks* pAllocator)
1084 {
1085 RADV_FROM_HANDLE(radv_device, device, _device);
1086
1087 if (!device)
1088 return;
1089
1090 if (device->trace_bo)
1091 device->ws->buffer_destroy(device->trace_bo);
1092
1093 if (device->gfx_init)
1094 device->ws->buffer_destroy(device->gfx_init);
1095
1096 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1097 for (unsigned q = 0; q < device->queue_count[i]; q++)
1098 radv_queue_finish(&device->queues[i][q]);
1099 if (device->queue_count[i])
1100 vk_free(&device->alloc, device->queues[i]);
1101 if (device->empty_cs[i])
1102 device->ws->cs_destroy(device->empty_cs[i]);
1103 }
1104 radv_device_finish_meta(device);
1105
1106 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1107 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1108
1109 radv_destroy_shader_slabs(device);
1110
1111 vk_free(&device->alloc, device);
1112 }
1113
1114 VkResult radv_EnumerateInstanceLayerProperties(
1115 uint32_t* pPropertyCount,
1116 VkLayerProperties* pProperties)
1117 {
1118 if (pProperties == NULL) {
1119 *pPropertyCount = 0;
1120 return VK_SUCCESS;
1121 }
1122
1123 /* None supported at this time */
1124 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1125 }
1126
1127 VkResult radv_EnumerateDeviceLayerProperties(
1128 VkPhysicalDevice physicalDevice,
1129 uint32_t* pPropertyCount,
1130 VkLayerProperties* pProperties)
1131 {
1132 if (pProperties == NULL) {
1133 *pPropertyCount = 0;
1134 return VK_SUCCESS;
1135 }
1136
1137 /* None supported at this time */
1138 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1139 }
1140
1141 void radv_GetDeviceQueue(
1142 VkDevice _device,
1143 uint32_t queueFamilyIndex,
1144 uint32_t queueIndex,
1145 VkQueue* pQueue)
1146 {
1147 RADV_FROM_HANDLE(radv_device, device, _device);
1148
1149 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1150 }
1151
1152 static void
1153 fill_geom_tess_rings(struct radv_queue *queue,
1154 uint32_t *map,
1155 bool add_sample_positions,
1156 uint32_t esgs_ring_size,
1157 struct radeon_winsys_bo *esgs_ring_bo,
1158 uint32_t gsvs_ring_size,
1159 struct radeon_winsys_bo *gsvs_ring_bo,
1160 uint32_t tess_factor_ring_size,
1161 struct radeon_winsys_bo *tess_factor_ring_bo,
1162 uint32_t tess_offchip_ring_size,
1163 struct radeon_winsys_bo *tess_offchip_ring_bo)
1164 {
1165 uint64_t esgs_va = 0, gsvs_va = 0;
1166 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1167 uint32_t *desc = &map[4];
1168
1169 if (esgs_ring_bo)
1170 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1171 if (gsvs_ring_bo)
1172 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1173 if (tess_factor_ring_bo)
1174 tess_factor_va = radv_buffer_get_va(tess_factor_ring_bo);
1175 if (tess_offchip_ring_bo)
1176 tess_offchip_va = radv_buffer_get_va(tess_offchip_ring_bo);
1177
1178 /* stride 0, num records - size, add tid, swizzle, elsize4,
1179 index stride 64 */
1180 desc[0] = esgs_va;
1181 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1182 S_008F04_STRIDE(0) |
1183 S_008F04_SWIZZLE_ENABLE(true);
1184 desc[2] = esgs_ring_size;
1185 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1186 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1187 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1188 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1189 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1190 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1191 S_008F0C_ELEMENT_SIZE(1) |
1192 S_008F0C_INDEX_STRIDE(3) |
1193 S_008F0C_ADD_TID_ENABLE(true);
1194
1195 desc += 4;
1196 /* GS entry for ES->GS ring */
1197 /* stride 0, num records - size, elsize0,
1198 index stride 0 */
1199 desc[0] = esgs_va;
1200 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1201 S_008F04_STRIDE(0) |
1202 S_008F04_SWIZZLE_ENABLE(false);
1203 desc[2] = esgs_ring_size;
1204 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1205 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1206 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1207 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1208 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1209 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1210 S_008F0C_ELEMENT_SIZE(0) |
1211 S_008F0C_INDEX_STRIDE(0) |
1212 S_008F0C_ADD_TID_ENABLE(false);
1213
1214 desc += 4;
1215 /* VS entry for GS->VS ring */
1216 /* stride 0, num records - size, elsize0,
1217 index stride 0 */
1218 desc[0] = gsvs_va;
1219 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1220 S_008F04_STRIDE(0) |
1221 S_008F04_SWIZZLE_ENABLE(false);
1222 desc[2] = gsvs_ring_size;
1223 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1224 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1225 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1226 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1227 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1228 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1229 S_008F0C_ELEMENT_SIZE(0) |
1230 S_008F0C_INDEX_STRIDE(0) |
1231 S_008F0C_ADD_TID_ENABLE(false);
1232 desc += 4;
1233
1234 /* stride gsvs_itemsize, num records 64
1235 elsize 4, index stride 16 */
1236 /* shader will patch stride and desc[2] */
1237 desc[0] = gsvs_va;
1238 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1239 S_008F04_STRIDE(0) |
1240 S_008F04_SWIZZLE_ENABLE(true);
1241 desc[2] = 0;
1242 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1243 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1244 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1245 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1246 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1247 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1248 S_008F0C_ELEMENT_SIZE(1) |
1249 S_008F0C_INDEX_STRIDE(1) |
1250 S_008F0C_ADD_TID_ENABLE(true);
1251 desc += 4;
1252
1253 desc[0] = tess_factor_va;
1254 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1255 S_008F04_STRIDE(0) |
1256 S_008F04_SWIZZLE_ENABLE(false);
1257 desc[2] = tess_factor_ring_size;
1258 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1259 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1260 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1261 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1262 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1263 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1264 S_008F0C_ELEMENT_SIZE(0) |
1265 S_008F0C_INDEX_STRIDE(0) |
1266 S_008F0C_ADD_TID_ENABLE(false);
1267 desc += 4;
1268
1269 desc[0] = tess_offchip_va;
1270 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1271 S_008F04_STRIDE(0) |
1272 S_008F04_SWIZZLE_ENABLE(false);
1273 desc[2] = tess_offchip_ring_size;
1274 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1275 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1276 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1277 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1278 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1279 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1280 S_008F0C_ELEMENT_SIZE(0) |
1281 S_008F0C_INDEX_STRIDE(0) |
1282 S_008F0C_ADD_TID_ENABLE(false);
1283 desc += 4;
1284
1285 /* add sample positions after all rings */
1286 memcpy(desc, queue->device->sample_locations_1x, 8);
1287 desc += 2;
1288 memcpy(desc, queue->device->sample_locations_2x, 16);
1289 desc += 4;
1290 memcpy(desc, queue->device->sample_locations_4x, 32);
1291 desc += 8;
1292 memcpy(desc, queue->device->sample_locations_8x, 64);
1293 desc += 16;
1294 memcpy(desc, queue->device->sample_locations_16x, 128);
1295 }
1296
1297 static unsigned
1298 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1299 {
1300 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1301 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1302 device->physical_device->rad_info.family != CHIP_STONEY;
1303 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1304 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1305 device->physical_device->rad_info.max_se;
1306 unsigned offchip_granularity;
1307 unsigned hs_offchip_param;
1308 switch (device->tess_offchip_block_dw_size) {
1309 default:
1310 assert(0);
1311 /* fall through */
1312 case 8192:
1313 offchip_granularity = V_03093C_X_8K_DWORDS;
1314 break;
1315 case 4096:
1316 offchip_granularity = V_03093C_X_4K_DWORDS;
1317 break;
1318 }
1319
1320 switch (device->physical_device->rad_info.chip_class) {
1321 case SI:
1322 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1323 break;
1324 case CIK:
1325 case VI:
1326 case GFX9:
1327 default:
1328 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1329 break;
1330 }
1331
1332 *max_offchip_buffers_p = max_offchip_buffers;
1333 if (device->physical_device->rad_info.chip_class >= CIK) {
1334 if (device->physical_device->rad_info.chip_class >= VI)
1335 --max_offchip_buffers;
1336 hs_offchip_param =
1337 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1338 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1339 } else {
1340 hs_offchip_param =
1341 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1342 }
1343 return hs_offchip_param;
1344 }
1345
1346 static VkResult
1347 radv_get_preamble_cs(struct radv_queue *queue,
1348 uint32_t scratch_size,
1349 uint32_t compute_scratch_size,
1350 uint32_t esgs_ring_size,
1351 uint32_t gsvs_ring_size,
1352 bool needs_tess_rings,
1353 bool needs_sample_positions,
1354 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1355 struct radeon_winsys_cs **initial_preamble_cs,
1356 struct radeon_winsys_cs **continue_preamble_cs)
1357 {
1358 struct radeon_winsys_bo *scratch_bo = NULL;
1359 struct radeon_winsys_bo *descriptor_bo = NULL;
1360 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1361 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1362 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1363 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1364 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1365 struct radeon_winsys_cs *dest_cs[3] = {0};
1366 bool add_tess_rings = false, add_sample_positions = false;
1367 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1368 unsigned max_offchip_buffers;
1369 unsigned hs_offchip_param = 0;
1370 if (!queue->has_tess_rings) {
1371 if (needs_tess_rings)
1372 add_tess_rings = true;
1373 }
1374 if (!queue->has_sample_positions) {
1375 if (needs_sample_positions)
1376 add_sample_positions = true;
1377 }
1378 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1379 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1380 &max_offchip_buffers);
1381 tess_offchip_ring_size = max_offchip_buffers *
1382 queue->device->tess_offchip_block_dw_size * 4;
1383
1384 if (scratch_size <= queue->scratch_size &&
1385 compute_scratch_size <= queue->compute_scratch_size &&
1386 esgs_ring_size <= queue->esgs_ring_size &&
1387 gsvs_ring_size <= queue->gsvs_ring_size &&
1388 !add_tess_rings && !add_sample_positions &&
1389 queue->initial_preamble_cs) {
1390 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1391 *initial_preamble_cs = queue->initial_preamble_cs;
1392 *continue_preamble_cs = queue->continue_preamble_cs;
1393 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1394 *continue_preamble_cs = NULL;
1395 return VK_SUCCESS;
1396 }
1397
1398 if (scratch_size > queue->scratch_size) {
1399 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1400 scratch_size,
1401 4096,
1402 RADEON_DOMAIN_VRAM,
1403 RADEON_FLAG_NO_CPU_ACCESS);
1404 if (!scratch_bo)
1405 goto fail;
1406 } else
1407 scratch_bo = queue->scratch_bo;
1408
1409 if (compute_scratch_size > queue->compute_scratch_size) {
1410 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1411 compute_scratch_size,
1412 4096,
1413 RADEON_DOMAIN_VRAM,
1414 RADEON_FLAG_NO_CPU_ACCESS);
1415 if (!compute_scratch_bo)
1416 goto fail;
1417
1418 } else
1419 compute_scratch_bo = queue->compute_scratch_bo;
1420
1421 if (esgs_ring_size > queue->esgs_ring_size) {
1422 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1423 esgs_ring_size,
1424 4096,
1425 RADEON_DOMAIN_VRAM,
1426 RADEON_FLAG_NO_CPU_ACCESS);
1427 if (!esgs_ring_bo)
1428 goto fail;
1429 } else {
1430 esgs_ring_bo = queue->esgs_ring_bo;
1431 esgs_ring_size = queue->esgs_ring_size;
1432 }
1433
1434 if (gsvs_ring_size > queue->gsvs_ring_size) {
1435 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1436 gsvs_ring_size,
1437 4096,
1438 RADEON_DOMAIN_VRAM,
1439 RADEON_FLAG_NO_CPU_ACCESS);
1440 if (!gsvs_ring_bo)
1441 goto fail;
1442 } else {
1443 gsvs_ring_bo = queue->gsvs_ring_bo;
1444 gsvs_ring_size = queue->gsvs_ring_size;
1445 }
1446
1447 if (add_tess_rings) {
1448 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1449 tess_factor_ring_size,
1450 256,
1451 RADEON_DOMAIN_VRAM,
1452 RADEON_FLAG_NO_CPU_ACCESS);
1453 if (!tess_factor_ring_bo)
1454 goto fail;
1455 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1456 tess_offchip_ring_size,
1457 256,
1458 RADEON_DOMAIN_VRAM,
1459 RADEON_FLAG_NO_CPU_ACCESS);
1460 if (!tess_offchip_ring_bo)
1461 goto fail;
1462 } else {
1463 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1464 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1465 }
1466
1467 if (scratch_bo != queue->scratch_bo ||
1468 esgs_ring_bo != queue->esgs_ring_bo ||
1469 gsvs_ring_bo != queue->gsvs_ring_bo ||
1470 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1471 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1472 uint32_t size = 0;
1473 if (gsvs_ring_bo || esgs_ring_bo ||
1474 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1475 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1476 if (add_sample_positions)
1477 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1478 }
1479 else if (scratch_bo)
1480 size = 8; /* 2 dword */
1481
1482 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1483 size,
1484 4096,
1485 RADEON_DOMAIN_VRAM,
1486 RADEON_FLAG_CPU_ACCESS);
1487 if (!descriptor_bo)
1488 goto fail;
1489 } else
1490 descriptor_bo = queue->descriptor_bo;
1491
1492 for(int i = 0; i < 3; ++i) {
1493 struct radeon_winsys_cs *cs = NULL;
1494 cs = queue->device->ws->cs_create(queue->device->ws,
1495 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1496 if (!cs)
1497 goto fail;
1498
1499 dest_cs[i] = cs;
1500
1501 if (scratch_bo)
1502 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1503
1504 if (esgs_ring_bo)
1505 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1506
1507 if (gsvs_ring_bo)
1508 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1509
1510 if (tess_factor_ring_bo)
1511 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1512
1513 if (tess_offchip_ring_bo)
1514 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1515
1516 if (descriptor_bo)
1517 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1518
1519 if (descriptor_bo != queue->descriptor_bo) {
1520 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1521
1522 if (scratch_bo) {
1523 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
1524 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1525 S_008F04_SWIZZLE_ENABLE(1);
1526 map[0] = scratch_va;
1527 map[1] = rsrc1;
1528 }
1529
1530 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1531 add_sample_positions)
1532 fill_geom_tess_rings(queue, map, add_sample_positions,
1533 esgs_ring_size, esgs_ring_bo,
1534 gsvs_ring_size, gsvs_ring_bo,
1535 tess_factor_ring_size, tess_factor_ring_bo,
1536 tess_offchip_ring_size, tess_offchip_ring_bo);
1537
1538 queue->device->ws->buffer_unmap(descriptor_bo);
1539 }
1540
1541 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1542 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1543 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1544 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1545 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1546 }
1547
1548 if (esgs_ring_bo || gsvs_ring_bo) {
1549 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1550 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1551 radeon_emit(cs, esgs_ring_size >> 8);
1552 radeon_emit(cs, gsvs_ring_size >> 8);
1553 } else {
1554 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1555 radeon_emit(cs, esgs_ring_size >> 8);
1556 radeon_emit(cs, gsvs_ring_size >> 8);
1557 }
1558 }
1559
1560 if (tess_factor_ring_bo) {
1561 uint64_t tf_va = radv_buffer_get_va(tess_factor_ring_bo);
1562 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1563 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1564 S_030938_SIZE(tess_factor_ring_size / 4));
1565 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1566 tf_va >> 8);
1567 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1568 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1569 tf_va >> 40);
1570 }
1571 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1572 } else {
1573 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1574 S_008988_SIZE(tess_factor_ring_size / 4));
1575 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1576 tf_va >> 8);
1577 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1578 hs_offchip_param);
1579 }
1580 }
1581
1582 if (descriptor_bo) {
1583 uint64_t va = radv_buffer_get_va(descriptor_bo);
1584 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1585 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1586 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1587 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
1588 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
1589
1590 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1591 radeon_set_sh_reg_seq(cs, regs[i], 2);
1592 radeon_emit(cs, va);
1593 radeon_emit(cs, va >> 32);
1594 }
1595 } else {
1596 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1597 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1598 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1599 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1600 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1601 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1602
1603 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1604 radeon_set_sh_reg_seq(cs, regs[i], 2);
1605 radeon_emit(cs, va);
1606 radeon_emit(cs, va >> 32);
1607 }
1608 }
1609 }
1610
1611 if (compute_scratch_bo) {
1612 uint64_t scratch_va = radv_buffer_get_va(compute_scratch_bo);
1613 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1614 S_008F04_SWIZZLE_ENABLE(1);
1615
1616 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1617
1618 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1619 radeon_emit(cs, scratch_va);
1620 radeon_emit(cs, rsrc1);
1621 }
1622
1623 if (i == 0) {
1624 si_cs_emit_cache_flush(cs,
1625 false,
1626 queue->device->physical_device->rad_info.chip_class,
1627 NULL, 0,
1628 queue->queue_family_index == RING_COMPUTE &&
1629 queue->device->physical_device->rad_info.chip_class >= CIK,
1630 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1631 RADV_CMD_FLAG_INV_ICACHE |
1632 RADV_CMD_FLAG_INV_SMEM_L1 |
1633 RADV_CMD_FLAG_INV_VMEM_L1 |
1634 RADV_CMD_FLAG_INV_GLOBAL_L2);
1635 } else if (i == 1) {
1636 si_cs_emit_cache_flush(cs,
1637 false,
1638 queue->device->physical_device->rad_info.chip_class,
1639 NULL, 0,
1640 queue->queue_family_index == RING_COMPUTE &&
1641 queue->device->physical_device->rad_info.chip_class >= CIK,
1642 RADV_CMD_FLAG_INV_ICACHE |
1643 RADV_CMD_FLAG_INV_SMEM_L1 |
1644 RADV_CMD_FLAG_INV_VMEM_L1 |
1645 RADV_CMD_FLAG_INV_GLOBAL_L2);
1646 }
1647
1648 if (!queue->device->ws->cs_finalize(cs))
1649 goto fail;
1650 }
1651
1652 if (queue->initial_full_flush_preamble_cs)
1653 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1654
1655 if (queue->initial_preamble_cs)
1656 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1657
1658 if (queue->continue_preamble_cs)
1659 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1660
1661 queue->initial_full_flush_preamble_cs = dest_cs[0];
1662 queue->initial_preamble_cs = dest_cs[1];
1663 queue->continue_preamble_cs = dest_cs[2];
1664
1665 if (scratch_bo != queue->scratch_bo) {
1666 if (queue->scratch_bo)
1667 queue->device->ws->buffer_destroy(queue->scratch_bo);
1668 queue->scratch_bo = scratch_bo;
1669 queue->scratch_size = scratch_size;
1670 }
1671
1672 if (compute_scratch_bo != queue->compute_scratch_bo) {
1673 if (queue->compute_scratch_bo)
1674 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1675 queue->compute_scratch_bo = compute_scratch_bo;
1676 queue->compute_scratch_size = compute_scratch_size;
1677 }
1678
1679 if (esgs_ring_bo != queue->esgs_ring_bo) {
1680 if (queue->esgs_ring_bo)
1681 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1682 queue->esgs_ring_bo = esgs_ring_bo;
1683 queue->esgs_ring_size = esgs_ring_size;
1684 }
1685
1686 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1687 if (queue->gsvs_ring_bo)
1688 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1689 queue->gsvs_ring_bo = gsvs_ring_bo;
1690 queue->gsvs_ring_size = gsvs_ring_size;
1691 }
1692
1693 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1694 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1695 }
1696
1697 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1698 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1699 queue->has_tess_rings = true;
1700 }
1701
1702 if (descriptor_bo != queue->descriptor_bo) {
1703 if (queue->descriptor_bo)
1704 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1705
1706 queue->descriptor_bo = descriptor_bo;
1707 }
1708
1709 if (add_sample_positions)
1710 queue->has_sample_positions = true;
1711
1712 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1713 *initial_preamble_cs = queue->initial_preamble_cs;
1714 *continue_preamble_cs = queue->continue_preamble_cs;
1715 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1716 *continue_preamble_cs = NULL;
1717 return VK_SUCCESS;
1718 fail:
1719 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1720 if (dest_cs[i])
1721 queue->device->ws->cs_destroy(dest_cs[i]);
1722 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1723 queue->device->ws->buffer_destroy(descriptor_bo);
1724 if (scratch_bo && scratch_bo != queue->scratch_bo)
1725 queue->device->ws->buffer_destroy(scratch_bo);
1726 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1727 queue->device->ws->buffer_destroy(compute_scratch_bo);
1728 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1729 queue->device->ws->buffer_destroy(esgs_ring_bo);
1730 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1731 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1732 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1733 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1734 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1735 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1736 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1737 }
1738
1739 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1740 int num_sems,
1741 const VkSemaphore *sems,
1742 bool reset_temp)
1743 {
1744 int syncobj_idx = 0, sem_idx = 0;
1745
1746 if (num_sems == 0)
1747 return VK_SUCCESS;
1748 for (uint32_t i = 0; i < num_sems; i++) {
1749 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1750
1751 if (sem->temp_syncobj || sem->syncobj)
1752 counts->syncobj_count++;
1753 else
1754 counts->sem_count++;
1755 }
1756
1757 if (counts->syncobj_count) {
1758 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1759 if (!counts->syncobj)
1760 return VK_ERROR_OUT_OF_HOST_MEMORY;
1761 }
1762
1763 if (counts->sem_count) {
1764 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1765 if (!counts->sem) {
1766 free(counts->syncobj);
1767 return VK_ERROR_OUT_OF_HOST_MEMORY;
1768 }
1769 }
1770
1771 for (uint32_t i = 0; i < num_sems; i++) {
1772 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1773
1774 if (sem->temp_syncobj) {
1775 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1776 if (reset_temp) {
1777 /* after we wait on a temp import - drop it */
1778 sem->temp_syncobj = 0;
1779 }
1780 }
1781 else if (sem->syncobj)
1782 counts->syncobj[syncobj_idx++] = sem->syncobj;
1783 else {
1784 assert(sem->sem);
1785 counts->sem[sem_idx++] = sem->sem;
1786 }
1787 }
1788
1789 return VK_SUCCESS;
1790 }
1791
1792 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1793 {
1794 free(sem_info->wait.syncobj);
1795 free(sem_info->wait.sem);
1796 free(sem_info->signal.syncobj);
1797 free(sem_info->signal.sem);
1798 }
1799
1800 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1801 int num_wait_sems,
1802 const VkSemaphore *wait_sems,
1803 int num_signal_sems,
1804 const VkSemaphore *signal_sems)
1805 {
1806 VkResult ret;
1807 memset(sem_info, 0, sizeof(*sem_info));
1808
1809 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
1810 if (ret)
1811 return ret;
1812 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
1813 if (ret)
1814 radv_free_sem_info(sem_info);
1815
1816 /* caller can override these */
1817 sem_info->cs_emit_wait = true;
1818 sem_info->cs_emit_signal = true;
1819 return ret;
1820 }
1821
1822 VkResult radv_QueueSubmit(
1823 VkQueue _queue,
1824 uint32_t submitCount,
1825 const VkSubmitInfo* pSubmits,
1826 VkFence _fence)
1827 {
1828 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1829 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1830 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1831 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1832 int ret;
1833 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1834 uint32_t scratch_size = 0;
1835 uint32_t compute_scratch_size = 0;
1836 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1837 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
1838 VkResult result;
1839 bool fence_emitted = false;
1840 bool tess_rings_needed = false;
1841 bool sample_positions_needed = false;
1842
1843 /* Do this first so failing to allocate scratch buffers can't result in
1844 * partially executed submissions. */
1845 for (uint32_t i = 0; i < submitCount; i++) {
1846 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1847 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1848 pSubmits[i].pCommandBuffers[j]);
1849
1850 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1851 compute_scratch_size = MAX2(compute_scratch_size,
1852 cmd_buffer->compute_scratch_size_needed);
1853 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1854 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1855 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1856 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1857 }
1858 }
1859
1860 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1861 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1862 sample_positions_needed, &initial_flush_preamble_cs,
1863 &initial_preamble_cs, &continue_preamble_cs);
1864 if (result != VK_SUCCESS)
1865 return result;
1866
1867 for (uint32_t i = 0; i < submitCount; i++) {
1868 struct radeon_winsys_cs **cs_array;
1869 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1870 bool can_patch = true;
1871 uint32_t advance;
1872 struct radv_winsys_sem_info sem_info;
1873
1874 result = radv_alloc_sem_info(&sem_info,
1875 pSubmits[i].waitSemaphoreCount,
1876 pSubmits[i].pWaitSemaphores,
1877 pSubmits[i].signalSemaphoreCount,
1878 pSubmits[i].pSignalSemaphores);
1879 if (result != VK_SUCCESS)
1880 return result;
1881
1882 if (!pSubmits[i].commandBufferCount) {
1883 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1884 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1885 &queue->device->empty_cs[queue->queue_family_index],
1886 1, NULL, NULL,
1887 &sem_info,
1888 false, base_fence);
1889 if (ret) {
1890 radv_loge("failed to submit CS %d\n", i);
1891 abort();
1892 }
1893 fence_emitted = true;
1894 }
1895 radv_free_sem_info(&sem_info);
1896 continue;
1897 }
1898
1899 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1900 (pSubmits[i].commandBufferCount));
1901
1902 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1903 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1904 pSubmits[i].pCommandBuffers[j]);
1905 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1906
1907 cs_array[j] = cmd_buffer->cs;
1908 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1909 can_patch = false;
1910 }
1911
1912 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
1913 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
1914 advance = MIN2(max_cs_submission,
1915 pSubmits[i].commandBufferCount - j);
1916
1917 if (queue->device->trace_bo)
1918 *queue->device->trace_id_ptr = 0;
1919
1920 sem_info.cs_emit_wait = j == 0;
1921 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
1922
1923 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1924 advance, initial_preamble, continue_preamble_cs,
1925 &sem_info,
1926 can_patch, base_fence);
1927
1928 if (ret) {
1929 radv_loge("failed to submit CS %d\n", i);
1930 abort();
1931 }
1932 fence_emitted = true;
1933 if (queue->device->trace_bo) {
1934 radv_check_gpu_hangs(queue, cs_array[j]);
1935 }
1936 }
1937
1938 radv_free_sem_info(&sem_info);
1939 free(cs_array);
1940 }
1941
1942 if (fence) {
1943 if (!fence_emitted) {
1944 struct radv_winsys_sem_info sem_info = {0};
1945 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1946 &queue->device->empty_cs[queue->queue_family_index],
1947 1, NULL, NULL, &sem_info,
1948 false, base_fence);
1949 }
1950 fence->submitted = true;
1951 }
1952
1953 return VK_SUCCESS;
1954 }
1955
1956 VkResult radv_QueueWaitIdle(
1957 VkQueue _queue)
1958 {
1959 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1960
1961 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1962 radv_queue_family_to_ring(queue->queue_family_index),
1963 queue->queue_idx);
1964 return VK_SUCCESS;
1965 }
1966
1967 VkResult radv_DeviceWaitIdle(
1968 VkDevice _device)
1969 {
1970 RADV_FROM_HANDLE(radv_device, device, _device);
1971
1972 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1973 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1974 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1975 }
1976 }
1977 return VK_SUCCESS;
1978 }
1979
1980 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1981 VkInstance instance,
1982 const char* pName)
1983 {
1984 return radv_lookup_entrypoint(pName);
1985 }
1986
1987 /* The loader wants us to expose a second GetInstanceProcAddr function
1988 * to work around certain LD_PRELOAD issues seen in apps.
1989 */
1990 PUBLIC
1991 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1992 VkInstance instance,
1993 const char* pName);
1994
1995 PUBLIC
1996 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1997 VkInstance instance,
1998 const char* pName)
1999 {
2000 return radv_GetInstanceProcAddr(instance, pName);
2001 }
2002
2003 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2004 VkDevice device,
2005 const char* pName)
2006 {
2007 return radv_lookup_entrypoint(pName);
2008 }
2009
2010 bool radv_get_memory_fd(struct radv_device *device,
2011 struct radv_device_memory *memory,
2012 int *pFD)
2013 {
2014 struct radeon_bo_metadata metadata;
2015
2016 if (memory->image) {
2017 radv_init_metadata(device, memory->image, &metadata);
2018 device->ws->buffer_set_metadata(memory->bo, &metadata);
2019 }
2020
2021 return device->ws->buffer_get_fd(device->ws, memory->bo,
2022 pFD);
2023 }
2024
2025 VkResult radv_AllocateMemory(
2026 VkDevice _device,
2027 const VkMemoryAllocateInfo* pAllocateInfo,
2028 const VkAllocationCallbacks* pAllocator,
2029 VkDeviceMemory* pMem)
2030 {
2031 RADV_FROM_HANDLE(radv_device, device, _device);
2032 struct radv_device_memory *mem;
2033 VkResult result;
2034 enum radeon_bo_domain domain;
2035 uint32_t flags = 0;
2036
2037 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2038
2039 if (pAllocateInfo->allocationSize == 0) {
2040 /* Apparently, this is allowed */
2041 *pMem = VK_NULL_HANDLE;
2042 return VK_SUCCESS;
2043 }
2044
2045 const VkImportMemoryFdInfoKHR *import_info =
2046 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2047 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2048 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2049
2050 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2051 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2052 if (mem == NULL)
2053 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2054
2055 if (dedicate_info) {
2056 mem->image = radv_image_from_handle(dedicate_info->image);
2057 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2058 } else {
2059 mem->image = NULL;
2060 mem->buffer = NULL;
2061 }
2062
2063 if (import_info) {
2064 assert(import_info->handleType ==
2065 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2066 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2067 NULL, NULL);
2068 if (!mem->bo) {
2069 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2070 goto fail;
2071 } else {
2072 close(import_info->fd);
2073 goto out_success;
2074 }
2075 }
2076
2077 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2078 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2079 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2080 domain = RADEON_DOMAIN_GTT;
2081 else
2082 domain = RADEON_DOMAIN_VRAM;
2083
2084 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2085 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2086 else
2087 flags |= RADEON_FLAG_CPU_ACCESS;
2088
2089 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2090 flags |= RADEON_FLAG_GTT_WC;
2091
2092 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2093 domain, flags);
2094
2095 if (!mem->bo) {
2096 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2097 goto fail;
2098 }
2099 mem->type_index = pAllocateInfo->memoryTypeIndex;
2100 out_success:
2101 *pMem = radv_device_memory_to_handle(mem);
2102
2103 return VK_SUCCESS;
2104
2105 fail:
2106 vk_free2(&device->alloc, pAllocator, mem);
2107
2108 return result;
2109 }
2110
2111 void radv_FreeMemory(
2112 VkDevice _device,
2113 VkDeviceMemory _mem,
2114 const VkAllocationCallbacks* pAllocator)
2115 {
2116 RADV_FROM_HANDLE(radv_device, device, _device);
2117 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2118
2119 if (mem == NULL)
2120 return;
2121
2122 device->ws->buffer_destroy(mem->bo);
2123 mem->bo = NULL;
2124
2125 vk_free2(&device->alloc, pAllocator, mem);
2126 }
2127
2128 VkResult radv_MapMemory(
2129 VkDevice _device,
2130 VkDeviceMemory _memory,
2131 VkDeviceSize offset,
2132 VkDeviceSize size,
2133 VkMemoryMapFlags flags,
2134 void** ppData)
2135 {
2136 RADV_FROM_HANDLE(radv_device, device, _device);
2137 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2138
2139 if (mem == NULL) {
2140 *ppData = NULL;
2141 return VK_SUCCESS;
2142 }
2143
2144 *ppData = device->ws->buffer_map(mem->bo);
2145 if (*ppData) {
2146 *ppData += offset;
2147 return VK_SUCCESS;
2148 }
2149
2150 return VK_ERROR_MEMORY_MAP_FAILED;
2151 }
2152
2153 void radv_UnmapMemory(
2154 VkDevice _device,
2155 VkDeviceMemory _memory)
2156 {
2157 RADV_FROM_HANDLE(radv_device, device, _device);
2158 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2159
2160 if (mem == NULL)
2161 return;
2162
2163 device->ws->buffer_unmap(mem->bo);
2164 }
2165
2166 VkResult radv_FlushMappedMemoryRanges(
2167 VkDevice _device,
2168 uint32_t memoryRangeCount,
2169 const VkMappedMemoryRange* pMemoryRanges)
2170 {
2171 return VK_SUCCESS;
2172 }
2173
2174 VkResult radv_InvalidateMappedMemoryRanges(
2175 VkDevice _device,
2176 uint32_t memoryRangeCount,
2177 const VkMappedMemoryRange* pMemoryRanges)
2178 {
2179 return VK_SUCCESS;
2180 }
2181
2182 void radv_GetBufferMemoryRequirements(
2183 VkDevice device,
2184 VkBuffer _buffer,
2185 VkMemoryRequirements* pMemoryRequirements)
2186 {
2187 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2188
2189 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2190
2191 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2192 pMemoryRequirements->alignment = 4096;
2193 else
2194 pMemoryRequirements->alignment = 16;
2195
2196 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2197 }
2198
2199 void radv_GetBufferMemoryRequirements2KHR(
2200 VkDevice device,
2201 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2202 VkMemoryRequirements2KHR* pMemoryRequirements)
2203 {
2204 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2205 &pMemoryRequirements->memoryRequirements);
2206
2207 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2208 switch (ext->sType) {
2209 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2210 VkMemoryDedicatedRequirementsKHR *req =
2211 (VkMemoryDedicatedRequirementsKHR *) ext;
2212 req->requiresDedicatedAllocation = false;
2213 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2214 break;
2215 }
2216 default:
2217 break;
2218 }
2219 }
2220 }
2221
2222 void radv_GetImageMemoryRequirements(
2223 VkDevice device,
2224 VkImage _image,
2225 VkMemoryRequirements* pMemoryRequirements)
2226 {
2227 RADV_FROM_HANDLE(radv_image, image, _image);
2228
2229 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2230
2231 pMemoryRequirements->size = image->size;
2232 pMemoryRequirements->alignment = image->alignment;
2233 }
2234
2235 void radv_GetImageMemoryRequirements2KHR(
2236 VkDevice device,
2237 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2238 VkMemoryRequirements2KHR* pMemoryRequirements)
2239 {
2240 radv_GetImageMemoryRequirements(device, pInfo->image,
2241 &pMemoryRequirements->memoryRequirements);
2242
2243 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2244
2245 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2246 switch (ext->sType) {
2247 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2248 VkMemoryDedicatedRequirementsKHR *req =
2249 (VkMemoryDedicatedRequirementsKHR *) ext;
2250 req->requiresDedicatedAllocation = image->shareable;
2251 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2252 break;
2253 }
2254 default:
2255 break;
2256 }
2257 }
2258 }
2259
2260 void radv_GetImageSparseMemoryRequirements(
2261 VkDevice device,
2262 VkImage image,
2263 uint32_t* pSparseMemoryRequirementCount,
2264 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2265 {
2266 stub();
2267 }
2268
2269 void radv_GetImageSparseMemoryRequirements2KHR(
2270 VkDevice device,
2271 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2272 uint32_t* pSparseMemoryRequirementCount,
2273 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2274 {
2275 stub();
2276 }
2277
2278 void radv_GetDeviceMemoryCommitment(
2279 VkDevice device,
2280 VkDeviceMemory memory,
2281 VkDeviceSize* pCommittedMemoryInBytes)
2282 {
2283 *pCommittedMemoryInBytes = 0;
2284 }
2285
2286 VkResult radv_BindBufferMemory2KHR(VkDevice device,
2287 uint32_t bindInfoCount,
2288 const VkBindBufferMemoryInfoKHR *pBindInfos)
2289 {
2290 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2291 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2292 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
2293
2294 if (mem) {
2295 buffer->bo = mem->bo;
2296 buffer->offset = pBindInfos[i].memoryOffset;
2297 } else {
2298 buffer->bo = NULL;
2299 }
2300 }
2301 return VK_SUCCESS;
2302 }
2303
2304 VkResult radv_BindBufferMemory(
2305 VkDevice device,
2306 VkBuffer buffer,
2307 VkDeviceMemory memory,
2308 VkDeviceSize memoryOffset)
2309 {
2310 const VkBindBufferMemoryInfoKHR info = {
2311 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2312 .buffer = buffer,
2313 .memory = memory,
2314 .memoryOffset = memoryOffset
2315 };
2316
2317 return radv_BindBufferMemory2KHR(device, 1, &info);
2318 }
2319
2320 VkResult radv_BindImageMemory2KHR(VkDevice device,
2321 uint32_t bindInfoCount,
2322 const VkBindImageMemoryInfoKHR *pBindInfos)
2323 {
2324 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2325 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
2326 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
2327
2328 if (mem) {
2329 image->bo = mem->bo;
2330 image->offset = pBindInfos[i].memoryOffset;
2331 } else {
2332 image->bo = NULL;
2333 image->offset = 0;
2334 }
2335 }
2336 return VK_SUCCESS;
2337 }
2338
2339
2340 VkResult radv_BindImageMemory(
2341 VkDevice device,
2342 VkImage image,
2343 VkDeviceMemory memory,
2344 VkDeviceSize memoryOffset)
2345 {
2346 const VkBindImageMemoryInfoKHR info = {
2347 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
2348 .image = image,
2349 .memory = memory,
2350 .memoryOffset = memoryOffset
2351 };
2352
2353 return radv_BindImageMemory2KHR(device, 1, &info);
2354 }
2355
2356
2357 static void
2358 radv_sparse_buffer_bind_memory(struct radv_device *device,
2359 const VkSparseBufferMemoryBindInfo *bind)
2360 {
2361 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2362
2363 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2364 struct radv_device_memory *mem = NULL;
2365
2366 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2367 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2368
2369 device->ws->buffer_virtual_bind(buffer->bo,
2370 bind->pBinds[i].resourceOffset,
2371 bind->pBinds[i].size,
2372 mem ? mem->bo : NULL,
2373 bind->pBinds[i].memoryOffset);
2374 }
2375 }
2376
2377 static void
2378 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2379 const VkSparseImageOpaqueMemoryBindInfo *bind)
2380 {
2381 RADV_FROM_HANDLE(radv_image, image, bind->image);
2382
2383 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2384 struct radv_device_memory *mem = NULL;
2385
2386 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2387 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2388
2389 device->ws->buffer_virtual_bind(image->bo,
2390 bind->pBinds[i].resourceOffset,
2391 bind->pBinds[i].size,
2392 mem ? mem->bo : NULL,
2393 bind->pBinds[i].memoryOffset);
2394 }
2395 }
2396
2397 VkResult radv_QueueBindSparse(
2398 VkQueue _queue,
2399 uint32_t bindInfoCount,
2400 const VkBindSparseInfo* pBindInfo,
2401 VkFence _fence)
2402 {
2403 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2404 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2405 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2406 bool fence_emitted = false;
2407
2408 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2409 struct radv_winsys_sem_info sem_info;
2410 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2411 radv_sparse_buffer_bind_memory(queue->device,
2412 pBindInfo[i].pBufferBinds + j);
2413 }
2414
2415 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2416 radv_sparse_image_opaque_bind_memory(queue->device,
2417 pBindInfo[i].pImageOpaqueBinds + j);
2418 }
2419
2420 VkResult result;
2421 result = radv_alloc_sem_info(&sem_info,
2422 pBindInfo[i].waitSemaphoreCount,
2423 pBindInfo[i].pWaitSemaphores,
2424 pBindInfo[i].signalSemaphoreCount,
2425 pBindInfo[i].pSignalSemaphores);
2426 if (result != VK_SUCCESS)
2427 return result;
2428
2429 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2430 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2431 &queue->device->empty_cs[queue->queue_family_index],
2432 1, NULL, NULL,
2433 &sem_info,
2434 false, base_fence);
2435 fence_emitted = true;
2436 if (fence)
2437 fence->submitted = true;
2438 }
2439
2440 radv_free_sem_info(&sem_info);
2441
2442 }
2443
2444 if (fence && !fence_emitted) {
2445 fence->signalled = true;
2446 }
2447
2448 return VK_SUCCESS;
2449 }
2450
2451 VkResult radv_CreateFence(
2452 VkDevice _device,
2453 const VkFenceCreateInfo* pCreateInfo,
2454 const VkAllocationCallbacks* pAllocator,
2455 VkFence* pFence)
2456 {
2457 RADV_FROM_HANDLE(radv_device, device, _device);
2458 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2459 sizeof(*fence), 8,
2460 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2461
2462 if (!fence)
2463 return VK_ERROR_OUT_OF_HOST_MEMORY;
2464
2465 memset(fence, 0, sizeof(*fence));
2466 fence->submitted = false;
2467 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2468 fence->fence = device->ws->create_fence();
2469 if (!fence->fence) {
2470 vk_free2(&device->alloc, pAllocator, fence);
2471 return VK_ERROR_OUT_OF_HOST_MEMORY;
2472 }
2473
2474 *pFence = radv_fence_to_handle(fence);
2475
2476 return VK_SUCCESS;
2477 }
2478
2479 void radv_DestroyFence(
2480 VkDevice _device,
2481 VkFence _fence,
2482 const VkAllocationCallbacks* pAllocator)
2483 {
2484 RADV_FROM_HANDLE(radv_device, device, _device);
2485 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2486
2487 if (!fence)
2488 return;
2489 device->ws->destroy_fence(fence->fence);
2490 vk_free2(&device->alloc, pAllocator, fence);
2491 }
2492
2493 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2494 {
2495 uint64_t current_time;
2496 struct timespec tv;
2497
2498 clock_gettime(CLOCK_MONOTONIC, &tv);
2499 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2500
2501 timeout = MIN2(UINT64_MAX - current_time, timeout);
2502
2503 return current_time + timeout;
2504 }
2505
2506 VkResult radv_WaitForFences(
2507 VkDevice _device,
2508 uint32_t fenceCount,
2509 const VkFence* pFences,
2510 VkBool32 waitAll,
2511 uint64_t timeout)
2512 {
2513 RADV_FROM_HANDLE(radv_device, device, _device);
2514 timeout = radv_get_absolute_timeout(timeout);
2515
2516 if (!waitAll && fenceCount > 1) {
2517 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2518 }
2519
2520 for (uint32_t i = 0; i < fenceCount; ++i) {
2521 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2522 bool expired = false;
2523
2524 if (fence->signalled)
2525 continue;
2526
2527 if (!fence->submitted)
2528 return VK_TIMEOUT;
2529
2530 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2531 if (!expired)
2532 return VK_TIMEOUT;
2533
2534 fence->signalled = true;
2535 }
2536
2537 return VK_SUCCESS;
2538 }
2539
2540 VkResult radv_ResetFences(VkDevice device,
2541 uint32_t fenceCount,
2542 const VkFence *pFences)
2543 {
2544 for (unsigned i = 0; i < fenceCount; ++i) {
2545 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2546 fence->submitted = fence->signalled = false;
2547 }
2548
2549 return VK_SUCCESS;
2550 }
2551
2552 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2553 {
2554 RADV_FROM_HANDLE(radv_device, device, _device);
2555 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2556
2557 if (fence->signalled)
2558 return VK_SUCCESS;
2559 if (!fence->submitted)
2560 return VK_NOT_READY;
2561
2562 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2563 return VK_NOT_READY;
2564
2565 return VK_SUCCESS;
2566 }
2567
2568
2569 // Queue semaphore functions
2570
2571 VkResult radv_CreateSemaphore(
2572 VkDevice _device,
2573 const VkSemaphoreCreateInfo* pCreateInfo,
2574 const VkAllocationCallbacks* pAllocator,
2575 VkSemaphore* pSemaphore)
2576 {
2577 RADV_FROM_HANDLE(radv_device, device, _device);
2578 const VkExportSemaphoreCreateInfoKHR *export =
2579 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2580 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2581 export ? export->handleTypes : 0;
2582
2583 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2584 sizeof(*sem), 8,
2585 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2586 if (!sem)
2587 return VK_ERROR_OUT_OF_HOST_MEMORY;
2588
2589 sem->temp_syncobj = 0;
2590 /* create a syncobject if we are going to export this semaphore */
2591 if (handleTypes) {
2592 assert (device->physical_device->rad_info.has_syncobj);
2593 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2594 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2595 if (ret) {
2596 vk_free2(&device->alloc, pAllocator, sem);
2597 return VK_ERROR_OUT_OF_HOST_MEMORY;
2598 }
2599 sem->sem = NULL;
2600 } else {
2601 sem->sem = device->ws->create_sem(device->ws);
2602 if (!sem->sem) {
2603 vk_free2(&device->alloc, pAllocator, sem);
2604 return VK_ERROR_OUT_OF_HOST_MEMORY;
2605 }
2606 sem->syncobj = 0;
2607 }
2608
2609 *pSemaphore = radv_semaphore_to_handle(sem);
2610 return VK_SUCCESS;
2611 }
2612
2613 void radv_DestroySemaphore(
2614 VkDevice _device,
2615 VkSemaphore _semaphore,
2616 const VkAllocationCallbacks* pAllocator)
2617 {
2618 RADV_FROM_HANDLE(radv_device, device, _device);
2619 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2620 if (!_semaphore)
2621 return;
2622
2623 if (sem->syncobj)
2624 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2625 else
2626 device->ws->destroy_sem(sem->sem);
2627 vk_free2(&device->alloc, pAllocator, sem);
2628 }
2629
2630 VkResult radv_CreateEvent(
2631 VkDevice _device,
2632 const VkEventCreateInfo* pCreateInfo,
2633 const VkAllocationCallbacks* pAllocator,
2634 VkEvent* pEvent)
2635 {
2636 RADV_FROM_HANDLE(radv_device, device, _device);
2637 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2638 sizeof(*event), 8,
2639 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2640
2641 if (!event)
2642 return VK_ERROR_OUT_OF_HOST_MEMORY;
2643
2644 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2645 RADEON_DOMAIN_GTT,
2646 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2647 if (!event->bo) {
2648 vk_free2(&device->alloc, pAllocator, event);
2649 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2650 }
2651
2652 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2653
2654 *pEvent = radv_event_to_handle(event);
2655
2656 return VK_SUCCESS;
2657 }
2658
2659 void radv_DestroyEvent(
2660 VkDevice _device,
2661 VkEvent _event,
2662 const VkAllocationCallbacks* pAllocator)
2663 {
2664 RADV_FROM_HANDLE(radv_device, device, _device);
2665 RADV_FROM_HANDLE(radv_event, event, _event);
2666
2667 if (!event)
2668 return;
2669 device->ws->buffer_destroy(event->bo);
2670 vk_free2(&device->alloc, pAllocator, event);
2671 }
2672
2673 VkResult radv_GetEventStatus(
2674 VkDevice _device,
2675 VkEvent _event)
2676 {
2677 RADV_FROM_HANDLE(radv_event, event, _event);
2678
2679 if (*event->map == 1)
2680 return VK_EVENT_SET;
2681 return VK_EVENT_RESET;
2682 }
2683
2684 VkResult radv_SetEvent(
2685 VkDevice _device,
2686 VkEvent _event)
2687 {
2688 RADV_FROM_HANDLE(radv_event, event, _event);
2689 *event->map = 1;
2690
2691 return VK_SUCCESS;
2692 }
2693
2694 VkResult radv_ResetEvent(
2695 VkDevice _device,
2696 VkEvent _event)
2697 {
2698 RADV_FROM_HANDLE(radv_event, event, _event);
2699 *event->map = 0;
2700
2701 return VK_SUCCESS;
2702 }
2703
2704 VkResult radv_CreateBuffer(
2705 VkDevice _device,
2706 const VkBufferCreateInfo* pCreateInfo,
2707 const VkAllocationCallbacks* pAllocator,
2708 VkBuffer* pBuffer)
2709 {
2710 RADV_FROM_HANDLE(radv_device, device, _device);
2711 struct radv_buffer *buffer;
2712
2713 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2714
2715 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2716 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2717 if (buffer == NULL)
2718 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2719
2720 buffer->size = pCreateInfo->size;
2721 buffer->usage = pCreateInfo->usage;
2722 buffer->bo = NULL;
2723 buffer->offset = 0;
2724 buffer->flags = pCreateInfo->flags;
2725
2726 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2727 buffer->bo = device->ws->buffer_create(device->ws,
2728 align64(buffer->size, 4096),
2729 4096, 0, RADEON_FLAG_VIRTUAL);
2730 if (!buffer->bo) {
2731 vk_free2(&device->alloc, pAllocator, buffer);
2732 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2733 }
2734 }
2735
2736 *pBuffer = radv_buffer_to_handle(buffer);
2737
2738 return VK_SUCCESS;
2739 }
2740
2741 void radv_DestroyBuffer(
2742 VkDevice _device,
2743 VkBuffer _buffer,
2744 const VkAllocationCallbacks* pAllocator)
2745 {
2746 RADV_FROM_HANDLE(radv_device, device, _device);
2747 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2748
2749 if (!buffer)
2750 return;
2751
2752 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2753 device->ws->buffer_destroy(buffer->bo);
2754
2755 vk_free2(&device->alloc, pAllocator, buffer);
2756 }
2757
2758 static inline unsigned
2759 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2760 {
2761 if (stencil)
2762 return image->surface.u.legacy.stencil_tiling_index[level];
2763 else
2764 return image->surface.u.legacy.tiling_index[level];
2765 }
2766
2767 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2768 {
2769 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2770 }
2771
2772 static void
2773 radv_initialise_color_surface(struct radv_device *device,
2774 struct radv_color_buffer_info *cb,
2775 struct radv_image_view *iview)
2776 {
2777 const struct vk_format_description *desc;
2778 unsigned ntype, format, swap, endian;
2779 unsigned blend_clamp = 0, blend_bypass = 0;
2780 uint64_t va;
2781 const struct radeon_surf *surf = &iview->image->surface;
2782
2783 desc = vk_format_description(iview->vk_format);
2784
2785 memset(cb, 0, sizeof(*cb));
2786
2787 /* Intensity is implemented as Red, so treat it that way. */
2788 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2789
2790 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2791
2792 cb->cb_color_base = va >> 8;
2793
2794 if (device->physical_device->rad_info.chip_class >= GFX9) {
2795 struct gfx9_surf_meta_flags meta;
2796 if (iview->image->dcc_offset)
2797 meta = iview->image->surface.u.gfx9.dcc;
2798 else
2799 meta = iview->image->surface.u.gfx9.cmask;
2800
2801 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2802 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2803 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2804 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2805
2806 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2807 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2808 } else {
2809 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2810 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2811
2812 cb->cb_color_base += level_info->offset >> 8;
2813 if (level_info->mode == RADEON_SURF_MODE_2D)
2814 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2815
2816 pitch_tile_max = level_info->nblk_x / 8 - 1;
2817 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2818 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2819
2820 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2821 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2822 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2823
2824 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2825 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2826
2827 if (iview->image->fmask.size) {
2828 if (device->physical_device->rad_info.chip_class >= CIK)
2829 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2830 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2831 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2832 } else {
2833 /* This must be set for fast clear to work without FMASK. */
2834 if (device->physical_device->rad_info.chip_class >= CIK)
2835 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2836 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2837 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2838 }
2839 }
2840
2841 /* CMASK variables */
2842 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2843 va += iview->image->cmask.offset;
2844 cb->cb_color_cmask = va >> 8;
2845
2846 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
2847 va += iview->image->dcc_offset;
2848 cb->cb_dcc_base = va >> 8;
2849 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
2850
2851 uint32_t max_slice = radv_surface_layer_count(iview);
2852 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2853 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2854
2855 if (iview->image->info.samples > 1) {
2856 unsigned log_samples = util_logbase2(iview->image->info.samples);
2857
2858 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2859 S_028C74_NUM_FRAGMENTS(log_samples);
2860 }
2861
2862 if (iview->image->fmask.size) {
2863 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2864 cb->cb_color_fmask = va >> 8;
2865 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
2866 } else {
2867 cb->cb_color_fmask = cb->cb_color_base;
2868 }
2869
2870 ntype = radv_translate_color_numformat(iview->vk_format,
2871 desc,
2872 vk_format_get_first_non_void_channel(iview->vk_format));
2873 format = radv_translate_colorformat(iview->vk_format);
2874 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2875 radv_finishme("Illegal color\n");
2876 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2877 endian = radv_colorformat_endian_swap(format);
2878
2879 /* blend clamp should be set for all NORM/SRGB types */
2880 if (ntype == V_028C70_NUMBER_UNORM ||
2881 ntype == V_028C70_NUMBER_SNORM ||
2882 ntype == V_028C70_NUMBER_SRGB)
2883 blend_clamp = 1;
2884
2885 /* set blend bypass according to docs if SINT/UINT or
2886 8/24 COLOR variants */
2887 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2888 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2889 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2890 blend_clamp = 0;
2891 blend_bypass = 1;
2892 }
2893 #if 0
2894 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2895 (format == V_028C70_COLOR_8 ||
2896 format == V_028C70_COLOR_8_8 ||
2897 format == V_028C70_COLOR_8_8_8_8))
2898 ->color_is_int8 = true;
2899 #endif
2900 cb->cb_color_info = S_028C70_FORMAT(format) |
2901 S_028C70_COMP_SWAP(swap) |
2902 S_028C70_BLEND_CLAMP(blend_clamp) |
2903 S_028C70_BLEND_BYPASS(blend_bypass) |
2904 S_028C70_SIMPLE_FLOAT(1) |
2905 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2906 ntype != V_028C70_NUMBER_SNORM &&
2907 ntype != V_028C70_NUMBER_SRGB &&
2908 format != V_028C70_COLOR_8_24 &&
2909 format != V_028C70_COLOR_24_8) |
2910 S_028C70_NUMBER_TYPE(ntype) |
2911 S_028C70_ENDIAN(endian);
2912 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
2913 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2914 if (device->physical_device->rad_info.chip_class == SI) {
2915 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
2916 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
2917 }
2918 }
2919
2920 if (iview->image->cmask.size &&
2921 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2922 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2923
2924 if (radv_vi_dcc_enabled(iview->image, iview->base_mip))
2925 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2926
2927 if (device->physical_device->rad_info.chip_class >= VI) {
2928 unsigned max_uncompressed_block_size = 2;
2929 if (iview->image->info.samples > 1) {
2930 if (iview->image->surface.bpe == 1)
2931 max_uncompressed_block_size = 0;
2932 else if (iview->image->surface.bpe == 2)
2933 max_uncompressed_block_size = 1;
2934 }
2935
2936 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2937 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2938 }
2939
2940 /* This must be set for fast clear to work without FMASK. */
2941 if (!iview->image->fmask.size &&
2942 device->physical_device->rad_info.chip_class == SI) {
2943 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
2944 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2945 }
2946
2947 if (device->physical_device->rad_info.chip_class >= GFX9) {
2948 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
2949 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
2950
2951 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
2952 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2953 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
2954 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
2955 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
2956 S_028C68_MAX_MIP(iview->image->info.levels - 1);
2957
2958 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
2959
2960 }
2961 }
2962
2963 static void
2964 radv_initialise_ds_surface(struct radv_device *device,
2965 struct radv_ds_buffer_info *ds,
2966 struct radv_image_view *iview)
2967 {
2968 unsigned level = iview->base_mip;
2969 unsigned format, stencil_format;
2970 uint64_t va, s_offs, z_offs;
2971 bool stencil_only = false;
2972 memset(ds, 0, sizeof(*ds));
2973 switch (iview->image->vk_format) {
2974 case VK_FORMAT_D24_UNORM_S8_UINT:
2975 case VK_FORMAT_X8_D24_UNORM_PACK32:
2976 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2977 ds->offset_scale = 2.0f;
2978 break;
2979 case VK_FORMAT_D16_UNORM:
2980 case VK_FORMAT_D16_UNORM_S8_UINT:
2981 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2982 ds->offset_scale = 4.0f;
2983 break;
2984 case VK_FORMAT_D32_SFLOAT:
2985 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2986 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2987 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2988 ds->offset_scale = 1.0f;
2989 break;
2990 case VK_FORMAT_S8_UINT:
2991 stencil_only = true;
2992 break;
2993 default:
2994 break;
2995 }
2996
2997 format = radv_translate_dbformat(iview->image->vk_format);
2998 stencil_format = iview->image->surface.has_stencil ?
2999 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3000
3001 uint32_t max_slice = radv_surface_layer_count(iview);
3002 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3003 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3004
3005 ds->db_htile_data_base = 0;
3006 ds->db_htile_surface = 0;
3007
3008 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3009 s_offs = z_offs = va;
3010
3011 if (device->physical_device->rad_info.chip_class >= GFX9) {
3012 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3013 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3014
3015 ds->db_z_info = S_028038_FORMAT(format) |
3016 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3017 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3018 S_028038_MAXMIP(iview->image->info.levels - 1);
3019 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3020 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3021
3022 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3023 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3024 ds->db_depth_view |= S_028008_MIPID(level);
3025
3026 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3027 S_02801C_Y_MAX(iview->image->info.height - 1);
3028
3029 if (radv_htile_enabled(iview->image, level)) {
3030 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3031
3032 if (iview->image->tc_compatible_htile) {
3033 unsigned max_zplanes = 4;
3034
3035 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
3036 iview->image->info.samples > 1)
3037 max_zplanes = 2;
3038
3039 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
3040 S_028038_ITERATE_FLUSH(1);
3041 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
3042 }
3043
3044 if (!iview->image->surface.has_stencil)
3045 /* Use all of the htile_buffer for depth if there's no stencil. */
3046 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3047 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3048 iview->image->htile_offset;
3049 ds->db_htile_data_base = va >> 8;
3050 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3051 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3052 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3053 }
3054 } else {
3055 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3056
3057 if (stencil_only)
3058 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3059
3060 z_offs += iview->image->surface.u.legacy.level[level].offset;
3061 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3062
3063 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
3064 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3065 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3066
3067 if (iview->image->info.samples > 1)
3068 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3069
3070 if (device->physical_device->rad_info.chip_class >= CIK) {
3071 struct radeon_info *info = &device->physical_device->rad_info;
3072 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3073 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3074 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3075 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3076 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3077 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3078
3079 if (stencil_only)
3080 tile_mode = stencil_tile_mode;
3081
3082 ds->db_depth_info |=
3083 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3084 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3085 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3086 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3087 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3088 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3089 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3090 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3091 } else {
3092 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3093 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3094 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3095 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3096 if (stencil_only)
3097 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3098 }
3099
3100 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3101 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3102 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3103
3104 if (radv_htile_enabled(iview->image, level)) {
3105 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3106
3107 if (!iview->image->surface.has_stencil &&
3108 !iview->image->tc_compatible_htile)
3109 /* Use all of the htile_buffer for depth if there's no stencil. */
3110 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3111
3112 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
3113 iview->image->htile_offset;
3114 ds->db_htile_data_base = va >> 8;
3115 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3116
3117 if (iview->image->tc_compatible_htile) {
3118 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
3119
3120 if (iview->image->info.samples <= 1)
3121 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(5);
3122 else if (iview->image->info.samples <= 4)
3123 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(3);
3124 else
3125 ds->db_z_info|= S_028040_DECOMPRESS_ON_N_ZPLANES(2);
3126 }
3127 }
3128 }
3129
3130 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3131 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3132 }
3133
3134 VkResult radv_CreateFramebuffer(
3135 VkDevice _device,
3136 const VkFramebufferCreateInfo* pCreateInfo,
3137 const VkAllocationCallbacks* pAllocator,
3138 VkFramebuffer* pFramebuffer)
3139 {
3140 RADV_FROM_HANDLE(radv_device, device, _device);
3141 struct radv_framebuffer *framebuffer;
3142
3143 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3144
3145 size_t size = sizeof(*framebuffer) +
3146 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3147 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3148 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3149 if (framebuffer == NULL)
3150 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3151
3152 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3153 framebuffer->width = pCreateInfo->width;
3154 framebuffer->height = pCreateInfo->height;
3155 framebuffer->layers = pCreateInfo->layers;
3156 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3157 VkImageView _iview = pCreateInfo->pAttachments[i];
3158 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3159 framebuffer->attachments[i].attachment = iview;
3160 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3161 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3162 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3163 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3164 }
3165 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3166 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3167 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3168 }
3169
3170 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3171 return VK_SUCCESS;
3172 }
3173
3174 void radv_DestroyFramebuffer(
3175 VkDevice _device,
3176 VkFramebuffer _fb,
3177 const VkAllocationCallbacks* pAllocator)
3178 {
3179 RADV_FROM_HANDLE(radv_device, device, _device);
3180 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3181
3182 if (!fb)
3183 return;
3184 vk_free2(&device->alloc, pAllocator, fb);
3185 }
3186
3187 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3188 {
3189 switch (address_mode) {
3190 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3191 return V_008F30_SQ_TEX_WRAP;
3192 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3193 return V_008F30_SQ_TEX_MIRROR;
3194 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3195 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3196 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3197 return V_008F30_SQ_TEX_CLAMP_BORDER;
3198 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3199 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3200 default:
3201 unreachable("illegal tex wrap mode");
3202 break;
3203 }
3204 }
3205
3206 static unsigned
3207 radv_tex_compare(VkCompareOp op)
3208 {
3209 switch (op) {
3210 case VK_COMPARE_OP_NEVER:
3211 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3212 case VK_COMPARE_OP_LESS:
3213 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3214 case VK_COMPARE_OP_EQUAL:
3215 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3216 case VK_COMPARE_OP_LESS_OR_EQUAL:
3217 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3218 case VK_COMPARE_OP_GREATER:
3219 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3220 case VK_COMPARE_OP_NOT_EQUAL:
3221 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3222 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3223 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3224 case VK_COMPARE_OP_ALWAYS:
3225 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3226 default:
3227 unreachable("illegal compare mode");
3228 break;
3229 }
3230 }
3231
3232 static unsigned
3233 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3234 {
3235 switch (filter) {
3236 case VK_FILTER_NEAREST:
3237 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3238 V_008F38_SQ_TEX_XY_FILTER_POINT);
3239 case VK_FILTER_LINEAR:
3240 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3241 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3242 case VK_FILTER_CUBIC_IMG:
3243 default:
3244 fprintf(stderr, "illegal texture filter");
3245 return 0;
3246 }
3247 }
3248
3249 static unsigned
3250 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3251 {
3252 switch (mode) {
3253 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3254 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3255 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3256 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3257 default:
3258 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3259 }
3260 }
3261
3262 static unsigned
3263 radv_tex_bordercolor(VkBorderColor bcolor)
3264 {
3265 switch (bcolor) {
3266 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3267 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3268 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3269 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3270 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3271 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3272 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3273 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3274 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3275 default:
3276 break;
3277 }
3278 return 0;
3279 }
3280
3281 static unsigned
3282 radv_tex_aniso_filter(unsigned filter)
3283 {
3284 if (filter < 2)
3285 return 0;
3286 if (filter < 4)
3287 return 1;
3288 if (filter < 8)
3289 return 2;
3290 if (filter < 16)
3291 return 3;
3292 return 4;
3293 }
3294
3295 static void
3296 radv_init_sampler(struct radv_device *device,
3297 struct radv_sampler *sampler,
3298 const VkSamplerCreateInfo *pCreateInfo)
3299 {
3300 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3301 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3302 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3303 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3304
3305 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3306 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3307 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3308 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3309 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3310 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3311 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3312 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3313 S_008F30_DISABLE_CUBE_WRAP(0) |
3314 S_008F30_COMPAT_MODE(is_vi));
3315 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3316 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3317 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3318 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3319 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3320 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3321 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3322 S_008F38_MIP_POINT_PRECLAMP(0) |
3323 S_008F38_DISABLE_LSB_CEIL(1) |
3324 S_008F38_FILTER_PREC_FIX(1) |
3325 S_008F38_ANISO_OVERRIDE(is_vi));
3326 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3327 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3328 }
3329
3330 VkResult radv_CreateSampler(
3331 VkDevice _device,
3332 const VkSamplerCreateInfo* pCreateInfo,
3333 const VkAllocationCallbacks* pAllocator,
3334 VkSampler* pSampler)
3335 {
3336 RADV_FROM_HANDLE(radv_device, device, _device);
3337 struct radv_sampler *sampler;
3338
3339 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3340
3341 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3342 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3343 if (!sampler)
3344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3345
3346 radv_init_sampler(device, sampler, pCreateInfo);
3347 *pSampler = radv_sampler_to_handle(sampler);
3348
3349 return VK_SUCCESS;
3350 }
3351
3352 void radv_DestroySampler(
3353 VkDevice _device,
3354 VkSampler _sampler,
3355 const VkAllocationCallbacks* pAllocator)
3356 {
3357 RADV_FROM_HANDLE(radv_device, device, _device);
3358 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3359
3360 if (!sampler)
3361 return;
3362 vk_free2(&device->alloc, pAllocator, sampler);
3363 }
3364
3365 /* vk_icd.h does not declare this function, so we declare it here to
3366 * suppress Wmissing-prototypes.
3367 */
3368 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3369 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3370
3371 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3372 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3373 {
3374 /* For the full details on loader interface versioning, see
3375 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3376 * What follows is a condensed summary, to help you navigate the large and
3377 * confusing official doc.
3378 *
3379 * - Loader interface v0 is incompatible with later versions. We don't
3380 * support it.
3381 *
3382 * - In loader interface v1:
3383 * - The first ICD entrypoint called by the loader is
3384 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3385 * entrypoint.
3386 * - The ICD must statically expose no other Vulkan symbol unless it is
3387 * linked with -Bsymbolic.
3388 * - Each dispatchable Vulkan handle created by the ICD must be
3389 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3390 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3391 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3392 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3393 * such loader-managed surfaces.
3394 *
3395 * - Loader interface v2 differs from v1 in:
3396 * - The first ICD entrypoint called by the loader is
3397 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3398 * statically expose this entrypoint.
3399 *
3400 * - Loader interface v3 differs from v2 in:
3401 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3402 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3403 * because the loader no longer does so.
3404 */
3405 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3406 return VK_SUCCESS;
3407 }
3408
3409 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3410 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3411 int *pFD)
3412 {
3413 RADV_FROM_HANDLE(radv_device, device, _device);
3414 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3415
3416 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3417
3418 /* We support only one handle type. */
3419 assert(pGetFdInfo->handleType ==
3420 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3421
3422 bool ret = radv_get_memory_fd(device, memory, pFD);
3423 if (ret == false)
3424 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3425 return VK_SUCCESS;
3426 }
3427
3428 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3429 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3430 int fd,
3431 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3432 {
3433 /* The valid usage section for this function says:
3434 *
3435 * "handleType must not be one of the handle types defined as opaque."
3436 *
3437 * Since we only handle opaque handles for now, there are no FD properties.
3438 */
3439 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3440 }
3441
3442 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3443 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3444 {
3445 RADV_FROM_HANDLE(radv_device, device, _device);
3446 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3447 uint32_t syncobj_handle = 0;
3448 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3449
3450 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3451 if (ret != 0)
3452 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3453
3454 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3455 sem->temp_syncobj = syncobj_handle;
3456 } else {
3457 sem->syncobj = syncobj_handle;
3458 }
3459 close(pImportSemaphoreFdInfo->fd);
3460 return VK_SUCCESS;
3461 }
3462
3463 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3464 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3465 int *pFd)
3466 {
3467 RADV_FROM_HANDLE(radv_device, device, _device);
3468 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3469 int ret;
3470 uint32_t syncobj_handle;
3471
3472 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3473 if (sem->temp_syncobj)
3474 syncobj_handle = sem->temp_syncobj;
3475 else
3476 syncobj_handle = sem->syncobj;
3477 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3478 if (ret)
3479 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3480 return VK_SUCCESS;
3481 }
3482
3483 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3484 VkPhysicalDevice physicalDevice,
3485 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3486 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3487 {
3488 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3489 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3490 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3491 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3492 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3493 } else {
3494 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3495 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3496 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3497 }
3498 }