2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
30 #include <linux/audit.h>
31 #include <linux/bpf.h>
32 #include <linux/filter.h>
33 #include <linux/seccomp.h>
34 #include <linux/unistd.h>
39 #include <sys/prctl.h>
43 #include <llvm/Config/llvm-config.h>
45 #include "radv_debug.h"
46 #include "radv_private.h"
47 #include "radv_shader.h"
49 #include "util/disk_cache.h"
50 #include "util/strtod.h"
54 #include <amdgpu_drm.h>
55 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
56 #include "ac_llvm_util.h"
57 #include "vk_format.h"
60 #include "util/build_id.h"
61 #include "util/debug.h"
62 #include "util/mesa-sha1.h"
63 #include "compiler/glsl_types.h"
64 #include "util/xmlpool.h"
67 radv_device_get_cache_uuid(enum radeon_family family
, void *uuid
)
70 unsigned char sha1
[20];
71 unsigned ptr_size
= sizeof(void*);
73 memset(uuid
, 0, VK_UUID_SIZE
);
74 _mesa_sha1_init(&ctx
);
76 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid
, &ctx
) ||
77 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo
, &ctx
))
80 _mesa_sha1_update(&ctx
, &family
, sizeof(family
));
81 _mesa_sha1_update(&ctx
, &ptr_size
, sizeof(ptr_size
));
82 _mesa_sha1_final(&ctx
, sha1
);
84 memcpy(uuid
, sha1
, VK_UUID_SIZE
);
89 radv_get_driver_uuid(void *uuid
)
91 ac_compute_driver_uuid(uuid
, VK_UUID_SIZE
);
95 radv_get_device_uuid(struct radeon_info
*info
, void *uuid
)
97 ac_compute_device_uuid(info
, uuid
, VK_UUID_SIZE
);
101 radv_get_visible_vram_size(struct radv_physical_device
*device
)
103 return MIN2(device
->rad_info
.vram_size
, device
->rad_info
.vram_vis_size
);
107 radv_get_vram_size(struct radv_physical_device
*device
)
109 return device
->rad_info
.vram_size
- radv_get_visible_vram_size(device
);
113 radv_physical_device_init_mem_types(struct radv_physical_device
*device
)
115 STATIC_ASSERT(RADV_MEM_HEAP_COUNT
<= VK_MAX_MEMORY_HEAPS
);
116 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
117 uint64_t vram_size
= radv_get_vram_size(device
);
118 int vram_index
= -1, visible_vram_index
= -1, gart_index
= -1;
119 device
->memory_properties
.memoryHeapCount
= 0;
121 vram_index
= device
->memory_properties
.memoryHeapCount
++;
122 device
->memory_properties
.memoryHeaps
[vram_index
] = (VkMemoryHeap
) {
124 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
127 if (visible_vram_size
) {
128 visible_vram_index
= device
->memory_properties
.memoryHeapCount
++;
129 device
->memory_properties
.memoryHeaps
[visible_vram_index
] = (VkMemoryHeap
) {
130 .size
= visible_vram_size
,
131 .flags
= VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
134 if (device
->rad_info
.gart_size
> 0) {
135 gart_index
= device
->memory_properties
.memoryHeapCount
++;
136 device
->memory_properties
.memoryHeaps
[gart_index
] = (VkMemoryHeap
) {
137 .size
= device
->rad_info
.gart_size
,
138 .flags
= device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT
,
142 STATIC_ASSERT(RADV_MEM_TYPE_COUNT
<= VK_MAX_MEMORY_TYPES
);
143 unsigned type_count
= 0;
144 if (vram_index
>= 0) {
145 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM
;
146 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
147 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
,
148 .heapIndex
= vram_index
,
151 if (gart_index
>= 0 && device
->rad_info
.has_dedicated_vram
) {
152 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
153 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
154 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
155 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
156 .heapIndex
= gart_index
,
159 if (visible_vram_index
>= 0) {
160 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_VRAM_CPU_ACCESS
;
161 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
162 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
163 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
164 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
165 .heapIndex
= visible_vram_index
,
168 if (gart_index
>= 0 && !device
->rad_info
.has_dedicated_vram
) {
169 /* Put GTT after visible VRAM for GPUs without dedicated VRAM
170 * as they have identical property flags, and according to the
171 * spec, for types with identical flags, the one with greater
172 * performance must be given a lower index. */
173 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_WRITE_COMBINE
;
174 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
175 .propertyFlags
= VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
|
176 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
,
178 .heapIndex
= gart_index
,
181 if (gart_index
>= 0) {
182 device
->mem_type_indices
[type_count
] = RADV_MEM_TYPE_GTT_CACHED
;
183 device
->memory_properties
.memoryTypes
[type_count
++] = (VkMemoryType
) {
184 .propertyFlags
= VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT
|
185 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT
|
186 VK_MEMORY_PROPERTY_HOST_CACHED_BIT
|
187 (device
->rad_info
.has_dedicated_vram
? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT
),
188 .heapIndex
= gart_index
,
191 device
->memory_properties
.memoryTypeCount
= type_count
;
195 radv_handle_env_var_force_family(struct radv_physical_device
*device
)
197 const char *family
= getenv("RADV_FORCE_FAMILY");
203 for (i
= CHIP_TAHITI
; i
< CHIP_LAST
; i
++) {
204 if (!strcmp(family
, ac_get_llvm_processor_name(i
))) {
205 /* Override family and chip_class. */
206 device
->rad_info
.family
= i
;
208 if (i
>= CHIP_NAVI10
)
209 device
->rad_info
.chip_class
= GFX10
;
210 else if (i
>= CHIP_VEGA10
)
211 device
->rad_info
.chip_class
= GFX9
;
212 else if (i
>= CHIP_TONGA
)
213 device
->rad_info
.chip_class
= GFX8
;
214 else if (i
>= CHIP_BONAIRE
)
215 device
->rad_info
.chip_class
= GFX7
;
217 device
->rad_info
.chip_class
= GFX6
;
223 fprintf(stderr
, "radv: Unknown family: %s\n", family
);
228 radv_physical_device_init(struct radv_physical_device
*device
,
229 struct radv_instance
*instance
,
230 drmDevicePtr drm_device
)
232 const char *path
= drm_device
->nodes
[DRM_NODE_RENDER
];
234 drmVersionPtr version
;
238 fd
= open(path
, O_RDWR
| O_CLOEXEC
);
240 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
241 radv_logi("Could not open device '%s'", path
);
243 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
246 version
= drmGetVersion(fd
);
250 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
251 radv_logi("Could not get the kernel driver version for device '%s'", path
);
253 return vk_errorf(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
,
254 "failed to get version %s: %m", path
);
257 if (strcmp(version
->name
, "amdgpu")) {
258 drmFreeVersion(version
);
261 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
262 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path
);
264 return VK_ERROR_INCOMPATIBLE_DRIVER
;
266 drmFreeVersion(version
);
268 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
269 radv_logi("Found compatible device '%s'.", path
);
271 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
272 device
->instance
= instance
;
274 device
->ws
= radv_amdgpu_winsys_create(fd
, instance
->debug_flags
,
275 instance
->perftest_flags
);
277 result
= vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
281 if (instance
->enabled_extensions
.KHR_display
) {
282 master_fd
= open(drm_device
->nodes
[DRM_NODE_PRIMARY
], O_RDWR
| O_CLOEXEC
);
283 if (master_fd
>= 0) {
284 uint32_t accel_working
= 0;
285 struct drm_amdgpu_info request
= {
286 .return_pointer
= (uintptr_t)&accel_working
,
287 .return_size
= sizeof(accel_working
),
288 .query
= AMDGPU_INFO_ACCEL_WORKING
291 if (drmCommandWrite(master_fd
, DRM_AMDGPU_INFO
, &request
, sizeof (struct drm_amdgpu_info
)) < 0 || !accel_working
) {
298 device
->master_fd
= master_fd
;
299 device
->local_fd
= fd
;
300 device
->ws
->query_info(device
->ws
, &device
->rad_info
);
302 radv_handle_env_var_force_family(device
);
304 device
->use_aco
= instance
->perftest_flags
& RADV_PERFTEST_ACO
;
305 if ((device
->rad_info
.chip_class
< GFX8
||
306 device
->rad_info
.chip_class
> GFX9
) && device
->use_aco
) {
307 fprintf(stderr
, "WARNING: disabling ACO on unsupported GPUs.\n");
308 device
->use_aco
= false;
311 snprintf(device
->name
, sizeof(device
->name
),
312 "AMD RADV%s %s (LLVM " MESA_LLVM_VERSION_STRING
")", device
->use_aco
? "/ACO" : "",
313 device
->rad_info
.name
);
315 if (radv_device_get_cache_uuid(device
->rad_info
.family
, device
->cache_uuid
)) {
316 device
->ws
->destroy(device
->ws
);
317 result
= vk_errorf(instance
, VK_ERROR_INITIALIZATION_FAILED
,
318 "cannot generate UUID");
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags
=
324 (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
? 0x1 : 0) |
325 (device
->instance
->debug_flags
& RADV_DEBUG_UNSAFE_MATH
? 0x2 : 0) |
326 (device
->use_aco
? 0x4 : 0);
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
331 char buf
[VK_UUID_SIZE
* 2 + 1];
332 disk_cache_format_hex_id(buf
, device
->cache_uuid
, VK_UUID_SIZE
* 2);
333 device
->disk_cache
= disk_cache_create(device
->name
, buf
, shader_env_flags
);
335 if (device
->rad_info
.chip_class
< GFX8
||
336 device
->rad_info
.chip_class
> GFX9
)
337 fprintf(stderr
, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
339 radv_get_driver_uuid(&device
->driver_uuid
);
340 radv_get_device_uuid(&device
->rad_info
, &device
->device_uuid
);
342 device
->out_of_order_rast_allowed
= device
->rad_info
.has_out_of_order_rast
&&
343 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_OUT_OF_ORDER
);
345 device
->dcc_msaa_allowed
=
346 (device
->instance
->perftest_flags
& RADV_PERFTEST_DCC_MSAA
);
348 device
->use_shader_ballot
= device
->rad_info
.chip_class
>= GFX8
&&
349 (device
->use_aco
|| device
->instance
->perftest_flags
& RADV_PERFTEST_SHADER_BALLOT
);
351 device
->use_ngg
= device
->rad_info
.chip_class
>= GFX10
&&
352 device
->rad_info
.family
!= CHIP_NAVI14
&&
353 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
);
354 if (device
->use_aco
&& device
->use_ngg
) {
355 fprintf(stderr
, "WARNING: disabling NGG because ACO is used.\n");
356 device
->use_ngg
= false;
359 device
->use_ngg_streamout
= false;
361 /* Determine the number of threads per wave for all stages. */
362 device
->cs_wave_size
= 64;
363 device
->ps_wave_size
= 64;
364 device
->ge_wave_size
= 64;
366 if (device
->rad_info
.chip_class
>= GFX10
) {
367 if (device
->instance
->perftest_flags
& RADV_PERFTEST_CS_WAVE_32
)
368 device
->cs_wave_size
= 32;
370 /* For pixel shaders, wave64 is recommanded. */
371 if (device
->instance
->perftest_flags
& RADV_PERFTEST_PS_WAVE_32
)
372 device
->ps_wave_size
= 32;
374 if (device
->instance
->perftest_flags
& RADV_PERFTEST_GE_WAVE_32
)
375 device
->ge_wave_size
= 32;
378 radv_physical_device_init_mem_types(device
);
379 radv_fill_device_extension_table(device
, &device
->supported_extensions
);
381 device
->bus_info
= *drm_device
->businfo
.pci
;
383 if ((device
->instance
->debug_flags
& RADV_DEBUG_INFO
))
384 ac_print_gpu_info(&device
->rad_info
);
386 /* The WSI is structured as a layer on top of the driver, so this has
387 * to be the last part of initialization (at least until we get other
390 result
= radv_init_wsi(device
);
391 if (result
!= VK_SUCCESS
) {
392 device
->ws
->destroy(device
->ws
);
393 vk_error(instance
, result
);
407 radv_physical_device_finish(struct radv_physical_device
*device
)
409 radv_finish_wsi(device
);
410 device
->ws
->destroy(device
->ws
);
411 disk_cache_destroy(device
->disk_cache
);
412 close(device
->local_fd
);
413 if (device
->master_fd
!= -1)
414 close(device
->master_fd
);
418 default_alloc_func(void *pUserData
, size_t size
, size_t align
,
419 VkSystemAllocationScope allocationScope
)
425 default_realloc_func(void *pUserData
, void *pOriginal
, size_t size
,
426 size_t align
, VkSystemAllocationScope allocationScope
)
428 return realloc(pOriginal
, size
);
432 default_free_func(void *pUserData
, void *pMemory
)
437 static const VkAllocationCallbacks default_alloc
= {
439 .pfnAllocation
= default_alloc_func
,
440 .pfnReallocation
= default_realloc_func
,
441 .pfnFree
= default_free_func
,
444 static const struct debug_control radv_debug_options
[] = {
445 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS
},
446 {"nodcc", RADV_DEBUG_NO_DCC
},
447 {"shaders", RADV_DEBUG_DUMP_SHADERS
},
448 {"nocache", RADV_DEBUG_NO_CACHE
},
449 {"nomemorycache", RADV_DEBUG_NO_MEMORY_CACHE
},
450 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS
},
451 {"nohiz", RADV_DEBUG_NO_HIZ
},
452 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE
},
453 {"unsafemath", RADV_DEBUG_UNSAFE_MATH
},
454 {"allbos", RADV_DEBUG_ALL_BOS
},
455 {"noibs", RADV_DEBUG_NO_IBS
},
456 {"spirv", RADV_DEBUG_DUMP_SPIRV
},
457 {"vmfaults", RADV_DEBUG_VM_FAULTS
},
458 {"zerovram", RADV_DEBUG_ZERO_VRAM
},
459 {"syncshaders", RADV_DEBUG_SYNC_SHADERS
},
460 {"nosisched", RADV_DEBUG_NO_SISCHED
},
461 {"preoptir", RADV_DEBUG_PREOPTIR
},
462 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS
},
463 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER
},
464 {"info", RADV_DEBUG_INFO
},
465 {"errors", RADV_DEBUG_ERRORS
},
466 {"startup", RADV_DEBUG_STARTUP
},
467 {"checkir", RADV_DEBUG_CHECKIR
},
468 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM
},
469 {"nobinning", RADV_DEBUG_NOBINNING
},
470 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT
},
471 {"nongg", RADV_DEBUG_NO_NGG
},
472 {"noshaderballot", RADV_DEBUG_NO_SHADER_BALLOT
},
473 {"allentrypoints", RADV_DEBUG_ALL_ENTRYPOINTS
},
474 {"metashaders", RADV_DEBUG_DUMP_META_SHADERS
},
479 radv_get_debug_option_name(int id
)
481 assert(id
< ARRAY_SIZE(radv_debug_options
) - 1);
482 return radv_debug_options
[id
].string
;
485 static const struct debug_control radv_perftest_options
[] = {
486 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN
},
487 {"sisched", RADV_PERFTEST_SISCHED
},
488 {"localbos", RADV_PERFTEST_LOCAL_BOS
},
489 {"dccmsaa", RADV_PERFTEST_DCC_MSAA
},
490 {"bolist", RADV_PERFTEST_BO_LIST
},
491 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT
},
492 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK
},
493 {"cswave32", RADV_PERFTEST_CS_WAVE_32
},
494 {"pswave32", RADV_PERFTEST_PS_WAVE_32
},
495 {"gewave32", RADV_PERFTEST_GE_WAVE_32
},
496 {"dfsm", RADV_PERFTEST_DFSM
},
497 {"aco", RADV_PERFTEST_ACO
},
502 radv_get_perftest_option_name(int id
)
504 assert(id
< ARRAY_SIZE(radv_perftest_options
) - 1);
505 return radv_perftest_options
[id
].string
;
509 radv_handle_per_app_options(struct radv_instance
*instance
,
510 const VkApplicationInfo
*info
)
512 const char *name
= info
? info
->pApplicationName
: NULL
;
517 if (!strcmp(name
, "Talos - Linux - 32bit") ||
518 !strcmp(name
, "Talos - Linux - 64bit")) {
519 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SISCHED
)) {
520 /* Force enable LLVM sisched for Talos because it looks
521 * safe and it gives few more FPS.
523 instance
->perftest_flags
|= RADV_PERFTEST_SISCHED
;
525 } else if (!strcmp(name
, "DOOM_VFR")) {
526 /* Work around a Doom VFR game bug */
527 instance
->debug_flags
|= RADV_DEBUG_NO_DYNAMIC_BOUNDS
;
528 } else if (!strcmp(name
, "MonsterHunterWorld.exe")) {
529 /* Workaround for a WaW hazard when LLVM moves/merges
530 * load/store memory operations.
531 * See https://reviews.llvm.org/D61313
533 if (LLVM_VERSION_MAJOR
< 9)
534 instance
->debug_flags
|= RADV_DEBUG_NO_LOAD_STORE_OPT
;
535 } else if (!strcmp(name
, "Wolfenstein: Youngblood")) {
536 if (!(instance
->debug_flags
& RADV_DEBUG_NO_SHADER_BALLOT
)) {
537 /* Force enable VK_AMD_shader_ballot because it looks
538 * safe and it gives a nice boost (+20% on Vega 56 at
541 instance
->perftest_flags
|= RADV_PERFTEST_SHADER_BALLOT
;
543 } else if (!strcmp(name
, "Fledge")) {
545 * Zero VRAM for "The Surge 2"
547 * This avoid a hang when when rendering any level. Likely
548 * uninitialized data in an indirect draw.
550 instance
->debug_flags
|= RADV_DEBUG_ZERO_VRAM
;
554 static int radv_get_instance_extension_index(const char *name
)
556 for (unsigned i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; ++i
) {
557 if (strcmp(name
, radv_instance_extensions
[i
].extensionName
) == 0)
563 static const char radv_dri_options_xml
[] =
565 DRI_CONF_SECTION_PERFORMANCE
566 DRI_CONF_ADAPTIVE_SYNC("true")
567 DRI_CONF_VK_X11_OVERRIDE_MIN_IMAGE_COUNT(0)
568 DRI_CONF_VK_X11_STRICT_IMAGE_COUNT("false")
572 static void radv_init_dri_options(struct radv_instance
*instance
)
574 driParseOptionInfo(&instance
->available_dri_options
, radv_dri_options_xml
);
575 driParseConfigFiles(&instance
->dri_options
,
576 &instance
->available_dri_options
,
578 instance
->engineName
,
579 instance
->engineVersion
);
582 VkResult
radv_CreateInstance(
583 const VkInstanceCreateInfo
* pCreateInfo
,
584 const VkAllocationCallbacks
* pAllocator
,
585 VkInstance
* pInstance
)
587 struct radv_instance
*instance
;
590 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO
);
592 uint32_t client_version
;
593 if (pCreateInfo
->pApplicationInfo
&&
594 pCreateInfo
->pApplicationInfo
->apiVersion
!= 0) {
595 client_version
= pCreateInfo
->pApplicationInfo
->apiVersion
;
597 client_version
= VK_API_VERSION_1_0
;
600 const char *engine_name
= NULL
;
601 uint32_t engine_version
= 0;
602 if (pCreateInfo
->pApplicationInfo
) {
603 engine_name
= pCreateInfo
->pApplicationInfo
->pEngineName
;
604 engine_version
= pCreateInfo
->pApplicationInfo
->engineVersion
;
607 instance
= vk_zalloc2(&default_alloc
, pAllocator
, sizeof(*instance
), 8,
608 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
610 return vk_error(NULL
, VK_ERROR_OUT_OF_HOST_MEMORY
);
612 instance
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
615 instance
->alloc
= *pAllocator
;
617 instance
->alloc
= default_alloc
;
619 instance
->apiVersion
= client_version
;
620 instance
->physicalDeviceCount
= -1;
622 /* Get secure compile thread count. NOTE: We cap this at 32 */
623 #define MAX_SC_PROCS 32
624 char *num_sc_threads
= getenv("RADV_SECURE_COMPILE_THREADS");
626 instance
->num_sc_threads
= MIN2(strtoul(num_sc_threads
, NULL
, 10), MAX_SC_PROCS
);
628 instance
->debug_flags
= parse_debug_string(getenv("RADV_DEBUG"),
631 /* Disable memory cache when secure compile is set */
632 if (radv_device_use_secure_compile(instance
))
633 instance
->debug_flags
|= RADV_DEBUG_NO_MEMORY_CACHE
;
635 instance
->perftest_flags
= parse_debug_string(getenv("RADV_PERFTEST"),
636 radv_perftest_options
);
638 if (instance
->perftest_flags
& RADV_PERFTEST_ACO
)
639 fprintf(stderr
, "WARNING: Experimental compiler backend enabled. Here be dragons! Incorrect rendering, GPU hangs and/or resets are likely\n");
641 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
642 radv_logi("Created an instance");
644 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
645 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
646 int index
= radv_get_instance_extension_index(ext_name
);
648 if (index
< 0 || !radv_supported_instance_extensions
.extensions
[index
]) {
649 vk_free2(&default_alloc
, pAllocator
, instance
);
650 return vk_error(instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
653 instance
->enabled_extensions
.extensions
[index
] = true;
656 result
= vk_debug_report_instance_init(&instance
->debug_report_callbacks
);
657 if (result
!= VK_SUCCESS
) {
658 vk_free2(&default_alloc
, pAllocator
, instance
);
659 return vk_error(instance
, result
);
662 instance
->engineName
= vk_strdup(&instance
->alloc
, engine_name
,
663 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE
);
664 instance
->engineVersion
= engine_version
;
667 glsl_type_singleton_init_or_ref();
669 VG(VALGRIND_CREATE_MEMPOOL(instance
, 0, false));
671 radv_init_dri_options(instance
);
672 radv_handle_per_app_options(instance
, pCreateInfo
->pApplicationInfo
);
674 *pInstance
= radv_instance_to_handle(instance
);
679 void radv_DestroyInstance(
680 VkInstance _instance
,
681 const VkAllocationCallbacks
* pAllocator
)
683 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
688 for (int i
= 0; i
< instance
->physicalDeviceCount
; ++i
) {
689 radv_physical_device_finish(instance
->physicalDevices
+ i
);
692 vk_free(&instance
->alloc
, instance
->engineName
);
694 VG(VALGRIND_DESTROY_MEMPOOL(instance
));
696 glsl_type_singleton_decref();
699 driDestroyOptionCache(&instance
->dri_options
);
700 driDestroyOptionInfo(&instance
->available_dri_options
);
702 vk_debug_report_instance_destroy(&instance
->debug_report_callbacks
);
704 vk_free(&instance
->alloc
, instance
);
708 radv_enumerate_devices(struct radv_instance
*instance
)
710 /* TODO: Check for more devices ? */
711 drmDevicePtr devices
[8];
712 VkResult result
= VK_ERROR_INCOMPATIBLE_DRIVER
;
715 instance
->physicalDeviceCount
= 0;
717 max_devices
= drmGetDevices2(0, devices
, ARRAY_SIZE(devices
));
719 if (instance
->debug_flags
& RADV_DEBUG_STARTUP
)
720 radv_logi("Found %d drm nodes", max_devices
);
723 return vk_error(instance
, VK_ERROR_INCOMPATIBLE_DRIVER
);
725 for (unsigned i
= 0; i
< (unsigned)max_devices
; i
++) {
726 if (devices
[i
]->available_nodes
& 1 << DRM_NODE_RENDER
&&
727 devices
[i
]->bustype
== DRM_BUS_PCI
&&
728 devices
[i
]->deviceinfo
.pci
->vendor_id
== ATI_VENDOR_ID
) {
730 result
= radv_physical_device_init(instance
->physicalDevices
+
731 instance
->physicalDeviceCount
,
734 if (result
== VK_SUCCESS
)
735 ++instance
->physicalDeviceCount
;
736 else if (result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
740 drmFreeDevices(devices
, max_devices
);
745 VkResult
radv_EnumeratePhysicalDevices(
746 VkInstance _instance
,
747 uint32_t* pPhysicalDeviceCount
,
748 VkPhysicalDevice
* pPhysicalDevices
)
750 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
753 if (instance
->physicalDeviceCount
< 0) {
754 result
= radv_enumerate_devices(instance
);
755 if (result
!= VK_SUCCESS
&&
756 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
760 if (!pPhysicalDevices
) {
761 *pPhysicalDeviceCount
= instance
->physicalDeviceCount
;
763 *pPhysicalDeviceCount
= MIN2(*pPhysicalDeviceCount
, instance
->physicalDeviceCount
);
764 for (unsigned i
= 0; i
< *pPhysicalDeviceCount
; ++i
)
765 pPhysicalDevices
[i
] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
768 return *pPhysicalDeviceCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
772 VkResult
radv_EnumeratePhysicalDeviceGroups(
773 VkInstance _instance
,
774 uint32_t* pPhysicalDeviceGroupCount
,
775 VkPhysicalDeviceGroupProperties
* pPhysicalDeviceGroupProperties
)
777 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
780 if (instance
->physicalDeviceCount
< 0) {
781 result
= radv_enumerate_devices(instance
);
782 if (result
!= VK_SUCCESS
&&
783 result
!= VK_ERROR_INCOMPATIBLE_DRIVER
)
787 if (!pPhysicalDeviceGroupProperties
) {
788 *pPhysicalDeviceGroupCount
= instance
->physicalDeviceCount
;
790 *pPhysicalDeviceGroupCount
= MIN2(*pPhysicalDeviceGroupCount
, instance
->physicalDeviceCount
);
791 for (unsigned i
= 0; i
< *pPhysicalDeviceGroupCount
; ++i
) {
792 pPhysicalDeviceGroupProperties
[i
].physicalDeviceCount
= 1;
793 pPhysicalDeviceGroupProperties
[i
].physicalDevices
[0] = radv_physical_device_to_handle(instance
->physicalDevices
+ i
);
794 pPhysicalDeviceGroupProperties
[i
].subsetAllocation
= false;
797 return *pPhysicalDeviceGroupCount
< instance
->physicalDeviceCount
? VK_INCOMPLETE
801 void radv_GetPhysicalDeviceFeatures(
802 VkPhysicalDevice physicalDevice
,
803 VkPhysicalDeviceFeatures
* pFeatures
)
805 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
806 memset(pFeatures
, 0, sizeof(*pFeatures
));
808 *pFeatures
= (VkPhysicalDeviceFeatures
) {
809 .robustBufferAccess
= true,
810 .fullDrawIndexUint32
= true,
811 .imageCubeArray
= true,
812 .independentBlend
= true,
813 .geometryShader
= true,
814 .tessellationShader
= true,
815 .sampleRateShading
= true,
816 .dualSrcBlend
= true,
818 .multiDrawIndirect
= true,
819 .drawIndirectFirstInstance
= true,
821 .depthBiasClamp
= true,
822 .fillModeNonSolid
= true,
827 .multiViewport
= true,
828 .samplerAnisotropy
= true,
829 .textureCompressionETC2
= radv_device_supports_etc(pdevice
),
830 .textureCompressionASTC_LDR
= false,
831 .textureCompressionBC
= true,
832 .occlusionQueryPrecise
= true,
833 .pipelineStatisticsQuery
= true,
834 .vertexPipelineStoresAndAtomics
= true,
835 .fragmentStoresAndAtomics
= true,
836 .shaderTessellationAndGeometryPointSize
= true,
837 .shaderImageGatherExtended
= true,
838 .shaderStorageImageExtendedFormats
= true,
839 .shaderStorageImageMultisample
= pdevice
->rad_info
.chip_class
>= GFX8
,
840 .shaderUniformBufferArrayDynamicIndexing
= true,
841 .shaderSampledImageArrayDynamicIndexing
= true,
842 .shaderStorageBufferArrayDynamicIndexing
= true,
843 .shaderStorageImageArrayDynamicIndexing
= true,
844 .shaderStorageImageReadWithoutFormat
= true,
845 .shaderStorageImageWriteWithoutFormat
= true,
846 .shaderClipDistance
= true,
847 .shaderCullDistance
= true,
848 .shaderFloat64
= true,
850 .shaderInt16
= pdevice
->rad_info
.chip_class
>= GFX9
&& !pdevice
->use_aco
,
851 .sparseBinding
= true,
852 .variableMultisampleRate
= true,
853 .inheritedQueries
= true,
857 void radv_GetPhysicalDeviceFeatures2(
858 VkPhysicalDevice physicalDevice
,
859 VkPhysicalDeviceFeatures2
*pFeatures
)
861 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
862 vk_foreach_struct(ext
, pFeatures
->pNext
) {
863 switch (ext
->sType
) {
864 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES
: {
865 VkPhysicalDeviceVariablePointersFeatures
*features
= (void *)ext
;
866 features
->variablePointersStorageBuffer
= true;
867 features
->variablePointers
= true;
870 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES
: {
871 VkPhysicalDeviceMultiviewFeatures
*features
= (VkPhysicalDeviceMultiviewFeatures
*)ext
;
872 features
->multiview
= true;
873 features
->multiviewGeometryShader
= true;
874 features
->multiviewTessellationShader
= true;
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES
: {
878 VkPhysicalDeviceShaderDrawParametersFeatures
*features
=
879 (VkPhysicalDeviceShaderDrawParametersFeatures
*)ext
;
880 features
->shaderDrawParameters
= true;
883 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES
: {
884 VkPhysicalDeviceProtectedMemoryFeatures
*features
=
885 (VkPhysicalDeviceProtectedMemoryFeatures
*)ext
;
886 features
->protectedMemory
= false;
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES
: {
890 VkPhysicalDevice16BitStorageFeatures
*features
=
891 (VkPhysicalDevice16BitStorageFeatures
*)ext
;
892 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
893 features
->storageBuffer16BitAccess
= enabled
;
894 features
->uniformAndStorageBuffer16BitAccess
= enabled
;
895 features
->storagePushConstant16
= enabled
;
896 features
->storageInputOutput16
= enabled
&& LLVM_VERSION_MAJOR
>= 9;
899 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES
: {
900 VkPhysicalDeviceSamplerYcbcrConversionFeatures
*features
=
901 (VkPhysicalDeviceSamplerYcbcrConversionFeatures
*)ext
;
902 features
->samplerYcbcrConversion
= true;
905 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT
: {
906 VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*features
=
907 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT
*)ext
;
908 features
->shaderInputAttachmentArrayDynamicIndexing
= true;
909 features
->shaderUniformTexelBufferArrayDynamicIndexing
= true;
910 features
->shaderStorageTexelBufferArrayDynamicIndexing
= true;
911 features
->shaderUniformBufferArrayNonUniformIndexing
= true;
912 features
->shaderSampledImageArrayNonUniformIndexing
= true;
913 features
->shaderStorageBufferArrayNonUniformIndexing
= true;
914 features
->shaderStorageImageArrayNonUniformIndexing
= true;
915 features
->shaderInputAttachmentArrayNonUniformIndexing
= true;
916 features
->shaderUniformTexelBufferArrayNonUniformIndexing
= true;
917 features
->shaderStorageTexelBufferArrayNonUniformIndexing
= true;
918 features
->descriptorBindingUniformBufferUpdateAfterBind
= true;
919 features
->descriptorBindingSampledImageUpdateAfterBind
= true;
920 features
->descriptorBindingStorageImageUpdateAfterBind
= true;
921 features
->descriptorBindingStorageBufferUpdateAfterBind
= true;
922 features
->descriptorBindingUniformTexelBufferUpdateAfterBind
= true;
923 features
->descriptorBindingStorageTexelBufferUpdateAfterBind
= true;
924 features
->descriptorBindingUpdateUnusedWhilePending
= true;
925 features
->descriptorBindingPartiallyBound
= true;
926 features
->descriptorBindingVariableDescriptorCount
= true;
927 features
->runtimeDescriptorArray
= true;
930 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT
: {
931 VkPhysicalDeviceConditionalRenderingFeaturesEXT
*features
=
932 (VkPhysicalDeviceConditionalRenderingFeaturesEXT
*)ext
;
933 features
->conditionalRendering
= true;
934 features
->inheritedConditionalRendering
= false;
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT
: {
938 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*features
=
939 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT
*)ext
;
940 features
->vertexAttributeInstanceRateDivisor
= VK_TRUE
;
941 features
->vertexAttributeInstanceRateZeroDivisor
= VK_TRUE
;
944 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT
: {
945 VkPhysicalDeviceTransformFeedbackFeaturesEXT
*features
=
946 (VkPhysicalDeviceTransformFeedbackFeaturesEXT
*)ext
;
947 features
->transformFeedback
= true;
948 features
->geometryStreams
= !pdevice
->use_ngg_streamout
;
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT
: {
952 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*features
=
953 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT
*)ext
;
954 features
->scalarBlockLayout
= pdevice
->rad_info
.chip_class
>= GFX7
;
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT
: {
958 VkPhysicalDeviceMemoryPriorityFeaturesEXT
*features
=
959 (VkPhysicalDeviceMemoryPriorityFeaturesEXT
*)ext
;
960 features
->memoryPriority
= VK_TRUE
;
963 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT
: {
964 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*features
=
965 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT
*)ext
;
966 features
->bufferDeviceAddress
= true;
967 features
->bufferDeviceAddressCaptureReplay
= false;
968 features
->bufferDeviceAddressMultiDevice
= false;
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT
: {
972 VkPhysicalDeviceDepthClipEnableFeaturesEXT
*features
=
973 (VkPhysicalDeviceDepthClipEnableFeaturesEXT
*)ext
;
974 features
->depthClipEnable
= true;
977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT
: {
978 VkPhysicalDeviceHostQueryResetFeaturesEXT
*features
=
979 (VkPhysicalDeviceHostQueryResetFeaturesEXT
*)ext
;
980 features
->hostQueryReset
= true;
983 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR
: {
984 VkPhysicalDevice8BitStorageFeaturesKHR
*features
=
985 (VkPhysicalDevice8BitStorageFeaturesKHR
*)ext
;
986 bool enabled
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
987 features
->storageBuffer8BitAccess
= enabled
;
988 features
->uniformAndStorageBuffer8BitAccess
= enabled
;
989 features
->storagePushConstant8
= enabled
;
992 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_FLOAT16_INT8_FEATURES_KHR
: {
993 VkPhysicalDeviceShaderFloat16Int8FeaturesKHR
*features
=
994 (VkPhysicalDeviceShaderFloat16Int8FeaturesKHR
*)ext
;
995 features
->shaderFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
&& !pdevice
->use_aco
;
996 features
->shaderInt8
= !pdevice
->use_aco
;
999 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR
: {
1000 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*features
=
1001 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR
*)ext
;
1002 features
->shaderBufferInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1003 features
->shaderSharedInt64Atomics
= LLVM_VERSION_MAJOR
>= 9;
1006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DEMOTE_TO_HELPER_INVOCATION_FEATURES_EXT
: {
1007 VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*features
=
1008 (VkPhysicalDeviceShaderDemoteToHelperInvocationFeaturesEXT
*)ext
;
1009 features
->shaderDemoteToHelperInvocation
= pdevice
->use_aco
;
1012 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT
: {
1013 VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*features
=
1014 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT
*)ext
;
1016 features
->inlineUniformBlock
= true;
1017 features
->descriptorBindingInlineUniformBlockUpdateAfterBind
= true;
1020 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV
: {
1021 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*features
=
1022 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV
*)ext
;
1023 features
->computeDerivativeGroupQuads
= false;
1024 features
->computeDerivativeGroupLinear
= true;
1027 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT
: {
1028 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*features
=
1029 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT
*)ext
;
1030 features
->ycbcrImageArrays
= true;
1033 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR
: {
1034 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*features
=
1035 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR
*)ext
;
1036 features
->uniformBufferStandardLayout
= true;
1039 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT
: {
1040 VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*features
=
1041 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT
*)ext
;
1042 features
->indexTypeUint8
= pdevice
->rad_info
.chip_class
>= GFX8
;
1045 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_IMAGELESS_FRAMEBUFFER_FEATURES_KHR
: {
1046 VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*features
=
1047 (VkPhysicalDeviceImagelessFramebufferFeaturesKHR
*)ext
;
1048 features
->imagelessFramebuffer
= true;
1051 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PIPELINE_EXECUTABLE_PROPERTIES_FEATURES_KHR
: {
1052 VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*features
=
1053 (VkPhysicalDevicePipelineExecutablePropertiesFeaturesKHR
*)ext
;
1054 features
->pipelineExecutableInfo
= true;
1057 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CLOCK_FEATURES_KHR
: {
1058 VkPhysicalDeviceShaderClockFeaturesKHR
*features
=
1059 (VkPhysicalDeviceShaderClockFeaturesKHR
*)ext
;
1060 features
->shaderSubgroupClock
= true;
1061 features
->shaderDeviceClock
= false;
1064 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_FEATURES_EXT
: {
1065 VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*features
=
1066 (VkPhysicalDeviceTexelBufferAlignmentFeaturesEXT
*)ext
;
1067 features
->texelBufferAlignment
= true;
1074 return radv_GetPhysicalDeviceFeatures(physicalDevice
, &pFeatures
->features
);
1077 void radv_GetPhysicalDeviceProperties(
1078 VkPhysicalDevice physicalDevice
,
1079 VkPhysicalDeviceProperties
* pProperties
)
1081 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1082 VkSampleCountFlags sample_counts
= 0xf;
1084 /* make sure that the entire descriptor set is addressable with a signed
1085 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1086 * be at most 2 GiB. the combined image & samples object count as one of
1087 * both. This limit is for the pipeline layout, not for the set layout, but
1088 * there is no set limit, so we just set a pipeline limit. I don't think
1089 * any app is going to hit this soon. */
1090 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
) /
1091 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1092 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1093 32 /* sampler, largest when combined with image */ +
1094 64 /* sampled image */ +
1095 64 /* storage image */);
1097 VkPhysicalDeviceLimits limits
= {
1098 .maxImageDimension1D
= (1 << 14),
1099 .maxImageDimension2D
= (1 << 14),
1100 .maxImageDimension3D
= (1 << 11),
1101 .maxImageDimensionCube
= (1 << 14),
1102 .maxImageArrayLayers
= (1 << 11),
1103 .maxTexelBufferElements
= 128 * 1024 * 1024,
1104 .maxUniformBufferRange
= UINT32_MAX
,
1105 .maxStorageBufferRange
= UINT32_MAX
,
1106 .maxPushConstantsSize
= MAX_PUSH_CONSTANTS_SIZE
,
1107 .maxMemoryAllocationCount
= UINT32_MAX
,
1108 .maxSamplerAllocationCount
= 64 * 1024,
1109 .bufferImageGranularity
= 64, /* A cache line */
1110 .sparseAddressSpaceSize
= 0xffffffffu
, /* buffer max size */
1111 .maxBoundDescriptorSets
= MAX_SETS
,
1112 .maxPerStageDescriptorSamplers
= max_descriptor_set_size
,
1113 .maxPerStageDescriptorUniformBuffers
= max_descriptor_set_size
,
1114 .maxPerStageDescriptorStorageBuffers
= max_descriptor_set_size
,
1115 .maxPerStageDescriptorSampledImages
= max_descriptor_set_size
,
1116 .maxPerStageDescriptorStorageImages
= max_descriptor_set_size
,
1117 .maxPerStageDescriptorInputAttachments
= max_descriptor_set_size
,
1118 .maxPerStageResources
= max_descriptor_set_size
,
1119 .maxDescriptorSetSamplers
= max_descriptor_set_size
,
1120 .maxDescriptorSetUniformBuffers
= max_descriptor_set_size
,
1121 .maxDescriptorSetUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
,
1122 .maxDescriptorSetStorageBuffers
= max_descriptor_set_size
,
1123 .maxDescriptorSetStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
,
1124 .maxDescriptorSetSampledImages
= max_descriptor_set_size
,
1125 .maxDescriptorSetStorageImages
= max_descriptor_set_size
,
1126 .maxDescriptorSetInputAttachments
= max_descriptor_set_size
,
1127 .maxVertexInputAttributes
= MAX_VERTEX_ATTRIBS
,
1128 .maxVertexInputBindings
= MAX_VBS
,
1129 .maxVertexInputAttributeOffset
= 2047,
1130 .maxVertexInputBindingStride
= 2048,
1131 .maxVertexOutputComponents
= 128,
1132 .maxTessellationGenerationLevel
= 64,
1133 .maxTessellationPatchSize
= 32,
1134 .maxTessellationControlPerVertexInputComponents
= 128,
1135 .maxTessellationControlPerVertexOutputComponents
= 128,
1136 .maxTessellationControlPerPatchOutputComponents
= 120,
1137 .maxTessellationControlTotalOutputComponents
= 4096,
1138 .maxTessellationEvaluationInputComponents
= 128,
1139 .maxTessellationEvaluationOutputComponents
= 128,
1140 .maxGeometryShaderInvocations
= 127,
1141 .maxGeometryInputComponents
= 64,
1142 .maxGeometryOutputComponents
= 128,
1143 .maxGeometryOutputVertices
= 256,
1144 .maxGeometryTotalOutputComponents
= 1024,
1145 .maxFragmentInputComponents
= 128,
1146 .maxFragmentOutputAttachments
= 8,
1147 .maxFragmentDualSrcAttachments
= 1,
1148 .maxFragmentCombinedOutputResources
= 8,
1149 .maxComputeSharedMemorySize
= 32768,
1150 .maxComputeWorkGroupCount
= { 65535, 65535, 65535 },
1151 .maxComputeWorkGroupInvocations
= 2048,
1152 .maxComputeWorkGroupSize
= {
1157 .subPixelPrecisionBits
= 8,
1158 .subTexelPrecisionBits
= 8,
1159 .mipmapPrecisionBits
= 8,
1160 .maxDrawIndexedIndexValue
= UINT32_MAX
,
1161 .maxDrawIndirectCount
= UINT32_MAX
,
1162 .maxSamplerLodBias
= 16,
1163 .maxSamplerAnisotropy
= 16,
1164 .maxViewports
= MAX_VIEWPORTS
,
1165 .maxViewportDimensions
= { (1 << 14), (1 << 14) },
1166 .viewportBoundsRange
= { INT16_MIN
, INT16_MAX
},
1167 .viewportSubPixelBits
= 8,
1168 .minMemoryMapAlignment
= 4096, /* A page */
1169 .minTexelBufferOffsetAlignment
= 4,
1170 .minUniformBufferOffsetAlignment
= 4,
1171 .minStorageBufferOffsetAlignment
= 4,
1172 .minTexelOffset
= -32,
1173 .maxTexelOffset
= 31,
1174 .minTexelGatherOffset
= -32,
1175 .maxTexelGatherOffset
= 31,
1176 .minInterpolationOffset
= -2,
1177 .maxInterpolationOffset
= 2,
1178 .subPixelInterpolationOffsetBits
= 8,
1179 .maxFramebufferWidth
= (1 << 14),
1180 .maxFramebufferHeight
= (1 << 14),
1181 .maxFramebufferLayers
= (1 << 10),
1182 .framebufferColorSampleCounts
= sample_counts
,
1183 .framebufferDepthSampleCounts
= sample_counts
,
1184 .framebufferStencilSampleCounts
= sample_counts
,
1185 .framebufferNoAttachmentsSampleCounts
= sample_counts
,
1186 .maxColorAttachments
= MAX_RTS
,
1187 .sampledImageColorSampleCounts
= sample_counts
,
1188 .sampledImageIntegerSampleCounts
= VK_SAMPLE_COUNT_1_BIT
,
1189 .sampledImageDepthSampleCounts
= sample_counts
,
1190 .sampledImageStencilSampleCounts
= sample_counts
,
1191 .storageImageSampleCounts
= pdevice
->rad_info
.chip_class
>= GFX8
? sample_counts
: VK_SAMPLE_COUNT_1_BIT
,
1192 .maxSampleMaskWords
= 1,
1193 .timestampComputeAndGraphics
= true,
1194 .timestampPeriod
= 1000000.0 / pdevice
->rad_info
.clock_crystal_freq
,
1195 .maxClipDistances
= 8,
1196 .maxCullDistances
= 8,
1197 .maxCombinedClipAndCullDistances
= 8,
1198 .discreteQueuePriorities
= 2,
1199 .pointSizeRange
= { 0.0, 8192.0 },
1200 .lineWidthRange
= { 0.0, 7.9921875 },
1201 .pointSizeGranularity
= (1.0 / 8.0),
1202 .lineWidthGranularity
= (1.0 / 128.0),
1203 .strictLines
= false, /* FINISHME */
1204 .standardSampleLocations
= true,
1205 .optimalBufferCopyOffsetAlignment
= 128,
1206 .optimalBufferCopyRowPitchAlignment
= 128,
1207 .nonCoherentAtomSize
= 64,
1210 *pProperties
= (VkPhysicalDeviceProperties
) {
1211 .apiVersion
= radv_physical_device_api_version(pdevice
),
1212 .driverVersion
= vk_get_driver_version(),
1213 .vendorID
= ATI_VENDOR_ID
,
1214 .deviceID
= pdevice
->rad_info
.pci_id
,
1215 .deviceType
= pdevice
->rad_info
.has_dedicated_vram
? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU
: VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU
,
1217 .sparseProperties
= {0},
1220 strcpy(pProperties
->deviceName
, pdevice
->name
);
1221 memcpy(pProperties
->pipelineCacheUUID
, pdevice
->cache_uuid
, VK_UUID_SIZE
);
1224 void radv_GetPhysicalDeviceProperties2(
1225 VkPhysicalDevice physicalDevice
,
1226 VkPhysicalDeviceProperties2
*pProperties
)
1228 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1229 radv_GetPhysicalDeviceProperties(physicalDevice
, &pProperties
->properties
);
1231 vk_foreach_struct(ext
, pProperties
->pNext
) {
1232 switch (ext
->sType
) {
1233 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR
: {
1234 VkPhysicalDevicePushDescriptorPropertiesKHR
*properties
=
1235 (VkPhysicalDevicePushDescriptorPropertiesKHR
*) ext
;
1236 properties
->maxPushDescriptors
= MAX_PUSH_DESCRIPTORS
;
1239 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES
: {
1240 VkPhysicalDeviceIDProperties
*properties
= (VkPhysicalDeviceIDProperties
*)ext
;
1241 memcpy(properties
->driverUUID
, pdevice
->driver_uuid
, VK_UUID_SIZE
);
1242 memcpy(properties
->deviceUUID
, pdevice
->device_uuid
, VK_UUID_SIZE
);
1243 properties
->deviceLUIDValid
= false;
1246 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES
: {
1247 VkPhysicalDeviceMultiviewProperties
*properties
= (VkPhysicalDeviceMultiviewProperties
*)ext
;
1248 properties
->maxMultiviewViewCount
= MAX_VIEWS
;
1249 properties
->maxMultiviewInstanceIndex
= INT_MAX
;
1252 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES
: {
1253 VkPhysicalDevicePointClippingProperties
*properties
=
1254 (VkPhysicalDevicePointClippingProperties
*)ext
;
1255 properties
->pointClippingBehavior
= VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES
;
1258 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT
: {
1259 VkPhysicalDeviceDiscardRectanglePropertiesEXT
*properties
=
1260 (VkPhysicalDeviceDiscardRectanglePropertiesEXT
*)ext
;
1261 properties
->maxDiscardRectangles
= MAX_DISCARD_RECTANGLES
;
1264 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT
: {
1265 VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*properties
=
1266 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT
*) ext
;
1267 properties
->minImportedHostPointerAlignment
= 4096;
1270 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES
: {
1271 VkPhysicalDeviceSubgroupProperties
*properties
=
1272 (VkPhysicalDeviceSubgroupProperties
*)ext
;
1273 properties
->subgroupSize
= 64;
1274 properties
->supportedStages
= VK_SHADER_STAGE_ALL
;
1275 properties
->supportedOperations
=
1276 VK_SUBGROUP_FEATURE_BASIC_BIT
|
1277 VK_SUBGROUP_FEATURE_BALLOT_BIT
|
1278 VK_SUBGROUP_FEATURE_QUAD_BIT
|
1279 VK_SUBGROUP_FEATURE_VOTE_BIT
;
1280 if (pdevice
->rad_info
.chip_class
>= GFX8
) {
1281 properties
->supportedOperations
|=
1282 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT
|
1283 VK_SUBGROUP_FEATURE_CLUSTERED_BIT
|
1284 VK_SUBGROUP_FEATURE_SHUFFLE_BIT
|
1285 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT
;
1287 properties
->quadOperationsInAllStages
= true;
1290 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES
: {
1291 VkPhysicalDeviceMaintenance3Properties
*properties
=
1292 (VkPhysicalDeviceMaintenance3Properties
*)ext
;
1293 /* Make sure everything is addressable by a signed 32-bit int, and
1294 * our largest descriptors are 96 bytes. */
1295 properties
->maxPerSetDescriptors
= (1ull << 31) / 96;
1296 /* Our buffer size fields allow only this much */
1297 properties
->maxMemoryAllocationSize
= 0xFFFFFFFFull
;
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT
: {
1301 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*properties
=
1302 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT
*)ext
;
1303 /* GFX6-8 only support single channel min/max filter. */
1304 properties
->filterMinmaxImageComponentMapping
= pdevice
->rad_info
.chip_class
>= GFX9
;
1305 properties
->filterMinmaxSingleComponentFormats
= true;
1308 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD
: {
1309 VkPhysicalDeviceShaderCorePropertiesAMD
*properties
=
1310 (VkPhysicalDeviceShaderCorePropertiesAMD
*)ext
;
1312 /* Shader engines. */
1313 properties
->shaderEngineCount
=
1314 pdevice
->rad_info
.max_se
;
1315 properties
->shaderArraysPerEngineCount
=
1316 pdevice
->rad_info
.max_sh_per_se
;
1317 properties
->computeUnitsPerShaderArray
=
1318 pdevice
->rad_info
.num_good_cu_per_sh
;
1319 properties
->simdPerComputeUnit
= 4;
1320 properties
->wavefrontsPerSimd
=
1321 pdevice
->rad_info
.family
== CHIP_TONGA
||
1322 pdevice
->rad_info
.family
== CHIP_ICELAND
||
1323 pdevice
->rad_info
.family
== CHIP_POLARIS10
||
1324 pdevice
->rad_info
.family
== CHIP_POLARIS11
||
1325 pdevice
->rad_info
.family
== CHIP_POLARIS12
||
1326 pdevice
->rad_info
.family
== CHIP_VEGAM
? 8 : 10;
1327 properties
->wavefrontSize
= 64;
1330 properties
->sgprsPerSimd
=
1331 pdevice
->rad_info
.num_physical_sgprs_per_simd
;
1332 properties
->minSgprAllocation
=
1333 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1334 properties
->maxSgprAllocation
=
1335 pdevice
->rad_info
.family
== CHIP_TONGA
||
1336 pdevice
->rad_info
.family
== CHIP_ICELAND
? 96 : 104;
1337 properties
->sgprAllocationGranularity
=
1338 pdevice
->rad_info
.chip_class
>= GFX8
? 16 : 8;
1341 properties
->vgprsPerSimd
= RADV_NUM_PHYSICAL_VGPRS
;
1342 properties
->minVgprAllocation
= 4;
1343 properties
->maxVgprAllocation
= 256;
1344 properties
->vgprAllocationGranularity
= 4;
1347 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_2_AMD
: {
1348 VkPhysicalDeviceShaderCoreProperties2AMD
*properties
=
1349 (VkPhysicalDeviceShaderCoreProperties2AMD
*)ext
;
1351 properties
->shaderCoreFeatures
= 0;
1352 properties
->activeComputeUnitCount
=
1353 pdevice
->rad_info
.num_good_compute_units
;
1356 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT
: {
1357 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*properties
=
1358 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT
*)ext
;
1359 properties
->maxVertexAttribDivisor
= UINT32_MAX
;
1362 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT
: {
1363 VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*properties
=
1364 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT
*)ext
;
1365 properties
->maxUpdateAfterBindDescriptorsInAllPools
= UINT32_MAX
/ 64;
1366 properties
->shaderUniformBufferArrayNonUniformIndexingNative
= false;
1367 properties
->shaderSampledImageArrayNonUniformIndexingNative
= false;
1368 properties
->shaderStorageBufferArrayNonUniformIndexingNative
= false;
1369 properties
->shaderStorageImageArrayNonUniformIndexingNative
= false;
1370 properties
->shaderInputAttachmentArrayNonUniformIndexingNative
= false;
1371 properties
->robustBufferAccessUpdateAfterBind
= false;
1372 properties
->quadDivergentImplicitLod
= false;
1374 size_t max_descriptor_set_size
= ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS
-
1375 MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_INLINE_UNIFORM_BLOCK_COUNT
) /
1376 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1377 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1378 32 /* sampler, largest when combined with image */ +
1379 64 /* sampled image */ +
1380 64 /* storage image */);
1381 properties
->maxPerStageDescriptorUpdateAfterBindSamplers
= max_descriptor_set_size
;
1382 properties
->maxPerStageDescriptorUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1383 properties
->maxPerStageDescriptorUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1384 properties
->maxPerStageDescriptorUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1385 properties
->maxPerStageDescriptorUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1386 properties
->maxPerStageDescriptorUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1387 properties
->maxPerStageUpdateAfterBindResources
= max_descriptor_set_size
;
1388 properties
->maxDescriptorSetUpdateAfterBindSamplers
= max_descriptor_set_size
;
1389 properties
->maxDescriptorSetUpdateAfterBindUniformBuffers
= max_descriptor_set_size
;
1390 properties
->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic
= MAX_DYNAMIC_UNIFORM_BUFFERS
;
1391 properties
->maxDescriptorSetUpdateAfterBindStorageBuffers
= max_descriptor_set_size
;
1392 properties
->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic
= MAX_DYNAMIC_STORAGE_BUFFERS
;
1393 properties
->maxDescriptorSetUpdateAfterBindSampledImages
= max_descriptor_set_size
;
1394 properties
->maxDescriptorSetUpdateAfterBindStorageImages
= max_descriptor_set_size
;
1395 properties
->maxDescriptorSetUpdateAfterBindInputAttachments
= max_descriptor_set_size
;
1398 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES
: {
1399 VkPhysicalDeviceProtectedMemoryProperties
*properties
=
1400 (VkPhysicalDeviceProtectedMemoryProperties
*)ext
;
1401 properties
->protectedNoFault
= false;
1404 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT
: {
1405 VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*properties
=
1406 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT
*)ext
;
1407 properties
->primitiveOverestimationSize
= 0;
1408 properties
->maxExtraPrimitiveOverestimationSize
= 0;
1409 properties
->extraPrimitiveOverestimationSizeGranularity
= 0;
1410 properties
->primitiveUnderestimation
= VK_FALSE
;
1411 properties
->conservativePointAndLineRasterization
= VK_FALSE
;
1412 properties
->degenerateTrianglesRasterized
= VK_FALSE
;
1413 properties
->degenerateLinesRasterized
= VK_FALSE
;
1414 properties
->fullyCoveredFragmentShaderInputVariable
= VK_FALSE
;
1415 properties
->conservativeRasterizationPostDepthCoverage
= VK_FALSE
;
1418 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT
: {
1419 VkPhysicalDevicePCIBusInfoPropertiesEXT
*properties
=
1420 (VkPhysicalDevicePCIBusInfoPropertiesEXT
*)ext
;
1421 properties
->pciDomain
= pdevice
->bus_info
.domain
;
1422 properties
->pciBus
= pdevice
->bus_info
.bus
;
1423 properties
->pciDevice
= pdevice
->bus_info
.dev
;
1424 properties
->pciFunction
= pdevice
->bus_info
.func
;
1427 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR
: {
1428 VkPhysicalDeviceDriverPropertiesKHR
*driver_props
=
1429 (VkPhysicalDeviceDriverPropertiesKHR
*) ext
;
1431 driver_props
->driverID
= VK_DRIVER_ID_MESA_RADV_KHR
;
1432 snprintf(driver_props
->driverName
, VK_MAX_DRIVER_NAME_SIZE_KHR
, "radv");
1433 snprintf(driver_props
->driverInfo
, VK_MAX_DRIVER_INFO_SIZE_KHR
,
1434 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1435 " (LLVM " MESA_LLVM_VERSION_STRING
")");
1437 driver_props
->conformanceVersion
= (VkConformanceVersionKHR
) {
1445 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT
: {
1446 VkPhysicalDeviceTransformFeedbackPropertiesEXT
*properties
=
1447 (VkPhysicalDeviceTransformFeedbackPropertiesEXT
*)ext
;
1448 properties
->maxTransformFeedbackStreams
= MAX_SO_STREAMS
;
1449 properties
->maxTransformFeedbackBuffers
= MAX_SO_BUFFERS
;
1450 properties
->maxTransformFeedbackBufferSize
= UINT32_MAX
;
1451 properties
->maxTransformFeedbackStreamDataSize
= 512;
1452 properties
->maxTransformFeedbackBufferDataSize
= UINT32_MAX
;
1453 properties
->maxTransformFeedbackBufferDataStride
= 512;
1454 properties
->transformFeedbackQueries
= !pdevice
->use_ngg_streamout
;
1455 properties
->transformFeedbackStreamsLinesTriangles
= !pdevice
->use_ngg_streamout
;
1456 properties
->transformFeedbackRasterizationStreamSelect
= false;
1457 properties
->transformFeedbackDraw
= true;
1460 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT
: {
1461 VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*props
=
1462 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT
*)ext
;
1464 props
->maxInlineUniformBlockSize
= MAX_INLINE_UNIFORM_BLOCK_SIZE
;
1465 props
->maxPerStageDescriptorInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1466 props
->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_SIZE
* MAX_SETS
;
1467 props
->maxDescriptorSetInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1468 props
->maxDescriptorSetUpdateAfterBindInlineUniformBlocks
= MAX_INLINE_UNIFORM_BLOCK_COUNT
;
1471 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT
: {
1472 VkPhysicalDeviceSampleLocationsPropertiesEXT
*properties
=
1473 (VkPhysicalDeviceSampleLocationsPropertiesEXT
*)ext
;
1474 properties
->sampleLocationSampleCounts
= VK_SAMPLE_COUNT_2_BIT
|
1475 VK_SAMPLE_COUNT_4_BIT
|
1476 VK_SAMPLE_COUNT_8_BIT
;
1477 properties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2 , 2 };
1478 properties
->sampleLocationCoordinateRange
[0] = 0.0f
;
1479 properties
->sampleLocationCoordinateRange
[1] = 0.9375f
;
1480 properties
->sampleLocationSubPixelBits
= 4;
1481 properties
->variableSampleLocations
= VK_FALSE
;
1484 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR
: {
1485 VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*properties
=
1486 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR
*)ext
;
1488 /* We support all of the depth resolve modes */
1489 properties
->supportedDepthResolveModes
=
1490 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1491 VK_RESOLVE_MODE_AVERAGE_BIT_KHR
|
1492 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1493 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1495 /* Average doesn't make sense for stencil so we don't support that */
1496 properties
->supportedStencilResolveModes
=
1497 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR
|
1498 VK_RESOLVE_MODE_MIN_BIT_KHR
|
1499 VK_RESOLVE_MODE_MAX_BIT_KHR
;
1501 properties
->independentResolveNone
= VK_TRUE
;
1502 properties
->independentResolve
= VK_TRUE
;
1505 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TEXEL_BUFFER_ALIGNMENT_PROPERTIES_EXT
: {
1506 VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*properties
=
1507 (VkPhysicalDeviceTexelBufferAlignmentPropertiesEXT
*)ext
;
1508 properties
->storageTexelBufferOffsetAlignmentBytes
= 4;
1509 properties
->storageTexelBufferOffsetSingleTexelAlignment
= true;
1510 properties
->uniformTexelBufferOffsetAlignmentBytes
= 4;
1511 properties
->uniformTexelBufferOffsetSingleTexelAlignment
= true;
1514 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT_CONTROLS_PROPERTIES_KHR
: {
1515 VkPhysicalDeviceFloatControlsPropertiesKHR
*properties
=
1516 (VkPhysicalDeviceFloatControlsPropertiesKHR
*)ext
;
1518 /* On AMD hardware, denormals and rounding modes for
1519 * fp16/fp64 are controlled by the same config
1522 properties
->denormBehaviorIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1523 properties
->roundingModeIndependence
= VK_SHADER_FLOAT_CONTROLS_INDEPENDENCE_32_BIT_ONLY_KHR
;
1525 /* Do not allow both preserving and flushing denorms
1526 * because different shaders in the same pipeline can
1527 * have different settings and this won't work for
1528 * merged shaders. To make it work, this requires LLVM
1529 * support for changing the register. The same logic
1530 * applies for the rounding modes because they are
1531 * configured with the same config register.
1533 properties
->shaderDenormFlushToZeroFloat32
= true;
1534 properties
->shaderDenormPreserveFloat32
= false;
1535 properties
->shaderRoundingModeRTEFloat32
= true;
1536 properties
->shaderRoundingModeRTZFloat32
= false;
1537 properties
->shaderSignedZeroInfNanPreserveFloat32
= true;
1539 properties
->shaderDenormFlushToZeroFloat16
= false;
1540 properties
->shaderDenormPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1541 properties
->shaderRoundingModeRTEFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1542 properties
->shaderRoundingModeRTZFloat16
= false;
1543 properties
->shaderSignedZeroInfNanPreserveFloat16
= pdevice
->rad_info
.chip_class
>= GFX8
;
1545 properties
->shaderDenormFlushToZeroFloat64
= false;
1546 properties
->shaderDenormPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1547 properties
->shaderRoundingModeRTEFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1548 properties
->shaderRoundingModeRTZFloat64
= false;
1549 properties
->shaderSignedZeroInfNanPreserveFloat64
= pdevice
->rad_info
.chip_class
>= GFX8
;
1558 static void radv_get_physical_device_queue_family_properties(
1559 struct radv_physical_device
* pdevice
,
1561 VkQueueFamilyProperties
** pQueueFamilyProperties
)
1563 int num_queue_families
= 1;
1565 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1566 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
))
1567 num_queue_families
++;
1569 if (pQueueFamilyProperties
== NULL
) {
1570 *pCount
= num_queue_families
;
1579 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1580 .queueFlags
= VK_QUEUE_GRAPHICS_BIT
|
1581 VK_QUEUE_COMPUTE_BIT
|
1582 VK_QUEUE_TRANSFER_BIT
|
1583 VK_QUEUE_SPARSE_BINDING_BIT
,
1585 .timestampValidBits
= 64,
1586 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1591 if (pdevice
->rad_info
.num_compute_rings
> 0 &&
1592 !(pdevice
->instance
->debug_flags
& RADV_DEBUG_NO_COMPUTE_QUEUE
)) {
1593 if (*pCount
> idx
) {
1594 *pQueueFamilyProperties
[idx
] = (VkQueueFamilyProperties
) {
1595 .queueFlags
= VK_QUEUE_COMPUTE_BIT
|
1596 VK_QUEUE_TRANSFER_BIT
|
1597 VK_QUEUE_SPARSE_BINDING_BIT
,
1598 .queueCount
= pdevice
->rad_info
.num_compute_rings
,
1599 .timestampValidBits
= 64,
1600 .minImageTransferGranularity
= (VkExtent3D
) { 1, 1, 1 },
1608 void radv_GetPhysicalDeviceQueueFamilyProperties(
1609 VkPhysicalDevice physicalDevice
,
1611 VkQueueFamilyProperties
* pQueueFamilyProperties
)
1613 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1614 if (!pQueueFamilyProperties
) {
1615 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1618 VkQueueFamilyProperties
*properties
[] = {
1619 pQueueFamilyProperties
+ 0,
1620 pQueueFamilyProperties
+ 1,
1621 pQueueFamilyProperties
+ 2,
1623 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1624 assert(*pCount
<= 3);
1627 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1628 VkPhysicalDevice physicalDevice
,
1630 VkQueueFamilyProperties2
*pQueueFamilyProperties
)
1632 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
1633 if (!pQueueFamilyProperties
) {
1634 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, NULL
);
1637 VkQueueFamilyProperties
*properties
[] = {
1638 &pQueueFamilyProperties
[0].queueFamilyProperties
,
1639 &pQueueFamilyProperties
[1].queueFamilyProperties
,
1640 &pQueueFamilyProperties
[2].queueFamilyProperties
,
1642 radv_get_physical_device_queue_family_properties(pdevice
, pCount
, properties
);
1643 assert(*pCount
<= 3);
1646 void radv_GetPhysicalDeviceMemoryProperties(
1647 VkPhysicalDevice physicalDevice
,
1648 VkPhysicalDeviceMemoryProperties
*pMemoryProperties
)
1650 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
1652 *pMemoryProperties
= physical_device
->memory_properties
;
1656 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice
,
1657 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memoryBudget
)
1659 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
1660 VkPhysicalDeviceMemoryProperties
*memory_properties
= &device
->memory_properties
;
1661 uint64_t visible_vram_size
= radv_get_visible_vram_size(device
);
1662 uint64_t vram_size
= radv_get_vram_size(device
);
1663 uint64_t gtt_size
= device
->rad_info
.gart_size
;
1664 uint64_t heap_budget
, heap_usage
;
1666 /* For all memory heaps, the computation of budget is as follow:
1667 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1669 * The Vulkan spec 1.1.97 says that the budget should include any
1670 * currently allocated device memory.
1672 * Note that the application heap usages are not really accurate (eg.
1673 * in presence of shared buffers).
1675 for (int i
= 0; i
< device
->memory_properties
.memoryTypeCount
; i
++) {
1676 uint32_t heap_index
= device
->memory_properties
.memoryTypes
[i
].heapIndex
;
1678 switch (device
->mem_type_indices
[i
]) {
1679 case RADV_MEM_TYPE_VRAM
:
1680 heap_usage
= device
->ws
->query_value(device
->ws
,
1681 RADEON_ALLOCATED_VRAM
);
1683 heap_budget
= vram_size
-
1684 device
->ws
->query_value(device
->ws
, RADEON_VRAM_USAGE
) +
1687 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1688 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1690 case RADV_MEM_TYPE_VRAM_CPU_ACCESS
:
1691 heap_usage
= device
->ws
->query_value(device
->ws
,
1692 RADEON_ALLOCATED_VRAM_VIS
);
1694 heap_budget
= visible_vram_size
-
1695 device
->ws
->query_value(device
->ws
, RADEON_VRAM_VIS_USAGE
) +
1698 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1699 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1701 case RADV_MEM_TYPE_GTT_WRITE_COMBINE
:
1702 heap_usage
= device
->ws
->query_value(device
->ws
,
1703 RADEON_ALLOCATED_GTT
);
1705 heap_budget
= gtt_size
-
1706 device
->ws
->query_value(device
->ws
, RADEON_GTT_USAGE
) +
1709 memoryBudget
->heapBudget
[heap_index
] = heap_budget
;
1710 memoryBudget
->heapUsage
[heap_index
] = heap_usage
;
1717 /* The heapBudget and heapUsage values must be zero for array elements
1718 * greater than or equal to
1719 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1721 for (uint32_t i
= memory_properties
->memoryHeapCount
; i
< VK_MAX_MEMORY_HEAPS
; i
++) {
1722 memoryBudget
->heapBudget
[i
] = 0;
1723 memoryBudget
->heapUsage
[i
] = 0;
1727 void radv_GetPhysicalDeviceMemoryProperties2(
1728 VkPhysicalDevice physicalDevice
,
1729 VkPhysicalDeviceMemoryProperties2
*pMemoryProperties
)
1731 radv_GetPhysicalDeviceMemoryProperties(physicalDevice
,
1732 &pMemoryProperties
->memoryProperties
);
1734 VkPhysicalDeviceMemoryBudgetPropertiesEXT
*memory_budget
=
1735 vk_find_struct(pMemoryProperties
->pNext
,
1736 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT
);
1738 radv_get_memory_budget_properties(physicalDevice
, memory_budget
);
1741 VkResult
radv_GetMemoryHostPointerPropertiesEXT(
1743 VkExternalMemoryHandleTypeFlagBits handleType
,
1744 const void *pHostPointer
,
1745 VkMemoryHostPointerPropertiesEXT
*pMemoryHostPointerProperties
)
1747 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1751 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
: {
1752 const struct radv_physical_device
*physical_device
= device
->physical_device
;
1753 uint32_t memoryTypeBits
= 0;
1754 for (int i
= 0; i
< physical_device
->memory_properties
.memoryTypeCount
; i
++) {
1755 if (physical_device
->mem_type_indices
[i
] == RADV_MEM_TYPE_GTT_CACHED
) {
1756 memoryTypeBits
= (1 << i
);
1760 pMemoryHostPointerProperties
->memoryTypeBits
= memoryTypeBits
;
1764 return VK_ERROR_INVALID_EXTERNAL_HANDLE
;
1768 static enum radeon_ctx_priority
1769 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT
*pObj
)
1771 /* Default to MEDIUM when a specific global priority isn't requested */
1773 return RADEON_CTX_PRIORITY_MEDIUM
;
1775 switch(pObj
->globalPriority
) {
1776 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT
:
1777 return RADEON_CTX_PRIORITY_REALTIME
;
1778 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT
:
1779 return RADEON_CTX_PRIORITY_HIGH
;
1780 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT
:
1781 return RADEON_CTX_PRIORITY_MEDIUM
;
1782 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT
:
1783 return RADEON_CTX_PRIORITY_LOW
;
1785 unreachable("Illegal global priority value");
1786 return RADEON_CTX_PRIORITY_INVALID
;
1791 radv_queue_init(struct radv_device
*device
, struct radv_queue
*queue
,
1792 uint32_t queue_family_index
, int idx
,
1793 VkDeviceQueueCreateFlags flags
,
1794 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
)
1796 queue
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1797 queue
->device
= device
;
1798 queue
->queue_family_index
= queue_family_index
;
1799 queue
->queue_idx
= idx
;
1800 queue
->priority
= radv_get_queue_global_priority(global_priority
);
1801 queue
->flags
= flags
;
1803 queue
->hw_ctx
= device
->ws
->ctx_create(device
->ws
, queue
->priority
);
1805 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1811 radv_queue_finish(struct radv_queue
*queue
)
1814 queue
->device
->ws
->ctx_destroy(queue
->hw_ctx
);
1816 if (queue
->initial_full_flush_preamble_cs
)
1817 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
1818 if (queue
->initial_preamble_cs
)
1819 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
1820 if (queue
->continue_preamble_cs
)
1821 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
1822 if (queue
->descriptor_bo
)
1823 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
1824 if (queue
->scratch_bo
)
1825 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
1826 if (queue
->esgs_ring_bo
)
1827 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
1828 if (queue
->gsvs_ring_bo
)
1829 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
1830 if (queue
->tess_rings_bo
)
1831 queue
->device
->ws
->buffer_destroy(queue
->tess_rings_bo
);
1833 queue
->device
->ws
->buffer_destroy(queue
->gds_bo
);
1834 if (queue
->gds_oa_bo
)
1835 queue
->device
->ws
->buffer_destroy(queue
->gds_oa_bo
);
1836 if (queue
->compute_scratch_bo
)
1837 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
1841 radv_bo_list_init(struct radv_bo_list
*bo_list
)
1843 pthread_mutex_init(&bo_list
->mutex
, NULL
);
1844 bo_list
->list
.count
= bo_list
->capacity
= 0;
1845 bo_list
->list
.bos
= NULL
;
1849 radv_bo_list_finish(struct radv_bo_list
*bo_list
)
1851 free(bo_list
->list
.bos
);
1852 pthread_mutex_destroy(&bo_list
->mutex
);
1855 static VkResult
radv_bo_list_add(struct radv_device
*device
,
1856 struct radeon_winsys_bo
*bo
)
1858 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1863 if (unlikely(!device
->use_global_bo_list
))
1866 pthread_mutex_lock(&bo_list
->mutex
);
1867 if (bo_list
->list
.count
== bo_list
->capacity
) {
1868 unsigned capacity
= MAX2(4, bo_list
->capacity
* 2);
1869 void *data
= realloc(bo_list
->list
.bos
, capacity
* sizeof(struct radeon_winsys_bo
*));
1872 pthread_mutex_unlock(&bo_list
->mutex
);
1873 return VK_ERROR_OUT_OF_HOST_MEMORY
;
1876 bo_list
->list
.bos
= (struct radeon_winsys_bo
**)data
;
1877 bo_list
->capacity
= capacity
;
1880 bo_list
->list
.bos
[bo_list
->list
.count
++] = bo
;
1881 pthread_mutex_unlock(&bo_list
->mutex
);
1885 static void radv_bo_list_remove(struct radv_device
*device
,
1886 struct radeon_winsys_bo
*bo
)
1888 struct radv_bo_list
*bo_list
= &device
->bo_list
;
1893 if (unlikely(!device
->use_global_bo_list
))
1896 pthread_mutex_lock(&bo_list
->mutex
);
1897 for(unsigned i
= 0; i
< bo_list
->list
.count
; ++i
) {
1898 if (bo_list
->list
.bos
[i
] == bo
) {
1899 bo_list
->list
.bos
[i
] = bo_list
->list
.bos
[bo_list
->list
.count
- 1];
1900 --bo_list
->list
.count
;
1904 pthread_mutex_unlock(&bo_list
->mutex
);
1908 radv_device_init_gs_info(struct radv_device
*device
)
1910 device
->gs_table_depth
= ac_get_gs_table_depth(device
->physical_device
->rad_info
.chip_class
,
1911 device
->physical_device
->rad_info
.family
);
1914 static int radv_get_device_extension_index(const char *name
)
1916 for (unsigned i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; ++i
) {
1917 if (strcmp(name
, radv_device_extensions
[i
].extensionName
) == 0)
1924 radv_get_int_debug_option(const char *name
, int default_value
)
1931 result
= default_value
;
1935 result
= strtol(str
, &endptr
, 0);
1936 if (str
== endptr
) {
1937 /* No digits founs. */
1938 result
= default_value
;
1945 static int install_seccomp_filter() {
1947 struct sock_filter filter
[] = {
1948 /* Check arch is 64bit x86 */
1949 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, arch
))),
1950 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, AUDIT_ARCH_X86_64
, 0, 12),
1952 /* Futex is required for mutex locks */
1953 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
1954 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_select
, 11, 0),
1956 /* Allow system exit calls for the forked process */
1957 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
1958 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_exit_group
, 9, 0),
1960 /* Allow system read calls */
1961 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
1962 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_read
, 7, 0),
1964 /* Allow system write calls */
1965 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
1966 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_write
, 5, 0),
1968 /* Allow system brk calls (we need this for malloc) */
1969 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
1970 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_brk
, 3, 0),
1972 /* Futex is required for mutex locks */
1973 BPF_STMT(BPF_LD
+ BPF_W
+ BPF_ABS
, (offsetof(struct seccomp_data
, nr
))),
1974 BPF_JUMP(BPF_JMP
+ BPF_JEQ
+ BPF_K
, __NR_futex
, 1, 0),
1976 /* Return error if we hit a system call not on the whitelist */
1977 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ERRNO
| (EPERM
& SECCOMP_RET_DATA
)),
1979 /* Allow whitelisted system calls */
1980 BPF_STMT(BPF_RET
+ BPF_K
, SECCOMP_RET_ALLOW
),
1983 struct sock_fprog prog
= {
1984 .len
= (unsigned short)(sizeof(filter
) / sizeof(filter
[0])),
1988 if (prctl(PR_SET_NO_NEW_PRIVS
, 1, 0, 0, 0))
1991 if (prctl(PR_SET_SECCOMP
, SECCOMP_MODE_FILTER
, &prog
))
1997 /* Helper function with timeout support for reading from the pipe between
1998 * processes used for secure compile.
2000 bool radv_sc_read(int fd
, void *buf
, size_t size
, bool timeout
)
2009 /* We can't rely on the value of tv after calling select() so
2010 * we must reset it on each iteration of the loop.
2015 int rval
= select(fd
+ 1, &fds
, NULL
, NULL
, timeout
? &tv
: NULL
);
2021 ssize_t bytes_read
= read(fd
, buf
, size
);
2030 /* select timeout */
2036 static void run_secure_compile_device(struct radv_device
*device
, unsigned process
,
2037 int *fd_secure_input
, int *fd_secure_output
)
2039 enum radv_secure_compile_type sc_type
;
2040 if (install_seccomp_filter() == -1) {
2041 sc_type
= RADV_SC_TYPE_INIT_FAILURE
;
2043 sc_type
= RADV_SC_TYPE_INIT_SUCCESS
;
2044 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[0];
2045 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[1];
2048 write(fd_secure_output
[1], &sc_type
, sizeof(sc_type
));
2050 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
)
2051 goto secure_compile_exit
;
2054 radv_sc_read(fd_secure_input
[0], &sc_type
, sizeof(sc_type
), false);
2056 if (sc_type
== RADV_SC_TYPE_COMPILE_PIPELINE
) {
2057 struct radv_pipeline
*pipeline
;
2058 bool sc_read
= true;
2060 pipeline
= vk_zalloc2(&device
->alloc
, NULL
, sizeof(*pipeline
), 8,
2061 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2063 pipeline
->device
= device
;
2065 /* Read pipeline layout */
2066 struct radv_pipeline_layout layout
;
2067 sc_read
= radv_sc_read(fd_secure_input
[0], &layout
, sizeof(struct radv_pipeline_layout
), true);
2068 sc_read
&= radv_sc_read(fd_secure_input
[0], &layout
.num_sets
, sizeof(uint32_t), true);
2070 goto secure_compile_exit
;
2072 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++) {
2073 uint32_t layout_size
;
2074 sc_read
&= radv_sc_read(fd_secure_input
[0], &layout_size
, sizeof(uint32_t), true);
2076 goto secure_compile_exit
;
2078 layout
.set
[set
].layout
= malloc(layout_size
);
2079 layout
.set
[set
].layout
->layout_size
= layout_size
;
2080 sc_read
&= radv_sc_read(fd_secure_input
[0], layout
.set
[set
].layout
,
2081 layout
.set
[set
].layout
->layout_size
, true);
2084 pipeline
->layout
= &layout
;
2086 /* Read pipeline key */
2087 struct radv_pipeline_key key
;
2088 sc_read
&= radv_sc_read(fd_secure_input
[0], &key
, sizeof(struct radv_pipeline_key
), true);
2090 /* Read pipeline create flags */
2091 VkPipelineCreateFlags flags
;
2092 sc_read
&= radv_sc_read(fd_secure_input
[0], &flags
, sizeof(VkPipelineCreateFlags
), true);
2094 /* Read stage and shader information */
2095 uint32_t num_stages
;
2096 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
2097 sc_read
&= radv_sc_read(fd_secure_input
[0], &num_stages
, sizeof(uint32_t), true);
2099 goto secure_compile_exit
;
2101 for (uint32_t i
= 0; i
< num_stages
; i
++) {
2104 gl_shader_stage stage
;
2105 sc_read
&= radv_sc_read(fd_secure_input
[0], &stage
, sizeof(gl_shader_stage
), true);
2107 VkPipelineShaderStageCreateInfo
*pStage
= calloc(1, sizeof(VkPipelineShaderStageCreateInfo
));
2109 /* Read entry point name */
2111 sc_read
&= radv_sc_read(fd_secure_input
[0], &name_size
, sizeof(size_t), true);
2113 goto secure_compile_exit
;
2115 char *ep_name
= malloc(name_size
);
2116 sc_read
&= radv_sc_read(fd_secure_input
[0], ep_name
, name_size
, true);
2117 pStage
->pName
= ep_name
;
2119 /* Read shader module */
2121 sc_read
&= radv_sc_read(fd_secure_input
[0], &module_size
, sizeof(size_t), true);
2123 goto secure_compile_exit
;
2125 struct radv_shader_module
*module
= malloc(module_size
);
2126 sc_read
&= radv_sc_read(fd_secure_input
[0], module
, module_size
, true);
2127 pStage
->module
= radv_shader_module_to_handle(module
);
2129 /* Read specialization info */
2131 sc_read
&= radv_sc_read(fd_secure_input
[0], &has_spec_info
, sizeof(bool), true);
2133 goto secure_compile_exit
;
2135 if (has_spec_info
) {
2136 VkSpecializationInfo
*specInfo
= malloc(sizeof(VkSpecializationInfo
));
2137 pStage
->pSpecializationInfo
= specInfo
;
2139 sc_read
&= radv_sc_read(fd_secure_input
[0], &specInfo
->dataSize
, sizeof(size_t), true);
2141 goto secure_compile_exit
;
2143 void *si_data
= malloc(specInfo
->dataSize
);
2144 sc_read
&= radv_sc_read(fd_secure_input
[0], si_data
, specInfo
->dataSize
, true);
2145 specInfo
->pData
= si_data
;
2147 sc_read
&= radv_sc_read(fd_secure_input
[0], &specInfo
->mapEntryCount
, sizeof(uint32_t), true);
2149 goto secure_compile_exit
;
2151 VkSpecializationMapEntry
*mapEntries
= malloc(sizeof(VkSpecializationMapEntry
) * specInfo
->mapEntryCount
);
2152 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++) {
2153 sc_read
&= radv_sc_read(fd_secure_input
[0], &mapEntries
[j
], sizeof(VkSpecializationMapEntry
), true);
2155 goto secure_compile_exit
;
2158 specInfo
->pMapEntries
= mapEntries
;
2161 pStages
[stage
] = pStage
;
2164 /* Compile the shaders */
2165 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
2166 radv_create_shaders(pipeline
, device
, NULL
, &key
, pStages
, flags
, NULL
, stage_feedbacks
);
2168 /* free memory allocated above */
2169 for (uint32_t set
= 0; set
< layout
.num_sets
; set
++)
2170 free(layout
.set
[set
].layout
);
2172 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2176 free((void *) pStages
[i
]->pName
);
2177 free(radv_shader_module_from_handle(pStages
[i
]->module
));
2178 if (pStages
[i
]->pSpecializationInfo
) {
2179 free((void *) pStages
[i
]->pSpecializationInfo
->pData
);
2180 free((void *) pStages
[i
]->pSpecializationInfo
->pMapEntries
);
2181 free((void *) pStages
[i
]->pSpecializationInfo
);
2183 free((void *) pStages
[i
]);
2186 vk_free(&device
->alloc
, pipeline
);
2188 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
;
2189 write(fd_secure_output
[1], &sc_type
, sizeof(sc_type
));
2191 } else if (sc_type
== RADV_SC_TYPE_DESTROY_DEVICE
) {
2192 goto secure_compile_exit
;
2196 secure_compile_exit
:
2197 close(fd_secure_input
[1]);
2198 close(fd_secure_input
[0]);
2199 close(fd_secure_output
[1]);
2200 close(fd_secure_output
[0]);
2204 static void destroy_secure_compile_device(struct radv_device
*device
, unsigned process
)
2206 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
2208 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
2209 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
2211 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
);
2212 close(device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
);
2215 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2218 static VkResult
fork_secure_compile_device(struct radv_device
*device
)
2220 device
->sc_state
= vk_zalloc(&device
->alloc
,
2221 sizeof(struct radv_secure_compile_state
),
2222 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2224 mtx_init(&device
->sc_state
->secure_compile_mutex
, mtx_plain
);
2226 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2227 int fd_secure_input
[MAX_SC_PROCS
][2];
2228 int fd_secure_output
[MAX_SC_PROCS
][2];
2230 /* create pipe descriptors (used to communicate between processes) */
2231 for (unsigned i
= 0; i
< sc_threads
; i
++) {
2232 if (pipe(fd_secure_input
[i
]) == -1 ||
2233 pipe(fd_secure_output
[i
]) == -1) {
2234 return VK_ERROR_INITIALIZATION_FAILED
;
2238 device
->sc_state
->secure_compile_processes
= vk_zalloc(&device
->alloc
,
2239 sizeof(struct radv_secure_compile_process
) * sc_threads
, 8,
2240 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2242 for (unsigned process
= 0; process
< sc_threads
; process
++) {
2243 if ((device
->sc_state
->secure_compile_processes
[process
].sc_pid
= fork()) == 0) {
2244 device
->sc_state
->secure_compile_thread_counter
= process
;
2245 run_secure_compile_device(device
, process
, fd_secure_input
[process
], fd_secure_output
[process
]);
2247 if (device
->sc_state
->secure_compile_processes
[process
].sc_pid
== -1)
2248 return VK_ERROR_INITIALIZATION_FAILED
;
2250 /* Read the init result returned from the secure process */
2251 enum radv_secure_compile_type sc_type
;
2252 bool sc_read
= radv_sc_read(fd_secure_output
[process
][0], &sc_type
, sizeof(sc_type
), true);
2254 if (sc_type
== RADV_SC_TYPE_INIT_FAILURE
|| !sc_read
) {
2255 close(fd_secure_input
[process
][0]);
2256 close(fd_secure_input
[process
][1]);
2257 close(fd_secure_output
[process
][1]);
2258 close(fd_secure_output
[process
][0]);
2260 waitpid(device
->sc_state
->secure_compile_processes
[process
].sc_pid
, &status
, 0);
2262 /* Destroy any forks that were created sucessfully */
2263 for (unsigned i
= 0; i
< process
; i
++) {
2264 destroy_secure_compile_device(device
, i
);
2267 return VK_ERROR_INITIALIZATION_FAILED
;
2269 assert(sc_type
== RADV_SC_TYPE_INIT_SUCCESS
);
2270 device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
= fd_secure_input
[process
][1];
2271 device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
= fd_secure_output
[process
][0];
2279 VkResult
radv_CreateDevice(
2280 VkPhysicalDevice physicalDevice
,
2281 const VkDeviceCreateInfo
* pCreateInfo
,
2282 const VkAllocationCallbacks
* pAllocator
,
2285 RADV_FROM_HANDLE(radv_physical_device
, physical_device
, physicalDevice
);
2287 struct radv_device
*device
;
2289 bool keep_shader_info
= false;
2291 /* Check enabled features */
2292 if (pCreateInfo
->pEnabledFeatures
) {
2293 VkPhysicalDeviceFeatures supported_features
;
2294 radv_GetPhysicalDeviceFeatures(physicalDevice
, &supported_features
);
2295 VkBool32
*supported_feature
= (VkBool32
*)&supported_features
;
2296 VkBool32
*enabled_feature
= (VkBool32
*)pCreateInfo
->pEnabledFeatures
;
2297 unsigned num_features
= sizeof(VkPhysicalDeviceFeatures
) / sizeof(VkBool32
);
2298 for (uint32_t i
= 0; i
< num_features
; i
++) {
2299 if (enabled_feature
[i
] && !supported_feature
[i
])
2300 return vk_error(physical_device
->instance
, VK_ERROR_FEATURE_NOT_PRESENT
);
2304 device
= vk_zalloc2(&physical_device
->instance
->alloc
, pAllocator
,
2306 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2308 return vk_error(physical_device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2310 device
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
2311 device
->instance
= physical_device
->instance
;
2312 device
->physical_device
= physical_device
;
2314 device
->ws
= physical_device
->ws
;
2316 device
->alloc
= *pAllocator
;
2318 device
->alloc
= physical_device
->instance
->alloc
;
2320 for (uint32_t i
= 0; i
< pCreateInfo
->enabledExtensionCount
; i
++) {
2321 const char *ext_name
= pCreateInfo
->ppEnabledExtensionNames
[i
];
2322 int index
= radv_get_device_extension_index(ext_name
);
2323 if (index
< 0 || !physical_device
->supported_extensions
.extensions
[index
]) {
2324 vk_free(&device
->alloc
, device
);
2325 return vk_error(physical_device
->instance
, VK_ERROR_EXTENSION_NOT_PRESENT
);
2328 device
->enabled_extensions
.extensions
[index
] = true;
2331 keep_shader_info
= device
->enabled_extensions
.AMD_shader_info
;
2333 /* With update after bind we can't attach bo's to the command buffer
2334 * from the descriptor set anymore, so we have to use a global BO list.
2336 device
->use_global_bo_list
=
2337 (device
->instance
->perftest_flags
& RADV_PERFTEST_BO_LIST
) ||
2338 device
->enabled_extensions
.EXT_descriptor_indexing
||
2339 device
->enabled_extensions
.EXT_buffer_device_address
;
2341 device
->robust_buffer_access
= pCreateInfo
->pEnabledFeatures
&&
2342 pCreateInfo
->pEnabledFeatures
->robustBufferAccess
;
2344 mtx_init(&device
->shader_slab_mutex
, mtx_plain
);
2345 list_inithead(&device
->shader_slabs
);
2347 radv_bo_list_init(&device
->bo_list
);
2349 for (unsigned i
= 0; i
< pCreateInfo
->queueCreateInfoCount
; i
++) {
2350 const VkDeviceQueueCreateInfo
*queue_create
= &pCreateInfo
->pQueueCreateInfos
[i
];
2351 uint32_t qfi
= queue_create
->queueFamilyIndex
;
2352 const VkDeviceQueueGlobalPriorityCreateInfoEXT
*global_priority
=
2353 vk_find_struct_const(queue_create
->pNext
, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT
);
2355 assert(!global_priority
|| device
->physical_device
->rad_info
.has_ctx_priority
);
2357 device
->queues
[qfi
] = vk_alloc(&device
->alloc
,
2358 queue_create
->queueCount
* sizeof(struct radv_queue
), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
2359 if (!device
->queues
[qfi
]) {
2360 result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
2364 memset(device
->queues
[qfi
], 0, queue_create
->queueCount
* sizeof(struct radv_queue
));
2366 device
->queue_count
[qfi
] = queue_create
->queueCount
;
2368 for (unsigned q
= 0; q
< queue_create
->queueCount
; q
++) {
2369 result
= radv_queue_init(device
, &device
->queues
[qfi
][q
],
2370 qfi
, q
, queue_create
->flags
,
2372 if (result
!= VK_SUCCESS
)
2377 device
->pbb_allowed
= device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2378 !(device
->instance
->debug_flags
& RADV_DEBUG_NOBINNING
);
2380 /* Disable DFSM by default. As of 2019-09-15 Talos on Low is still 3% slower on Raven. */
2381 device
->dfsm_allowed
= device
->pbb_allowed
&&
2382 (device
->instance
->perftest_flags
& RADV_PERFTEST_DFSM
);
2384 device
->always_use_syncobj
= device
->physical_device
->rad_info
.has_syncobj_wait_for_submit
;
2386 /* The maximum number of scratch waves. Scratch space isn't divided
2387 * evenly between CUs. The number is only a function of the number of CUs.
2388 * We can decrease the constant to decrease the scratch buffer size.
2390 * sctx->scratch_waves must be >= the maximum possible size of
2391 * 1 threadgroup, so that the hw doesn't hang from being unable
2394 * The recommended value is 4 per CU at most. Higher numbers don't
2395 * bring much benefit, but they still occupy chip resources (think
2396 * async compute). I've seen ~2% performance difference between 4 and 32.
2398 uint32_t max_threads_per_block
= 2048;
2399 device
->scratch_waves
= MAX2(32 * physical_device
->rad_info
.num_good_compute_units
,
2400 max_threads_per_block
/ 64);
2402 device
->dispatch_initiator
= S_00B800_COMPUTE_SHADER_EN(1) |
2403 S_00B800_CS_W32_EN(device
->physical_device
->cs_wave_size
== 32);
2405 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2406 /* If the KMD allows it (there is a KMD hw register for it),
2407 * allow launching waves out-of-order.
2409 device
->dispatch_initiator
|= S_00B800_ORDER_MODE(1);
2412 radv_device_init_gs_info(device
);
2414 device
->tess_offchip_block_dw_size
=
2415 device
->physical_device
->rad_info
.family
== CHIP_HAWAII
? 4096 : 8192;
2417 if (getenv("RADV_TRACE_FILE")) {
2418 const char *filename
= getenv("RADV_TRACE_FILE");
2420 keep_shader_info
= true;
2422 if (!radv_init_trace(device
))
2425 fprintf(stderr
, "*****************************************************************************\n");
2426 fprintf(stderr
, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
2427 fprintf(stderr
, "*****************************************************************************\n");
2429 fprintf(stderr
, "Trace file will be dumped to %s\n", filename
);
2430 radv_dump_enabled_options(device
, stderr
);
2433 /* Temporarily disable secure compile while we create meta shaders, etc */
2434 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
2436 device
->instance
->num_sc_threads
= 0;
2438 device
->keep_shader_info
= keep_shader_info
;
2439 result
= radv_device_init_meta(device
);
2440 if (result
!= VK_SUCCESS
)
2443 radv_device_init_msaa(device
);
2445 for (int family
= 0; family
< RADV_MAX_QUEUE_FAMILIES
; ++family
) {
2446 device
->empty_cs
[family
] = device
->ws
->cs_create(device
->ws
, family
);
2448 case RADV_QUEUE_GENERAL
:
2449 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_CONTEXT_CONTROL
, 1, 0));
2450 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_LOAD_ENABLE(1));
2451 radeon_emit(device
->empty_cs
[family
], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2453 case RADV_QUEUE_COMPUTE
:
2454 radeon_emit(device
->empty_cs
[family
], PKT3(PKT3_NOP
, 0, 0));
2455 radeon_emit(device
->empty_cs
[family
], 0);
2458 device
->ws
->cs_finalize(device
->empty_cs
[family
]);
2461 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
2462 cik_create_gfx_config(device
);
2464 VkPipelineCacheCreateInfo ci
;
2465 ci
.sType
= VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO
;
2468 ci
.pInitialData
= NULL
;
2469 ci
.initialDataSize
= 0;
2471 result
= radv_CreatePipelineCache(radv_device_to_handle(device
),
2473 if (result
!= VK_SUCCESS
)
2476 device
->mem_cache
= radv_pipeline_cache_from_handle(pc
);
2478 device
->force_aniso
=
2479 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2480 if (device
->force_aniso
>= 0) {
2481 fprintf(stderr
, "radv: Forcing anisotropy filter to %ix\n",
2482 1 << util_logbase2(device
->force_aniso
));
2485 /* Fork device for secure compile as required */
2486 device
->instance
->num_sc_threads
= sc_threads
;
2487 if (radv_device_use_secure_compile(device
->instance
)) {
2488 result
= fork_secure_compile_device(device
);
2489 if (result
!= VK_SUCCESS
)
2493 *pDevice
= radv_device_to_handle(device
);
2497 radv_device_finish_meta(device
);
2499 radv_bo_list_finish(&device
->bo_list
);
2501 if (device
->trace_bo
)
2502 device
->ws
->buffer_destroy(device
->trace_bo
);
2504 if (device
->gfx_init
)
2505 device
->ws
->buffer_destroy(device
->gfx_init
);
2507 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2508 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2509 radv_queue_finish(&device
->queues
[i
][q
]);
2510 if (device
->queue_count
[i
])
2511 vk_free(&device
->alloc
, device
->queues
[i
]);
2514 vk_free(&device
->alloc
, device
);
2518 void radv_DestroyDevice(
2520 const VkAllocationCallbacks
* pAllocator
)
2522 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2527 if (device
->trace_bo
)
2528 device
->ws
->buffer_destroy(device
->trace_bo
);
2530 if (device
->gfx_init
)
2531 device
->ws
->buffer_destroy(device
->gfx_init
);
2533 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
2534 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++)
2535 radv_queue_finish(&device
->queues
[i
][q
]);
2536 if (device
->queue_count
[i
])
2537 vk_free(&device
->alloc
, device
->queues
[i
]);
2538 if (device
->empty_cs
[i
])
2539 device
->ws
->cs_destroy(device
->empty_cs
[i
]);
2541 radv_device_finish_meta(device
);
2543 VkPipelineCache pc
= radv_pipeline_cache_to_handle(device
->mem_cache
);
2544 radv_DestroyPipelineCache(radv_device_to_handle(device
), pc
, NULL
);
2546 radv_destroy_shader_slabs(device
);
2548 radv_bo_list_finish(&device
->bo_list
);
2550 if (radv_device_use_secure_compile(device
->instance
)) {
2551 for (unsigned i
= 0; i
< device
->instance
->num_sc_threads
; i
++ ) {
2552 destroy_secure_compile_device(device
, i
);
2556 if (device
->sc_state
)
2557 vk_free(&device
->alloc
, device
->sc_state
->secure_compile_processes
);
2558 vk_free(&device
->alloc
, device
->sc_state
);
2559 vk_free(&device
->alloc
, device
);
2562 VkResult
radv_EnumerateInstanceLayerProperties(
2563 uint32_t* pPropertyCount
,
2564 VkLayerProperties
* pProperties
)
2566 if (pProperties
== NULL
) {
2567 *pPropertyCount
= 0;
2571 /* None supported at this time */
2572 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2575 VkResult
radv_EnumerateDeviceLayerProperties(
2576 VkPhysicalDevice physicalDevice
,
2577 uint32_t* pPropertyCount
,
2578 VkLayerProperties
* pProperties
)
2580 if (pProperties
== NULL
) {
2581 *pPropertyCount
= 0;
2585 /* None supported at this time */
2586 return vk_error(NULL
, VK_ERROR_LAYER_NOT_PRESENT
);
2589 void radv_GetDeviceQueue2(
2591 const VkDeviceQueueInfo2
* pQueueInfo
,
2594 RADV_FROM_HANDLE(radv_device
, device
, _device
);
2595 struct radv_queue
*queue
;
2597 queue
= &device
->queues
[pQueueInfo
->queueFamilyIndex
][pQueueInfo
->queueIndex
];
2598 if (pQueueInfo
->flags
!= queue
->flags
) {
2599 /* From the Vulkan 1.1.70 spec:
2601 * "The queue returned by vkGetDeviceQueue2 must have the same
2602 * flags value from this structure as that used at device
2603 * creation time in a VkDeviceQueueCreateInfo instance. If no
2604 * matching flags were specified at device creation time then
2605 * pQueue will return VK_NULL_HANDLE."
2607 *pQueue
= VK_NULL_HANDLE
;
2611 *pQueue
= radv_queue_to_handle(queue
);
2614 void radv_GetDeviceQueue(
2616 uint32_t queueFamilyIndex
,
2617 uint32_t queueIndex
,
2620 const VkDeviceQueueInfo2 info
= (VkDeviceQueueInfo2
) {
2621 .sType
= VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2
,
2622 .queueFamilyIndex
= queueFamilyIndex
,
2623 .queueIndex
= queueIndex
2626 radv_GetDeviceQueue2(_device
, &info
, pQueue
);
2630 fill_geom_tess_rings(struct radv_queue
*queue
,
2632 bool add_sample_positions
,
2633 uint32_t esgs_ring_size
,
2634 struct radeon_winsys_bo
*esgs_ring_bo
,
2635 uint32_t gsvs_ring_size
,
2636 struct radeon_winsys_bo
*gsvs_ring_bo
,
2637 uint32_t tess_factor_ring_size
,
2638 uint32_t tess_offchip_ring_offset
,
2639 uint32_t tess_offchip_ring_size
,
2640 struct radeon_winsys_bo
*tess_rings_bo
)
2642 uint32_t *desc
= &map
[4];
2645 uint64_t esgs_va
= radv_buffer_get_va(esgs_ring_bo
);
2647 /* stride 0, num records - size, add tid, swizzle, elsize4,
2650 desc
[1] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32) |
2651 S_008F04_SWIZZLE_ENABLE(true);
2652 desc
[2] = esgs_ring_size
;
2653 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2654 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2655 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2656 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2657 S_008F0C_INDEX_STRIDE(3) |
2658 S_008F0C_ADD_TID_ENABLE(1);
2660 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2661 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2662 S_008F0C_OOB_SELECT(2) |
2663 S_008F0C_RESOURCE_LEVEL(1);
2665 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2666 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2667 S_008F0C_ELEMENT_SIZE(1);
2670 /* GS entry for ES->GS ring */
2671 /* stride 0, num records - size, elsize0,
2674 desc
[5] = S_008F04_BASE_ADDRESS_HI(esgs_va
>> 32);
2675 desc
[6] = esgs_ring_size
;
2676 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2677 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2678 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2679 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2681 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2682 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2683 S_008F0C_OOB_SELECT(2) |
2684 S_008F0C_RESOURCE_LEVEL(1);
2686 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2687 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2694 uint64_t gsvs_va
= radv_buffer_get_va(gsvs_ring_bo
);
2696 /* VS entry for GS->VS ring */
2697 /* stride 0, num records - size, elsize0,
2700 desc
[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32);
2701 desc
[2] = gsvs_ring_size
;
2702 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2703 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2704 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2705 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2707 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2708 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2709 S_008F0C_OOB_SELECT(2) |
2710 S_008F0C_RESOURCE_LEVEL(1);
2712 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2713 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2716 /* stride gsvs_itemsize, num records 64
2717 elsize 4, index stride 16 */
2718 /* shader will patch stride and desc[2] */
2720 desc
[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va
>> 32) |
2721 S_008F04_SWIZZLE_ENABLE(1);
2723 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2724 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2725 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2726 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
) |
2727 S_008F0C_INDEX_STRIDE(1) |
2728 S_008F0C_ADD_TID_ENABLE(true);
2730 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2731 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2732 S_008F0C_OOB_SELECT(2) |
2733 S_008F0C_RESOURCE_LEVEL(1);
2735 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2736 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
) |
2737 S_008F0C_ELEMENT_SIZE(1);
2744 if (tess_rings_bo
) {
2745 uint64_t tess_va
= radv_buffer_get_va(tess_rings_bo
);
2746 uint64_t tess_offchip_va
= tess_va
+ tess_offchip_ring_offset
;
2749 desc
[1] = S_008F04_BASE_ADDRESS_HI(tess_va
>> 32);
2750 desc
[2] = tess_factor_ring_size
;
2751 desc
[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2752 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2753 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2754 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2756 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2757 desc
[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2758 S_008F0C_OOB_SELECT(3) |
2759 S_008F0C_RESOURCE_LEVEL(1);
2761 desc
[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2762 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2765 desc
[4] = tess_offchip_va
;
2766 desc
[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va
>> 32);
2767 desc
[6] = tess_offchip_ring_size
;
2768 desc
[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
2769 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
2770 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
2771 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
2773 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2774 desc
[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
2775 S_008F0C_OOB_SELECT(3) |
2776 S_008F0C_RESOURCE_LEVEL(1);
2778 desc
[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
2779 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
2785 if (add_sample_positions
) {
2786 /* add sample positions after all rings */
2787 memcpy(desc
, queue
->device
->sample_locations_1x
, 8);
2789 memcpy(desc
, queue
->device
->sample_locations_2x
, 16);
2791 memcpy(desc
, queue
->device
->sample_locations_4x
, 32);
2793 memcpy(desc
, queue
->device
->sample_locations_8x
, 64);
2798 radv_get_hs_offchip_param(struct radv_device
*device
, uint32_t *max_offchip_buffers_p
)
2800 bool double_offchip_buffers
= device
->physical_device
->rad_info
.chip_class
>= GFX7
&&
2801 device
->physical_device
->rad_info
.family
!= CHIP_CARRIZO
&&
2802 device
->physical_device
->rad_info
.family
!= CHIP_STONEY
;
2803 unsigned max_offchip_buffers_per_se
= double_offchip_buffers
? 128 : 64;
2804 unsigned max_offchip_buffers
;
2805 unsigned offchip_granularity
;
2806 unsigned hs_offchip_param
;
2810 * This must be one less than the maximum number due to a hw limitation.
2811 * Various hardware bugs need thGFX7
2814 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2815 * Gfx7 should limit max_offchip_buffers to 508
2816 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2818 * Follow AMDVLK here.
2820 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2821 max_offchip_buffers_per_se
= 256;
2822 } else if (device
->physical_device
->rad_info
.family
== CHIP_VEGA10
||
2823 device
->physical_device
->rad_info
.chip_class
== GFX7
||
2824 device
->physical_device
->rad_info
.chip_class
== GFX6
)
2825 --max_offchip_buffers_per_se
;
2827 max_offchip_buffers
= max_offchip_buffers_per_se
*
2828 device
->physical_device
->rad_info
.max_se
;
2830 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2831 * around by setting 4K granularity.
2833 if (device
->tess_offchip_block_dw_size
== 4096) {
2834 assert(device
->physical_device
->rad_info
.family
== CHIP_HAWAII
);
2835 offchip_granularity
= V_03093C_X_4K_DWORDS
;
2837 assert(device
->tess_offchip_block_dw_size
== 8192);
2838 offchip_granularity
= V_03093C_X_8K_DWORDS
;
2841 switch (device
->physical_device
->rad_info
.chip_class
) {
2843 max_offchip_buffers
= MIN2(max_offchip_buffers
, 126);
2848 max_offchip_buffers
= MIN2(max_offchip_buffers
, 508);
2856 *max_offchip_buffers_p
= max_offchip_buffers
;
2857 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2858 if (device
->physical_device
->rad_info
.chip_class
>= GFX8
)
2859 --max_offchip_buffers
;
2861 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers
) |
2862 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity
);
2865 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers
);
2867 return hs_offchip_param
;
2871 radv_emit_gs_ring_sizes(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2872 struct radeon_winsys_bo
*esgs_ring_bo
,
2873 uint32_t esgs_ring_size
,
2874 struct radeon_winsys_bo
*gsvs_ring_bo
,
2875 uint32_t gsvs_ring_size
)
2877 if (!esgs_ring_bo
&& !gsvs_ring_bo
)
2881 radv_cs_add_buffer(queue
->device
->ws
, cs
, esgs_ring_bo
);
2884 radv_cs_add_buffer(queue
->device
->ws
, cs
, gsvs_ring_bo
);
2886 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2887 radeon_set_uconfig_reg_seq(cs
, R_030900_VGT_ESGS_RING_SIZE
, 2);
2888 radeon_emit(cs
, esgs_ring_size
>> 8);
2889 radeon_emit(cs
, gsvs_ring_size
>> 8);
2891 radeon_set_config_reg_seq(cs
, R_0088C8_VGT_ESGS_RING_SIZE
, 2);
2892 radeon_emit(cs
, esgs_ring_size
>> 8);
2893 radeon_emit(cs
, gsvs_ring_size
>> 8);
2898 radv_emit_tess_factor_ring(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2899 unsigned hs_offchip_param
, unsigned tf_ring_size
,
2900 struct radeon_winsys_bo
*tess_rings_bo
)
2907 tf_va
= radv_buffer_get_va(tess_rings_bo
);
2909 radv_cs_add_buffer(queue
->device
->ws
, cs
, tess_rings_bo
);
2911 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2912 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
2913 S_030938_SIZE(tf_ring_size
/ 4));
2914 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
,
2917 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2918 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
2919 S_030984_BASE_HI(tf_va
>> 40));
2920 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2921 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
2922 S_030944_BASE_HI(tf_va
>> 40));
2924 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
2927 radeon_set_config_reg(cs
, R_008988_VGT_TF_RING_SIZE
,
2928 S_008988_SIZE(tf_ring_size
/ 4));
2929 radeon_set_config_reg(cs
, R_0089B8_VGT_TF_MEMORY_BASE
,
2931 radeon_set_config_reg(cs
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
2937 radv_emit_compute_scratch(struct radv_queue
*queue
, struct radeon_cmdbuf
*cs
,
2938 struct radeon_winsys_bo
*compute_scratch_bo
)
2940 uint64_t scratch_va
;
2942 if (!compute_scratch_bo
)
2945 scratch_va
= radv_buffer_get_va(compute_scratch_bo
);
2947 radv_cs_add_buffer(queue
->device
->ws
, cs
, compute_scratch_bo
);
2949 radeon_set_sh_reg_seq(cs
, R_00B900_COMPUTE_USER_DATA_0
, 2);
2950 radeon_emit(cs
, scratch_va
);
2951 radeon_emit(cs
, S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
2952 S_008F04_SWIZZLE_ENABLE(1));
2956 radv_emit_global_shader_pointers(struct radv_queue
*queue
,
2957 struct radeon_cmdbuf
*cs
,
2958 struct radeon_winsys_bo
*descriptor_bo
)
2965 va
= radv_buffer_get_va(descriptor_bo
);
2967 radv_cs_add_buffer(queue
->device
->ws
, cs
, descriptor_bo
);
2969 if (queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
2970 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2971 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2972 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2973 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2975 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2976 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2979 } else if (queue
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
2980 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2981 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2982 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS
,
2983 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS
};
2985 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2986 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
2990 uint32_t regs
[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0
,
2991 R_00B130_SPI_SHADER_USER_DATA_VS_0
,
2992 R_00B230_SPI_SHADER_USER_DATA_GS_0
,
2993 R_00B330_SPI_SHADER_USER_DATA_ES_0
,
2994 R_00B430_SPI_SHADER_USER_DATA_HS_0
,
2995 R_00B530_SPI_SHADER_USER_DATA_LS_0
};
2997 for (int i
= 0; i
< ARRAY_SIZE(regs
); ++i
) {
2998 radv_emit_shader_pointer(queue
->device
, cs
, regs
[i
],
3005 radv_init_graphics_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3007 struct radv_device
*device
= queue
->device
;
3009 if (device
->gfx_init
) {
3010 uint64_t va
= radv_buffer_get_va(device
->gfx_init
);
3012 radeon_emit(cs
, PKT3(PKT3_INDIRECT_BUFFER_CIK
, 2, 0));
3013 radeon_emit(cs
, va
);
3014 radeon_emit(cs
, va
>> 32);
3015 radeon_emit(cs
, device
->gfx_init_size_dw
& 0xffff);
3017 radv_cs_add_buffer(device
->ws
, cs
, device
->gfx_init
);
3019 struct radv_physical_device
*physical_device
= device
->physical_device
;
3020 si_emit_graphics(physical_device
, cs
);
3025 radv_init_compute_state(struct radeon_cmdbuf
*cs
, struct radv_queue
*queue
)
3027 struct radv_physical_device
*physical_device
= queue
->device
->physical_device
;
3028 si_emit_compute(physical_device
, cs
);
3032 radv_get_preamble_cs(struct radv_queue
*queue
,
3033 uint32_t scratch_size
,
3034 uint32_t compute_scratch_size
,
3035 uint32_t esgs_ring_size
,
3036 uint32_t gsvs_ring_size
,
3037 bool needs_tess_rings
,
3039 bool needs_sample_positions
,
3040 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3041 struct radeon_cmdbuf
**initial_preamble_cs
,
3042 struct radeon_cmdbuf
**continue_preamble_cs
)
3044 struct radeon_winsys_bo
*scratch_bo
= NULL
;
3045 struct radeon_winsys_bo
*descriptor_bo
= NULL
;
3046 struct radeon_winsys_bo
*compute_scratch_bo
= NULL
;
3047 struct radeon_winsys_bo
*esgs_ring_bo
= NULL
;
3048 struct radeon_winsys_bo
*gsvs_ring_bo
= NULL
;
3049 struct radeon_winsys_bo
*tess_rings_bo
= NULL
;
3050 struct radeon_winsys_bo
*gds_bo
= NULL
;
3051 struct radeon_winsys_bo
*gds_oa_bo
= NULL
;
3052 struct radeon_cmdbuf
*dest_cs
[3] = {0};
3053 bool add_tess_rings
= false, add_gds
= false, add_sample_positions
= false;
3054 unsigned tess_factor_ring_size
= 0, tess_offchip_ring_size
= 0;
3055 unsigned max_offchip_buffers
;
3056 unsigned hs_offchip_param
= 0;
3057 unsigned tess_offchip_ring_offset
;
3058 uint32_t ring_bo_flags
= RADEON_FLAG_NO_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
;
3059 if (!queue
->has_tess_rings
) {
3060 if (needs_tess_rings
)
3061 add_tess_rings
= true;
3063 if (!queue
->has_gds
) {
3067 if (!queue
->has_sample_positions
) {
3068 if (needs_sample_positions
)
3069 add_sample_positions
= true;
3071 tess_factor_ring_size
= 32768 * queue
->device
->physical_device
->rad_info
.max_se
;
3072 hs_offchip_param
= radv_get_hs_offchip_param(queue
->device
,
3073 &max_offchip_buffers
);
3074 tess_offchip_ring_offset
= align(tess_factor_ring_size
, 64 * 1024);
3075 tess_offchip_ring_size
= max_offchip_buffers
*
3076 queue
->device
->tess_offchip_block_dw_size
* 4;
3078 if (scratch_size
<= queue
->scratch_size
&&
3079 compute_scratch_size
<= queue
->compute_scratch_size
&&
3080 esgs_ring_size
<= queue
->esgs_ring_size
&&
3081 gsvs_ring_size
<= queue
->gsvs_ring_size
&&
3082 !add_tess_rings
&& !add_gds
&& !add_sample_positions
&&
3083 queue
->initial_preamble_cs
) {
3084 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3085 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3086 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3087 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
&&
3088 !needs_tess_rings
&& !needs_gds
&& !needs_sample_positions
)
3089 *continue_preamble_cs
= NULL
;
3093 if (scratch_size
> queue
->scratch_size
) {
3094 scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3099 RADV_BO_PRIORITY_SCRATCH
);
3103 scratch_bo
= queue
->scratch_bo
;
3105 if (compute_scratch_size
> queue
->compute_scratch_size
) {
3106 compute_scratch_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3107 compute_scratch_size
,
3111 RADV_BO_PRIORITY_SCRATCH
);
3112 if (!compute_scratch_bo
)
3116 compute_scratch_bo
= queue
->compute_scratch_bo
;
3118 if (esgs_ring_size
> queue
->esgs_ring_size
) {
3119 esgs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3124 RADV_BO_PRIORITY_SCRATCH
);
3128 esgs_ring_bo
= queue
->esgs_ring_bo
;
3129 esgs_ring_size
= queue
->esgs_ring_size
;
3132 if (gsvs_ring_size
> queue
->gsvs_ring_size
) {
3133 gsvs_ring_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3138 RADV_BO_PRIORITY_SCRATCH
);
3142 gsvs_ring_bo
= queue
->gsvs_ring_bo
;
3143 gsvs_ring_size
= queue
->gsvs_ring_size
;
3146 if (add_tess_rings
) {
3147 tess_rings_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3148 tess_offchip_ring_offset
+ tess_offchip_ring_size
,
3152 RADV_BO_PRIORITY_SCRATCH
);
3156 tess_rings_bo
= queue
->tess_rings_bo
;
3160 assert(queue
->device
->physical_device
->rad_info
.chip_class
>= GFX10
);
3162 /* 4 streamout GDS counters.
3163 * We need 256B (64 dw) of GDS, otherwise streamout hangs.
3165 gds_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3169 RADV_BO_PRIORITY_SCRATCH
);
3173 gds_oa_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3177 RADV_BO_PRIORITY_SCRATCH
);
3181 gds_bo
= queue
->gds_bo
;
3182 gds_oa_bo
= queue
->gds_oa_bo
;
3185 if (scratch_bo
!= queue
->scratch_bo
||
3186 esgs_ring_bo
!= queue
->esgs_ring_bo
||
3187 gsvs_ring_bo
!= queue
->gsvs_ring_bo
||
3188 tess_rings_bo
!= queue
->tess_rings_bo
||
3189 add_sample_positions
) {
3191 if (gsvs_ring_bo
|| esgs_ring_bo
||
3192 tess_rings_bo
|| add_sample_positions
) {
3193 size
= 112; /* 2 dword + 2 padding + 4 dword * 6 */
3194 if (add_sample_positions
)
3195 size
+= 128; /* 64+32+16+8 = 120 bytes */
3197 else if (scratch_bo
)
3198 size
= 8; /* 2 dword */
3200 descriptor_bo
= queue
->device
->ws
->buffer_create(queue
->device
->ws
,
3204 RADEON_FLAG_CPU_ACCESS
|
3205 RADEON_FLAG_NO_INTERPROCESS_SHARING
|
3206 RADEON_FLAG_READ_ONLY
,
3207 RADV_BO_PRIORITY_DESCRIPTOR
);
3211 descriptor_bo
= queue
->descriptor_bo
;
3213 if (descriptor_bo
!= queue
->descriptor_bo
) {
3214 uint32_t *map
= (uint32_t*)queue
->device
->ws
->buffer_map(descriptor_bo
);
3217 uint64_t scratch_va
= radv_buffer_get_va(scratch_bo
);
3218 uint32_t rsrc1
= S_008F04_BASE_ADDRESS_HI(scratch_va
>> 32) |
3219 S_008F04_SWIZZLE_ENABLE(1);
3220 map
[0] = scratch_va
;
3224 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
|| add_sample_positions
)
3225 fill_geom_tess_rings(queue
, map
, add_sample_positions
,
3226 esgs_ring_size
, esgs_ring_bo
,
3227 gsvs_ring_size
, gsvs_ring_bo
,
3228 tess_factor_ring_size
,
3229 tess_offchip_ring_offset
,
3230 tess_offchip_ring_size
,
3233 queue
->device
->ws
->buffer_unmap(descriptor_bo
);
3236 for(int i
= 0; i
< 3; ++i
) {
3237 struct radeon_cmdbuf
*cs
= NULL
;
3238 cs
= queue
->device
->ws
->cs_create(queue
->device
->ws
,
3239 queue
->queue_family_index
? RING_COMPUTE
: RING_GFX
);
3246 radv_cs_add_buffer(queue
->device
->ws
, cs
, scratch_bo
);
3248 /* Emit initial configuration. */
3249 switch (queue
->queue_family_index
) {
3250 case RADV_QUEUE_GENERAL
:
3251 radv_init_graphics_state(cs
, queue
);
3253 case RADV_QUEUE_COMPUTE
:
3254 radv_init_compute_state(cs
, queue
);
3256 case RADV_QUEUE_TRANSFER
:
3260 if (esgs_ring_bo
|| gsvs_ring_bo
|| tess_rings_bo
) {
3261 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3262 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3264 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3265 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3268 radv_emit_gs_ring_sizes(queue
, cs
, esgs_ring_bo
, esgs_ring_size
,
3269 gsvs_ring_bo
, gsvs_ring_size
);
3270 radv_emit_tess_factor_ring(queue
, cs
, hs_offchip_param
,
3271 tess_factor_ring_size
, tess_rings_bo
);
3272 radv_emit_global_shader_pointers(queue
, cs
, descriptor_bo
);
3273 radv_emit_compute_scratch(queue
, cs
, compute_scratch_bo
);
3276 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_bo
);
3278 radv_cs_add_buffer(queue
->device
->ws
, cs
, gds_oa_bo
);
3281 si_cs_emit_cache_flush(cs
,
3282 queue
->device
->physical_device
->rad_info
.chip_class
,
3284 queue
->queue_family_index
== RING_COMPUTE
&&
3285 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3286 (queue
->queue_family_index
== RADV_QUEUE_COMPUTE
? RADV_CMD_FLAG_CS_PARTIAL_FLUSH
: (RADV_CMD_FLAG_CS_PARTIAL_FLUSH
| RADV_CMD_FLAG_PS_PARTIAL_FLUSH
)) |
3287 RADV_CMD_FLAG_INV_ICACHE
|
3288 RADV_CMD_FLAG_INV_SCACHE
|
3289 RADV_CMD_FLAG_INV_VCACHE
|
3290 RADV_CMD_FLAG_INV_L2
|
3291 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3292 } else if (i
== 1) {
3293 si_cs_emit_cache_flush(cs
,
3294 queue
->device
->physical_device
->rad_info
.chip_class
,
3296 queue
->queue_family_index
== RING_COMPUTE
&&
3297 queue
->device
->physical_device
->rad_info
.chip_class
>= GFX7
,
3298 RADV_CMD_FLAG_INV_ICACHE
|
3299 RADV_CMD_FLAG_INV_SCACHE
|
3300 RADV_CMD_FLAG_INV_VCACHE
|
3301 RADV_CMD_FLAG_INV_L2
|
3302 RADV_CMD_FLAG_START_PIPELINE_STATS
, 0);
3305 if (!queue
->device
->ws
->cs_finalize(cs
))
3309 if (queue
->initial_full_flush_preamble_cs
)
3310 queue
->device
->ws
->cs_destroy(queue
->initial_full_flush_preamble_cs
);
3312 if (queue
->initial_preamble_cs
)
3313 queue
->device
->ws
->cs_destroy(queue
->initial_preamble_cs
);
3315 if (queue
->continue_preamble_cs
)
3316 queue
->device
->ws
->cs_destroy(queue
->continue_preamble_cs
);
3318 queue
->initial_full_flush_preamble_cs
= dest_cs
[0];
3319 queue
->initial_preamble_cs
= dest_cs
[1];
3320 queue
->continue_preamble_cs
= dest_cs
[2];
3322 if (scratch_bo
!= queue
->scratch_bo
) {
3323 if (queue
->scratch_bo
)
3324 queue
->device
->ws
->buffer_destroy(queue
->scratch_bo
);
3325 queue
->scratch_bo
= scratch_bo
;
3326 queue
->scratch_size
= scratch_size
;
3329 if (compute_scratch_bo
!= queue
->compute_scratch_bo
) {
3330 if (queue
->compute_scratch_bo
)
3331 queue
->device
->ws
->buffer_destroy(queue
->compute_scratch_bo
);
3332 queue
->compute_scratch_bo
= compute_scratch_bo
;
3333 queue
->compute_scratch_size
= compute_scratch_size
;
3336 if (esgs_ring_bo
!= queue
->esgs_ring_bo
) {
3337 if (queue
->esgs_ring_bo
)
3338 queue
->device
->ws
->buffer_destroy(queue
->esgs_ring_bo
);
3339 queue
->esgs_ring_bo
= esgs_ring_bo
;
3340 queue
->esgs_ring_size
= esgs_ring_size
;
3343 if (gsvs_ring_bo
!= queue
->gsvs_ring_bo
) {
3344 if (queue
->gsvs_ring_bo
)
3345 queue
->device
->ws
->buffer_destroy(queue
->gsvs_ring_bo
);
3346 queue
->gsvs_ring_bo
= gsvs_ring_bo
;
3347 queue
->gsvs_ring_size
= gsvs_ring_size
;
3350 if (tess_rings_bo
!= queue
->tess_rings_bo
) {
3351 queue
->tess_rings_bo
= tess_rings_bo
;
3352 queue
->has_tess_rings
= true;
3355 if (gds_bo
!= queue
->gds_bo
) {
3356 queue
->gds_bo
= gds_bo
;
3357 queue
->has_gds
= true;
3360 if (gds_oa_bo
!= queue
->gds_oa_bo
)
3361 queue
->gds_oa_bo
= gds_oa_bo
;
3363 if (descriptor_bo
!= queue
->descriptor_bo
) {
3364 if (queue
->descriptor_bo
)
3365 queue
->device
->ws
->buffer_destroy(queue
->descriptor_bo
);
3367 queue
->descriptor_bo
= descriptor_bo
;
3370 if (add_sample_positions
)
3371 queue
->has_sample_positions
= true;
3373 *initial_full_flush_preamble_cs
= queue
->initial_full_flush_preamble_cs
;
3374 *initial_preamble_cs
= queue
->initial_preamble_cs
;
3375 *continue_preamble_cs
= queue
->continue_preamble_cs
;
3376 if (!scratch_size
&& !compute_scratch_size
&& !esgs_ring_size
&& !gsvs_ring_size
)
3377 *continue_preamble_cs
= NULL
;
3380 for (int i
= 0; i
< ARRAY_SIZE(dest_cs
); ++i
)
3382 queue
->device
->ws
->cs_destroy(dest_cs
[i
]);
3383 if (descriptor_bo
&& descriptor_bo
!= queue
->descriptor_bo
)
3384 queue
->device
->ws
->buffer_destroy(descriptor_bo
);
3385 if (scratch_bo
&& scratch_bo
!= queue
->scratch_bo
)
3386 queue
->device
->ws
->buffer_destroy(scratch_bo
);
3387 if (compute_scratch_bo
&& compute_scratch_bo
!= queue
->compute_scratch_bo
)
3388 queue
->device
->ws
->buffer_destroy(compute_scratch_bo
);
3389 if (esgs_ring_bo
&& esgs_ring_bo
!= queue
->esgs_ring_bo
)
3390 queue
->device
->ws
->buffer_destroy(esgs_ring_bo
);
3391 if (gsvs_ring_bo
&& gsvs_ring_bo
!= queue
->gsvs_ring_bo
)
3392 queue
->device
->ws
->buffer_destroy(gsvs_ring_bo
);
3393 if (tess_rings_bo
&& tess_rings_bo
!= queue
->tess_rings_bo
)
3394 queue
->device
->ws
->buffer_destroy(tess_rings_bo
);
3395 if (gds_bo
&& gds_bo
!= queue
->gds_bo
)
3396 queue
->device
->ws
->buffer_destroy(gds_bo
);
3397 if (gds_oa_bo
&& gds_oa_bo
!= queue
->gds_oa_bo
)
3398 queue
->device
->ws
->buffer_destroy(gds_oa_bo
);
3400 return vk_error(queue
->device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
3403 static VkResult
radv_alloc_sem_counts(struct radv_instance
*instance
,
3404 struct radv_winsys_sem_counts
*counts
,
3406 const VkSemaphore
*sems
,
3409 int syncobj_idx
= 0, sem_idx
= 0;
3411 if (num_sems
== 0 && _fence
== VK_NULL_HANDLE
)
3414 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3415 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
3417 if (sem
->temp_syncobj
|| sem
->syncobj
)
3418 counts
->syncobj_count
++;
3420 counts
->sem_count
++;
3423 if (_fence
!= VK_NULL_HANDLE
) {
3424 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3425 if (fence
->temp_syncobj
|| fence
->syncobj
)
3426 counts
->syncobj_count
++;
3429 if (counts
->syncobj_count
) {
3430 counts
->syncobj
= (uint32_t *)malloc(sizeof(uint32_t) * counts
->syncobj_count
);
3431 if (!counts
->syncobj
)
3432 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3435 if (counts
->sem_count
) {
3436 counts
->sem
= (struct radeon_winsys_sem
**)malloc(sizeof(struct radeon_winsys_sem
*) * counts
->sem_count
);
3438 free(counts
->syncobj
);
3439 return vk_error(instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
3443 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3444 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
3446 if (sem
->temp_syncobj
) {
3447 counts
->syncobj
[syncobj_idx
++] = sem
->temp_syncobj
;
3449 else if (sem
->syncobj
)
3450 counts
->syncobj
[syncobj_idx
++] = sem
->syncobj
;
3453 counts
->sem
[sem_idx
++] = sem
->sem
;
3457 if (_fence
!= VK_NULL_HANDLE
) {
3458 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
3459 if (fence
->temp_syncobj
)
3460 counts
->syncobj
[syncobj_idx
++] = fence
->temp_syncobj
;
3461 else if (fence
->syncobj
)
3462 counts
->syncobj
[syncobj_idx
++] = fence
->syncobj
;
3469 radv_free_sem_info(struct radv_winsys_sem_info
*sem_info
)
3471 free(sem_info
->wait
.syncobj
);
3472 free(sem_info
->wait
.sem
);
3473 free(sem_info
->signal
.syncobj
);
3474 free(sem_info
->signal
.sem
);
3478 static void radv_free_temp_syncobjs(struct radv_device
*device
,
3480 const VkSemaphore
*sems
)
3482 for (uint32_t i
= 0; i
< num_sems
; i
++) {
3483 RADV_FROM_HANDLE(radv_semaphore
, sem
, sems
[i
]);
3485 if (sem
->temp_syncobj
) {
3486 device
->ws
->destroy_syncobj(device
->ws
, sem
->temp_syncobj
);
3487 sem
->temp_syncobj
= 0;
3493 radv_alloc_sem_info(struct radv_instance
*instance
,
3494 struct radv_winsys_sem_info
*sem_info
,
3496 const VkSemaphore
*wait_sems
,
3497 int num_signal_sems
,
3498 const VkSemaphore
*signal_sems
,
3502 memset(sem_info
, 0, sizeof(*sem_info
));
3504 ret
= radv_alloc_sem_counts(instance
, &sem_info
->wait
, num_wait_sems
, wait_sems
, VK_NULL_HANDLE
);
3507 ret
= radv_alloc_sem_counts(instance
, &sem_info
->signal
, num_signal_sems
, signal_sems
, fence
);
3509 radv_free_sem_info(sem_info
);
3511 /* caller can override these */
3512 sem_info
->cs_emit_wait
= true;
3513 sem_info
->cs_emit_signal
= true;
3518 radv_sparse_buffer_bind_memory(struct radv_device
*device
,
3519 const VkSparseBufferMemoryBindInfo
*bind
)
3521 RADV_FROM_HANDLE(radv_buffer
, buffer
, bind
->buffer
);
3523 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3524 struct radv_device_memory
*mem
= NULL
;
3526 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3527 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3529 device
->ws
->buffer_virtual_bind(buffer
->bo
,
3530 bind
->pBinds
[i
].resourceOffset
,
3531 bind
->pBinds
[i
].size
,
3532 mem
? mem
->bo
: NULL
,
3533 bind
->pBinds
[i
].memoryOffset
);
3538 radv_sparse_image_opaque_bind_memory(struct radv_device
*device
,
3539 const VkSparseImageOpaqueMemoryBindInfo
*bind
)
3541 RADV_FROM_HANDLE(radv_image
, image
, bind
->image
);
3543 for (uint32_t i
= 0; i
< bind
->bindCount
; ++i
) {
3544 struct radv_device_memory
*mem
= NULL
;
3546 if (bind
->pBinds
[i
].memory
!= VK_NULL_HANDLE
)
3547 mem
= radv_device_memory_from_handle(bind
->pBinds
[i
].memory
);
3549 device
->ws
->buffer_virtual_bind(image
->bo
,
3550 bind
->pBinds
[i
].resourceOffset
,
3551 bind
->pBinds
[i
].size
,
3552 mem
? mem
->bo
: NULL
,
3553 bind
->pBinds
[i
].memoryOffset
);
3558 radv_get_preambles(struct radv_queue
*queue
,
3559 const VkCommandBuffer
*cmd_buffers
,
3560 uint32_t cmd_buffer_count
,
3561 struct radeon_cmdbuf
**initial_full_flush_preamble_cs
,
3562 struct radeon_cmdbuf
**initial_preamble_cs
,
3563 struct radeon_cmdbuf
**continue_preamble_cs
)
3565 uint32_t scratch_size
= 0;
3566 uint32_t compute_scratch_size
= 0;
3567 uint32_t esgs_ring_size
= 0, gsvs_ring_size
= 0;
3568 bool tess_rings_needed
= false;
3569 bool gds_needed
= false;
3570 bool sample_positions_needed
= false;
3572 for (uint32_t j
= 0; j
< cmd_buffer_count
; j
++) {
3573 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
,
3576 scratch_size
= MAX2(scratch_size
, cmd_buffer
->scratch_size_needed
);
3577 compute_scratch_size
= MAX2(compute_scratch_size
,
3578 cmd_buffer
->compute_scratch_size_needed
);
3579 esgs_ring_size
= MAX2(esgs_ring_size
, cmd_buffer
->esgs_ring_size_needed
);
3580 gsvs_ring_size
= MAX2(gsvs_ring_size
, cmd_buffer
->gsvs_ring_size_needed
);
3581 tess_rings_needed
|= cmd_buffer
->tess_rings_needed
;
3582 gds_needed
|= cmd_buffer
->gds_needed
;
3583 sample_positions_needed
|= cmd_buffer
->sample_positions_needed
;
3586 return radv_get_preamble_cs(queue
, scratch_size
, compute_scratch_size
,
3587 esgs_ring_size
, gsvs_ring_size
, tess_rings_needed
,
3588 gds_needed
, sample_positions_needed
,
3589 initial_full_flush_preamble_cs
,
3590 initial_preamble_cs
, continue_preamble_cs
);
3594 struct radv_queue_submission
{
3595 const VkCommandBuffer
*cmd_buffers
;
3596 uint32_t cmd_buffer_count
;
3598 /* Sparse bindings that happen on a queue. */
3599 const VkSparseBufferMemoryBindInfo
*buffer_binds
;
3600 uint32_t buffer_bind_count
;
3601 const VkSparseImageOpaqueMemoryBindInfo
*image_opaque_binds
;
3602 uint32_t image_opaque_bind_count
;
3605 VkPipelineStageFlags wait_dst_stage_mask
;
3606 const VkSemaphore
*wait_semaphores
;
3607 uint32_t wait_semaphore_count
;
3608 const VkSemaphore
*signal_semaphores
;
3609 uint32_t signal_semaphore_count
;
3614 radv_queue_submit(struct radv_queue
*queue
,
3615 const struct radv_queue_submission
*submission
)
3617 RADV_FROM_HANDLE(radv_fence
, fence
, submission
->fence
);
3618 struct radeon_cmdbuf
**cs_array
;
3619 struct radeon_winsys_ctx
*ctx
= queue
->hw_ctx
;
3620 uint32_t max_cs_submission
= queue
->device
->trace_bo
? 1 : RADV_MAX_IBS_PER_SUBMIT
;
3621 struct radeon_winsys_fence
*base_fence
= fence
? fence
->fence
: NULL
;
3622 bool do_flush
= submission
->flush_caches
|| submission
->wait_dst_stage_mask
;
3623 bool can_patch
= true;
3625 struct radv_winsys_sem_info sem_info
;
3628 struct radeon_cmdbuf
*initial_preamble_cs
= NULL
;
3629 struct radeon_cmdbuf
*initial_flush_preamble_cs
= NULL
;
3630 struct radeon_cmdbuf
*continue_preamble_cs
= NULL
;
3632 result
= radv_get_preambles(queue
, submission
->cmd_buffers
,
3633 submission
->cmd_buffer_count
,
3634 &initial_preamble_cs
,
3635 &initial_flush_preamble_cs
,
3636 &continue_preamble_cs
);
3637 if (result
!= VK_SUCCESS
)
3640 result
= radv_alloc_sem_info(queue
->device
->instance
,
3642 submission
->wait_semaphore_count
,
3643 submission
->wait_semaphores
,
3644 submission
->signal_semaphore_count
,
3645 submission
->signal_semaphores
,
3647 if (result
!= VK_SUCCESS
)
3650 for (uint32_t i
= 0; i
< submission
->buffer_bind_count
; ++i
) {
3651 radv_sparse_buffer_bind_memory(queue
->device
,
3652 submission
->buffer_binds
+ i
);
3655 for (uint32_t i
= 0; i
< submission
->image_opaque_bind_count
; ++i
) {
3656 radv_sparse_image_opaque_bind_memory(queue
->device
,
3657 submission
->image_opaque_binds
+ i
);
3660 if (!submission
->cmd_buffer_count
) {
3661 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
,
3662 &queue
->device
->empty_cs
[queue
->queue_family_index
],
3667 radv_loge("failed to submit CS\n");
3670 radv_free_sem_info(&sem_info
);
3674 cs_array
= malloc(sizeof(struct radeon_cmdbuf
*) *
3675 (submission
->cmd_buffer_count
));
3677 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
++) {
3678 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, submission
->cmd_buffers
[j
]);
3679 assert(cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
);
3681 cs_array
[j
] = cmd_buffer
->cs
;
3682 if ((cmd_buffer
->usage_flags
& VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT
))
3685 cmd_buffer
->status
= RADV_CMD_BUFFER_STATUS_PENDING
;
3688 for (uint32_t j
= 0; j
< submission
->cmd_buffer_count
; j
+= advance
) {
3689 struct radeon_cmdbuf
*initial_preamble
= (do_flush
&& !j
) ? initial_flush_preamble_cs
: initial_preamble_cs
;
3690 const struct radv_winsys_bo_list
*bo_list
= NULL
;
3692 advance
= MIN2(max_cs_submission
,
3693 submission
->cmd_buffer_count
- j
);
3695 if (queue
->device
->trace_bo
)
3696 *queue
->device
->trace_id_ptr
= 0;
3698 sem_info
.cs_emit_wait
= j
== 0;
3699 sem_info
.cs_emit_signal
= j
+ advance
== submission
->cmd_buffer_count
;
3701 if (unlikely(queue
->device
->use_global_bo_list
)) {
3702 pthread_mutex_lock(&queue
->device
->bo_list
.mutex
);
3703 bo_list
= &queue
->device
->bo_list
.list
;
3706 ret
= queue
->device
->ws
->cs_submit(ctx
, queue
->queue_idx
, cs_array
+ j
,
3707 advance
, initial_preamble
, continue_preamble_cs
,
3709 can_patch
, base_fence
);
3711 if (unlikely(queue
->device
->use_global_bo_list
))
3712 pthread_mutex_unlock(&queue
->device
->bo_list
.mutex
);
3715 radv_loge("failed to submit CS\n");
3718 if (queue
->device
->trace_bo
) {
3719 radv_check_gpu_hangs(queue
, cs_array
[j
]);
3723 radv_free_temp_syncobjs(queue
->device
,
3724 submission
->wait_semaphore_count
,
3725 submission
->wait_semaphores
);
3726 radv_free_sem_info(&sem_info
);
3731 /* Signals fence as soon as all the work currently put on queue is done. */
3732 static VkResult
radv_signal_fence(struct radv_queue
*queue
,
3735 return radv_queue_submit(queue
, &(struct radv_queue_submission
) {
3740 static bool radv_submit_has_effects(const VkSubmitInfo
*info
)
3742 return info
->commandBufferCount
||
3743 info
->waitSemaphoreCount
||
3744 info
->signalSemaphoreCount
;
3747 VkResult
radv_QueueSubmit(
3749 uint32_t submitCount
,
3750 const VkSubmitInfo
* pSubmits
,
3753 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3755 uint32_t fence_idx
= 0;
3756 bool flushed_caches
= false;
3758 if (fence
!= VK_NULL_HANDLE
) {
3759 for (uint32_t i
= 0; i
< submitCount
; ++i
)
3760 if (radv_submit_has_effects(pSubmits
+ i
))
3763 fence_idx
= UINT32_MAX
;
3765 for (uint32_t i
= 0; i
< submitCount
; i
++) {
3766 if (!radv_submit_has_effects(pSubmits
+ i
) && fence_idx
!= i
)
3769 VkPipelineStageFlags wait_dst_stage_mask
= 0;
3770 for (unsigned j
= 0; j
< pSubmits
[i
].waitSemaphoreCount
; ++j
) {
3771 wait_dst_stage_mask
|= pSubmits
[i
].pWaitDstStageMask
[j
];
3774 result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
3775 .cmd_buffers
= pSubmits
[i
].pCommandBuffers
,
3776 .cmd_buffer_count
= pSubmits
[i
].commandBufferCount
,
3777 .wait_dst_stage_mask
= wait_dst_stage_mask
,
3778 .flush_caches
= !flushed_caches
,
3779 .wait_semaphores
= pSubmits
[i
].pWaitSemaphores
,
3780 .wait_semaphore_count
= pSubmits
[i
].waitSemaphoreCount
,
3781 .signal_semaphores
= pSubmits
[i
].pSignalSemaphores
,
3782 .signal_semaphore_count
= pSubmits
[i
].signalSemaphoreCount
,
3783 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
3785 if (result
!= VK_SUCCESS
)
3788 flushed_caches
= true;
3791 if (fence
!= VK_NULL_HANDLE
&& !submitCount
) {
3792 result
= radv_signal_fence(queue
, fence
);
3793 if (result
!= VK_SUCCESS
)
3800 VkResult
radv_QueueWaitIdle(
3803 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
3805 queue
->device
->ws
->ctx_wait_idle(queue
->hw_ctx
,
3806 radv_queue_family_to_ring(queue
->queue_family_index
),
3811 VkResult
radv_DeviceWaitIdle(
3814 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3816 for (unsigned i
= 0; i
< RADV_MAX_QUEUE_FAMILIES
; i
++) {
3817 for (unsigned q
= 0; q
< device
->queue_count
[i
]; q
++) {
3818 radv_QueueWaitIdle(radv_queue_to_handle(&device
->queues
[i
][q
]));
3824 VkResult
radv_EnumerateInstanceExtensionProperties(
3825 const char* pLayerName
,
3826 uint32_t* pPropertyCount
,
3827 VkExtensionProperties
* pProperties
)
3829 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3831 for (int i
= 0; i
< RADV_INSTANCE_EXTENSION_COUNT
; i
++) {
3832 if (radv_supported_instance_extensions
.extensions
[i
]) {
3833 vk_outarray_append(&out
, prop
) {
3834 *prop
= radv_instance_extensions
[i
];
3839 return vk_outarray_status(&out
);
3842 VkResult
radv_EnumerateDeviceExtensionProperties(
3843 VkPhysicalDevice physicalDevice
,
3844 const char* pLayerName
,
3845 uint32_t* pPropertyCount
,
3846 VkExtensionProperties
* pProperties
)
3848 RADV_FROM_HANDLE(radv_physical_device
, device
, physicalDevice
);
3849 VK_OUTARRAY_MAKE(out
, pProperties
, pPropertyCount
);
3851 for (int i
= 0; i
< RADV_DEVICE_EXTENSION_COUNT
; i
++) {
3852 if (device
->supported_extensions
.extensions
[i
]) {
3853 vk_outarray_append(&out
, prop
) {
3854 *prop
= radv_device_extensions
[i
];
3859 return vk_outarray_status(&out
);
3862 PFN_vkVoidFunction
radv_GetInstanceProcAddr(
3863 VkInstance _instance
,
3866 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3867 bool unchecked
= instance
? instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3870 return radv_lookup_entrypoint_unchecked(pName
);
3872 return radv_lookup_entrypoint_checked(pName
,
3873 instance
? instance
->apiVersion
: 0,
3874 instance
? &instance
->enabled_extensions
: NULL
,
3879 /* The loader wants us to expose a second GetInstanceProcAddr function
3880 * to work around certain LD_PRELOAD issues seen in apps.
3883 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3884 VkInstance instance
,
3888 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetInstanceProcAddr(
3889 VkInstance instance
,
3892 return radv_GetInstanceProcAddr(instance
, pName
);
3896 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3897 VkInstance _instance
,
3901 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL
vk_icdGetPhysicalDeviceProcAddr(
3902 VkInstance _instance
,
3905 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
3907 return radv_lookup_physical_device_entrypoint_checked(pName
,
3908 instance
? instance
->apiVersion
: 0,
3909 instance
? &instance
->enabled_extensions
: NULL
);
3912 PFN_vkVoidFunction
radv_GetDeviceProcAddr(
3916 RADV_FROM_HANDLE(radv_device
, device
, _device
);
3917 bool unchecked
= device
? device
->instance
->debug_flags
& RADV_DEBUG_ALL_ENTRYPOINTS
: false;
3920 return radv_lookup_entrypoint_unchecked(pName
);
3922 return radv_lookup_entrypoint_checked(pName
,
3923 device
->instance
->apiVersion
,
3924 &device
->instance
->enabled_extensions
,
3925 &device
->enabled_extensions
);
3929 bool radv_get_memory_fd(struct radv_device
*device
,
3930 struct radv_device_memory
*memory
,
3933 struct radeon_bo_metadata metadata
;
3935 if (memory
->image
) {
3936 radv_init_metadata(device
, memory
->image
, &metadata
);
3937 device
->ws
->buffer_set_metadata(memory
->bo
, &metadata
);
3940 return device
->ws
->buffer_get_fd(device
->ws
, memory
->bo
,
3945 static void radv_free_memory(struct radv_device
*device
,
3946 const VkAllocationCallbacks
* pAllocator
,
3947 struct radv_device_memory
*mem
)
3952 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
3953 if (mem
->android_hardware_buffer
)
3954 AHardwareBuffer_release(mem
->android_hardware_buffer
);
3958 radv_bo_list_remove(device
, mem
->bo
);
3959 device
->ws
->buffer_destroy(mem
->bo
);
3963 vk_free2(&device
->alloc
, pAllocator
, mem
);
3966 static VkResult
radv_alloc_memory(struct radv_device
*device
,
3967 const VkMemoryAllocateInfo
* pAllocateInfo
,
3968 const VkAllocationCallbacks
* pAllocator
,
3969 VkDeviceMemory
* pMem
)
3971 struct radv_device_memory
*mem
;
3973 enum radeon_bo_domain domain
;
3975 enum radv_mem_type mem_type_index
= device
->physical_device
->mem_type_indices
[pAllocateInfo
->memoryTypeIndex
];
3977 assert(pAllocateInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO
);
3979 const VkImportMemoryFdInfoKHR
*import_info
=
3980 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_FD_INFO_KHR
);
3981 const VkMemoryDedicatedAllocateInfo
*dedicate_info
=
3982 vk_find_struct_const(pAllocateInfo
->pNext
, MEMORY_DEDICATED_ALLOCATE_INFO
);
3983 const VkExportMemoryAllocateInfo
*export_info
=
3984 vk_find_struct_const(pAllocateInfo
->pNext
, EXPORT_MEMORY_ALLOCATE_INFO
);
3985 const struct VkImportAndroidHardwareBufferInfoANDROID
*ahb_import_info
=
3986 vk_find_struct_const(pAllocateInfo
->pNext
,
3987 IMPORT_ANDROID_HARDWARE_BUFFER_INFO_ANDROID
);
3988 const VkImportMemoryHostPointerInfoEXT
*host_ptr_info
=
3989 vk_find_struct_const(pAllocateInfo
->pNext
, IMPORT_MEMORY_HOST_POINTER_INFO_EXT
);
3991 const struct wsi_memory_allocate_info
*wsi_info
=
3992 vk_find_struct_const(pAllocateInfo
->pNext
, WSI_MEMORY_ALLOCATE_INFO_MESA
);
3994 if (pAllocateInfo
->allocationSize
== 0 && !ahb_import_info
&&
3995 !(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
))) {
3996 /* Apparently, this is allowed */
3997 *pMem
= VK_NULL_HANDLE
;
4001 mem
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*mem
), 8,
4002 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4004 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4006 if (wsi_info
&& wsi_info
->implicit_sync
)
4007 flags
|= RADEON_FLAG_IMPLICIT_SYNC
;
4009 if (dedicate_info
) {
4010 mem
->image
= radv_image_from_handle(dedicate_info
->image
);
4011 mem
->buffer
= radv_buffer_from_handle(dedicate_info
->buffer
);
4017 float priority_float
= 0.5;
4018 const struct VkMemoryPriorityAllocateInfoEXT
*priority_ext
=
4019 vk_find_struct_const(pAllocateInfo
->pNext
,
4020 MEMORY_PRIORITY_ALLOCATE_INFO_EXT
);
4022 priority_float
= priority_ext
->priority
;
4024 unsigned priority
= MIN2(RADV_BO_PRIORITY_APPLICATION_MAX
- 1,
4025 (int)(priority_float
* RADV_BO_PRIORITY_APPLICATION_MAX
));
4027 mem
->user_ptr
= NULL
;
4030 #if RADV_SUPPORT_ANDROID_HARDWARE_BUFFER
4031 mem
->android_hardware_buffer
= NULL
;
4034 if (ahb_import_info
) {
4035 result
= radv_import_ahb_memory(device
, mem
, priority
, ahb_import_info
);
4036 if (result
!= VK_SUCCESS
)
4038 } else if(export_info
&& (export_info
->handleTypes
& VK_EXTERNAL_MEMORY_HANDLE_TYPE_ANDROID_HARDWARE_BUFFER_BIT_ANDROID
)) {
4039 result
= radv_create_ahb_memory(device
, mem
, priority
, pAllocateInfo
);
4040 if (result
!= VK_SUCCESS
)
4042 } else if (import_info
) {
4043 assert(import_info
->handleType
==
4044 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
4045 import_info
->handleType
==
4046 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
4047 mem
->bo
= device
->ws
->buffer_from_fd(device
->ws
, import_info
->fd
,
4050 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
4053 close(import_info
->fd
);
4055 } else if (host_ptr_info
) {
4056 assert(host_ptr_info
->handleType
== VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT
);
4057 assert(mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
);
4058 mem
->bo
= device
->ws
->buffer_from_ptr(device
->ws
, host_ptr_info
->pHostPointer
,
4059 pAllocateInfo
->allocationSize
,
4062 result
= VK_ERROR_INVALID_EXTERNAL_HANDLE
;
4065 mem
->user_ptr
= host_ptr_info
->pHostPointer
;
4068 uint64_t alloc_size
= align_u64(pAllocateInfo
->allocationSize
, 4096);
4069 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
||
4070 mem_type_index
== RADV_MEM_TYPE_GTT_CACHED
)
4071 domain
= RADEON_DOMAIN_GTT
;
4073 domain
= RADEON_DOMAIN_VRAM
;
4075 if (mem_type_index
== RADV_MEM_TYPE_VRAM
)
4076 flags
|= RADEON_FLAG_NO_CPU_ACCESS
;
4078 flags
|= RADEON_FLAG_CPU_ACCESS
;
4080 if (mem_type_index
== RADV_MEM_TYPE_GTT_WRITE_COMBINE
)
4081 flags
|= RADEON_FLAG_GTT_WC
;
4083 if (!dedicate_info
&& !import_info
&& (!export_info
|| !export_info
->handleTypes
)) {
4084 flags
|= RADEON_FLAG_NO_INTERPROCESS_SHARING
;
4085 if (device
->use_global_bo_list
) {
4086 flags
|= RADEON_FLAG_PREFER_LOCAL_BO
;
4090 mem
->bo
= device
->ws
->buffer_create(device
->ws
, alloc_size
, device
->physical_device
->rad_info
.max_alignment
,
4091 domain
, flags
, priority
);
4094 result
= VK_ERROR_OUT_OF_DEVICE_MEMORY
;
4097 mem
->type_index
= mem_type_index
;
4100 result
= radv_bo_list_add(device
, mem
->bo
);
4101 if (result
!= VK_SUCCESS
)
4104 *pMem
= radv_device_memory_to_handle(mem
);
4109 radv_free_memory(device
, pAllocator
,mem
);
4110 vk_free2(&device
->alloc
, pAllocator
, mem
);
4115 VkResult
radv_AllocateMemory(
4117 const VkMemoryAllocateInfo
* pAllocateInfo
,
4118 const VkAllocationCallbacks
* pAllocator
,
4119 VkDeviceMemory
* pMem
)
4121 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4122 return radv_alloc_memory(device
, pAllocateInfo
, pAllocator
, pMem
);
4125 void radv_FreeMemory(
4127 VkDeviceMemory _mem
,
4128 const VkAllocationCallbacks
* pAllocator
)
4130 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4131 RADV_FROM_HANDLE(radv_device_memory
, mem
, _mem
);
4133 radv_free_memory(device
, pAllocator
, mem
);
4136 VkResult
radv_MapMemory(
4138 VkDeviceMemory _memory
,
4139 VkDeviceSize offset
,
4141 VkMemoryMapFlags flags
,
4144 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4145 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
4153 *ppData
= mem
->user_ptr
;
4155 *ppData
= device
->ws
->buffer_map(mem
->bo
);
4162 return vk_error(device
->instance
, VK_ERROR_MEMORY_MAP_FAILED
);
4165 void radv_UnmapMemory(
4167 VkDeviceMemory _memory
)
4169 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4170 RADV_FROM_HANDLE(radv_device_memory
, mem
, _memory
);
4175 if (mem
->user_ptr
== NULL
)
4176 device
->ws
->buffer_unmap(mem
->bo
);
4179 VkResult
radv_FlushMappedMemoryRanges(
4181 uint32_t memoryRangeCount
,
4182 const VkMappedMemoryRange
* pMemoryRanges
)
4187 VkResult
radv_InvalidateMappedMemoryRanges(
4189 uint32_t memoryRangeCount
,
4190 const VkMappedMemoryRange
* pMemoryRanges
)
4195 void radv_GetBufferMemoryRequirements(
4198 VkMemoryRequirements
* pMemoryRequirements
)
4200 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4201 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4203 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
4205 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4206 pMemoryRequirements
->alignment
= 4096;
4208 pMemoryRequirements
->alignment
= 16;
4210 pMemoryRequirements
->size
= align64(buffer
->size
, pMemoryRequirements
->alignment
);
4213 void radv_GetBufferMemoryRequirements2(
4215 const VkBufferMemoryRequirementsInfo2
*pInfo
,
4216 VkMemoryRequirements2
*pMemoryRequirements
)
4218 radv_GetBufferMemoryRequirements(device
, pInfo
->buffer
,
4219 &pMemoryRequirements
->memoryRequirements
);
4220 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4221 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
4222 switch (ext
->sType
) {
4223 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
4224 VkMemoryDedicatedRequirements
*req
=
4225 (VkMemoryDedicatedRequirements
*) ext
;
4226 req
->requiresDedicatedAllocation
= buffer
->shareable
;
4227 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
4236 void radv_GetImageMemoryRequirements(
4239 VkMemoryRequirements
* pMemoryRequirements
)
4241 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4242 RADV_FROM_HANDLE(radv_image
, image
, _image
);
4244 pMemoryRequirements
->memoryTypeBits
= (1u << device
->physical_device
->memory_properties
.memoryTypeCount
) - 1;
4246 pMemoryRequirements
->size
= image
->size
;
4247 pMemoryRequirements
->alignment
= image
->alignment
;
4250 void radv_GetImageMemoryRequirements2(
4252 const VkImageMemoryRequirementsInfo2
*pInfo
,
4253 VkMemoryRequirements2
*pMemoryRequirements
)
4255 radv_GetImageMemoryRequirements(device
, pInfo
->image
,
4256 &pMemoryRequirements
->memoryRequirements
);
4258 RADV_FROM_HANDLE(radv_image
, image
, pInfo
->image
);
4260 vk_foreach_struct(ext
, pMemoryRequirements
->pNext
) {
4261 switch (ext
->sType
) {
4262 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS
: {
4263 VkMemoryDedicatedRequirements
*req
=
4264 (VkMemoryDedicatedRequirements
*) ext
;
4265 req
->requiresDedicatedAllocation
= image
->shareable
;
4266 req
->prefersDedicatedAllocation
= req
->requiresDedicatedAllocation
;
4275 void radv_GetImageSparseMemoryRequirements(
4278 uint32_t* pSparseMemoryRequirementCount
,
4279 VkSparseImageMemoryRequirements
* pSparseMemoryRequirements
)
4284 void radv_GetImageSparseMemoryRequirements2(
4286 const VkImageSparseMemoryRequirementsInfo2
*pInfo
,
4287 uint32_t* pSparseMemoryRequirementCount
,
4288 VkSparseImageMemoryRequirements2
*pSparseMemoryRequirements
)
4293 void radv_GetDeviceMemoryCommitment(
4295 VkDeviceMemory memory
,
4296 VkDeviceSize
* pCommittedMemoryInBytes
)
4298 *pCommittedMemoryInBytes
= 0;
4301 VkResult
radv_BindBufferMemory2(VkDevice device
,
4302 uint32_t bindInfoCount
,
4303 const VkBindBufferMemoryInfo
*pBindInfos
)
4305 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
4306 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
4307 RADV_FROM_HANDLE(radv_buffer
, buffer
, pBindInfos
[i
].buffer
);
4310 buffer
->bo
= mem
->bo
;
4311 buffer
->offset
= pBindInfos
[i
].memoryOffset
;
4319 VkResult
radv_BindBufferMemory(
4322 VkDeviceMemory memory
,
4323 VkDeviceSize memoryOffset
)
4325 const VkBindBufferMemoryInfo info
= {
4326 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
4329 .memoryOffset
= memoryOffset
4332 return radv_BindBufferMemory2(device
, 1, &info
);
4335 VkResult
radv_BindImageMemory2(VkDevice device
,
4336 uint32_t bindInfoCount
,
4337 const VkBindImageMemoryInfo
*pBindInfos
)
4339 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
4340 RADV_FROM_HANDLE(radv_device_memory
, mem
, pBindInfos
[i
].memory
);
4341 RADV_FROM_HANDLE(radv_image
, image
, pBindInfos
[i
].image
);
4344 image
->bo
= mem
->bo
;
4345 image
->offset
= pBindInfos
[i
].memoryOffset
;
4355 VkResult
radv_BindImageMemory(
4358 VkDeviceMemory memory
,
4359 VkDeviceSize memoryOffset
)
4361 const VkBindImageMemoryInfo info
= {
4362 .sType
= VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO
,
4365 .memoryOffset
= memoryOffset
4368 return radv_BindImageMemory2(device
, 1, &info
);
4371 static bool radv_sparse_bind_has_effects(const VkBindSparseInfo
*info
)
4373 return info
->bufferBindCount
||
4374 info
->imageOpaqueBindCount
||
4375 info
->imageBindCount
||
4376 info
->waitSemaphoreCount
||
4377 info
->signalSemaphoreCount
;
4380 VkResult
radv_QueueBindSparse(
4382 uint32_t bindInfoCount
,
4383 const VkBindSparseInfo
* pBindInfo
,
4386 RADV_FROM_HANDLE(radv_queue
, queue
, _queue
);
4388 uint32_t fence_idx
= 0;
4390 if (fence
!= VK_NULL_HANDLE
) {
4391 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
)
4392 if (radv_sparse_bind_has_effects(pBindInfo
+ i
))
4395 fence_idx
= UINT32_MAX
;
4397 for (uint32_t i
= 0; i
< bindInfoCount
; ++i
) {
4398 if (i
!= fence_idx
&& !radv_sparse_bind_has_effects(pBindInfo
+ i
))
4401 VkResult result
= radv_queue_submit(queue
, &(struct radv_queue_submission
) {
4402 .buffer_binds
= pBindInfo
[i
].pBufferBinds
,
4403 .buffer_bind_count
= pBindInfo
[i
].bufferBindCount
,
4404 .image_opaque_binds
= pBindInfo
[i
].pImageOpaqueBinds
,
4405 .image_opaque_bind_count
= pBindInfo
[i
].imageOpaqueBindCount
,
4406 .wait_semaphores
= pBindInfo
[i
].pWaitSemaphores
,
4407 .wait_semaphore_count
= pBindInfo
[i
].waitSemaphoreCount
,
4408 .signal_semaphores
= pBindInfo
[i
].pSignalSemaphores
,
4409 .signal_semaphore_count
= pBindInfo
[i
].signalSemaphoreCount
,
4410 .fence
= i
== fence_idx
? fence
: VK_NULL_HANDLE
,
4413 if (result
!= VK_SUCCESS
)
4417 if (fence
!= VK_NULL_HANDLE
&& !bindInfoCount
) {
4418 result
= radv_signal_fence(queue
, fence
);
4419 if (result
!= VK_SUCCESS
)
4426 VkResult
radv_CreateFence(
4428 const VkFenceCreateInfo
* pCreateInfo
,
4429 const VkAllocationCallbacks
* pAllocator
,
4432 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4433 const VkExportFenceCreateInfo
*export
=
4434 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_FENCE_CREATE_INFO
);
4435 VkExternalFenceHandleTypeFlags handleTypes
=
4436 export
? export
->handleTypes
: 0;
4438 struct radv_fence
*fence
= vk_alloc2(&device
->alloc
, pAllocator
,
4440 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4443 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4445 fence
->fence_wsi
= NULL
;
4446 fence
->temp_syncobj
= 0;
4447 if (device
->always_use_syncobj
|| handleTypes
) {
4448 int ret
= device
->ws
->create_syncobj(device
->ws
, &fence
->syncobj
);
4450 vk_free2(&device
->alloc
, pAllocator
, fence
);
4451 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4453 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
) {
4454 device
->ws
->signal_syncobj(device
->ws
, fence
->syncobj
);
4456 fence
->fence
= NULL
;
4458 fence
->fence
= device
->ws
->create_fence();
4459 if (!fence
->fence
) {
4460 vk_free2(&device
->alloc
, pAllocator
, fence
);
4461 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4464 if (pCreateInfo
->flags
& VK_FENCE_CREATE_SIGNALED_BIT
)
4465 device
->ws
->signal_fence(fence
->fence
);
4468 *pFence
= radv_fence_to_handle(fence
);
4473 void radv_DestroyFence(
4476 const VkAllocationCallbacks
* pAllocator
)
4478 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4479 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4484 if (fence
->temp_syncobj
)
4485 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4487 device
->ws
->destroy_syncobj(device
->ws
, fence
->syncobj
);
4489 device
->ws
->destroy_fence(fence
->fence
);
4490 if (fence
->fence_wsi
)
4491 fence
->fence_wsi
->destroy(fence
->fence_wsi
);
4492 vk_free2(&device
->alloc
, pAllocator
, fence
);
4496 uint64_t radv_get_current_time(void)
4499 clock_gettime(CLOCK_MONOTONIC
, &tv
);
4500 return tv
.tv_nsec
+ tv
.tv_sec
*1000000000ull;
4503 static uint64_t radv_get_absolute_timeout(uint64_t timeout
)
4505 uint64_t current_time
= radv_get_current_time();
4507 timeout
= MIN2(UINT64_MAX
- current_time
, timeout
);
4509 return current_time
+ timeout
;
4513 static bool radv_all_fences_plain_and_submitted(struct radv_device
*device
,
4514 uint32_t fenceCount
, const VkFence
*pFences
)
4516 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4517 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4518 if (fence
->fence
== NULL
|| fence
->syncobj
||
4519 fence
->temp_syncobj
|| fence
->fence_wsi
||
4520 (!device
->ws
->is_fence_waitable(fence
->fence
)))
4526 static bool radv_all_fences_syncobj(uint32_t fenceCount
, const VkFence
*pFences
)
4528 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4529 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4530 if (fence
->syncobj
== 0 && fence
->temp_syncobj
== 0)
4536 VkResult
radv_WaitForFences(
4538 uint32_t fenceCount
,
4539 const VkFence
* pFences
,
4543 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4544 timeout
= radv_get_absolute_timeout(timeout
);
4546 if (device
->always_use_syncobj
&&
4547 radv_all_fences_syncobj(fenceCount
, pFences
))
4549 uint32_t *handles
= malloc(sizeof(uint32_t) * fenceCount
);
4551 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4553 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4554 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4555 handles
[i
] = fence
->temp_syncobj
? fence
->temp_syncobj
: fence
->syncobj
;
4558 bool success
= device
->ws
->wait_syncobj(device
->ws
, handles
, fenceCount
, waitAll
, timeout
);
4561 return success
? VK_SUCCESS
: VK_TIMEOUT
;
4564 if (!waitAll
&& fenceCount
> 1) {
4565 /* Not doing this by default for waitAll, due to needing to allocate twice. */
4566 if (device
->physical_device
->rad_info
.drm_minor
>= 10 && radv_all_fences_plain_and_submitted(device
, fenceCount
, pFences
)) {
4567 uint32_t wait_count
= 0;
4568 struct radeon_winsys_fence
**fences
= malloc(sizeof(struct radeon_winsys_fence
*) * fenceCount
);
4570 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4572 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4573 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4575 if (device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0)) {
4580 fences
[wait_count
++] = fence
->fence
;
4583 bool success
= device
->ws
->fences_wait(device
->ws
, fences
, wait_count
,
4584 waitAll
, timeout
- radv_get_current_time());
4587 return success
? VK_SUCCESS
: VK_TIMEOUT
;
4590 while(radv_get_current_time() <= timeout
) {
4591 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4592 if (radv_GetFenceStatus(_device
, pFences
[i
]) == VK_SUCCESS
)
4599 for (uint32_t i
= 0; i
< fenceCount
; ++i
) {
4600 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4601 bool expired
= false;
4603 if (fence
->temp_syncobj
) {
4604 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, timeout
))
4609 if (fence
->syncobj
) {
4610 if (!device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, timeout
))
4616 if (!device
->ws
->is_fence_waitable(fence
->fence
)) {
4617 while(!device
->ws
->is_fence_waitable(fence
->fence
) &&
4618 radv_get_current_time() <= timeout
)
4622 expired
= device
->ws
->fence_wait(device
->ws
,
4629 if (fence
->fence_wsi
) {
4630 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, timeout
);
4631 if (result
!= VK_SUCCESS
)
4639 VkResult
radv_ResetFences(VkDevice _device
,
4640 uint32_t fenceCount
,
4641 const VkFence
*pFences
)
4643 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4645 for (unsigned i
= 0; i
< fenceCount
; ++i
) {
4646 RADV_FROM_HANDLE(radv_fence
, fence
, pFences
[i
]);
4648 device
->ws
->reset_fence(fence
->fence
);
4650 /* Per spec, we first restore the permanent payload, and then reset, so
4651 * having a temp syncobj should not skip resetting the permanent syncobj. */
4652 if (fence
->temp_syncobj
) {
4653 device
->ws
->destroy_syncobj(device
->ws
, fence
->temp_syncobj
);
4654 fence
->temp_syncobj
= 0;
4657 if (fence
->syncobj
) {
4658 device
->ws
->reset_syncobj(device
->ws
, fence
->syncobj
);
4665 VkResult
radv_GetFenceStatus(VkDevice _device
, VkFence _fence
)
4667 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4668 RADV_FROM_HANDLE(radv_fence
, fence
, _fence
);
4670 if (fence
->temp_syncobj
) {
4671 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->temp_syncobj
, 1, true, 0);
4672 return success
? VK_SUCCESS
: VK_NOT_READY
;
4675 if (fence
->syncobj
) {
4676 bool success
= device
->ws
->wait_syncobj(device
->ws
, &fence
->syncobj
, 1, true, 0);
4677 return success
? VK_SUCCESS
: VK_NOT_READY
;
4681 if (!device
->ws
->fence_wait(device
->ws
, fence
->fence
, false, 0))
4682 return VK_NOT_READY
;
4684 if (fence
->fence_wsi
) {
4685 VkResult result
= fence
->fence_wsi
->wait(fence
->fence_wsi
, 0);
4687 if (result
!= VK_SUCCESS
) {
4688 if (result
== VK_TIMEOUT
)
4689 return VK_NOT_READY
;
4697 // Queue semaphore functions
4699 VkResult
radv_CreateSemaphore(
4701 const VkSemaphoreCreateInfo
* pCreateInfo
,
4702 const VkAllocationCallbacks
* pAllocator
,
4703 VkSemaphore
* pSemaphore
)
4705 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4706 const VkExportSemaphoreCreateInfo
*export
=
4707 vk_find_struct_const(pCreateInfo
->pNext
, EXPORT_SEMAPHORE_CREATE_INFO
);
4708 VkExternalSemaphoreHandleTypeFlags handleTypes
=
4709 export
? export
->handleTypes
: 0;
4711 struct radv_semaphore
*sem
= vk_alloc2(&device
->alloc
, pAllocator
,
4713 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4715 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4717 sem
->temp_syncobj
= 0;
4718 /* create a syncobject if we are going to export this semaphore */
4719 if (device
->always_use_syncobj
|| handleTypes
) {
4720 assert (device
->physical_device
->rad_info
.has_syncobj
);
4721 int ret
= device
->ws
->create_syncobj(device
->ws
, &sem
->syncobj
);
4723 vk_free2(&device
->alloc
, pAllocator
, sem
);
4724 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4728 sem
->sem
= device
->ws
->create_sem(device
->ws
);
4730 vk_free2(&device
->alloc
, pAllocator
, sem
);
4731 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4736 *pSemaphore
= radv_semaphore_to_handle(sem
);
4740 void radv_DestroySemaphore(
4742 VkSemaphore _semaphore
,
4743 const VkAllocationCallbacks
* pAllocator
)
4745 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4746 RADV_FROM_HANDLE(radv_semaphore
, sem
, _semaphore
);
4751 device
->ws
->destroy_syncobj(device
->ws
, sem
->syncobj
);
4753 device
->ws
->destroy_sem(sem
->sem
);
4754 vk_free2(&device
->alloc
, pAllocator
, sem
);
4757 VkResult
radv_CreateEvent(
4759 const VkEventCreateInfo
* pCreateInfo
,
4760 const VkAllocationCallbacks
* pAllocator
,
4763 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4764 struct radv_event
*event
= vk_alloc2(&device
->alloc
, pAllocator
,
4766 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4769 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4771 event
->bo
= device
->ws
->buffer_create(device
->ws
, 8, 8,
4773 RADEON_FLAG_VA_UNCACHED
| RADEON_FLAG_CPU_ACCESS
| RADEON_FLAG_NO_INTERPROCESS_SHARING
,
4774 RADV_BO_PRIORITY_FENCE
);
4776 vk_free2(&device
->alloc
, pAllocator
, event
);
4777 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4780 event
->map
= (uint64_t*)device
->ws
->buffer_map(event
->bo
);
4782 *pEvent
= radv_event_to_handle(event
);
4787 void radv_DestroyEvent(
4790 const VkAllocationCallbacks
* pAllocator
)
4792 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4793 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4797 device
->ws
->buffer_destroy(event
->bo
);
4798 vk_free2(&device
->alloc
, pAllocator
, event
);
4801 VkResult
radv_GetEventStatus(
4805 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4807 if (*event
->map
== 1)
4808 return VK_EVENT_SET
;
4809 return VK_EVENT_RESET
;
4812 VkResult
radv_SetEvent(
4816 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4822 VkResult
radv_ResetEvent(
4826 RADV_FROM_HANDLE(radv_event
, event
, _event
);
4832 VkResult
radv_CreateBuffer(
4834 const VkBufferCreateInfo
* pCreateInfo
,
4835 const VkAllocationCallbacks
* pAllocator
,
4838 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4839 struct radv_buffer
*buffer
;
4841 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO
);
4843 buffer
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*buffer
), 8,
4844 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4846 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4848 buffer
->size
= pCreateInfo
->size
;
4849 buffer
->usage
= pCreateInfo
->usage
;
4852 buffer
->flags
= pCreateInfo
->flags
;
4854 buffer
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
4855 EXTERNAL_MEMORY_BUFFER_CREATE_INFO
) != NULL
;
4857 if (pCreateInfo
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
) {
4858 buffer
->bo
= device
->ws
->buffer_create(device
->ws
,
4859 align64(buffer
->size
, 4096),
4860 4096, 0, RADEON_FLAG_VIRTUAL
,
4861 RADV_BO_PRIORITY_VIRTUAL
);
4863 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4864 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
4868 *pBuffer
= radv_buffer_to_handle(buffer
);
4873 void radv_DestroyBuffer(
4876 const VkAllocationCallbacks
* pAllocator
)
4878 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4879 RADV_FROM_HANDLE(radv_buffer
, buffer
, _buffer
);
4884 if (buffer
->flags
& VK_BUFFER_CREATE_SPARSE_BINDING_BIT
)
4885 device
->ws
->buffer_destroy(buffer
->bo
);
4887 vk_free2(&device
->alloc
, pAllocator
, buffer
);
4890 VkDeviceAddress
radv_GetBufferDeviceAddressEXT(
4892 const VkBufferDeviceAddressInfoEXT
* pInfo
)
4894 RADV_FROM_HANDLE(radv_buffer
, buffer
, pInfo
->buffer
);
4895 return radv_buffer_get_va(buffer
->bo
) + buffer
->offset
;
4899 static inline unsigned
4900 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
4903 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
4905 return plane
->surface
.u
.legacy
.tiling_index
[level
];
4908 static uint32_t radv_surface_max_layer_count(struct radv_image_view
*iview
)
4910 return iview
->type
== VK_IMAGE_VIEW_TYPE_3D
? iview
->extent
.depth
: (iview
->base_layer
+ iview
->layer_count
);
4914 radv_init_dcc_control_reg(struct radv_device
*device
,
4915 struct radv_image_view
*iview
)
4917 unsigned max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_256B
;
4918 unsigned min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_32B
;
4919 unsigned max_compressed_block_size
;
4920 unsigned independent_128b_blocks
;
4921 unsigned independent_64b_blocks
;
4923 if (!radv_dcc_enabled(iview
->image
, iview
->base_mip
))
4926 if (!device
->physical_device
->rad_info
.has_dedicated_vram
) {
4927 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4928 * dGPU and 64 for APU because all of our APUs to date use
4929 * DIMMs which have a request granularity size of 64B while all
4930 * other chips have a 32B request size.
4932 min_compressed_block_size
= V_028C78_MIN_BLOCK_SIZE_64B
;
4935 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4936 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4937 independent_64b_blocks
= 0;
4938 independent_128b_blocks
= 1;
4940 independent_128b_blocks
= 0;
4942 if (iview
->image
->info
.samples
> 1) {
4943 if (iview
->image
->planes
[0].surface
.bpe
== 1)
4944 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4945 else if (iview
->image
->planes
[0].surface
.bpe
== 2)
4946 max_uncompressed_block_size
= V_028C78_MAX_BLOCK_SIZE_128B
;
4949 if (iview
->image
->usage
& (VK_IMAGE_USAGE_SAMPLED_BIT
|
4950 VK_IMAGE_USAGE_TRANSFER_SRC_BIT
|
4951 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT
)) {
4952 /* If this DCC image is potentially going to be used in texture
4953 * fetches, we need some special settings.
4955 independent_64b_blocks
= 1;
4956 max_compressed_block_size
= V_028C78_MAX_BLOCK_SIZE_64B
;
4958 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4959 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4960 * big as possible for better compression state.
4962 independent_64b_blocks
= 0;
4963 max_compressed_block_size
= max_uncompressed_block_size
;
4967 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size
) |
4968 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size
) |
4969 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size
) |
4970 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks
) |
4971 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks
);
4975 radv_initialise_color_surface(struct radv_device
*device
,
4976 struct radv_color_buffer_info
*cb
,
4977 struct radv_image_view
*iview
)
4979 const struct vk_format_description
*desc
;
4980 unsigned ntype
, format
, swap
, endian
;
4981 unsigned blend_clamp
= 0, blend_bypass
= 0;
4983 const struct radv_image_plane
*plane
= &iview
->image
->planes
[iview
->plane_id
];
4984 const struct radeon_surf
*surf
= &plane
->surface
;
4986 desc
= vk_format_description(iview
->vk_format
);
4988 memset(cb
, 0, sizeof(*cb
));
4990 /* Intensity is implemented as Red, so treat it that way. */
4991 cb
->cb_color_attrib
= S_028C74_FORCE_DST_ALPHA_1(desc
->swizzle
[3] == VK_SWIZZLE_1
);
4993 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ plane
->offset
;
4995 cb
->cb_color_base
= va
>> 8;
4997 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4998 struct gfx9_surf_meta_flags meta
;
4999 if (iview
->image
->dcc_offset
)
5000 meta
= surf
->u
.gfx9
.dcc
;
5002 meta
= surf
->u
.gfx9
.cmask
;
5004 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5005 cb
->cb_color_attrib3
|= S_028EE0_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
5006 S_028EE0_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
5007 S_028EE0_CMASK_PIPE_ALIGNED(surf
->u
.gfx9
.cmask
.pipe_aligned
) |
5008 S_028EE0_DCC_PIPE_ALIGNED(surf
->u
.gfx9
.dcc
.pipe_aligned
);
5010 cb
->cb_color_attrib
|= S_028C74_COLOR_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
5011 S_028C74_FMASK_SW_MODE(surf
->u
.gfx9
.fmask
.swizzle_mode
) |
5012 S_028C74_RB_ALIGNED(meta
.rb_aligned
) |
5013 S_028C74_PIPE_ALIGNED(meta
.pipe_aligned
);
5014 cb
->cb_mrt_epitch
= S_0287A0_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
5017 cb
->cb_color_base
+= surf
->u
.gfx9
.surf_offset
>> 8;
5018 cb
->cb_color_base
|= surf
->tile_swizzle
;
5020 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[iview
->base_mip
];
5021 unsigned pitch_tile_max
, slice_tile_max
, tile_mode_index
;
5023 cb
->cb_color_base
+= level_info
->offset
>> 8;
5024 if (level_info
->mode
== RADEON_SURF_MODE_2D
)
5025 cb
->cb_color_base
|= surf
->tile_swizzle
;
5027 pitch_tile_max
= level_info
->nblk_x
/ 8 - 1;
5028 slice_tile_max
= (level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1;
5029 tile_mode_index
= si_tile_mode_index(plane
, iview
->base_mip
, false);
5031 cb
->cb_color_pitch
= S_028C64_TILE_MAX(pitch_tile_max
);
5032 cb
->cb_color_slice
= S_028C68_TILE_MAX(slice_tile_max
);
5033 cb
->cb_color_cmask_slice
= surf
->u
.legacy
.cmask_slice_tile_max
;
5035 cb
->cb_color_attrib
|= S_028C74_TILE_MODE_INDEX(tile_mode_index
);
5037 if (radv_image_has_fmask(iview
->image
)) {
5038 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
5039 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(surf
->u
.legacy
.fmask
.pitch_in_pixels
/ 8 - 1);
5040 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(surf
->u
.legacy
.fmask
.tiling_index
);
5041 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(surf
->u
.legacy
.fmask
.slice_tile_max
);
5043 /* This must be set for fast clear to work without FMASK. */
5044 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
)
5045 cb
->cb_color_pitch
|= S_028C64_FMASK_TILE_MAX(pitch_tile_max
);
5046 cb
->cb_color_attrib
|= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index
);
5047 cb
->cb_color_fmask_slice
= S_028C88_TILE_MAX(slice_tile_max
);
5051 /* CMASK variables */
5052 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
5053 va
+= iview
->image
->cmask_offset
;
5054 cb
->cb_color_cmask
= va
>> 8;
5056 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
5057 va
+= iview
->image
->dcc_offset
;
5059 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
) &&
5060 device
->physical_device
->rad_info
.chip_class
<= GFX8
)
5061 va
+= plane
->surface
.u
.legacy
.level
[iview
->base_mip
].dcc_offset
;
5063 unsigned dcc_tile_swizzle
= surf
->tile_swizzle
;
5064 dcc_tile_swizzle
&= (surf
->dcc_alignment
- 1) >> 8;
5066 cb
->cb_dcc_base
= va
>> 8;
5067 cb
->cb_dcc_base
|= dcc_tile_swizzle
;
5069 /* GFX10 field has the same base shift as the GFX6 field. */
5070 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
5071 cb
->cb_color_view
= S_028C6C_SLICE_START(iview
->base_layer
) |
5072 S_028C6C_SLICE_MAX_GFX10(max_slice
);
5074 if (iview
->image
->info
.samples
> 1) {
5075 unsigned log_samples
= util_logbase2(iview
->image
->info
.samples
);
5077 cb
->cb_color_attrib
|= S_028C74_NUM_SAMPLES(log_samples
) |
5078 S_028C74_NUM_FRAGMENTS(log_samples
);
5081 if (radv_image_has_fmask(iview
->image
)) {
5082 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+ iview
->image
->fmask_offset
;
5083 cb
->cb_color_fmask
= va
>> 8;
5084 cb
->cb_color_fmask
|= surf
->fmask_tile_swizzle
;
5086 cb
->cb_color_fmask
= cb
->cb_color_base
;
5089 ntype
= radv_translate_color_numformat(iview
->vk_format
,
5091 vk_format_get_first_non_void_channel(iview
->vk_format
));
5092 format
= radv_translate_colorformat(iview
->vk_format
);
5093 if (format
== V_028C70_COLOR_INVALID
|| ntype
== ~0u)
5094 radv_finishme("Illegal color\n");
5095 swap
= radv_translate_colorswap(iview
->vk_format
, false);
5096 endian
= radv_colorformat_endian_swap(format
);
5098 /* blend clamp should be set for all NORM/SRGB types */
5099 if (ntype
== V_028C70_NUMBER_UNORM
||
5100 ntype
== V_028C70_NUMBER_SNORM
||
5101 ntype
== V_028C70_NUMBER_SRGB
)
5104 /* set blend bypass according to docs if SINT/UINT or
5105 8/24 COLOR variants */
5106 if (ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
||
5107 format
== V_028C70_COLOR_8_24
|| format
== V_028C70_COLOR_24_8
||
5108 format
== V_028C70_COLOR_X24_8_32_FLOAT
) {
5113 if ((ntype
== V_028C70_NUMBER_UINT
|| ntype
== V_028C70_NUMBER_SINT
) &&
5114 (format
== V_028C70_COLOR_8
||
5115 format
== V_028C70_COLOR_8_8
||
5116 format
== V_028C70_COLOR_8_8_8_8
))
5117 ->color_is_int8
= true;
5119 cb
->cb_color_info
= S_028C70_FORMAT(format
) |
5120 S_028C70_COMP_SWAP(swap
) |
5121 S_028C70_BLEND_CLAMP(blend_clamp
) |
5122 S_028C70_BLEND_BYPASS(blend_bypass
) |
5123 S_028C70_SIMPLE_FLOAT(1) |
5124 S_028C70_ROUND_MODE(ntype
!= V_028C70_NUMBER_UNORM
&&
5125 ntype
!= V_028C70_NUMBER_SNORM
&&
5126 ntype
!= V_028C70_NUMBER_SRGB
&&
5127 format
!= V_028C70_COLOR_8_24
&&
5128 format
!= V_028C70_COLOR_24_8
) |
5129 S_028C70_NUMBER_TYPE(ntype
) |
5130 S_028C70_ENDIAN(endian
);
5131 if (radv_image_has_fmask(iview
->image
)) {
5132 cb
->cb_color_info
|= S_028C70_COMPRESSION(1);
5133 if (device
->physical_device
->rad_info
.chip_class
== GFX6
) {
5134 unsigned fmask_bankh
= util_logbase2(surf
->u
.legacy
.fmask
.bankh
);
5135 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh
);
5138 if (radv_image_is_tc_compat_cmask(iview
->image
)) {
5139 /* Allow the texture block to read FMASK directly
5140 * without decompressing it. This bit must be cleared
5141 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
5142 * otherwise the operation doesn't happen.
5144 cb
->cb_color_info
|= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
5146 /* Set CMASK into a tiling format that allows the
5147 * texture block to read it.
5149 cb
->cb_color_info
|= S_028C70_CMASK_ADDR_TYPE(2);
5153 if (radv_image_has_cmask(iview
->image
) &&
5154 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_FAST_CLEARS
))
5155 cb
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
5157 if (radv_dcc_enabled(iview
->image
, iview
->base_mip
))
5158 cb
->cb_color_info
|= S_028C70_DCC_ENABLE(1);
5160 cb
->cb_dcc_control
= radv_init_dcc_control_reg(device
, iview
);
5162 /* This must be set for fast clear to work without FMASK. */
5163 if (!radv_image_has_fmask(iview
->image
) &&
5164 device
->physical_device
->rad_info
.chip_class
== GFX6
) {
5165 unsigned bankh
= util_logbase2(surf
->u
.legacy
.bankh
);
5166 cb
->cb_color_attrib
|= S_028C74_FMASK_BANK_HEIGHT(bankh
);
5169 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
5170 const struct vk_format_description
*format_desc
= vk_format_description(iview
->image
->vk_format
);
5172 unsigned mip0_depth
= iview
->image
->type
== VK_IMAGE_TYPE_3D
?
5173 (iview
->extent
.depth
- 1) : (iview
->image
->info
.array_size
- 1);
5174 unsigned width
= iview
->extent
.width
/ (iview
->plane_id
? format_desc
->width_divisor
: 1);
5175 unsigned height
= iview
->extent
.height
/ (iview
->plane_id
? format_desc
->height_divisor
: 1);
5177 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5178 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX10(iview
->base_mip
);
5180 cb
->cb_color_attrib3
|= S_028EE0_MIP0_DEPTH(mip0_depth
) |
5181 S_028EE0_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
) |
5182 S_028EE0_RESOURCE_LEVEL(1);
5184 cb
->cb_color_view
|= S_028C6C_MIP_LEVEL_GFX9(iview
->base_mip
);
5185 cb
->cb_color_attrib
|= S_028C74_MIP0_DEPTH(mip0_depth
) |
5186 S_028C74_RESOURCE_TYPE(surf
->u
.gfx9
.resource_type
);
5189 cb
->cb_color_attrib2
= S_028C68_MIP0_WIDTH(width
- 1) |
5190 S_028C68_MIP0_HEIGHT(height
- 1) |
5191 S_028C68_MAX_MIP(iview
->image
->info
.levels
- 1);
5196 radv_calc_decompress_on_z_planes(struct radv_device
*device
,
5197 struct radv_image_view
*iview
)
5199 unsigned max_zplanes
= 0;
5201 assert(radv_image_is_tc_compat_htile(iview
->image
));
5203 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
5204 /* Default value for 32-bit depth surfaces. */
5207 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
&&
5208 iview
->image
->info
.samples
> 1)
5211 max_zplanes
= max_zplanes
+ 1;
5213 if (iview
->vk_format
== VK_FORMAT_D16_UNORM
) {
5214 /* Do not enable Z plane compression for 16-bit depth
5215 * surfaces because isn't supported on GFX8. Only
5216 * 32-bit depth surfaces are supported by the hardware.
5217 * This allows to maintain shader compatibility and to
5218 * reduce the number of depth decompressions.
5222 if (iview
->image
->info
.samples
<= 1)
5224 else if (iview
->image
->info
.samples
<= 4)
5235 radv_initialise_ds_surface(struct radv_device
*device
,
5236 struct radv_ds_buffer_info
*ds
,
5237 struct radv_image_view
*iview
)
5239 unsigned level
= iview
->base_mip
;
5240 unsigned format
, stencil_format
;
5241 uint64_t va
, s_offs
, z_offs
;
5242 bool stencil_only
= false;
5243 const struct radv_image_plane
*plane
= &iview
->image
->planes
[0];
5244 const struct radeon_surf
*surf
= &plane
->surface
;
5246 assert(vk_format_get_plane_count(iview
->image
->vk_format
) == 1);
5248 memset(ds
, 0, sizeof(*ds
));
5249 switch (iview
->image
->vk_format
) {
5250 case VK_FORMAT_D24_UNORM_S8_UINT
:
5251 case VK_FORMAT_X8_D24_UNORM_PACK32
:
5252 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
5253 ds
->offset_scale
= 2.0f
;
5255 case VK_FORMAT_D16_UNORM
:
5256 case VK_FORMAT_D16_UNORM_S8_UINT
:
5257 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
5258 ds
->offset_scale
= 4.0f
;
5260 case VK_FORMAT_D32_SFLOAT
:
5261 case VK_FORMAT_D32_SFLOAT_S8_UINT
:
5262 ds
->pa_su_poly_offset_db_fmt_cntl
= S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
5263 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
5264 ds
->offset_scale
= 1.0f
;
5266 case VK_FORMAT_S8_UINT
:
5267 stencil_only
= true;
5273 format
= radv_translate_dbformat(iview
->image
->vk_format
);
5274 stencil_format
= surf
->has_stencil
?
5275 V_028044_STENCIL_8
: V_028044_STENCIL_INVALID
;
5277 uint32_t max_slice
= radv_surface_max_layer_count(iview
) - 1;
5278 ds
->db_depth_view
= S_028008_SLICE_START(iview
->base_layer
) |
5279 S_028008_SLICE_MAX(max_slice
);
5280 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5281 ds
->db_depth_view
|= S_028008_SLICE_START_HI(iview
->base_layer
>> 11) |
5282 S_028008_SLICE_MAX_HI(max_slice
>> 11);
5285 ds
->db_htile_data_base
= 0;
5286 ds
->db_htile_surface
= 0;
5288 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
;
5289 s_offs
= z_offs
= va
;
5291 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
5292 assert(surf
->u
.gfx9
.surf_offset
== 0);
5293 s_offs
+= surf
->u
.gfx9
.stencil_offset
;
5295 ds
->db_z_info
= S_028038_FORMAT(format
) |
5296 S_028038_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
)) |
5297 S_028038_SW_MODE(surf
->u
.gfx9
.surf
.swizzle_mode
) |
5298 S_028038_MAXMIP(iview
->image
->info
.levels
- 1) |
5299 S_028038_ZRANGE_PRECISION(1);
5300 ds
->db_stencil_info
= S_02803C_FORMAT(stencil_format
) |
5301 S_02803C_SW_MODE(surf
->u
.gfx9
.stencil
.swizzle_mode
);
5303 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
5304 ds
->db_z_info2
= S_028068_EPITCH(surf
->u
.gfx9
.surf
.epitch
);
5305 ds
->db_stencil_info2
= S_02806C_EPITCH(surf
->u
.gfx9
.stencil
.epitch
);
5308 ds
->db_depth_view
|= S_028008_MIPID(level
);
5309 ds
->db_depth_size
= S_02801C_X_MAX(iview
->image
->info
.width
- 1) |
5310 S_02801C_Y_MAX(iview
->image
->info
.height
- 1);
5312 if (radv_htile_enabled(iview
->image
, level
)) {
5313 ds
->db_z_info
|= S_028038_TILE_SURFACE_ENABLE(1);
5315 if (radv_image_is_tc_compat_htile(iview
->image
)) {
5316 unsigned max_zplanes
=
5317 radv_calc_decompress_on_z_planes(device
, iview
);
5319 ds
->db_z_info
|= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
5321 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5322 ds
->db_z_info
|= S_028040_ITERATE_FLUSH(1);
5323 ds
->db_stencil_info
|= S_028044_ITERATE_FLUSH(1);
5325 ds
->db_z_info
|= S_028038_ITERATE_FLUSH(1);
5326 ds
->db_stencil_info
|= S_02803C_ITERATE_FLUSH(1);
5330 if (!surf
->has_stencil
)
5331 /* Use all of the htile_buffer for depth if there's no stencil. */
5332 ds
->db_stencil_info
|= S_02803C_TILE_STENCIL_DISABLE(1);
5333 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
5334 iview
->image
->htile_offset
;
5335 ds
->db_htile_data_base
= va
>> 8;
5336 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1) |
5337 S_028ABC_PIPE_ALIGNED(surf
->u
.gfx9
.htile
.pipe_aligned
);
5339 if (device
->physical_device
->rad_info
.chip_class
== GFX9
) {
5340 ds
->db_htile_surface
|= S_028ABC_RB_ALIGNED(surf
->u
.gfx9
.htile
.rb_aligned
);
5344 const struct legacy_surf_level
*level_info
= &surf
->u
.legacy
.level
[level
];
5347 level_info
= &surf
->u
.legacy
.stencil_level
[level
];
5349 z_offs
+= surf
->u
.legacy
.level
[level
].offset
;
5350 s_offs
+= surf
->u
.legacy
.stencil_level
[level
].offset
;
5352 ds
->db_depth_info
= S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview
->image
));
5353 ds
->db_z_info
= S_028040_FORMAT(format
) | S_028040_ZRANGE_PRECISION(1);
5354 ds
->db_stencil_info
= S_028044_FORMAT(stencil_format
);
5356 if (iview
->image
->info
.samples
> 1)
5357 ds
->db_z_info
|= S_028040_NUM_SAMPLES(util_logbase2(iview
->image
->info
.samples
));
5359 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
5360 struct radeon_info
*info
= &device
->physical_device
->rad_info
;
5361 unsigned tiling_index
= surf
->u
.legacy
.tiling_index
[level
];
5362 unsigned stencil_index
= surf
->u
.legacy
.stencil_tiling_index
[level
];
5363 unsigned macro_index
= surf
->u
.legacy
.macro_tile_index
;
5364 unsigned tile_mode
= info
->si_tile_mode_array
[tiling_index
];
5365 unsigned stencil_tile_mode
= info
->si_tile_mode_array
[stencil_index
];
5366 unsigned macro_mode
= info
->cik_macrotile_mode_array
[macro_index
];
5369 tile_mode
= stencil_tile_mode
;
5371 ds
->db_depth_info
|=
5372 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode
)) |
5373 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode
)) |
5374 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode
)) |
5375 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode
)) |
5376 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode
)) |
5377 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode
));
5378 ds
->db_z_info
|= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode
));
5379 ds
->db_stencil_info
|= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode
));
5381 unsigned tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, false);
5382 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
5383 tile_mode_index
= si_tile_mode_index(&iview
->image
->planes
[0], level
, true);
5384 ds
->db_stencil_info
|= S_028044_TILE_MODE_INDEX(tile_mode_index
);
5386 ds
->db_z_info
|= S_028040_TILE_MODE_INDEX(tile_mode_index
);
5389 ds
->db_depth_size
= S_028058_PITCH_TILE_MAX((level_info
->nblk_x
/ 8) - 1) |
5390 S_028058_HEIGHT_TILE_MAX((level_info
->nblk_y
/ 8) - 1);
5391 ds
->db_depth_slice
= S_02805C_SLICE_TILE_MAX((level_info
->nblk_x
* level_info
->nblk_y
) / 64 - 1);
5393 if (radv_htile_enabled(iview
->image
, level
)) {
5394 ds
->db_z_info
|= S_028040_TILE_SURFACE_ENABLE(1);
5396 if (!surf
->has_stencil
&&
5397 !radv_image_is_tc_compat_htile(iview
->image
))
5398 /* Use all of the htile_buffer for depth if there's no stencil. */
5399 ds
->db_stencil_info
|= S_028044_TILE_STENCIL_DISABLE(1);
5401 va
= radv_buffer_get_va(iview
->bo
) + iview
->image
->offset
+
5402 iview
->image
->htile_offset
;
5403 ds
->db_htile_data_base
= va
>> 8;
5404 ds
->db_htile_surface
= S_028ABC_FULL_CACHE(1);
5406 if (radv_image_is_tc_compat_htile(iview
->image
)) {
5407 unsigned max_zplanes
=
5408 radv_calc_decompress_on_z_planes(device
, iview
);
5410 ds
->db_htile_surface
|= S_028ABC_TC_COMPATIBLE(1);
5411 ds
->db_z_info
|= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes
);
5416 ds
->db_z_read_base
= ds
->db_z_write_base
= z_offs
>> 8;
5417 ds
->db_stencil_read_base
= ds
->db_stencil_write_base
= s_offs
>> 8;
5420 VkResult
radv_CreateFramebuffer(
5422 const VkFramebufferCreateInfo
* pCreateInfo
,
5423 const VkAllocationCallbacks
* pAllocator
,
5424 VkFramebuffer
* pFramebuffer
)
5426 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5427 struct radv_framebuffer
*framebuffer
;
5428 const VkFramebufferAttachmentsCreateInfoKHR
*imageless_create_info
=
5429 vk_find_struct_const(pCreateInfo
->pNext
,
5430 FRAMEBUFFER_ATTACHMENTS_CREATE_INFO_KHR
);
5432 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
);
5434 size_t size
= sizeof(*framebuffer
);
5435 if (!imageless_create_info
)
5436 size
+= sizeof(struct radv_image_view
*) * pCreateInfo
->attachmentCount
;
5437 framebuffer
= vk_alloc2(&device
->alloc
, pAllocator
, size
, 8,
5438 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5439 if (framebuffer
== NULL
)
5440 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5442 framebuffer
->attachment_count
= pCreateInfo
->attachmentCount
;
5443 framebuffer
->width
= pCreateInfo
->width
;
5444 framebuffer
->height
= pCreateInfo
->height
;
5445 framebuffer
->layers
= pCreateInfo
->layers
;
5446 if (imageless_create_info
) {
5447 for (unsigned i
= 0; i
< imageless_create_info
->attachmentImageInfoCount
; ++i
) {
5448 const VkFramebufferAttachmentImageInfoKHR
*attachment
=
5449 imageless_create_info
->pAttachmentImageInfos
+ i
;
5450 framebuffer
->width
= MIN2(framebuffer
->width
, attachment
->width
);
5451 framebuffer
->height
= MIN2(framebuffer
->height
, attachment
->height
);
5452 framebuffer
->layers
= MIN2(framebuffer
->layers
, attachment
->layerCount
);
5455 for (uint32_t i
= 0; i
< pCreateInfo
->attachmentCount
; i
++) {
5456 VkImageView _iview
= pCreateInfo
->pAttachments
[i
];
5457 struct radv_image_view
*iview
= radv_image_view_from_handle(_iview
);
5458 framebuffer
->attachments
[i
] = iview
;
5459 framebuffer
->width
= MIN2(framebuffer
->width
, iview
->extent
.width
);
5460 framebuffer
->height
= MIN2(framebuffer
->height
, iview
->extent
.height
);
5461 framebuffer
->layers
= MIN2(framebuffer
->layers
, radv_surface_max_layer_count(iview
));
5465 *pFramebuffer
= radv_framebuffer_to_handle(framebuffer
);
5469 void radv_DestroyFramebuffer(
5472 const VkAllocationCallbacks
* pAllocator
)
5474 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5475 RADV_FROM_HANDLE(radv_framebuffer
, fb
, _fb
);
5479 vk_free2(&device
->alloc
, pAllocator
, fb
);
5482 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode
)
5484 switch (address_mode
) {
5485 case VK_SAMPLER_ADDRESS_MODE_REPEAT
:
5486 return V_008F30_SQ_TEX_WRAP
;
5487 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT
:
5488 return V_008F30_SQ_TEX_MIRROR
;
5489 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
:
5490 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL
;
5491 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER
:
5492 return V_008F30_SQ_TEX_CLAMP_BORDER
;
5493 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE
:
5494 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL
;
5496 unreachable("illegal tex wrap mode");
5502 radv_tex_compare(VkCompareOp op
)
5505 case VK_COMPARE_OP_NEVER
:
5506 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER
;
5507 case VK_COMPARE_OP_LESS
:
5508 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS
;
5509 case VK_COMPARE_OP_EQUAL
:
5510 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL
;
5511 case VK_COMPARE_OP_LESS_OR_EQUAL
:
5512 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL
;
5513 case VK_COMPARE_OP_GREATER
:
5514 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER
;
5515 case VK_COMPARE_OP_NOT_EQUAL
:
5516 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL
;
5517 case VK_COMPARE_OP_GREATER_OR_EQUAL
:
5518 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL
;
5519 case VK_COMPARE_OP_ALWAYS
:
5520 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS
;
5522 unreachable("illegal compare mode");
5528 radv_tex_filter(VkFilter filter
, unsigned max_ansio
)
5531 case VK_FILTER_NEAREST
:
5532 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT
:
5533 V_008F38_SQ_TEX_XY_FILTER_POINT
);
5534 case VK_FILTER_LINEAR
:
5535 return (max_ansio
> 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR
:
5536 V_008F38_SQ_TEX_XY_FILTER_BILINEAR
);
5537 case VK_FILTER_CUBIC_IMG
:
5539 fprintf(stderr
, "illegal texture filter");
5545 radv_tex_mipfilter(VkSamplerMipmapMode mode
)
5548 case VK_SAMPLER_MIPMAP_MODE_NEAREST
:
5549 return V_008F38_SQ_TEX_Z_FILTER_POINT
;
5550 case VK_SAMPLER_MIPMAP_MODE_LINEAR
:
5551 return V_008F38_SQ_TEX_Z_FILTER_LINEAR
;
5553 return V_008F38_SQ_TEX_Z_FILTER_NONE
;
5558 radv_tex_bordercolor(VkBorderColor bcolor
)
5561 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK
:
5562 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK
:
5563 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK
;
5564 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK
:
5565 case VK_BORDER_COLOR_INT_OPAQUE_BLACK
:
5566 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK
;
5567 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE
:
5568 case VK_BORDER_COLOR_INT_OPAQUE_WHITE
:
5569 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE
;
5577 radv_tex_aniso_filter(unsigned filter
)
5591 radv_tex_filter_mode(VkSamplerReductionModeEXT mode
)
5594 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT
:
5595 return V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5596 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT
:
5597 return V_008F30_SQ_IMG_FILTER_MODE_MIN
;
5598 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT
:
5599 return V_008F30_SQ_IMG_FILTER_MODE_MAX
;
5607 radv_get_max_anisotropy(struct radv_device
*device
,
5608 const VkSamplerCreateInfo
*pCreateInfo
)
5610 if (device
->force_aniso
>= 0)
5611 return device
->force_aniso
;
5613 if (pCreateInfo
->anisotropyEnable
&&
5614 pCreateInfo
->maxAnisotropy
> 1.0f
)
5615 return (uint32_t)pCreateInfo
->maxAnisotropy
;
5621 radv_init_sampler(struct radv_device
*device
,
5622 struct radv_sampler
*sampler
,
5623 const VkSamplerCreateInfo
*pCreateInfo
)
5625 uint32_t max_aniso
= radv_get_max_anisotropy(device
, pCreateInfo
);
5626 uint32_t max_aniso_ratio
= radv_tex_aniso_filter(max_aniso
);
5627 bool compat_mode
= device
->physical_device
->rad_info
.chip_class
== GFX8
||
5628 device
->physical_device
->rad_info
.chip_class
== GFX9
;
5629 unsigned filter_mode
= V_008F30_SQ_IMG_FILTER_MODE_BLEND
;
5631 const struct VkSamplerReductionModeCreateInfoEXT
*sampler_reduction
=
5632 vk_find_struct_const(pCreateInfo
->pNext
,
5633 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT
);
5634 if (sampler_reduction
)
5635 filter_mode
= radv_tex_filter_mode(sampler_reduction
->reductionMode
);
5637 sampler
->state
[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo
->addressModeU
)) |
5638 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo
->addressModeV
)) |
5639 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo
->addressModeW
)) |
5640 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio
) |
5641 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo
->compareOp
)) |
5642 S_008F30_FORCE_UNNORMALIZED(pCreateInfo
->unnormalizedCoordinates
? 1 : 0) |
5643 S_008F30_ANISO_THRESHOLD(max_aniso_ratio
>> 1) |
5644 S_008F30_ANISO_BIAS(max_aniso_ratio
) |
5645 S_008F30_DISABLE_CUBE_WRAP(0) |
5646 S_008F30_COMPAT_MODE(compat_mode
) |
5647 S_008F30_FILTER_MODE(filter_mode
));
5648 sampler
->state
[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo
->minLod
, 0, 15), 8)) |
5649 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo
->maxLod
, 0, 15), 8)) |
5650 S_008F34_PERF_MIP(max_aniso_ratio
? max_aniso_ratio
+ 6 : 0));
5651 sampler
->state
[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo
->mipLodBias
, -16, 16), 8)) |
5652 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo
->magFilter
, max_aniso
)) |
5653 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo
->minFilter
, max_aniso
)) |
5654 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo
->mipmapMode
)) |
5655 S_008F38_MIP_POINT_PRECLAMP(0));
5656 sampler
->state
[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5657 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo
->borderColor
)));
5659 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5660 sampler
->state
[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5662 sampler
->state
[2] |=
5663 S_008F38_DISABLE_LSB_CEIL(device
->physical_device
->rad_info
.chip_class
<= GFX8
) |
5664 S_008F38_FILTER_PREC_FIX(1) |
5665 S_008F38_ANISO_OVERRIDE_GFX6(device
->physical_device
->rad_info
.chip_class
>= GFX8
);
5669 VkResult
radv_CreateSampler(
5671 const VkSamplerCreateInfo
* pCreateInfo
,
5672 const VkAllocationCallbacks
* pAllocator
,
5673 VkSampler
* pSampler
)
5675 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5676 struct radv_sampler
*sampler
;
5678 const struct VkSamplerYcbcrConversionInfo
*ycbcr_conversion
=
5679 vk_find_struct_const(pCreateInfo
->pNext
,
5680 SAMPLER_YCBCR_CONVERSION_INFO
);
5682 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
);
5684 sampler
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*sampler
), 8,
5685 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5687 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5689 radv_init_sampler(device
, sampler
, pCreateInfo
);
5691 sampler
->ycbcr_sampler
= ycbcr_conversion
? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion
->conversion
): NULL
;
5692 *pSampler
= radv_sampler_to_handle(sampler
);
5697 void radv_DestroySampler(
5700 const VkAllocationCallbacks
* pAllocator
)
5702 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5703 RADV_FROM_HANDLE(radv_sampler
, sampler
, _sampler
);
5707 vk_free2(&device
->alloc
, pAllocator
, sampler
);
5710 /* vk_icd.h does not declare this function, so we declare it here to
5711 * suppress Wmissing-prototypes.
5713 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5714 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
);
5716 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5717 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion
)
5719 /* For the full details on loader interface versioning, see
5720 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5721 * What follows is a condensed summary, to help you navigate the large and
5722 * confusing official doc.
5724 * - Loader interface v0 is incompatible with later versions. We don't
5727 * - In loader interface v1:
5728 * - The first ICD entrypoint called by the loader is
5729 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5731 * - The ICD must statically expose no other Vulkan symbol unless it is
5732 * linked with -Bsymbolic.
5733 * - Each dispatchable Vulkan handle created by the ICD must be
5734 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5735 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5736 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5737 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5738 * such loader-managed surfaces.
5740 * - Loader interface v2 differs from v1 in:
5741 * - The first ICD entrypoint called by the loader is
5742 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5743 * statically expose this entrypoint.
5745 * - Loader interface v3 differs from v2 in:
5746 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5747 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5748 * because the loader no longer does so.
5750 *pSupportedVersion
= MIN2(*pSupportedVersion
, 4u);
5754 VkResult
radv_GetMemoryFdKHR(VkDevice _device
,
5755 const VkMemoryGetFdInfoKHR
*pGetFdInfo
,
5758 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5759 RADV_FROM_HANDLE(radv_device_memory
, memory
, pGetFdInfo
->memory
);
5761 assert(pGetFdInfo
->sType
== VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR
);
5763 /* At the moment, we support only the below handle types. */
5764 assert(pGetFdInfo
->handleType
==
5765 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT
||
5766 pGetFdInfo
->handleType
==
5767 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
);
5769 bool ret
= radv_get_memory_fd(device
, memory
, pFD
);
5771 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
5775 VkResult
radv_GetMemoryFdPropertiesKHR(VkDevice _device
,
5776 VkExternalMemoryHandleTypeFlagBits handleType
,
5778 VkMemoryFdPropertiesKHR
*pMemoryFdProperties
)
5780 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5782 switch (handleType
) {
5783 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT
:
5784 pMemoryFdProperties
->memoryTypeBits
= (1 << RADV_MEM_TYPE_COUNT
) - 1;
5788 /* The valid usage section for this function says:
5790 * "handleType must not be one of the handle types defined as
5793 * So opaque handle types fall into the default "unsupported" case.
5795 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5799 static VkResult
radv_import_opaque_fd(struct radv_device
*device
,
5803 uint32_t syncobj_handle
= 0;
5804 int ret
= device
->ws
->import_syncobj(device
->ws
, fd
, &syncobj_handle
);
5806 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5809 device
->ws
->destroy_syncobj(device
->ws
, *syncobj
);
5811 *syncobj
= syncobj_handle
;
5817 static VkResult
radv_import_sync_fd(struct radv_device
*device
,
5821 /* If we create a syncobj we do it locally so that if we have an error, we don't
5822 * leave a syncobj in an undetermined state in the fence. */
5823 uint32_t syncobj_handle
= *syncobj
;
5824 if (!syncobj_handle
) {
5825 int ret
= device
->ws
->create_syncobj(device
->ws
, &syncobj_handle
);
5827 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5832 device
->ws
->signal_syncobj(device
->ws
, syncobj_handle
);
5834 int ret
= device
->ws
->import_syncobj_from_sync_file(device
->ws
, syncobj_handle
, fd
);
5836 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5839 *syncobj
= syncobj_handle
;
5846 VkResult
radv_ImportSemaphoreFdKHR(VkDevice _device
,
5847 const VkImportSemaphoreFdInfoKHR
*pImportSemaphoreFdInfo
)
5849 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5850 RADV_FROM_HANDLE(radv_semaphore
, sem
, pImportSemaphoreFdInfo
->semaphore
);
5851 uint32_t *syncobj_dst
= NULL
;
5853 if (pImportSemaphoreFdInfo
->flags
& VK_SEMAPHORE_IMPORT_TEMPORARY_BIT
) {
5854 syncobj_dst
= &sem
->temp_syncobj
;
5856 syncobj_dst
= &sem
->syncobj
;
5859 switch(pImportSemaphoreFdInfo
->handleType
) {
5860 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5861 return radv_import_opaque_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5862 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5863 return radv_import_sync_fd(device
, pImportSemaphoreFdInfo
->fd
, syncobj_dst
);
5865 unreachable("Unhandled semaphore handle type");
5869 VkResult
radv_GetSemaphoreFdKHR(VkDevice _device
,
5870 const VkSemaphoreGetFdInfoKHR
*pGetFdInfo
,
5873 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5874 RADV_FROM_HANDLE(radv_semaphore
, sem
, pGetFdInfo
->semaphore
);
5876 uint32_t syncobj_handle
;
5878 if (sem
->temp_syncobj
)
5879 syncobj_handle
= sem
->temp_syncobj
;
5881 syncobj_handle
= sem
->syncobj
;
5883 switch(pGetFdInfo
->handleType
) {
5884 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5885 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5887 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
:
5888 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5890 if (sem
->temp_syncobj
) {
5891 close (sem
->temp_syncobj
);
5892 sem
->temp_syncobj
= 0;
5894 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5899 unreachable("Unhandled semaphore handle type");
5903 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5907 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5908 VkPhysicalDevice physicalDevice
,
5909 const VkPhysicalDeviceExternalSemaphoreInfo
*pExternalSemaphoreInfo
,
5910 VkExternalSemaphoreProperties
*pExternalSemaphoreProperties
)
5912 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
5914 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5915 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
5916 (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
||
5917 pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
)) {
5918 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5919 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT
;
5920 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5921 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5922 } else if (pExternalSemaphoreInfo
->handleType
== VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
) {
5923 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5924 pExternalSemaphoreProperties
->compatibleHandleTypes
= VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT
;
5925 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT
|
5926 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
5928 pExternalSemaphoreProperties
->exportFromImportedHandleTypes
= 0;
5929 pExternalSemaphoreProperties
->compatibleHandleTypes
= 0;
5930 pExternalSemaphoreProperties
->externalSemaphoreFeatures
= 0;
5934 VkResult
radv_ImportFenceFdKHR(VkDevice _device
,
5935 const VkImportFenceFdInfoKHR
*pImportFenceFdInfo
)
5937 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5938 RADV_FROM_HANDLE(radv_fence
, fence
, pImportFenceFdInfo
->fence
);
5939 uint32_t *syncobj_dst
= NULL
;
5942 if (pImportFenceFdInfo
->flags
& VK_FENCE_IMPORT_TEMPORARY_BIT
) {
5943 syncobj_dst
= &fence
->temp_syncobj
;
5945 syncobj_dst
= &fence
->syncobj
;
5948 switch(pImportFenceFdInfo
->handleType
) {
5949 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5950 return radv_import_opaque_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5951 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5952 return radv_import_sync_fd(device
, pImportFenceFdInfo
->fd
, syncobj_dst
);
5954 unreachable("Unhandled fence handle type");
5958 VkResult
radv_GetFenceFdKHR(VkDevice _device
,
5959 const VkFenceGetFdInfoKHR
*pGetFdInfo
,
5962 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5963 RADV_FROM_HANDLE(radv_fence
, fence
, pGetFdInfo
->fence
);
5965 uint32_t syncobj_handle
;
5967 if (fence
->temp_syncobj
)
5968 syncobj_handle
= fence
->temp_syncobj
;
5970 syncobj_handle
= fence
->syncobj
;
5972 switch(pGetFdInfo
->handleType
) {
5973 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
:
5974 ret
= device
->ws
->export_syncobj(device
->ws
, syncobj_handle
, pFd
);
5976 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
:
5977 ret
= device
->ws
->export_syncobj_to_sync_file(device
->ws
, syncobj_handle
, pFd
);
5979 if (fence
->temp_syncobj
) {
5980 close (fence
->temp_syncobj
);
5981 fence
->temp_syncobj
= 0;
5983 device
->ws
->reset_syncobj(device
->ws
, syncobj_handle
);
5988 unreachable("Unhandled fence handle type");
5992 return vk_error(device
->instance
, VK_ERROR_INVALID_EXTERNAL_HANDLE
);
5996 void radv_GetPhysicalDeviceExternalFenceProperties(
5997 VkPhysicalDevice physicalDevice
,
5998 const VkPhysicalDeviceExternalFenceInfo
*pExternalFenceInfo
,
5999 VkExternalFenceProperties
*pExternalFenceProperties
)
6001 RADV_FROM_HANDLE(radv_physical_device
, pdevice
, physicalDevice
);
6003 if (pdevice
->rad_info
.has_syncobj_wait_for_submit
&&
6004 (pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
||
6005 pExternalFenceInfo
->handleType
== VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
)) {
6006 pExternalFenceProperties
->exportFromImportedHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
6007 pExternalFenceProperties
->compatibleHandleTypes
= VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT
| VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT
;
6008 pExternalFenceProperties
->externalFenceFeatures
= VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT
|
6009 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT
;
6011 pExternalFenceProperties
->exportFromImportedHandleTypes
= 0;
6012 pExternalFenceProperties
->compatibleHandleTypes
= 0;
6013 pExternalFenceProperties
->externalFenceFeatures
= 0;
6018 radv_CreateDebugReportCallbackEXT(VkInstance _instance
,
6019 const VkDebugReportCallbackCreateInfoEXT
* pCreateInfo
,
6020 const VkAllocationCallbacks
* pAllocator
,
6021 VkDebugReportCallbackEXT
* pCallback
)
6023 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
6024 return vk_create_debug_report_callback(&instance
->debug_report_callbacks
,
6025 pCreateInfo
, pAllocator
, &instance
->alloc
,
6030 radv_DestroyDebugReportCallbackEXT(VkInstance _instance
,
6031 VkDebugReportCallbackEXT _callback
,
6032 const VkAllocationCallbacks
* pAllocator
)
6034 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
6035 vk_destroy_debug_report_callback(&instance
->debug_report_callbacks
,
6036 _callback
, pAllocator
, &instance
->alloc
);
6040 radv_DebugReportMessageEXT(VkInstance _instance
,
6041 VkDebugReportFlagsEXT flags
,
6042 VkDebugReportObjectTypeEXT objectType
,
6045 int32_t messageCode
,
6046 const char* pLayerPrefix
,
6047 const char* pMessage
)
6049 RADV_FROM_HANDLE(radv_instance
, instance
, _instance
);
6050 vk_debug_report(&instance
->debug_report_callbacks
, flags
, objectType
,
6051 object
, location
, messageCode
, pLayerPrefix
, pMessage
);
6055 radv_GetDeviceGroupPeerMemoryFeatures(
6058 uint32_t localDeviceIndex
,
6059 uint32_t remoteDeviceIndex
,
6060 VkPeerMemoryFeatureFlags
* pPeerMemoryFeatures
)
6062 assert(localDeviceIndex
== remoteDeviceIndex
);
6064 *pPeerMemoryFeatures
= VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT
|
6065 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT
|
6066 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT
|
6067 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT
;
6070 static const VkTimeDomainEXT radv_time_domains
[] = {
6071 VK_TIME_DOMAIN_DEVICE_EXT
,
6072 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
,
6073 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
,
6076 VkResult
radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
6077 VkPhysicalDevice physicalDevice
,
6078 uint32_t *pTimeDomainCount
,
6079 VkTimeDomainEXT
*pTimeDomains
)
6082 VK_OUTARRAY_MAKE(out
, pTimeDomains
, pTimeDomainCount
);
6084 for (d
= 0; d
< ARRAY_SIZE(radv_time_domains
); d
++) {
6085 vk_outarray_append(&out
, i
) {
6086 *i
= radv_time_domains
[d
];
6090 return vk_outarray_status(&out
);
6094 radv_clock_gettime(clockid_t clock_id
)
6096 struct timespec current
;
6099 ret
= clock_gettime(clock_id
, ¤t
);
6100 if (ret
< 0 && clock_id
== CLOCK_MONOTONIC_RAW
)
6101 ret
= clock_gettime(CLOCK_MONOTONIC
, ¤t
);
6105 return (uint64_t) current
.tv_sec
* 1000000000ULL + current
.tv_nsec
;
6108 VkResult
radv_GetCalibratedTimestampsEXT(
6110 uint32_t timestampCount
,
6111 const VkCalibratedTimestampInfoEXT
*pTimestampInfos
,
6112 uint64_t *pTimestamps
,
6113 uint64_t *pMaxDeviation
)
6115 RADV_FROM_HANDLE(radv_device
, device
, _device
);
6116 uint32_t clock_crystal_freq
= device
->physical_device
->rad_info
.clock_crystal_freq
;
6118 uint64_t begin
, end
;
6119 uint64_t max_clock_period
= 0;
6121 begin
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
6123 for (d
= 0; d
< timestampCount
; d
++) {
6124 switch (pTimestampInfos
[d
].timeDomain
) {
6125 case VK_TIME_DOMAIN_DEVICE_EXT
:
6126 pTimestamps
[d
] = device
->ws
->query_value(device
->ws
,
6128 uint64_t device_period
= DIV_ROUND_UP(1000000, clock_crystal_freq
);
6129 max_clock_period
= MAX2(max_clock_period
, device_period
);
6131 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT
:
6132 pTimestamps
[d
] = radv_clock_gettime(CLOCK_MONOTONIC
);
6133 max_clock_period
= MAX2(max_clock_period
, 1);
6136 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT
:
6137 pTimestamps
[d
] = begin
;
6145 end
= radv_clock_gettime(CLOCK_MONOTONIC_RAW
);
6148 * The maximum deviation is the sum of the interval over which we
6149 * perform the sampling and the maximum period of any sampled
6150 * clock. That's because the maximum skew between any two sampled
6151 * clock edges is when the sampled clock with the largest period is
6152 * sampled at the end of that period but right at the beginning of the
6153 * sampling interval and some other clock is sampled right at the
6154 * begining of its sampling period and right at the end of the
6155 * sampling interval. Let's assume the GPU has the longest clock
6156 * period and that the application is sampling GPU and monotonic:
6159 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
6160 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
6164 * GPU -----_____-----_____-----_____-----_____
6167 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
6168 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
6170 * Interval <----------------->
6171 * Deviation <-------------------------->
6175 * m = read(monotonic) 2
6178 * We round the sample interval up by one tick to cover sampling error
6179 * in the interval clock
6182 uint64_t sample_interval
= end
- begin
+ 1;
6184 *pMaxDeviation
= sample_interval
+ max_clock_period
;
6189 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
6190 VkPhysicalDevice physicalDevice
,
6191 VkSampleCountFlagBits samples
,
6192 VkMultisamplePropertiesEXT
* pMultisampleProperties
)
6194 if (samples
& (VK_SAMPLE_COUNT_2_BIT
|
6195 VK_SAMPLE_COUNT_4_BIT
|
6196 VK_SAMPLE_COUNT_8_BIT
)) {
6197 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 2, 2 };
6199 pMultisampleProperties
->maxSampleLocationGridSize
= (VkExtent2D
){ 0, 0 };