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radv/gfx10: set RADV_FORCE_FAMILY
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 default: chip_string = "AMD RADV unknown"; break;
117 }
118
119 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
120 }
121
122 static uint64_t
123 radv_get_visible_vram_size(struct radv_physical_device *device)
124 {
125 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
126 }
127
128 static uint64_t
129 radv_get_vram_size(struct radv_physical_device *device)
130 {
131 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
132 }
133
134 static void
135 radv_physical_device_init_mem_types(struct radv_physical_device *device)
136 {
137 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
138 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
139 uint64_t vram_size = radv_get_vram_size(device);
140 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
141 device->memory_properties.memoryHeapCount = 0;
142 if (vram_size > 0) {
143 vram_index = device->memory_properties.memoryHeapCount++;
144 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
145 .size = vram_size,
146 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
147 };
148 }
149 if (visible_vram_size) {
150 visible_vram_index = device->memory_properties.memoryHeapCount++;
151 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
152 .size = visible_vram_size,
153 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
154 };
155 }
156 if (device->rad_info.gart_size > 0) {
157 gart_index = device->memory_properties.memoryHeapCount++;
158 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
159 .size = device->rad_info.gart_size,
160 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
161 };
162 }
163
164 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
165 unsigned type_count = 0;
166 if (vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
170 .heapIndex = vram_index,
171 };
172 }
173 if (gart_index >= 0) {
174 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
175 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
176 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
177 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
178 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
179 .heapIndex = gart_index,
180 };
181 }
182 if (visible_vram_index >= 0) {
183 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
184 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
185 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
186 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
187 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
188 .heapIndex = visible_vram_index,
189 };
190 }
191 if (gart_index >= 0) {
192 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
193 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
194 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
195 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
196 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
197 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
198 .heapIndex = gart_index,
199 };
200 }
201 device->memory_properties.memoryTypeCount = type_count;
202 }
203
204 static void
205 radv_handle_env_var_force_family(struct radv_physical_device *device)
206 {
207 const char *family = getenv("RADV_FORCE_FAMILY");
208 unsigned i;
209
210 if (!family)
211 return;
212
213 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
214 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
215 /* Override family and chip_class. */
216 device->rad_info.family = i;
217
218 if (i >= CHIP_NAVI10)
219 device->rad_info.chip_class = GFX10;
220 else if (i >= CHIP_VEGA10)
221 device->rad_info.chip_class = GFX9;
222 else if (i >= CHIP_TONGA)
223 device->rad_info.chip_class = GFX8;
224 else if (i >= CHIP_BONAIRE)
225 device->rad_info.chip_class = GFX7;
226 else
227 device->rad_info.chip_class = GFX6;
228
229 return;
230 }
231 }
232
233 fprintf(stderr, "radv: Unknown family: %s\n", family);
234 exit(1);
235 }
236
237 static VkResult
238 radv_physical_device_init(struct radv_physical_device *device,
239 struct radv_instance *instance,
240 drmDevicePtr drm_device)
241 {
242 const char *path = drm_device->nodes[DRM_NODE_RENDER];
243 VkResult result;
244 drmVersionPtr version;
245 int fd;
246 int master_fd = -1;
247
248 fd = open(path, O_RDWR | O_CLOEXEC);
249 if (fd < 0) {
250 if (instance->debug_flags & RADV_DEBUG_STARTUP)
251 radv_logi("Could not open device '%s'", path);
252
253 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
254 }
255
256 version = drmGetVersion(fd);
257 if (!version) {
258 close(fd);
259
260 if (instance->debug_flags & RADV_DEBUG_STARTUP)
261 radv_logi("Could not get the kernel driver version for device '%s'", path);
262
263 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
264 "failed to get version %s: %m", path);
265 }
266
267 if (strcmp(version->name, "amdgpu")) {
268 drmFreeVersion(version);
269 close(fd);
270
271 if (instance->debug_flags & RADV_DEBUG_STARTUP)
272 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
273
274 return VK_ERROR_INCOMPATIBLE_DRIVER;
275 }
276 drmFreeVersion(version);
277
278 if (instance->debug_flags & RADV_DEBUG_STARTUP)
279 radv_logi("Found compatible device '%s'.", path);
280
281 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
282 device->instance = instance;
283
284 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
285 instance->perftest_flags);
286 if (!device->ws) {
287 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
288 goto fail;
289 }
290
291 if (instance->enabled_extensions.KHR_display) {
292 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
293 if (master_fd >= 0) {
294 uint32_t accel_working = 0;
295 struct drm_amdgpu_info request = {
296 .return_pointer = (uintptr_t)&accel_working,
297 .return_size = sizeof(accel_working),
298 .query = AMDGPU_INFO_ACCEL_WORKING
299 };
300
301 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
302 close(master_fd);
303 master_fd = -1;
304 }
305 }
306 }
307
308 device->master_fd = master_fd;
309 device->local_fd = fd;
310 device->ws->query_info(device->ws, &device->rad_info);
311
312 radv_handle_env_var_force_family(device);
313
314 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
315
316 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
317 device->ws->destroy(device->ws);
318 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
319 "cannot generate UUID");
320 goto fail;
321 }
322
323 /* These flags affect shader compilation. */
324 uint64_t shader_env_flags =
325 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
326 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
327
328 /* The gpu id is already embedded in the uuid so we just pass "radv"
329 * when creating the cache.
330 */
331 char buf[VK_UUID_SIZE * 2 + 1];
332 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
333 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
334
335 if (device->rad_info.chip_class < GFX8 ||
336 device->rad_info.chip_class > GFX9)
337 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
338
339 radv_get_driver_uuid(&device->driver_uuid);
340 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
341
342 if (device->rad_info.family == CHIP_STONEY ||
343 device->rad_info.chip_class >= GFX9) {
344 device->has_rbplus = true;
345 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.family == CHIP_VEGA12 ||
347 device->rad_info.family == CHIP_RAVEN ||
348 device->rad_info.family == CHIP_RAVEN2;
349 }
350
351 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
352 * on GFX6.
353 */
354 device->has_clear_state = device->rad_info.chip_class >= GFX7;
355
356 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
357
358 /* Vega10/Raven need a special workaround for a hardware bug. */
359 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
360 device->rad_info.family == CHIP_RAVEN;
361
362 /* Out-of-order primitive rasterization. */
363 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
364 device->rad_info.max_se >= 2;
365 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
366 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
367
368 device->dcc_msaa_allowed =
369 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
370
371 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
372 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
373 (device->rad_info.chip_class >= GFX8 &&
374 device->rad_info.me_fw_feature >= 41);
375
376 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2;
377
378 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
379
380 radv_physical_device_init_mem_types(device);
381 radv_fill_device_extension_table(device, &device->supported_extensions);
382
383 device->bus_info = *drm_device->businfo.pci;
384
385 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
386 ac_print_gpu_info(&device->rad_info);
387
388 /* The WSI is structured as a layer on top of the driver, so this has
389 * to be the last part of initialization (at least until we get other
390 * semi-layers).
391 */
392 result = radv_init_wsi(device);
393 if (result != VK_SUCCESS) {
394 device->ws->destroy(device->ws);
395 vk_error(instance, result);
396 goto fail;
397 }
398
399 return VK_SUCCESS;
400
401 fail:
402 close(fd);
403 if (master_fd != -1)
404 close(master_fd);
405 return result;
406 }
407
408 static void
409 radv_physical_device_finish(struct radv_physical_device *device)
410 {
411 radv_finish_wsi(device);
412 device->ws->destroy(device->ws);
413 disk_cache_destroy(device->disk_cache);
414 close(device->local_fd);
415 if (device->master_fd != -1)
416 close(device->master_fd);
417 }
418
419 static void *
420 default_alloc_func(void *pUserData, size_t size, size_t align,
421 VkSystemAllocationScope allocationScope)
422 {
423 return malloc(size);
424 }
425
426 static void *
427 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
428 size_t align, VkSystemAllocationScope allocationScope)
429 {
430 return realloc(pOriginal, size);
431 }
432
433 static void
434 default_free_func(void *pUserData, void *pMemory)
435 {
436 free(pMemory);
437 }
438
439 static const VkAllocationCallbacks default_alloc = {
440 .pUserData = NULL,
441 .pfnAllocation = default_alloc_func,
442 .pfnReallocation = default_realloc_func,
443 .pfnFree = default_free_func,
444 };
445
446 static const struct debug_control radv_debug_options[] = {
447 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
448 {"nodcc", RADV_DEBUG_NO_DCC},
449 {"shaders", RADV_DEBUG_DUMP_SHADERS},
450 {"nocache", RADV_DEBUG_NO_CACHE},
451 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
452 {"nohiz", RADV_DEBUG_NO_HIZ},
453 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
454 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
455 {"allbos", RADV_DEBUG_ALL_BOS},
456 {"noibs", RADV_DEBUG_NO_IBS},
457 {"spirv", RADV_DEBUG_DUMP_SPIRV},
458 {"vmfaults", RADV_DEBUG_VM_FAULTS},
459 {"zerovram", RADV_DEBUG_ZERO_VRAM},
460 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
461 {"nosisched", RADV_DEBUG_NO_SISCHED},
462 {"preoptir", RADV_DEBUG_PREOPTIR},
463 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
464 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
465 {"info", RADV_DEBUG_INFO},
466 {"errors", RADV_DEBUG_ERRORS},
467 {"startup", RADV_DEBUG_STARTUP},
468 {"checkir", RADV_DEBUG_CHECKIR},
469 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
470 {"nobinning", RADV_DEBUG_NOBINNING},
471 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
472 {NULL, 0}
473 };
474
475 const char *
476 radv_get_debug_option_name(int id)
477 {
478 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
479 return radv_debug_options[id].string;
480 }
481
482 static const struct debug_control radv_perftest_options[] = {
483 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
484 {"sisched", RADV_PERFTEST_SISCHED},
485 {"localbos", RADV_PERFTEST_LOCAL_BOS},
486 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
487 {"bolist", RADV_PERFTEST_BO_LIST},
488 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
489 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
490 {NULL, 0}
491 };
492
493 const char *
494 radv_get_perftest_option_name(int id)
495 {
496 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
497 return radv_perftest_options[id].string;
498 }
499
500 static void
501 radv_handle_per_app_options(struct radv_instance *instance,
502 const VkApplicationInfo *info)
503 {
504 const char *name = info ? info->pApplicationName : NULL;
505
506 if (!name)
507 return;
508
509 if (!strcmp(name, "Talos - Linux - 32bit") ||
510 !strcmp(name, "Talos - Linux - 64bit")) {
511 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
512 /* Force enable LLVM sisched for Talos because it looks
513 * safe and it gives few more FPS.
514 */
515 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
516 }
517 } else if (!strcmp(name, "DOOM_VFR")) {
518 /* Work around a Doom VFR game bug */
519 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
520 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
521 /* Workaround for a WaW hazard when LLVM moves/merges
522 * load/store memory operations.
523 * See https://reviews.llvm.org/D61313
524 */
525 if (HAVE_LLVM < 0x900)
526 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
527 }
528 }
529
530 static int radv_get_instance_extension_index(const char *name)
531 {
532 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
533 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
534 return i;
535 }
536 return -1;
537 }
538
539 static const char radv_dri_options_xml[] =
540 DRI_CONF_BEGIN
541 DRI_CONF_SECTION_QUALITY
542 DRI_CONF_ADAPTIVE_SYNC("true")
543 DRI_CONF_SECTION_END
544 DRI_CONF_END;
545
546 static void radv_init_dri_options(struct radv_instance *instance)
547 {
548 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
549 driParseConfigFiles(&instance->dri_options,
550 &instance->available_dri_options,
551 0, "radv", NULL);
552 }
553
554 VkResult radv_CreateInstance(
555 const VkInstanceCreateInfo* pCreateInfo,
556 const VkAllocationCallbacks* pAllocator,
557 VkInstance* pInstance)
558 {
559 struct radv_instance *instance;
560 VkResult result;
561
562 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
563
564 uint32_t client_version;
565 if (pCreateInfo->pApplicationInfo &&
566 pCreateInfo->pApplicationInfo->apiVersion != 0) {
567 client_version = pCreateInfo->pApplicationInfo->apiVersion;
568 } else {
569 client_version = VK_API_VERSION_1_0;
570 }
571
572 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
573 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
574 if (!instance)
575 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
576
577 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
578
579 if (pAllocator)
580 instance->alloc = *pAllocator;
581 else
582 instance->alloc = default_alloc;
583
584 instance->apiVersion = client_version;
585 instance->physicalDeviceCount = -1;
586
587 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
588 radv_debug_options);
589
590 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
591 radv_perftest_options);
592
593
594 if (instance->debug_flags & RADV_DEBUG_STARTUP)
595 radv_logi("Created an instance");
596
597 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
598 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
599 int index = radv_get_instance_extension_index(ext_name);
600
601 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
602 vk_free2(&default_alloc, pAllocator, instance);
603 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
604 }
605
606 instance->enabled_extensions.extensions[index] = true;
607 }
608
609 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
610 if (result != VK_SUCCESS) {
611 vk_free2(&default_alloc, pAllocator, instance);
612 return vk_error(instance, result);
613 }
614
615 _mesa_locale_init();
616 glsl_type_singleton_init_or_ref();
617
618 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
619
620 radv_init_dri_options(instance);
621 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
622
623 *pInstance = radv_instance_to_handle(instance);
624
625 return VK_SUCCESS;
626 }
627
628 void radv_DestroyInstance(
629 VkInstance _instance,
630 const VkAllocationCallbacks* pAllocator)
631 {
632 RADV_FROM_HANDLE(radv_instance, instance, _instance);
633
634 if (!instance)
635 return;
636
637 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
638 radv_physical_device_finish(instance->physicalDevices + i);
639 }
640
641 VG(VALGRIND_DESTROY_MEMPOOL(instance));
642
643 glsl_type_singleton_decref();
644 _mesa_locale_fini();
645
646 driDestroyOptionCache(&instance->dri_options);
647 driDestroyOptionInfo(&instance->available_dri_options);
648
649 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
650
651 vk_free(&instance->alloc, instance);
652 }
653
654 static VkResult
655 radv_enumerate_devices(struct radv_instance *instance)
656 {
657 /* TODO: Check for more devices ? */
658 drmDevicePtr devices[8];
659 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
660 int max_devices;
661
662 instance->physicalDeviceCount = 0;
663
664 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
665
666 if (instance->debug_flags & RADV_DEBUG_STARTUP)
667 radv_logi("Found %d drm nodes", max_devices);
668
669 if (max_devices < 1)
670 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
671
672 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
673 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
674 devices[i]->bustype == DRM_BUS_PCI &&
675 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
676
677 result = radv_physical_device_init(instance->physicalDevices +
678 instance->physicalDeviceCount,
679 instance,
680 devices[i]);
681 if (result == VK_SUCCESS)
682 ++instance->physicalDeviceCount;
683 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
684 break;
685 }
686 }
687 drmFreeDevices(devices, max_devices);
688
689 return result;
690 }
691
692 VkResult radv_EnumeratePhysicalDevices(
693 VkInstance _instance,
694 uint32_t* pPhysicalDeviceCount,
695 VkPhysicalDevice* pPhysicalDevices)
696 {
697 RADV_FROM_HANDLE(radv_instance, instance, _instance);
698 VkResult result;
699
700 if (instance->physicalDeviceCount < 0) {
701 result = radv_enumerate_devices(instance);
702 if (result != VK_SUCCESS &&
703 result != VK_ERROR_INCOMPATIBLE_DRIVER)
704 return result;
705 }
706
707 if (!pPhysicalDevices) {
708 *pPhysicalDeviceCount = instance->physicalDeviceCount;
709 } else {
710 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
711 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
712 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
713 }
714
715 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
716 : VK_SUCCESS;
717 }
718
719 VkResult radv_EnumeratePhysicalDeviceGroups(
720 VkInstance _instance,
721 uint32_t* pPhysicalDeviceGroupCount,
722 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
723 {
724 RADV_FROM_HANDLE(radv_instance, instance, _instance);
725 VkResult result;
726
727 if (instance->physicalDeviceCount < 0) {
728 result = radv_enumerate_devices(instance);
729 if (result != VK_SUCCESS &&
730 result != VK_ERROR_INCOMPATIBLE_DRIVER)
731 return result;
732 }
733
734 if (!pPhysicalDeviceGroupProperties) {
735 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
736 } else {
737 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
738 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
739 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
740 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
741 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
742 }
743 }
744 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
745 : VK_SUCCESS;
746 }
747
748 void radv_GetPhysicalDeviceFeatures(
749 VkPhysicalDevice physicalDevice,
750 VkPhysicalDeviceFeatures* pFeatures)
751 {
752 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
753 memset(pFeatures, 0, sizeof(*pFeatures));
754
755 *pFeatures = (VkPhysicalDeviceFeatures) {
756 .robustBufferAccess = true,
757 .fullDrawIndexUint32 = true,
758 .imageCubeArray = true,
759 .independentBlend = true,
760 .geometryShader = true,
761 .tessellationShader = true,
762 .sampleRateShading = true,
763 .dualSrcBlend = true,
764 .logicOp = true,
765 .multiDrawIndirect = true,
766 .drawIndirectFirstInstance = true,
767 .depthClamp = true,
768 .depthBiasClamp = true,
769 .fillModeNonSolid = true,
770 .depthBounds = true,
771 .wideLines = true,
772 .largePoints = true,
773 .alphaToOne = true,
774 .multiViewport = true,
775 .samplerAnisotropy = true,
776 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
777 .textureCompressionASTC_LDR = false,
778 .textureCompressionBC = true,
779 .occlusionQueryPrecise = true,
780 .pipelineStatisticsQuery = true,
781 .vertexPipelineStoresAndAtomics = true,
782 .fragmentStoresAndAtomics = true,
783 .shaderTessellationAndGeometryPointSize = true,
784 .shaderImageGatherExtended = true,
785 .shaderStorageImageExtendedFormats = true,
786 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
787 .shaderUniformBufferArrayDynamicIndexing = true,
788 .shaderSampledImageArrayDynamicIndexing = true,
789 .shaderStorageBufferArrayDynamicIndexing = true,
790 .shaderStorageImageArrayDynamicIndexing = true,
791 .shaderStorageImageReadWithoutFormat = true,
792 .shaderStorageImageWriteWithoutFormat = true,
793 .shaderClipDistance = true,
794 .shaderCullDistance = true,
795 .shaderFloat64 = true,
796 .shaderInt64 = true,
797 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
798 .sparseBinding = true,
799 .variableMultisampleRate = true,
800 .inheritedQueries = true,
801 };
802 }
803
804 void radv_GetPhysicalDeviceFeatures2(
805 VkPhysicalDevice physicalDevice,
806 VkPhysicalDeviceFeatures2 *pFeatures)
807 {
808 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
809 vk_foreach_struct(ext, pFeatures->pNext) {
810 switch (ext->sType) {
811 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
812 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
813 features->variablePointersStorageBuffer = true;
814 features->variablePointers = true;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
818 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
819 features->multiview = true;
820 features->multiviewGeometryShader = true;
821 features->multiviewTessellationShader = true;
822 break;
823 }
824 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
825 VkPhysicalDeviceShaderDrawParametersFeatures *features =
826 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
827 features->shaderDrawParameters = true;
828 break;
829 }
830 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
831 VkPhysicalDeviceProtectedMemoryFeatures *features =
832 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
833 features->protectedMemory = false;
834 break;
835 }
836 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
837 VkPhysicalDevice16BitStorageFeatures *features =
838 (VkPhysicalDevice16BitStorageFeatures*)ext;
839 bool enabled = pdevice->rad_info.chip_class >= GFX8;
840 features->storageBuffer16BitAccess = enabled;
841 features->uniformAndStorageBuffer16BitAccess = enabled;
842 features->storagePushConstant16 = enabled;
843 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
844 break;
845 }
846 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
847 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
848 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
849 features->samplerYcbcrConversion = true;
850 break;
851 }
852 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
853 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
854 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
855 features->shaderInputAttachmentArrayDynamicIndexing = true;
856 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
857 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
858 features->shaderUniformBufferArrayNonUniformIndexing = true;
859 features->shaderSampledImageArrayNonUniformIndexing = true;
860 features->shaderStorageBufferArrayNonUniformIndexing = true;
861 features->shaderStorageImageArrayNonUniformIndexing = true;
862 features->shaderInputAttachmentArrayNonUniformIndexing = true;
863 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
864 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
865 features->descriptorBindingUniformBufferUpdateAfterBind = true;
866 features->descriptorBindingSampledImageUpdateAfterBind = true;
867 features->descriptorBindingStorageImageUpdateAfterBind = true;
868 features->descriptorBindingStorageBufferUpdateAfterBind = true;
869 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
870 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
871 features->descriptorBindingUpdateUnusedWhilePending = true;
872 features->descriptorBindingPartiallyBound = true;
873 features->descriptorBindingVariableDescriptorCount = true;
874 features->runtimeDescriptorArray = true;
875 break;
876 }
877 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
878 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
879 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
880 features->conditionalRendering = true;
881 features->inheritedConditionalRendering = false;
882 break;
883 }
884 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
885 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
886 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
887 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
888 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
889 break;
890 }
891 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
892 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
893 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
894 features->transformFeedback = true;
895 features->geometryStreams = true;
896 break;
897 }
898 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
899 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
900 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
901 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
905 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
906 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
907 features->memoryPriority = VK_TRUE;
908 break;
909 }
910 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
911 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
912 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
913 features->bufferDeviceAddress = true;
914 features->bufferDeviceAddressCaptureReplay = false;
915 features->bufferDeviceAddressMultiDevice = false;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
919 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
920 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
921 features->depthClipEnable = true;
922 break;
923 }
924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
925 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
926 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
927 features->hostQueryReset = true;
928 break;
929 }
930 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
931 VkPhysicalDevice8BitStorageFeaturesKHR *features =
932 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
933 bool enabled = pdevice->rad_info.chip_class >= GFX8;
934 features->storageBuffer8BitAccess = enabled;
935 features->uniformAndStorageBuffer8BitAccess = enabled;
936 features->storagePushConstant8 = enabled;
937 break;
938 }
939 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
940 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
941 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
942 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
943 features->shaderInt8 = true;
944 break;
945 }
946 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
947 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
948 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
949 /* TODO: Enable this once the driver supports 64-bit
950 * compare&swap atomic operations.
951 */
952 features->shaderBufferInt64Atomics = false;
953 features->shaderSharedInt64Atomics = false;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
957 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
958 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
959
960 features->inlineUniformBlock = true;
961 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
962 break;
963 }
964 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
965 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
966 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
967 features->computeDerivativeGroupQuads = false;
968 features->computeDerivativeGroupLinear = true;
969 break;
970 }
971 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
972 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
973 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
974 features->ycbcrImageArrays = true;
975 break;
976 }
977 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
978 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
979 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
980 features->uniformBufferStandardLayout = true;
981 break;
982 }
983 default:
984 break;
985 }
986 }
987 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
988 }
989
990 void radv_GetPhysicalDeviceProperties(
991 VkPhysicalDevice physicalDevice,
992 VkPhysicalDeviceProperties* pProperties)
993 {
994 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
995 VkSampleCountFlags sample_counts = 0xf;
996
997 /* make sure that the entire descriptor set is addressable with a signed
998 * 32-bit int. So the sum of all limits scaled by descriptor size has to
999 * be at most 2 GiB. the combined image & samples object count as one of
1000 * both. This limit is for the pipeline layout, not for the set layout, but
1001 * there is no set limit, so we just set a pipeline limit. I don't think
1002 * any app is going to hit this soon. */
1003 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1004 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1005 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1006 32 /* sampler, largest when combined with image */ +
1007 64 /* sampled image */ +
1008 64 /* storage image */);
1009
1010 VkPhysicalDeviceLimits limits = {
1011 .maxImageDimension1D = (1 << 14),
1012 .maxImageDimension2D = (1 << 14),
1013 .maxImageDimension3D = (1 << 11),
1014 .maxImageDimensionCube = (1 << 14),
1015 .maxImageArrayLayers = (1 << 11),
1016 .maxTexelBufferElements = 128 * 1024 * 1024,
1017 .maxUniformBufferRange = UINT32_MAX,
1018 .maxStorageBufferRange = UINT32_MAX,
1019 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1020 .maxMemoryAllocationCount = UINT32_MAX,
1021 .maxSamplerAllocationCount = 64 * 1024,
1022 .bufferImageGranularity = 64, /* A cache line */
1023 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1024 .maxBoundDescriptorSets = MAX_SETS,
1025 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1026 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1027 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1028 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1029 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1030 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1031 .maxPerStageResources = max_descriptor_set_size,
1032 .maxDescriptorSetSamplers = max_descriptor_set_size,
1033 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1034 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1035 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1036 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1037 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1038 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1039 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1040 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1041 .maxVertexInputBindings = MAX_VBS,
1042 .maxVertexInputAttributeOffset = 2047,
1043 .maxVertexInputBindingStride = 2048,
1044 .maxVertexOutputComponents = 128,
1045 .maxTessellationGenerationLevel = 64,
1046 .maxTessellationPatchSize = 32,
1047 .maxTessellationControlPerVertexInputComponents = 128,
1048 .maxTessellationControlPerVertexOutputComponents = 128,
1049 .maxTessellationControlPerPatchOutputComponents = 120,
1050 .maxTessellationControlTotalOutputComponents = 4096,
1051 .maxTessellationEvaluationInputComponents = 128,
1052 .maxTessellationEvaluationOutputComponents = 128,
1053 .maxGeometryShaderInvocations = 127,
1054 .maxGeometryInputComponents = 64,
1055 .maxGeometryOutputComponents = 128,
1056 .maxGeometryOutputVertices = 256,
1057 .maxGeometryTotalOutputComponents = 1024,
1058 .maxFragmentInputComponents = 128,
1059 .maxFragmentOutputAttachments = 8,
1060 .maxFragmentDualSrcAttachments = 1,
1061 .maxFragmentCombinedOutputResources = 8,
1062 .maxComputeSharedMemorySize = 32768,
1063 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1064 .maxComputeWorkGroupInvocations = 2048,
1065 .maxComputeWorkGroupSize = {
1066 2048,
1067 2048,
1068 2048
1069 },
1070 .subPixelPrecisionBits = 8,
1071 .subTexelPrecisionBits = 8,
1072 .mipmapPrecisionBits = 8,
1073 .maxDrawIndexedIndexValue = UINT32_MAX,
1074 .maxDrawIndirectCount = UINT32_MAX,
1075 .maxSamplerLodBias = 16,
1076 .maxSamplerAnisotropy = 16,
1077 .maxViewports = MAX_VIEWPORTS,
1078 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1079 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1080 .viewportSubPixelBits = 8,
1081 .minMemoryMapAlignment = 4096, /* A page */
1082 .minTexelBufferOffsetAlignment = 1,
1083 .minUniformBufferOffsetAlignment = 4,
1084 .minStorageBufferOffsetAlignment = 4,
1085 .minTexelOffset = -32,
1086 .maxTexelOffset = 31,
1087 .minTexelGatherOffset = -32,
1088 .maxTexelGatherOffset = 31,
1089 .minInterpolationOffset = -2,
1090 .maxInterpolationOffset = 2,
1091 .subPixelInterpolationOffsetBits = 8,
1092 .maxFramebufferWidth = (1 << 14),
1093 .maxFramebufferHeight = (1 << 14),
1094 .maxFramebufferLayers = (1 << 10),
1095 .framebufferColorSampleCounts = sample_counts,
1096 .framebufferDepthSampleCounts = sample_counts,
1097 .framebufferStencilSampleCounts = sample_counts,
1098 .framebufferNoAttachmentsSampleCounts = sample_counts,
1099 .maxColorAttachments = MAX_RTS,
1100 .sampledImageColorSampleCounts = sample_counts,
1101 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1102 .sampledImageDepthSampleCounts = sample_counts,
1103 .sampledImageStencilSampleCounts = sample_counts,
1104 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1105 .maxSampleMaskWords = 1,
1106 .timestampComputeAndGraphics = true,
1107 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1108 .maxClipDistances = 8,
1109 .maxCullDistances = 8,
1110 .maxCombinedClipAndCullDistances = 8,
1111 .discreteQueuePriorities = 2,
1112 .pointSizeRange = { 0.0, 8192.0 },
1113 .lineWidthRange = { 0.0, 7.9921875 },
1114 .pointSizeGranularity = (1.0 / 8.0),
1115 .lineWidthGranularity = (1.0 / 128.0),
1116 .strictLines = false, /* FINISHME */
1117 .standardSampleLocations = true,
1118 .optimalBufferCopyOffsetAlignment = 128,
1119 .optimalBufferCopyRowPitchAlignment = 128,
1120 .nonCoherentAtomSize = 64,
1121 };
1122
1123 *pProperties = (VkPhysicalDeviceProperties) {
1124 .apiVersion = radv_physical_device_api_version(pdevice),
1125 .driverVersion = vk_get_driver_version(),
1126 .vendorID = ATI_VENDOR_ID,
1127 .deviceID = pdevice->rad_info.pci_id,
1128 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1129 .limits = limits,
1130 .sparseProperties = {0},
1131 };
1132
1133 strcpy(pProperties->deviceName, pdevice->name);
1134 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1135 }
1136
1137 void radv_GetPhysicalDeviceProperties2(
1138 VkPhysicalDevice physicalDevice,
1139 VkPhysicalDeviceProperties2 *pProperties)
1140 {
1141 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1142 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1143
1144 vk_foreach_struct(ext, pProperties->pNext) {
1145 switch (ext->sType) {
1146 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1147 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1148 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1149 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1150 break;
1151 }
1152 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1153 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1154 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1155 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1156 properties->deviceLUIDValid = false;
1157 break;
1158 }
1159 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1160 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1161 properties->maxMultiviewViewCount = MAX_VIEWS;
1162 properties->maxMultiviewInstanceIndex = INT_MAX;
1163 break;
1164 }
1165 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1166 VkPhysicalDevicePointClippingProperties *properties =
1167 (VkPhysicalDevicePointClippingProperties*)ext;
1168 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1169 break;
1170 }
1171 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1172 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1173 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1174 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1175 break;
1176 }
1177 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1178 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1179 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1180 properties->minImportedHostPointerAlignment = 4096;
1181 break;
1182 }
1183 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1184 VkPhysicalDeviceSubgroupProperties *properties =
1185 (VkPhysicalDeviceSubgroupProperties*)ext;
1186 properties->subgroupSize = 64;
1187 properties->supportedStages = VK_SHADER_STAGE_ALL;
1188 properties->supportedOperations =
1189 VK_SUBGROUP_FEATURE_BASIC_BIT |
1190 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1191 VK_SUBGROUP_FEATURE_QUAD_BIT |
1192 VK_SUBGROUP_FEATURE_VOTE_BIT;
1193 if (pdevice->rad_info.chip_class >= GFX8) {
1194 properties->supportedOperations |=
1195 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1196 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1197 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1198 }
1199 properties->quadOperationsInAllStages = true;
1200 break;
1201 }
1202 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1203 VkPhysicalDeviceMaintenance3Properties *properties =
1204 (VkPhysicalDeviceMaintenance3Properties*)ext;
1205 /* Make sure everything is addressable by a signed 32-bit int, and
1206 * our largest descriptors are 96 bytes. */
1207 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1208 /* Our buffer size fields allow only this much */
1209 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1210 break;
1211 }
1212 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1213 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1214 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1215 /* GFX6-8 only support single channel min/max filter. */
1216 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1217 properties->filterMinmaxSingleComponentFormats = true;
1218 break;
1219 }
1220 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1221 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1222 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1223
1224 /* Shader engines. */
1225 properties->shaderEngineCount =
1226 pdevice->rad_info.max_se;
1227 properties->shaderArraysPerEngineCount =
1228 pdevice->rad_info.max_sh_per_se;
1229 properties->computeUnitsPerShaderArray =
1230 pdevice->rad_info.num_good_cu_per_sh;
1231 properties->simdPerComputeUnit = 4;
1232 properties->wavefrontsPerSimd =
1233 pdevice->rad_info.family == CHIP_TONGA ||
1234 pdevice->rad_info.family == CHIP_ICELAND ||
1235 pdevice->rad_info.family == CHIP_POLARIS10 ||
1236 pdevice->rad_info.family == CHIP_POLARIS11 ||
1237 pdevice->rad_info.family == CHIP_POLARIS12 ||
1238 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1239 properties->wavefrontSize = 64;
1240
1241 /* SGPR. */
1242 properties->sgprsPerSimd =
1243 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1244 properties->minSgprAllocation =
1245 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1246 properties->maxSgprAllocation =
1247 pdevice->rad_info.family == CHIP_TONGA ||
1248 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1249 properties->sgprAllocationGranularity =
1250 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1251
1252 /* VGPR. */
1253 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1254 properties->minVgprAllocation = 4;
1255 properties->maxVgprAllocation = 256;
1256 properties->vgprAllocationGranularity = 4;
1257 break;
1258 }
1259 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1260 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1261 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1262 properties->maxVertexAttribDivisor = UINT32_MAX;
1263 break;
1264 }
1265 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1266 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1267 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1268 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1269 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1270 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1271 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1272 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1273 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1274 properties->robustBufferAccessUpdateAfterBind = false;
1275 properties->quadDivergentImplicitLod = false;
1276
1277 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1278 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1279 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1280 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1281 32 /* sampler, largest when combined with image */ +
1282 64 /* sampled image */ +
1283 64 /* storage image */);
1284 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1285 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1286 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1287 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1288 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1289 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1290 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1291 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1292 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1293 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1294 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1295 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1296 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1297 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1298 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1299 break;
1300 }
1301 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1302 VkPhysicalDeviceProtectedMemoryProperties *properties =
1303 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1304 properties->protectedNoFault = false;
1305 break;
1306 }
1307 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1308 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1309 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1310 properties->primitiveOverestimationSize = 0;
1311 properties->maxExtraPrimitiveOverestimationSize = 0;
1312 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1313 properties->primitiveUnderestimation = VK_FALSE;
1314 properties->conservativePointAndLineRasterization = VK_FALSE;
1315 properties->degenerateTrianglesRasterized = VK_FALSE;
1316 properties->degenerateLinesRasterized = VK_FALSE;
1317 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1318 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1319 break;
1320 }
1321 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1322 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1323 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1324 properties->pciDomain = pdevice->bus_info.domain;
1325 properties->pciBus = pdevice->bus_info.bus;
1326 properties->pciDevice = pdevice->bus_info.dev;
1327 properties->pciFunction = pdevice->bus_info.func;
1328 break;
1329 }
1330 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1331 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1332 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1333
1334 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1335 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1336 strcpy(driver_props->driverName, "radv");
1337
1338 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1339 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1340 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1341 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1342
1343 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1344 .major = 1,
1345 .minor = 1,
1346 .subminor = 2,
1347 .patch = 0,
1348 };
1349 break;
1350 }
1351 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1352 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1353 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1354 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1355 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1356 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1357 properties->maxTransformFeedbackStreamDataSize = 512;
1358 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1359 properties->maxTransformFeedbackBufferDataStride = 512;
1360 properties->transformFeedbackQueries = true;
1361 properties->transformFeedbackStreamsLinesTriangles = true;
1362 properties->transformFeedbackRasterizationStreamSelect = false;
1363 properties->transformFeedbackDraw = true;
1364 break;
1365 }
1366 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1367 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1368 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1369
1370 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1371 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1372 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1373 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1374 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1375 break;
1376 }
1377 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1378 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1379 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1380 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1381 VK_SAMPLE_COUNT_4_BIT |
1382 VK_SAMPLE_COUNT_8_BIT;
1383 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1384 properties->sampleLocationCoordinateRange[0] = 0.0f;
1385 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1386 properties->sampleLocationSubPixelBits = 4;
1387 properties->variableSampleLocations = VK_FALSE;
1388 break;
1389 }
1390 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1391 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1392 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1393
1394 /* We support all of the depth resolve modes */
1395 properties->supportedDepthResolveModes =
1396 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1397 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1398 VK_RESOLVE_MODE_MIN_BIT_KHR |
1399 VK_RESOLVE_MODE_MAX_BIT_KHR;
1400
1401 /* Average doesn't make sense for stencil so we don't support that */
1402 properties->supportedStencilResolveModes =
1403 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1404 VK_RESOLVE_MODE_MIN_BIT_KHR |
1405 VK_RESOLVE_MODE_MAX_BIT_KHR;
1406
1407 properties->independentResolveNone = VK_TRUE;
1408 properties->independentResolve = VK_TRUE;
1409 break;
1410 }
1411 default:
1412 break;
1413 }
1414 }
1415 }
1416
1417 static void radv_get_physical_device_queue_family_properties(
1418 struct radv_physical_device* pdevice,
1419 uint32_t* pCount,
1420 VkQueueFamilyProperties** pQueueFamilyProperties)
1421 {
1422 int num_queue_families = 1;
1423 int idx;
1424 if (pdevice->rad_info.num_compute_rings > 0 &&
1425 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1426 num_queue_families++;
1427
1428 if (pQueueFamilyProperties == NULL) {
1429 *pCount = num_queue_families;
1430 return;
1431 }
1432
1433 if (!*pCount)
1434 return;
1435
1436 idx = 0;
1437 if (*pCount >= 1) {
1438 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1439 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1440 VK_QUEUE_COMPUTE_BIT |
1441 VK_QUEUE_TRANSFER_BIT |
1442 VK_QUEUE_SPARSE_BINDING_BIT,
1443 .queueCount = 1,
1444 .timestampValidBits = 64,
1445 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1446 };
1447 idx++;
1448 }
1449
1450 if (pdevice->rad_info.num_compute_rings > 0 &&
1451 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1452 if (*pCount > idx) {
1453 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1454 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1455 VK_QUEUE_TRANSFER_BIT |
1456 VK_QUEUE_SPARSE_BINDING_BIT,
1457 .queueCount = pdevice->rad_info.num_compute_rings,
1458 .timestampValidBits = 64,
1459 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1460 };
1461 idx++;
1462 }
1463 }
1464 *pCount = idx;
1465 }
1466
1467 void radv_GetPhysicalDeviceQueueFamilyProperties(
1468 VkPhysicalDevice physicalDevice,
1469 uint32_t* pCount,
1470 VkQueueFamilyProperties* pQueueFamilyProperties)
1471 {
1472 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1473 if (!pQueueFamilyProperties) {
1474 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1475 return;
1476 }
1477 VkQueueFamilyProperties *properties[] = {
1478 pQueueFamilyProperties + 0,
1479 pQueueFamilyProperties + 1,
1480 pQueueFamilyProperties + 2,
1481 };
1482 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1483 assert(*pCount <= 3);
1484 }
1485
1486 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1487 VkPhysicalDevice physicalDevice,
1488 uint32_t* pCount,
1489 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1490 {
1491 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1492 if (!pQueueFamilyProperties) {
1493 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1494 return;
1495 }
1496 VkQueueFamilyProperties *properties[] = {
1497 &pQueueFamilyProperties[0].queueFamilyProperties,
1498 &pQueueFamilyProperties[1].queueFamilyProperties,
1499 &pQueueFamilyProperties[2].queueFamilyProperties,
1500 };
1501 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1502 assert(*pCount <= 3);
1503 }
1504
1505 void radv_GetPhysicalDeviceMemoryProperties(
1506 VkPhysicalDevice physicalDevice,
1507 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1508 {
1509 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1510
1511 *pMemoryProperties = physical_device->memory_properties;
1512 }
1513
1514 static void
1515 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1516 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1517 {
1518 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1519 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1520 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1521 uint64_t vram_size = radv_get_vram_size(device);
1522 uint64_t gtt_size = device->rad_info.gart_size;
1523 uint64_t heap_budget, heap_usage;
1524
1525 /* For all memory heaps, the computation of budget is as follow:
1526 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1527 *
1528 * The Vulkan spec 1.1.97 says that the budget should include any
1529 * currently allocated device memory.
1530 *
1531 * Note that the application heap usages are not really accurate (eg.
1532 * in presence of shared buffers).
1533 */
1534 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1535 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1536
1537 switch (device->mem_type_indices[i]) {
1538 case RADV_MEM_TYPE_VRAM:
1539 heap_usage = device->ws->query_value(device->ws,
1540 RADEON_ALLOCATED_VRAM);
1541
1542 heap_budget = vram_size -
1543 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1544 heap_usage;
1545
1546 memoryBudget->heapBudget[heap_index] = heap_budget;
1547 memoryBudget->heapUsage[heap_index] = heap_usage;
1548 break;
1549 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1550 heap_usage = device->ws->query_value(device->ws,
1551 RADEON_ALLOCATED_VRAM_VIS);
1552
1553 heap_budget = visible_vram_size -
1554 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1555 heap_usage;
1556
1557 memoryBudget->heapBudget[heap_index] = heap_budget;
1558 memoryBudget->heapUsage[heap_index] = heap_usage;
1559 break;
1560 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1561 heap_usage = device->ws->query_value(device->ws,
1562 RADEON_ALLOCATED_GTT);
1563
1564 heap_budget = gtt_size -
1565 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1566 heap_usage;
1567
1568 memoryBudget->heapBudget[heap_index] = heap_budget;
1569 memoryBudget->heapUsage[heap_index] = heap_usage;
1570 break;
1571 default:
1572 break;
1573 }
1574 }
1575
1576 /* The heapBudget and heapUsage values must be zero for array elements
1577 * greater than or equal to
1578 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1579 */
1580 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1581 memoryBudget->heapBudget[i] = 0;
1582 memoryBudget->heapUsage[i] = 0;
1583 }
1584 }
1585
1586 void radv_GetPhysicalDeviceMemoryProperties2(
1587 VkPhysicalDevice physicalDevice,
1588 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1589 {
1590 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1591 &pMemoryProperties->memoryProperties);
1592
1593 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1594 vk_find_struct(pMemoryProperties->pNext,
1595 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1596 if (memory_budget)
1597 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1598 }
1599
1600 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1601 VkDevice _device,
1602 VkExternalMemoryHandleTypeFlagBits handleType,
1603 const void *pHostPointer,
1604 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1605 {
1606 RADV_FROM_HANDLE(radv_device, device, _device);
1607
1608 switch (handleType)
1609 {
1610 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1611 const struct radv_physical_device *physical_device = device->physical_device;
1612 uint32_t memoryTypeBits = 0;
1613 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1614 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1615 memoryTypeBits = (1 << i);
1616 break;
1617 }
1618 }
1619 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1620 return VK_SUCCESS;
1621 }
1622 default:
1623 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1624 }
1625 }
1626
1627 static enum radeon_ctx_priority
1628 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1629 {
1630 /* Default to MEDIUM when a specific global priority isn't requested */
1631 if (!pObj)
1632 return RADEON_CTX_PRIORITY_MEDIUM;
1633
1634 switch(pObj->globalPriority) {
1635 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1636 return RADEON_CTX_PRIORITY_REALTIME;
1637 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1638 return RADEON_CTX_PRIORITY_HIGH;
1639 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1640 return RADEON_CTX_PRIORITY_MEDIUM;
1641 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1642 return RADEON_CTX_PRIORITY_LOW;
1643 default:
1644 unreachable("Illegal global priority value");
1645 return RADEON_CTX_PRIORITY_INVALID;
1646 }
1647 }
1648
1649 static int
1650 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1651 uint32_t queue_family_index, int idx,
1652 VkDeviceQueueCreateFlags flags,
1653 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1654 {
1655 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1656 queue->device = device;
1657 queue->queue_family_index = queue_family_index;
1658 queue->queue_idx = idx;
1659 queue->priority = radv_get_queue_global_priority(global_priority);
1660 queue->flags = flags;
1661
1662 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1663 if (!queue->hw_ctx)
1664 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1665
1666 return VK_SUCCESS;
1667 }
1668
1669 static void
1670 radv_queue_finish(struct radv_queue *queue)
1671 {
1672 if (queue->hw_ctx)
1673 queue->device->ws->ctx_destroy(queue->hw_ctx);
1674
1675 if (queue->initial_full_flush_preamble_cs)
1676 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1677 if (queue->initial_preamble_cs)
1678 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1679 if (queue->continue_preamble_cs)
1680 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1681 if (queue->descriptor_bo)
1682 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1683 if (queue->scratch_bo)
1684 queue->device->ws->buffer_destroy(queue->scratch_bo);
1685 if (queue->esgs_ring_bo)
1686 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1687 if (queue->gsvs_ring_bo)
1688 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1689 if (queue->tess_rings_bo)
1690 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1691 if (queue->compute_scratch_bo)
1692 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1693 }
1694
1695 static void
1696 radv_bo_list_init(struct radv_bo_list *bo_list)
1697 {
1698 pthread_mutex_init(&bo_list->mutex, NULL);
1699 bo_list->list.count = bo_list->capacity = 0;
1700 bo_list->list.bos = NULL;
1701 }
1702
1703 static void
1704 radv_bo_list_finish(struct radv_bo_list *bo_list)
1705 {
1706 free(bo_list->list.bos);
1707 pthread_mutex_destroy(&bo_list->mutex);
1708 }
1709
1710 static VkResult radv_bo_list_add(struct radv_device *device,
1711 struct radeon_winsys_bo *bo)
1712 {
1713 struct radv_bo_list *bo_list = &device->bo_list;
1714
1715 if (bo->is_local)
1716 return VK_SUCCESS;
1717
1718 if (unlikely(!device->use_global_bo_list))
1719 return VK_SUCCESS;
1720
1721 pthread_mutex_lock(&bo_list->mutex);
1722 if (bo_list->list.count == bo_list->capacity) {
1723 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1724 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1725
1726 if (!data) {
1727 pthread_mutex_unlock(&bo_list->mutex);
1728 return VK_ERROR_OUT_OF_HOST_MEMORY;
1729 }
1730
1731 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1732 bo_list->capacity = capacity;
1733 }
1734
1735 bo_list->list.bos[bo_list->list.count++] = bo;
1736 pthread_mutex_unlock(&bo_list->mutex);
1737 return VK_SUCCESS;
1738 }
1739
1740 static void radv_bo_list_remove(struct radv_device *device,
1741 struct radeon_winsys_bo *bo)
1742 {
1743 struct radv_bo_list *bo_list = &device->bo_list;
1744
1745 if (bo->is_local)
1746 return;
1747
1748 if (unlikely(!device->use_global_bo_list))
1749 return;
1750
1751 pthread_mutex_lock(&bo_list->mutex);
1752 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1753 if (bo_list->list.bos[i] == bo) {
1754 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1755 --bo_list->list.count;
1756 break;
1757 }
1758 }
1759 pthread_mutex_unlock(&bo_list->mutex);
1760 }
1761
1762 static void
1763 radv_device_init_gs_info(struct radv_device *device)
1764 {
1765 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1766 device->physical_device->rad_info.family);
1767 }
1768
1769 static int radv_get_device_extension_index(const char *name)
1770 {
1771 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1772 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1773 return i;
1774 }
1775 return -1;
1776 }
1777
1778 static int
1779 radv_get_int_debug_option(const char *name, int default_value)
1780 {
1781 const char *str;
1782 int result;
1783
1784 str = getenv(name);
1785 if (!str) {
1786 result = default_value;
1787 } else {
1788 char *endptr;
1789
1790 result = strtol(str, &endptr, 0);
1791 if (str == endptr) {
1792 /* No digits founs. */
1793 result = default_value;
1794 }
1795 }
1796
1797 return result;
1798 }
1799
1800 VkResult radv_CreateDevice(
1801 VkPhysicalDevice physicalDevice,
1802 const VkDeviceCreateInfo* pCreateInfo,
1803 const VkAllocationCallbacks* pAllocator,
1804 VkDevice* pDevice)
1805 {
1806 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1807 VkResult result;
1808 struct radv_device *device;
1809
1810 bool keep_shader_info = false;
1811
1812 /* Check enabled features */
1813 if (pCreateInfo->pEnabledFeatures) {
1814 VkPhysicalDeviceFeatures supported_features;
1815 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1816 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1817 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1818 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1819 for (uint32_t i = 0; i < num_features; i++) {
1820 if (enabled_feature[i] && !supported_feature[i])
1821 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1822 }
1823 }
1824
1825 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1826 sizeof(*device), 8,
1827 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1828 if (!device)
1829 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1830
1831 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1832 device->instance = physical_device->instance;
1833 device->physical_device = physical_device;
1834
1835 device->ws = physical_device->ws;
1836 if (pAllocator)
1837 device->alloc = *pAllocator;
1838 else
1839 device->alloc = physical_device->instance->alloc;
1840
1841 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1842 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1843 int index = radv_get_device_extension_index(ext_name);
1844 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1845 vk_free(&device->alloc, device);
1846 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1847 }
1848
1849 device->enabled_extensions.extensions[index] = true;
1850 }
1851
1852 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1853
1854 /* With update after bind we can't attach bo's to the command buffer
1855 * from the descriptor set anymore, so we have to use a global BO list.
1856 */
1857 device->use_global_bo_list =
1858 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1859 device->enabled_extensions.EXT_descriptor_indexing ||
1860 device->enabled_extensions.EXT_buffer_device_address;
1861
1862 mtx_init(&device->shader_slab_mutex, mtx_plain);
1863 list_inithead(&device->shader_slabs);
1864
1865 radv_bo_list_init(&device->bo_list);
1866
1867 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1868 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1869 uint32_t qfi = queue_create->queueFamilyIndex;
1870 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1871 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1872
1873 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1874
1875 device->queues[qfi] = vk_alloc(&device->alloc,
1876 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1877 if (!device->queues[qfi]) {
1878 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1879 goto fail;
1880 }
1881
1882 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1883
1884 device->queue_count[qfi] = queue_create->queueCount;
1885
1886 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1887 result = radv_queue_init(device, &device->queues[qfi][q],
1888 qfi, q, queue_create->flags,
1889 global_priority);
1890 if (result != VK_SUCCESS)
1891 goto fail;
1892 }
1893 }
1894
1895 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1896 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1897
1898 /* Disabled and not implemented for now. */
1899 device->dfsm_allowed = device->pbb_allowed &&
1900 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1901 device->physical_device->rad_info.family == CHIP_RAVEN2);
1902
1903 #ifdef ANDROID
1904 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1905 #endif
1906
1907 /* The maximum number of scratch waves. Scratch space isn't divided
1908 * evenly between CUs. The number is only a function of the number of CUs.
1909 * We can decrease the constant to decrease the scratch buffer size.
1910 *
1911 * sctx->scratch_waves must be >= the maximum possible size of
1912 * 1 threadgroup, so that the hw doesn't hang from being unable
1913 * to start any.
1914 *
1915 * The recommended value is 4 per CU at most. Higher numbers don't
1916 * bring much benefit, but they still occupy chip resources (think
1917 * async compute). I've seen ~2% performance difference between 4 and 32.
1918 */
1919 uint32_t max_threads_per_block = 2048;
1920 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1921 max_threads_per_block / 64);
1922
1923 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1924
1925 if (device->physical_device->rad_info.chip_class >= GFX7) {
1926 /* If the KMD allows it (there is a KMD hw register for it),
1927 * allow launching waves out-of-order.
1928 */
1929 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1930 }
1931
1932 radv_device_init_gs_info(device);
1933
1934 device->tess_offchip_block_dw_size =
1935 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1936 device->has_distributed_tess =
1937 device->physical_device->rad_info.chip_class >= GFX8 &&
1938 device->physical_device->rad_info.max_se >= 2;
1939
1940 if (getenv("RADV_TRACE_FILE")) {
1941 const char *filename = getenv("RADV_TRACE_FILE");
1942
1943 keep_shader_info = true;
1944
1945 if (!radv_init_trace(device))
1946 goto fail;
1947
1948 fprintf(stderr, "*****************************************************************************\n");
1949 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1950 fprintf(stderr, "*****************************************************************************\n");
1951
1952 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1953 radv_dump_enabled_options(device, stderr);
1954 }
1955
1956 device->keep_shader_info = keep_shader_info;
1957
1958 result = radv_device_init_meta(device);
1959 if (result != VK_SUCCESS)
1960 goto fail;
1961
1962 radv_device_init_msaa(device);
1963
1964 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1965 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1966 switch (family) {
1967 case RADV_QUEUE_GENERAL:
1968 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1969 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1970 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1971 break;
1972 case RADV_QUEUE_COMPUTE:
1973 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1974 radeon_emit(device->empty_cs[family], 0);
1975 break;
1976 }
1977 device->ws->cs_finalize(device->empty_cs[family]);
1978 }
1979
1980 if (device->physical_device->rad_info.chip_class >= GFX7)
1981 cik_create_gfx_config(device);
1982
1983 VkPipelineCacheCreateInfo ci;
1984 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1985 ci.pNext = NULL;
1986 ci.flags = 0;
1987 ci.pInitialData = NULL;
1988 ci.initialDataSize = 0;
1989 VkPipelineCache pc;
1990 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1991 &ci, NULL, &pc);
1992 if (result != VK_SUCCESS)
1993 goto fail_meta;
1994
1995 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1996
1997 device->force_aniso =
1998 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1999 if (device->force_aniso >= 0) {
2000 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2001 1 << util_logbase2(device->force_aniso));
2002 }
2003
2004 *pDevice = radv_device_to_handle(device);
2005 return VK_SUCCESS;
2006
2007 fail_meta:
2008 radv_device_finish_meta(device);
2009 fail:
2010 radv_bo_list_finish(&device->bo_list);
2011
2012 if (device->trace_bo)
2013 device->ws->buffer_destroy(device->trace_bo);
2014
2015 if (device->gfx_init)
2016 device->ws->buffer_destroy(device->gfx_init);
2017
2018 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2019 for (unsigned q = 0; q < device->queue_count[i]; q++)
2020 radv_queue_finish(&device->queues[i][q]);
2021 if (device->queue_count[i])
2022 vk_free(&device->alloc, device->queues[i]);
2023 }
2024
2025 vk_free(&device->alloc, device);
2026 return result;
2027 }
2028
2029 void radv_DestroyDevice(
2030 VkDevice _device,
2031 const VkAllocationCallbacks* pAllocator)
2032 {
2033 RADV_FROM_HANDLE(radv_device, device, _device);
2034
2035 if (!device)
2036 return;
2037
2038 if (device->trace_bo)
2039 device->ws->buffer_destroy(device->trace_bo);
2040
2041 if (device->gfx_init)
2042 device->ws->buffer_destroy(device->gfx_init);
2043
2044 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2045 for (unsigned q = 0; q < device->queue_count[i]; q++)
2046 radv_queue_finish(&device->queues[i][q]);
2047 if (device->queue_count[i])
2048 vk_free(&device->alloc, device->queues[i]);
2049 if (device->empty_cs[i])
2050 device->ws->cs_destroy(device->empty_cs[i]);
2051 }
2052 radv_device_finish_meta(device);
2053
2054 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2055 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2056
2057 radv_destroy_shader_slabs(device);
2058
2059 radv_bo_list_finish(&device->bo_list);
2060 vk_free(&device->alloc, device);
2061 }
2062
2063 VkResult radv_EnumerateInstanceLayerProperties(
2064 uint32_t* pPropertyCount,
2065 VkLayerProperties* pProperties)
2066 {
2067 if (pProperties == NULL) {
2068 *pPropertyCount = 0;
2069 return VK_SUCCESS;
2070 }
2071
2072 /* None supported at this time */
2073 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2074 }
2075
2076 VkResult radv_EnumerateDeviceLayerProperties(
2077 VkPhysicalDevice physicalDevice,
2078 uint32_t* pPropertyCount,
2079 VkLayerProperties* pProperties)
2080 {
2081 if (pProperties == NULL) {
2082 *pPropertyCount = 0;
2083 return VK_SUCCESS;
2084 }
2085
2086 /* None supported at this time */
2087 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2088 }
2089
2090 void radv_GetDeviceQueue2(
2091 VkDevice _device,
2092 const VkDeviceQueueInfo2* pQueueInfo,
2093 VkQueue* pQueue)
2094 {
2095 RADV_FROM_HANDLE(radv_device, device, _device);
2096 struct radv_queue *queue;
2097
2098 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2099 if (pQueueInfo->flags != queue->flags) {
2100 /* From the Vulkan 1.1.70 spec:
2101 *
2102 * "The queue returned by vkGetDeviceQueue2 must have the same
2103 * flags value from this structure as that used at device
2104 * creation time in a VkDeviceQueueCreateInfo instance. If no
2105 * matching flags were specified at device creation time then
2106 * pQueue will return VK_NULL_HANDLE."
2107 */
2108 *pQueue = VK_NULL_HANDLE;
2109 return;
2110 }
2111
2112 *pQueue = radv_queue_to_handle(queue);
2113 }
2114
2115 void radv_GetDeviceQueue(
2116 VkDevice _device,
2117 uint32_t queueFamilyIndex,
2118 uint32_t queueIndex,
2119 VkQueue* pQueue)
2120 {
2121 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2122 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2123 .queueFamilyIndex = queueFamilyIndex,
2124 .queueIndex = queueIndex
2125 };
2126
2127 radv_GetDeviceQueue2(_device, &info, pQueue);
2128 }
2129
2130 static void
2131 fill_geom_tess_rings(struct radv_queue *queue,
2132 uint32_t *map,
2133 bool add_sample_positions,
2134 uint32_t esgs_ring_size,
2135 struct radeon_winsys_bo *esgs_ring_bo,
2136 uint32_t gsvs_ring_size,
2137 struct radeon_winsys_bo *gsvs_ring_bo,
2138 uint32_t tess_factor_ring_size,
2139 uint32_t tess_offchip_ring_offset,
2140 uint32_t tess_offchip_ring_size,
2141 struct radeon_winsys_bo *tess_rings_bo)
2142 {
2143 uint32_t *desc = &map[4];
2144
2145 if (esgs_ring_bo) {
2146 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2147
2148 /* stride 0, num records - size, add tid, swizzle, elsize4,
2149 index stride 64 */
2150 desc[0] = esgs_va;
2151 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2152 S_008F04_STRIDE(0) |
2153 S_008F04_SWIZZLE_ENABLE(true);
2154 desc[2] = esgs_ring_size;
2155 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2156 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2157 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2158 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2159 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2160 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2161 S_008F0C_ELEMENT_SIZE(1) |
2162 S_008F0C_INDEX_STRIDE(3) |
2163 S_008F0C_ADD_TID_ENABLE(true);
2164
2165 /* GS entry for ES->GS ring */
2166 /* stride 0, num records - size, elsize0,
2167 index stride 0 */
2168 desc[4] = esgs_va;
2169 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2170 S_008F04_STRIDE(0) |
2171 S_008F04_SWIZZLE_ENABLE(false);
2172 desc[6] = esgs_ring_size;
2173 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2174 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2175 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2176 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2177 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2178 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2179 S_008F0C_ELEMENT_SIZE(0) |
2180 S_008F0C_INDEX_STRIDE(0) |
2181 S_008F0C_ADD_TID_ENABLE(false);
2182 }
2183
2184 desc += 8;
2185
2186 if (gsvs_ring_bo) {
2187 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2188
2189 /* VS entry for GS->VS ring */
2190 /* stride 0, num records - size, elsize0,
2191 index stride 0 */
2192 desc[0] = gsvs_va;
2193 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2194 S_008F04_STRIDE(0) |
2195 S_008F04_SWIZZLE_ENABLE(false);
2196 desc[2] = gsvs_ring_size;
2197 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2198 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2199 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2200 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2201 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2202 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2203 S_008F0C_ELEMENT_SIZE(0) |
2204 S_008F0C_INDEX_STRIDE(0) |
2205 S_008F0C_ADD_TID_ENABLE(false);
2206
2207 /* stride gsvs_itemsize, num records 64
2208 elsize 4, index stride 16 */
2209 /* shader will patch stride and desc[2] */
2210 desc[4] = gsvs_va;
2211 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2212 S_008F04_STRIDE(0) |
2213 S_008F04_SWIZZLE_ENABLE(true);
2214 desc[6] = 0;
2215 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2216 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2217 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2218 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2219 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2220 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2221 S_008F0C_ELEMENT_SIZE(1) |
2222 S_008F0C_INDEX_STRIDE(1) |
2223 S_008F0C_ADD_TID_ENABLE(true);
2224 }
2225
2226 desc += 8;
2227
2228 if (tess_rings_bo) {
2229 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2230 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2231
2232 desc[0] = tess_va;
2233 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2234 S_008F04_STRIDE(0) |
2235 S_008F04_SWIZZLE_ENABLE(false);
2236 desc[2] = tess_factor_ring_size;
2237 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2238 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2239 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2240 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2241 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2242 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2243 S_008F0C_ELEMENT_SIZE(0) |
2244 S_008F0C_INDEX_STRIDE(0) |
2245 S_008F0C_ADD_TID_ENABLE(false);
2246
2247 desc[4] = tess_offchip_va;
2248 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2249 S_008F04_STRIDE(0) |
2250 S_008F04_SWIZZLE_ENABLE(false);
2251 desc[6] = tess_offchip_ring_size;
2252 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2253 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2254 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2255 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2256 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2257 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2258 S_008F0C_ELEMENT_SIZE(0) |
2259 S_008F0C_INDEX_STRIDE(0) |
2260 S_008F0C_ADD_TID_ENABLE(false);
2261 }
2262
2263 desc += 8;
2264
2265 if (add_sample_positions) {
2266 /* add sample positions after all rings */
2267 memcpy(desc, queue->device->sample_locations_1x, 8);
2268 desc += 2;
2269 memcpy(desc, queue->device->sample_locations_2x, 16);
2270 desc += 4;
2271 memcpy(desc, queue->device->sample_locations_4x, 32);
2272 desc += 8;
2273 memcpy(desc, queue->device->sample_locations_8x, 64);
2274 }
2275 }
2276
2277 static unsigned
2278 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2279 {
2280 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2281 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2282 device->physical_device->rad_info.family != CHIP_STONEY;
2283 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2284 unsigned max_offchip_buffers;
2285 unsigned offchip_granularity;
2286 unsigned hs_offchip_param;
2287
2288 /*
2289 * Per RadeonSI:
2290 * This must be one less than the maximum number due to a hw limitation.
2291 * Various hardware bugs need thGFX7
2292 *
2293 * Per AMDVLK:
2294 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2295 * Gfx7 should limit max_offchip_buffers to 508
2296 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2297 *
2298 * Follow AMDVLK here.
2299 */
2300 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2301 device->physical_device->rad_info.chip_class == GFX7 ||
2302 device->physical_device->rad_info.chip_class == GFX6)
2303 --max_offchip_buffers_per_se;
2304
2305 max_offchip_buffers = max_offchip_buffers_per_se *
2306 device->physical_device->rad_info.max_se;
2307
2308 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2309 * around by setting 4K granularity.
2310 */
2311 if (device->tess_offchip_block_dw_size == 4096) {
2312 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2313 offchip_granularity = V_03093C_X_4K_DWORDS;
2314 } else {
2315 assert(device->tess_offchip_block_dw_size == 8192);
2316 offchip_granularity = V_03093C_X_8K_DWORDS;
2317 }
2318
2319 switch (device->physical_device->rad_info.chip_class) {
2320 case GFX6:
2321 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2322 break;
2323 case GFX7:
2324 case GFX8:
2325 case GFX9:
2326 default:
2327 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2328 break;
2329 }
2330
2331 *max_offchip_buffers_p = max_offchip_buffers;
2332 if (device->physical_device->rad_info.chip_class >= GFX7) {
2333 if (device->physical_device->rad_info.chip_class >= GFX8)
2334 --max_offchip_buffers;
2335 hs_offchip_param =
2336 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2337 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2338 } else {
2339 hs_offchip_param =
2340 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2341 }
2342 return hs_offchip_param;
2343 }
2344
2345 static void
2346 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2347 struct radeon_winsys_bo *esgs_ring_bo,
2348 uint32_t esgs_ring_size,
2349 struct radeon_winsys_bo *gsvs_ring_bo,
2350 uint32_t gsvs_ring_size)
2351 {
2352 if (!esgs_ring_bo && !gsvs_ring_bo)
2353 return;
2354
2355 if (esgs_ring_bo)
2356 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2357
2358 if (gsvs_ring_bo)
2359 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2360
2361 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2362 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2363 radeon_emit(cs, esgs_ring_size >> 8);
2364 radeon_emit(cs, gsvs_ring_size >> 8);
2365 } else {
2366 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2367 radeon_emit(cs, esgs_ring_size >> 8);
2368 radeon_emit(cs, gsvs_ring_size >> 8);
2369 }
2370 }
2371
2372 static void
2373 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2374 unsigned hs_offchip_param, unsigned tf_ring_size,
2375 struct radeon_winsys_bo *tess_rings_bo)
2376 {
2377 uint64_t tf_va;
2378
2379 if (!tess_rings_bo)
2380 return;
2381
2382 tf_va = radv_buffer_get_va(tess_rings_bo);
2383
2384 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2385
2386 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2387 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2388 S_030938_SIZE(tf_ring_size / 4));
2389 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2390 tf_va >> 8);
2391
2392 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2393 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2394 S_030984_BASE_HI(tf_va >> 40));
2395 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2396 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2397 S_030944_BASE_HI(tf_va >> 40));
2398 }
2399 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2400 hs_offchip_param);
2401 } else {
2402 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2403 S_008988_SIZE(tf_ring_size / 4));
2404 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2405 tf_va >> 8);
2406 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2407 hs_offchip_param);
2408 }
2409 }
2410
2411 static void
2412 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2413 struct radeon_winsys_bo *compute_scratch_bo)
2414 {
2415 uint64_t scratch_va;
2416
2417 if (!compute_scratch_bo)
2418 return;
2419
2420 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2421
2422 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2423
2424 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2425 radeon_emit(cs, scratch_va);
2426 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2427 S_008F04_SWIZZLE_ENABLE(1));
2428 }
2429
2430 static void
2431 radv_emit_global_shader_pointers(struct radv_queue *queue,
2432 struct radeon_cmdbuf *cs,
2433 struct radeon_winsys_bo *descriptor_bo)
2434 {
2435 uint64_t va;
2436
2437 if (!descriptor_bo)
2438 return;
2439
2440 va = radv_buffer_get_va(descriptor_bo);
2441
2442 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2443
2444 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2445 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2446 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2447 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2448 R_00B430_SPI_SHADER_USER_DATA_HS_0};
2449
2450 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2451 radv_emit_shader_pointer(queue->device, cs, regs[i],
2452 va, true);
2453 }
2454 } else if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2455 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2456 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2457 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2458 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2459
2460 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2461 radv_emit_shader_pointer(queue->device, cs, regs[i],
2462 va, true);
2463 }
2464 } else {
2465 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2466 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2467 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2468 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2469 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2470 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2471
2472 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2473 radv_emit_shader_pointer(queue->device, cs, regs[i],
2474 va, true);
2475 }
2476 }
2477 }
2478
2479 static void
2480 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2481 {
2482 struct radv_device *device = queue->device;
2483
2484 if (device->gfx_init) {
2485 uint64_t va = radv_buffer_get_va(device->gfx_init);
2486
2487 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2488 radeon_emit(cs, va);
2489 radeon_emit(cs, va >> 32);
2490 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2491
2492 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2493 } else {
2494 struct radv_physical_device *physical_device = device->physical_device;
2495 si_emit_graphics(physical_device, cs);
2496 }
2497 }
2498
2499 static void
2500 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2501 {
2502 struct radv_physical_device *physical_device = queue->device->physical_device;
2503 si_emit_compute(physical_device, cs);
2504 }
2505
2506 static VkResult
2507 radv_get_preamble_cs(struct radv_queue *queue,
2508 uint32_t scratch_size,
2509 uint32_t compute_scratch_size,
2510 uint32_t esgs_ring_size,
2511 uint32_t gsvs_ring_size,
2512 bool needs_tess_rings,
2513 bool needs_sample_positions,
2514 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2515 struct radeon_cmdbuf **initial_preamble_cs,
2516 struct radeon_cmdbuf **continue_preamble_cs)
2517 {
2518 struct radeon_winsys_bo *scratch_bo = NULL;
2519 struct radeon_winsys_bo *descriptor_bo = NULL;
2520 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2521 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2522 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2523 struct radeon_winsys_bo *tess_rings_bo = NULL;
2524 struct radeon_cmdbuf *dest_cs[3] = {0};
2525 bool add_tess_rings = false, add_sample_positions = false;
2526 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2527 unsigned max_offchip_buffers;
2528 unsigned hs_offchip_param = 0;
2529 unsigned tess_offchip_ring_offset;
2530 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2531 if (!queue->has_tess_rings) {
2532 if (needs_tess_rings)
2533 add_tess_rings = true;
2534 }
2535 if (!queue->has_sample_positions) {
2536 if (needs_sample_positions)
2537 add_sample_positions = true;
2538 }
2539 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2540 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2541 &max_offchip_buffers);
2542 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2543 tess_offchip_ring_size = max_offchip_buffers *
2544 queue->device->tess_offchip_block_dw_size * 4;
2545
2546 if (scratch_size <= queue->scratch_size &&
2547 compute_scratch_size <= queue->compute_scratch_size &&
2548 esgs_ring_size <= queue->esgs_ring_size &&
2549 gsvs_ring_size <= queue->gsvs_ring_size &&
2550 !add_tess_rings && !add_sample_positions &&
2551 queue->initial_preamble_cs) {
2552 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2553 *initial_preamble_cs = queue->initial_preamble_cs;
2554 *continue_preamble_cs = queue->continue_preamble_cs;
2555 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2556 *continue_preamble_cs = NULL;
2557 return VK_SUCCESS;
2558 }
2559
2560 if (scratch_size > queue->scratch_size) {
2561 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2562 scratch_size,
2563 4096,
2564 RADEON_DOMAIN_VRAM,
2565 ring_bo_flags,
2566 RADV_BO_PRIORITY_SCRATCH);
2567 if (!scratch_bo)
2568 goto fail;
2569 } else
2570 scratch_bo = queue->scratch_bo;
2571
2572 if (compute_scratch_size > queue->compute_scratch_size) {
2573 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2574 compute_scratch_size,
2575 4096,
2576 RADEON_DOMAIN_VRAM,
2577 ring_bo_flags,
2578 RADV_BO_PRIORITY_SCRATCH);
2579 if (!compute_scratch_bo)
2580 goto fail;
2581
2582 } else
2583 compute_scratch_bo = queue->compute_scratch_bo;
2584
2585 if (esgs_ring_size > queue->esgs_ring_size) {
2586 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2587 esgs_ring_size,
2588 4096,
2589 RADEON_DOMAIN_VRAM,
2590 ring_bo_flags,
2591 RADV_BO_PRIORITY_SCRATCH);
2592 if (!esgs_ring_bo)
2593 goto fail;
2594 } else {
2595 esgs_ring_bo = queue->esgs_ring_bo;
2596 esgs_ring_size = queue->esgs_ring_size;
2597 }
2598
2599 if (gsvs_ring_size > queue->gsvs_ring_size) {
2600 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2601 gsvs_ring_size,
2602 4096,
2603 RADEON_DOMAIN_VRAM,
2604 ring_bo_flags,
2605 RADV_BO_PRIORITY_SCRATCH);
2606 if (!gsvs_ring_bo)
2607 goto fail;
2608 } else {
2609 gsvs_ring_bo = queue->gsvs_ring_bo;
2610 gsvs_ring_size = queue->gsvs_ring_size;
2611 }
2612
2613 if (add_tess_rings) {
2614 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2615 tess_offchip_ring_offset + tess_offchip_ring_size,
2616 256,
2617 RADEON_DOMAIN_VRAM,
2618 ring_bo_flags,
2619 RADV_BO_PRIORITY_SCRATCH);
2620 if (!tess_rings_bo)
2621 goto fail;
2622 } else {
2623 tess_rings_bo = queue->tess_rings_bo;
2624 }
2625
2626 if (scratch_bo != queue->scratch_bo ||
2627 esgs_ring_bo != queue->esgs_ring_bo ||
2628 gsvs_ring_bo != queue->gsvs_ring_bo ||
2629 tess_rings_bo != queue->tess_rings_bo ||
2630 add_sample_positions) {
2631 uint32_t size = 0;
2632 if (gsvs_ring_bo || esgs_ring_bo ||
2633 tess_rings_bo || add_sample_positions) {
2634 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2635 if (add_sample_positions)
2636 size += 128; /* 64+32+16+8 = 120 bytes */
2637 }
2638 else if (scratch_bo)
2639 size = 8; /* 2 dword */
2640
2641 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2642 size,
2643 4096,
2644 RADEON_DOMAIN_VRAM,
2645 RADEON_FLAG_CPU_ACCESS |
2646 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2647 RADEON_FLAG_READ_ONLY,
2648 RADV_BO_PRIORITY_DESCRIPTOR);
2649 if (!descriptor_bo)
2650 goto fail;
2651 } else
2652 descriptor_bo = queue->descriptor_bo;
2653
2654 if (descriptor_bo != queue->descriptor_bo) {
2655 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2656
2657 if (scratch_bo) {
2658 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2659 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2660 S_008F04_SWIZZLE_ENABLE(1);
2661 map[0] = scratch_va;
2662 map[1] = rsrc1;
2663 }
2664
2665 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2666 fill_geom_tess_rings(queue, map, add_sample_positions,
2667 esgs_ring_size, esgs_ring_bo,
2668 gsvs_ring_size, gsvs_ring_bo,
2669 tess_factor_ring_size,
2670 tess_offchip_ring_offset,
2671 tess_offchip_ring_size,
2672 tess_rings_bo);
2673
2674 queue->device->ws->buffer_unmap(descriptor_bo);
2675 }
2676
2677 for(int i = 0; i < 3; ++i) {
2678 struct radeon_cmdbuf *cs = NULL;
2679 cs = queue->device->ws->cs_create(queue->device->ws,
2680 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2681 if (!cs)
2682 goto fail;
2683
2684 dest_cs[i] = cs;
2685
2686 if (scratch_bo)
2687 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2688
2689 /* Emit initial configuration. */
2690 switch (queue->queue_family_index) {
2691 case RADV_QUEUE_GENERAL:
2692 radv_init_graphics_state(cs, queue);
2693 break;
2694 case RADV_QUEUE_COMPUTE:
2695 radv_init_compute_state(cs, queue);
2696 break;
2697 case RADV_QUEUE_TRANSFER:
2698 break;
2699 }
2700
2701 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2702 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2703 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2704 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2705 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2706 }
2707
2708 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2709 gsvs_ring_bo, gsvs_ring_size);
2710 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2711 tess_factor_ring_size, tess_rings_bo);
2712 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2713 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2714
2715 if (i == 0) {
2716 si_cs_emit_cache_flush(cs,
2717 queue->device->physical_device->rad_info.chip_class,
2718 NULL, 0,
2719 queue->queue_family_index == RING_COMPUTE &&
2720 queue->device->physical_device->rad_info.chip_class >= GFX7,
2721 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2722 RADV_CMD_FLAG_INV_ICACHE |
2723 RADV_CMD_FLAG_INV_SCACHE |
2724 RADV_CMD_FLAG_INV_VCACHE |
2725 RADV_CMD_FLAG_INV_L2 |
2726 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2727 } else if (i == 1) {
2728 si_cs_emit_cache_flush(cs,
2729 queue->device->physical_device->rad_info.chip_class,
2730 NULL, 0,
2731 queue->queue_family_index == RING_COMPUTE &&
2732 queue->device->physical_device->rad_info.chip_class >= GFX7,
2733 RADV_CMD_FLAG_INV_ICACHE |
2734 RADV_CMD_FLAG_INV_SCACHE |
2735 RADV_CMD_FLAG_INV_VCACHE |
2736 RADV_CMD_FLAG_INV_L2 |
2737 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2738 }
2739
2740 if (!queue->device->ws->cs_finalize(cs))
2741 goto fail;
2742 }
2743
2744 if (queue->initial_full_flush_preamble_cs)
2745 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2746
2747 if (queue->initial_preamble_cs)
2748 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2749
2750 if (queue->continue_preamble_cs)
2751 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2752
2753 queue->initial_full_flush_preamble_cs = dest_cs[0];
2754 queue->initial_preamble_cs = dest_cs[1];
2755 queue->continue_preamble_cs = dest_cs[2];
2756
2757 if (scratch_bo != queue->scratch_bo) {
2758 if (queue->scratch_bo)
2759 queue->device->ws->buffer_destroy(queue->scratch_bo);
2760 queue->scratch_bo = scratch_bo;
2761 queue->scratch_size = scratch_size;
2762 }
2763
2764 if (compute_scratch_bo != queue->compute_scratch_bo) {
2765 if (queue->compute_scratch_bo)
2766 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2767 queue->compute_scratch_bo = compute_scratch_bo;
2768 queue->compute_scratch_size = compute_scratch_size;
2769 }
2770
2771 if (esgs_ring_bo != queue->esgs_ring_bo) {
2772 if (queue->esgs_ring_bo)
2773 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2774 queue->esgs_ring_bo = esgs_ring_bo;
2775 queue->esgs_ring_size = esgs_ring_size;
2776 }
2777
2778 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2779 if (queue->gsvs_ring_bo)
2780 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2781 queue->gsvs_ring_bo = gsvs_ring_bo;
2782 queue->gsvs_ring_size = gsvs_ring_size;
2783 }
2784
2785 if (tess_rings_bo != queue->tess_rings_bo) {
2786 queue->tess_rings_bo = tess_rings_bo;
2787 queue->has_tess_rings = true;
2788 }
2789
2790 if (descriptor_bo != queue->descriptor_bo) {
2791 if (queue->descriptor_bo)
2792 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2793
2794 queue->descriptor_bo = descriptor_bo;
2795 }
2796
2797 if (add_sample_positions)
2798 queue->has_sample_positions = true;
2799
2800 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2801 *initial_preamble_cs = queue->initial_preamble_cs;
2802 *continue_preamble_cs = queue->continue_preamble_cs;
2803 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2804 *continue_preamble_cs = NULL;
2805 return VK_SUCCESS;
2806 fail:
2807 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2808 if (dest_cs[i])
2809 queue->device->ws->cs_destroy(dest_cs[i]);
2810 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2811 queue->device->ws->buffer_destroy(descriptor_bo);
2812 if (scratch_bo && scratch_bo != queue->scratch_bo)
2813 queue->device->ws->buffer_destroy(scratch_bo);
2814 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2815 queue->device->ws->buffer_destroy(compute_scratch_bo);
2816 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2817 queue->device->ws->buffer_destroy(esgs_ring_bo);
2818 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2819 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2820 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2821 queue->device->ws->buffer_destroy(tess_rings_bo);
2822 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2823 }
2824
2825 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2826 struct radv_winsys_sem_counts *counts,
2827 int num_sems,
2828 const VkSemaphore *sems,
2829 VkFence _fence,
2830 bool reset_temp)
2831 {
2832 int syncobj_idx = 0, sem_idx = 0;
2833
2834 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2835 return VK_SUCCESS;
2836
2837 for (uint32_t i = 0; i < num_sems; i++) {
2838 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2839
2840 if (sem->temp_syncobj || sem->syncobj)
2841 counts->syncobj_count++;
2842 else
2843 counts->sem_count++;
2844 }
2845
2846 if (_fence != VK_NULL_HANDLE) {
2847 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2848 if (fence->temp_syncobj || fence->syncobj)
2849 counts->syncobj_count++;
2850 }
2851
2852 if (counts->syncobj_count) {
2853 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2854 if (!counts->syncobj)
2855 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2856 }
2857
2858 if (counts->sem_count) {
2859 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2860 if (!counts->sem) {
2861 free(counts->syncobj);
2862 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2863 }
2864 }
2865
2866 for (uint32_t i = 0; i < num_sems; i++) {
2867 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2868
2869 if (sem->temp_syncobj) {
2870 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2871 }
2872 else if (sem->syncobj)
2873 counts->syncobj[syncobj_idx++] = sem->syncobj;
2874 else {
2875 assert(sem->sem);
2876 counts->sem[sem_idx++] = sem->sem;
2877 }
2878 }
2879
2880 if (_fence != VK_NULL_HANDLE) {
2881 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2882 if (fence->temp_syncobj)
2883 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2884 else if (fence->syncobj)
2885 counts->syncobj[syncobj_idx++] = fence->syncobj;
2886 }
2887
2888 return VK_SUCCESS;
2889 }
2890
2891 static void
2892 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2893 {
2894 free(sem_info->wait.syncobj);
2895 free(sem_info->wait.sem);
2896 free(sem_info->signal.syncobj);
2897 free(sem_info->signal.sem);
2898 }
2899
2900
2901 static void radv_free_temp_syncobjs(struct radv_device *device,
2902 int num_sems,
2903 const VkSemaphore *sems)
2904 {
2905 for (uint32_t i = 0; i < num_sems; i++) {
2906 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2907
2908 if (sem->temp_syncobj) {
2909 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2910 sem->temp_syncobj = 0;
2911 }
2912 }
2913 }
2914
2915 static VkResult
2916 radv_alloc_sem_info(struct radv_instance *instance,
2917 struct radv_winsys_sem_info *sem_info,
2918 int num_wait_sems,
2919 const VkSemaphore *wait_sems,
2920 int num_signal_sems,
2921 const VkSemaphore *signal_sems,
2922 VkFence fence)
2923 {
2924 VkResult ret;
2925 memset(sem_info, 0, sizeof(*sem_info));
2926
2927 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2928 if (ret)
2929 return ret;
2930 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2931 if (ret)
2932 radv_free_sem_info(sem_info);
2933
2934 /* caller can override these */
2935 sem_info->cs_emit_wait = true;
2936 sem_info->cs_emit_signal = true;
2937 return ret;
2938 }
2939
2940 /* Signals fence as soon as all the work currently put on queue is done. */
2941 static VkResult radv_signal_fence(struct radv_queue *queue,
2942 struct radv_fence *fence)
2943 {
2944 int ret;
2945 VkResult result;
2946 struct radv_winsys_sem_info sem_info;
2947
2948 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2949 radv_fence_to_handle(fence));
2950 if (result != VK_SUCCESS)
2951 return result;
2952
2953 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2954 &queue->device->empty_cs[queue->queue_family_index],
2955 1, NULL, NULL, &sem_info, NULL,
2956 false, fence->fence);
2957 radv_free_sem_info(&sem_info);
2958
2959 if (ret)
2960 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2961
2962 return VK_SUCCESS;
2963 }
2964
2965 VkResult radv_QueueSubmit(
2966 VkQueue _queue,
2967 uint32_t submitCount,
2968 const VkSubmitInfo* pSubmits,
2969 VkFence _fence)
2970 {
2971 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2972 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2973 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2974 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2975 int ret;
2976 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2977 uint32_t scratch_size = 0;
2978 uint32_t compute_scratch_size = 0;
2979 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2980 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2981 VkResult result;
2982 bool fence_emitted = false;
2983 bool tess_rings_needed = false;
2984 bool sample_positions_needed = false;
2985
2986 /* Do this first so failing to allocate scratch buffers can't result in
2987 * partially executed submissions. */
2988 for (uint32_t i = 0; i < submitCount; i++) {
2989 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2990 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2991 pSubmits[i].pCommandBuffers[j]);
2992
2993 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2994 compute_scratch_size = MAX2(compute_scratch_size,
2995 cmd_buffer->compute_scratch_size_needed);
2996 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2997 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2998 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2999 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3000 }
3001 }
3002
3003 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3004 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3005 sample_positions_needed, &initial_flush_preamble_cs,
3006 &initial_preamble_cs, &continue_preamble_cs);
3007 if (result != VK_SUCCESS)
3008 return result;
3009
3010 for (uint32_t i = 0; i < submitCount; i++) {
3011 struct radeon_cmdbuf **cs_array;
3012 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3013 bool can_patch = true;
3014 uint32_t advance;
3015 struct radv_winsys_sem_info sem_info;
3016
3017 result = radv_alloc_sem_info(queue->device->instance,
3018 &sem_info,
3019 pSubmits[i].waitSemaphoreCount,
3020 pSubmits[i].pWaitSemaphores,
3021 pSubmits[i].signalSemaphoreCount,
3022 pSubmits[i].pSignalSemaphores,
3023 _fence);
3024 if (result != VK_SUCCESS)
3025 return result;
3026
3027 if (!pSubmits[i].commandBufferCount) {
3028 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3029 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3030 &queue->device->empty_cs[queue->queue_family_index],
3031 1, NULL, NULL,
3032 &sem_info, NULL,
3033 false, base_fence);
3034 if (ret) {
3035 radv_loge("failed to submit CS %d\n", i);
3036 abort();
3037 }
3038 fence_emitted = true;
3039 }
3040 radv_free_sem_info(&sem_info);
3041 continue;
3042 }
3043
3044 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3045 (pSubmits[i].commandBufferCount));
3046
3047 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3048 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3049 pSubmits[i].pCommandBuffers[j]);
3050 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3051
3052 cs_array[j] = cmd_buffer->cs;
3053 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3054 can_patch = false;
3055
3056 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3057 }
3058
3059 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3060 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3061 const struct radv_winsys_bo_list *bo_list = NULL;
3062
3063 advance = MIN2(max_cs_submission,
3064 pSubmits[i].commandBufferCount - j);
3065
3066 if (queue->device->trace_bo)
3067 *queue->device->trace_id_ptr = 0;
3068
3069 sem_info.cs_emit_wait = j == 0;
3070 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3071
3072 if (unlikely(queue->device->use_global_bo_list)) {
3073 pthread_mutex_lock(&queue->device->bo_list.mutex);
3074 bo_list = &queue->device->bo_list.list;
3075 }
3076
3077 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3078 advance, initial_preamble, continue_preamble_cs,
3079 &sem_info, bo_list,
3080 can_patch, base_fence);
3081
3082 if (unlikely(queue->device->use_global_bo_list))
3083 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3084
3085 if (ret) {
3086 radv_loge("failed to submit CS %d\n", i);
3087 abort();
3088 }
3089 fence_emitted = true;
3090 if (queue->device->trace_bo) {
3091 radv_check_gpu_hangs(queue, cs_array[j]);
3092 }
3093 }
3094
3095 radv_free_temp_syncobjs(queue->device,
3096 pSubmits[i].waitSemaphoreCount,
3097 pSubmits[i].pWaitSemaphores);
3098 radv_free_sem_info(&sem_info);
3099 free(cs_array);
3100 }
3101
3102 if (fence) {
3103 if (!fence_emitted) {
3104 result = radv_signal_fence(queue, fence);
3105 if (result != VK_SUCCESS)
3106 return result;
3107 }
3108 }
3109
3110 return VK_SUCCESS;
3111 }
3112
3113 VkResult radv_QueueWaitIdle(
3114 VkQueue _queue)
3115 {
3116 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3117
3118 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3119 radv_queue_family_to_ring(queue->queue_family_index),
3120 queue->queue_idx);
3121 return VK_SUCCESS;
3122 }
3123
3124 VkResult radv_DeviceWaitIdle(
3125 VkDevice _device)
3126 {
3127 RADV_FROM_HANDLE(radv_device, device, _device);
3128
3129 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3130 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3131 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3132 }
3133 }
3134 return VK_SUCCESS;
3135 }
3136
3137 VkResult radv_EnumerateInstanceExtensionProperties(
3138 const char* pLayerName,
3139 uint32_t* pPropertyCount,
3140 VkExtensionProperties* pProperties)
3141 {
3142 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3143
3144 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3145 if (radv_supported_instance_extensions.extensions[i]) {
3146 vk_outarray_append(&out, prop) {
3147 *prop = radv_instance_extensions[i];
3148 }
3149 }
3150 }
3151
3152 return vk_outarray_status(&out);
3153 }
3154
3155 VkResult radv_EnumerateDeviceExtensionProperties(
3156 VkPhysicalDevice physicalDevice,
3157 const char* pLayerName,
3158 uint32_t* pPropertyCount,
3159 VkExtensionProperties* pProperties)
3160 {
3161 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3162 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3163
3164 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3165 if (device->supported_extensions.extensions[i]) {
3166 vk_outarray_append(&out, prop) {
3167 *prop = radv_device_extensions[i];
3168 }
3169 }
3170 }
3171
3172 return vk_outarray_status(&out);
3173 }
3174
3175 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3176 VkInstance _instance,
3177 const char* pName)
3178 {
3179 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3180
3181 return radv_lookup_entrypoint_checked(pName,
3182 instance ? instance->apiVersion : 0,
3183 instance ? &instance->enabled_extensions : NULL,
3184 NULL);
3185 }
3186
3187 /* The loader wants us to expose a second GetInstanceProcAddr function
3188 * to work around certain LD_PRELOAD issues seen in apps.
3189 */
3190 PUBLIC
3191 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3192 VkInstance instance,
3193 const char* pName);
3194
3195 PUBLIC
3196 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3197 VkInstance instance,
3198 const char* pName)
3199 {
3200 return radv_GetInstanceProcAddr(instance, pName);
3201 }
3202
3203 PUBLIC
3204 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3205 VkInstance _instance,
3206 const char* pName);
3207
3208 PUBLIC
3209 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3210 VkInstance _instance,
3211 const char* pName)
3212 {
3213 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3214
3215 return radv_lookup_physical_device_entrypoint_checked(pName,
3216 instance ? instance->apiVersion : 0,
3217 instance ? &instance->enabled_extensions : NULL);
3218 }
3219
3220 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3221 VkDevice _device,
3222 const char* pName)
3223 {
3224 RADV_FROM_HANDLE(radv_device, device, _device);
3225
3226 return radv_lookup_entrypoint_checked(pName,
3227 device->instance->apiVersion,
3228 &device->instance->enabled_extensions,
3229 &device->enabled_extensions);
3230 }
3231
3232 bool radv_get_memory_fd(struct radv_device *device,
3233 struct radv_device_memory *memory,
3234 int *pFD)
3235 {
3236 struct radeon_bo_metadata metadata;
3237
3238 if (memory->image) {
3239 radv_init_metadata(device, memory->image, &metadata);
3240 device->ws->buffer_set_metadata(memory->bo, &metadata);
3241 }
3242
3243 return device->ws->buffer_get_fd(device->ws, memory->bo,
3244 pFD);
3245 }
3246
3247 static VkResult radv_alloc_memory(struct radv_device *device,
3248 const VkMemoryAllocateInfo* pAllocateInfo,
3249 const VkAllocationCallbacks* pAllocator,
3250 VkDeviceMemory* pMem)
3251 {
3252 struct radv_device_memory *mem;
3253 VkResult result;
3254 enum radeon_bo_domain domain;
3255 uint32_t flags = 0;
3256 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3257
3258 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3259
3260 if (pAllocateInfo->allocationSize == 0) {
3261 /* Apparently, this is allowed */
3262 *pMem = VK_NULL_HANDLE;
3263 return VK_SUCCESS;
3264 }
3265
3266 const VkImportMemoryFdInfoKHR *import_info =
3267 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3268 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3269 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3270 const VkExportMemoryAllocateInfo *export_info =
3271 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3272 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3273 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3274
3275 const struct wsi_memory_allocate_info *wsi_info =
3276 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3277
3278 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3279 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3280 if (mem == NULL)
3281 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3282
3283 if (wsi_info && wsi_info->implicit_sync)
3284 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3285
3286 if (dedicate_info) {
3287 mem->image = radv_image_from_handle(dedicate_info->image);
3288 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3289 } else {
3290 mem->image = NULL;
3291 mem->buffer = NULL;
3292 }
3293
3294 float priority_float = 0.5;
3295 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3296 vk_find_struct_const(pAllocateInfo->pNext,
3297 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3298 if (priority_ext)
3299 priority_float = priority_ext->priority;
3300
3301 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3302 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3303
3304 mem->user_ptr = NULL;
3305
3306 if (import_info) {
3307 assert(import_info->handleType ==
3308 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3309 import_info->handleType ==
3310 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3311 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3312 priority, NULL, NULL);
3313 if (!mem->bo) {
3314 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3315 goto fail;
3316 } else {
3317 close(import_info->fd);
3318 }
3319 } else if (host_ptr_info) {
3320 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3321 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3322 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3323 pAllocateInfo->allocationSize,
3324 priority);
3325 if (!mem->bo) {
3326 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3327 goto fail;
3328 } else {
3329 mem->user_ptr = host_ptr_info->pHostPointer;
3330 }
3331 } else {
3332 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3333 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3334 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3335 domain = RADEON_DOMAIN_GTT;
3336 else
3337 domain = RADEON_DOMAIN_VRAM;
3338
3339 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3340 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3341 else
3342 flags |= RADEON_FLAG_CPU_ACCESS;
3343
3344 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3345 flags |= RADEON_FLAG_GTT_WC;
3346
3347 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3348 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3349 if (device->use_global_bo_list) {
3350 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3351 }
3352 }
3353
3354 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3355 domain, flags, priority);
3356
3357 if (!mem->bo) {
3358 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3359 goto fail;
3360 }
3361 mem->type_index = mem_type_index;
3362 }
3363
3364 result = radv_bo_list_add(device, mem->bo);
3365 if (result != VK_SUCCESS)
3366 goto fail_bo;
3367
3368 *pMem = radv_device_memory_to_handle(mem);
3369
3370 return VK_SUCCESS;
3371
3372 fail_bo:
3373 device->ws->buffer_destroy(mem->bo);
3374 fail:
3375 vk_free2(&device->alloc, pAllocator, mem);
3376
3377 return result;
3378 }
3379
3380 VkResult radv_AllocateMemory(
3381 VkDevice _device,
3382 const VkMemoryAllocateInfo* pAllocateInfo,
3383 const VkAllocationCallbacks* pAllocator,
3384 VkDeviceMemory* pMem)
3385 {
3386 RADV_FROM_HANDLE(radv_device, device, _device);
3387 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3388 }
3389
3390 void radv_FreeMemory(
3391 VkDevice _device,
3392 VkDeviceMemory _mem,
3393 const VkAllocationCallbacks* pAllocator)
3394 {
3395 RADV_FROM_HANDLE(radv_device, device, _device);
3396 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3397
3398 if (mem == NULL)
3399 return;
3400
3401 radv_bo_list_remove(device, mem->bo);
3402 device->ws->buffer_destroy(mem->bo);
3403 mem->bo = NULL;
3404
3405 vk_free2(&device->alloc, pAllocator, mem);
3406 }
3407
3408 VkResult radv_MapMemory(
3409 VkDevice _device,
3410 VkDeviceMemory _memory,
3411 VkDeviceSize offset,
3412 VkDeviceSize size,
3413 VkMemoryMapFlags flags,
3414 void** ppData)
3415 {
3416 RADV_FROM_HANDLE(radv_device, device, _device);
3417 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3418
3419 if (mem == NULL) {
3420 *ppData = NULL;
3421 return VK_SUCCESS;
3422 }
3423
3424 if (mem->user_ptr)
3425 *ppData = mem->user_ptr;
3426 else
3427 *ppData = device->ws->buffer_map(mem->bo);
3428
3429 if (*ppData) {
3430 *ppData += offset;
3431 return VK_SUCCESS;
3432 }
3433
3434 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3435 }
3436
3437 void radv_UnmapMemory(
3438 VkDevice _device,
3439 VkDeviceMemory _memory)
3440 {
3441 RADV_FROM_HANDLE(radv_device, device, _device);
3442 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3443
3444 if (mem == NULL)
3445 return;
3446
3447 if (mem->user_ptr == NULL)
3448 device->ws->buffer_unmap(mem->bo);
3449 }
3450
3451 VkResult radv_FlushMappedMemoryRanges(
3452 VkDevice _device,
3453 uint32_t memoryRangeCount,
3454 const VkMappedMemoryRange* pMemoryRanges)
3455 {
3456 return VK_SUCCESS;
3457 }
3458
3459 VkResult radv_InvalidateMappedMemoryRanges(
3460 VkDevice _device,
3461 uint32_t memoryRangeCount,
3462 const VkMappedMemoryRange* pMemoryRanges)
3463 {
3464 return VK_SUCCESS;
3465 }
3466
3467 void radv_GetBufferMemoryRequirements(
3468 VkDevice _device,
3469 VkBuffer _buffer,
3470 VkMemoryRequirements* pMemoryRequirements)
3471 {
3472 RADV_FROM_HANDLE(radv_device, device, _device);
3473 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3474
3475 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3476
3477 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3478 pMemoryRequirements->alignment = 4096;
3479 else
3480 pMemoryRequirements->alignment = 16;
3481
3482 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3483 }
3484
3485 void radv_GetBufferMemoryRequirements2(
3486 VkDevice device,
3487 const VkBufferMemoryRequirementsInfo2 *pInfo,
3488 VkMemoryRequirements2 *pMemoryRequirements)
3489 {
3490 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3491 &pMemoryRequirements->memoryRequirements);
3492 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3493 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3494 switch (ext->sType) {
3495 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3496 VkMemoryDedicatedRequirements *req =
3497 (VkMemoryDedicatedRequirements *) ext;
3498 req->requiresDedicatedAllocation = buffer->shareable;
3499 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3500 break;
3501 }
3502 default:
3503 break;
3504 }
3505 }
3506 }
3507
3508 void radv_GetImageMemoryRequirements(
3509 VkDevice _device,
3510 VkImage _image,
3511 VkMemoryRequirements* pMemoryRequirements)
3512 {
3513 RADV_FROM_HANDLE(radv_device, device, _device);
3514 RADV_FROM_HANDLE(radv_image, image, _image);
3515
3516 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3517
3518 pMemoryRequirements->size = image->size;
3519 pMemoryRequirements->alignment = image->alignment;
3520 }
3521
3522 void radv_GetImageMemoryRequirements2(
3523 VkDevice device,
3524 const VkImageMemoryRequirementsInfo2 *pInfo,
3525 VkMemoryRequirements2 *pMemoryRequirements)
3526 {
3527 radv_GetImageMemoryRequirements(device, pInfo->image,
3528 &pMemoryRequirements->memoryRequirements);
3529
3530 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3531
3532 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3533 switch (ext->sType) {
3534 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3535 VkMemoryDedicatedRequirements *req =
3536 (VkMemoryDedicatedRequirements *) ext;
3537 req->requiresDedicatedAllocation = image->shareable;
3538 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3539 break;
3540 }
3541 default:
3542 break;
3543 }
3544 }
3545 }
3546
3547 void radv_GetImageSparseMemoryRequirements(
3548 VkDevice device,
3549 VkImage image,
3550 uint32_t* pSparseMemoryRequirementCount,
3551 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3552 {
3553 stub();
3554 }
3555
3556 void radv_GetImageSparseMemoryRequirements2(
3557 VkDevice device,
3558 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3559 uint32_t* pSparseMemoryRequirementCount,
3560 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3561 {
3562 stub();
3563 }
3564
3565 void radv_GetDeviceMemoryCommitment(
3566 VkDevice device,
3567 VkDeviceMemory memory,
3568 VkDeviceSize* pCommittedMemoryInBytes)
3569 {
3570 *pCommittedMemoryInBytes = 0;
3571 }
3572
3573 VkResult radv_BindBufferMemory2(VkDevice device,
3574 uint32_t bindInfoCount,
3575 const VkBindBufferMemoryInfo *pBindInfos)
3576 {
3577 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3578 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3579 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3580
3581 if (mem) {
3582 buffer->bo = mem->bo;
3583 buffer->offset = pBindInfos[i].memoryOffset;
3584 } else {
3585 buffer->bo = NULL;
3586 }
3587 }
3588 return VK_SUCCESS;
3589 }
3590
3591 VkResult radv_BindBufferMemory(
3592 VkDevice device,
3593 VkBuffer buffer,
3594 VkDeviceMemory memory,
3595 VkDeviceSize memoryOffset)
3596 {
3597 const VkBindBufferMemoryInfo info = {
3598 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3599 .buffer = buffer,
3600 .memory = memory,
3601 .memoryOffset = memoryOffset
3602 };
3603
3604 return radv_BindBufferMemory2(device, 1, &info);
3605 }
3606
3607 VkResult radv_BindImageMemory2(VkDevice device,
3608 uint32_t bindInfoCount,
3609 const VkBindImageMemoryInfo *pBindInfos)
3610 {
3611 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3612 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3613 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3614
3615 if (mem) {
3616 image->bo = mem->bo;
3617 image->offset = pBindInfos[i].memoryOffset;
3618 } else {
3619 image->bo = NULL;
3620 image->offset = 0;
3621 }
3622 }
3623 return VK_SUCCESS;
3624 }
3625
3626
3627 VkResult radv_BindImageMemory(
3628 VkDevice device,
3629 VkImage image,
3630 VkDeviceMemory memory,
3631 VkDeviceSize memoryOffset)
3632 {
3633 const VkBindImageMemoryInfo info = {
3634 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3635 .image = image,
3636 .memory = memory,
3637 .memoryOffset = memoryOffset
3638 };
3639
3640 return radv_BindImageMemory2(device, 1, &info);
3641 }
3642
3643
3644 static void
3645 radv_sparse_buffer_bind_memory(struct radv_device *device,
3646 const VkSparseBufferMemoryBindInfo *bind)
3647 {
3648 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3649
3650 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3651 struct radv_device_memory *mem = NULL;
3652
3653 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3654 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3655
3656 device->ws->buffer_virtual_bind(buffer->bo,
3657 bind->pBinds[i].resourceOffset,
3658 bind->pBinds[i].size,
3659 mem ? mem->bo : NULL,
3660 bind->pBinds[i].memoryOffset);
3661 }
3662 }
3663
3664 static void
3665 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3666 const VkSparseImageOpaqueMemoryBindInfo *bind)
3667 {
3668 RADV_FROM_HANDLE(radv_image, image, bind->image);
3669
3670 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3671 struct radv_device_memory *mem = NULL;
3672
3673 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3674 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3675
3676 device->ws->buffer_virtual_bind(image->bo,
3677 bind->pBinds[i].resourceOffset,
3678 bind->pBinds[i].size,
3679 mem ? mem->bo : NULL,
3680 bind->pBinds[i].memoryOffset);
3681 }
3682 }
3683
3684 VkResult radv_QueueBindSparse(
3685 VkQueue _queue,
3686 uint32_t bindInfoCount,
3687 const VkBindSparseInfo* pBindInfo,
3688 VkFence _fence)
3689 {
3690 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3691 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3692 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3693 bool fence_emitted = false;
3694 VkResult result;
3695 int ret;
3696
3697 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3698 struct radv_winsys_sem_info sem_info;
3699 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3700 radv_sparse_buffer_bind_memory(queue->device,
3701 pBindInfo[i].pBufferBinds + j);
3702 }
3703
3704 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3705 radv_sparse_image_opaque_bind_memory(queue->device,
3706 pBindInfo[i].pImageOpaqueBinds + j);
3707 }
3708
3709 VkResult result;
3710 result = radv_alloc_sem_info(queue->device->instance,
3711 &sem_info,
3712 pBindInfo[i].waitSemaphoreCount,
3713 pBindInfo[i].pWaitSemaphores,
3714 pBindInfo[i].signalSemaphoreCount,
3715 pBindInfo[i].pSignalSemaphores,
3716 _fence);
3717 if (result != VK_SUCCESS)
3718 return result;
3719
3720 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3721 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3722 &queue->device->empty_cs[queue->queue_family_index],
3723 1, NULL, NULL,
3724 &sem_info, NULL,
3725 false, base_fence);
3726 if (ret) {
3727 radv_loge("failed to submit CS %d\n", i);
3728 abort();
3729 }
3730
3731 fence_emitted = true;
3732 }
3733
3734 radv_free_sem_info(&sem_info);
3735
3736 }
3737
3738 if (fence) {
3739 if (!fence_emitted) {
3740 result = radv_signal_fence(queue, fence);
3741 if (result != VK_SUCCESS)
3742 return result;
3743 }
3744 }
3745
3746 return VK_SUCCESS;
3747 }
3748
3749 VkResult radv_CreateFence(
3750 VkDevice _device,
3751 const VkFenceCreateInfo* pCreateInfo,
3752 const VkAllocationCallbacks* pAllocator,
3753 VkFence* pFence)
3754 {
3755 RADV_FROM_HANDLE(radv_device, device, _device);
3756 const VkExportFenceCreateInfo *export =
3757 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3758 VkExternalFenceHandleTypeFlags handleTypes =
3759 export ? export->handleTypes : 0;
3760
3761 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3762 sizeof(*fence), 8,
3763 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3764
3765 if (!fence)
3766 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3767
3768 fence->fence_wsi = NULL;
3769 fence->temp_syncobj = 0;
3770 if (device->always_use_syncobj || handleTypes) {
3771 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3772 if (ret) {
3773 vk_free2(&device->alloc, pAllocator, fence);
3774 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3775 }
3776 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3777 device->ws->signal_syncobj(device->ws, fence->syncobj);
3778 }
3779 fence->fence = NULL;
3780 } else {
3781 fence->fence = device->ws->create_fence();
3782 if (!fence->fence) {
3783 vk_free2(&device->alloc, pAllocator, fence);
3784 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3785 }
3786 fence->syncobj = 0;
3787 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3788 device->ws->signal_fence(fence->fence);
3789 }
3790
3791 *pFence = radv_fence_to_handle(fence);
3792
3793 return VK_SUCCESS;
3794 }
3795
3796 void radv_DestroyFence(
3797 VkDevice _device,
3798 VkFence _fence,
3799 const VkAllocationCallbacks* pAllocator)
3800 {
3801 RADV_FROM_HANDLE(radv_device, device, _device);
3802 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3803
3804 if (!fence)
3805 return;
3806
3807 if (fence->temp_syncobj)
3808 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3809 if (fence->syncobj)
3810 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3811 if (fence->fence)
3812 device->ws->destroy_fence(fence->fence);
3813 if (fence->fence_wsi)
3814 fence->fence_wsi->destroy(fence->fence_wsi);
3815 vk_free2(&device->alloc, pAllocator, fence);
3816 }
3817
3818
3819 uint64_t radv_get_current_time(void)
3820 {
3821 struct timespec tv;
3822 clock_gettime(CLOCK_MONOTONIC, &tv);
3823 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3824 }
3825
3826 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3827 {
3828 uint64_t current_time = radv_get_current_time();
3829
3830 timeout = MIN2(UINT64_MAX - current_time, timeout);
3831
3832 return current_time + timeout;
3833 }
3834
3835
3836 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3837 uint32_t fenceCount, const VkFence *pFences)
3838 {
3839 for (uint32_t i = 0; i < fenceCount; ++i) {
3840 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3841 if (fence->fence == NULL || fence->syncobj ||
3842 fence->temp_syncobj || fence->fence_wsi ||
3843 (!device->ws->is_fence_waitable(fence->fence)))
3844 return false;
3845 }
3846 return true;
3847 }
3848
3849 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3850 {
3851 for (uint32_t i = 0; i < fenceCount; ++i) {
3852 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3853 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3854 return false;
3855 }
3856 return true;
3857 }
3858
3859 VkResult radv_WaitForFences(
3860 VkDevice _device,
3861 uint32_t fenceCount,
3862 const VkFence* pFences,
3863 VkBool32 waitAll,
3864 uint64_t timeout)
3865 {
3866 RADV_FROM_HANDLE(radv_device, device, _device);
3867 timeout = radv_get_absolute_timeout(timeout);
3868
3869 if (device->always_use_syncobj &&
3870 radv_all_fences_syncobj(fenceCount, pFences))
3871 {
3872 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3873 if (!handles)
3874 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3875
3876 for (uint32_t i = 0; i < fenceCount; ++i) {
3877 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3878 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3879 }
3880
3881 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3882
3883 free(handles);
3884 return success ? VK_SUCCESS : VK_TIMEOUT;
3885 }
3886
3887 if (!waitAll && fenceCount > 1) {
3888 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3889 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3890 uint32_t wait_count = 0;
3891 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3892 if (!fences)
3893 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3894
3895 for (uint32_t i = 0; i < fenceCount; ++i) {
3896 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3897
3898 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3899 free(fences);
3900 return VK_SUCCESS;
3901 }
3902
3903 fences[wait_count++] = fence->fence;
3904 }
3905
3906 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3907 waitAll, timeout - radv_get_current_time());
3908
3909 free(fences);
3910 return success ? VK_SUCCESS : VK_TIMEOUT;
3911 }
3912
3913 while(radv_get_current_time() <= timeout) {
3914 for (uint32_t i = 0; i < fenceCount; ++i) {
3915 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3916 return VK_SUCCESS;
3917 }
3918 }
3919 return VK_TIMEOUT;
3920 }
3921
3922 for (uint32_t i = 0; i < fenceCount; ++i) {
3923 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3924 bool expired = false;
3925
3926 if (fence->temp_syncobj) {
3927 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3928 return VK_TIMEOUT;
3929 continue;
3930 }
3931
3932 if (fence->syncobj) {
3933 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3934 return VK_TIMEOUT;
3935 continue;
3936 }
3937
3938 if (fence->fence) {
3939 if (!device->ws->is_fence_waitable(fence->fence)) {
3940 while(!device->ws->is_fence_waitable(fence->fence) &&
3941 radv_get_current_time() <= timeout)
3942 /* Do nothing */;
3943 }
3944
3945 expired = device->ws->fence_wait(device->ws,
3946 fence->fence,
3947 true, timeout);
3948 if (!expired)
3949 return VK_TIMEOUT;
3950 }
3951
3952 if (fence->fence_wsi) {
3953 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3954 if (result != VK_SUCCESS)
3955 return result;
3956 }
3957 }
3958
3959 return VK_SUCCESS;
3960 }
3961
3962 VkResult radv_ResetFences(VkDevice _device,
3963 uint32_t fenceCount,
3964 const VkFence *pFences)
3965 {
3966 RADV_FROM_HANDLE(radv_device, device, _device);
3967
3968 for (unsigned i = 0; i < fenceCount; ++i) {
3969 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3970 if (fence->fence)
3971 device->ws->reset_fence(fence->fence);
3972
3973 /* Per spec, we first restore the permanent payload, and then reset, so
3974 * having a temp syncobj should not skip resetting the permanent syncobj. */
3975 if (fence->temp_syncobj) {
3976 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3977 fence->temp_syncobj = 0;
3978 }
3979
3980 if (fence->syncobj) {
3981 device->ws->reset_syncobj(device->ws, fence->syncobj);
3982 }
3983 }
3984
3985 return VK_SUCCESS;
3986 }
3987
3988 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3989 {
3990 RADV_FROM_HANDLE(radv_device, device, _device);
3991 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3992
3993 if (fence->temp_syncobj) {
3994 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3995 return success ? VK_SUCCESS : VK_NOT_READY;
3996 }
3997
3998 if (fence->syncobj) {
3999 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4000 return success ? VK_SUCCESS : VK_NOT_READY;
4001 }
4002
4003 if (fence->fence) {
4004 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4005 return VK_NOT_READY;
4006 }
4007 if (fence->fence_wsi) {
4008 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4009
4010 if (result != VK_SUCCESS) {
4011 if (result == VK_TIMEOUT)
4012 return VK_NOT_READY;
4013 return result;
4014 }
4015 }
4016 return VK_SUCCESS;
4017 }
4018
4019
4020 // Queue semaphore functions
4021
4022 VkResult radv_CreateSemaphore(
4023 VkDevice _device,
4024 const VkSemaphoreCreateInfo* pCreateInfo,
4025 const VkAllocationCallbacks* pAllocator,
4026 VkSemaphore* pSemaphore)
4027 {
4028 RADV_FROM_HANDLE(radv_device, device, _device);
4029 const VkExportSemaphoreCreateInfo *export =
4030 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4031 VkExternalSemaphoreHandleTypeFlags handleTypes =
4032 export ? export->handleTypes : 0;
4033
4034 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4035 sizeof(*sem), 8,
4036 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4037 if (!sem)
4038 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4039
4040 sem->temp_syncobj = 0;
4041 /* create a syncobject if we are going to export this semaphore */
4042 if (device->always_use_syncobj || handleTypes) {
4043 assert (device->physical_device->rad_info.has_syncobj);
4044 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4045 if (ret) {
4046 vk_free2(&device->alloc, pAllocator, sem);
4047 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4048 }
4049 sem->sem = NULL;
4050 } else {
4051 sem->sem = device->ws->create_sem(device->ws);
4052 if (!sem->sem) {
4053 vk_free2(&device->alloc, pAllocator, sem);
4054 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4055 }
4056 sem->syncobj = 0;
4057 }
4058
4059 *pSemaphore = radv_semaphore_to_handle(sem);
4060 return VK_SUCCESS;
4061 }
4062
4063 void radv_DestroySemaphore(
4064 VkDevice _device,
4065 VkSemaphore _semaphore,
4066 const VkAllocationCallbacks* pAllocator)
4067 {
4068 RADV_FROM_HANDLE(radv_device, device, _device);
4069 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4070 if (!_semaphore)
4071 return;
4072
4073 if (sem->syncobj)
4074 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4075 else
4076 device->ws->destroy_sem(sem->sem);
4077 vk_free2(&device->alloc, pAllocator, sem);
4078 }
4079
4080 VkResult radv_CreateEvent(
4081 VkDevice _device,
4082 const VkEventCreateInfo* pCreateInfo,
4083 const VkAllocationCallbacks* pAllocator,
4084 VkEvent* pEvent)
4085 {
4086 RADV_FROM_HANDLE(radv_device, device, _device);
4087 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4088 sizeof(*event), 8,
4089 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4090
4091 if (!event)
4092 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4093
4094 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4095 RADEON_DOMAIN_GTT,
4096 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4097 RADV_BO_PRIORITY_FENCE);
4098 if (!event->bo) {
4099 vk_free2(&device->alloc, pAllocator, event);
4100 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4101 }
4102
4103 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4104
4105 *pEvent = radv_event_to_handle(event);
4106
4107 return VK_SUCCESS;
4108 }
4109
4110 void radv_DestroyEvent(
4111 VkDevice _device,
4112 VkEvent _event,
4113 const VkAllocationCallbacks* pAllocator)
4114 {
4115 RADV_FROM_HANDLE(radv_device, device, _device);
4116 RADV_FROM_HANDLE(radv_event, event, _event);
4117
4118 if (!event)
4119 return;
4120 device->ws->buffer_destroy(event->bo);
4121 vk_free2(&device->alloc, pAllocator, event);
4122 }
4123
4124 VkResult radv_GetEventStatus(
4125 VkDevice _device,
4126 VkEvent _event)
4127 {
4128 RADV_FROM_HANDLE(radv_event, event, _event);
4129
4130 if (*event->map == 1)
4131 return VK_EVENT_SET;
4132 return VK_EVENT_RESET;
4133 }
4134
4135 VkResult radv_SetEvent(
4136 VkDevice _device,
4137 VkEvent _event)
4138 {
4139 RADV_FROM_HANDLE(radv_event, event, _event);
4140 *event->map = 1;
4141
4142 return VK_SUCCESS;
4143 }
4144
4145 VkResult radv_ResetEvent(
4146 VkDevice _device,
4147 VkEvent _event)
4148 {
4149 RADV_FROM_HANDLE(radv_event, event, _event);
4150 *event->map = 0;
4151
4152 return VK_SUCCESS;
4153 }
4154
4155 VkResult radv_CreateBuffer(
4156 VkDevice _device,
4157 const VkBufferCreateInfo* pCreateInfo,
4158 const VkAllocationCallbacks* pAllocator,
4159 VkBuffer* pBuffer)
4160 {
4161 RADV_FROM_HANDLE(radv_device, device, _device);
4162 struct radv_buffer *buffer;
4163
4164 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4165
4166 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4167 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4168 if (buffer == NULL)
4169 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4170
4171 buffer->size = pCreateInfo->size;
4172 buffer->usage = pCreateInfo->usage;
4173 buffer->bo = NULL;
4174 buffer->offset = 0;
4175 buffer->flags = pCreateInfo->flags;
4176
4177 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4178 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4179
4180 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4181 buffer->bo = device->ws->buffer_create(device->ws,
4182 align64(buffer->size, 4096),
4183 4096, 0, RADEON_FLAG_VIRTUAL,
4184 RADV_BO_PRIORITY_VIRTUAL);
4185 if (!buffer->bo) {
4186 vk_free2(&device->alloc, pAllocator, buffer);
4187 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4188 }
4189 }
4190
4191 *pBuffer = radv_buffer_to_handle(buffer);
4192
4193 return VK_SUCCESS;
4194 }
4195
4196 void radv_DestroyBuffer(
4197 VkDevice _device,
4198 VkBuffer _buffer,
4199 const VkAllocationCallbacks* pAllocator)
4200 {
4201 RADV_FROM_HANDLE(radv_device, device, _device);
4202 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4203
4204 if (!buffer)
4205 return;
4206
4207 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4208 device->ws->buffer_destroy(buffer->bo);
4209
4210 vk_free2(&device->alloc, pAllocator, buffer);
4211 }
4212
4213 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4214 VkDevice device,
4215 const VkBufferDeviceAddressInfoEXT* pInfo)
4216 {
4217 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4218 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4219 }
4220
4221
4222 static inline unsigned
4223 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4224 {
4225 if (stencil)
4226 return plane->surface.u.legacy.stencil_tiling_index[level];
4227 else
4228 return plane->surface.u.legacy.tiling_index[level];
4229 }
4230
4231 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4232 {
4233 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4234 }
4235
4236 static uint32_t
4237 radv_init_dcc_control_reg(struct radv_device *device,
4238 struct radv_image_view *iview)
4239 {
4240 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4241 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4242 unsigned max_compressed_block_size;
4243 unsigned independent_128b_blocks;
4244 unsigned independent_64b_blocks;
4245
4246 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4247 return 0;
4248
4249 if (!device->physical_device->rad_info.has_dedicated_vram) {
4250 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4251 * dGPU and 64 for APU because all of our APUs to date use
4252 * DIMMs which have a request granularity size of 64B while all
4253 * other chips have a 32B request size.
4254 */
4255 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4256 }
4257
4258 if (device->physical_device->rad_info.chip_class >= GFX10) {
4259 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4260 independent_64b_blocks = 0;
4261 independent_128b_blocks = 1;
4262 } else {
4263 independent_128b_blocks = 0;
4264
4265 if (iview->image->info.samples > 1) {
4266 if (iview->image->planes[0].surface.bpe == 1)
4267 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4268 else if (iview->image->planes[0].surface.bpe == 2)
4269 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4270 }
4271
4272 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4273 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4274 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4275 /* If this DCC image is potentially going to be used in texture
4276 * fetches, we need some special settings.
4277 */
4278 independent_64b_blocks = 1;
4279 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4280 } else {
4281 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4282 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4283 * big as possible for better compression state.
4284 */
4285 independent_64b_blocks = 0;
4286 max_compressed_block_size = max_uncompressed_block_size;
4287 }
4288 }
4289
4290 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4291 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4292 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4293 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4294 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4295 }
4296
4297 static void
4298 radv_initialise_color_surface(struct radv_device *device,
4299 struct radv_color_buffer_info *cb,
4300 struct radv_image_view *iview)
4301 {
4302 const struct vk_format_description *desc;
4303 unsigned ntype, format, swap, endian;
4304 unsigned blend_clamp = 0, blend_bypass = 0;
4305 uint64_t va;
4306 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4307 const struct radeon_surf *surf = &plane->surface;
4308
4309 desc = vk_format_description(iview->vk_format);
4310
4311 memset(cb, 0, sizeof(*cb));
4312
4313 /* Intensity is implemented as Red, so treat it that way. */
4314 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4315
4316 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4317
4318 cb->cb_color_base = va >> 8;
4319
4320 if (device->physical_device->rad_info.chip_class >= GFX9) {
4321 struct gfx9_surf_meta_flags meta;
4322 if (iview->image->dcc_offset)
4323 meta = surf->u.gfx9.dcc;
4324 else
4325 meta = surf->u.gfx9.cmask;
4326
4327 if (device->physical_device->rad_info.chip_class >= GFX10) {
4328 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4329 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4330 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4331 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4332 } else {
4333 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4334 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4335 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4336 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4337 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4338 }
4339
4340 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4341 cb->cb_color_base |= surf->tile_swizzle;
4342 } else {
4343 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4344 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4345
4346 cb->cb_color_base += level_info->offset >> 8;
4347 if (level_info->mode == RADEON_SURF_MODE_2D)
4348 cb->cb_color_base |= surf->tile_swizzle;
4349
4350 pitch_tile_max = level_info->nblk_x / 8 - 1;
4351 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4352 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4353
4354 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4355 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4356 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4357
4358 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4359
4360 if (radv_image_has_fmask(iview->image)) {
4361 if (device->physical_device->rad_info.chip_class >= GFX7)
4362 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4363 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4364 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4365 } else {
4366 /* This must be set for fast clear to work without FMASK. */
4367 if (device->physical_device->rad_info.chip_class >= GFX7)
4368 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4369 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4370 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4371 }
4372 }
4373
4374 /* CMASK variables */
4375 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4376 va += iview->image->cmask.offset;
4377 cb->cb_color_cmask = va >> 8;
4378
4379 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4380 va += iview->image->dcc_offset;
4381
4382 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4383 device->physical_device->rad_info.chip_class <= GFX8)
4384 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4385
4386 cb->cb_dcc_base = va >> 8;
4387 cb->cb_dcc_base |= surf->tile_swizzle;
4388
4389 /* GFX10 field has the same base shift as the GFX6 field. */
4390 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4391 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4392 S_028C6C_SLICE_MAX_GFX10(max_slice);
4393
4394 if (iview->image->info.samples > 1) {
4395 unsigned log_samples = util_logbase2(iview->image->info.samples);
4396
4397 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4398 S_028C74_NUM_FRAGMENTS(log_samples);
4399 }
4400
4401 if (radv_image_has_fmask(iview->image)) {
4402 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4403 cb->cb_color_fmask = va >> 8;
4404 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4405 } else {
4406 cb->cb_color_fmask = cb->cb_color_base;
4407 }
4408
4409 ntype = radv_translate_color_numformat(iview->vk_format,
4410 desc,
4411 vk_format_get_first_non_void_channel(iview->vk_format));
4412 format = radv_translate_colorformat(iview->vk_format);
4413 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4414 radv_finishme("Illegal color\n");
4415 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4416 endian = radv_colorformat_endian_swap(format);
4417
4418 /* blend clamp should be set for all NORM/SRGB types */
4419 if (ntype == V_028C70_NUMBER_UNORM ||
4420 ntype == V_028C70_NUMBER_SNORM ||
4421 ntype == V_028C70_NUMBER_SRGB)
4422 blend_clamp = 1;
4423
4424 /* set blend bypass according to docs if SINT/UINT or
4425 8/24 COLOR variants */
4426 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4427 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4428 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4429 blend_clamp = 0;
4430 blend_bypass = 1;
4431 }
4432 #if 0
4433 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4434 (format == V_028C70_COLOR_8 ||
4435 format == V_028C70_COLOR_8_8 ||
4436 format == V_028C70_COLOR_8_8_8_8))
4437 ->color_is_int8 = true;
4438 #endif
4439 cb->cb_color_info = S_028C70_FORMAT(format) |
4440 S_028C70_COMP_SWAP(swap) |
4441 S_028C70_BLEND_CLAMP(blend_clamp) |
4442 S_028C70_BLEND_BYPASS(blend_bypass) |
4443 S_028C70_SIMPLE_FLOAT(1) |
4444 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4445 ntype != V_028C70_NUMBER_SNORM &&
4446 ntype != V_028C70_NUMBER_SRGB &&
4447 format != V_028C70_COLOR_8_24 &&
4448 format != V_028C70_COLOR_24_8) |
4449 S_028C70_NUMBER_TYPE(ntype) |
4450 S_028C70_ENDIAN(endian);
4451 if (radv_image_has_fmask(iview->image)) {
4452 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4453 if (device->physical_device->rad_info.chip_class == GFX6) {
4454 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4455 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4456 }
4457
4458 if (radv_image_is_tc_compat_cmask(iview->image)) {
4459 /* Allow the texture block to read FMASK directly
4460 * without decompressing it. This bit must be cleared
4461 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4462 * otherwise the operation doesn't happen.
4463 */
4464 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4465
4466 /* Set CMASK into a tiling format that allows the
4467 * texture block to read it.
4468 */
4469 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4470 }
4471 }
4472
4473 if (radv_image_has_cmask(iview->image) &&
4474 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4475 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4476
4477 if (radv_dcc_enabled(iview->image, iview->base_mip))
4478 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4479
4480 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4481
4482 /* This must be set for fast clear to work without FMASK. */
4483 if (!radv_image_has_fmask(iview->image) &&
4484 device->physical_device->rad_info.chip_class == GFX6) {
4485 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4486 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4487 }
4488
4489 if (device->physical_device->rad_info.chip_class >= GFX9) {
4490 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4491
4492 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4493 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4494 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4495 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4496
4497 if (device->physical_device->rad_info.chip_class >= GFX10) {
4498 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4499
4500 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4501 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4502 S_028EE0_RESOURCE_LEVEL(1);
4503 } else {
4504 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4505 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4506 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4507 }
4508
4509 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4510 S_028C68_MIP0_HEIGHT(height - 1) |
4511 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4512 }
4513 }
4514
4515 static unsigned
4516 radv_calc_decompress_on_z_planes(struct radv_device *device,
4517 struct radv_image_view *iview)
4518 {
4519 unsigned max_zplanes = 0;
4520
4521 assert(radv_image_is_tc_compat_htile(iview->image));
4522
4523 if (device->physical_device->rad_info.chip_class >= GFX9) {
4524 /* Default value for 32-bit depth surfaces. */
4525 max_zplanes = 4;
4526
4527 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4528 iview->image->info.samples > 1)
4529 max_zplanes = 2;
4530
4531 max_zplanes = max_zplanes + 1;
4532 } else {
4533 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4534 /* Do not enable Z plane compression for 16-bit depth
4535 * surfaces because isn't supported on GFX8. Only
4536 * 32-bit depth surfaces are supported by the hardware.
4537 * This allows to maintain shader compatibility and to
4538 * reduce the number of depth decompressions.
4539 */
4540 max_zplanes = 1;
4541 } else {
4542 if (iview->image->info.samples <= 1)
4543 max_zplanes = 5;
4544 else if (iview->image->info.samples <= 4)
4545 max_zplanes = 3;
4546 else
4547 max_zplanes = 2;
4548 }
4549 }
4550
4551 return max_zplanes;
4552 }
4553
4554 static void
4555 radv_initialise_ds_surface(struct radv_device *device,
4556 struct radv_ds_buffer_info *ds,
4557 struct radv_image_view *iview)
4558 {
4559 unsigned level = iview->base_mip;
4560 unsigned format, stencil_format;
4561 uint64_t va, s_offs, z_offs;
4562 bool stencil_only = false;
4563 const struct radv_image_plane *plane = &iview->image->planes[0];
4564 const struct radeon_surf *surf = &plane->surface;
4565
4566 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4567
4568 memset(ds, 0, sizeof(*ds));
4569 switch (iview->image->vk_format) {
4570 case VK_FORMAT_D24_UNORM_S8_UINT:
4571 case VK_FORMAT_X8_D24_UNORM_PACK32:
4572 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4573 ds->offset_scale = 2.0f;
4574 break;
4575 case VK_FORMAT_D16_UNORM:
4576 case VK_FORMAT_D16_UNORM_S8_UINT:
4577 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4578 ds->offset_scale = 4.0f;
4579 break;
4580 case VK_FORMAT_D32_SFLOAT:
4581 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4582 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4583 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4584 ds->offset_scale = 1.0f;
4585 break;
4586 case VK_FORMAT_S8_UINT:
4587 stencil_only = true;
4588 break;
4589 default:
4590 break;
4591 }
4592
4593 format = radv_translate_dbformat(iview->image->vk_format);
4594 stencil_format = surf->has_stencil ?
4595 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4596
4597 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4598 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4599 S_028008_SLICE_MAX(max_slice);
4600 if (device->physical_device->rad_info.chip_class >= GFX10) {
4601 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4602 S_028008_SLICE_MAX_HI(max_slice >> 11);
4603 }
4604
4605 ds->db_htile_data_base = 0;
4606 ds->db_htile_surface = 0;
4607
4608 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4609 s_offs = z_offs = va;
4610
4611 if (device->physical_device->rad_info.chip_class >= GFX9) {
4612 assert(surf->u.gfx9.surf_offset == 0);
4613 s_offs += surf->u.gfx9.stencil_offset;
4614
4615 ds->db_z_info = S_028038_FORMAT(format) |
4616 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4617 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4618 S_028038_MAXMIP(iview->image->info.levels - 1) |
4619 S_028038_ZRANGE_PRECISION(1);
4620 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4621 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4622
4623 if (device->physical_device->rad_info.chip_class == GFX9) {
4624 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4625 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4626 }
4627
4628 ds->db_depth_view |= S_028008_MIPID(level);
4629 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4630 S_02801C_Y_MAX(iview->image->info.height - 1);
4631
4632 if (radv_htile_enabled(iview->image, level)) {
4633 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4634
4635 if (radv_image_is_tc_compat_htile(iview->image)) {
4636 unsigned max_zplanes =
4637 radv_calc_decompress_on_z_planes(device, iview);
4638
4639 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4640
4641 if (device->physical_device->rad_info.chip_class >= GFX10) {
4642 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4643 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4644 } else {
4645 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4646 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4647 }
4648 }
4649
4650 if (!surf->has_stencil)
4651 /* Use all of the htile_buffer for depth if there's no stencil. */
4652 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4653 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4654 iview->image->htile_offset;
4655 ds->db_htile_data_base = va >> 8;
4656 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4657 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4658
4659 if (device->physical_device->rad_info.chip_class == GFX9) {
4660 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4661 }
4662 }
4663 } else {
4664 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4665
4666 if (stencil_only)
4667 level_info = &surf->u.legacy.stencil_level[level];
4668
4669 z_offs += surf->u.legacy.level[level].offset;
4670 s_offs += surf->u.legacy.stencil_level[level].offset;
4671
4672 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4673 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4674 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4675
4676 if (iview->image->info.samples > 1)
4677 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4678
4679 if (device->physical_device->rad_info.chip_class >= GFX7) {
4680 struct radeon_info *info = &device->physical_device->rad_info;
4681 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4682 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4683 unsigned macro_index = surf->u.legacy.macro_tile_index;
4684 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4685 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4686 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4687
4688 if (stencil_only)
4689 tile_mode = stencil_tile_mode;
4690
4691 ds->db_depth_info |=
4692 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4693 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4694 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4695 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4696 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4697 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4698 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4699 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4700 } else {
4701 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4702 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4703 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4704 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4705 if (stencil_only)
4706 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4707 }
4708
4709 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4710 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4711 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4712
4713 if (radv_htile_enabled(iview->image, level)) {
4714 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4715
4716 if (!surf->has_stencil &&
4717 !radv_image_is_tc_compat_htile(iview->image))
4718 /* Use all of the htile_buffer for depth if there's no stencil. */
4719 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4720
4721 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4722 iview->image->htile_offset;
4723 ds->db_htile_data_base = va >> 8;
4724 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4725
4726 if (radv_image_is_tc_compat_htile(iview->image)) {
4727 unsigned max_zplanes =
4728 radv_calc_decompress_on_z_planes(device, iview);
4729
4730 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4731 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4732 }
4733 }
4734 }
4735
4736 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4737 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4738 }
4739
4740 VkResult radv_CreateFramebuffer(
4741 VkDevice _device,
4742 const VkFramebufferCreateInfo* pCreateInfo,
4743 const VkAllocationCallbacks* pAllocator,
4744 VkFramebuffer* pFramebuffer)
4745 {
4746 RADV_FROM_HANDLE(radv_device, device, _device);
4747 struct radv_framebuffer *framebuffer;
4748
4749 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4750
4751 size_t size = sizeof(*framebuffer) +
4752 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4753 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4754 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4755 if (framebuffer == NULL)
4756 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4757
4758 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4759 framebuffer->width = pCreateInfo->width;
4760 framebuffer->height = pCreateInfo->height;
4761 framebuffer->layers = pCreateInfo->layers;
4762 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4763 VkImageView _iview = pCreateInfo->pAttachments[i];
4764 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4765 framebuffer->attachments[i].attachment = iview;
4766 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4767 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4768 } else {
4769 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4770 }
4771 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4772 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4773 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4774 }
4775
4776 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4777 return VK_SUCCESS;
4778 }
4779
4780 void radv_DestroyFramebuffer(
4781 VkDevice _device,
4782 VkFramebuffer _fb,
4783 const VkAllocationCallbacks* pAllocator)
4784 {
4785 RADV_FROM_HANDLE(radv_device, device, _device);
4786 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4787
4788 if (!fb)
4789 return;
4790 vk_free2(&device->alloc, pAllocator, fb);
4791 }
4792
4793 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4794 {
4795 switch (address_mode) {
4796 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4797 return V_008F30_SQ_TEX_WRAP;
4798 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4799 return V_008F30_SQ_TEX_MIRROR;
4800 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4801 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4802 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4803 return V_008F30_SQ_TEX_CLAMP_BORDER;
4804 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4805 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4806 default:
4807 unreachable("illegal tex wrap mode");
4808 break;
4809 }
4810 }
4811
4812 static unsigned
4813 radv_tex_compare(VkCompareOp op)
4814 {
4815 switch (op) {
4816 case VK_COMPARE_OP_NEVER:
4817 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4818 case VK_COMPARE_OP_LESS:
4819 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4820 case VK_COMPARE_OP_EQUAL:
4821 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4822 case VK_COMPARE_OP_LESS_OR_EQUAL:
4823 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4824 case VK_COMPARE_OP_GREATER:
4825 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4826 case VK_COMPARE_OP_NOT_EQUAL:
4827 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4828 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4829 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4830 case VK_COMPARE_OP_ALWAYS:
4831 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4832 default:
4833 unreachable("illegal compare mode");
4834 break;
4835 }
4836 }
4837
4838 static unsigned
4839 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4840 {
4841 switch (filter) {
4842 case VK_FILTER_NEAREST:
4843 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4844 V_008F38_SQ_TEX_XY_FILTER_POINT);
4845 case VK_FILTER_LINEAR:
4846 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4847 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4848 case VK_FILTER_CUBIC_IMG:
4849 default:
4850 fprintf(stderr, "illegal texture filter");
4851 return 0;
4852 }
4853 }
4854
4855 static unsigned
4856 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4857 {
4858 switch (mode) {
4859 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4860 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4861 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4862 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4863 default:
4864 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4865 }
4866 }
4867
4868 static unsigned
4869 radv_tex_bordercolor(VkBorderColor bcolor)
4870 {
4871 switch (bcolor) {
4872 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4873 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4874 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4875 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4876 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4877 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4878 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4879 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4880 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4881 default:
4882 break;
4883 }
4884 return 0;
4885 }
4886
4887 static unsigned
4888 radv_tex_aniso_filter(unsigned filter)
4889 {
4890 if (filter < 2)
4891 return 0;
4892 if (filter < 4)
4893 return 1;
4894 if (filter < 8)
4895 return 2;
4896 if (filter < 16)
4897 return 3;
4898 return 4;
4899 }
4900
4901 static unsigned
4902 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4903 {
4904 switch (mode) {
4905 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4906 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4907 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4908 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4909 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4910 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4911 default:
4912 break;
4913 }
4914 return 0;
4915 }
4916
4917 static uint32_t
4918 radv_get_max_anisotropy(struct radv_device *device,
4919 const VkSamplerCreateInfo *pCreateInfo)
4920 {
4921 if (device->force_aniso >= 0)
4922 return device->force_aniso;
4923
4924 if (pCreateInfo->anisotropyEnable &&
4925 pCreateInfo->maxAnisotropy > 1.0f)
4926 return (uint32_t)pCreateInfo->maxAnisotropy;
4927
4928 return 0;
4929 }
4930
4931 static void
4932 radv_init_sampler(struct radv_device *device,
4933 struct radv_sampler *sampler,
4934 const VkSamplerCreateInfo *pCreateInfo)
4935 {
4936 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4937 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4938 bool is_vi = (device->physical_device->rad_info.chip_class >= GFX8);
4939 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4940
4941 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4942 vk_find_struct_const(pCreateInfo->pNext,
4943 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4944 if (sampler_reduction)
4945 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4946
4947 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4948 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4949 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4950 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4951 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4952 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4953 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4954 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4955 S_008F30_DISABLE_CUBE_WRAP(0) |
4956 S_008F30_COMPAT_MODE(is_vi) |
4957 S_008F30_FILTER_MODE(filter_mode));
4958 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4959 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4960 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4961 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4962 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4963 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4964 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4965 S_008F38_MIP_POINT_PRECLAMP(0) |
4966 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
4967 S_008F38_FILTER_PREC_FIX(1) |
4968 S_008F38_ANISO_OVERRIDE_GFX6(is_vi));
4969 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4970 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4971 }
4972
4973 VkResult radv_CreateSampler(
4974 VkDevice _device,
4975 const VkSamplerCreateInfo* pCreateInfo,
4976 const VkAllocationCallbacks* pAllocator,
4977 VkSampler* pSampler)
4978 {
4979 RADV_FROM_HANDLE(radv_device, device, _device);
4980 struct radv_sampler *sampler;
4981
4982 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4983 vk_find_struct_const(pCreateInfo->pNext,
4984 SAMPLER_YCBCR_CONVERSION_INFO);
4985
4986 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4987
4988 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4989 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4990 if (!sampler)
4991 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4992
4993 radv_init_sampler(device, sampler, pCreateInfo);
4994
4995 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4996 *pSampler = radv_sampler_to_handle(sampler);
4997
4998 return VK_SUCCESS;
4999 }
5000
5001 void radv_DestroySampler(
5002 VkDevice _device,
5003 VkSampler _sampler,
5004 const VkAllocationCallbacks* pAllocator)
5005 {
5006 RADV_FROM_HANDLE(radv_device, device, _device);
5007 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5008
5009 if (!sampler)
5010 return;
5011 vk_free2(&device->alloc, pAllocator, sampler);
5012 }
5013
5014 /* vk_icd.h does not declare this function, so we declare it here to
5015 * suppress Wmissing-prototypes.
5016 */
5017 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5018 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5019
5020 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5021 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5022 {
5023 /* For the full details on loader interface versioning, see
5024 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5025 * What follows is a condensed summary, to help you navigate the large and
5026 * confusing official doc.
5027 *
5028 * - Loader interface v0 is incompatible with later versions. We don't
5029 * support it.
5030 *
5031 * - In loader interface v1:
5032 * - The first ICD entrypoint called by the loader is
5033 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5034 * entrypoint.
5035 * - The ICD must statically expose no other Vulkan symbol unless it is
5036 * linked with -Bsymbolic.
5037 * - Each dispatchable Vulkan handle created by the ICD must be
5038 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5039 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5040 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5041 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5042 * such loader-managed surfaces.
5043 *
5044 * - Loader interface v2 differs from v1 in:
5045 * - The first ICD entrypoint called by the loader is
5046 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5047 * statically expose this entrypoint.
5048 *
5049 * - Loader interface v3 differs from v2 in:
5050 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5051 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5052 * because the loader no longer does so.
5053 */
5054 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5055 return VK_SUCCESS;
5056 }
5057
5058 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5059 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5060 int *pFD)
5061 {
5062 RADV_FROM_HANDLE(radv_device, device, _device);
5063 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5064
5065 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5066
5067 /* At the moment, we support only the below handle types. */
5068 assert(pGetFdInfo->handleType ==
5069 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5070 pGetFdInfo->handleType ==
5071 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5072
5073 bool ret = radv_get_memory_fd(device, memory, pFD);
5074 if (ret == false)
5075 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5076 return VK_SUCCESS;
5077 }
5078
5079 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5080 VkExternalMemoryHandleTypeFlagBits handleType,
5081 int fd,
5082 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5083 {
5084 RADV_FROM_HANDLE(radv_device, device, _device);
5085
5086 switch (handleType) {
5087 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5088 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5089 return VK_SUCCESS;
5090
5091 default:
5092 /* The valid usage section for this function says:
5093 *
5094 * "handleType must not be one of the handle types defined as
5095 * opaque."
5096 *
5097 * So opaque handle types fall into the default "unsupported" case.
5098 */
5099 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5100 }
5101 }
5102
5103 static VkResult radv_import_opaque_fd(struct radv_device *device,
5104 int fd,
5105 uint32_t *syncobj)
5106 {
5107 uint32_t syncobj_handle = 0;
5108 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5109 if (ret != 0)
5110 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5111
5112 if (*syncobj)
5113 device->ws->destroy_syncobj(device->ws, *syncobj);
5114
5115 *syncobj = syncobj_handle;
5116 close(fd);
5117
5118 return VK_SUCCESS;
5119 }
5120
5121 static VkResult radv_import_sync_fd(struct radv_device *device,
5122 int fd,
5123 uint32_t *syncobj)
5124 {
5125 /* If we create a syncobj we do it locally so that if we have an error, we don't
5126 * leave a syncobj in an undetermined state in the fence. */
5127 uint32_t syncobj_handle = *syncobj;
5128 if (!syncobj_handle) {
5129 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5130 if (ret) {
5131 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5132 }
5133 }
5134
5135 if (fd == -1) {
5136 device->ws->signal_syncobj(device->ws, syncobj_handle);
5137 } else {
5138 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5139 if (ret != 0)
5140 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5141 }
5142
5143 *syncobj = syncobj_handle;
5144 if (fd != -1)
5145 close(fd);
5146
5147 return VK_SUCCESS;
5148 }
5149
5150 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5151 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5152 {
5153 RADV_FROM_HANDLE(radv_device, device, _device);
5154 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5155 uint32_t *syncobj_dst = NULL;
5156
5157 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5158 syncobj_dst = &sem->temp_syncobj;
5159 } else {
5160 syncobj_dst = &sem->syncobj;
5161 }
5162
5163 switch(pImportSemaphoreFdInfo->handleType) {
5164 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5165 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5166 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5167 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5168 default:
5169 unreachable("Unhandled semaphore handle type");
5170 }
5171 }
5172
5173 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5174 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5175 int *pFd)
5176 {
5177 RADV_FROM_HANDLE(radv_device, device, _device);
5178 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5179 int ret;
5180 uint32_t syncobj_handle;
5181
5182 if (sem->temp_syncobj)
5183 syncobj_handle = sem->temp_syncobj;
5184 else
5185 syncobj_handle = sem->syncobj;
5186
5187 switch(pGetFdInfo->handleType) {
5188 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5189 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5190 break;
5191 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5192 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5193 if (!ret) {
5194 if (sem->temp_syncobj) {
5195 close (sem->temp_syncobj);
5196 sem->temp_syncobj = 0;
5197 } else {
5198 device->ws->reset_syncobj(device->ws, syncobj_handle);
5199 }
5200 }
5201 break;
5202 default:
5203 unreachable("Unhandled semaphore handle type");
5204 }
5205
5206 if (ret)
5207 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5208 return VK_SUCCESS;
5209 }
5210
5211 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5212 VkPhysicalDevice physicalDevice,
5213 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5214 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5215 {
5216 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5217
5218 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5219 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5220 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5221 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5222 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5223 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5224 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5225 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5226 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5227 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5228 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5229 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5230 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5231 } else {
5232 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5233 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5234 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5235 }
5236 }
5237
5238 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5239 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5240 {
5241 RADV_FROM_HANDLE(radv_device, device, _device);
5242 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5243 uint32_t *syncobj_dst = NULL;
5244
5245
5246 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5247 syncobj_dst = &fence->temp_syncobj;
5248 } else {
5249 syncobj_dst = &fence->syncobj;
5250 }
5251
5252 switch(pImportFenceFdInfo->handleType) {
5253 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5254 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5255 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5256 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5257 default:
5258 unreachable("Unhandled fence handle type");
5259 }
5260 }
5261
5262 VkResult radv_GetFenceFdKHR(VkDevice _device,
5263 const VkFenceGetFdInfoKHR *pGetFdInfo,
5264 int *pFd)
5265 {
5266 RADV_FROM_HANDLE(radv_device, device, _device);
5267 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5268 int ret;
5269 uint32_t syncobj_handle;
5270
5271 if (fence->temp_syncobj)
5272 syncobj_handle = fence->temp_syncobj;
5273 else
5274 syncobj_handle = fence->syncobj;
5275
5276 switch(pGetFdInfo->handleType) {
5277 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5278 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5279 break;
5280 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5281 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5282 if (!ret) {
5283 if (fence->temp_syncobj) {
5284 close (fence->temp_syncobj);
5285 fence->temp_syncobj = 0;
5286 } else {
5287 device->ws->reset_syncobj(device->ws, syncobj_handle);
5288 }
5289 }
5290 break;
5291 default:
5292 unreachable("Unhandled fence handle type");
5293 }
5294
5295 if (ret)
5296 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5297 return VK_SUCCESS;
5298 }
5299
5300 void radv_GetPhysicalDeviceExternalFenceProperties(
5301 VkPhysicalDevice physicalDevice,
5302 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5303 VkExternalFenceProperties *pExternalFenceProperties)
5304 {
5305 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5306
5307 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5308 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5309 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5310 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5311 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5312 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5313 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5314 } else {
5315 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5316 pExternalFenceProperties->compatibleHandleTypes = 0;
5317 pExternalFenceProperties->externalFenceFeatures = 0;
5318 }
5319 }
5320
5321 VkResult
5322 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5323 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5324 const VkAllocationCallbacks* pAllocator,
5325 VkDebugReportCallbackEXT* pCallback)
5326 {
5327 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5328 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5329 pCreateInfo, pAllocator, &instance->alloc,
5330 pCallback);
5331 }
5332
5333 void
5334 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5335 VkDebugReportCallbackEXT _callback,
5336 const VkAllocationCallbacks* pAllocator)
5337 {
5338 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5339 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5340 _callback, pAllocator, &instance->alloc);
5341 }
5342
5343 void
5344 radv_DebugReportMessageEXT(VkInstance _instance,
5345 VkDebugReportFlagsEXT flags,
5346 VkDebugReportObjectTypeEXT objectType,
5347 uint64_t object,
5348 size_t location,
5349 int32_t messageCode,
5350 const char* pLayerPrefix,
5351 const char* pMessage)
5352 {
5353 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5354 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5355 object, location, messageCode, pLayerPrefix, pMessage);
5356 }
5357
5358 void
5359 radv_GetDeviceGroupPeerMemoryFeatures(
5360 VkDevice device,
5361 uint32_t heapIndex,
5362 uint32_t localDeviceIndex,
5363 uint32_t remoteDeviceIndex,
5364 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5365 {
5366 assert(localDeviceIndex == remoteDeviceIndex);
5367
5368 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5369 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5370 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5371 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5372 }
5373
5374 static const VkTimeDomainEXT radv_time_domains[] = {
5375 VK_TIME_DOMAIN_DEVICE_EXT,
5376 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5377 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5378 };
5379
5380 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5381 VkPhysicalDevice physicalDevice,
5382 uint32_t *pTimeDomainCount,
5383 VkTimeDomainEXT *pTimeDomains)
5384 {
5385 int d;
5386 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5387
5388 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5389 vk_outarray_append(&out, i) {
5390 *i = radv_time_domains[d];
5391 }
5392 }
5393
5394 return vk_outarray_status(&out);
5395 }
5396
5397 static uint64_t
5398 radv_clock_gettime(clockid_t clock_id)
5399 {
5400 struct timespec current;
5401 int ret;
5402
5403 ret = clock_gettime(clock_id, &current);
5404 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5405 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5406 if (ret < 0)
5407 return 0;
5408
5409 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5410 }
5411
5412 VkResult radv_GetCalibratedTimestampsEXT(
5413 VkDevice _device,
5414 uint32_t timestampCount,
5415 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5416 uint64_t *pTimestamps,
5417 uint64_t *pMaxDeviation)
5418 {
5419 RADV_FROM_HANDLE(radv_device, device, _device);
5420 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5421 int d;
5422 uint64_t begin, end;
5423 uint64_t max_clock_period = 0;
5424
5425 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5426
5427 for (d = 0; d < timestampCount; d++) {
5428 switch (pTimestampInfos[d].timeDomain) {
5429 case VK_TIME_DOMAIN_DEVICE_EXT:
5430 pTimestamps[d] = device->ws->query_value(device->ws,
5431 RADEON_TIMESTAMP);
5432 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5433 max_clock_period = MAX2(max_clock_period, device_period);
5434 break;
5435 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5436 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5437 max_clock_period = MAX2(max_clock_period, 1);
5438 break;
5439
5440 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5441 pTimestamps[d] = begin;
5442 break;
5443 default:
5444 pTimestamps[d] = 0;
5445 break;
5446 }
5447 }
5448
5449 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5450
5451 /*
5452 * The maximum deviation is the sum of the interval over which we
5453 * perform the sampling and the maximum period of any sampled
5454 * clock. That's because the maximum skew between any two sampled
5455 * clock edges is when the sampled clock with the largest period is
5456 * sampled at the end of that period but right at the beginning of the
5457 * sampling interval and some other clock is sampled right at the
5458 * begining of its sampling period and right at the end of the
5459 * sampling interval. Let's assume the GPU has the longest clock
5460 * period and that the application is sampling GPU and monotonic:
5461 *
5462 * s e
5463 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5464 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5465 *
5466 * g
5467 * 0 1 2 3
5468 * GPU -----_____-----_____-----_____-----_____
5469 *
5470 * m
5471 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5472 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5473 *
5474 * Interval <----------------->
5475 * Deviation <-------------------------->
5476 *
5477 * s = read(raw) 2
5478 * g = read(GPU) 1
5479 * m = read(monotonic) 2
5480 * e = read(raw) b
5481 *
5482 * We round the sample interval up by one tick to cover sampling error
5483 * in the interval clock
5484 */
5485
5486 uint64_t sample_interval = end - begin + 1;
5487
5488 *pMaxDeviation = sample_interval + max_clock_period;
5489
5490 return VK_SUCCESS;
5491 }
5492
5493 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5494 VkPhysicalDevice physicalDevice,
5495 VkSampleCountFlagBits samples,
5496 VkMultisamplePropertiesEXT* pMultisampleProperties)
5497 {
5498 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5499 VK_SAMPLE_COUNT_4_BIT |
5500 VK_SAMPLE_COUNT_8_BIT)) {
5501 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5502 } else {
5503 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5504 }
5505 }