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radv/gfx10: add Wave32 support for vertex, tessellation and geometry shaders
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "util/build_id.h"
48 #include "util/debug.h"
49 #include "util/mesa-sha1.h"
50 #include "compiler/glsl_types.h"
51 #include "util/xmlpool.h"
52
53 static int
54 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
55 {
56 struct mesa_sha1 ctx;
57 unsigned char sha1[20];
58 unsigned ptr_size = sizeof(void*);
59
60 memset(uuid, 0, VK_UUID_SIZE);
61 _mesa_sha1_init(&ctx);
62
63 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
64 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
65 return -1;
66
67 _mesa_sha1_update(&ctx, &family, sizeof(family));
68 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
69 _mesa_sha1_final(&ctx, sha1);
70
71 memcpy(uuid, sha1, VK_UUID_SIZE);
72 return 0;
73 }
74
75 static void
76 radv_get_driver_uuid(void *uuid)
77 {
78 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
79 }
80
81 static void
82 radv_get_device_uuid(struct radeon_info *info, void *uuid)
83 {
84 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
85 }
86
87 static void
88 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
89 {
90 const char *chip_string;
91
92 switch (family) {
93 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
94 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
95 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
96 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
97 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
98 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
99 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
100 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
101 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
102 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
103 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
104 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
105 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
106 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
107 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
108 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
109 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
110 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
111 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
112 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
113 case CHIP_VEGA20: chip_string = "AMD RADV VEGA20"; break;
114 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
115 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
116 case CHIP_NAVI10: chip_string = "AMD RADV NAVI10"; break;
117 case CHIP_NAVI12: chip_string = "AMD RADV NAVI12"; break;
118 case CHIP_NAVI14: chip_string = "AMD RADV NAVI14"; break;
119 default: chip_string = "AMD RADV unknown"; break;
120 }
121
122 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
123 }
124
125 static uint64_t
126 radv_get_visible_vram_size(struct radv_physical_device *device)
127 {
128 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
129 }
130
131 static uint64_t
132 radv_get_vram_size(struct radv_physical_device *device)
133 {
134 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
135 }
136
137 static void
138 radv_physical_device_init_mem_types(struct radv_physical_device *device)
139 {
140 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
141 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
142 uint64_t vram_size = radv_get_vram_size(device);
143 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
144 device->memory_properties.memoryHeapCount = 0;
145 if (vram_size > 0) {
146 vram_index = device->memory_properties.memoryHeapCount++;
147 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
148 .size = vram_size,
149 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
150 };
151 }
152 if (visible_vram_size) {
153 visible_vram_index = device->memory_properties.memoryHeapCount++;
154 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
155 .size = visible_vram_size,
156 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
157 };
158 }
159 if (device->rad_info.gart_size > 0) {
160 gart_index = device->memory_properties.memoryHeapCount++;
161 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
162 .size = device->rad_info.gart_size,
163 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
164 };
165 }
166
167 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
168 unsigned type_count = 0;
169 if (vram_index >= 0) {
170 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
171 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
172 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
173 .heapIndex = vram_index,
174 };
175 }
176 if (gart_index >= 0) {
177 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
178 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
179 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
180 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 if (visible_vram_index >= 0) {
186 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
187 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
188 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
189 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
190 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
191 .heapIndex = visible_vram_index,
192 };
193 }
194 if (gart_index >= 0) {
195 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
196 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
197 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
198 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
199 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
200 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
201 .heapIndex = gart_index,
202 };
203 }
204 device->memory_properties.memoryTypeCount = type_count;
205 }
206
207 static void
208 radv_handle_env_var_force_family(struct radv_physical_device *device)
209 {
210 const char *family = getenv("RADV_FORCE_FAMILY");
211 unsigned i;
212
213 if (!family)
214 return;
215
216 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
217 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
218 /* Override family and chip_class. */
219 device->rad_info.family = i;
220
221 if (i >= CHIP_NAVI10)
222 device->rad_info.chip_class = GFX10;
223 else if (i >= CHIP_VEGA10)
224 device->rad_info.chip_class = GFX9;
225 else if (i >= CHIP_TONGA)
226 device->rad_info.chip_class = GFX8;
227 else if (i >= CHIP_BONAIRE)
228 device->rad_info.chip_class = GFX7;
229 else
230 device->rad_info.chip_class = GFX6;
231
232 return;
233 }
234 }
235
236 fprintf(stderr, "radv: Unknown family: %s\n", family);
237 exit(1);
238 }
239
240 static VkResult
241 radv_physical_device_init(struct radv_physical_device *device,
242 struct radv_instance *instance,
243 drmDevicePtr drm_device)
244 {
245 const char *path = drm_device->nodes[DRM_NODE_RENDER];
246 VkResult result;
247 drmVersionPtr version;
248 int fd;
249 int master_fd = -1;
250
251 fd = open(path, O_RDWR | O_CLOEXEC);
252 if (fd < 0) {
253 if (instance->debug_flags & RADV_DEBUG_STARTUP)
254 radv_logi("Could not open device '%s'", path);
255
256 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
257 }
258
259 version = drmGetVersion(fd);
260 if (!version) {
261 close(fd);
262
263 if (instance->debug_flags & RADV_DEBUG_STARTUP)
264 radv_logi("Could not get the kernel driver version for device '%s'", path);
265
266 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
267 "failed to get version %s: %m", path);
268 }
269
270 if (strcmp(version->name, "amdgpu")) {
271 drmFreeVersion(version);
272 close(fd);
273
274 if (instance->debug_flags & RADV_DEBUG_STARTUP)
275 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
276
277 return VK_ERROR_INCOMPATIBLE_DRIVER;
278 }
279 drmFreeVersion(version);
280
281 if (instance->debug_flags & RADV_DEBUG_STARTUP)
282 radv_logi("Found compatible device '%s'.", path);
283
284 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
285 device->instance = instance;
286
287 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
288 instance->perftest_flags);
289 if (!device->ws) {
290 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
291 goto fail;
292 }
293
294 if (instance->enabled_extensions.KHR_display) {
295 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
296 if (master_fd >= 0) {
297 uint32_t accel_working = 0;
298 struct drm_amdgpu_info request = {
299 .return_pointer = (uintptr_t)&accel_working,
300 .return_size = sizeof(accel_working),
301 .query = AMDGPU_INFO_ACCEL_WORKING
302 };
303
304 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
305 close(master_fd);
306 master_fd = -1;
307 }
308 }
309 }
310
311 device->master_fd = master_fd;
312 device->local_fd = fd;
313 device->ws->query_info(device->ws, &device->rad_info);
314
315 radv_handle_env_var_force_family(device);
316
317 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
318
319 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
320 device->ws->destroy(device->ws);
321 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
322 "cannot generate UUID");
323 goto fail;
324 }
325
326 /* These flags affect shader compilation. */
327 uint64_t shader_env_flags =
328 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
329 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
330
331 /* The gpu id is already embedded in the uuid so we just pass "radv"
332 * when creating the cache.
333 */
334 char buf[VK_UUID_SIZE * 2 + 1];
335 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
336 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
337
338 if (device->rad_info.chip_class < GFX8 ||
339 device->rad_info.chip_class > GFX9)
340 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
341
342 radv_get_driver_uuid(&device->driver_uuid);
343 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
344
345 if (device->rad_info.family == CHIP_STONEY ||
346 device->rad_info.chip_class >= GFX9) {
347 device->has_rbplus = true;
348 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
349 device->rad_info.family == CHIP_VEGA12 ||
350 device->rad_info.family == CHIP_RAVEN ||
351 device->rad_info.family == CHIP_RAVEN2;
352 }
353
354 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
355 * on GFX6.
356 */
357 device->has_clear_state = device->rad_info.chip_class >= GFX7;
358
359 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= GFX8;
360
361 /* Vega10/Raven need a special workaround for a hardware bug. */
362 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
363 device->rad_info.family == CHIP_RAVEN;
364
365 device->has_tc_compat_zrange_bug = device->rad_info.chip_class < GFX10;
366
367 /* Out-of-order primitive rasterization. */
368 device->has_out_of_order_rast = device->rad_info.chip_class >= GFX8 &&
369 device->rad_info.max_se >= 2;
370 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
371 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
372
373 device->dcc_msaa_allowed =
374 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
375
376 /* TODO: Figure out how to use LOAD_CONTEXT_REG on GFX6-GFX7. */
377 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
378 (device->rad_info.chip_class >= GFX8 &&
379 device->rad_info.me_fw_feature >= 41);
380
381 device->has_dcc_constant_encode = device->rad_info.family == CHIP_RAVEN2 ||
382 device->rad_info.chip_class >= GFX10;
383
384 device->use_shader_ballot = device->instance->perftest_flags & RADV_PERFTEST_SHADER_BALLOT;
385
386 /* Determine the number of threads per wave for all stages. */
387 device->cs_wave_size = 64;
388 device->ps_wave_size = 64;
389 device->ge_wave_size = 64;
390
391 if (device->rad_info.chip_class >= GFX10) {
392 if (device->instance->perftest_flags & RADV_PERFTEST_CS_WAVE_32)
393 device->cs_wave_size = 32;
394
395 /* For pixel shaders, wave64 is recommanded. */
396 if (device->instance->perftest_flags & RADV_PERFTEST_PS_WAVE_32)
397 device->ps_wave_size = 32;
398
399 if (device->instance->perftest_flags & RADV_PERFTEST_GE_WAVE_32)
400 device->ge_wave_size = 32;
401 }
402
403 radv_physical_device_init_mem_types(device);
404 radv_fill_device_extension_table(device, &device->supported_extensions);
405
406 device->bus_info = *drm_device->businfo.pci;
407
408 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
409 ac_print_gpu_info(&device->rad_info);
410
411 /* The WSI is structured as a layer on top of the driver, so this has
412 * to be the last part of initialization (at least until we get other
413 * semi-layers).
414 */
415 result = radv_init_wsi(device);
416 if (result != VK_SUCCESS) {
417 device->ws->destroy(device->ws);
418 vk_error(instance, result);
419 goto fail;
420 }
421
422 return VK_SUCCESS;
423
424 fail:
425 close(fd);
426 if (master_fd != -1)
427 close(master_fd);
428 return result;
429 }
430
431 static void
432 radv_physical_device_finish(struct radv_physical_device *device)
433 {
434 radv_finish_wsi(device);
435 device->ws->destroy(device->ws);
436 disk_cache_destroy(device->disk_cache);
437 close(device->local_fd);
438 if (device->master_fd != -1)
439 close(device->master_fd);
440 }
441
442 static void *
443 default_alloc_func(void *pUserData, size_t size, size_t align,
444 VkSystemAllocationScope allocationScope)
445 {
446 return malloc(size);
447 }
448
449 static void *
450 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
451 size_t align, VkSystemAllocationScope allocationScope)
452 {
453 return realloc(pOriginal, size);
454 }
455
456 static void
457 default_free_func(void *pUserData, void *pMemory)
458 {
459 free(pMemory);
460 }
461
462 static const VkAllocationCallbacks default_alloc = {
463 .pUserData = NULL,
464 .pfnAllocation = default_alloc_func,
465 .pfnReallocation = default_realloc_func,
466 .pfnFree = default_free_func,
467 };
468
469 static const struct debug_control radv_debug_options[] = {
470 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
471 {"nodcc", RADV_DEBUG_NO_DCC},
472 {"shaders", RADV_DEBUG_DUMP_SHADERS},
473 {"nocache", RADV_DEBUG_NO_CACHE},
474 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
475 {"nohiz", RADV_DEBUG_NO_HIZ},
476 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
477 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
478 {"allbos", RADV_DEBUG_ALL_BOS},
479 {"noibs", RADV_DEBUG_NO_IBS},
480 {"spirv", RADV_DEBUG_DUMP_SPIRV},
481 {"vmfaults", RADV_DEBUG_VM_FAULTS},
482 {"zerovram", RADV_DEBUG_ZERO_VRAM},
483 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
484 {"nosisched", RADV_DEBUG_NO_SISCHED},
485 {"preoptir", RADV_DEBUG_PREOPTIR},
486 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
487 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
488 {"info", RADV_DEBUG_INFO},
489 {"errors", RADV_DEBUG_ERRORS},
490 {"startup", RADV_DEBUG_STARTUP},
491 {"checkir", RADV_DEBUG_CHECKIR},
492 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
493 {"nobinning", RADV_DEBUG_NOBINNING},
494 {"noloadstoreopt", RADV_DEBUG_NO_LOAD_STORE_OPT},
495 {"nongg", RADV_DEBUG_NO_NGG},
496 {NULL, 0}
497 };
498
499 const char *
500 radv_get_debug_option_name(int id)
501 {
502 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
503 return radv_debug_options[id].string;
504 }
505
506 static const struct debug_control radv_perftest_options[] = {
507 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
508 {"sisched", RADV_PERFTEST_SISCHED},
509 {"localbos", RADV_PERFTEST_LOCAL_BOS},
510 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
511 {"bolist", RADV_PERFTEST_BO_LIST},
512 {"shader_ballot", RADV_PERFTEST_SHADER_BALLOT},
513 {"tccompatcmask", RADV_PERFTEST_TC_COMPAT_CMASK},
514 {"cswave32", RADV_PERFTEST_CS_WAVE_32},
515 {"pswave32", RADV_PERFTEST_PS_WAVE_32},
516 {"gewave32", RADV_PERFTEST_GE_WAVE_32},
517 {NULL, 0}
518 };
519
520 const char *
521 radv_get_perftest_option_name(int id)
522 {
523 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
524 return radv_perftest_options[id].string;
525 }
526
527 static void
528 radv_handle_per_app_options(struct radv_instance *instance,
529 const VkApplicationInfo *info)
530 {
531 const char *name = info ? info->pApplicationName : NULL;
532
533 if (!name)
534 return;
535
536 if (!strcmp(name, "Talos - Linux - 32bit") ||
537 !strcmp(name, "Talos - Linux - 64bit")) {
538 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
539 /* Force enable LLVM sisched for Talos because it looks
540 * safe and it gives few more FPS.
541 */
542 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
543 }
544 } else if (!strcmp(name, "DOOM_VFR")) {
545 /* Work around a Doom VFR game bug */
546 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
547 } else if (!strcmp(name, "MonsterHunterWorld.exe")) {
548 /* Workaround for a WaW hazard when LLVM moves/merges
549 * load/store memory operations.
550 * See https://reviews.llvm.org/D61313
551 */
552 if (HAVE_LLVM < 0x900)
553 instance->debug_flags |= RADV_DEBUG_NO_LOAD_STORE_OPT;
554 }
555 }
556
557 static int radv_get_instance_extension_index(const char *name)
558 {
559 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
560 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
561 return i;
562 }
563 return -1;
564 }
565
566 static const char radv_dri_options_xml[] =
567 DRI_CONF_BEGIN
568 DRI_CONF_SECTION_QUALITY
569 DRI_CONF_ADAPTIVE_SYNC("true")
570 DRI_CONF_SECTION_END
571 DRI_CONF_END;
572
573 static void radv_init_dri_options(struct radv_instance *instance)
574 {
575 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
576 driParseConfigFiles(&instance->dri_options,
577 &instance->available_dri_options,
578 0, "radv", NULL);
579 }
580
581 VkResult radv_CreateInstance(
582 const VkInstanceCreateInfo* pCreateInfo,
583 const VkAllocationCallbacks* pAllocator,
584 VkInstance* pInstance)
585 {
586 struct radv_instance *instance;
587 VkResult result;
588
589 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
590
591 uint32_t client_version;
592 if (pCreateInfo->pApplicationInfo &&
593 pCreateInfo->pApplicationInfo->apiVersion != 0) {
594 client_version = pCreateInfo->pApplicationInfo->apiVersion;
595 } else {
596 client_version = VK_API_VERSION_1_0;
597 }
598
599 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
600 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
601 if (!instance)
602 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
603
604 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
605
606 if (pAllocator)
607 instance->alloc = *pAllocator;
608 else
609 instance->alloc = default_alloc;
610
611 instance->apiVersion = client_version;
612 instance->physicalDeviceCount = -1;
613
614 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
615 radv_debug_options);
616
617 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
618 radv_perftest_options);
619
620
621 if (instance->debug_flags & RADV_DEBUG_STARTUP)
622 radv_logi("Created an instance");
623
624 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
625 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
626 int index = radv_get_instance_extension_index(ext_name);
627
628 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
629 vk_free2(&default_alloc, pAllocator, instance);
630 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
631 }
632
633 instance->enabled_extensions.extensions[index] = true;
634 }
635
636 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
637 if (result != VK_SUCCESS) {
638 vk_free2(&default_alloc, pAllocator, instance);
639 return vk_error(instance, result);
640 }
641
642 _mesa_locale_init();
643 glsl_type_singleton_init_or_ref();
644
645 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
646
647 radv_init_dri_options(instance);
648 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
649
650 *pInstance = radv_instance_to_handle(instance);
651
652 return VK_SUCCESS;
653 }
654
655 void radv_DestroyInstance(
656 VkInstance _instance,
657 const VkAllocationCallbacks* pAllocator)
658 {
659 RADV_FROM_HANDLE(radv_instance, instance, _instance);
660
661 if (!instance)
662 return;
663
664 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
665 radv_physical_device_finish(instance->physicalDevices + i);
666 }
667
668 VG(VALGRIND_DESTROY_MEMPOOL(instance));
669
670 glsl_type_singleton_decref();
671 _mesa_locale_fini();
672
673 driDestroyOptionCache(&instance->dri_options);
674 driDestroyOptionInfo(&instance->available_dri_options);
675
676 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
677
678 vk_free(&instance->alloc, instance);
679 }
680
681 static VkResult
682 radv_enumerate_devices(struct radv_instance *instance)
683 {
684 /* TODO: Check for more devices ? */
685 drmDevicePtr devices[8];
686 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
687 int max_devices;
688
689 instance->physicalDeviceCount = 0;
690
691 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
692
693 if (instance->debug_flags & RADV_DEBUG_STARTUP)
694 radv_logi("Found %d drm nodes", max_devices);
695
696 if (max_devices < 1)
697 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
698
699 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
700 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
701 devices[i]->bustype == DRM_BUS_PCI &&
702 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
703
704 result = radv_physical_device_init(instance->physicalDevices +
705 instance->physicalDeviceCount,
706 instance,
707 devices[i]);
708 if (result == VK_SUCCESS)
709 ++instance->physicalDeviceCount;
710 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
711 break;
712 }
713 }
714 drmFreeDevices(devices, max_devices);
715
716 return result;
717 }
718
719 VkResult radv_EnumeratePhysicalDevices(
720 VkInstance _instance,
721 uint32_t* pPhysicalDeviceCount,
722 VkPhysicalDevice* pPhysicalDevices)
723 {
724 RADV_FROM_HANDLE(radv_instance, instance, _instance);
725 VkResult result;
726
727 if (instance->physicalDeviceCount < 0) {
728 result = radv_enumerate_devices(instance);
729 if (result != VK_SUCCESS &&
730 result != VK_ERROR_INCOMPATIBLE_DRIVER)
731 return result;
732 }
733
734 if (!pPhysicalDevices) {
735 *pPhysicalDeviceCount = instance->physicalDeviceCount;
736 } else {
737 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
738 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
739 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
740 }
741
742 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
743 : VK_SUCCESS;
744 }
745
746 VkResult radv_EnumeratePhysicalDeviceGroups(
747 VkInstance _instance,
748 uint32_t* pPhysicalDeviceGroupCount,
749 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
750 {
751 RADV_FROM_HANDLE(radv_instance, instance, _instance);
752 VkResult result;
753
754 if (instance->physicalDeviceCount < 0) {
755 result = radv_enumerate_devices(instance);
756 if (result != VK_SUCCESS &&
757 result != VK_ERROR_INCOMPATIBLE_DRIVER)
758 return result;
759 }
760
761 if (!pPhysicalDeviceGroupProperties) {
762 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
763 } else {
764 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
765 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
766 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
767 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
768 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
769 }
770 }
771 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
772 : VK_SUCCESS;
773 }
774
775 void radv_GetPhysicalDeviceFeatures(
776 VkPhysicalDevice physicalDevice,
777 VkPhysicalDeviceFeatures* pFeatures)
778 {
779 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
780 memset(pFeatures, 0, sizeof(*pFeatures));
781
782 *pFeatures = (VkPhysicalDeviceFeatures) {
783 .robustBufferAccess = true,
784 .fullDrawIndexUint32 = true,
785 .imageCubeArray = true,
786 .independentBlend = true,
787 .geometryShader = true,
788 .tessellationShader = true,
789 .sampleRateShading = true,
790 .dualSrcBlend = true,
791 .logicOp = true,
792 .multiDrawIndirect = true,
793 .drawIndirectFirstInstance = true,
794 .depthClamp = true,
795 .depthBiasClamp = true,
796 .fillModeNonSolid = true,
797 .depthBounds = true,
798 .wideLines = true,
799 .largePoints = true,
800 .alphaToOne = true,
801 .multiViewport = true,
802 .samplerAnisotropy = true,
803 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
804 .textureCompressionASTC_LDR = false,
805 .textureCompressionBC = true,
806 .occlusionQueryPrecise = true,
807 .pipelineStatisticsQuery = true,
808 .vertexPipelineStoresAndAtomics = true,
809 .fragmentStoresAndAtomics = true,
810 .shaderTessellationAndGeometryPointSize = true,
811 .shaderImageGatherExtended = true,
812 .shaderStorageImageExtendedFormats = true,
813 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= GFX8,
814 .shaderUniformBufferArrayDynamicIndexing = true,
815 .shaderSampledImageArrayDynamicIndexing = true,
816 .shaderStorageBufferArrayDynamicIndexing = true,
817 .shaderStorageImageArrayDynamicIndexing = true,
818 .shaderStorageImageReadWithoutFormat = true,
819 .shaderStorageImageWriteWithoutFormat = true,
820 .shaderClipDistance = true,
821 .shaderCullDistance = true,
822 .shaderFloat64 = true,
823 .shaderInt64 = true,
824 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
825 .sparseBinding = true,
826 .variableMultisampleRate = true,
827 .inheritedQueries = true,
828 };
829 }
830
831 void radv_GetPhysicalDeviceFeatures2(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceFeatures2 *pFeatures)
834 {
835 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
836 vk_foreach_struct(ext, pFeatures->pNext) {
837 switch (ext->sType) {
838 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTERS_FEATURES: {
839 VkPhysicalDeviceVariablePointersFeatures *features = (void *)ext;
840 features->variablePointersStorageBuffer = true;
841 features->variablePointers = true;
842 break;
843 }
844 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
845 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
846 features->multiview = true;
847 features->multiviewGeometryShader = true;
848 features->multiviewTessellationShader = true;
849 break;
850 }
851 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETERS_FEATURES: {
852 VkPhysicalDeviceShaderDrawParametersFeatures *features =
853 (VkPhysicalDeviceShaderDrawParametersFeatures*)ext;
854 features->shaderDrawParameters = true;
855 break;
856 }
857 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
858 VkPhysicalDeviceProtectedMemoryFeatures *features =
859 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
860 features->protectedMemory = false;
861 break;
862 }
863 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
864 VkPhysicalDevice16BitStorageFeatures *features =
865 (VkPhysicalDevice16BitStorageFeatures*)ext;
866 bool enabled = pdevice->rad_info.chip_class >= GFX8;
867 features->storageBuffer16BitAccess = enabled;
868 features->uniformAndStorageBuffer16BitAccess = enabled;
869 features->storagePushConstant16 = enabled;
870 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
871 break;
872 }
873 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
874 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
875 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
876 features->samplerYcbcrConversion = true;
877 break;
878 }
879 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
880 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
881 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
882 features->shaderInputAttachmentArrayDynamicIndexing = true;
883 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
884 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
885 features->shaderUniformBufferArrayNonUniformIndexing = true;
886 features->shaderSampledImageArrayNonUniformIndexing = true;
887 features->shaderStorageBufferArrayNonUniformIndexing = true;
888 features->shaderStorageImageArrayNonUniformIndexing = true;
889 features->shaderInputAttachmentArrayNonUniformIndexing = true;
890 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
891 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
892 features->descriptorBindingUniformBufferUpdateAfterBind = true;
893 features->descriptorBindingSampledImageUpdateAfterBind = true;
894 features->descriptorBindingStorageImageUpdateAfterBind = true;
895 features->descriptorBindingStorageBufferUpdateAfterBind = true;
896 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
897 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
898 features->descriptorBindingUpdateUnusedWhilePending = true;
899 features->descriptorBindingPartiallyBound = true;
900 features->descriptorBindingVariableDescriptorCount = true;
901 features->runtimeDescriptorArray = true;
902 break;
903 }
904 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
905 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
906 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
907 features->conditionalRendering = true;
908 features->inheritedConditionalRendering = false;
909 break;
910 }
911 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
912 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
913 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
914 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
915 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
916 break;
917 }
918 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
919 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
920 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
921 features->transformFeedback = true;
922 features->geometryStreams = true;
923 break;
924 }
925 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
926 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
927 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
928 features->scalarBlockLayout = pdevice->rad_info.chip_class >= GFX7;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
932 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
933 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
934 features->memoryPriority = VK_TRUE;
935 break;
936 }
937 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_DEVICE_ADDRESS_FEATURES_EXT: {
938 VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *features =
939 (VkPhysicalDeviceBufferDeviceAddressFeaturesEXT *)ext;
940 features->bufferDeviceAddress = true;
941 features->bufferDeviceAddressCaptureReplay = false;
942 features->bufferDeviceAddressMultiDevice = false;
943 break;
944 }
945 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
946 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
947 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
948 features->depthClipEnable = true;
949 break;
950 }
951 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
952 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
953 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
954 features->hostQueryReset = true;
955 break;
956 }
957 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
958 VkPhysicalDevice8BitStorageFeaturesKHR *features =
959 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
960 bool enabled = pdevice->rad_info.chip_class >= GFX8;
961 features->storageBuffer8BitAccess = enabled;
962 features->uniformAndStorageBuffer8BitAccess = enabled;
963 features->storagePushConstant8 = enabled;
964 break;
965 }
966 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
967 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
968 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
969 features->shaderFloat16 = pdevice->rad_info.chip_class >= GFX8 && HAVE_LLVM >= 0x0800;
970 features->shaderInt8 = true;
971 break;
972 }
973 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
974 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
975 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
976 /* TODO: Enable this once the driver supports 64-bit
977 * compare&swap atomic operations.
978 */
979 features->shaderBufferInt64Atomics = false;
980 features->shaderSharedInt64Atomics = false;
981 break;
982 }
983 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
984 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
985 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
986
987 features->inlineUniformBlock = true;
988 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
989 break;
990 }
991 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
992 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
993 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
994 features->computeDerivativeGroupQuads = false;
995 features->computeDerivativeGroupLinear = true;
996 break;
997 }
998 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
999 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
1000 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
1001 features->ycbcrImageArrays = true;
1002 break;
1003 }
1004 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_UNIFORM_BUFFER_STANDARD_LAYOUT_FEATURES_KHR: {
1005 VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *features =
1006 (VkPhysicalDeviceUniformBufferStandardLayoutFeaturesKHR *)ext;
1007 features->uniformBufferStandardLayout = true;
1008 break;
1009 }
1010 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INDEX_TYPE_UINT8_FEATURES_EXT: {
1011 VkPhysicalDeviceIndexTypeUint8FeaturesEXT *features =
1012 (VkPhysicalDeviceIndexTypeUint8FeaturesEXT *)ext;
1013 features->indexTypeUint8 = pdevice->rad_info.chip_class >= GFX8;
1014 break;
1015 }
1016 default:
1017 break;
1018 }
1019 }
1020 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
1021 }
1022
1023 void radv_GetPhysicalDeviceProperties(
1024 VkPhysicalDevice physicalDevice,
1025 VkPhysicalDeviceProperties* pProperties)
1026 {
1027 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1028 VkSampleCountFlags sample_counts = 0xf;
1029
1030 /* make sure that the entire descriptor set is addressable with a signed
1031 * 32-bit int. So the sum of all limits scaled by descriptor size has to
1032 * be at most 2 GiB. the combined image & samples object count as one of
1033 * both. This limit is for the pipeline layout, not for the set layout, but
1034 * there is no set limit, so we just set a pipeline limit. I don't think
1035 * any app is going to hit this soon. */
1036 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1037 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1038 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1039 32 /* sampler, largest when combined with image */ +
1040 64 /* sampled image */ +
1041 64 /* storage image */);
1042
1043 VkPhysicalDeviceLimits limits = {
1044 .maxImageDimension1D = (1 << 14),
1045 .maxImageDimension2D = (1 << 14),
1046 .maxImageDimension3D = (1 << 11),
1047 .maxImageDimensionCube = (1 << 14),
1048 .maxImageArrayLayers = (1 << 11),
1049 .maxTexelBufferElements = 128 * 1024 * 1024,
1050 .maxUniformBufferRange = UINT32_MAX,
1051 .maxStorageBufferRange = UINT32_MAX,
1052 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
1053 .maxMemoryAllocationCount = UINT32_MAX,
1054 .maxSamplerAllocationCount = 64 * 1024,
1055 .bufferImageGranularity = 64, /* A cache line */
1056 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1057 .maxBoundDescriptorSets = MAX_SETS,
1058 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1059 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1060 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1061 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1062 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1063 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1064 .maxPerStageResources = max_descriptor_set_size,
1065 .maxDescriptorSetSamplers = max_descriptor_set_size,
1066 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1067 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1068 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1069 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1070 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1071 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1072 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1073 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1074 .maxVertexInputBindings = MAX_VBS,
1075 .maxVertexInputAttributeOffset = 2047,
1076 .maxVertexInputBindingStride = 2048,
1077 .maxVertexOutputComponents = 128,
1078 .maxTessellationGenerationLevel = 64,
1079 .maxTessellationPatchSize = 32,
1080 .maxTessellationControlPerVertexInputComponents = 128,
1081 .maxTessellationControlPerVertexOutputComponents = 128,
1082 .maxTessellationControlPerPatchOutputComponents = 120,
1083 .maxTessellationControlTotalOutputComponents = 4096,
1084 .maxTessellationEvaluationInputComponents = 128,
1085 .maxTessellationEvaluationOutputComponents = 128,
1086 .maxGeometryShaderInvocations = 127,
1087 .maxGeometryInputComponents = 64,
1088 .maxGeometryOutputComponents = 128,
1089 .maxGeometryOutputVertices = 256,
1090 .maxGeometryTotalOutputComponents = 1024,
1091 .maxFragmentInputComponents = 128,
1092 .maxFragmentOutputAttachments = 8,
1093 .maxFragmentDualSrcAttachments = 1,
1094 .maxFragmentCombinedOutputResources = 8,
1095 .maxComputeSharedMemorySize = 32768,
1096 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1097 .maxComputeWorkGroupInvocations = 2048,
1098 .maxComputeWorkGroupSize = {
1099 2048,
1100 2048,
1101 2048
1102 },
1103 .subPixelPrecisionBits = 8,
1104 .subTexelPrecisionBits = 8,
1105 .mipmapPrecisionBits = 8,
1106 .maxDrawIndexedIndexValue = UINT32_MAX,
1107 .maxDrawIndirectCount = UINT32_MAX,
1108 .maxSamplerLodBias = 16,
1109 .maxSamplerAnisotropy = 16,
1110 .maxViewports = MAX_VIEWPORTS,
1111 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1112 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1113 .viewportSubPixelBits = 8,
1114 .minMemoryMapAlignment = 4096, /* A page */
1115 .minTexelBufferOffsetAlignment = 1,
1116 .minUniformBufferOffsetAlignment = 4,
1117 .minStorageBufferOffsetAlignment = 4,
1118 .minTexelOffset = -32,
1119 .maxTexelOffset = 31,
1120 .minTexelGatherOffset = -32,
1121 .maxTexelGatherOffset = 31,
1122 .minInterpolationOffset = -2,
1123 .maxInterpolationOffset = 2,
1124 .subPixelInterpolationOffsetBits = 8,
1125 .maxFramebufferWidth = (1 << 14),
1126 .maxFramebufferHeight = (1 << 14),
1127 .maxFramebufferLayers = (1 << 10),
1128 .framebufferColorSampleCounts = sample_counts,
1129 .framebufferDepthSampleCounts = sample_counts,
1130 .framebufferStencilSampleCounts = sample_counts,
1131 .framebufferNoAttachmentsSampleCounts = sample_counts,
1132 .maxColorAttachments = MAX_RTS,
1133 .sampledImageColorSampleCounts = sample_counts,
1134 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1135 .sampledImageDepthSampleCounts = sample_counts,
1136 .sampledImageStencilSampleCounts = sample_counts,
1137 .storageImageSampleCounts = pdevice->rad_info.chip_class >= GFX8 ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1138 .maxSampleMaskWords = 1,
1139 .timestampComputeAndGraphics = true,
1140 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1141 .maxClipDistances = 8,
1142 .maxCullDistances = 8,
1143 .maxCombinedClipAndCullDistances = 8,
1144 .discreteQueuePriorities = 2,
1145 .pointSizeRange = { 0.0, 8192.0 },
1146 .lineWidthRange = { 0.0, 7.9921875 },
1147 .pointSizeGranularity = (1.0 / 8.0),
1148 .lineWidthGranularity = (1.0 / 128.0),
1149 .strictLines = false, /* FINISHME */
1150 .standardSampleLocations = true,
1151 .optimalBufferCopyOffsetAlignment = 128,
1152 .optimalBufferCopyRowPitchAlignment = 128,
1153 .nonCoherentAtomSize = 64,
1154 };
1155
1156 *pProperties = (VkPhysicalDeviceProperties) {
1157 .apiVersion = radv_physical_device_api_version(pdevice),
1158 .driverVersion = vk_get_driver_version(),
1159 .vendorID = ATI_VENDOR_ID,
1160 .deviceID = pdevice->rad_info.pci_id,
1161 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1162 .limits = limits,
1163 .sparseProperties = {0},
1164 };
1165
1166 strcpy(pProperties->deviceName, pdevice->name);
1167 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1168 }
1169
1170 void radv_GetPhysicalDeviceProperties2(
1171 VkPhysicalDevice physicalDevice,
1172 VkPhysicalDeviceProperties2 *pProperties)
1173 {
1174 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1175 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1176
1177 vk_foreach_struct(ext, pProperties->pNext) {
1178 switch (ext->sType) {
1179 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1180 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1181 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1182 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1183 break;
1184 }
1185 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1186 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1187 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1188 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1189 properties->deviceLUIDValid = false;
1190 break;
1191 }
1192 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1193 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1194 properties->maxMultiviewViewCount = MAX_VIEWS;
1195 properties->maxMultiviewInstanceIndex = INT_MAX;
1196 break;
1197 }
1198 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1199 VkPhysicalDevicePointClippingProperties *properties =
1200 (VkPhysicalDevicePointClippingProperties*)ext;
1201 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1202 break;
1203 }
1204 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1205 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1206 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1207 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1208 break;
1209 }
1210 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1211 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1212 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1213 properties->minImportedHostPointerAlignment = 4096;
1214 break;
1215 }
1216 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1217 VkPhysicalDeviceSubgroupProperties *properties =
1218 (VkPhysicalDeviceSubgroupProperties*)ext;
1219 properties->subgroupSize = 64;
1220 properties->supportedStages = VK_SHADER_STAGE_ALL;
1221 properties->supportedOperations =
1222 VK_SUBGROUP_FEATURE_BASIC_BIT |
1223 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1224 VK_SUBGROUP_FEATURE_QUAD_BIT |
1225 VK_SUBGROUP_FEATURE_VOTE_BIT;
1226 if (pdevice->rad_info.chip_class >= GFX8) {
1227 properties->supportedOperations |=
1228 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1229 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1230 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1231 }
1232 properties->quadOperationsInAllStages = true;
1233 break;
1234 }
1235 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1236 VkPhysicalDeviceMaintenance3Properties *properties =
1237 (VkPhysicalDeviceMaintenance3Properties*)ext;
1238 /* Make sure everything is addressable by a signed 32-bit int, and
1239 * our largest descriptors are 96 bytes. */
1240 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1241 /* Our buffer size fields allow only this much */
1242 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1243 break;
1244 }
1245 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1246 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1247 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1248 /* GFX6-8 only support single channel min/max filter. */
1249 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1250 properties->filterMinmaxSingleComponentFormats = true;
1251 break;
1252 }
1253 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1254 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1255 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1256
1257 /* Shader engines. */
1258 properties->shaderEngineCount =
1259 pdevice->rad_info.max_se;
1260 properties->shaderArraysPerEngineCount =
1261 pdevice->rad_info.max_sh_per_se;
1262 properties->computeUnitsPerShaderArray =
1263 pdevice->rad_info.num_good_cu_per_sh;
1264 properties->simdPerComputeUnit = 4;
1265 properties->wavefrontsPerSimd =
1266 pdevice->rad_info.family == CHIP_TONGA ||
1267 pdevice->rad_info.family == CHIP_ICELAND ||
1268 pdevice->rad_info.family == CHIP_POLARIS10 ||
1269 pdevice->rad_info.family == CHIP_POLARIS11 ||
1270 pdevice->rad_info.family == CHIP_POLARIS12 ||
1271 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1272 properties->wavefrontSize = 64;
1273
1274 /* SGPR. */
1275 properties->sgprsPerSimd =
1276 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1277 properties->minSgprAllocation =
1278 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1279 properties->maxSgprAllocation =
1280 pdevice->rad_info.family == CHIP_TONGA ||
1281 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1282 properties->sgprAllocationGranularity =
1283 pdevice->rad_info.chip_class >= GFX8 ? 16 : 8;
1284
1285 /* VGPR. */
1286 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1287 properties->minVgprAllocation = 4;
1288 properties->maxVgprAllocation = 256;
1289 properties->vgprAllocationGranularity = 4;
1290 break;
1291 }
1292 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1293 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1294 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1295 properties->maxVertexAttribDivisor = UINT32_MAX;
1296 break;
1297 }
1298 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1299 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1300 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1301 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1302 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1303 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1304 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1305 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1306 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1307 properties->robustBufferAccessUpdateAfterBind = false;
1308 properties->quadDivergentImplicitLod = false;
1309
1310 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1311 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1312 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1313 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1314 32 /* sampler, largest when combined with image */ +
1315 64 /* sampled image */ +
1316 64 /* storage image */);
1317 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1318 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1319 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1320 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1321 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1322 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1323 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1324 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1325 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1326 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1327 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1328 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1329 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1330 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1331 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1332 break;
1333 }
1334 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1335 VkPhysicalDeviceProtectedMemoryProperties *properties =
1336 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1337 properties->protectedNoFault = false;
1338 break;
1339 }
1340 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1341 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1342 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1343 properties->primitiveOverestimationSize = 0;
1344 properties->maxExtraPrimitiveOverestimationSize = 0;
1345 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1346 properties->primitiveUnderestimation = VK_FALSE;
1347 properties->conservativePointAndLineRasterization = VK_FALSE;
1348 properties->degenerateTrianglesRasterized = VK_FALSE;
1349 properties->degenerateLinesRasterized = VK_FALSE;
1350 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1351 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1352 break;
1353 }
1354 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1355 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1356 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1357 properties->pciDomain = pdevice->bus_info.domain;
1358 properties->pciBus = pdevice->bus_info.bus;
1359 properties->pciDevice = pdevice->bus_info.dev;
1360 properties->pciFunction = pdevice->bus_info.func;
1361 break;
1362 }
1363 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1364 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1365 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1366
1367 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1368 snprintf(driver_props->driverName, VK_MAX_DRIVER_NAME_SIZE_KHR, "radv");
1369 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1370 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1371 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1372
1373 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1374 .major = 1,
1375 .minor = 1,
1376 .subminor = 2,
1377 .patch = 0,
1378 };
1379 break;
1380 }
1381 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1382 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1383 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1384 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1385 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1386 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1387 properties->maxTransformFeedbackStreamDataSize = 512;
1388 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1389 properties->maxTransformFeedbackBufferDataStride = 512;
1390 properties->transformFeedbackQueries = true;
1391 properties->transformFeedbackStreamsLinesTriangles = true;
1392 properties->transformFeedbackRasterizationStreamSelect = false;
1393 properties->transformFeedbackDraw = true;
1394 break;
1395 }
1396 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1397 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1398 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1399
1400 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1401 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1402 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1403 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1404 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1405 break;
1406 }
1407 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLE_LOCATIONS_PROPERTIES_EXT: {
1408 VkPhysicalDeviceSampleLocationsPropertiesEXT *properties =
1409 (VkPhysicalDeviceSampleLocationsPropertiesEXT *)ext;
1410 properties->sampleLocationSampleCounts = VK_SAMPLE_COUNT_2_BIT |
1411 VK_SAMPLE_COUNT_4_BIT |
1412 VK_SAMPLE_COUNT_8_BIT;
1413 properties->maxSampleLocationGridSize = (VkExtent2D){ 2 , 2 };
1414 properties->sampleLocationCoordinateRange[0] = 0.0f;
1415 properties->sampleLocationCoordinateRange[1] = 0.9375f;
1416 properties->sampleLocationSubPixelBits = 4;
1417 properties->variableSampleLocations = VK_FALSE;
1418 break;
1419 }
1420 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_STENCIL_RESOLVE_PROPERTIES_KHR: {
1421 VkPhysicalDeviceDepthStencilResolvePropertiesKHR *properties =
1422 (VkPhysicalDeviceDepthStencilResolvePropertiesKHR *)ext;
1423
1424 /* We support all of the depth resolve modes */
1425 properties->supportedDepthResolveModes =
1426 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1427 VK_RESOLVE_MODE_AVERAGE_BIT_KHR |
1428 VK_RESOLVE_MODE_MIN_BIT_KHR |
1429 VK_RESOLVE_MODE_MAX_BIT_KHR;
1430
1431 /* Average doesn't make sense for stencil so we don't support that */
1432 properties->supportedStencilResolveModes =
1433 VK_RESOLVE_MODE_SAMPLE_ZERO_BIT_KHR |
1434 VK_RESOLVE_MODE_MIN_BIT_KHR |
1435 VK_RESOLVE_MODE_MAX_BIT_KHR;
1436
1437 properties->independentResolveNone = VK_TRUE;
1438 properties->independentResolve = VK_TRUE;
1439 break;
1440 }
1441 default:
1442 break;
1443 }
1444 }
1445 }
1446
1447 static void radv_get_physical_device_queue_family_properties(
1448 struct radv_physical_device* pdevice,
1449 uint32_t* pCount,
1450 VkQueueFamilyProperties** pQueueFamilyProperties)
1451 {
1452 int num_queue_families = 1;
1453 int idx;
1454 if (pdevice->rad_info.num_compute_rings > 0 &&
1455 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1456 num_queue_families++;
1457
1458 if (pQueueFamilyProperties == NULL) {
1459 *pCount = num_queue_families;
1460 return;
1461 }
1462
1463 if (!*pCount)
1464 return;
1465
1466 idx = 0;
1467 if (*pCount >= 1) {
1468 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1469 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1470 VK_QUEUE_COMPUTE_BIT |
1471 VK_QUEUE_TRANSFER_BIT |
1472 VK_QUEUE_SPARSE_BINDING_BIT,
1473 .queueCount = 1,
1474 .timestampValidBits = 64,
1475 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1476 };
1477 idx++;
1478 }
1479
1480 if (pdevice->rad_info.num_compute_rings > 0 &&
1481 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1482 if (*pCount > idx) {
1483 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1484 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1485 VK_QUEUE_TRANSFER_BIT |
1486 VK_QUEUE_SPARSE_BINDING_BIT,
1487 .queueCount = pdevice->rad_info.num_compute_rings,
1488 .timestampValidBits = 64,
1489 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1490 };
1491 idx++;
1492 }
1493 }
1494 *pCount = idx;
1495 }
1496
1497 void radv_GetPhysicalDeviceQueueFamilyProperties(
1498 VkPhysicalDevice physicalDevice,
1499 uint32_t* pCount,
1500 VkQueueFamilyProperties* pQueueFamilyProperties)
1501 {
1502 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1503 if (!pQueueFamilyProperties) {
1504 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1505 return;
1506 }
1507 VkQueueFamilyProperties *properties[] = {
1508 pQueueFamilyProperties + 0,
1509 pQueueFamilyProperties + 1,
1510 pQueueFamilyProperties + 2,
1511 };
1512 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1513 assert(*pCount <= 3);
1514 }
1515
1516 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1517 VkPhysicalDevice physicalDevice,
1518 uint32_t* pCount,
1519 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1520 {
1521 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1522 if (!pQueueFamilyProperties) {
1523 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1524 return;
1525 }
1526 VkQueueFamilyProperties *properties[] = {
1527 &pQueueFamilyProperties[0].queueFamilyProperties,
1528 &pQueueFamilyProperties[1].queueFamilyProperties,
1529 &pQueueFamilyProperties[2].queueFamilyProperties,
1530 };
1531 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1532 assert(*pCount <= 3);
1533 }
1534
1535 void radv_GetPhysicalDeviceMemoryProperties(
1536 VkPhysicalDevice physicalDevice,
1537 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1538 {
1539 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1540
1541 *pMemoryProperties = physical_device->memory_properties;
1542 }
1543
1544 static void
1545 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1546 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1547 {
1548 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1549 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1550 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1551 uint64_t vram_size = radv_get_vram_size(device);
1552 uint64_t gtt_size = device->rad_info.gart_size;
1553 uint64_t heap_budget, heap_usage;
1554
1555 /* For all memory heaps, the computation of budget is as follow:
1556 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1557 *
1558 * The Vulkan spec 1.1.97 says that the budget should include any
1559 * currently allocated device memory.
1560 *
1561 * Note that the application heap usages are not really accurate (eg.
1562 * in presence of shared buffers).
1563 */
1564 for (int i = 0; i < device->memory_properties.memoryTypeCount; i++) {
1565 uint32_t heap_index = device->memory_properties.memoryTypes[i].heapIndex;
1566
1567 switch (device->mem_type_indices[i]) {
1568 case RADV_MEM_TYPE_VRAM:
1569 heap_usage = device->ws->query_value(device->ws,
1570 RADEON_ALLOCATED_VRAM);
1571
1572 heap_budget = vram_size -
1573 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1574 heap_usage;
1575
1576 memoryBudget->heapBudget[heap_index] = heap_budget;
1577 memoryBudget->heapUsage[heap_index] = heap_usage;
1578 break;
1579 case RADV_MEM_TYPE_VRAM_CPU_ACCESS:
1580 heap_usage = device->ws->query_value(device->ws,
1581 RADEON_ALLOCATED_VRAM_VIS);
1582
1583 heap_budget = visible_vram_size -
1584 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1585 heap_usage;
1586
1587 memoryBudget->heapBudget[heap_index] = heap_budget;
1588 memoryBudget->heapUsage[heap_index] = heap_usage;
1589 break;
1590 case RADV_MEM_TYPE_GTT_WRITE_COMBINE:
1591 heap_usage = device->ws->query_value(device->ws,
1592 RADEON_ALLOCATED_GTT);
1593
1594 heap_budget = gtt_size -
1595 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1596 heap_usage;
1597
1598 memoryBudget->heapBudget[heap_index] = heap_budget;
1599 memoryBudget->heapUsage[heap_index] = heap_usage;
1600 break;
1601 default:
1602 break;
1603 }
1604 }
1605
1606 /* The heapBudget and heapUsage values must be zero for array elements
1607 * greater than or equal to
1608 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1609 */
1610 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1611 memoryBudget->heapBudget[i] = 0;
1612 memoryBudget->heapUsage[i] = 0;
1613 }
1614 }
1615
1616 void radv_GetPhysicalDeviceMemoryProperties2(
1617 VkPhysicalDevice physicalDevice,
1618 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1619 {
1620 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1621 &pMemoryProperties->memoryProperties);
1622
1623 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1624 vk_find_struct(pMemoryProperties->pNext,
1625 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1626 if (memory_budget)
1627 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1628 }
1629
1630 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1631 VkDevice _device,
1632 VkExternalMemoryHandleTypeFlagBits handleType,
1633 const void *pHostPointer,
1634 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1635 {
1636 RADV_FROM_HANDLE(radv_device, device, _device);
1637
1638 switch (handleType)
1639 {
1640 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1641 const struct radv_physical_device *physical_device = device->physical_device;
1642 uint32_t memoryTypeBits = 0;
1643 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1644 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1645 memoryTypeBits = (1 << i);
1646 break;
1647 }
1648 }
1649 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1650 return VK_SUCCESS;
1651 }
1652 default:
1653 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1654 }
1655 }
1656
1657 static enum radeon_ctx_priority
1658 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1659 {
1660 /* Default to MEDIUM when a specific global priority isn't requested */
1661 if (!pObj)
1662 return RADEON_CTX_PRIORITY_MEDIUM;
1663
1664 switch(pObj->globalPriority) {
1665 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1666 return RADEON_CTX_PRIORITY_REALTIME;
1667 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1668 return RADEON_CTX_PRIORITY_HIGH;
1669 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1670 return RADEON_CTX_PRIORITY_MEDIUM;
1671 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1672 return RADEON_CTX_PRIORITY_LOW;
1673 default:
1674 unreachable("Illegal global priority value");
1675 return RADEON_CTX_PRIORITY_INVALID;
1676 }
1677 }
1678
1679 static int
1680 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1681 uint32_t queue_family_index, int idx,
1682 VkDeviceQueueCreateFlags flags,
1683 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1684 {
1685 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1686 queue->device = device;
1687 queue->queue_family_index = queue_family_index;
1688 queue->queue_idx = idx;
1689 queue->priority = radv_get_queue_global_priority(global_priority);
1690 queue->flags = flags;
1691
1692 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1693 if (!queue->hw_ctx)
1694 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1695
1696 return VK_SUCCESS;
1697 }
1698
1699 static void
1700 radv_queue_finish(struct radv_queue *queue)
1701 {
1702 if (queue->hw_ctx)
1703 queue->device->ws->ctx_destroy(queue->hw_ctx);
1704
1705 if (queue->initial_full_flush_preamble_cs)
1706 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1707 if (queue->initial_preamble_cs)
1708 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1709 if (queue->continue_preamble_cs)
1710 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1711 if (queue->descriptor_bo)
1712 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1713 if (queue->scratch_bo)
1714 queue->device->ws->buffer_destroy(queue->scratch_bo);
1715 if (queue->esgs_ring_bo)
1716 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1717 if (queue->gsvs_ring_bo)
1718 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1719 if (queue->tess_rings_bo)
1720 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1721 if (queue->compute_scratch_bo)
1722 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1723 }
1724
1725 static void
1726 radv_bo_list_init(struct radv_bo_list *bo_list)
1727 {
1728 pthread_mutex_init(&bo_list->mutex, NULL);
1729 bo_list->list.count = bo_list->capacity = 0;
1730 bo_list->list.bos = NULL;
1731 }
1732
1733 static void
1734 radv_bo_list_finish(struct radv_bo_list *bo_list)
1735 {
1736 free(bo_list->list.bos);
1737 pthread_mutex_destroy(&bo_list->mutex);
1738 }
1739
1740 static VkResult radv_bo_list_add(struct radv_device *device,
1741 struct radeon_winsys_bo *bo)
1742 {
1743 struct radv_bo_list *bo_list = &device->bo_list;
1744
1745 if (bo->is_local)
1746 return VK_SUCCESS;
1747
1748 if (unlikely(!device->use_global_bo_list))
1749 return VK_SUCCESS;
1750
1751 pthread_mutex_lock(&bo_list->mutex);
1752 if (bo_list->list.count == bo_list->capacity) {
1753 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1754 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1755
1756 if (!data) {
1757 pthread_mutex_unlock(&bo_list->mutex);
1758 return VK_ERROR_OUT_OF_HOST_MEMORY;
1759 }
1760
1761 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1762 bo_list->capacity = capacity;
1763 }
1764
1765 bo_list->list.bos[bo_list->list.count++] = bo;
1766 pthread_mutex_unlock(&bo_list->mutex);
1767 return VK_SUCCESS;
1768 }
1769
1770 static void radv_bo_list_remove(struct radv_device *device,
1771 struct radeon_winsys_bo *bo)
1772 {
1773 struct radv_bo_list *bo_list = &device->bo_list;
1774
1775 if (bo->is_local)
1776 return;
1777
1778 if (unlikely(!device->use_global_bo_list))
1779 return;
1780
1781 pthread_mutex_lock(&bo_list->mutex);
1782 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1783 if (bo_list->list.bos[i] == bo) {
1784 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1785 --bo_list->list.count;
1786 break;
1787 }
1788 }
1789 pthread_mutex_unlock(&bo_list->mutex);
1790 }
1791
1792 static void
1793 radv_device_init_gs_info(struct radv_device *device)
1794 {
1795 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1796 device->physical_device->rad_info.family);
1797 }
1798
1799 static int radv_get_device_extension_index(const char *name)
1800 {
1801 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1802 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1803 return i;
1804 }
1805 return -1;
1806 }
1807
1808 static int
1809 radv_get_int_debug_option(const char *name, int default_value)
1810 {
1811 const char *str;
1812 int result;
1813
1814 str = getenv(name);
1815 if (!str) {
1816 result = default_value;
1817 } else {
1818 char *endptr;
1819
1820 result = strtol(str, &endptr, 0);
1821 if (str == endptr) {
1822 /* No digits founs. */
1823 result = default_value;
1824 }
1825 }
1826
1827 return result;
1828 }
1829
1830 VkResult radv_CreateDevice(
1831 VkPhysicalDevice physicalDevice,
1832 const VkDeviceCreateInfo* pCreateInfo,
1833 const VkAllocationCallbacks* pAllocator,
1834 VkDevice* pDevice)
1835 {
1836 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1837 VkResult result;
1838 struct radv_device *device;
1839
1840 bool keep_shader_info = false;
1841
1842 /* Check enabled features */
1843 if (pCreateInfo->pEnabledFeatures) {
1844 VkPhysicalDeviceFeatures supported_features;
1845 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1846 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1847 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1848 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1849 for (uint32_t i = 0; i < num_features; i++) {
1850 if (enabled_feature[i] && !supported_feature[i])
1851 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1852 }
1853 }
1854
1855 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1856 sizeof(*device), 8,
1857 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1858 if (!device)
1859 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1860
1861 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1862 device->instance = physical_device->instance;
1863 device->physical_device = physical_device;
1864
1865 device->ws = physical_device->ws;
1866 if (pAllocator)
1867 device->alloc = *pAllocator;
1868 else
1869 device->alloc = physical_device->instance->alloc;
1870
1871 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1872 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1873 int index = radv_get_device_extension_index(ext_name);
1874 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1875 vk_free(&device->alloc, device);
1876 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1877 }
1878
1879 device->enabled_extensions.extensions[index] = true;
1880 }
1881
1882 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1883
1884 /* With update after bind we can't attach bo's to the command buffer
1885 * from the descriptor set anymore, so we have to use a global BO list.
1886 */
1887 device->use_global_bo_list =
1888 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1889 device->enabled_extensions.EXT_descriptor_indexing ||
1890 device->enabled_extensions.EXT_buffer_device_address;
1891
1892 mtx_init(&device->shader_slab_mutex, mtx_plain);
1893 list_inithead(&device->shader_slabs);
1894
1895 radv_bo_list_init(&device->bo_list);
1896
1897 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1898 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1899 uint32_t qfi = queue_create->queueFamilyIndex;
1900 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1901 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1902
1903 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1904
1905 device->queues[qfi] = vk_alloc(&device->alloc,
1906 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1907 if (!device->queues[qfi]) {
1908 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1909 goto fail;
1910 }
1911
1912 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1913
1914 device->queue_count[qfi] = queue_create->queueCount;
1915
1916 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1917 result = radv_queue_init(device, &device->queues[qfi][q],
1918 qfi, q, queue_create->flags,
1919 global_priority);
1920 if (result != VK_SUCCESS)
1921 goto fail;
1922 }
1923 }
1924
1925 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1926 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1927
1928 /* Disabled and not implemented for now. */
1929 device->dfsm_allowed = device->pbb_allowed &&
1930 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1931 device->physical_device->rad_info.family == CHIP_RAVEN2);
1932
1933 #ifdef ANDROID
1934 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1935 #endif
1936
1937 /* The maximum number of scratch waves. Scratch space isn't divided
1938 * evenly between CUs. The number is only a function of the number of CUs.
1939 * We can decrease the constant to decrease the scratch buffer size.
1940 *
1941 * sctx->scratch_waves must be >= the maximum possible size of
1942 * 1 threadgroup, so that the hw doesn't hang from being unable
1943 * to start any.
1944 *
1945 * The recommended value is 4 per CU at most. Higher numbers don't
1946 * bring much benefit, but they still occupy chip resources (think
1947 * async compute). I've seen ~2% performance difference between 4 and 32.
1948 */
1949 uint32_t max_threads_per_block = 2048;
1950 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1951 max_threads_per_block / 64);
1952
1953 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1) |
1954 S_00B800_CS_W32_EN(device->physical_device->cs_wave_size == 32);
1955
1956 if (device->physical_device->rad_info.chip_class >= GFX7) {
1957 /* If the KMD allows it (there is a KMD hw register for it),
1958 * allow launching waves out-of-order.
1959 */
1960 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1961 }
1962
1963 radv_device_init_gs_info(device);
1964
1965 device->tess_offchip_block_dw_size =
1966 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1967 device->has_distributed_tess =
1968 device->physical_device->rad_info.chip_class >= GFX8 &&
1969 device->physical_device->rad_info.max_se >= 2;
1970
1971 if (getenv("RADV_TRACE_FILE")) {
1972 const char *filename = getenv("RADV_TRACE_FILE");
1973
1974 keep_shader_info = true;
1975
1976 if (!radv_init_trace(device))
1977 goto fail;
1978
1979 fprintf(stderr, "*****************************************************************************\n");
1980 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1981 fprintf(stderr, "*****************************************************************************\n");
1982
1983 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1984 radv_dump_enabled_options(device, stderr);
1985 }
1986
1987 device->keep_shader_info = keep_shader_info;
1988
1989 result = radv_device_init_meta(device);
1990 if (result != VK_SUCCESS)
1991 goto fail;
1992
1993 radv_device_init_msaa(device);
1994
1995 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1996 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1997 switch (family) {
1998 case RADV_QUEUE_GENERAL:
1999 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
2000 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
2001 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
2002 break;
2003 case RADV_QUEUE_COMPUTE:
2004 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
2005 radeon_emit(device->empty_cs[family], 0);
2006 break;
2007 }
2008 device->ws->cs_finalize(device->empty_cs[family]);
2009 }
2010
2011 if (device->physical_device->rad_info.chip_class >= GFX7)
2012 cik_create_gfx_config(device);
2013
2014 VkPipelineCacheCreateInfo ci;
2015 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
2016 ci.pNext = NULL;
2017 ci.flags = 0;
2018 ci.pInitialData = NULL;
2019 ci.initialDataSize = 0;
2020 VkPipelineCache pc;
2021 result = radv_CreatePipelineCache(radv_device_to_handle(device),
2022 &ci, NULL, &pc);
2023 if (result != VK_SUCCESS)
2024 goto fail_meta;
2025
2026 device->mem_cache = radv_pipeline_cache_from_handle(pc);
2027
2028 device->force_aniso =
2029 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
2030 if (device->force_aniso >= 0) {
2031 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
2032 1 << util_logbase2(device->force_aniso));
2033 }
2034
2035 *pDevice = radv_device_to_handle(device);
2036 return VK_SUCCESS;
2037
2038 fail_meta:
2039 radv_device_finish_meta(device);
2040 fail:
2041 radv_bo_list_finish(&device->bo_list);
2042
2043 if (device->trace_bo)
2044 device->ws->buffer_destroy(device->trace_bo);
2045
2046 if (device->gfx_init)
2047 device->ws->buffer_destroy(device->gfx_init);
2048
2049 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2050 for (unsigned q = 0; q < device->queue_count[i]; q++)
2051 radv_queue_finish(&device->queues[i][q]);
2052 if (device->queue_count[i])
2053 vk_free(&device->alloc, device->queues[i]);
2054 }
2055
2056 vk_free(&device->alloc, device);
2057 return result;
2058 }
2059
2060 void radv_DestroyDevice(
2061 VkDevice _device,
2062 const VkAllocationCallbacks* pAllocator)
2063 {
2064 RADV_FROM_HANDLE(radv_device, device, _device);
2065
2066 if (!device)
2067 return;
2068
2069 if (device->trace_bo)
2070 device->ws->buffer_destroy(device->trace_bo);
2071
2072 if (device->gfx_init)
2073 device->ws->buffer_destroy(device->gfx_init);
2074
2075 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2076 for (unsigned q = 0; q < device->queue_count[i]; q++)
2077 radv_queue_finish(&device->queues[i][q]);
2078 if (device->queue_count[i])
2079 vk_free(&device->alloc, device->queues[i]);
2080 if (device->empty_cs[i])
2081 device->ws->cs_destroy(device->empty_cs[i]);
2082 }
2083 radv_device_finish_meta(device);
2084
2085 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
2086 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
2087
2088 radv_destroy_shader_slabs(device);
2089
2090 radv_bo_list_finish(&device->bo_list);
2091 vk_free(&device->alloc, device);
2092 }
2093
2094 VkResult radv_EnumerateInstanceLayerProperties(
2095 uint32_t* pPropertyCount,
2096 VkLayerProperties* pProperties)
2097 {
2098 if (pProperties == NULL) {
2099 *pPropertyCount = 0;
2100 return VK_SUCCESS;
2101 }
2102
2103 /* None supported at this time */
2104 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2105 }
2106
2107 VkResult radv_EnumerateDeviceLayerProperties(
2108 VkPhysicalDevice physicalDevice,
2109 uint32_t* pPropertyCount,
2110 VkLayerProperties* pProperties)
2111 {
2112 if (pProperties == NULL) {
2113 *pPropertyCount = 0;
2114 return VK_SUCCESS;
2115 }
2116
2117 /* None supported at this time */
2118 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2119 }
2120
2121 void radv_GetDeviceQueue2(
2122 VkDevice _device,
2123 const VkDeviceQueueInfo2* pQueueInfo,
2124 VkQueue* pQueue)
2125 {
2126 RADV_FROM_HANDLE(radv_device, device, _device);
2127 struct radv_queue *queue;
2128
2129 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2130 if (pQueueInfo->flags != queue->flags) {
2131 /* From the Vulkan 1.1.70 spec:
2132 *
2133 * "The queue returned by vkGetDeviceQueue2 must have the same
2134 * flags value from this structure as that used at device
2135 * creation time in a VkDeviceQueueCreateInfo instance. If no
2136 * matching flags were specified at device creation time then
2137 * pQueue will return VK_NULL_HANDLE."
2138 */
2139 *pQueue = VK_NULL_HANDLE;
2140 return;
2141 }
2142
2143 *pQueue = radv_queue_to_handle(queue);
2144 }
2145
2146 void radv_GetDeviceQueue(
2147 VkDevice _device,
2148 uint32_t queueFamilyIndex,
2149 uint32_t queueIndex,
2150 VkQueue* pQueue)
2151 {
2152 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2153 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2154 .queueFamilyIndex = queueFamilyIndex,
2155 .queueIndex = queueIndex
2156 };
2157
2158 radv_GetDeviceQueue2(_device, &info, pQueue);
2159 }
2160
2161 static void
2162 fill_geom_tess_rings(struct radv_queue *queue,
2163 uint32_t *map,
2164 bool add_sample_positions,
2165 uint32_t esgs_ring_size,
2166 struct radeon_winsys_bo *esgs_ring_bo,
2167 uint32_t gsvs_ring_size,
2168 struct radeon_winsys_bo *gsvs_ring_bo,
2169 uint32_t tess_factor_ring_size,
2170 uint32_t tess_offchip_ring_offset,
2171 uint32_t tess_offchip_ring_size,
2172 struct radeon_winsys_bo *tess_rings_bo)
2173 {
2174 uint32_t *desc = &map[4];
2175
2176 if (esgs_ring_bo) {
2177 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2178
2179 /* stride 0, num records - size, add tid, swizzle, elsize4,
2180 index stride 64 */
2181 desc[0] = esgs_va;
2182 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2183 S_008F04_SWIZZLE_ENABLE(true);
2184 desc[2] = esgs_ring_size;
2185 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2186 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2187 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2188 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2189 S_008F0C_INDEX_STRIDE(3) |
2190 S_008F0C_ADD_TID_ENABLE(1);
2191
2192 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2193 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2194 S_008F0C_OOB_SELECT(2) |
2195 S_008F0C_RESOURCE_LEVEL(1);
2196 } else {
2197 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2198 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2199 S_008F0C_ELEMENT_SIZE(1);
2200 }
2201
2202 /* GS entry for ES->GS ring */
2203 /* stride 0, num records - size, elsize0,
2204 index stride 0 */
2205 desc[4] = esgs_va;
2206 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32);
2207 desc[6] = esgs_ring_size;
2208 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2209 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2210 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2211 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2212
2213 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2214 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2215 S_008F0C_OOB_SELECT(2) |
2216 S_008F0C_RESOURCE_LEVEL(1);
2217 } else {
2218 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2219 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2220 }
2221 }
2222
2223 desc += 8;
2224
2225 if (gsvs_ring_bo) {
2226 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2227
2228 /* VS entry for GS->VS ring */
2229 /* stride 0, num records - size, elsize0,
2230 index stride 0 */
2231 desc[0] = gsvs_va;
2232 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32);
2233 desc[2] = gsvs_ring_size;
2234 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2235 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2236 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2237 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2238
2239 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2240 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2241 S_008F0C_OOB_SELECT(2) |
2242 S_008F0C_RESOURCE_LEVEL(1);
2243 } else {
2244 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2245 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2246 }
2247
2248 /* stride gsvs_itemsize, num records 64
2249 elsize 4, index stride 16 */
2250 /* shader will patch stride and desc[2] */
2251 desc[4] = gsvs_va;
2252 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32) |
2253 S_008F04_SWIZZLE_ENABLE(1);
2254 desc[6] = 0;
2255 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2256 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2257 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2258 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2259 S_008F0C_INDEX_STRIDE(1) |
2260 S_008F0C_ADD_TID_ENABLE(true);
2261
2262 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2263 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2264 S_008F0C_OOB_SELECT(2) |
2265 S_008F0C_RESOURCE_LEVEL(1);
2266 } else {
2267 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2268 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2269 S_008F0C_ELEMENT_SIZE(1);
2270 }
2271
2272 }
2273
2274 desc += 8;
2275
2276 if (tess_rings_bo) {
2277 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2278 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2279
2280 desc[0] = tess_va;
2281 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32);
2282 desc[2] = tess_factor_ring_size;
2283 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2284 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2285 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2286 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2287
2288 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2289 desc[3] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2290 S_008F0C_OOB_SELECT(3) |
2291 S_008F0C_RESOURCE_LEVEL(1);
2292 } else {
2293 desc[3] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2294 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2295 }
2296
2297 desc[4] = tess_offchip_va;
2298 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32);
2299 desc[6] = tess_offchip_ring_size;
2300 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2301 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2302 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2303 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
2304
2305 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2306 desc[7] |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
2307 S_008F0C_OOB_SELECT(3) |
2308 S_008F0C_RESOURCE_LEVEL(1);
2309 } else {
2310 desc[7] |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2311 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
2312 }
2313 }
2314
2315 desc += 8;
2316
2317 if (add_sample_positions) {
2318 /* add sample positions after all rings */
2319 memcpy(desc, queue->device->sample_locations_1x, 8);
2320 desc += 2;
2321 memcpy(desc, queue->device->sample_locations_2x, 16);
2322 desc += 4;
2323 memcpy(desc, queue->device->sample_locations_4x, 32);
2324 desc += 8;
2325 memcpy(desc, queue->device->sample_locations_8x, 64);
2326 }
2327 }
2328
2329 static unsigned
2330 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2331 {
2332 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= GFX7 &&
2333 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2334 device->physical_device->rad_info.family != CHIP_STONEY;
2335 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2336 unsigned max_offchip_buffers;
2337 unsigned offchip_granularity;
2338 unsigned hs_offchip_param;
2339
2340 /*
2341 * Per RadeonSI:
2342 * This must be one less than the maximum number due to a hw limitation.
2343 * Various hardware bugs need thGFX7
2344 *
2345 * Per AMDVLK:
2346 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2347 * Gfx7 should limit max_offchip_buffers to 508
2348 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2349 *
2350 * Follow AMDVLK here.
2351 */
2352 if (device->physical_device->rad_info.chip_class >= GFX10) {
2353 max_offchip_buffers_per_se = 256;
2354 } else if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2355 device->physical_device->rad_info.chip_class == GFX7 ||
2356 device->physical_device->rad_info.chip_class == GFX6)
2357 --max_offchip_buffers_per_se;
2358
2359 max_offchip_buffers = max_offchip_buffers_per_se *
2360 device->physical_device->rad_info.max_se;
2361
2362 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2363 * around by setting 4K granularity.
2364 */
2365 if (device->tess_offchip_block_dw_size == 4096) {
2366 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2367 offchip_granularity = V_03093C_X_4K_DWORDS;
2368 } else {
2369 assert(device->tess_offchip_block_dw_size == 8192);
2370 offchip_granularity = V_03093C_X_8K_DWORDS;
2371 }
2372
2373 switch (device->physical_device->rad_info.chip_class) {
2374 case GFX6:
2375 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2376 break;
2377 case GFX7:
2378 case GFX8:
2379 case GFX9:
2380 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2381 break;
2382 case GFX10:
2383 break;
2384 default:
2385 break;
2386 }
2387
2388 *max_offchip_buffers_p = max_offchip_buffers;
2389 if (device->physical_device->rad_info.chip_class >= GFX7) {
2390 if (device->physical_device->rad_info.chip_class >= GFX8)
2391 --max_offchip_buffers;
2392 hs_offchip_param =
2393 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2394 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2395 } else {
2396 hs_offchip_param =
2397 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2398 }
2399 return hs_offchip_param;
2400 }
2401
2402 static void
2403 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2404 struct radeon_winsys_bo *esgs_ring_bo,
2405 uint32_t esgs_ring_size,
2406 struct radeon_winsys_bo *gsvs_ring_bo,
2407 uint32_t gsvs_ring_size)
2408 {
2409 if (!esgs_ring_bo && !gsvs_ring_bo)
2410 return;
2411
2412 if (esgs_ring_bo)
2413 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2414
2415 if (gsvs_ring_bo)
2416 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2417
2418 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2419 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2420 radeon_emit(cs, esgs_ring_size >> 8);
2421 radeon_emit(cs, gsvs_ring_size >> 8);
2422 } else {
2423 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2424 radeon_emit(cs, esgs_ring_size >> 8);
2425 radeon_emit(cs, gsvs_ring_size >> 8);
2426 }
2427 }
2428
2429 static void
2430 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2431 unsigned hs_offchip_param, unsigned tf_ring_size,
2432 struct radeon_winsys_bo *tess_rings_bo)
2433 {
2434 uint64_t tf_va;
2435
2436 if (!tess_rings_bo)
2437 return;
2438
2439 tf_va = radv_buffer_get_va(tess_rings_bo);
2440
2441 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2442
2443 if (queue->device->physical_device->rad_info.chip_class >= GFX7) {
2444 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2445 S_030938_SIZE(tf_ring_size / 4));
2446 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2447 tf_va >> 8);
2448
2449 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2450 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
2451 S_030984_BASE_HI(tf_va >> 40));
2452 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2453 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2454 S_030944_BASE_HI(tf_va >> 40));
2455 }
2456 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2457 hs_offchip_param);
2458 } else {
2459 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2460 S_008988_SIZE(tf_ring_size / 4));
2461 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2462 tf_va >> 8);
2463 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2464 hs_offchip_param);
2465 }
2466 }
2467
2468 static void
2469 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2470 struct radeon_winsys_bo *compute_scratch_bo)
2471 {
2472 uint64_t scratch_va;
2473
2474 if (!compute_scratch_bo)
2475 return;
2476
2477 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2478
2479 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2480
2481 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2482 radeon_emit(cs, scratch_va);
2483 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2484 S_008F04_SWIZZLE_ENABLE(1));
2485 }
2486
2487 static void
2488 radv_emit_global_shader_pointers(struct radv_queue *queue,
2489 struct radeon_cmdbuf *cs,
2490 struct radeon_winsys_bo *descriptor_bo)
2491 {
2492 uint64_t va;
2493
2494 if (!descriptor_bo)
2495 return;
2496
2497 va = radv_buffer_get_va(descriptor_bo);
2498
2499 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2500
2501 if (queue->device->physical_device->rad_info.chip_class >= GFX10) {
2502 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2503 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2504 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2505 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2506
2507 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2508 radv_emit_shader_pointer(queue->device, cs, regs[i],
2509 va, true);
2510 }
2511 } else if (queue->device->physical_device->rad_info.chip_class == GFX9) {
2512 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2513 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2514 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2515 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2516
2517 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2518 radv_emit_shader_pointer(queue->device, cs, regs[i],
2519 va, true);
2520 }
2521 } else {
2522 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2523 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2524 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2525 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2526 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2527 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2528
2529 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2530 radv_emit_shader_pointer(queue->device, cs, regs[i],
2531 va, true);
2532 }
2533 }
2534 }
2535
2536 static void
2537 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2538 {
2539 struct radv_device *device = queue->device;
2540
2541 if (device->gfx_init) {
2542 uint64_t va = radv_buffer_get_va(device->gfx_init);
2543
2544 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2545 radeon_emit(cs, va);
2546 radeon_emit(cs, va >> 32);
2547 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2548
2549 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2550 } else {
2551 struct radv_physical_device *physical_device = device->physical_device;
2552 si_emit_graphics(physical_device, cs);
2553 }
2554 }
2555
2556 static void
2557 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2558 {
2559 struct radv_physical_device *physical_device = queue->device->physical_device;
2560 si_emit_compute(physical_device, cs);
2561 }
2562
2563 static VkResult
2564 radv_get_preamble_cs(struct radv_queue *queue,
2565 uint32_t scratch_size,
2566 uint32_t compute_scratch_size,
2567 uint32_t esgs_ring_size,
2568 uint32_t gsvs_ring_size,
2569 bool needs_tess_rings,
2570 bool needs_sample_positions,
2571 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2572 struct radeon_cmdbuf **initial_preamble_cs,
2573 struct radeon_cmdbuf **continue_preamble_cs)
2574 {
2575 struct radeon_winsys_bo *scratch_bo = NULL;
2576 struct radeon_winsys_bo *descriptor_bo = NULL;
2577 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2578 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2579 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2580 struct radeon_winsys_bo *tess_rings_bo = NULL;
2581 struct radeon_cmdbuf *dest_cs[3] = {0};
2582 bool add_tess_rings = false, add_sample_positions = false;
2583 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2584 unsigned max_offchip_buffers;
2585 unsigned hs_offchip_param = 0;
2586 unsigned tess_offchip_ring_offset;
2587 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2588 if (!queue->has_tess_rings) {
2589 if (needs_tess_rings)
2590 add_tess_rings = true;
2591 }
2592 if (!queue->has_sample_positions) {
2593 if (needs_sample_positions)
2594 add_sample_positions = true;
2595 }
2596 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2597 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2598 &max_offchip_buffers);
2599 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2600 tess_offchip_ring_size = max_offchip_buffers *
2601 queue->device->tess_offchip_block_dw_size * 4;
2602
2603 if (scratch_size <= queue->scratch_size &&
2604 compute_scratch_size <= queue->compute_scratch_size &&
2605 esgs_ring_size <= queue->esgs_ring_size &&
2606 gsvs_ring_size <= queue->gsvs_ring_size &&
2607 !add_tess_rings && !add_sample_positions &&
2608 queue->initial_preamble_cs) {
2609 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2610 *initial_preamble_cs = queue->initial_preamble_cs;
2611 *continue_preamble_cs = queue->continue_preamble_cs;
2612 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2613 *continue_preamble_cs = NULL;
2614 return VK_SUCCESS;
2615 }
2616
2617 if (scratch_size > queue->scratch_size) {
2618 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2619 scratch_size,
2620 4096,
2621 RADEON_DOMAIN_VRAM,
2622 ring_bo_flags,
2623 RADV_BO_PRIORITY_SCRATCH);
2624 if (!scratch_bo)
2625 goto fail;
2626 } else
2627 scratch_bo = queue->scratch_bo;
2628
2629 if (compute_scratch_size > queue->compute_scratch_size) {
2630 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2631 compute_scratch_size,
2632 4096,
2633 RADEON_DOMAIN_VRAM,
2634 ring_bo_flags,
2635 RADV_BO_PRIORITY_SCRATCH);
2636 if (!compute_scratch_bo)
2637 goto fail;
2638
2639 } else
2640 compute_scratch_bo = queue->compute_scratch_bo;
2641
2642 if (esgs_ring_size > queue->esgs_ring_size) {
2643 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2644 esgs_ring_size,
2645 4096,
2646 RADEON_DOMAIN_VRAM,
2647 ring_bo_flags,
2648 RADV_BO_PRIORITY_SCRATCH);
2649 if (!esgs_ring_bo)
2650 goto fail;
2651 } else {
2652 esgs_ring_bo = queue->esgs_ring_bo;
2653 esgs_ring_size = queue->esgs_ring_size;
2654 }
2655
2656 if (gsvs_ring_size > queue->gsvs_ring_size) {
2657 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2658 gsvs_ring_size,
2659 4096,
2660 RADEON_DOMAIN_VRAM,
2661 ring_bo_flags,
2662 RADV_BO_PRIORITY_SCRATCH);
2663 if (!gsvs_ring_bo)
2664 goto fail;
2665 } else {
2666 gsvs_ring_bo = queue->gsvs_ring_bo;
2667 gsvs_ring_size = queue->gsvs_ring_size;
2668 }
2669
2670 if (add_tess_rings) {
2671 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2672 tess_offchip_ring_offset + tess_offchip_ring_size,
2673 256,
2674 RADEON_DOMAIN_VRAM,
2675 ring_bo_flags,
2676 RADV_BO_PRIORITY_SCRATCH);
2677 if (!tess_rings_bo)
2678 goto fail;
2679 } else {
2680 tess_rings_bo = queue->tess_rings_bo;
2681 }
2682
2683 if (scratch_bo != queue->scratch_bo ||
2684 esgs_ring_bo != queue->esgs_ring_bo ||
2685 gsvs_ring_bo != queue->gsvs_ring_bo ||
2686 tess_rings_bo != queue->tess_rings_bo ||
2687 add_sample_positions) {
2688 uint32_t size = 0;
2689 if (gsvs_ring_bo || esgs_ring_bo ||
2690 tess_rings_bo || add_sample_positions) {
2691 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2692 if (add_sample_positions)
2693 size += 128; /* 64+32+16+8 = 120 bytes */
2694 }
2695 else if (scratch_bo)
2696 size = 8; /* 2 dword */
2697
2698 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2699 size,
2700 4096,
2701 RADEON_DOMAIN_VRAM,
2702 RADEON_FLAG_CPU_ACCESS |
2703 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2704 RADEON_FLAG_READ_ONLY,
2705 RADV_BO_PRIORITY_DESCRIPTOR);
2706 if (!descriptor_bo)
2707 goto fail;
2708 } else
2709 descriptor_bo = queue->descriptor_bo;
2710
2711 if (descriptor_bo != queue->descriptor_bo) {
2712 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2713
2714 if (scratch_bo) {
2715 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2716 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2717 S_008F04_SWIZZLE_ENABLE(1);
2718 map[0] = scratch_va;
2719 map[1] = rsrc1;
2720 }
2721
2722 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2723 fill_geom_tess_rings(queue, map, add_sample_positions,
2724 esgs_ring_size, esgs_ring_bo,
2725 gsvs_ring_size, gsvs_ring_bo,
2726 tess_factor_ring_size,
2727 tess_offchip_ring_offset,
2728 tess_offchip_ring_size,
2729 tess_rings_bo);
2730
2731 queue->device->ws->buffer_unmap(descriptor_bo);
2732 }
2733
2734 for(int i = 0; i < 3; ++i) {
2735 struct radeon_cmdbuf *cs = NULL;
2736 cs = queue->device->ws->cs_create(queue->device->ws,
2737 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2738 if (!cs)
2739 goto fail;
2740
2741 dest_cs[i] = cs;
2742
2743 if (scratch_bo)
2744 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2745
2746 /* Emit initial configuration. */
2747 switch (queue->queue_family_index) {
2748 case RADV_QUEUE_GENERAL:
2749 radv_init_graphics_state(cs, queue);
2750 break;
2751 case RADV_QUEUE_COMPUTE:
2752 radv_init_compute_state(cs, queue);
2753 break;
2754 case RADV_QUEUE_TRANSFER:
2755 break;
2756 }
2757
2758 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2759 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2760 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2761
2762 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2763 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2764 }
2765
2766 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2767 gsvs_ring_bo, gsvs_ring_size);
2768 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2769 tess_factor_ring_size, tess_rings_bo);
2770 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2771 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2772
2773 if (i == 0) {
2774 si_cs_emit_cache_flush(cs,
2775 queue->device->physical_device->rad_info.chip_class,
2776 NULL, 0,
2777 queue->queue_family_index == RING_COMPUTE &&
2778 queue->device->physical_device->rad_info.chip_class >= GFX7,
2779 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2780 RADV_CMD_FLAG_INV_ICACHE |
2781 RADV_CMD_FLAG_INV_SCACHE |
2782 RADV_CMD_FLAG_INV_VCACHE |
2783 RADV_CMD_FLAG_INV_L2 |
2784 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2785 } else if (i == 1) {
2786 si_cs_emit_cache_flush(cs,
2787 queue->device->physical_device->rad_info.chip_class,
2788 NULL, 0,
2789 queue->queue_family_index == RING_COMPUTE &&
2790 queue->device->physical_device->rad_info.chip_class >= GFX7,
2791 RADV_CMD_FLAG_INV_ICACHE |
2792 RADV_CMD_FLAG_INV_SCACHE |
2793 RADV_CMD_FLAG_INV_VCACHE |
2794 RADV_CMD_FLAG_INV_L2 |
2795 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2796 }
2797
2798 if (!queue->device->ws->cs_finalize(cs))
2799 goto fail;
2800 }
2801
2802 if (queue->initial_full_flush_preamble_cs)
2803 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2804
2805 if (queue->initial_preamble_cs)
2806 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2807
2808 if (queue->continue_preamble_cs)
2809 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2810
2811 queue->initial_full_flush_preamble_cs = dest_cs[0];
2812 queue->initial_preamble_cs = dest_cs[1];
2813 queue->continue_preamble_cs = dest_cs[2];
2814
2815 if (scratch_bo != queue->scratch_bo) {
2816 if (queue->scratch_bo)
2817 queue->device->ws->buffer_destroy(queue->scratch_bo);
2818 queue->scratch_bo = scratch_bo;
2819 queue->scratch_size = scratch_size;
2820 }
2821
2822 if (compute_scratch_bo != queue->compute_scratch_bo) {
2823 if (queue->compute_scratch_bo)
2824 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2825 queue->compute_scratch_bo = compute_scratch_bo;
2826 queue->compute_scratch_size = compute_scratch_size;
2827 }
2828
2829 if (esgs_ring_bo != queue->esgs_ring_bo) {
2830 if (queue->esgs_ring_bo)
2831 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2832 queue->esgs_ring_bo = esgs_ring_bo;
2833 queue->esgs_ring_size = esgs_ring_size;
2834 }
2835
2836 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2837 if (queue->gsvs_ring_bo)
2838 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2839 queue->gsvs_ring_bo = gsvs_ring_bo;
2840 queue->gsvs_ring_size = gsvs_ring_size;
2841 }
2842
2843 if (tess_rings_bo != queue->tess_rings_bo) {
2844 queue->tess_rings_bo = tess_rings_bo;
2845 queue->has_tess_rings = true;
2846 }
2847
2848 if (descriptor_bo != queue->descriptor_bo) {
2849 if (queue->descriptor_bo)
2850 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2851
2852 queue->descriptor_bo = descriptor_bo;
2853 }
2854
2855 if (add_sample_positions)
2856 queue->has_sample_positions = true;
2857
2858 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2859 *initial_preamble_cs = queue->initial_preamble_cs;
2860 *continue_preamble_cs = queue->continue_preamble_cs;
2861 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2862 *continue_preamble_cs = NULL;
2863 return VK_SUCCESS;
2864 fail:
2865 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2866 if (dest_cs[i])
2867 queue->device->ws->cs_destroy(dest_cs[i]);
2868 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2869 queue->device->ws->buffer_destroy(descriptor_bo);
2870 if (scratch_bo && scratch_bo != queue->scratch_bo)
2871 queue->device->ws->buffer_destroy(scratch_bo);
2872 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2873 queue->device->ws->buffer_destroy(compute_scratch_bo);
2874 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2875 queue->device->ws->buffer_destroy(esgs_ring_bo);
2876 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2877 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2878 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2879 queue->device->ws->buffer_destroy(tess_rings_bo);
2880 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2881 }
2882
2883 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2884 struct radv_winsys_sem_counts *counts,
2885 int num_sems,
2886 const VkSemaphore *sems,
2887 VkFence _fence,
2888 bool reset_temp)
2889 {
2890 int syncobj_idx = 0, sem_idx = 0;
2891
2892 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2893 return VK_SUCCESS;
2894
2895 for (uint32_t i = 0; i < num_sems; i++) {
2896 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2897
2898 if (sem->temp_syncobj || sem->syncobj)
2899 counts->syncobj_count++;
2900 else
2901 counts->sem_count++;
2902 }
2903
2904 if (_fence != VK_NULL_HANDLE) {
2905 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2906 if (fence->temp_syncobj || fence->syncobj)
2907 counts->syncobj_count++;
2908 }
2909
2910 if (counts->syncobj_count) {
2911 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2912 if (!counts->syncobj)
2913 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2914 }
2915
2916 if (counts->sem_count) {
2917 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2918 if (!counts->sem) {
2919 free(counts->syncobj);
2920 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2921 }
2922 }
2923
2924 for (uint32_t i = 0; i < num_sems; i++) {
2925 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2926
2927 if (sem->temp_syncobj) {
2928 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2929 }
2930 else if (sem->syncobj)
2931 counts->syncobj[syncobj_idx++] = sem->syncobj;
2932 else {
2933 assert(sem->sem);
2934 counts->sem[sem_idx++] = sem->sem;
2935 }
2936 }
2937
2938 if (_fence != VK_NULL_HANDLE) {
2939 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2940 if (fence->temp_syncobj)
2941 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2942 else if (fence->syncobj)
2943 counts->syncobj[syncobj_idx++] = fence->syncobj;
2944 }
2945
2946 return VK_SUCCESS;
2947 }
2948
2949 static void
2950 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2951 {
2952 free(sem_info->wait.syncobj);
2953 free(sem_info->wait.sem);
2954 free(sem_info->signal.syncobj);
2955 free(sem_info->signal.sem);
2956 }
2957
2958
2959 static void radv_free_temp_syncobjs(struct radv_device *device,
2960 int num_sems,
2961 const VkSemaphore *sems)
2962 {
2963 for (uint32_t i = 0; i < num_sems; i++) {
2964 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2965
2966 if (sem->temp_syncobj) {
2967 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2968 sem->temp_syncobj = 0;
2969 }
2970 }
2971 }
2972
2973 static VkResult
2974 radv_alloc_sem_info(struct radv_instance *instance,
2975 struct radv_winsys_sem_info *sem_info,
2976 int num_wait_sems,
2977 const VkSemaphore *wait_sems,
2978 int num_signal_sems,
2979 const VkSemaphore *signal_sems,
2980 VkFence fence)
2981 {
2982 VkResult ret;
2983 memset(sem_info, 0, sizeof(*sem_info));
2984
2985 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2986 if (ret)
2987 return ret;
2988 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2989 if (ret)
2990 radv_free_sem_info(sem_info);
2991
2992 /* caller can override these */
2993 sem_info->cs_emit_wait = true;
2994 sem_info->cs_emit_signal = true;
2995 return ret;
2996 }
2997
2998 /* Signals fence as soon as all the work currently put on queue is done. */
2999 static VkResult radv_signal_fence(struct radv_queue *queue,
3000 struct radv_fence *fence)
3001 {
3002 int ret;
3003 VkResult result;
3004 struct radv_winsys_sem_info sem_info;
3005
3006 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
3007 radv_fence_to_handle(fence));
3008 if (result != VK_SUCCESS)
3009 return result;
3010
3011 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3012 &queue->device->empty_cs[queue->queue_family_index],
3013 1, NULL, NULL, &sem_info, NULL,
3014 false, fence->fence);
3015 radv_free_sem_info(&sem_info);
3016
3017 if (ret)
3018 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
3019
3020 return VK_SUCCESS;
3021 }
3022
3023 VkResult radv_QueueSubmit(
3024 VkQueue _queue,
3025 uint32_t submitCount,
3026 const VkSubmitInfo* pSubmits,
3027 VkFence _fence)
3028 {
3029 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3030 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3031 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3032 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
3033 int ret;
3034 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
3035 uint32_t scratch_size = 0;
3036 uint32_t compute_scratch_size = 0;
3037 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
3038 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
3039 VkResult result;
3040 bool fence_emitted = false;
3041 bool tess_rings_needed = false;
3042 bool sample_positions_needed = false;
3043
3044 /* Do this first so failing to allocate scratch buffers can't result in
3045 * partially executed submissions. */
3046 for (uint32_t i = 0; i < submitCount; i++) {
3047 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3048 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3049 pSubmits[i].pCommandBuffers[j]);
3050
3051 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
3052 compute_scratch_size = MAX2(compute_scratch_size,
3053 cmd_buffer->compute_scratch_size_needed);
3054 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
3055 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
3056 tess_rings_needed |= cmd_buffer->tess_rings_needed;
3057 sample_positions_needed |= cmd_buffer->sample_positions_needed;
3058 }
3059 }
3060
3061 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
3062 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
3063 sample_positions_needed, &initial_flush_preamble_cs,
3064 &initial_preamble_cs, &continue_preamble_cs);
3065 if (result != VK_SUCCESS)
3066 return result;
3067
3068 for (uint32_t i = 0; i < submitCount; i++) {
3069 struct radeon_cmdbuf **cs_array;
3070 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
3071 bool can_patch = true;
3072 uint32_t advance;
3073 struct radv_winsys_sem_info sem_info;
3074
3075 result = radv_alloc_sem_info(queue->device->instance,
3076 &sem_info,
3077 pSubmits[i].waitSemaphoreCount,
3078 pSubmits[i].pWaitSemaphores,
3079 pSubmits[i].signalSemaphoreCount,
3080 pSubmits[i].pSignalSemaphores,
3081 _fence);
3082 if (result != VK_SUCCESS)
3083 return result;
3084
3085 if (!pSubmits[i].commandBufferCount) {
3086 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
3087 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
3088 &queue->device->empty_cs[queue->queue_family_index],
3089 1, NULL, NULL,
3090 &sem_info, NULL,
3091 false, base_fence);
3092 if (ret) {
3093 radv_loge("failed to submit CS %d\n", i);
3094 abort();
3095 }
3096 fence_emitted = true;
3097 }
3098 radv_free_sem_info(&sem_info);
3099 continue;
3100 }
3101
3102 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
3103 (pSubmits[i].commandBufferCount));
3104
3105 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
3106 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
3107 pSubmits[i].pCommandBuffers[j]);
3108 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
3109
3110 cs_array[j] = cmd_buffer->cs;
3111 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
3112 can_patch = false;
3113
3114 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
3115 }
3116
3117 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
3118 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
3119 const struct radv_winsys_bo_list *bo_list = NULL;
3120
3121 advance = MIN2(max_cs_submission,
3122 pSubmits[i].commandBufferCount - j);
3123
3124 if (queue->device->trace_bo)
3125 *queue->device->trace_id_ptr = 0;
3126
3127 sem_info.cs_emit_wait = j == 0;
3128 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
3129
3130 if (unlikely(queue->device->use_global_bo_list)) {
3131 pthread_mutex_lock(&queue->device->bo_list.mutex);
3132 bo_list = &queue->device->bo_list.list;
3133 }
3134
3135 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3136 advance, initial_preamble, continue_preamble_cs,
3137 &sem_info, bo_list,
3138 can_patch, base_fence);
3139
3140 if (unlikely(queue->device->use_global_bo_list))
3141 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3142
3143 if (ret) {
3144 radv_loge("failed to submit CS %d\n", i);
3145 abort();
3146 }
3147 fence_emitted = true;
3148 if (queue->device->trace_bo) {
3149 radv_check_gpu_hangs(queue, cs_array[j]);
3150 }
3151 }
3152
3153 radv_free_temp_syncobjs(queue->device,
3154 pSubmits[i].waitSemaphoreCount,
3155 pSubmits[i].pWaitSemaphores);
3156 radv_free_sem_info(&sem_info);
3157 free(cs_array);
3158 }
3159
3160 if (fence) {
3161 if (!fence_emitted) {
3162 result = radv_signal_fence(queue, fence);
3163 if (result != VK_SUCCESS)
3164 return result;
3165 }
3166 }
3167
3168 return VK_SUCCESS;
3169 }
3170
3171 VkResult radv_QueueWaitIdle(
3172 VkQueue _queue)
3173 {
3174 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3175
3176 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3177 radv_queue_family_to_ring(queue->queue_family_index),
3178 queue->queue_idx);
3179 return VK_SUCCESS;
3180 }
3181
3182 VkResult radv_DeviceWaitIdle(
3183 VkDevice _device)
3184 {
3185 RADV_FROM_HANDLE(radv_device, device, _device);
3186
3187 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3188 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3189 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3190 }
3191 }
3192 return VK_SUCCESS;
3193 }
3194
3195 VkResult radv_EnumerateInstanceExtensionProperties(
3196 const char* pLayerName,
3197 uint32_t* pPropertyCount,
3198 VkExtensionProperties* pProperties)
3199 {
3200 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3201
3202 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3203 if (radv_supported_instance_extensions.extensions[i]) {
3204 vk_outarray_append(&out, prop) {
3205 *prop = radv_instance_extensions[i];
3206 }
3207 }
3208 }
3209
3210 return vk_outarray_status(&out);
3211 }
3212
3213 VkResult radv_EnumerateDeviceExtensionProperties(
3214 VkPhysicalDevice physicalDevice,
3215 const char* pLayerName,
3216 uint32_t* pPropertyCount,
3217 VkExtensionProperties* pProperties)
3218 {
3219 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3220 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3221
3222 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3223 if (device->supported_extensions.extensions[i]) {
3224 vk_outarray_append(&out, prop) {
3225 *prop = radv_device_extensions[i];
3226 }
3227 }
3228 }
3229
3230 return vk_outarray_status(&out);
3231 }
3232
3233 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3234 VkInstance _instance,
3235 const char* pName)
3236 {
3237 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3238
3239 return radv_lookup_entrypoint_checked(pName,
3240 instance ? instance->apiVersion : 0,
3241 instance ? &instance->enabled_extensions : NULL,
3242 NULL);
3243 }
3244
3245 /* The loader wants us to expose a second GetInstanceProcAddr function
3246 * to work around certain LD_PRELOAD issues seen in apps.
3247 */
3248 PUBLIC
3249 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3250 VkInstance instance,
3251 const char* pName);
3252
3253 PUBLIC
3254 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3255 VkInstance instance,
3256 const char* pName)
3257 {
3258 return radv_GetInstanceProcAddr(instance, pName);
3259 }
3260
3261 PUBLIC
3262 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3263 VkInstance _instance,
3264 const char* pName);
3265
3266 PUBLIC
3267 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetPhysicalDeviceProcAddr(
3268 VkInstance _instance,
3269 const char* pName)
3270 {
3271 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3272
3273 return radv_lookup_physical_device_entrypoint_checked(pName,
3274 instance ? instance->apiVersion : 0,
3275 instance ? &instance->enabled_extensions : NULL);
3276 }
3277
3278 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3279 VkDevice _device,
3280 const char* pName)
3281 {
3282 RADV_FROM_HANDLE(radv_device, device, _device);
3283
3284 return radv_lookup_entrypoint_checked(pName,
3285 device->instance->apiVersion,
3286 &device->instance->enabled_extensions,
3287 &device->enabled_extensions);
3288 }
3289
3290 bool radv_get_memory_fd(struct radv_device *device,
3291 struct radv_device_memory *memory,
3292 int *pFD)
3293 {
3294 struct radeon_bo_metadata metadata;
3295
3296 if (memory->image) {
3297 radv_init_metadata(device, memory->image, &metadata);
3298 device->ws->buffer_set_metadata(memory->bo, &metadata);
3299 }
3300
3301 return device->ws->buffer_get_fd(device->ws, memory->bo,
3302 pFD);
3303 }
3304
3305 static VkResult radv_alloc_memory(struct radv_device *device,
3306 const VkMemoryAllocateInfo* pAllocateInfo,
3307 const VkAllocationCallbacks* pAllocator,
3308 VkDeviceMemory* pMem)
3309 {
3310 struct radv_device_memory *mem;
3311 VkResult result;
3312 enum radeon_bo_domain domain;
3313 uint32_t flags = 0;
3314 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3315
3316 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3317
3318 if (pAllocateInfo->allocationSize == 0) {
3319 /* Apparently, this is allowed */
3320 *pMem = VK_NULL_HANDLE;
3321 return VK_SUCCESS;
3322 }
3323
3324 const VkImportMemoryFdInfoKHR *import_info =
3325 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3326 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3327 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3328 const VkExportMemoryAllocateInfo *export_info =
3329 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3330 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3331 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3332
3333 const struct wsi_memory_allocate_info *wsi_info =
3334 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3335
3336 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3337 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3338 if (mem == NULL)
3339 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3340
3341 if (wsi_info && wsi_info->implicit_sync)
3342 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3343
3344 if (dedicate_info) {
3345 mem->image = radv_image_from_handle(dedicate_info->image);
3346 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3347 } else {
3348 mem->image = NULL;
3349 mem->buffer = NULL;
3350 }
3351
3352 float priority_float = 0.5;
3353 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3354 vk_find_struct_const(pAllocateInfo->pNext,
3355 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3356 if (priority_ext)
3357 priority_float = priority_ext->priority;
3358
3359 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3360 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3361
3362 mem->user_ptr = NULL;
3363
3364 if (import_info) {
3365 assert(import_info->handleType ==
3366 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3367 import_info->handleType ==
3368 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3369 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3370 priority, NULL, NULL);
3371 if (!mem->bo) {
3372 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3373 goto fail;
3374 } else {
3375 close(import_info->fd);
3376 }
3377 } else if (host_ptr_info) {
3378 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3379 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3380 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3381 pAllocateInfo->allocationSize,
3382 priority);
3383 if (!mem->bo) {
3384 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3385 goto fail;
3386 } else {
3387 mem->user_ptr = host_ptr_info->pHostPointer;
3388 }
3389 } else {
3390 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3391 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3392 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3393 domain = RADEON_DOMAIN_GTT;
3394 else
3395 domain = RADEON_DOMAIN_VRAM;
3396
3397 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3398 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3399 else
3400 flags |= RADEON_FLAG_CPU_ACCESS;
3401
3402 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3403 flags |= RADEON_FLAG_GTT_WC;
3404
3405 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3406 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3407 if (device->use_global_bo_list) {
3408 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3409 }
3410 }
3411
3412 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3413 domain, flags, priority);
3414
3415 if (!mem->bo) {
3416 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3417 goto fail;
3418 }
3419 mem->type_index = mem_type_index;
3420 }
3421
3422 result = radv_bo_list_add(device, mem->bo);
3423 if (result != VK_SUCCESS)
3424 goto fail_bo;
3425
3426 *pMem = radv_device_memory_to_handle(mem);
3427
3428 return VK_SUCCESS;
3429
3430 fail_bo:
3431 device->ws->buffer_destroy(mem->bo);
3432 fail:
3433 vk_free2(&device->alloc, pAllocator, mem);
3434
3435 return result;
3436 }
3437
3438 VkResult radv_AllocateMemory(
3439 VkDevice _device,
3440 const VkMemoryAllocateInfo* pAllocateInfo,
3441 const VkAllocationCallbacks* pAllocator,
3442 VkDeviceMemory* pMem)
3443 {
3444 RADV_FROM_HANDLE(radv_device, device, _device);
3445 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3446 }
3447
3448 void radv_FreeMemory(
3449 VkDevice _device,
3450 VkDeviceMemory _mem,
3451 const VkAllocationCallbacks* pAllocator)
3452 {
3453 RADV_FROM_HANDLE(radv_device, device, _device);
3454 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3455
3456 if (mem == NULL)
3457 return;
3458
3459 radv_bo_list_remove(device, mem->bo);
3460 device->ws->buffer_destroy(mem->bo);
3461 mem->bo = NULL;
3462
3463 vk_free2(&device->alloc, pAllocator, mem);
3464 }
3465
3466 VkResult radv_MapMemory(
3467 VkDevice _device,
3468 VkDeviceMemory _memory,
3469 VkDeviceSize offset,
3470 VkDeviceSize size,
3471 VkMemoryMapFlags flags,
3472 void** ppData)
3473 {
3474 RADV_FROM_HANDLE(radv_device, device, _device);
3475 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3476
3477 if (mem == NULL) {
3478 *ppData = NULL;
3479 return VK_SUCCESS;
3480 }
3481
3482 if (mem->user_ptr)
3483 *ppData = mem->user_ptr;
3484 else
3485 *ppData = device->ws->buffer_map(mem->bo);
3486
3487 if (*ppData) {
3488 *ppData += offset;
3489 return VK_SUCCESS;
3490 }
3491
3492 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3493 }
3494
3495 void radv_UnmapMemory(
3496 VkDevice _device,
3497 VkDeviceMemory _memory)
3498 {
3499 RADV_FROM_HANDLE(radv_device, device, _device);
3500 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3501
3502 if (mem == NULL)
3503 return;
3504
3505 if (mem->user_ptr == NULL)
3506 device->ws->buffer_unmap(mem->bo);
3507 }
3508
3509 VkResult radv_FlushMappedMemoryRanges(
3510 VkDevice _device,
3511 uint32_t memoryRangeCount,
3512 const VkMappedMemoryRange* pMemoryRanges)
3513 {
3514 return VK_SUCCESS;
3515 }
3516
3517 VkResult radv_InvalidateMappedMemoryRanges(
3518 VkDevice _device,
3519 uint32_t memoryRangeCount,
3520 const VkMappedMemoryRange* pMemoryRanges)
3521 {
3522 return VK_SUCCESS;
3523 }
3524
3525 void radv_GetBufferMemoryRequirements(
3526 VkDevice _device,
3527 VkBuffer _buffer,
3528 VkMemoryRequirements* pMemoryRequirements)
3529 {
3530 RADV_FROM_HANDLE(radv_device, device, _device);
3531 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3532
3533 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3534
3535 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3536 pMemoryRequirements->alignment = 4096;
3537 else
3538 pMemoryRequirements->alignment = 16;
3539
3540 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3541 }
3542
3543 void radv_GetBufferMemoryRequirements2(
3544 VkDevice device,
3545 const VkBufferMemoryRequirementsInfo2 *pInfo,
3546 VkMemoryRequirements2 *pMemoryRequirements)
3547 {
3548 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3549 &pMemoryRequirements->memoryRequirements);
3550 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3551 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3552 switch (ext->sType) {
3553 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3554 VkMemoryDedicatedRequirements *req =
3555 (VkMemoryDedicatedRequirements *) ext;
3556 req->requiresDedicatedAllocation = buffer->shareable;
3557 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3558 break;
3559 }
3560 default:
3561 break;
3562 }
3563 }
3564 }
3565
3566 void radv_GetImageMemoryRequirements(
3567 VkDevice _device,
3568 VkImage _image,
3569 VkMemoryRequirements* pMemoryRequirements)
3570 {
3571 RADV_FROM_HANDLE(radv_device, device, _device);
3572 RADV_FROM_HANDLE(radv_image, image, _image);
3573
3574 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3575
3576 pMemoryRequirements->size = image->size;
3577 pMemoryRequirements->alignment = image->alignment;
3578 }
3579
3580 void radv_GetImageMemoryRequirements2(
3581 VkDevice device,
3582 const VkImageMemoryRequirementsInfo2 *pInfo,
3583 VkMemoryRequirements2 *pMemoryRequirements)
3584 {
3585 radv_GetImageMemoryRequirements(device, pInfo->image,
3586 &pMemoryRequirements->memoryRequirements);
3587
3588 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3589
3590 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3591 switch (ext->sType) {
3592 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3593 VkMemoryDedicatedRequirements *req =
3594 (VkMemoryDedicatedRequirements *) ext;
3595 req->requiresDedicatedAllocation = image->shareable;
3596 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3597 break;
3598 }
3599 default:
3600 break;
3601 }
3602 }
3603 }
3604
3605 void radv_GetImageSparseMemoryRequirements(
3606 VkDevice device,
3607 VkImage image,
3608 uint32_t* pSparseMemoryRequirementCount,
3609 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3610 {
3611 stub();
3612 }
3613
3614 void radv_GetImageSparseMemoryRequirements2(
3615 VkDevice device,
3616 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3617 uint32_t* pSparseMemoryRequirementCount,
3618 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3619 {
3620 stub();
3621 }
3622
3623 void radv_GetDeviceMemoryCommitment(
3624 VkDevice device,
3625 VkDeviceMemory memory,
3626 VkDeviceSize* pCommittedMemoryInBytes)
3627 {
3628 *pCommittedMemoryInBytes = 0;
3629 }
3630
3631 VkResult radv_BindBufferMemory2(VkDevice device,
3632 uint32_t bindInfoCount,
3633 const VkBindBufferMemoryInfo *pBindInfos)
3634 {
3635 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3636 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3637 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3638
3639 if (mem) {
3640 buffer->bo = mem->bo;
3641 buffer->offset = pBindInfos[i].memoryOffset;
3642 } else {
3643 buffer->bo = NULL;
3644 }
3645 }
3646 return VK_SUCCESS;
3647 }
3648
3649 VkResult radv_BindBufferMemory(
3650 VkDevice device,
3651 VkBuffer buffer,
3652 VkDeviceMemory memory,
3653 VkDeviceSize memoryOffset)
3654 {
3655 const VkBindBufferMemoryInfo info = {
3656 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3657 .buffer = buffer,
3658 .memory = memory,
3659 .memoryOffset = memoryOffset
3660 };
3661
3662 return radv_BindBufferMemory2(device, 1, &info);
3663 }
3664
3665 VkResult radv_BindImageMemory2(VkDevice device,
3666 uint32_t bindInfoCount,
3667 const VkBindImageMemoryInfo *pBindInfos)
3668 {
3669 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3670 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3671 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3672
3673 if (mem) {
3674 image->bo = mem->bo;
3675 image->offset = pBindInfos[i].memoryOffset;
3676 } else {
3677 image->bo = NULL;
3678 image->offset = 0;
3679 }
3680 }
3681 return VK_SUCCESS;
3682 }
3683
3684
3685 VkResult radv_BindImageMemory(
3686 VkDevice device,
3687 VkImage image,
3688 VkDeviceMemory memory,
3689 VkDeviceSize memoryOffset)
3690 {
3691 const VkBindImageMemoryInfo info = {
3692 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3693 .image = image,
3694 .memory = memory,
3695 .memoryOffset = memoryOffset
3696 };
3697
3698 return radv_BindImageMemory2(device, 1, &info);
3699 }
3700
3701
3702 static void
3703 radv_sparse_buffer_bind_memory(struct radv_device *device,
3704 const VkSparseBufferMemoryBindInfo *bind)
3705 {
3706 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3707
3708 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3709 struct radv_device_memory *mem = NULL;
3710
3711 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3712 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3713
3714 device->ws->buffer_virtual_bind(buffer->bo,
3715 bind->pBinds[i].resourceOffset,
3716 bind->pBinds[i].size,
3717 mem ? mem->bo : NULL,
3718 bind->pBinds[i].memoryOffset);
3719 }
3720 }
3721
3722 static void
3723 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3724 const VkSparseImageOpaqueMemoryBindInfo *bind)
3725 {
3726 RADV_FROM_HANDLE(radv_image, image, bind->image);
3727
3728 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3729 struct radv_device_memory *mem = NULL;
3730
3731 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3732 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3733
3734 device->ws->buffer_virtual_bind(image->bo,
3735 bind->pBinds[i].resourceOffset,
3736 bind->pBinds[i].size,
3737 mem ? mem->bo : NULL,
3738 bind->pBinds[i].memoryOffset);
3739 }
3740 }
3741
3742 VkResult radv_QueueBindSparse(
3743 VkQueue _queue,
3744 uint32_t bindInfoCount,
3745 const VkBindSparseInfo* pBindInfo,
3746 VkFence _fence)
3747 {
3748 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3749 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3750 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3751 bool fence_emitted = false;
3752 VkResult result;
3753 int ret;
3754
3755 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3756 struct radv_winsys_sem_info sem_info;
3757 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3758 radv_sparse_buffer_bind_memory(queue->device,
3759 pBindInfo[i].pBufferBinds + j);
3760 }
3761
3762 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3763 radv_sparse_image_opaque_bind_memory(queue->device,
3764 pBindInfo[i].pImageOpaqueBinds + j);
3765 }
3766
3767 VkResult result;
3768 result = radv_alloc_sem_info(queue->device->instance,
3769 &sem_info,
3770 pBindInfo[i].waitSemaphoreCount,
3771 pBindInfo[i].pWaitSemaphores,
3772 pBindInfo[i].signalSemaphoreCount,
3773 pBindInfo[i].pSignalSemaphores,
3774 _fence);
3775 if (result != VK_SUCCESS)
3776 return result;
3777
3778 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3779 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3780 &queue->device->empty_cs[queue->queue_family_index],
3781 1, NULL, NULL,
3782 &sem_info, NULL,
3783 false, base_fence);
3784 if (ret) {
3785 radv_loge("failed to submit CS %d\n", i);
3786 abort();
3787 }
3788
3789 fence_emitted = true;
3790 }
3791
3792 radv_free_sem_info(&sem_info);
3793
3794 }
3795
3796 if (fence) {
3797 if (!fence_emitted) {
3798 result = radv_signal_fence(queue, fence);
3799 if (result != VK_SUCCESS)
3800 return result;
3801 }
3802 }
3803
3804 return VK_SUCCESS;
3805 }
3806
3807 VkResult radv_CreateFence(
3808 VkDevice _device,
3809 const VkFenceCreateInfo* pCreateInfo,
3810 const VkAllocationCallbacks* pAllocator,
3811 VkFence* pFence)
3812 {
3813 RADV_FROM_HANDLE(radv_device, device, _device);
3814 const VkExportFenceCreateInfo *export =
3815 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3816 VkExternalFenceHandleTypeFlags handleTypes =
3817 export ? export->handleTypes : 0;
3818
3819 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3820 sizeof(*fence), 8,
3821 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3822
3823 if (!fence)
3824 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3825
3826 fence->fence_wsi = NULL;
3827 fence->temp_syncobj = 0;
3828 if (device->always_use_syncobj || handleTypes) {
3829 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3830 if (ret) {
3831 vk_free2(&device->alloc, pAllocator, fence);
3832 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3833 }
3834 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3835 device->ws->signal_syncobj(device->ws, fence->syncobj);
3836 }
3837 fence->fence = NULL;
3838 } else {
3839 fence->fence = device->ws->create_fence();
3840 if (!fence->fence) {
3841 vk_free2(&device->alloc, pAllocator, fence);
3842 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3843 }
3844 fence->syncobj = 0;
3845 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT)
3846 device->ws->signal_fence(fence->fence);
3847 }
3848
3849 *pFence = radv_fence_to_handle(fence);
3850
3851 return VK_SUCCESS;
3852 }
3853
3854 void radv_DestroyFence(
3855 VkDevice _device,
3856 VkFence _fence,
3857 const VkAllocationCallbacks* pAllocator)
3858 {
3859 RADV_FROM_HANDLE(radv_device, device, _device);
3860 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3861
3862 if (!fence)
3863 return;
3864
3865 if (fence->temp_syncobj)
3866 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3867 if (fence->syncobj)
3868 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3869 if (fence->fence)
3870 device->ws->destroy_fence(fence->fence);
3871 if (fence->fence_wsi)
3872 fence->fence_wsi->destroy(fence->fence_wsi);
3873 vk_free2(&device->alloc, pAllocator, fence);
3874 }
3875
3876
3877 uint64_t radv_get_current_time(void)
3878 {
3879 struct timespec tv;
3880 clock_gettime(CLOCK_MONOTONIC, &tv);
3881 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3882 }
3883
3884 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3885 {
3886 uint64_t current_time = radv_get_current_time();
3887
3888 timeout = MIN2(UINT64_MAX - current_time, timeout);
3889
3890 return current_time + timeout;
3891 }
3892
3893
3894 static bool radv_all_fences_plain_and_submitted(struct radv_device *device,
3895 uint32_t fenceCount, const VkFence *pFences)
3896 {
3897 for (uint32_t i = 0; i < fenceCount; ++i) {
3898 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3899 if (fence->fence == NULL || fence->syncobj ||
3900 fence->temp_syncobj || fence->fence_wsi ||
3901 (!device->ws->is_fence_waitable(fence->fence)))
3902 return false;
3903 }
3904 return true;
3905 }
3906
3907 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3908 {
3909 for (uint32_t i = 0; i < fenceCount; ++i) {
3910 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3911 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3912 return false;
3913 }
3914 return true;
3915 }
3916
3917 VkResult radv_WaitForFences(
3918 VkDevice _device,
3919 uint32_t fenceCount,
3920 const VkFence* pFences,
3921 VkBool32 waitAll,
3922 uint64_t timeout)
3923 {
3924 RADV_FROM_HANDLE(radv_device, device, _device);
3925 timeout = radv_get_absolute_timeout(timeout);
3926
3927 if (device->always_use_syncobj &&
3928 radv_all_fences_syncobj(fenceCount, pFences))
3929 {
3930 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3931 if (!handles)
3932 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3933
3934 for (uint32_t i = 0; i < fenceCount; ++i) {
3935 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3936 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3937 }
3938
3939 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3940
3941 free(handles);
3942 return success ? VK_SUCCESS : VK_TIMEOUT;
3943 }
3944
3945 if (!waitAll && fenceCount > 1) {
3946 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3947 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(device, fenceCount, pFences)) {
3948 uint32_t wait_count = 0;
3949 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3950 if (!fences)
3951 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3952
3953 for (uint32_t i = 0; i < fenceCount; ++i) {
3954 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3955
3956 if (device->ws->fence_wait(device->ws, fence->fence, false, 0)) {
3957 free(fences);
3958 return VK_SUCCESS;
3959 }
3960
3961 fences[wait_count++] = fence->fence;
3962 }
3963
3964 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3965 waitAll, timeout - radv_get_current_time());
3966
3967 free(fences);
3968 return success ? VK_SUCCESS : VK_TIMEOUT;
3969 }
3970
3971 while(radv_get_current_time() <= timeout) {
3972 for (uint32_t i = 0; i < fenceCount; ++i) {
3973 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3974 return VK_SUCCESS;
3975 }
3976 }
3977 return VK_TIMEOUT;
3978 }
3979
3980 for (uint32_t i = 0; i < fenceCount; ++i) {
3981 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3982 bool expired = false;
3983
3984 if (fence->temp_syncobj) {
3985 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3986 return VK_TIMEOUT;
3987 continue;
3988 }
3989
3990 if (fence->syncobj) {
3991 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3992 return VK_TIMEOUT;
3993 continue;
3994 }
3995
3996 if (fence->fence) {
3997 if (!device->ws->is_fence_waitable(fence->fence)) {
3998 while(!device->ws->is_fence_waitable(fence->fence) &&
3999 radv_get_current_time() <= timeout)
4000 /* Do nothing */;
4001 }
4002
4003 expired = device->ws->fence_wait(device->ws,
4004 fence->fence,
4005 true, timeout);
4006 if (!expired)
4007 return VK_TIMEOUT;
4008 }
4009
4010 if (fence->fence_wsi) {
4011 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
4012 if (result != VK_SUCCESS)
4013 return result;
4014 }
4015 }
4016
4017 return VK_SUCCESS;
4018 }
4019
4020 VkResult radv_ResetFences(VkDevice _device,
4021 uint32_t fenceCount,
4022 const VkFence *pFences)
4023 {
4024 RADV_FROM_HANDLE(radv_device, device, _device);
4025
4026 for (unsigned i = 0; i < fenceCount; ++i) {
4027 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
4028 if (fence->fence)
4029 device->ws->reset_fence(fence->fence);
4030
4031 /* Per spec, we first restore the permanent payload, and then reset, so
4032 * having a temp syncobj should not skip resetting the permanent syncobj. */
4033 if (fence->temp_syncobj) {
4034 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
4035 fence->temp_syncobj = 0;
4036 }
4037
4038 if (fence->syncobj) {
4039 device->ws->reset_syncobj(device->ws, fence->syncobj);
4040 }
4041 }
4042
4043 return VK_SUCCESS;
4044 }
4045
4046 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
4047 {
4048 RADV_FROM_HANDLE(radv_device, device, _device);
4049 RADV_FROM_HANDLE(radv_fence, fence, _fence);
4050
4051 if (fence->temp_syncobj) {
4052 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
4053 return success ? VK_SUCCESS : VK_NOT_READY;
4054 }
4055
4056 if (fence->syncobj) {
4057 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
4058 return success ? VK_SUCCESS : VK_NOT_READY;
4059 }
4060
4061 if (fence->fence) {
4062 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
4063 return VK_NOT_READY;
4064 }
4065 if (fence->fence_wsi) {
4066 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
4067
4068 if (result != VK_SUCCESS) {
4069 if (result == VK_TIMEOUT)
4070 return VK_NOT_READY;
4071 return result;
4072 }
4073 }
4074 return VK_SUCCESS;
4075 }
4076
4077
4078 // Queue semaphore functions
4079
4080 VkResult radv_CreateSemaphore(
4081 VkDevice _device,
4082 const VkSemaphoreCreateInfo* pCreateInfo,
4083 const VkAllocationCallbacks* pAllocator,
4084 VkSemaphore* pSemaphore)
4085 {
4086 RADV_FROM_HANDLE(radv_device, device, _device);
4087 const VkExportSemaphoreCreateInfo *export =
4088 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
4089 VkExternalSemaphoreHandleTypeFlags handleTypes =
4090 export ? export->handleTypes : 0;
4091
4092 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
4093 sizeof(*sem), 8,
4094 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4095 if (!sem)
4096 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4097
4098 sem->temp_syncobj = 0;
4099 /* create a syncobject if we are going to export this semaphore */
4100 if (device->always_use_syncobj || handleTypes) {
4101 assert (device->physical_device->rad_info.has_syncobj);
4102 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
4103 if (ret) {
4104 vk_free2(&device->alloc, pAllocator, sem);
4105 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4106 }
4107 sem->sem = NULL;
4108 } else {
4109 sem->sem = device->ws->create_sem(device->ws);
4110 if (!sem->sem) {
4111 vk_free2(&device->alloc, pAllocator, sem);
4112 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4113 }
4114 sem->syncobj = 0;
4115 }
4116
4117 *pSemaphore = radv_semaphore_to_handle(sem);
4118 return VK_SUCCESS;
4119 }
4120
4121 void radv_DestroySemaphore(
4122 VkDevice _device,
4123 VkSemaphore _semaphore,
4124 const VkAllocationCallbacks* pAllocator)
4125 {
4126 RADV_FROM_HANDLE(radv_device, device, _device);
4127 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
4128 if (!_semaphore)
4129 return;
4130
4131 if (sem->syncobj)
4132 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4133 else
4134 device->ws->destroy_sem(sem->sem);
4135 vk_free2(&device->alloc, pAllocator, sem);
4136 }
4137
4138 VkResult radv_CreateEvent(
4139 VkDevice _device,
4140 const VkEventCreateInfo* pCreateInfo,
4141 const VkAllocationCallbacks* pAllocator,
4142 VkEvent* pEvent)
4143 {
4144 RADV_FROM_HANDLE(radv_device, device, _device);
4145 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4146 sizeof(*event), 8,
4147 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4148
4149 if (!event)
4150 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4151
4152 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4153 RADEON_DOMAIN_GTT,
4154 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4155 RADV_BO_PRIORITY_FENCE);
4156 if (!event->bo) {
4157 vk_free2(&device->alloc, pAllocator, event);
4158 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4159 }
4160
4161 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4162
4163 *pEvent = radv_event_to_handle(event);
4164
4165 return VK_SUCCESS;
4166 }
4167
4168 void radv_DestroyEvent(
4169 VkDevice _device,
4170 VkEvent _event,
4171 const VkAllocationCallbacks* pAllocator)
4172 {
4173 RADV_FROM_HANDLE(radv_device, device, _device);
4174 RADV_FROM_HANDLE(radv_event, event, _event);
4175
4176 if (!event)
4177 return;
4178 device->ws->buffer_destroy(event->bo);
4179 vk_free2(&device->alloc, pAllocator, event);
4180 }
4181
4182 VkResult radv_GetEventStatus(
4183 VkDevice _device,
4184 VkEvent _event)
4185 {
4186 RADV_FROM_HANDLE(radv_event, event, _event);
4187
4188 if (*event->map == 1)
4189 return VK_EVENT_SET;
4190 return VK_EVENT_RESET;
4191 }
4192
4193 VkResult radv_SetEvent(
4194 VkDevice _device,
4195 VkEvent _event)
4196 {
4197 RADV_FROM_HANDLE(radv_event, event, _event);
4198 *event->map = 1;
4199
4200 return VK_SUCCESS;
4201 }
4202
4203 VkResult radv_ResetEvent(
4204 VkDevice _device,
4205 VkEvent _event)
4206 {
4207 RADV_FROM_HANDLE(radv_event, event, _event);
4208 *event->map = 0;
4209
4210 return VK_SUCCESS;
4211 }
4212
4213 VkResult radv_CreateBuffer(
4214 VkDevice _device,
4215 const VkBufferCreateInfo* pCreateInfo,
4216 const VkAllocationCallbacks* pAllocator,
4217 VkBuffer* pBuffer)
4218 {
4219 RADV_FROM_HANDLE(radv_device, device, _device);
4220 struct radv_buffer *buffer;
4221
4222 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4223
4224 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4225 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4226 if (buffer == NULL)
4227 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4228
4229 buffer->size = pCreateInfo->size;
4230 buffer->usage = pCreateInfo->usage;
4231 buffer->bo = NULL;
4232 buffer->offset = 0;
4233 buffer->flags = pCreateInfo->flags;
4234
4235 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4236 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4237
4238 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4239 buffer->bo = device->ws->buffer_create(device->ws,
4240 align64(buffer->size, 4096),
4241 4096, 0, RADEON_FLAG_VIRTUAL,
4242 RADV_BO_PRIORITY_VIRTUAL);
4243 if (!buffer->bo) {
4244 vk_free2(&device->alloc, pAllocator, buffer);
4245 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4246 }
4247 }
4248
4249 *pBuffer = radv_buffer_to_handle(buffer);
4250
4251 return VK_SUCCESS;
4252 }
4253
4254 void radv_DestroyBuffer(
4255 VkDevice _device,
4256 VkBuffer _buffer,
4257 const VkAllocationCallbacks* pAllocator)
4258 {
4259 RADV_FROM_HANDLE(radv_device, device, _device);
4260 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4261
4262 if (!buffer)
4263 return;
4264
4265 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4266 device->ws->buffer_destroy(buffer->bo);
4267
4268 vk_free2(&device->alloc, pAllocator, buffer);
4269 }
4270
4271 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4272 VkDevice device,
4273 const VkBufferDeviceAddressInfoEXT* pInfo)
4274 {
4275 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4276 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4277 }
4278
4279
4280 static inline unsigned
4281 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4282 {
4283 if (stencil)
4284 return plane->surface.u.legacy.stencil_tiling_index[level];
4285 else
4286 return plane->surface.u.legacy.tiling_index[level];
4287 }
4288
4289 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4290 {
4291 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4292 }
4293
4294 static uint32_t
4295 radv_init_dcc_control_reg(struct radv_device *device,
4296 struct radv_image_view *iview)
4297 {
4298 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4299 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4300 unsigned max_compressed_block_size;
4301 unsigned independent_128b_blocks;
4302 unsigned independent_64b_blocks;
4303
4304 if (!radv_dcc_enabled(iview->image, iview->base_mip))
4305 return 0;
4306
4307 if (!device->physical_device->rad_info.has_dedicated_vram) {
4308 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4309 * dGPU and 64 for APU because all of our APUs to date use
4310 * DIMMs which have a request granularity size of 64B while all
4311 * other chips have a 32B request size.
4312 */
4313 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4314 }
4315
4316 if (device->physical_device->rad_info.chip_class >= GFX10) {
4317 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4318 independent_64b_blocks = 0;
4319 independent_128b_blocks = 1;
4320 } else {
4321 independent_128b_blocks = 0;
4322
4323 if (iview->image->info.samples > 1) {
4324 if (iview->image->planes[0].surface.bpe == 1)
4325 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4326 else if (iview->image->planes[0].surface.bpe == 2)
4327 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4328 }
4329
4330 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4331 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4332 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4333 /* If this DCC image is potentially going to be used in texture
4334 * fetches, we need some special settings.
4335 */
4336 independent_64b_blocks = 1;
4337 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4338 } else {
4339 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4340 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4341 * big as possible for better compression state.
4342 */
4343 independent_64b_blocks = 0;
4344 max_compressed_block_size = max_uncompressed_block_size;
4345 }
4346 }
4347
4348 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4349 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4350 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4351 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks) |
4352 S_028C78_INDEPENDENT_128B_BLOCKS(independent_128b_blocks);
4353 }
4354
4355 static void
4356 radv_initialise_color_surface(struct radv_device *device,
4357 struct radv_color_buffer_info *cb,
4358 struct radv_image_view *iview)
4359 {
4360 const struct vk_format_description *desc;
4361 unsigned ntype, format, swap, endian;
4362 unsigned blend_clamp = 0, blend_bypass = 0;
4363 uint64_t va;
4364 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4365 const struct radeon_surf *surf = &plane->surface;
4366
4367 desc = vk_format_description(iview->vk_format);
4368
4369 memset(cb, 0, sizeof(*cb));
4370
4371 /* Intensity is implemented as Red, so treat it that way. */
4372 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4373
4374 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4375
4376 cb->cb_color_base = va >> 8;
4377
4378 if (device->physical_device->rad_info.chip_class >= GFX9) {
4379 struct gfx9_surf_meta_flags meta;
4380 if (iview->image->dcc_offset)
4381 meta = surf->u.gfx9.dcc;
4382 else
4383 meta = surf->u.gfx9.cmask;
4384
4385 if (device->physical_device->rad_info.chip_class >= GFX10) {
4386 cb->cb_color_attrib3 |= S_028EE0_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4387 S_028EE0_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4388 S_028EE0_CMASK_PIPE_ALIGNED(surf->u.gfx9.cmask.pipe_aligned) |
4389 S_028EE0_DCC_PIPE_ALIGNED(surf->u.gfx9.dcc.pipe_aligned);
4390 } else {
4391 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4392 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4393 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4394 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4395 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4396 }
4397
4398 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4399 cb->cb_color_base |= surf->tile_swizzle;
4400 } else {
4401 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4402 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4403
4404 cb->cb_color_base += level_info->offset >> 8;
4405 if (level_info->mode == RADEON_SURF_MODE_2D)
4406 cb->cb_color_base |= surf->tile_swizzle;
4407
4408 pitch_tile_max = level_info->nblk_x / 8 - 1;
4409 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4410 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4411
4412 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4413 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4414 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4415
4416 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4417
4418 if (radv_image_has_fmask(iview->image)) {
4419 if (device->physical_device->rad_info.chip_class >= GFX7)
4420 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4421 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4422 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4423 } else {
4424 /* This must be set for fast clear to work without FMASK. */
4425 if (device->physical_device->rad_info.chip_class >= GFX7)
4426 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4427 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4428 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4429 }
4430 }
4431
4432 /* CMASK variables */
4433 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4434 va += iview->image->cmask.offset;
4435 cb->cb_color_cmask = va >> 8;
4436
4437 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4438 va += iview->image->dcc_offset;
4439
4440 if (radv_dcc_enabled(iview->image, iview->base_mip) &&
4441 device->physical_device->rad_info.chip_class <= GFX8)
4442 va += plane->surface.u.legacy.level[iview->base_mip].dcc_offset;
4443
4444 unsigned dcc_tile_swizzle = surf->tile_swizzle;
4445 dcc_tile_swizzle &= (surf->dcc_alignment - 1) >> 8;
4446
4447 cb->cb_dcc_base = va >> 8;
4448 cb->cb_dcc_base |= dcc_tile_swizzle;
4449
4450 /* GFX10 field has the same base shift as the GFX6 field. */
4451 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4452 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4453 S_028C6C_SLICE_MAX_GFX10(max_slice);
4454
4455 if (iview->image->info.samples > 1) {
4456 unsigned log_samples = util_logbase2(iview->image->info.samples);
4457
4458 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4459 S_028C74_NUM_FRAGMENTS(log_samples);
4460 }
4461
4462 if (radv_image_has_fmask(iview->image)) {
4463 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4464 cb->cb_color_fmask = va >> 8;
4465 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4466 } else {
4467 cb->cb_color_fmask = cb->cb_color_base;
4468 }
4469
4470 ntype = radv_translate_color_numformat(iview->vk_format,
4471 desc,
4472 vk_format_get_first_non_void_channel(iview->vk_format));
4473 format = radv_translate_colorformat(iview->vk_format);
4474 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4475 radv_finishme("Illegal color\n");
4476 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4477 endian = radv_colorformat_endian_swap(format);
4478
4479 /* blend clamp should be set for all NORM/SRGB types */
4480 if (ntype == V_028C70_NUMBER_UNORM ||
4481 ntype == V_028C70_NUMBER_SNORM ||
4482 ntype == V_028C70_NUMBER_SRGB)
4483 blend_clamp = 1;
4484
4485 /* set blend bypass according to docs if SINT/UINT or
4486 8/24 COLOR variants */
4487 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4488 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4489 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4490 blend_clamp = 0;
4491 blend_bypass = 1;
4492 }
4493 #if 0
4494 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4495 (format == V_028C70_COLOR_8 ||
4496 format == V_028C70_COLOR_8_8 ||
4497 format == V_028C70_COLOR_8_8_8_8))
4498 ->color_is_int8 = true;
4499 #endif
4500 cb->cb_color_info = S_028C70_FORMAT(format) |
4501 S_028C70_COMP_SWAP(swap) |
4502 S_028C70_BLEND_CLAMP(blend_clamp) |
4503 S_028C70_BLEND_BYPASS(blend_bypass) |
4504 S_028C70_SIMPLE_FLOAT(1) |
4505 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4506 ntype != V_028C70_NUMBER_SNORM &&
4507 ntype != V_028C70_NUMBER_SRGB &&
4508 format != V_028C70_COLOR_8_24 &&
4509 format != V_028C70_COLOR_24_8) |
4510 S_028C70_NUMBER_TYPE(ntype) |
4511 S_028C70_ENDIAN(endian);
4512 if (radv_image_has_fmask(iview->image)) {
4513 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4514 if (device->physical_device->rad_info.chip_class == GFX6) {
4515 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4516 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4517 }
4518
4519 if (radv_image_is_tc_compat_cmask(iview->image)) {
4520 /* Allow the texture block to read FMASK directly
4521 * without decompressing it. This bit must be cleared
4522 * when performing FMASK_DECOMPRESS or DCC_COMPRESS,
4523 * otherwise the operation doesn't happen.
4524 */
4525 cb->cb_color_info |= S_028C70_FMASK_COMPRESS_1FRAG_ONLY(1);
4526
4527 /* Set CMASK into a tiling format that allows the
4528 * texture block to read it.
4529 */
4530 cb->cb_color_info |= S_028C70_CMASK_ADDR_TYPE(2);
4531 }
4532 }
4533
4534 if (radv_image_has_cmask(iview->image) &&
4535 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4536 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4537
4538 if (radv_dcc_enabled(iview->image, iview->base_mip))
4539 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4540
4541 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4542
4543 /* This must be set for fast clear to work without FMASK. */
4544 if (!radv_image_has_fmask(iview->image) &&
4545 device->physical_device->rad_info.chip_class == GFX6) {
4546 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4547 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4548 }
4549
4550 if (device->physical_device->rad_info.chip_class >= GFX9) {
4551 const struct vk_format_description *format_desc = vk_format_description(iview->image->vk_format);
4552
4553 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4554 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4555 unsigned width = iview->extent.width / (iview->plane_id ? format_desc->width_divisor : 1);
4556 unsigned height = iview->extent.height / (iview->plane_id ? format_desc->height_divisor : 1);
4557
4558 if (device->physical_device->rad_info.chip_class >= GFX10) {
4559 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX10(iview->base_mip);
4560
4561 cb->cb_color_attrib3 |= S_028EE0_MIP0_DEPTH(mip0_depth) |
4562 S_028EE0_RESOURCE_TYPE(surf->u.gfx9.resource_type) |
4563 S_028EE0_RESOURCE_LEVEL(1);
4564 } else {
4565 cb->cb_color_view |= S_028C6C_MIP_LEVEL_GFX9(iview->base_mip);
4566 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4567 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4568 }
4569
4570 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(width - 1) |
4571 S_028C68_MIP0_HEIGHT(height - 1) |
4572 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4573 }
4574 }
4575
4576 static unsigned
4577 radv_calc_decompress_on_z_planes(struct radv_device *device,
4578 struct radv_image_view *iview)
4579 {
4580 unsigned max_zplanes = 0;
4581
4582 assert(radv_image_is_tc_compat_htile(iview->image));
4583
4584 if (device->physical_device->rad_info.chip_class >= GFX9) {
4585 /* Default value for 32-bit depth surfaces. */
4586 max_zplanes = 4;
4587
4588 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4589 iview->image->info.samples > 1)
4590 max_zplanes = 2;
4591
4592 max_zplanes = max_zplanes + 1;
4593 } else {
4594 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4595 /* Do not enable Z plane compression for 16-bit depth
4596 * surfaces because isn't supported on GFX8. Only
4597 * 32-bit depth surfaces are supported by the hardware.
4598 * This allows to maintain shader compatibility and to
4599 * reduce the number of depth decompressions.
4600 */
4601 max_zplanes = 1;
4602 } else {
4603 if (iview->image->info.samples <= 1)
4604 max_zplanes = 5;
4605 else if (iview->image->info.samples <= 4)
4606 max_zplanes = 3;
4607 else
4608 max_zplanes = 2;
4609 }
4610 }
4611
4612 return max_zplanes;
4613 }
4614
4615 static void
4616 radv_initialise_ds_surface(struct radv_device *device,
4617 struct radv_ds_buffer_info *ds,
4618 struct radv_image_view *iview)
4619 {
4620 unsigned level = iview->base_mip;
4621 unsigned format, stencil_format;
4622 uint64_t va, s_offs, z_offs;
4623 bool stencil_only = false;
4624 const struct radv_image_plane *plane = &iview->image->planes[0];
4625 const struct radeon_surf *surf = &plane->surface;
4626
4627 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4628
4629 memset(ds, 0, sizeof(*ds));
4630 switch (iview->image->vk_format) {
4631 case VK_FORMAT_D24_UNORM_S8_UINT:
4632 case VK_FORMAT_X8_D24_UNORM_PACK32:
4633 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4634 ds->offset_scale = 2.0f;
4635 break;
4636 case VK_FORMAT_D16_UNORM:
4637 case VK_FORMAT_D16_UNORM_S8_UINT:
4638 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4639 ds->offset_scale = 4.0f;
4640 break;
4641 case VK_FORMAT_D32_SFLOAT:
4642 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4643 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4644 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4645 ds->offset_scale = 1.0f;
4646 break;
4647 case VK_FORMAT_S8_UINT:
4648 stencil_only = true;
4649 break;
4650 default:
4651 break;
4652 }
4653
4654 format = radv_translate_dbformat(iview->image->vk_format);
4655 stencil_format = surf->has_stencil ?
4656 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4657
4658 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4659 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4660 S_028008_SLICE_MAX(max_slice);
4661 if (device->physical_device->rad_info.chip_class >= GFX10) {
4662 ds->db_depth_view |= S_028008_SLICE_START_HI(iview->base_layer >> 11) |
4663 S_028008_SLICE_MAX_HI(max_slice >> 11);
4664 }
4665
4666 ds->db_htile_data_base = 0;
4667 ds->db_htile_surface = 0;
4668
4669 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4670 s_offs = z_offs = va;
4671
4672 if (device->physical_device->rad_info.chip_class >= GFX9) {
4673 assert(surf->u.gfx9.surf_offset == 0);
4674 s_offs += surf->u.gfx9.stencil_offset;
4675
4676 ds->db_z_info = S_028038_FORMAT(format) |
4677 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4678 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4679 S_028038_MAXMIP(iview->image->info.levels - 1) |
4680 S_028038_ZRANGE_PRECISION(1);
4681 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4682 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4683
4684 if (device->physical_device->rad_info.chip_class == GFX9) {
4685 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4686 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4687 }
4688
4689 ds->db_depth_view |= S_028008_MIPID(level);
4690 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4691 S_02801C_Y_MAX(iview->image->info.height - 1);
4692
4693 if (radv_htile_enabled(iview->image, level)) {
4694 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4695
4696 if (radv_image_is_tc_compat_htile(iview->image)) {
4697 unsigned max_zplanes =
4698 radv_calc_decompress_on_z_planes(device, iview);
4699
4700 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4701
4702 if (device->physical_device->rad_info.chip_class >= GFX10) {
4703 ds->db_z_info |= S_028040_ITERATE_FLUSH(1);
4704 ds->db_stencil_info |= S_028044_ITERATE_FLUSH(1);
4705 } else {
4706 ds->db_z_info |= S_028038_ITERATE_FLUSH(1);
4707 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4708 }
4709 }
4710
4711 if (!surf->has_stencil)
4712 /* Use all of the htile_buffer for depth if there's no stencil. */
4713 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4714 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4715 iview->image->htile_offset;
4716 ds->db_htile_data_base = va >> 8;
4717 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4718 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned);
4719
4720 if (device->physical_device->rad_info.chip_class == GFX9) {
4721 ds->db_htile_surface |= S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4722 }
4723 }
4724 } else {
4725 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4726
4727 if (stencil_only)
4728 level_info = &surf->u.legacy.stencil_level[level];
4729
4730 z_offs += surf->u.legacy.level[level].offset;
4731 s_offs += surf->u.legacy.stencil_level[level].offset;
4732
4733 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4734 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4735 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4736
4737 if (iview->image->info.samples > 1)
4738 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4739
4740 if (device->physical_device->rad_info.chip_class >= GFX7) {
4741 struct radeon_info *info = &device->physical_device->rad_info;
4742 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4743 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4744 unsigned macro_index = surf->u.legacy.macro_tile_index;
4745 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4746 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4747 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4748
4749 if (stencil_only)
4750 tile_mode = stencil_tile_mode;
4751
4752 ds->db_depth_info |=
4753 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4754 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4755 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4756 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4757 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4758 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4759 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4760 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4761 } else {
4762 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4763 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4764 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4765 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4766 if (stencil_only)
4767 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4768 }
4769
4770 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4771 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4772 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4773
4774 if (radv_htile_enabled(iview->image, level)) {
4775 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4776
4777 if (!surf->has_stencil &&
4778 !radv_image_is_tc_compat_htile(iview->image))
4779 /* Use all of the htile_buffer for depth if there's no stencil. */
4780 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4781
4782 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4783 iview->image->htile_offset;
4784 ds->db_htile_data_base = va >> 8;
4785 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4786
4787 if (radv_image_is_tc_compat_htile(iview->image)) {
4788 unsigned max_zplanes =
4789 radv_calc_decompress_on_z_planes(device, iview);
4790
4791 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4792 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4793 }
4794 }
4795 }
4796
4797 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4798 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4799 }
4800
4801 VkResult radv_CreateFramebuffer(
4802 VkDevice _device,
4803 const VkFramebufferCreateInfo* pCreateInfo,
4804 const VkAllocationCallbacks* pAllocator,
4805 VkFramebuffer* pFramebuffer)
4806 {
4807 RADV_FROM_HANDLE(radv_device, device, _device);
4808 struct radv_framebuffer *framebuffer;
4809
4810 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4811
4812 size_t size = sizeof(*framebuffer) +
4813 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4814 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4815 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4816 if (framebuffer == NULL)
4817 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4818
4819 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4820 framebuffer->width = pCreateInfo->width;
4821 framebuffer->height = pCreateInfo->height;
4822 framebuffer->layers = pCreateInfo->layers;
4823 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4824 VkImageView _iview = pCreateInfo->pAttachments[i];
4825 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4826 framebuffer->attachments[i].attachment = iview;
4827 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4828 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4829 } else {
4830 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4831 }
4832 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4833 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4834 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4835 }
4836
4837 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4838 return VK_SUCCESS;
4839 }
4840
4841 void radv_DestroyFramebuffer(
4842 VkDevice _device,
4843 VkFramebuffer _fb,
4844 const VkAllocationCallbacks* pAllocator)
4845 {
4846 RADV_FROM_HANDLE(radv_device, device, _device);
4847 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4848
4849 if (!fb)
4850 return;
4851 vk_free2(&device->alloc, pAllocator, fb);
4852 }
4853
4854 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4855 {
4856 switch (address_mode) {
4857 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4858 return V_008F30_SQ_TEX_WRAP;
4859 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4860 return V_008F30_SQ_TEX_MIRROR;
4861 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4862 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4863 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4864 return V_008F30_SQ_TEX_CLAMP_BORDER;
4865 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4866 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4867 default:
4868 unreachable("illegal tex wrap mode");
4869 break;
4870 }
4871 }
4872
4873 static unsigned
4874 radv_tex_compare(VkCompareOp op)
4875 {
4876 switch (op) {
4877 case VK_COMPARE_OP_NEVER:
4878 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4879 case VK_COMPARE_OP_LESS:
4880 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4881 case VK_COMPARE_OP_EQUAL:
4882 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4883 case VK_COMPARE_OP_LESS_OR_EQUAL:
4884 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4885 case VK_COMPARE_OP_GREATER:
4886 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4887 case VK_COMPARE_OP_NOT_EQUAL:
4888 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4889 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4890 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4891 case VK_COMPARE_OP_ALWAYS:
4892 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4893 default:
4894 unreachable("illegal compare mode");
4895 break;
4896 }
4897 }
4898
4899 static unsigned
4900 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4901 {
4902 switch (filter) {
4903 case VK_FILTER_NEAREST:
4904 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4905 V_008F38_SQ_TEX_XY_FILTER_POINT);
4906 case VK_FILTER_LINEAR:
4907 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4908 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4909 case VK_FILTER_CUBIC_IMG:
4910 default:
4911 fprintf(stderr, "illegal texture filter");
4912 return 0;
4913 }
4914 }
4915
4916 static unsigned
4917 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4918 {
4919 switch (mode) {
4920 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4921 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4922 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4923 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4924 default:
4925 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4926 }
4927 }
4928
4929 static unsigned
4930 radv_tex_bordercolor(VkBorderColor bcolor)
4931 {
4932 switch (bcolor) {
4933 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4934 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4935 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4936 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4937 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4938 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4939 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4940 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4941 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4942 default:
4943 break;
4944 }
4945 return 0;
4946 }
4947
4948 static unsigned
4949 radv_tex_aniso_filter(unsigned filter)
4950 {
4951 if (filter < 2)
4952 return 0;
4953 if (filter < 4)
4954 return 1;
4955 if (filter < 8)
4956 return 2;
4957 if (filter < 16)
4958 return 3;
4959 return 4;
4960 }
4961
4962 static unsigned
4963 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4964 {
4965 switch (mode) {
4966 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4967 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4968 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4969 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4970 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4971 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4972 default:
4973 break;
4974 }
4975 return 0;
4976 }
4977
4978 static uint32_t
4979 radv_get_max_anisotropy(struct radv_device *device,
4980 const VkSamplerCreateInfo *pCreateInfo)
4981 {
4982 if (device->force_aniso >= 0)
4983 return device->force_aniso;
4984
4985 if (pCreateInfo->anisotropyEnable &&
4986 pCreateInfo->maxAnisotropy > 1.0f)
4987 return (uint32_t)pCreateInfo->maxAnisotropy;
4988
4989 return 0;
4990 }
4991
4992 static void
4993 radv_init_sampler(struct radv_device *device,
4994 struct radv_sampler *sampler,
4995 const VkSamplerCreateInfo *pCreateInfo)
4996 {
4997 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4998 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4999 bool compat_mode = device->physical_device->rad_info.chip_class == GFX8 ||
5000 device->physical_device->rad_info.chip_class == GFX9;
5001 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
5002
5003 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
5004 vk_find_struct_const(pCreateInfo->pNext,
5005 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
5006 if (sampler_reduction)
5007 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
5008
5009 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
5010 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
5011 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
5012 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
5013 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
5014 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
5015 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
5016 S_008F30_ANISO_BIAS(max_aniso_ratio) |
5017 S_008F30_DISABLE_CUBE_WRAP(0) |
5018 S_008F30_COMPAT_MODE(compat_mode) |
5019 S_008F30_FILTER_MODE(filter_mode));
5020 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
5021 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
5022 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
5023 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
5024 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
5025 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
5026 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
5027 S_008F38_MIP_POINT_PRECLAMP(0));
5028 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
5029 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
5030
5031 if (device->physical_device->rad_info.chip_class >= GFX10) {
5032 sampler->state[2] |= S_008F38_ANISO_OVERRIDE_GFX10(1);
5033 } else {
5034 sampler->state[2] |=
5035 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= GFX8) |
5036 S_008F38_FILTER_PREC_FIX(1) |
5037 S_008F38_ANISO_OVERRIDE_GFX6(device->physical_device->rad_info.chip_class >= GFX8);
5038 }
5039 }
5040
5041 VkResult radv_CreateSampler(
5042 VkDevice _device,
5043 const VkSamplerCreateInfo* pCreateInfo,
5044 const VkAllocationCallbacks* pAllocator,
5045 VkSampler* pSampler)
5046 {
5047 RADV_FROM_HANDLE(radv_device, device, _device);
5048 struct radv_sampler *sampler;
5049
5050 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
5051 vk_find_struct_const(pCreateInfo->pNext,
5052 SAMPLER_YCBCR_CONVERSION_INFO);
5053
5054 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
5055
5056 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
5057 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5058 if (!sampler)
5059 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5060
5061 radv_init_sampler(device, sampler, pCreateInfo);
5062
5063 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
5064 *pSampler = radv_sampler_to_handle(sampler);
5065
5066 return VK_SUCCESS;
5067 }
5068
5069 void radv_DestroySampler(
5070 VkDevice _device,
5071 VkSampler _sampler,
5072 const VkAllocationCallbacks* pAllocator)
5073 {
5074 RADV_FROM_HANDLE(radv_device, device, _device);
5075 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
5076
5077 if (!sampler)
5078 return;
5079 vk_free2(&device->alloc, pAllocator, sampler);
5080 }
5081
5082 /* vk_icd.h does not declare this function, so we declare it here to
5083 * suppress Wmissing-prototypes.
5084 */
5085 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5086 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
5087
5088 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
5089 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
5090 {
5091 /* For the full details on loader interface versioning, see
5092 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
5093 * What follows is a condensed summary, to help you navigate the large and
5094 * confusing official doc.
5095 *
5096 * - Loader interface v0 is incompatible with later versions. We don't
5097 * support it.
5098 *
5099 * - In loader interface v1:
5100 * - The first ICD entrypoint called by the loader is
5101 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
5102 * entrypoint.
5103 * - The ICD must statically expose no other Vulkan symbol unless it is
5104 * linked with -Bsymbolic.
5105 * - Each dispatchable Vulkan handle created by the ICD must be
5106 * a pointer to a struct whose first member is VK_LOADER_DATA. The
5107 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
5108 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
5109 * vkDestroySurfaceKHR(). The ICD must be capable of working with
5110 * such loader-managed surfaces.
5111 *
5112 * - Loader interface v2 differs from v1 in:
5113 * - The first ICD entrypoint called by the loader is
5114 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
5115 * statically expose this entrypoint.
5116 *
5117 * - Loader interface v3 differs from v2 in:
5118 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
5119 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
5120 * because the loader no longer does so.
5121 */
5122 *pSupportedVersion = MIN2(*pSupportedVersion, 4u);
5123 return VK_SUCCESS;
5124 }
5125
5126 VkResult radv_GetMemoryFdKHR(VkDevice _device,
5127 const VkMemoryGetFdInfoKHR *pGetFdInfo,
5128 int *pFD)
5129 {
5130 RADV_FROM_HANDLE(radv_device, device, _device);
5131 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
5132
5133 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
5134
5135 /* At the moment, we support only the below handle types. */
5136 assert(pGetFdInfo->handleType ==
5137 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
5138 pGetFdInfo->handleType ==
5139 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
5140
5141 bool ret = radv_get_memory_fd(device, memory, pFD);
5142 if (ret == false)
5143 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
5144 return VK_SUCCESS;
5145 }
5146
5147 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
5148 VkExternalMemoryHandleTypeFlagBits handleType,
5149 int fd,
5150 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
5151 {
5152 RADV_FROM_HANDLE(radv_device, device, _device);
5153
5154 switch (handleType) {
5155 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
5156 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
5157 return VK_SUCCESS;
5158
5159 default:
5160 /* The valid usage section for this function says:
5161 *
5162 * "handleType must not be one of the handle types defined as
5163 * opaque."
5164 *
5165 * So opaque handle types fall into the default "unsupported" case.
5166 */
5167 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5168 }
5169 }
5170
5171 static VkResult radv_import_opaque_fd(struct radv_device *device,
5172 int fd,
5173 uint32_t *syncobj)
5174 {
5175 uint32_t syncobj_handle = 0;
5176 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
5177 if (ret != 0)
5178 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5179
5180 if (*syncobj)
5181 device->ws->destroy_syncobj(device->ws, *syncobj);
5182
5183 *syncobj = syncobj_handle;
5184 close(fd);
5185
5186 return VK_SUCCESS;
5187 }
5188
5189 static VkResult radv_import_sync_fd(struct radv_device *device,
5190 int fd,
5191 uint32_t *syncobj)
5192 {
5193 /* If we create a syncobj we do it locally so that if we have an error, we don't
5194 * leave a syncobj in an undetermined state in the fence. */
5195 uint32_t syncobj_handle = *syncobj;
5196 if (!syncobj_handle) {
5197 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
5198 if (ret) {
5199 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5200 }
5201 }
5202
5203 if (fd == -1) {
5204 device->ws->signal_syncobj(device->ws, syncobj_handle);
5205 } else {
5206 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5207 if (ret != 0)
5208 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5209 }
5210
5211 *syncobj = syncobj_handle;
5212 if (fd != -1)
5213 close(fd);
5214
5215 return VK_SUCCESS;
5216 }
5217
5218 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5219 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5220 {
5221 RADV_FROM_HANDLE(radv_device, device, _device);
5222 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5223 uint32_t *syncobj_dst = NULL;
5224
5225 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5226 syncobj_dst = &sem->temp_syncobj;
5227 } else {
5228 syncobj_dst = &sem->syncobj;
5229 }
5230
5231 switch(pImportSemaphoreFdInfo->handleType) {
5232 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5233 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5234 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5235 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5236 default:
5237 unreachable("Unhandled semaphore handle type");
5238 }
5239 }
5240
5241 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5242 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5243 int *pFd)
5244 {
5245 RADV_FROM_HANDLE(radv_device, device, _device);
5246 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5247 int ret;
5248 uint32_t syncobj_handle;
5249
5250 if (sem->temp_syncobj)
5251 syncobj_handle = sem->temp_syncobj;
5252 else
5253 syncobj_handle = sem->syncobj;
5254
5255 switch(pGetFdInfo->handleType) {
5256 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5257 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5258 break;
5259 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5260 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5261 if (!ret) {
5262 if (sem->temp_syncobj) {
5263 close (sem->temp_syncobj);
5264 sem->temp_syncobj = 0;
5265 } else {
5266 device->ws->reset_syncobj(device->ws, syncobj_handle);
5267 }
5268 }
5269 break;
5270 default:
5271 unreachable("Unhandled semaphore handle type");
5272 }
5273
5274 if (ret)
5275 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5276 return VK_SUCCESS;
5277 }
5278
5279 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5280 VkPhysicalDevice physicalDevice,
5281 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5282 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5283 {
5284 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5285
5286 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5287 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5288 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5289 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5290 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5291 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5292 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5293 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5294 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5295 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5296 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5297 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5298 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5299 } else {
5300 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5301 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5302 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5303 }
5304 }
5305
5306 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5307 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5308 {
5309 RADV_FROM_HANDLE(radv_device, device, _device);
5310 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5311 uint32_t *syncobj_dst = NULL;
5312
5313
5314 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5315 syncobj_dst = &fence->temp_syncobj;
5316 } else {
5317 syncobj_dst = &fence->syncobj;
5318 }
5319
5320 switch(pImportFenceFdInfo->handleType) {
5321 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5322 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5323 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5324 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5325 default:
5326 unreachable("Unhandled fence handle type");
5327 }
5328 }
5329
5330 VkResult radv_GetFenceFdKHR(VkDevice _device,
5331 const VkFenceGetFdInfoKHR *pGetFdInfo,
5332 int *pFd)
5333 {
5334 RADV_FROM_HANDLE(radv_device, device, _device);
5335 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5336 int ret;
5337 uint32_t syncobj_handle;
5338
5339 if (fence->temp_syncobj)
5340 syncobj_handle = fence->temp_syncobj;
5341 else
5342 syncobj_handle = fence->syncobj;
5343
5344 switch(pGetFdInfo->handleType) {
5345 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5346 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5347 break;
5348 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5349 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5350 if (!ret) {
5351 if (fence->temp_syncobj) {
5352 close (fence->temp_syncobj);
5353 fence->temp_syncobj = 0;
5354 } else {
5355 device->ws->reset_syncobj(device->ws, syncobj_handle);
5356 }
5357 }
5358 break;
5359 default:
5360 unreachable("Unhandled fence handle type");
5361 }
5362
5363 if (ret)
5364 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5365 return VK_SUCCESS;
5366 }
5367
5368 void radv_GetPhysicalDeviceExternalFenceProperties(
5369 VkPhysicalDevice physicalDevice,
5370 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5371 VkExternalFenceProperties *pExternalFenceProperties)
5372 {
5373 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5374
5375 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5376 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5377 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5378 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5379 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5380 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5381 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5382 } else {
5383 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5384 pExternalFenceProperties->compatibleHandleTypes = 0;
5385 pExternalFenceProperties->externalFenceFeatures = 0;
5386 }
5387 }
5388
5389 VkResult
5390 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5391 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5392 const VkAllocationCallbacks* pAllocator,
5393 VkDebugReportCallbackEXT* pCallback)
5394 {
5395 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5396 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5397 pCreateInfo, pAllocator, &instance->alloc,
5398 pCallback);
5399 }
5400
5401 void
5402 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5403 VkDebugReportCallbackEXT _callback,
5404 const VkAllocationCallbacks* pAllocator)
5405 {
5406 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5407 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5408 _callback, pAllocator, &instance->alloc);
5409 }
5410
5411 void
5412 radv_DebugReportMessageEXT(VkInstance _instance,
5413 VkDebugReportFlagsEXT flags,
5414 VkDebugReportObjectTypeEXT objectType,
5415 uint64_t object,
5416 size_t location,
5417 int32_t messageCode,
5418 const char* pLayerPrefix,
5419 const char* pMessage)
5420 {
5421 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5422 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5423 object, location, messageCode, pLayerPrefix, pMessage);
5424 }
5425
5426 void
5427 radv_GetDeviceGroupPeerMemoryFeatures(
5428 VkDevice device,
5429 uint32_t heapIndex,
5430 uint32_t localDeviceIndex,
5431 uint32_t remoteDeviceIndex,
5432 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5433 {
5434 assert(localDeviceIndex == remoteDeviceIndex);
5435
5436 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5437 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5438 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5439 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5440 }
5441
5442 static const VkTimeDomainEXT radv_time_domains[] = {
5443 VK_TIME_DOMAIN_DEVICE_EXT,
5444 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5445 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5446 };
5447
5448 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5449 VkPhysicalDevice physicalDevice,
5450 uint32_t *pTimeDomainCount,
5451 VkTimeDomainEXT *pTimeDomains)
5452 {
5453 int d;
5454 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5455
5456 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5457 vk_outarray_append(&out, i) {
5458 *i = radv_time_domains[d];
5459 }
5460 }
5461
5462 return vk_outarray_status(&out);
5463 }
5464
5465 static uint64_t
5466 radv_clock_gettime(clockid_t clock_id)
5467 {
5468 struct timespec current;
5469 int ret;
5470
5471 ret = clock_gettime(clock_id, &current);
5472 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5473 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5474 if (ret < 0)
5475 return 0;
5476
5477 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5478 }
5479
5480 VkResult radv_GetCalibratedTimestampsEXT(
5481 VkDevice _device,
5482 uint32_t timestampCount,
5483 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5484 uint64_t *pTimestamps,
5485 uint64_t *pMaxDeviation)
5486 {
5487 RADV_FROM_HANDLE(radv_device, device, _device);
5488 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5489 int d;
5490 uint64_t begin, end;
5491 uint64_t max_clock_period = 0;
5492
5493 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5494
5495 for (d = 0; d < timestampCount; d++) {
5496 switch (pTimestampInfos[d].timeDomain) {
5497 case VK_TIME_DOMAIN_DEVICE_EXT:
5498 pTimestamps[d] = device->ws->query_value(device->ws,
5499 RADEON_TIMESTAMP);
5500 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5501 max_clock_period = MAX2(max_clock_period, device_period);
5502 break;
5503 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5504 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5505 max_clock_period = MAX2(max_clock_period, 1);
5506 break;
5507
5508 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5509 pTimestamps[d] = begin;
5510 break;
5511 default:
5512 pTimestamps[d] = 0;
5513 break;
5514 }
5515 }
5516
5517 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5518
5519 /*
5520 * The maximum deviation is the sum of the interval over which we
5521 * perform the sampling and the maximum period of any sampled
5522 * clock. That's because the maximum skew between any two sampled
5523 * clock edges is when the sampled clock with the largest period is
5524 * sampled at the end of that period but right at the beginning of the
5525 * sampling interval and some other clock is sampled right at the
5526 * begining of its sampling period and right at the end of the
5527 * sampling interval. Let's assume the GPU has the longest clock
5528 * period and that the application is sampling GPU and monotonic:
5529 *
5530 * s e
5531 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5532 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5533 *
5534 * g
5535 * 0 1 2 3
5536 * GPU -----_____-----_____-----_____-----_____
5537 *
5538 * m
5539 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5540 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5541 *
5542 * Interval <----------------->
5543 * Deviation <-------------------------->
5544 *
5545 * s = read(raw) 2
5546 * g = read(GPU) 1
5547 * m = read(monotonic) 2
5548 * e = read(raw) b
5549 *
5550 * We round the sample interval up by one tick to cover sampling error
5551 * in the interval clock
5552 */
5553
5554 uint64_t sample_interval = end - begin + 1;
5555
5556 *pMaxDeviation = sample_interval + max_clock_period;
5557
5558 return VK_SUCCESS;
5559 }
5560
5561 void radv_GetPhysicalDeviceMultisamplePropertiesEXT(
5562 VkPhysicalDevice physicalDevice,
5563 VkSampleCountFlagBits samples,
5564 VkMultisamplePropertiesEXT* pMultisampleProperties)
5565 {
5566 if (samples & (VK_SAMPLE_COUNT_2_BIT |
5567 VK_SAMPLE_COUNT_4_BIT |
5568 VK_SAMPLE_COUNT_8_BIT)) {
5569 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 2, 2 };
5570 } else {
5571 pMultisampleProperties->maxSampleLocationGridSize = (VkExtent2D){ 0, 0 };
5572 }
5573 }