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radv: detect command buffers that do no work and drop them (v2)
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "radv_cs.h"
36 #include "util/strtod.h"
37
38 #include <xf86drm.h>
39 #include <amdgpu.h>
40 #include <amdgpu_drm.h>
41 #include "amdgpu_id.h"
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "util/debug.h"
47 struct radv_dispatch_table dtable;
48
49 static int
50 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
51 {
52 Dl_info info;
53 struct stat st;
54 if (!dladdr(ptr, &info) || !info.dli_fname) {
55 return -1;
56 }
57 if (stat(info.dli_fname, &st)) {
58 return -1;
59 }
60 *timestamp = st.st_mtim.tv_sec;
61 return 0;
62 }
63
64 static int
65 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
66 {
67 uint32_t mesa_timestamp, llvm_timestamp;
68 uint16_t f = family;
69 memset(uuid, 0, VK_UUID_SIZE);
70 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
71 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
72 return -1;
73
74 memcpy(uuid, &mesa_timestamp, 4);
75 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
76 memcpy((char*)uuid + 8, &f, 2);
77 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
78 return 0;
79 }
80
81 static const VkExtensionProperties instance_extensions[] = {
82 {
83 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
84 .specVersion = 25,
85 },
86 #ifdef VK_USE_PLATFORM_XCB_KHR
87 {
88 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
89 .specVersion = 6,
90 },
91 #endif
92 #ifdef VK_USE_PLATFORM_XLIB_KHR
93 {
94 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
95 .specVersion = 6,
96 },
97 #endif
98 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
99 {
100 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
101 .specVersion = 5,
102 },
103 #endif
104 };
105
106 static const VkExtensionProperties common_device_extensions[] = {
107 {
108 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
109 .specVersion = 1,
110 },
111 {
112 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
113 .specVersion = 1,
114 },
115 {
116 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
117 .specVersion = 68,
118 },
119 {
120 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
129 .specVersion = 1,
130 },
131 };
132
133 static VkResult
134 radv_extensions_register(struct radv_instance *instance,
135 struct radv_extensions *extensions,
136 const VkExtensionProperties *new_ext,
137 uint32_t num_ext)
138 {
139 size_t new_size;
140 VkExtensionProperties *new_ptr;
141
142 assert(new_ext && num_ext > 0);
143
144 if (!new_ext)
145 return VK_ERROR_INITIALIZATION_FAILED;
146
147 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
148 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
149 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
150
151 /* Old array continues to be valid, update nothing */
152 if (!new_ptr)
153 return VK_ERROR_OUT_OF_HOST_MEMORY;
154
155 memcpy(&new_ptr[extensions->num_ext], new_ext,
156 num_ext * sizeof(VkExtensionProperties));
157 extensions->ext_array = new_ptr;
158 extensions->num_ext += num_ext;
159
160 return VK_SUCCESS;
161 }
162
163 static void
164 radv_extensions_finish(struct radv_instance *instance,
165 struct radv_extensions *extensions)
166 {
167 assert(extensions);
168
169 if (!extensions)
170 radv_loge("Attemted to free invalid extension struct\n");
171
172 if (extensions->ext_array)
173 vk_free(&instance->alloc, extensions->ext_array);
174 }
175
176 static bool
177 is_extension_enabled(const VkExtensionProperties *extensions,
178 size_t num_ext,
179 const char *name)
180 {
181 assert(extensions && name);
182
183 for (uint32_t i = 0; i < num_ext; i++) {
184 if (strcmp(name, extensions[i].extensionName) == 0)
185 return true;
186 }
187
188 return false;
189 }
190
191 static VkResult
192 radv_physical_device_init(struct radv_physical_device *device,
193 struct radv_instance *instance,
194 const char *path)
195 {
196 VkResult result;
197 drmVersionPtr version;
198 int fd;
199
200 fd = open(path, O_RDWR | O_CLOEXEC);
201 if (fd < 0)
202 return VK_ERROR_INCOMPATIBLE_DRIVER;
203
204 version = drmGetVersion(fd);
205 if (!version) {
206 close(fd);
207 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
208 "failed to get version %s: %m", path);
209 }
210
211 if (strcmp(version->name, "amdgpu")) {
212 drmFreeVersion(version);
213 close(fd);
214 return VK_ERROR_INCOMPATIBLE_DRIVER;
215 }
216 drmFreeVersion(version);
217
218 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
219 device->instance = instance;
220 assert(strlen(path) < ARRAY_SIZE(device->path));
221 strncpy(device->path, path, ARRAY_SIZE(device->path));
222
223 device->ws = radv_amdgpu_winsys_create(fd);
224 if (!device->ws) {
225 result = VK_ERROR_INCOMPATIBLE_DRIVER;
226 goto fail;
227 }
228 device->ws->query_info(device->ws, &device->rad_info);
229 result = radv_init_wsi(device);
230 if (result != VK_SUCCESS) {
231 device->ws->destroy(device->ws);
232 goto fail;
233 }
234
235 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
236 radv_finish_wsi(device);
237 device->ws->destroy(device->ws);
238 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
239 "cannot generate UUID");
240 goto fail;
241 }
242
243 result = radv_extensions_register(instance,
244 &device->extensions,
245 common_device_extensions,
246 ARRAY_SIZE(common_device_extensions));
247 if (result != VK_SUCCESS)
248 goto fail;
249
250 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
251 device->name = device->rad_info.name;
252 close(fd);
253 return VK_SUCCESS;
254
255 fail:
256 close(fd);
257 return result;
258 }
259
260 static void
261 radv_physical_device_finish(struct radv_physical_device *device)
262 {
263 radv_extensions_finish(device->instance, &device->extensions);
264 radv_finish_wsi(device);
265 device->ws->destroy(device->ws);
266 }
267
268
269 static void *
270 default_alloc_func(void *pUserData, size_t size, size_t align,
271 VkSystemAllocationScope allocationScope)
272 {
273 return malloc(size);
274 }
275
276 static void *
277 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
278 size_t align, VkSystemAllocationScope allocationScope)
279 {
280 return realloc(pOriginal, size);
281 }
282
283 static void
284 default_free_func(void *pUserData, void *pMemory)
285 {
286 free(pMemory);
287 }
288
289 static const VkAllocationCallbacks default_alloc = {
290 .pUserData = NULL,
291 .pfnAllocation = default_alloc_func,
292 .pfnReallocation = default_realloc_func,
293 .pfnFree = default_free_func,
294 };
295
296 static const struct debug_control radv_debug_options[] = {
297 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
298 {"nodcc", RADV_DEBUG_NO_DCC},
299 {"shaders", RADV_DEBUG_DUMP_SHADERS},
300 {"nocache", RADV_DEBUG_NO_CACHE},
301 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
302 {"nohiz", RADV_DEBUG_NO_HIZ},
303 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
304 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
305 {NULL, 0}
306 };
307
308 VkResult radv_CreateInstance(
309 const VkInstanceCreateInfo* pCreateInfo,
310 const VkAllocationCallbacks* pAllocator,
311 VkInstance* pInstance)
312 {
313 struct radv_instance *instance;
314
315 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
316
317 uint32_t client_version;
318 if (pCreateInfo->pApplicationInfo &&
319 pCreateInfo->pApplicationInfo->apiVersion != 0) {
320 client_version = pCreateInfo->pApplicationInfo->apiVersion;
321 } else {
322 client_version = VK_MAKE_VERSION(1, 0, 0);
323 }
324
325 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
326 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
327 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
328 "Client requested version %d.%d.%d",
329 VK_VERSION_MAJOR(client_version),
330 VK_VERSION_MINOR(client_version),
331 VK_VERSION_PATCH(client_version));
332 }
333
334 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
335 if (!is_extension_enabled(instance_extensions,
336 ARRAY_SIZE(instance_extensions),
337 pCreateInfo->ppEnabledExtensionNames[i]))
338 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
339 }
340
341 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
342 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
343 if (!instance)
344 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
345
346 memset(instance, 0, sizeof(*instance));
347
348 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
349
350 if (pAllocator)
351 instance->alloc = *pAllocator;
352 else
353 instance->alloc = default_alloc;
354
355 instance->apiVersion = client_version;
356 instance->physicalDeviceCount = -1;
357
358 _mesa_locale_init();
359
360 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
361
362 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
363 radv_debug_options);
364
365 *pInstance = radv_instance_to_handle(instance);
366
367 return VK_SUCCESS;
368 }
369
370 void radv_DestroyInstance(
371 VkInstance _instance,
372 const VkAllocationCallbacks* pAllocator)
373 {
374 RADV_FROM_HANDLE(radv_instance, instance, _instance);
375
376 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
377 radv_physical_device_finish(instance->physicalDevices + i);
378 }
379
380 VG(VALGRIND_DESTROY_MEMPOOL(instance));
381
382 _mesa_locale_fini();
383
384 vk_free(&instance->alloc, instance);
385 }
386
387 VkResult radv_EnumeratePhysicalDevices(
388 VkInstance _instance,
389 uint32_t* pPhysicalDeviceCount,
390 VkPhysicalDevice* pPhysicalDevices)
391 {
392 RADV_FROM_HANDLE(radv_instance, instance, _instance);
393 VkResult result;
394
395 if (instance->physicalDeviceCount < 0) {
396 char path[20];
397 instance->physicalDeviceCount = 0;
398 for (unsigned i = 0; i < RADV_MAX_DRM_DEVICES; i++) {
399 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
400 result = radv_physical_device_init(instance->physicalDevices +
401 instance->physicalDeviceCount,
402 instance, path);
403 if (result == VK_SUCCESS)
404 ++instance->physicalDeviceCount;
405 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
406 return result;
407 }
408 }
409
410 if (!pPhysicalDevices) {
411 *pPhysicalDeviceCount = instance->physicalDeviceCount;
412 } else {
413 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
414 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
415 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
416 }
417
418 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
419 : VK_SUCCESS;
420 }
421
422 void radv_GetPhysicalDeviceFeatures(
423 VkPhysicalDevice physicalDevice,
424 VkPhysicalDeviceFeatures* pFeatures)
425 {
426 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
427
428 memset(pFeatures, 0, sizeof(*pFeatures));
429
430 *pFeatures = (VkPhysicalDeviceFeatures) {
431 .robustBufferAccess = true,
432 .fullDrawIndexUint32 = true,
433 .imageCubeArray = true,
434 .independentBlend = true,
435 .geometryShader = true,
436 .tessellationShader = false,
437 .sampleRateShading = false,
438 .dualSrcBlend = true,
439 .logicOp = true,
440 .multiDrawIndirect = true,
441 .drawIndirectFirstInstance = true,
442 .depthClamp = true,
443 .depthBiasClamp = true,
444 .fillModeNonSolid = true,
445 .depthBounds = true,
446 .wideLines = true,
447 .largePoints = true,
448 .alphaToOne = true,
449 .multiViewport = true,
450 .samplerAnisotropy = true,
451 .textureCompressionETC2 = false,
452 .textureCompressionASTC_LDR = false,
453 .textureCompressionBC = true,
454 .occlusionQueryPrecise = true,
455 .pipelineStatisticsQuery = false,
456 .vertexPipelineStoresAndAtomics = true,
457 .fragmentStoresAndAtomics = true,
458 .shaderTessellationAndGeometryPointSize = true,
459 .shaderImageGatherExtended = true,
460 .shaderStorageImageExtendedFormats = true,
461 .shaderStorageImageMultisample = false,
462 .shaderUniformBufferArrayDynamicIndexing = true,
463 .shaderSampledImageArrayDynamicIndexing = true,
464 .shaderStorageBufferArrayDynamicIndexing = true,
465 .shaderStorageImageArrayDynamicIndexing = true,
466 .shaderStorageImageReadWithoutFormat = false,
467 .shaderStorageImageWriteWithoutFormat = false,
468 .shaderClipDistance = true,
469 .shaderCullDistance = true,
470 .shaderFloat64 = true,
471 .shaderInt64 = false,
472 .shaderInt16 = false,
473 .alphaToOne = true,
474 .variableMultisampleRate = false,
475 .inheritedQueries = false,
476 };
477 }
478
479 void radv_GetPhysicalDeviceFeatures2KHR(
480 VkPhysicalDevice physicalDevice,
481 VkPhysicalDeviceFeatures2KHR *pFeatures)
482 {
483 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
484 }
485
486 void radv_GetPhysicalDeviceProperties(
487 VkPhysicalDevice physicalDevice,
488 VkPhysicalDeviceProperties* pProperties)
489 {
490 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
491 VkSampleCountFlags sample_counts = 0xf;
492 VkPhysicalDeviceLimits limits = {
493 .maxImageDimension1D = (1 << 14),
494 .maxImageDimension2D = (1 << 14),
495 .maxImageDimension3D = (1 << 11),
496 .maxImageDimensionCube = (1 << 14),
497 .maxImageArrayLayers = (1 << 11),
498 .maxTexelBufferElements = 128 * 1024 * 1024,
499 .maxUniformBufferRange = UINT32_MAX,
500 .maxStorageBufferRange = UINT32_MAX,
501 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
502 .maxMemoryAllocationCount = UINT32_MAX,
503 .maxSamplerAllocationCount = 64 * 1024,
504 .bufferImageGranularity = 64, /* A cache line */
505 .sparseAddressSpaceSize = 0,
506 .maxBoundDescriptorSets = MAX_SETS,
507 .maxPerStageDescriptorSamplers = 64,
508 .maxPerStageDescriptorUniformBuffers = 64,
509 .maxPerStageDescriptorStorageBuffers = 64,
510 .maxPerStageDescriptorSampledImages = 64,
511 .maxPerStageDescriptorStorageImages = 64,
512 .maxPerStageDescriptorInputAttachments = 64,
513 .maxPerStageResources = 128,
514 .maxDescriptorSetSamplers = 256,
515 .maxDescriptorSetUniformBuffers = 256,
516 .maxDescriptorSetUniformBuffersDynamic = 256,
517 .maxDescriptorSetStorageBuffers = 256,
518 .maxDescriptorSetStorageBuffersDynamic = 256,
519 .maxDescriptorSetSampledImages = 256,
520 .maxDescriptorSetStorageImages = 256,
521 .maxDescriptorSetInputAttachments = 256,
522 .maxVertexInputAttributes = 32,
523 .maxVertexInputBindings = 32,
524 .maxVertexInputAttributeOffset = 2047,
525 .maxVertexInputBindingStride = 2048,
526 .maxVertexOutputComponents = 128,
527 .maxTessellationGenerationLevel = 0,
528 .maxTessellationPatchSize = 0,
529 .maxTessellationControlPerVertexInputComponents = 0,
530 .maxTessellationControlPerVertexOutputComponents = 0,
531 .maxTessellationControlPerPatchOutputComponents = 0,
532 .maxTessellationControlTotalOutputComponents = 0,
533 .maxTessellationEvaluationInputComponents = 0,
534 .maxTessellationEvaluationOutputComponents = 0,
535 .maxGeometryShaderInvocations = 32,
536 .maxGeometryInputComponents = 64,
537 .maxGeometryOutputComponents = 128,
538 .maxGeometryOutputVertices = 256,
539 .maxGeometryTotalOutputComponents = 1024,
540 .maxFragmentInputComponents = 128,
541 .maxFragmentOutputAttachments = 8,
542 .maxFragmentDualSrcAttachments = 1,
543 .maxFragmentCombinedOutputResources = 8,
544 .maxComputeSharedMemorySize = 32768,
545 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
546 .maxComputeWorkGroupInvocations = 2048,
547 .maxComputeWorkGroupSize = {
548 2048,
549 2048,
550 2048
551 },
552 .subPixelPrecisionBits = 4 /* FIXME */,
553 .subTexelPrecisionBits = 4 /* FIXME */,
554 .mipmapPrecisionBits = 4 /* FIXME */,
555 .maxDrawIndexedIndexValue = UINT32_MAX,
556 .maxDrawIndirectCount = UINT32_MAX,
557 .maxSamplerLodBias = 16,
558 .maxSamplerAnisotropy = 16,
559 .maxViewports = MAX_VIEWPORTS,
560 .maxViewportDimensions = { (1 << 14), (1 << 14) },
561 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
562 .viewportSubPixelBits = 13, /* We take a float? */
563 .minMemoryMapAlignment = 4096, /* A page */
564 .minTexelBufferOffsetAlignment = 1,
565 .minUniformBufferOffsetAlignment = 4,
566 .minStorageBufferOffsetAlignment = 4,
567 .minTexelOffset = -32,
568 .maxTexelOffset = 31,
569 .minTexelGatherOffset = -32,
570 .maxTexelGatherOffset = 31,
571 .minInterpolationOffset = -2,
572 .maxInterpolationOffset = 2,
573 .subPixelInterpolationOffsetBits = 8,
574 .maxFramebufferWidth = (1 << 14),
575 .maxFramebufferHeight = (1 << 14),
576 .maxFramebufferLayers = (1 << 10),
577 .framebufferColorSampleCounts = sample_counts,
578 .framebufferDepthSampleCounts = sample_counts,
579 .framebufferStencilSampleCounts = sample_counts,
580 .framebufferNoAttachmentsSampleCounts = sample_counts,
581 .maxColorAttachments = MAX_RTS,
582 .sampledImageColorSampleCounts = sample_counts,
583 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
584 .sampledImageDepthSampleCounts = sample_counts,
585 .sampledImageStencilSampleCounts = sample_counts,
586 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
587 .maxSampleMaskWords = 1,
588 .timestampComputeAndGraphics = false,
589 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
590 .maxClipDistances = 8,
591 .maxCullDistances = 8,
592 .maxCombinedClipAndCullDistances = 8,
593 .discreteQueuePriorities = 1,
594 .pointSizeRange = { 0.125, 255.875 },
595 .lineWidthRange = { 0.0, 7.9921875 },
596 .pointSizeGranularity = (1.0 / 8.0),
597 .lineWidthGranularity = (1.0 / 128.0),
598 .strictLines = false, /* FINISHME */
599 .standardSampleLocations = true,
600 .optimalBufferCopyOffsetAlignment = 128,
601 .optimalBufferCopyRowPitchAlignment = 128,
602 .nonCoherentAtomSize = 64,
603 };
604
605 *pProperties = (VkPhysicalDeviceProperties) {
606 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
607 .driverVersion = 1,
608 .vendorID = 0x1002,
609 .deviceID = pdevice->rad_info.pci_id,
610 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
611 .limits = limits,
612 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
613 };
614
615 strcpy(pProperties->deviceName, pdevice->name);
616 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
617 }
618
619 void radv_GetPhysicalDeviceProperties2KHR(
620 VkPhysicalDevice physicalDevice,
621 VkPhysicalDeviceProperties2KHR *pProperties)
622 {
623 return radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
624 }
625
626 static void radv_get_physical_device_queue_family_properties(
627 struct radv_physical_device* pdevice,
628 uint32_t* pCount,
629 VkQueueFamilyProperties** pQueueFamilyProperties)
630 {
631 int num_queue_families = 1;
632 int idx;
633 if (pdevice->rad_info.compute_rings > 0 &&
634 pdevice->rad_info.chip_class >= CIK &&
635 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
636 num_queue_families++;
637
638 if (pQueueFamilyProperties == NULL) {
639 *pCount = num_queue_families;
640 return;
641 }
642
643 if (!*pCount)
644 return;
645
646 idx = 0;
647 if (*pCount >= 1) {
648 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
649 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
650 VK_QUEUE_COMPUTE_BIT |
651 VK_QUEUE_TRANSFER_BIT,
652 .queueCount = 1,
653 .timestampValidBits = 64,
654 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
655 };
656 idx++;
657 }
658
659 if (pdevice->rad_info.compute_rings > 0 &&
660 pdevice->rad_info.chip_class >= CIK &&
661 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
662 if (*pCount > idx) {
663 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
664 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
665 .queueCount = pdevice->rad_info.compute_rings,
666 .timestampValidBits = 64,
667 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
668 };
669 idx++;
670 }
671 }
672 *pCount = idx;
673 }
674
675 void radv_GetPhysicalDeviceQueueFamilyProperties(
676 VkPhysicalDevice physicalDevice,
677 uint32_t* pCount,
678 VkQueueFamilyProperties* pQueueFamilyProperties)
679 {
680 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
681 if (!pQueueFamilyProperties) {
682 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
683 return;
684 }
685 VkQueueFamilyProperties *properties[] = {
686 pQueueFamilyProperties + 0,
687 pQueueFamilyProperties + 1,
688 pQueueFamilyProperties + 2,
689 };
690 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
691 assert(*pCount <= 3);
692 }
693
694 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
695 VkPhysicalDevice physicalDevice,
696 uint32_t* pCount,
697 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
698 {
699 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
700 if (!pQueueFamilyProperties) {
701 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
702 return;
703 }
704 VkQueueFamilyProperties *properties[] = {
705 &pQueueFamilyProperties[0].queueFamilyProperties,
706 &pQueueFamilyProperties[1].queueFamilyProperties,
707 &pQueueFamilyProperties[2].queueFamilyProperties,
708 };
709 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
710 assert(*pCount <= 3);
711 }
712
713 void radv_GetPhysicalDeviceMemoryProperties(
714 VkPhysicalDevice physicalDevice,
715 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
716 {
717 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
718
719 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
720
721 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
722 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
723 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
724 .heapIndex = RADV_MEM_HEAP_VRAM,
725 };
726 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
727 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
728 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
729 .heapIndex = RADV_MEM_HEAP_GTT,
730 };
731 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
732 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
733 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
734 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
735 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
736 };
737 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
738 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
739 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
740 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
741 .heapIndex = RADV_MEM_HEAP_GTT,
742 };
743
744 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
745
746 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
747 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
748 .size = physical_device->rad_info.vram_size -
749 physical_device->rad_info.visible_vram_size,
750 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
751 };
752 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
753 .size = physical_device->rad_info.visible_vram_size,
754 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
755 };
756 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
757 .size = physical_device->rad_info.gart_size,
758 .flags = 0,
759 };
760 }
761
762 void radv_GetPhysicalDeviceMemoryProperties2KHR(
763 VkPhysicalDevice physicalDevice,
764 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
765 {
766 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
767 &pMemoryProperties->memoryProperties);
768 }
769
770 static int
771 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
772 int queue_family_index, int idx)
773 {
774 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
775 queue->device = device;
776 queue->queue_family_index = queue_family_index;
777 queue->queue_idx = idx;
778
779 queue->hw_ctx = device->ws->ctx_create(device->ws);
780 if (!queue->hw_ctx)
781 return VK_ERROR_OUT_OF_HOST_MEMORY;
782
783 return VK_SUCCESS;
784 }
785
786 static void
787 radv_queue_finish(struct radv_queue *queue)
788 {
789 if (queue->hw_ctx)
790 queue->device->ws->ctx_destroy(queue->hw_ctx);
791
792 if (queue->preamble_cs)
793 queue->device->ws->cs_destroy(queue->preamble_cs);
794 if (queue->descriptor_bo)
795 queue->device->ws->buffer_destroy(queue->descriptor_bo);
796 if (queue->scratch_bo)
797 queue->device->ws->buffer_destroy(queue->scratch_bo);
798 if (queue->esgs_ring_bo)
799 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
800 if (queue->gsvs_ring_bo)
801 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
802 if (queue->compute_scratch_bo)
803 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
804 }
805
806 static void
807 radv_device_init_gs_info(struct radv_device *device)
808 {
809 switch (device->physical_device->rad_info.family) {
810 case CHIP_OLAND:
811 case CHIP_HAINAN:
812 case CHIP_KAVERI:
813 case CHIP_KABINI:
814 case CHIP_MULLINS:
815 case CHIP_ICELAND:
816 case CHIP_CARRIZO:
817 case CHIP_STONEY:
818 device->gs_table_depth = 16;
819 return;
820 case CHIP_TAHITI:
821 case CHIP_PITCAIRN:
822 case CHIP_VERDE:
823 case CHIP_BONAIRE:
824 case CHIP_HAWAII:
825 case CHIP_TONGA:
826 case CHIP_FIJI:
827 case CHIP_POLARIS10:
828 case CHIP_POLARIS11:
829 device->gs_table_depth = 32;
830 return;
831 default:
832 unreachable("unknown GPU");
833 }
834 }
835
836 VkResult radv_CreateDevice(
837 VkPhysicalDevice physicalDevice,
838 const VkDeviceCreateInfo* pCreateInfo,
839 const VkAllocationCallbacks* pAllocator,
840 VkDevice* pDevice)
841 {
842 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
843 VkResult result;
844 struct radv_device *device;
845
846 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
847 if (!is_extension_enabled(physical_device->extensions.ext_array,
848 physical_device->extensions.num_ext,
849 pCreateInfo->ppEnabledExtensionNames[i]))
850 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
851 }
852
853 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
854 sizeof(*device), 8,
855 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
856 if (!device)
857 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
858
859 memset(device, 0, sizeof(*device));
860
861 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
862 device->instance = physical_device->instance;
863 device->physical_device = physical_device;
864
865 device->debug_flags = device->instance->debug_flags;
866
867 device->ws = physical_device->ws;
868 if (pAllocator)
869 device->alloc = *pAllocator;
870 else
871 device->alloc = physical_device->instance->alloc;
872
873 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
874 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
875 uint32_t qfi = queue_create->queueFamilyIndex;
876
877 device->queues[qfi] = vk_alloc(&device->alloc,
878 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
879 if (!device->queues[qfi]) {
880 result = VK_ERROR_OUT_OF_HOST_MEMORY;
881 goto fail;
882 }
883
884 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
885
886 device->queue_count[qfi] = queue_create->queueCount;
887
888 for (unsigned q = 0; q < queue_create->queueCount; q++) {
889 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
890 if (result != VK_SUCCESS)
891 goto fail;
892 }
893 }
894
895 #if HAVE_LLVM < 0x0400
896 device->llvm_supports_spill = false;
897 #else
898 device->llvm_supports_spill = true;
899 #endif
900
901 /* The maximum number of scratch waves. Scratch space isn't divided
902 * evenly between CUs. The number is only a function of the number of CUs.
903 * We can decrease the constant to decrease the scratch buffer size.
904 *
905 * sctx->scratch_waves must be >= the maximum posible size of
906 * 1 threadgroup, so that the hw doesn't hang from being unable
907 * to start any.
908 *
909 * The recommended value is 4 per CU at most. Higher numbers don't
910 * bring much benefit, but they still occupy chip resources (think
911 * async compute). I've seen ~2% performance difference between 4 and 32.
912 */
913 uint32_t max_threads_per_block = 2048;
914 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
915 max_threads_per_block / 64);
916
917 radv_device_init_gs_info(device);
918
919 result = radv_device_init_meta(device);
920 if (result != VK_SUCCESS)
921 goto fail;
922
923 radv_device_init_msaa(device);
924
925 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
926 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
927 switch (family) {
928 case RADV_QUEUE_GENERAL:
929 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
930 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
931 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
932 break;
933 case RADV_QUEUE_COMPUTE:
934 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
935 radeon_emit(device->empty_cs[family], 0);
936 break;
937 }
938 device->ws->cs_finalize(device->empty_cs[family]);
939 }
940
941 if (getenv("RADV_TRACE_FILE")) {
942 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
943 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
944 if (!device->trace_bo)
945 goto fail;
946
947 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
948 if (!device->trace_id_ptr)
949 goto fail;
950 }
951
952 *pDevice = radv_device_to_handle(device);
953 return VK_SUCCESS;
954
955 fail:
956 if (device->trace_bo)
957 device->ws->buffer_destroy(device->trace_bo);
958
959 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
960 for (unsigned q = 0; q < device->queue_count[i]; q++)
961 radv_queue_finish(&device->queues[i][q]);
962 if (device->queue_count[i])
963 vk_free(&device->alloc, device->queues[i]);
964 }
965
966 vk_free(&device->alloc, device);
967 return result;
968 }
969
970 void radv_DestroyDevice(
971 VkDevice _device,
972 const VkAllocationCallbacks* pAllocator)
973 {
974 RADV_FROM_HANDLE(radv_device, device, _device);
975
976 if (device->trace_bo)
977 device->ws->buffer_destroy(device->trace_bo);
978
979 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
980 for (unsigned q = 0; q < device->queue_count[i]; q++)
981 radv_queue_finish(&device->queues[i][q]);
982 if (device->queue_count[i])
983 vk_free(&device->alloc, device->queues[i]);
984 }
985 radv_device_finish_meta(device);
986
987 vk_free(&device->alloc, device);
988 }
989
990 VkResult radv_EnumerateInstanceExtensionProperties(
991 const char* pLayerName,
992 uint32_t* pPropertyCount,
993 VkExtensionProperties* pProperties)
994 {
995 if (pProperties == NULL) {
996 *pPropertyCount = ARRAY_SIZE(instance_extensions);
997 return VK_SUCCESS;
998 }
999
1000 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1001 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1002
1003 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1004 return VK_INCOMPLETE;
1005
1006 return VK_SUCCESS;
1007 }
1008
1009 VkResult radv_EnumerateDeviceExtensionProperties(
1010 VkPhysicalDevice physicalDevice,
1011 const char* pLayerName,
1012 uint32_t* pPropertyCount,
1013 VkExtensionProperties* pProperties)
1014 {
1015 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1016
1017 if (pProperties == NULL) {
1018 *pPropertyCount = pdevice->extensions.num_ext;
1019 return VK_SUCCESS;
1020 }
1021
1022 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1023 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1024
1025 if (*pPropertyCount < pdevice->extensions.num_ext)
1026 return VK_INCOMPLETE;
1027
1028 return VK_SUCCESS;
1029 }
1030
1031 VkResult radv_EnumerateInstanceLayerProperties(
1032 uint32_t* pPropertyCount,
1033 VkLayerProperties* pProperties)
1034 {
1035 if (pProperties == NULL) {
1036 *pPropertyCount = 0;
1037 return VK_SUCCESS;
1038 }
1039
1040 /* None supported at this time */
1041 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1042 }
1043
1044 VkResult radv_EnumerateDeviceLayerProperties(
1045 VkPhysicalDevice physicalDevice,
1046 uint32_t* pPropertyCount,
1047 VkLayerProperties* pProperties)
1048 {
1049 if (pProperties == NULL) {
1050 *pPropertyCount = 0;
1051 return VK_SUCCESS;
1052 }
1053
1054 /* None supported at this time */
1055 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1056 }
1057
1058 void radv_GetDeviceQueue(
1059 VkDevice _device,
1060 uint32_t queueFamilyIndex,
1061 uint32_t queueIndex,
1062 VkQueue* pQueue)
1063 {
1064 RADV_FROM_HANDLE(radv_device, device, _device);
1065
1066 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1067 }
1068
1069 static void radv_dump_trace(struct radv_device *device,
1070 struct radeon_winsys_cs *cs)
1071 {
1072 const char *filename = getenv("RADV_TRACE_FILE");
1073 FILE *f = fopen(filename, "w");
1074 if (!f) {
1075 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1076 return;
1077 }
1078
1079 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1080 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1081 fclose(f);
1082 }
1083
1084 static void
1085 fill_geom_rings(struct radv_queue *queue,
1086 uint32_t *map,
1087 uint32_t esgs_ring_size,
1088 struct radeon_winsys_bo *esgs_ring_bo,
1089 uint32_t gsvs_ring_size,
1090 struct radeon_winsys_bo *gsvs_ring_bo)
1091 {
1092 uint64_t esgs_va = 0, gsvs_va = 0;
1093 uint32_t *desc = &map[4];
1094
1095 if (esgs_ring_bo)
1096 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1097 if (gsvs_ring_bo)
1098 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1099
1100 /* stride 0, num records - size, add tid, swizzle, elsize4,
1101 index stride 64 */
1102 desc[0] = esgs_va;
1103 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1104 S_008F04_STRIDE(0) |
1105 S_008F04_SWIZZLE_ENABLE(true);
1106 desc[2] = esgs_ring_size;
1107 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1108 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1109 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1110 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1111 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1112 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1113 S_008F0C_ELEMENT_SIZE(1) |
1114 S_008F0C_INDEX_STRIDE(3) |
1115 S_008F0C_ADD_TID_ENABLE(true);
1116
1117 desc += 4;
1118 /* GS entry for ES->GS ring */
1119 /* stride 0, num records - size, elsize0,
1120 index stride 0 */
1121 desc[0] = esgs_va;
1122 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1123 S_008F04_STRIDE(0) |
1124 S_008F04_SWIZZLE_ENABLE(false);
1125 desc[2] = esgs_ring_size;
1126 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1127 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1128 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1129 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1130 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1131 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1132 S_008F0C_ELEMENT_SIZE(0) |
1133 S_008F0C_INDEX_STRIDE(0) |
1134 S_008F0C_ADD_TID_ENABLE(false);
1135
1136 desc += 4;
1137 /* VS entry for GS->VS ring */
1138 /* stride 0, num records - size, elsize0,
1139 index stride 0 */
1140 desc[0] = gsvs_va;
1141 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1142 S_008F04_STRIDE(0) |
1143 S_008F04_SWIZZLE_ENABLE(false);
1144 desc[2] = gsvs_ring_size;
1145 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1146 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1147 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1148 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1149 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1150 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1151 S_008F0C_ELEMENT_SIZE(0) |
1152 S_008F0C_INDEX_STRIDE(0) |
1153 S_008F0C_ADD_TID_ENABLE(false);
1154 desc += 4;
1155
1156 /* stride gsvs_itemsize, num records 64
1157 elsize 4, index stride 16 */
1158 /* shader will patch stride and desc[2] */
1159 desc[0] = gsvs_va;
1160 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1161 S_008F04_STRIDE(0) |
1162 S_008F04_SWIZZLE_ENABLE(true);
1163 desc[2] = 0;
1164 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1165 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1166 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1167 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1168 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1169 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1170 S_008F0C_ELEMENT_SIZE(1) |
1171 S_008F0C_INDEX_STRIDE(1) |
1172 S_008F0C_ADD_TID_ENABLE(true);
1173 }
1174
1175 static VkResult
1176 radv_get_preamble_cs(struct radv_queue *queue,
1177 uint32_t scratch_size,
1178 uint32_t compute_scratch_size,
1179 uint32_t esgs_ring_size,
1180 uint32_t gsvs_ring_size,
1181 struct radeon_winsys_cs **preamble_cs)
1182 {
1183 struct radeon_winsys_bo *scratch_bo = NULL;
1184 struct radeon_winsys_bo *descriptor_bo = NULL;
1185 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1186 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1187 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1188 struct radeon_winsys_cs *cs = NULL;
1189
1190 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size) {
1191 *preamble_cs = NULL;
1192 return VK_SUCCESS;
1193 }
1194
1195 if (scratch_size <= queue->scratch_size &&
1196 compute_scratch_size <= queue->compute_scratch_size &&
1197 esgs_ring_size <= queue->esgs_ring_size &&
1198 gsvs_ring_size <= queue->gsvs_ring_size) {
1199 *preamble_cs = queue->preamble_cs;
1200 return VK_SUCCESS;
1201 }
1202
1203 if (scratch_size > queue->scratch_size) {
1204 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1205 scratch_size,
1206 4096,
1207 RADEON_DOMAIN_VRAM,
1208 RADEON_FLAG_NO_CPU_ACCESS);
1209 if (!scratch_bo)
1210 goto fail;
1211 } else
1212 scratch_bo = queue->scratch_bo;
1213
1214 if (compute_scratch_size > queue->compute_scratch_size) {
1215 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1216 compute_scratch_size,
1217 4096,
1218 RADEON_DOMAIN_VRAM,
1219 RADEON_FLAG_NO_CPU_ACCESS);
1220 if (!compute_scratch_bo)
1221 goto fail;
1222
1223 } else
1224 compute_scratch_bo = queue->compute_scratch_bo;
1225
1226 if (esgs_ring_size > queue->esgs_ring_size) {
1227 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1228 esgs_ring_size,
1229 4096,
1230 RADEON_DOMAIN_VRAM,
1231 RADEON_FLAG_NO_CPU_ACCESS);
1232 if (!esgs_ring_bo)
1233 goto fail;
1234 } else {
1235 esgs_ring_bo = queue->esgs_ring_bo;
1236 esgs_ring_size = queue->esgs_ring_size;
1237 }
1238
1239 if (gsvs_ring_size > queue->gsvs_ring_size) {
1240 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1241 gsvs_ring_size,
1242 4096,
1243 RADEON_DOMAIN_VRAM,
1244 RADEON_FLAG_NO_CPU_ACCESS);
1245 if (!gsvs_ring_bo)
1246 goto fail;
1247 } else {
1248 gsvs_ring_bo = queue->gsvs_ring_bo;
1249 gsvs_ring_size = queue->gsvs_ring_size;
1250 }
1251
1252 if (scratch_bo != queue->scratch_bo ||
1253 esgs_ring_bo != queue->esgs_ring_bo ||
1254 gsvs_ring_bo != queue->gsvs_ring_bo) {
1255 uint32_t size = 0;
1256 if (gsvs_ring_bo || esgs_ring_bo)
1257 size = 80; /* 2 dword + 2 padding + 4 dword * 4 */
1258 else if (scratch_bo)
1259 size = 8; /* 2 dword */
1260
1261 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1262 size,
1263 4096,
1264 RADEON_DOMAIN_VRAM,
1265 RADEON_FLAG_CPU_ACCESS);
1266 if (!descriptor_bo)
1267 goto fail;
1268 } else
1269 descriptor_bo = queue->descriptor_bo;
1270
1271 cs = queue->device->ws->cs_create(queue->device->ws,
1272 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1273 if (!cs)
1274 goto fail;
1275
1276
1277 if (scratch_bo)
1278 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1279
1280 if (esgs_ring_bo)
1281 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1282
1283 if (gsvs_ring_bo)
1284 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1285
1286 if (descriptor_bo)
1287 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1288
1289 if (descriptor_bo != queue->descriptor_bo) {
1290 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1291
1292 if (scratch_bo) {
1293 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1294 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1295 S_008F04_SWIZZLE_ENABLE(1);
1296 map[0] = scratch_va;
1297 map[1] = rsrc1;
1298 }
1299
1300 if (esgs_ring_bo || gsvs_ring_bo)
1301 fill_geom_rings(queue, map, esgs_ring_size, esgs_ring_bo, gsvs_ring_size, gsvs_ring_bo);
1302
1303 queue->device->ws->buffer_unmap(descriptor_bo);
1304 }
1305
1306 if (esgs_ring_bo || gsvs_ring_bo) {
1307 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1308 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1309 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1310 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1311
1312 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1313 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1314 radeon_emit(cs, esgs_ring_size >> 8);
1315 radeon_emit(cs, gsvs_ring_size >> 8);
1316 } else {
1317 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1318 radeon_emit(cs, esgs_ring_size >> 8);
1319 radeon_emit(cs, gsvs_ring_size >> 8);
1320 }
1321 }
1322
1323 if (descriptor_bo) {
1324 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1325 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1326 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1327 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1328 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1329 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1330
1331 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1332
1333 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1334 radeon_set_sh_reg_seq(cs, regs[i], 2);
1335 radeon_emit(cs, va);
1336 radeon_emit(cs, va >> 32);
1337 }
1338 }
1339
1340 if (compute_scratch_bo) {
1341 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1342 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1343 S_008F04_SWIZZLE_ENABLE(1);
1344
1345 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1346
1347 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1348 radeon_emit(cs, scratch_va);
1349 radeon_emit(cs, rsrc1);
1350 }
1351
1352 if (!queue->device->ws->cs_finalize(cs))
1353 goto fail;
1354
1355 if (queue->preamble_cs)
1356 queue->device->ws->cs_destroy(queue->preamble_cs);
1357
1358 queue->preamble_cs = cs;
1359
1360 if (scratch_bo != queue->scratch_bo) {
1361 if (queue->scratch_bo)
1362 queue->device->ws->buffer_destroy(queue->scratch_bo);
1363 queue->scratch_bo = scratch_bo;
1364 queue->scratch_size = scratch_size;
1365 }
1366
1367 if (compute_scratch_bo != queue->compute_scratch_bo) {
1368 if (queue->compute_scratch_bo)
1369 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1370 queue->compute_scratch_bo = compute_scratch_bo;
1371 queue->compute_scratch_size = compute_scratch_size;
1372 }
1373
1374 if (esgs_ring_bo != queue->esgs_ring_bo) {
1375 if (queue->esgs_ring_bo)
1376 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1377 queue->esgs_ring_bo = esgs_ring_bo;
1378 queue->esgs_ring_size = esgs_ring_size;
1379 }
1380
1381 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1382 if (queue->gsvs_ring_bo)
1383 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1384 queue->gsvs_ring_bo = gsvs_ring_bo;
1385 queue->gsvs_ring_size = gsvs_ring_size;
1386 }
1387
1388 if (descriptor_bo != queue->descriptor_bo) {
1389 if (queue->descriptor_bo)
1390 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1391
1392 queue->descriptor_bo = descriptor_bo;
1393 }
1394
1395 *preamble_cs = cs;
1396 return VK_SUCCESS;
1397 fail:
1398 if (cs)
1399 queue->device->ws->cs_destroy(cs);
1400 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1401 queue->device->ws->buffer_destroy(descriptor_bo);
1402 if (scratch_bo && scratch_bo != queue->scratch_bo)
1403 queue->device->ws->buffer_destroy(scratch_bo);
1404 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1405 queue->device->ws->buffer_destroy(compute_scratch_bo);
1406 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1407 queue->device->ws->buffer_destroy(esgs_ring_bo);
1408 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1409 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1410 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1411 }
1412
1413 VkResult radv_QueueSubmit(
1414 VkQueue _queue,
1415 uint32_t submitCount,
1416 const VkSubmitInfo* pSubmits,
1417 VkFence _fence)
1418 {
1419 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1420 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1421 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1422 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1423 int ret;
1424 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1425 uint32_t scratch_size = 0;
1426 uint32_t compute_scratch_size = 0;
1427 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1428 struct radeon_winsys_cs *preamble_cs = NULL;
1429 VkResult result;
1430 bool fence_emitted = false;
1431
1432 /* Do this first so failing to allocate scratch buffers can't result in
1433 * partially executed submissions. */
1434 for (uint32_t i = 0; i < submitCount; i++) {
1435 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1436 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1437 pSubmits[i].pCommandBuffers[j]);
1438
1439 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1440 compute_scratch_size = MAX2(compute_scratch_size,
1441 cmd_buffer->compute_scratch_size_needed);
1442 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1443 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1444 }
1445 }
1446
1447 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size, esgs_ring_size, gsvs_ring_size, &preamble_cs);
1448 if (result != VK_SUCCESS)
1449 return result;
1450
1451 for (uint32_t i = 0; i < submitCount; i++) {
1452 struct radeon_winsys_cs **cs_array;
1453 bool can_patch = true;
1454 uint32_t advance;
1455 int draw_cmd_buffers_count = 0;
1456
1457 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1458 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1459 pSubmits[i].pCommandBuffers[j]);
1460 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1461 if (cmd_buffer->no_draws == true)
1462 continue;
1463 draw_cmd_buffers_count++;
1464 }
1465
1466 if (!draw_cmd_buffers_count) {
1467 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1468 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1469 &queue->device->empty_cs[queue->queue_family_index],
1470 1, NULL,
1471 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1472 pSubmits[i].waitSemaphoreCount,
1473 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1474 pSubmits[i].signalSemaphoreCount,
1475 false, base_fence);
1476 if (ret) {
1477 radv_loge("failed to submit CS %d\n", i);
1478 abort();
1479 }
1480 fence_emitted = true;
1481 }
1482 continue;
1483 }
1484
1485 cs_array = malloc(sizeof(struct radeon_winsys_cs *) * draw_cmd_buffers_count);
1486
1487 int draw_cmd_buffer_idx = 0;
1488 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1489 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1490 pSubmits[i].pCommandBuffers[j]);
1491 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1492 if (cmd_buffer->no_draws == true)
1493 continue;
1494
1495 cs_array[draw_cmd_buffer_idx] = cmd_buffer->cs;
1496 draw_cmd_buffer_idx++;
1497 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1498 can_patch = false;
1499 }
1500
1501 for (uint32_t j = 0; j < draw_cmd_buffers_count; j += advance) {
1502 advance = MIN2(max_cs_submission,
1503 draw_cmd_buffers_count - j);
1504 bool b = j == 0;
1505 bool e = j + advance == draw_cmd_buffers_count;
1506
1507 if (queue->device->trace_bo)
1508 *queue->device->trace_id_ptr = 0;
1509
1510 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1511 advance, preamble_cs,
1512 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1513 b ? pSubmits[i].waitSemaphoreCount : 0,
1514 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1515 e ? pSubmits[i].signalSemaphoreCount : 0,
1516 can_patch, base_fence);
1517
1518 if (ret) {
1519 radv_loge("failed to submit CS %d\n", i);
1520 abort();
1521 }
1522 fence_emitted = true;
1523 if (queue->device->trace_bo) {
1524 bool success = queue->device->ws->ctx_wait_idle(
1525 queue->hw_ctx,
1526 radv_queue_family_to_ring(
1527 queue->queue_family_index),
1528 queue->queue_idx);
1529
1530 if (!success) { /* Hang */
1531 radv_dump_trace(queue->device, cs_array[j]);
1532 abort();
1533 }
1534 }
1535 }
1536 free(cs_array);
1537 }
1538
1539 if (fence) {
1540 if (!fence_emitted)
1541 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1542 &queue->device->empty_cs[queue->queue_family_index],
1543 1, NULL, NULL, 0, NULL, 0,
1544 false, base_fence);
1545
1546 fence->submitted = true;
1547 }
1548
1549 return VK_SUCCESS;
1550 }
1551
1552 VkResult radv_QueueWaitIdle(
1553 VkQueue _queue)
1554 {
1555 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1556
1557 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1558 radv_queue_family_to_ring(queue->queue_family_index),
1559 queue->queue_idx);
1560 return VK_SUCCESS;
1561 }
1562
1563 VkResult radv_DeviceWaitIdle(
1564 VkDevice _device)
1565 {
1566 RADV_FROM_HANDLE(radv_device, device, _device);
1567
1568 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1569 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1570 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1571 }
1572 }
1573 return VK_SUCCESS;
1574 }
1575
1576 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1577 VkInstance instance,
1578 const char* pName)
1579 {
1580 return radv_lookup_entrypoint(pName);
1581 }
1582
1583 /* The loader wants us to expose a second GetInstanceProcAddr function
1584 * to work around certain LD_PRELOAD issues seen in apps.
1585 */
1586 PUBLIC
1587 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1588 VkInstance instance,
1589 const char* pName);
1590
1591 PUBLIC
1592 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1593 VkInstance instance,
1594 const char* pName)
1595 {
1596 return radv_GetInstanceProcAddr(instance, pName);
1597 }
1598
1599 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1600 VkDevice device,
1601 const char* pName)
1602 {
1603 return radv_lookup_entrypoint(pName);
1604 }
1605
1606 VkResult radv_AllocateMemory(
1607 VkDevice _device,
1608 const VkMemoryAllocateInfo* pAllocateInfo,
1609 const VkAllocationCallbacks* pAllocator,
1610 VkDeviceMemory* pMem)
1611 {
1612 RADV_FROM_HANDLE(radv_device, device, _device);
1613 struct radv_device_memory *mem;
1614 VkResult result;
1615 enum radeon_bo_domain domain;
1616 uint32_t flags = 0;
1617 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1618
1619 if (pAllocateInfo->allocationSize == 0) {
1620 /* Apparently, this is allowed */
1621 *pMem = VK_NULL_HANDLE;
1622 return VK_SUCCESS;
1623 }
1624
1625 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1626 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1627 if (mem == NULL)
1628 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1629
1630 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1631 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1632 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1633 domain = RADEON_DOMAIN_GTT;
1634 else
1635 domain = RADEON_DOMAIN_VRAM;
1636
1637 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1638 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1639 else
1640 flags |= RADEON_FLAG_CPU_ACCESS;
1641
1642 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1643 flags |= RADEON_FLAG_GTT_WC;
1644
1645 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1646 domain, flags);
1647
1648 if (!mem->bo) {
1649 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1650 goto fail;
1651 }
1652 mem->type_index = pAllocateInfo->memoryTypeIndex;
1653
1654 *pMem = radv_device_memory_to_handle(mem);
1655
1656 return VK_SUCCESS;
1657
1658 fail:
1659 vk_free2(&device->alloc, pAllocator, mem);
1660
1661 return result;
1662 }
1663
1664 void radv_FreeMemory(
1665 VkDevice _device,
1666 VkDeviceMemory _mem,
1667 const VkAllocationCallbacks* pAllocator)
1668 {
1669 RADV_FROM_HANDLE(radv_device, device, _device);
1670 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1671
1672 if (mem == NULL)
1673 return;
1674
1675 device->ws->buffer_destroy(mem->bo);
1676 mem->bo = NULL;
1677
1678 vk_free2(&device->alloc, pAllocator, mem);
1679 }
1680
1681 VkResult radv_MapMemory(
1682 VkDevice _device,
1683 VkDeviceMemory _memory,
1684 VkDeviceSize offset,
1685 VkDeviceSize size,
1686 VkMemoryMapFlags flags,
1687 void** ppData)
1688 {
1689 RADV_FROM_HANDLE(radv_device, device, _device);
1690 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1691
1692 if (mem == NULL) {
1693 *ppData = NULL;
1694 return VK_SUCCESS;
1695 }
1696
1697 *ppData = device->ws->buffer_map(mem->bo);
1698 if (*ppData) {
1699 *ppData += offset;
1700 return VK_SUCCESS;
1701 }
1702
1703 return VK_ERROR_MEMORY_MAP_FAILED;
1704 }
1705
1706 void radv_UnmapMemory(
1707 VkDevice _device,
1708 VkDeviceMemory _memory)
1709 {
1710 RADV_FROM_HANDLE(radv_device, device, _device);
1711 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1712
1713 if (mem == NULL)
1714 return;
1715
1716 device->ws->buffer_unmap(mem->bo);
1717 }
1718
1719 VkResult radv_FlushMappedMemoryRanges(
1720 VkDevice _device,
1721 uint32_t memoryRangeCount,
1722 const VkMappedMemoryRange* pMemoryRanges)
1723 {
1724 return VK_SUCCESS;
1725 }
1726
1727 VkResult radv_InvalidateMappedMemoryRanges(
1728 VkDevice _device,
1729 uint32_t memoryRangeCount,
1730 const VkMappedMemoryRange* pMemoryRanges)
1731 {
1732 return VK_SUCCESS;
1733 }
1734
1735 void radv_GetBufferMemoryRequirements(
1736 VkDevice device,
1737 VkBuffer _buffer,
1738 VkMemoryRequirements* pMemoryRequirements)
1739 {
1740 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1741
1742 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1743
1744 pMemoryRequirements->size = buffer->size;
1745 pMemoryRequirements->alignment = 16;
1746 }
1747
1748 void radv_GetImageMemoryRequirements(
1749 VkDevice device,
1750 VkImage _image,
1751 VkMemoryRequirements* pMemoryRequirements)
1752 {
1753 RADV_FROM_HANDLE(radv_image, image, _image);
1754
1755 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1756
1757 pMemoryRequirements->size = image->size;
1758 pMemoryRequirements->alignment = image->alignment;
1759 }
1760
1761 void radv_GetImageSparseMemoryRequirements(
1762 VkDevice device,
1763 VkImage image,
1764 uint32_t* pSparseMemoryRequirementCount,
1765 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1766 {
1767 stub();
1768 }
1769
1770 void radv_GetDeviceMemoryCommitment(
1771 VkDevice device,
1772 VkDeviceMemory memory,
1773 VkDeviceSize* pCommittedMemoryInBytes)
1774 {
1775 *pCommittedMemoryInBytes = 0;
1776 }
1777
1778 VkResult radv_BindBufferMemory(
1779 VkDevice device,
1780 VkBuffer _buffer,
1781 VkDeviceMemory _memory,
1782 VkDeviceSize memoryOffset)
1783 {
1784 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1785 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1786
1787 if (mem) {
1788 buffer->bo = mem->bo;
1789 buffer->offset = memoryOffset;
1790 } else {
1791 buffer->bo = NULL;
1792 buffer->offset = 0;
1793 }
1794
1795 return VK_SUCCESS;
1796 }
1797
1798 VkResult radv_BindImageMemory(
1799 VkDevice device,
1800 VkImage _image,
1801 VkDeviceMemory _memory,
1802 VkDeviceSize memoryOffset)
1803 {
1804 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1805 RADV_FROM_HANDLE(radv_image, image, _image);
1806
1807 if (mem) {
1808 image->bo = mem->bo;
1809 image->offset = memoryOffset;
1810 } else {
1811 image->bo = NULL;
1812 image->offset = 0;
1813 }
1814
1815 return VK_SUCCESS;
1816 }
1817
1818 VkResult radv_QueueBindSparse(
1819 VkQueue queue,
1820 uint32_t bindInfoCount,
1821 const VkBindSparseInfo* pBindInfo,
1822 VkFence fence)
1823 {
1824 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1825 }
1826
1827 VkResult radv_CreateFence(
1828 VkDevice _device,
1829 const VkFenceCreateInfo* pCreateInfo,
1830 const VkAllocationCallbacks* pAllocator,
1831 VkFence* pFence)
1832 {
1833 RADV_FROM_HANDLE(radv_device, device, _device);
1834 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1835 sizeof(*fence), 8,
1836 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1837
1838 if (!fence)
1839 return VK_ERROR_OUT_OF_HOST_MEMORY;
1840
1841 memset(fence, 0, sizeof(*fence));
1842 fence->submitted = false;
1843 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1844 fence->fence = device->ws->create_fence();
1845 if (!fence->fence) {
1846 vk_free2(&device->alloc, pAllocator, fence);
1847 return VK_ERROR_OUT_OF_HOST_MEMORY;
1848 }
1849
1850 *pFence = radv_fence_to_handle(fence);
1851
1852 return VK_SUCCESS;
1853 }
1854
1855 void radv_DestroyFence(
1856 VkDevice _device,
1857 VkFence _fence,
1858 const VkAllocationCallbacks* pAllocator)
1859 {
1860 RADV_FROM_HANDLE(radv_device, device, _device);
1861 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1862
1863 if (!fence)
1864 return;
1865 device->ws->destroy_fence(fence->fence);
1866 vk_free2(&device->alloc, pAllocator, fence);
1867 }
1868
1869 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1870 {
1871 uint64_t current_time;
1872 struct timespec tv;
1873
1874 clock_gettime(CLOCK_MONOTONIC, &tv);
1875 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1876
1877 timeout = MIN2(UINT64_MAX - current_time, timeout);
1878
1879 return current_time + timeout;
1880 }
1881
1882 VkResult radv_WaitForFences(
1883 VkDevice _device,
1884 uint32_t fenceCount,
1885 const VkFence* pFences,
1886 VkBool32 waitAll,
1887 uint64_t timeout)
1888 {
1889 RADV_FROM_HANDLE(radv_device, device, _device);
1890 timeout = radv_get_absolute_timeout(timeout);
1891
1892 if (!waitAll && fenceCount > 1) {
1893 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1894 }
1895
1896 for (uint32_t i = 0; i < fenceCount; ++i) {
1897 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1898 bool expired = false;
1899
1900 if (fence->signalled)
1901 continue;
1902
1903 if (!fence->submitted)
1904 return VK_TIMEOUT;
1905
1906 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1907 if (!expired)
1908 return VK_TIMEOUT;
1909
1910 fence->signalled = true;
1911 }
1912
1913 return VK_SUCCESS;
1914 }
1915
1916 VkResult radv_ResetFences(VkDevice device,
1917 uint32_t fenceCount,
1918 const VkFence *pFences)
1919 {
1920 for (unsigned i = 0; i < fenceCount; ++i) {
1921 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1922 fence->submitted = fence->signalled = false;
1923 }
1924
1925 return VK_SUCCESS;
1926 }
1927
1928 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1929 {
1930 RADV_FROM_HANDLE(radv_device, device, _device);
1931 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1932
1933 if (fence->signalled)
1934 return VK_SUCCESS;
1935 if (!fence->submitted)
1936 return VK_NOT_READY;
1937
1938 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1939 return VK_NOT_READY;
1940
1941 return VK_SUCCESS;
1942 }
1943
1944
1945 // Queue semaphore functions
1946
1947 VkResult radv_CreateSemaphore(
1948 VkDevice _device,
1949 const VkSemaphoreCreateInfo* pCreateInfo,
1950 const VkAllocationCallbacks* pAllocator,
1951 VkSemaphore* pSemaphore)
1952 {
1953 RADV_FROM_HANDLE(radv_device, device, _device);
1954 struct radeon_winsys_sem *sem;
1955
1956 sem = device->ws->create_sem(device->ws);
1957 if (!sem)
1958 return VK_ERROR_OUT_OF_HOST_MEMORY;
1959
1960 *pSemaphore = (VkSemaphore)sem;
1961 return VK_SUCCESS;
1962 }
1963
1964 void radv_DestroySemaphore(
1965 VkDevice _device,
1966 VkSemaphore _semaphore,
1967 const VkAllocationCallbacks* pAllocator)
1968 {
1969 RADV_FROM_HANDLE(radv_device, device, _device);
1970 struct radeon_winsys_sem *sem;
1971 if (!_semaphore)
1972 return;
1973
1974 sem = (struct radeon_winsys_sem *)_semaphore;
1975 device->ws->destroy_sem(sem);
1976 }
1977
1978 VkResult radv_CreateEvent(
1979 VkDevice _device,
1980 const VkEventCreateInfo* pCreateInfo,
1981 const VkAllocationCallbacks* pAllocator,
1982 VkEvent* pEvent)
1983 {
1984 RADV_FROM_HANDLE(radv_device, device, _device);
1985 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1986 sizeof(*event), 8,
1987 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1988
1989 if (!event)
1990 return VK_ERROR_OUT_OF_HOST_MEMORY;
1991
1992 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1993 RADEON_DOMAIN_GTT,
1994 RADEON_FLAG_CPU_ACCESS);
1995 if (!event->bo) {
1996 vk_free2(&device->alloc, pAllocator, event);
1997 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1998 }
1999
2000 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2001
2002 *pEvent = radv_event_to_handle(event);
2003
2004 return VK_SUCCESS;
2005 }
2006
2007 void radv_DestroyEvent(
2008 VkDevice _device,
2009 VkEvent _event,
2010 const VkAllocationCallbacks* pAllocator)
2011 {
2012 RADV_FROM_HANDLE(radv_device, device, _device);
2013 RADV_FROM_HANDLE(radv_event, event, _event);
2014
2015 if (!event)
2016 return;
2017 device->ws->buffer_destroy(event->bo);
2018 vk_free2(&device->alloc, pAllocator, event);
2019 }
2020
2021 VkResult radv_GetEventStatus(
2022 VkDevice _device,
2023 VkEvent _event)
2024 {
2025 RADV_FROM_HANDLE(radv_event, event, _event);
2026
2027 if (*event->map == 1)
2028 return VK_EVENT_SET;
2029 return VK_EVENT_RESET;
2030 }
2031
2032 VkResult radv_SetEvent(
2033 VkDevice _device,
2034 VkEvent _event)
2035 {
2036 RADV_FROM_HANDLE(radv_event, event, _event);
2037 *event->map = 1;
2038
2039 return VK_SUCCESS;
2040 }
2041
2042 VkResult radv_ResetEvent(
2043 VkDevice _device,
2044 VkEvent _event)
2045 {
2046 RADV_FROM_HANDLE(radv_event, event, _event);
2047 *event->map = 0;
2048
2049 return VK_SUCCESS;
2050 }
2051
2052 VkResult radv_CreateBuffer(
2053 VkDevice _device,
2054 const VkBufferCreateInfo* pCreateInfo,
2055 const VkAllocationCallbacks* pAllocator,
2056 VkBuffer* pBuffer)
2057 {
2058 RADV_FROM_HANDLE(radv_device, device, _device);
2059 struct radv_buffer *buffer;
2060
2061 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2062
2063 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2064 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2065 if (buffer == NULL)
2066 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2067
2068 buffer->size = pCreateInfo->size;
2069 buffer->usage = pCreateInfo->usage;
2070 buffer->bo = NULL;
2071 buffer->offset = 0;
2072
2073 *pBuffer = radv_buffer_to_handle(buffer);
2074
2075 return VK_SUCCESS;
2076 }
2077
2078 void radv_DestroyBuffer(
2079 VkDevice _device,
2080 VkBuffer _buffer,
2081 const VkAllocationCallbacks* pAllocator)
2082 {
2083 RADV_FROM_HANDLE(radv_device, device, _device);
2084 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2085
2086 if (!buffer)
2087 return;
2088
2089 vk_free2(&device->alloc, pAllocator, buffer);
2090 }
2091
2092 static inline unsigned
2093 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2094 {
2095 if (stencil)
2096 return image->surface.stencil_tiling_index[level];
2097 else
2098 return image->surface.tiling_index[level];
2099 }
2100
2101 static void
2102 radv_initialise_color_surface(struct radv_device *device,
2103 struct radv_color_buffer_info *cb,
2104 struct radv_image_view *iview)
2105 {
2106 const struct vk_format_description *desc;
2107 unsigned ntype, format, swap, endian;
2108 unsigned blend_clamp = 0, blend_bypass = 0;
2109 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2110 uint64_t va;
2111 const struct radeon_surf *surf = &iview->image->surface;
2112 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
2113
2114 desc = vk_format_description(iview->vk_format);
2115
2116 memset(cb, 0, sizeof(*cb));
2117
2118 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2119 va += level_info->offset;
2120 cb->cb_color_base = va >> 8;
2121
2122 /* CMASK variables */
2123 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2124 va += iview->image->cmask.offset;
2125 cb->cb_color_cmask = va >> 8;
2126 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2127
2128 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2129 va += iview->image->dcc_offset;
2130 cb->cb_dcc_base = va >> 8;
2131
2132 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2133 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2134 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2135
2136 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2137 pitch_tile_max = level_info->nblk_x / 8 - 1;
2138 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2139 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2140
2141 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2142 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2143
2144 /* Intensity is implemented as Red, so treat it that way. */
2145 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
2146 S_028C74_TILE_MODE_INDEX(tile_mode_index);
2147
2148 if (iview->image->samples > 1) {
2149 unsigned log_samples = util_logbase2(iview->image->samples);
2150
2151 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2152 S_028C74_NUM_FRAGMENTS(log_samples);
2153 }
2154
2155 if (iview->image->fmask.size) {
2156 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2157 if (device->physical_device->rad_info.chip_class >= CIK)
2158 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2159 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2160 cb->cb_color_fmask = va >> 8;
2161 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2162 } else {
2163 /* This must be set for fast clear to work without FMASK. */
2164 if (device->physical_device->rad_info.chip_class >= CIK)
2165 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2166 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2167 cb->cb_color_fmask = cb->cb_color_base;
2168 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2169 }
2170
2171 ntype = radv_translate_color_numformat(iview->vk_format,
2172 desc,
2173 vk_format_get_first_non_void_channel(iview->vk_format));
2174 format = radv_translate_colorformat(iview->vk_format);
2175 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2176 radv_finishme("Illegal color\n");
2177 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2178 endian = radv_colorformat_endian_swap(format);
2179
2180 /* blend clamp should be set for all NORM/SRGB types */
2181 if (ntype == V_028C70_NUMBER_UNORM ||
2182 ntype == V_028C70_NUMBER_SNORM ||
2183 ntype == V_028C70_NUMBER_SRGB)
2184 blend_clamp = 1;
2185
2186 /* set blend bypass according to docs if SINT/UINT or
2187 8/24 COLOR variants */
2188 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2189 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2190 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2191 blend_clamp = 0;
2192 blend_bypass = 1;
2193 }
2194 #if 0
2195 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2196 (format == V_028C70_COLOR_8 ||
2197 format == V_028C70_COLOR_8_8 ||
2198 format == V_028C70_COLOR_8_8_8_8))
2199 ->color_is_int8 = true;
2200 #endif
2201 cb->cb_color_info = S_028C70_FORMAT(format) |
2202 S_028C70_COMP_SWAP(swap) |
2203 S_028C70_BLEND_CLAMP(blend_clamp) |
2204 S_028C70_BLEND_BYPASS(blend_bypass) |
2205 S_028C70_SIMPLE_FLOAT(1) |
2206 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2207 ntype != V_028C70_NUMBER_SNORM &&
2208 ntype != V_028C70_NUMBER_SRGB &&
2209 format != V_028C70_COLOR_8_24 &&
2210 format != V_028C70_COLOR_24_8) |
2211 S_028C70_NUMBER_TYPE(ntype) |
2212 S_028C70_ENDIAN(endian);
2213 if (iview->image->samples > 1)
2214 if (iview->image->fmask.size)
2215 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2216
2217 if (iview->image->cmask.size &&
2218 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2219 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2220
2221 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
2222 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2223
2224 if (device->physical_device->rad_info.chip_class >= VI) {
2225 unsigned max_uncompressed_block_size = 2;
2226 if (iview->image->samples > 1) {
2227 if (iview->image->surface.bpe == 1)
2228 max_uncompressed_block_size = 0;
2229 else if (iview->image->surface.bpe == 2)
2230 max_uncompressed_block_size = 1;
2231 }
2232
2233 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2234 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2235 }
2236
2237 /* This must be set for fast clear to work without FMASK. */
2238 if (!iview->image->fmask.size &&
2239 device->physical_device->rad_info.chip_class == SI) {
2240 unsigned bankh = util_logbase2(iview->image->surface.bankh);
2241 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2242 }
2243 }
2244
2245 static void
2246 radv_initialise_ds_surface(struct radv_device *device,
2247 struct radv_ds_buffer_info *ds,
2248 struct radv_image_view *iview)
2249 {
2250 unsigned level = iview->base_mip;
2251 unsigned format;
2252 uint64_t va, s_offs, z_offs;
2253 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
2254 memset(ds, 0, sizeof(*ds));
2255 switch (iview->vk_format) {
2256 case VK_FORMAT_D24_UNORM_S8_UINT:
2257 case VK_FORMAT_X8_D24_UNORM_PACK32:
2258 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2259 ds->offset_scale = 2.0f;
2260 break;
2261 case VK_FORMAT_D16_UNORM:
2262 case VK_FORMAT_D16_UNORM_S8_UINT:
2263 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2264 ds->offset_scale = 4.0f;
2265 break;
2266 case VK_FORMAT_D32_SFLOAT:
2267 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2268 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2269 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2270 ds->offset_scale = 1.0f;
2271 break;
2272 default:
2273 break;
2274 }
2275
2276 format = radv_translate_dbformat(iview->vk_format);
2277 if (format == V_028040_Z_INVALID) {
2278 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
2279 }
2280
2281 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2282 s_offs = z_offs = va;
2283 z_offs += iview->image->surface.level[level].offset;
2284 s_offs += iview->image->surface.stencil_level[level].offset;
2285
2286 uint32_t max_slice = iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2287 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2288 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2289 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2290 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2291
2292 if (iview->image->samples > 1)
2293 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
2294
2295 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
2296 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
2297 else
2298 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
2299
2300 if (device->physical_device->rad_info.chip_class >= CIK) {
2301 struct radeon_info *info = &device->physical_device->rad_info;
2302 unsigned tiling_index = iview->image->surface.tiling_index[level];
2303 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
2304 unsigned macro_index = iview->image->surface.macro_tile_index;
2305 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2306 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2307 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2308
2309 ds->db_depth_info |=
2310 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2311 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2312 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2313 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2314 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2315 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2316 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2317 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2318 } else {
2319 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2320 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2321 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2322 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2323 }
2324
2325 if (iview->image->htile.size && !level) {
2326 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
2327 S_028040_ALLOW_EXPCLEAR(1);
2328
2329 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
2330 /* Workaround: For a not yet understood reason, the
2331 * combination of MSAA, fast stencil clear and stencil
2332 * decompress messes with subsequent stencil buffer
2333 * uses. Problem was reproduced on Verde, Bonaire,
2334 * Tonga, and Carrizo.
2335 *
2336 * Disabling EXPCLEAR works around the problem.
2337 *
2338 * Check piglit's arb_texture_multisample-stencil-clear
2339 * test if you want to try changing this.
2340 */
2341 if (iview->image->samples <= 1)
2342 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
2343 } else
2344 /* Use all of the htile_buffer for depth if there's no stencil. */
2345 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2346
2347 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2348 iview->image->htile.offset;
2349 ds->db_htile_data_base = va >> 8;
2350 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2351 } else {
2352 ds->db_htile_data_base = 0;
2353 ds->db_htile_surface = 0;
2354 }
2355
2356 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2357 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2358
2359 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2360 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2361 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2362 }
2363
2364 VkResult radv_CreateFramebuffer(
2365 VkDevice _device,
2366 const VkFramebufferCreateInfo* pCreateInfo,
2367 const VkAllocationCallbacks* pAllocator,
2368 VkFramebuffer* pFramebuffer)
2369 {
2370 RADV_FROM_HANDLE(radv_device, device, _device);
2371 struct radv_framebuffer *framebuffer;
2372
2373 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2374
2375 size_t size = sizeof(*framebuffer) +
2376 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2377 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2378 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2379 if (framebuffer == NULL)
2380 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2381
2382 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2383 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2384 VkImageView _iview = pCreateInfo->pAttachments[i];
2385 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2386 framebuffer->attachments[i].attachment = iview;
2387 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2388 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2389 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2390 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2391 }
2392 }
2393
2394 framebuffer->width = pCreateInfo->width;
2395 framebuffer->height = pCreateInfo->height;
2396 framebuffer->layers = pCreateInfo->layers;
2397
2398 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2399 return VK_SUCCESS;
2400 }
2401
2402 void radv_DestroyFramebuffer(
2403 VkDevice _device,
2404 VkFramebuffer _fb,
2405 const VkAllocationCallbacks* pAllocator)
2406 {
2407 RADV_FROM_HANDLE(radv_device, device, _device);
2408 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2409
2410 if (!fb)
2411 return;
2412 vk_free2(&device->alloc, pAllocator, fb);
2413 }
2414
2415 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
2416 {
2417 switch (address_mode) {
2418 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
2419 return V_008F30_SQ_TEX_WRAP;
2420 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
2421 return V_008F30_SQ_TEX_MIRROR;
2422 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
2423 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
2424 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
2425 return V_008F30_SQ_TEX_CLAMP_BORDER;
2426 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
2427 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
2428 default:
2429 unreachable("illegal tex wrap mode");
2430 break;
2431 }
2432 }
2433
2434 static unsigned
2435 radv_tex_compare(VkCompareOp op)
2436 {
2437 switch (op) {
2438 case VK_COMPARE_OP_NEVER:
2439 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
2440 case VK_COMPARE_OP_LESS:
2441 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
2442 case VK_COMPARE_OP_EQUAL:
2443 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
2444 case VK_COMPARE_OP_LESS_OR_EQUAL:
2445 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
2446 case VK_COMPARE_OP_GREATER:
2447 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
2448 case VK_COMPARE_OP_NOT_EQUAL:
2449 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
2450 case VK_COMPARE_OP_GREATER_OR_EQUAL:
2451 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
2452 case VK_COMPARE_OP_ALWAYS:
2453 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
2454 default:
2455 unreachable("illegal compare mode");
2456 break;
2457 }
2458 }
2459
2460 static unsigned
2461 radv_tex_filter(VkFilter filter, unsigned max_ansio)
2462 {
2463 switch (filter) {
2464 case VK_FILTER_NEAREST:
2465 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
2466 V_008F38_SQ_TEX_XY_FILTER_POINT);
2467 case VK_FILTER_LINEAR:
2468 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
2469 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
2470 case VK_FILTER_CUBIC_IMG:
2471 default:
2472 fprintf(stderr, "illegal texture filter");
2473 return 0;
2474 }
2475 }
2476
2477 static unsigned
2478 radv_tex_mipfilter(VkSamplerMipmapMode mode)
2479 {
2480 switch (mode) {
2481 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
2482 return V_008F38_SQ_TEX_Z_FILTER_POINT;
2483 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
2484 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
2485 default:
2486 return V_008F38_SQ_TEX_Z_FILTER_NONE;
2487 }
2488 }
2489
2490 static unsigned
2491 radv_tex_bordercolor(VkBorderColor bcolor)
2492 {
2493 switch (bcolor) {
2494 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
2495 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
2496 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
2497 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
2498 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
2499 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
2500 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
2501 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
2502 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
2503 default:
2504 break;
2505 }
2506 return 0;
2507 }
2508
2509 static unsigned
2510 radv_tex_aniso_filter(unsigned filter)
2511 {
2512 if (filter < 2)
2513 return 0;
2514 if (filter < 4)
2515 return 1;
2516 if (filter < 8)
2517 return 2;
2518 if (filter < 16)
2519 return 3;
2520 return 4;
2521 }
2522
2523 static void
2524 radv_init_sampler(struct radv_device *device,
2525 struct radv_sampler *sampler,
2526 const VkSamplerCreateInfo *pCreateInfo)
2527 {
2528 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
2529 (uint32_t) pCreateInfo->maxAnisotropy : 0;
2530 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
2531 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
2532
2533 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
2534 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
2535 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
2536 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
2537 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
2538 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
2539 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
2540 S_008F30_ANISO_BIAS(max_aniso_ratio) |
2541 S_008F30_DISABLE_CUBE_WRAP(0) |
2542 S_008F30_COMPAT_MODE(is_vi));
2543 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
2544 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
2545 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
2546 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
2547 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
2548 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
2549 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
2550 S_008F38_MIP_POINT_PRECLAMP(1) |
2551 S_008F38_DISABLE_LSB_CEIL(1) |
2552 S_008F38_FILTER_PREC_FIX(1) |
2553 S_008F38_ANISO_OVERRIDE(is_vi));
2554 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
2555 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
2556 }
2557
2558 VkResult radv_CreateSampler(
2559 VkDevice _device,
2560 const VkSamplerCreateInfo* pCreateInfo,
2561 const VkAllocationCallbacks* pAllocator,
2562 VkSampler* pSampler)
2563 {
2564 RADV_FROM_HANDLE(radv_device, device, _device);
2565 struct radv_sampler *sampler;
2566
2567 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2568
2569 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2570 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2571 if (!sampler)
2572 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2573
2574 radv_init_sampler(device, sampler, pCreateInfo);
2575 *pSampler = radv_sampler_to_handle(sampler);
2576
2577 return VK_SUCCESS;
2578 }
2579
2580 void radv_DestroySampler(
2581 VkDevice _device,
2582 VkSampler _sampler,
2583 const VkAllocationCallbacks* pAllocator)
2584 {
2585 RADV_FROM_HANDLE(radv_device, device, _device);
2586 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2587
2588 if (!sampler)
2589 return;
2590 vk_free2(&device->alloc, pAllocator, sampler);
2591 }
2592
2593
2594 /* vk_icd.h does not declare this function, so we declare it here to
2595 * suppress Wmissing-prototypes.
2596 */
2597 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2598 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
2599
2600 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
2601 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
2602 {
2603 /* For the full details on loader interface versioning, see
2604 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
2605 * What follows is a condensed summary, to help you navigate the large and
2606 * confusing official doc.
2607 *
2608 * - Loader interface v0 is incompatible with later versions. We don't
2609 * support it.
2610 *
2611 * - In loader interface v1:
2612 * - The first ICD entrypoint called by the loader is
2613 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
2614 * entrypoint.
2615 * - The ICD must statically expose no other Vulkan symbol unless it is
2616 * linked with -Bsymbolic.
2617 * - Each dispatchable Vulkan handle created by the ICD must be
2618 * a pointer to a struct whose first member is VK_LOADER_DATA. The
2619 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
2620 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
2621 * vkDestroySurfaceKHR(). The ICD must be capable of working with
2622 * such loader-managed surfaces.
2623 *
2624 * - Loader interface v2 differs from v1 in:
2625 * - The first ICD entrypoint called by the loader is
2626 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
2627 * statically expose this entrypoint.
2628 *
2629 * - Loader interface v3 differs from v2 in:
2630 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
2631 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
2632 * because the loader no longer does so.
2633 */
2634 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
2635 return VK_SUCCESS;
2636 }