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radv: Expose VK_EXT_ycbcr_image_arrays.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "git_sha1.h"
47 #include "gfx9d.h"
48 #include "util/build_id.h"
49 #include "util/debug.h"
50 #include "util/mesa-sha1.h"
51 #include "compiler/glsl_types.h"
52 #include "util/xmlpool.h"
53
54 static int
55 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
56 {
57 struct mesa_sha1 ctx;
58 unsigned char sha1[20];
59 unsigned ptr_size = sizeof(void*);
60
61 memset(uuid, 0, VK_UUID_SIZE);
62 _mesa_sha1_init(&ctx);
63
64 if (!disk_cache_get_function_identifier(radv_device_get_cache_uuid, &ctx) ||
65 !disk_cache_get_function_identifier(LLVMInitializeAMDGPUTargetInfo, &ctx))
66 return -1;
67
68 _mesa_sha1_update(&ctx, &family, sizeof(family));
69 _mesa_sha1_update(&ctx, &ptr_size, sizeof(ptr_size));
70 _mesa_sha1_final(&ctx, sha1);
71
72 memcpy(uuid, sha1, VK_UUID_SIZE);
73 return 0;
74 }
75
76 static void
77 radv_get_driver_uuid(void *uuid)
78 {
79 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
80 }
81
82 static void
83 radv_get_device_uuid(struct radeon_info *info, void *uuid)
84 {
85 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
86 }
87
88 static void
89 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
90 {
91 const char *chip_string;
92
93 switch (family) {
94 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
95 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
96 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
97 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
98 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
99 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
100 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
101 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
102 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
103 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
104 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
105 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
106 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
107 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
108 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
109 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
110 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
111 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
112 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
113 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
114 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
115 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
116 case CHIP_RAVEN2: chip_string = "AMD RADV RAVEN2"; break;
117 default: chip_string = "AMD RADV unknown"; break;
118 }
119
120 snprintf(name, name_len, "%s (LLVM " MESA_LLVM_VERSION_STRING ")", chip_string);
121 }
122
123 static uint64_t
124 radv_get_visible_vram_size(struct radv_physical_device *device)
125 {
126 return MIN2(device->rad_info.vram_size, device->rad_info.vram_vis_size);
127 }
128
129 static uint64_t
130 radv_get_vram_size(struct radv_physical_device *device)
131 {
132 return device->rad_info.vram_size - radv_get_visible_vram_size(device);
133 }
134
135 static void
136 radv_physical_device_init_mem_types(struct radv_physical_device *device)
137 {
138 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
139 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
140 uint64_t vram_size = radv_get_vram_size(device);
141 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
142 device->memory_properties.memoryHeapCount = 0;
143 if (vram_size > 0) {
144 vram_index = device->memory_properties.memoryHeapCount++;
145 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
146 .size = vram_size,
147 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
148 };
149 }
150 if (visible_vram_size) {
151 visible_vram_index = device->memory_properties.memoryHeapCount++;
152 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
153 .size = visible_vram_size,
154 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
155 };
156 }
157 if (device->rad_info.gart_size > 0) {
158 gart_index = device->memory_properties.memoryHeapCount++;
159 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
160 .size = device->rad_info.gart_size,
161 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
162 };
163 }
164
165 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
166 unsigned type_count = 0;
167 if (vram_index >= 0) {
168 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
169 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
170 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
171 .heapIndex = vram_index,
172 };
173 }
174 if (gart_index >= 0) {
175 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
176 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
177 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
178 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
179 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
180 .heapIndex = gart_index,
181 };
182 }
183 if (visible_vram_index >= 0) {
184 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
185 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
186 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
187 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
188 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
189 .heapIndex = visible_vram_index,
190 };
191 }
192 if (gart_index >= 0) {
193 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
194 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
195 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
196 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
197 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
198 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
199 .heapIndex = gart_index,
200 };
201 }
202 device->memory_properties.memoryTypeCount = type_count;
203 }
204
205 static void
206 radv_handle_env_var_force_family(struct radv_physical_device *device)
207 {
208 const char *family = getenv("RADV_FORCE_FAMILY");
209 unsigned i;
210
211 if (!family)
212 return;
213
214 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
215 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
216 /* Override family and chip_class. */
217 device->rad_info.family = i;
218
219 if (i >= CHIP_VEGA10)
220 device->rad_info.chip_class = GFX9;
221 else if (i >= CHIP_TONGA)
222 device->rad_info.chip_class = VI;
223 else if (i >= CHIP_BONAIRE)
224 device->rad_info.chip_class = CIK;
225 else
226 device->rad_info.chip_class = SI;
227
228 return;
229 }
230 }
231
232 fprintf(stderr, "radv: Unknown family: %s\n", family);
233 exit(1);
234 }
235
236 static VkResult
237 radv_physical_device_init(struct radv_physical_device *device,
238 struct radv_instance *instance,
239 drmDevicePtr drm_device)
240 {
241 const char *path = drm_device->nodes[DRM_NODE_RENDER];
242 VkResult result;
243 drmVersionPtr version;
244 int fd;
245 int master_fd = -1;
246
247 fd = open(path, O_RDWR | O_CLOEXEC);
248 if (fd < 0) {
249 if (instance->debug_flags & RADV_DEBUG_STARTUP)
250 radv_logi("Could not open device '%s'", path);
251
252 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
253 }
254
255 version = drmGetVersion(fd);
256 if (!version) {
257 close(fd);
258
259 if (instance->debug_flags & RADV_DEBUG_STARTUP)
260 radv_logi("Could not get the kernel driver version for device '%s'", path);
261
262 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
263 "failed to get version %s: %m", path);
264 }
265
266 if (strcmp(version->name, "amdgpu")) {
267 drmFreeVersion(version);
268 close(fd);
269
270 if (instance->debug_flags & RADV_DEBUG_STARTUP)
271 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
272
273 return VK_ERROR_INCOMPATIBLE_DRIVER;
274 }
275 drmFreeVersion(version);
276
277 if (instance->debug_flags & RADV_DEBUG_STARTUP)
278 radv_logi("Found compatible device '%s'.", path);
279
280 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
281 device->instance = instance;
282
283 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
284 instance->perftest_flags);
285 if (!device->ws) {
286 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
287 goto fail;
288 }
289
290 if (instance->enabled_extensions.KHR_display) {
291 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
292 if (master_fd >= 0) {
293 uint32_t accel_working = 0;
294 struct drm_amdgpu_info request = {
295 .return_pointer = (uintptr_t)&accel_working,
296 .return_size = sizeof(accel_working),
297 .query = AMDGPU_INFO_ACCEL_WORKING
298 };
299
300 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
301 close(master_fd);
302 master_fd = -1;
303 }
304 }
305 }
306
307 device->master_fd = master_fd;
308 device->local_fd = fd;
309 device->ws->query_info(device->ws, &device->rad_info);
310
311 radv_handle_env_var_force_family(device);
312
313 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
314
315 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
316 device->ws->destroy(device->ws);
317 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
318 "cannot generate UUID");
319 goto fail;
320 }
321
322 /* These flags affect shader compilation. */
323 uint64_t shader_env_flags =
324 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
325 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
326
327 /* The gpu id is already embedded in the uuid so we just pass "radv"
328 * when creating the cache.
329 */
330 char buf[VK_UUID_SIZE * 2 + 1];
331 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
332 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
333
334 if (device->rad_info.chip_class < VI ||
335 device->rad_info.chip_class > GFX9)
336 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
337
338 radv_get_driver_uuid(&device->driver_uuid);
339 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
340
341 if (device->rad_info.family == CHIP_STONEY ||
342 device->rad_info.chip_class >= GFX9) {
343 device->has_rbplus = true;
344 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
345 device->rad_info.family == CHIP_VEGA12 ||
346 device->rad_info.family == CHIP_RAVEN ||
347 device->rad_info.family == CHIP_RAVEN2;
348 }
349
350 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
351 * on SI.
352 */
353 device->has_clear_state = device->rad_info.chip_class >= CIK;
354
355 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
356
357 /* Vega10/Raven need a special workaround for a hardware bug. */
358 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
359 device->rad_info.family == CHIP_RAVEN;
360
361 /* Out-of-order primitive rasterization. */
362 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
363 device->rad_info.max_se >= 2;
364 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
365 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
366
367 device->dcc_msaa_allowed =
368 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
369
370 /* TODO: Figure out how to use LOAD_CONTEXT_REG on SI/CIK. */
371 device->has_load_ctx_reg_pkt = device->rad_info.chip_class >= GFX9 ||
372 (device->rad_info.chip_class >= VI &&
373 device->rad_info.me_fw_feature >= 41);
374
375 radv_physical_device_init_mem_types(device);
376 radv_fill_device_extension_table(device, &device->supported_extensions);
377
378 device->bus_info = *drm_device->businfo.pci;
379
380 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
381 ac_print_gpu_info(&device->rad_info);
382
383 /* The WSI is structured as a layer on top of the driver, so this has
384 * to be the last part of initialization (at least until we get other
385 * semi-layers).
386 */
387 result = radv_init_wsi(device);
388 if (result != VK_SUCCESS) {
389 device->ws->destroy(device->ws);
390 vk_error(instance, result);
391 goto fail;
392 }
393
394 return VK_SUCCESS;
395
396 fail:
397 close(fd);
398 if (master_fd != -1)
399 close(master_fd);
400 return result;
401 }
402
403 static void
404 radv_physical_device_finish(struct radv_physical_device *device)
405 {
406 radv_finish_wsi(device);
407 device->ws->destroy(device->ws);
408 disk_cache_destroy(device->disk_cache);
409 close(device->local_fd);
410 if (device->master_fd != -1)
411 close(device->master_fd);
412 }
413
414 static void *
415 default_alloc_func(void *pUserData, size_t size, size_t align,
416 VkSystemAllocationScope allocationScope)
417 {
418 return malloc(size);
419 }
420
421 static void *
422 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
423 size_t align, VkSystemAllocationScope allocationScope)
424 {
425 return realloc(pOriginal, size);
426 }
427
428 static void
429 default_free_func(void *pUserData, void *pMemory)
430 {
431 free(pMemory);
432 }
433
434 static const VkAllocationCallbacks default_alloc = {
435 .pUserData = NULL,
436 .pfnAllocation = default_alloc_func,
437 .pfnReallocation = default_realloc_func,
438 .pfnFree = default_free_func,
439 };
440
441 static const struct debug_control radv_debug_options[] = {
442 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
443 {"nodcc", RADV_DEBUG_NO_DCC},
444 {"shaders", RADV_DEBUG_DUMP_SHADERS},
445 {"nocache", RADV_DEBUG_NO_CACHE},
446 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
447 {"nohiz", RADV_DEBUG_NO_HIZ},
448 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
449 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
450 {"allbos", RADV_DEBUG_ALL_BOS},
451 {"noibs", RADV_DEBUG_NO_IBS},
452 {"spirv", RADV_DEBUG_DUMP_SPIRV},
453 {"vmfaults", RADV_DEBUG_VM_FAULTS},
454 {"zerovram", RADV_DEBUG_ZERO_VRAM},
455 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
456 {"nosisched", RADV_DEBUG_NO_SISCHED},
457 {"preoptir", RADV_DEBUG_PREOPTIR},
458 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
459 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
460 {"info", RADV_DEBUG_INFO},
461 {"errors", RADV_DEBUG_ERRORS},
462 {"startup", RADV_DEBUG_STARTUP},
463 {"checkir", RADV_DEBUG_CHECKIR},
464 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
465 {"nobinning", RADV_DEBUG_NOBINNING},
466 {NULL, 0}
467 };
468
469 const char *
470 radv_get_debug_option_name(int id)
471 {
472 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
473 return radv_debug_options[id].string;
474 }
475
476 static const struct debug_control radv_perftest_options[] = {
477 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
478 {"sisched", RADV_PERFTEST_SISCHED},
479 {"localbos", RADV_PERFTEST_LOCAL_BOS},
480 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
481 {"bolist", RADV_PERFTEST_BO_LIST},
482 {NULL, 0}
483 };
484
485 const char *
486 radv_get_perftest_option_name(int id)
487 {
488 assert(id < ARRAY_SIZE(radv_perftest_options) - 1);
489 return radv_perftest_options[id].string;
490 }
491
492 static void
493 radv_handle_per_app_options(struct radv_instance *instance,
494 const VkApplicationInfo *info)
495 {
496 const char *name = info ? info->pApplicationName : NULL;
497
498 if (!name)
499 return;
500
501 if (!strcmp(name, "Talos - Linux - 32bit") ||
502 !strcmp(name, "Talos - Linux - 64bit")) {
503 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
504 /* Force enable LLVM sisched for Talos because it looks
505 * safe and it gives few more FPS.
506 */
507 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
508 }
509 } else if (!strcmp(name, "DOOM_VFR")) {
510 /* Work around a Doom VFR game bug */
511 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
512 }
513 }
514
515 static int radv_get_instance_extension_index(const char *name)
516 {
517 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
518 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
519 return i;
520 }
521 return -1;
522 }
523
524 static const char radv_dri_options_xml[] =
525 DRI_CONF_BEGIN
526 DRI_CONF_SECTION_QUALITY
527 DRI_CONF_ADAPTIVE_SYNC("true")
528 DRI_CONF_SECTION_END
529 DRI_CONF_END;
530
531 static void radv_init_dri_options(struct radv_instance *instance)
532 {
533 driParseOptionInfo(&instance->available_dri_options, radv_dri_options_xml);
534 driParseConfigFiles(&instance->dri_options,
535 &instance->available_dri_options,
536 0, "radv", NULL);
537 }
538
539 VkResult radv_CreateInstance(
540 const VkInstanceCreateInfo* pCreateInfo,
541 const VkAllocationCallbacks* pAllocator,
542 VkInstance* pInstance)
543 {
544 struct radv_instance *instance;
545 VkResult result;
546
547 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
548
549 uint32_t client_version;
550 if (pCreateInfo->pApplicationInfo &&
551 pCreateInfo->pApplicationInfo->apiVersion != 0) {
552 client_version = pCreateInfo->pApplicationInfo->apiVersion;
553 } else {
554 client_version = VK_API_VERSION_1_0;
555 }
556
557 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
558 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
559 if (!instance)
560 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
561
562 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
563
564 if (pAllocator)
565 instance->alloc = *pAllocator;
566 else
567 instance->alloc = default_alloc;
568
569 instance->apiVersion = client_version;
570 instance->physicalDeviceCount = -1;
571
572 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
573 radv_debug_options);
574
575 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
576 radv_perftest_options);
577
578
579 if (instance->debug_flags & RADV_DEBUG_STARTUP)
580 radv_logi("Created an instance");
581
582 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
583 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
584 int index = radv_get_instance_extension_index(ext_name);
585
586 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
587 vk_free2(&default_alloc, pAllocator, instance);
588 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
589 }
590
591 instance->enabled_extensions.extensions[index] = true;
592 }
593
594 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
595 if (result != VK_SUCCESS) {
596 vk_free2(&default_alloc, pAllocator, instance);
597 return vk_error(instance, result);
598 }
599
600 _mesa_locale_init();
601 glsl_type_singleton_init_or_ref();
602
603 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
604
605 radv_init_dri_options(instance);
606 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
607
608 *pInstance = radv_instance_to_handle(instance);
609
610 return VK_SUCCESS;
611 }
612
613 void radv_DestroyInstance(
614 VkInstance _instance,
615 const VkAllocationCallbacks* pAllocator)
616 {
617 RADV_FROM_HANDLE(radv_instance, instance, _instance);
618
619 if (!instance)
620 return;
621
622 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
623 radv_physical_device_finish(instance->physicalDevices + i);
624 }
625
626 VG(VALGRIND_DESTROY_MEMPOOL(instance));
627
628 glsl_type_singleton_decref();
629 _mesa_locale_fini();
630
631 driDestroyOptionCache(&instance->dri_options);
632 driDestroyOptionInfo(&instance->available_dri_options);
633
634 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
635
636 vk_free(&instance->alloc, instance);
637 }
638
639 static VkResult
640 radv_enumerate_devices(struct radv_instance *instance)
641 {
642 /* TODO: Check for more devices ? */
643 drmDevicePtr devices[8];
644 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
645 int max_devices;
646
647 instance->physicalDeviceCount = 0;
648
649 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
650
651 if (instance->debug_flags & RADV_DEBUG_STARTUP)
652 radv_logi("Found %d drm nodes", max_devices);
653
654 if (max_devices < 1)
655 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
656
657 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
658 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
659 devices[i]->bustype == DRM_BUS_PCI &&
660 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
661
662 result = radv_physical_device_init(instance->physicalDevices +
663 instance->physicalDeviceCount,
664 instance,
665 devices[i]);
666 if (result == VK_SUCCESS)
667 ++instance->physicalDeviceCount;
668 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
669 break;
670 }
671 }
672 drmFreeDevices(devices, max_devices);
673
674 return result;
675 }
676
677 VkResult radv_EnumeratePhysicalDevices(
678 VkInstance _instance,
679 uint32_t* pPhysicalDeviceCount,
680 VkPhysicalDevice* pPhysicalDevices)
681 {
682 RADV_FROM_HANDLE(radv_instance, instance, _instance);
683 VkResult result;
684
685 if (instance->physicalDeviceCount < 0) {
686 result = radv_enumerate_devices(instance);
687 if (result != VK_SUCCESS &&
688 result != VK_ERROR_INCOMPATIBLE_DRIVER)
689 return result;
690 }
691
692 if (!pPhysicalDevices) {
693 *pPhysicalDeviceCount = instance->physicalDeviceCount;
694 } else {
695 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
696 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
697 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
698 }
699
700 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
701 : VK_SUCCESS;
702 }
703
704 VkResult radv_EnumeratePhysicalDeviceGroups(
705 VkInstance _instance,
706 uint32_t* pPhysicalDeviceGroupCount,
707 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
708 {
709 RADV_FROM_HANDLE(radv_instance, instance, _instance);
710 VkResult result;
711
712 if (instance->physicalDeviceCount < 0) {
713 result = radv_enumerate_devices(instance);
714 if (result != VK_SUCCESS &&
715 result != VK_ERROR_INCOMPATIBLE_DRIVER)
716 return result;
717 }
718
719 if (!pPhysicalDeviceGroupProperties) {
720 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
721 } else {
722 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
723 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
724 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
725 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
726 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
727 }
728 }
729 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
730 : VK_SUCCESS;
731 }
732
733 void radv_GetPhysicalDeviceFeatures(
734 VkPhysicalDevice physicalDevice,
735 VkPhysicalDeviceFeatures* pFeatures)
736 {
737 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
738 memset(pFeatures, 0, sizeof(*pFeatures));
739
740 *pFeatures = (VkPhysicalDeviceFeatures) {
741 .robustBufferAccess = true,
742 .fullDrawIndexUint32 = true,
743 .imageCubeArray = true,
744 .independentBlend = true,
745 .geometryShader = true,
746 .tessellationShader = true,
747 .sampleRateShading = true,
748 .dualSrcBlend = true,
749 .logicOp = true,
750 .multiDrawIndirect = true,
751 .drawIndirectFirstInstance = true,
752 .depthClamp = true,
753 .depthBiasClamp = true,
754 .fillModeNonSolid = true,
755 .depthBounds = true,
756 .wideLines = true,
757 .largePoints = true,
758 .alphaToOne = true,
759 .multiViewport = true,
760 .samplerAnisotropy = true,
761 .textureCompressionETC2 = radv_device_supports_etc(pdevice),
762 .textureCompressionASTC_LDR = false,
763 .textureCompressionBC = true,
764 .occlusionQueryPrecise = true,
765 .pipelineStatisticsQuery = true,
766 .vertexPipelineStoresAndAtomics = true,
767 .fragmentStoresAndAtomics = true,
768 .shaderTessellationAndGeometryPointSize = true,
769 .shaderImageGatherExtended = true,
770 .shaderStorageImageExtendedFormats = true,
771 .shaderStorageImageMultisample = pdevice->rad_info.chip_class >= VI,
772 .shaderUniformBufferArrayDynamicIndexing = true,
773 .shaderSampledImageArrayDynamicIndexing = true,
774 .shaderStorageBufferArrayDynamicIndexing = true,
775 .shaderStorageImageArrayDynamicIndexing = true,
776 .shaderStorageImageReadWithoutFormat = true,
777 .shaderStorageImageWriteWithoutFormat = true,
778 .shaderClipDistance = true,
779 .shaderCullDistance = true,
780 .shaderFloat64 = true,
781 .shaderInt64 = true,
782 .shaderInt16 = pdevice->rad_info.chip_class >= GFX9,
783 .sparseBinding = true,
784 .variableMultisampleRate = true,
785 .inheritedQueries = true,
786 };
787 }
788
789 void radv_GetPhysicalDeviceFeatures2(
790 VkPhysicalDevice physicalDevice,
791 VkPhysicalDeviceFeatures2 *pFeatures)
792 {
793 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
794 vk_foreach_struct(ext, pFeatures->pNext) {
795 switch (ext->sType) {
796 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES: {
797 VkPhysicalDeviceVariablePointerFeatures *features = (void *)ext;
798 features->variablePointersStorageBuffer = true;
799 features->variablePointers = true;
800 break;
801 }
802 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES: {
803 VkPhysicalDeviceMultiviewFeatures *features = (VkPhysicalDeviceMultiviewFeatures*)ext;
804 features->multiview = true;
805 features->multiviewGeometryShader = true;
806 features->multiviewTessellationShader = true;
807 break;
808 }
809 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
810 VkPhysicalDeviceShaderDrawParameterFeatures *features =
811 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
812 features->shaderDrawParameters = true;
813 break;
814 }
815 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
816 VkPhysicalDeviceProtectedMemoryFeatures *features =
817 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
818 features->protectedMemory = false;
819 break;
820 }
821 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
822 VkPhysicalDevice16BitStorageFeatures *features =
823 (VkPhysicalDevice16BitStorageFeatures*)ext;
824 bool enabled = pdevice->rad_info.chip_class >= VI;
825 features->storageBuffer16BitAccess = enabled;
826 features->uniformAndStorageBuffer16BitAccess = enabled;
827 features->storagePushConstant16 = enabled;
828 features->storageInputOutput16 = enabled && HAVE_LLVM >= 0x900;
829 break;
830 }
831 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
832 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
833 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
834 features->samplerYcbcrConversion = true;
835 break;
836 }
837 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
838 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
839 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
840 features->shaderInputAttachmentArrayDynamicIndexing = true;
841 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
842 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
843 features->shaderUniformBufferArrayNonUniformIndexing = true;
844 features->shaderSampledImageArrayNonUniformIndexing = true;
845 features->shaderStorageBufferArrayNonUniformIndexing = true;
846 features->shaderStorageImageArrayNonUniformIndexing = true;
847 features->shaderInputAttachmentArrayNonUniformIndexing = true;
848 features->shaderUniformTexelBufferArrayNonUniformIndexing = true;
849 features->shaderStorageTexelBufferArrayNonUniformIndexing = true;
850 features->descriptorBindingUniformBufferUpdateAfterBind = true;
851 features->descriptorBindingSampledImageUpdateAfterBind = true;
852 features->descriptorBindingStorageImageUpdateAfterBind = true;
853 features->descriptorBindingStorageBufferUpdateAfterBind = true;
854 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
855 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
856 features->descriptorBindingUpdateUnusedWhilePending = true;
857 features->descriptorBindingPartiallyBound = true;
858 features->descriptorBindingVariableDescriptorCount = true;
859 features->runtimeDescriptorArray = true;
860 break;
861 }
862 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
863 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
864 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
865 features->conditionalRendering = true;
866 features->inheritedConditionalRendering = false;
867 break;
868 }
869 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_FEATURES_EXT: {
870 VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *features =
871 (VkPhysicalDeviceVertexAttributeDivisorFeaturesEXT *)ext;
872 features->vertexAttributeInstanceRateDivisor = VK_TRUE;
873 features->vertexAttributeInstanceRateZeroDivisor = VK_TRUE;
874 break;
875 }
876 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_FEATURES_EXT: {
877 VkPhysicalDeviceTransformFeedbackFeaturesEXT *features =
878 (VkPhysicalDeviceTransformFeedbackFeaturesEXT*)ext;
879 features->transformFeedback = true;
880 features->geometryStreams = true;
881 break;
882 }
883 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SCALAR_BLOCK_LAYOUT_FEATURES_EXT: {
884 VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *features =
885 (VkPhysicalDeviceScalarBlockLayoutFeaturesEXT *)ext;
886 features->scalarBlockLayout = pdevice->rad_info.chip_class >= CIK;
887 break;
888 }
889 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MEMORY_PRIORITY_FEATURES_EXT: {
890 VkPhysicalDeviceMemoryPriorityFeaturesEXT *features =
891 (VkPhysicalDeviceMemoryPriorityFeaturesEXT *)ext;
892 features->memoryPriority = VK_TRUE;
893 break;
894 }
895 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_BUFFER_ADDRESS_FEATURES_EXT: {
896 VkPhysicalDeviceBufferAddressFeaturesEXT *features =
897 (VkPhysicalDeviceBufferAddressFeaturesEXT *)ext;
898 features->bufferDeviceAddress = true;
899 features->bufferDeviceAddressCaptureReplay = false;
900 features->bufferDeviceAddressMultiDevice = false;
901 break;
902 }
903 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DEPTH_CLIP_ENABLE_FEATURES_EXT: {
904 VkPhysicalDeviceDepthClipEnableFeaturesEXT *features =
905 (VkPhysicalDeviceDepthClipEnableFeaturesEXT *)ext;
906 features->depthClipEnable = true;
907 break;
908 }
909 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_HOST_QUERY_RESET_FEATURES_EXT: {
910 VkPhysicalDeviceHostQueryResetFeaturesEXT *features =
911 (VkPhysicalDeviceHostQueryResetFeaturesEXT *)ext;
912 features->hostQueryReset = true;
913 break;
914 }
915 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_8BIT_STORAGE_FEATURES_KHR: {
916 VkPhysicalDevice8BitStorageFeaturesKHR *features =
917 (VkPhysicalDevice8BitStorageFeaturesKHR*)ext;
918 bool enabled = pdevice->rad_info.chip_class >= VI;
919 features->storageBuffer8BitAccess = enabled;
920 features->uniformAndStorageBuffer8BitAccess = enabled;
921 features->storagePushConstant8 = enabled;
922 break;
923 }
924 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_FLOAT16_INT8_FEATURES_KHR: {
925 VkPhysicalDeviceFloat16Int8FeaturesKHR *features =
926 (VkPhysicalDeviceFloat16Int8FeaturesKHR*)ext;
927 features->shaderFloat16 = pdevice->rad_info.chip_class >= VI && HAVE_LLVM >= 0x0800;
928 features->shaderInt8 = true;
929 break;
930 }
931 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_ATOMIC_INT64_FEATURES_KHR: {
932 VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *features =
933 (VkPhysicalDeviceShaderAtomicInt64FeaturesKHR *)ext;
934 /* TODO: Enable this once the driver supports 64-bit
935 * compare&swap atomic operations.
936 */
937 features->shaderBufferInt64Atomics = false;
938 features->shaderSharedInt64Atomics = false;
939 break;
940 }
941 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_FEATURES_EXT: {
942 VkPhysicalDeviceInlineUniformBlockFeaturesEXT *features =
943 (VkPhysicalDeviceInlineUniformBlockFeaturesEXT *)ext;
944
945 features->inlineUniformBlock = true;
946 features->descriptorBindingInlineUniformBlockUpdateAfterBind = true;
947 break;
948 }
949 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_COMPUTE_SHADER_DERIVATIVES_FEATURES_NV: {
950 VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *features =
951 (VkPhysicalDeviceComputeShaderDerivativesFeaturesNV *)ext;
952 features->computeDerivativeGroupQuads = false;
953 features->computeDerivativeGroupLinear = true;
954 break;
955 }
956 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_YCBCR_IMAGE_ARRAYS_FEATURES_EXT: {
957 VkPhysicalDeviceYcbcrImageArraysFeaturesEXT *features =
958 (VkPhysicalDeviceYcbcrImageArraysFeaturesEXT*)ext;
959 features->ycbcrImageArrays = true;
960 break;
961 }
962 default:
963 break;
964 }
965 }
966 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
967 }
968
969 void radv_GetPhysicalDeviceProperties(
970 VkPhysicalDevice physicalDevice,
971 VkPhysicalDeviceProperties* pProperties)
972 {
973 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
974 VkSampleCountFlags sample_counts = 0xf;
975
976 /* make sure that the entire descriptor set is addressable with a signed
977 * 32-bit int. So the sum of all limits scaled by descriptor size has to
978 * be at most 2 GiB. the combined image & samples object count as one of
979 * both. This limit is for the pipeline layout, not for the set layout, but
980 * there is no set limit, so we just set a pipeline limit. I don't think
981 * any app is going to hit this soon. */
982 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
983 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
984 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
985 32 /* sampler, largest when combined with image */ +
986 64 /* sampled image */ +
987 64 /* storage image */);
988
989 VkPhysicalDeviceLimits limits = {
990 .maxImageDimension1D = (1 << 14),
991 .maxImageDimension2D = (1 << 14),
992 .maxImageDimension3D = (1 << 11),
993 .maxImageDimensionCube = (1 << 14),
994 .maxImageArrayLayers = (1 << 11),
995 .maxTexelBufferElements = 128 * 1024 * 1024,
996 .maxUniformBufferRange = UINT32_MAX,
997 .maxStorageBufferRange = UINT32_MAX,
998 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
999 .maxMemoryAllocationCount = UINT32_MAX,
1000 .maxSamplerAllocationCount = 64 * 1024,
1001 .bufferImageGranularity = 64, /* A cache line */
1002 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
1003 .maxBoundDescriptorSets = MAX_SETS,
1004 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
1005 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
1006 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
1007 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
1008 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
1009 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
1010 .maxPerStageResources = max_descriptor_set_size,
1011 .maxDescriptorSetSamplers = max_descriptor_set_size,
1012 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
1013 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
1014 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
1015 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
1016 .maxDescriptorSetSampledImages = max_descriptor_set_size,
1017 .maxDescriptorSetStorageImages = max_descriptor_set_size,
1018 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
1019 .maxVertexInputAttributes = MAX_VERTEX_ATTRIBS,
1020 .maxVertexInputBindings = MAX_VBS,
1021 .maxVertexInputAttributeOffset = 2047,
1022 .maxVertexInputBindingStride = 2048,
1023 .maxVertexOutputComponents = 128,
1024 .maxTessellationGenerationLevel = 64,
1025 .maxTessellationPatchSize = 32,
1026 .maxTessellationControlPerVertexInputComponents = 128,
1027 .maxTessellationControlPerVertexOutputComponents = 128,
1028 .maxTessellationControlPerPatchOutputComponents = 120,
1029 .maxTessellationControlTotalOutputComponents = 4096,
1030 .maxTessellationEvaluationInputComponents = 128,
1031 .maxTessellationEvaluationOutputComponents = 128,
1032 .maxGeometryShaderInvocations = 127,
1033 .maxGeometryInputComponents = 64,
1034 .maxGeometryOutputComponents = 128,
1035 .maxGeometryOutputVertices = 256,
1036 .maxGeometryTotalOutputComponents = 1024,
1037 .maxFragmentInputComponents = 128,
1038 .maxFragmentOutputAttachments = 8,
1039 .maxFragmentDualSrcAttachments = 1,
1040 .maxFragmentCombinedOutputResources = 8,
1041 .maxComputeSharedMemorySize = 32768,
1042 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
1043 .maxComputeWorkGroupInvocations = 2048,
1044 .maxComputeWorkGroupSize = {
1045 2048,
1046 2048,
1047 2048
1048 },
1049 .subPixelPrecisionBits = 8,
1050 .subTexelPrecisionBits = 8,
1051 .mipmapPrecisionBits = 8,
1052 .maxDrawIndexedIndexValue = UINT32_MAX,
1053 .maxDrawIndirectCount = UINT32_MAX,
1054 .maxSamplerLodBias = 16,
1055 .maxSamplerAnisotropy = 16,
1056 .maxViewports = MAX_VIEWPORTS,
1057 .maxViewportDimensions = { (1 << 14), (1 << 14) },
1058 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
1059 .viewportSubPixelBits = 8,
1060 .minMemoryMapAlignment = 4096, /* A page */
1061 .minTexelBufferOffsetAlignment = 1,
1062 .minUniformBufferOffsetAlignment = 4,
1063 .minStorageBufferOffsetAlignment = 4,
1064 .minTexelOffset = -32,
1065 .maxTexelOffset = 31,
1066 .minTexelGatherOffset = -32,
1067 .maxTexelGatherOffset = 31,
1068 .minInterpolationOffset = -2,
1069 .maxInterpolationOffset = 2,
1070 .subPixelInterpolationOffsetBits = 8,
1071 .maxFramebufferWidth = (1 << 14),
1072 .maxFramebufferHeight = (1 << 14),
1073 .maxFramebufferLayers = (1 << 10),
1074 .framebufferColorSampleCounts = sample_counts,
1075 .framebufferDepthSampleCounts = sample_counts,
1076 .framebufferStencilSampleCounts = sample_counts,
1077 .framebufferNoAttachmentsSampleCounts = sample_counts,
1078 .maxColorAttachments = MAX_RTS,
1079 .sampledImageColorSampleCounts = sample_counts,
1080 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
1081 .sampledImageDepthSampleCounts = sample_counts,
1082 .sampledImageStencilSampleCounts = sample_counts,
1083 .storageImageSampleCounts = pdevice->rad_info.chip_class >= VI ? sample_counts : VK_SAMPLE_COUNT_1_BIT,
1084 .maxSampleMaskWords = 1,
1085 .timestampComputeAndGraphics = true,
1086 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
1087 .maxClipDistances = 8,
1088 .maxCullDistances = 8,
1089 .maxCombinedClipAndCullDistances = 8,
1090 .discreteQueuePriorities = 2,
1091 .pointSizeRange = { 0.0, 8192.0 },
1092 .lineWidthRange = { 0.0, 7.9921875 },
1093 .pointSizeGranularity = (1.0 / 8.0),
1094 .lineWidthGranularity = (1.0 / 128.0),
1095 .strictLines = false, /* FINISHME */
1096 .standardSampleLocations = true,
1097 .optimalBufferCopyOffsetAlignment = 128,
1098 .optimalBufferCopyRowPitchAlignment = 128,
1099 .nonCoherentAtomSize = 64,
1100 };
1101
1102 *pProperties = (VkPhysicalDeviceProperties) {
1103 .apiVersion = radv_physical_device_api_version(pdevice),
1104 .driverVersion = vk_get_driver_version(),
1105 .vendorID = ATI_VENDOR_ID,
1106 .deviceID = pdevice->rad_info.pci_id,
1107 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
1108 .limits = limits,
1109 .sparseProperties = {0},
1110 };
1111
1112 strcpy(pProperties->deviceName, pdevice->name);
1113 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
1114 }
1115
1116 void radv_GetPhysicalDeviceProperties2(
1117 VkPhysicalDevice physicalDevice,
1118 VkPhysicalDeviceProperties2 *pProperties)
1119 {
1120 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1121 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
1122
1123 vk_foreach_struct(ext, pProperties->pNext) {
1124 switch (ext->sType) {
1125 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
1126 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
1127 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
1128 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
1129 break;
1130 }
1131 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES: {
1132 VkPhysicalDeviceIDProperties *properties = (VkPhysicalDeviceIDProperties*)ext;
1133 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
1134 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
1135 properties->deviceLUIDValid = false;
1136 break;
1137 }
1138 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES: {
1139 VkPhysicalDeviceMultiviewProperties *properties = (VkPhysicalDeviceMultiviewProperties*)ext;
1140 properties->maxMultiviewViewCount = MAX_VIEWS;
1141 properties->maxMultiviewInstanceIndex = INT_MAX;
1142 break;
1143 }
1144 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES: {
1145 VkPhysicalDevicePointClippingProperties *properties =
1146 (VkPhysicalDevicePointClippingProperties*)ext;
1147 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES;
1148 break;
1149 }
1150 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1151 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1152 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1153 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1154 break;
1155 }
1156 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1157 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1158 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1159 properties->minImportedHostPointerAlignment = 4096;
1160 break;
1161 }
1162 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1163 VkPhysicalDeviceSubgroupProperties *properties =
1164 (VkPhysicalDeviceSubgroupProperties*)ext;
1165 properties->subgroupSize = 64;
1166 properties->supportedStages = VK_SHADER_STAGE_ALL;
1167 properties->supportedOperations =
1168 VK_SUBGROUP_FEATURE_BASIC_BIT |
1169 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1170 VK_SUBGROUP_FEATURE_QUAD_BIT |
1171 VK_SUBGROUP_FEATURE_VOTE_BIT;
1172 if (pdevice->rad_info.chip_class >= VI) {
1173 properties->supportedOperations |=
1174 VK_SUBGROUP_FEATURE_ARITHMETIC_BIT |
1175 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1176 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1177 }
1178 properties->quadOperationsInAllStages = true;
1179 break;
1180 }
1181 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1182 VkPhysicalDeviceMaintenance3Properties *properties =
1183 (VkPhysicalDeviceMaintenance3Properties*)ext;
1184 /* Make sure everything is addressable by a signed 32-bit int, and
1185 * our largest descriptors are 96 bytes. */
1186 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1187 /* Our buffer size fields allow only this much */
1188 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1189 break;
1190 }
1191 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1192 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1193 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1194 /* GFX6-8 only support single channel min/max filter. */
1195 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1196 properties->filterMinmaxSingleComponentFormats = true;
1197 break;
1198 }
1199 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1200 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1201 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1202
1203 /* Shader engines. */
1204 properties->shaderEngineCount =
1205 pdevice->rad_info.max_se;
1206 properties->shaderArraysPerEngineCount =
1207 pdevice->rad_info.max_sh_per_se;
1208 properties->computeUnitsPerShaderArray =
1209 pdevice->rad_info.num_good_cu_per_sh;
1210 properties->simdPerComputeUnit = 4;
1211 properties->wavefrontsPerSimd =
1212 pdevice->rad_info.family == CHIP_TONGA ||
1213 pdevice->rad_info.family == CHIP_ICELAND ||
1214 pdevice->rad_info.family == CHIP_POLARIS10 ||
1215 pdevice->rad_info.family == CHIP_POLARIS11 ||
1216 pdevice->rad_info.family == CHIP_POLARIS12 ||
1217 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1218 properties->wavefrontSize = 64;
1219
1220 /* SGPR. */
1221 properties->sgprsPerSimd =
1222 ac_get_num_physical_sgprs(pdevice->rad_info.chip_class);
1223 properties->minSgprAllocation =
1224 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1225 properties->maxSgprAllocation =
1226 pdevice->rad_info.family == CHIP_TONGA ||
1227 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1228 properties->sgprAllocationGranularity =
1229 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1230
1231 /* VGPR. */
1232 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1233 properties->minVgprAllocation = 4;
1234 properties->maxVgprAllocation = 256;
1235 properties->vgprAllocationGranularity = 4;
1236 break;
1237 }
1238 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1239 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1240 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1241 properties->maxVertexAttribDivisor = UINT32_MAX;
1242 break;
1243 }
1244 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1245 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1246 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1247 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1248 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1249 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1250 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1251 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1252 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1253 properties->robustBufferAccessUpdateAfterBind = false;
1254 properties->quadDivergentImplicitLod = false;
1255
1256 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS -
1257 MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_INLINE_UNIFORM_BLOCK_COUNT) /
1258 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1259 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1260 32 /* sampler, largest when combined with image */ +
1261 64 /* sampled image */ +
1262 64 /* storage image */);
1263 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1264 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1265 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1266 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1267 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1268 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1269 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1270 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1271 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1272 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1273 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1274 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1275 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1276 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1277 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1278 break;
1279 }
1280 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1281 VkPhysicalDeviceProtectedMemoryProperties *properties =
1282 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1283 properties->protectedNoFault = false;
1284 break;
1285 }
1286 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONSERVATIVE_RASTERIZATION_PROPERTIES_EXT: {
1287 VkPhysicalDeviceConservativeRasterizationPropertiesEXT *properties =
1288 (VkPhysicalDeviceConservativeRasterizationPropertiesEXT *)ext;
1289 properties->primitiveOverestimationSize = 0;
1290 properties->maxExtraPrimitiveOverestimationSize = 0;
1291 properties->extraPrimitiveOverestimationSizeGranularity = 0;
1292 properties->primitiveUnderestimation = VK_FALSE;
1293 properties->conservativePointAndLineRasterization = VK_FALSE;
1294 properties->degenerateTrianglesRasterized = VK_FALSE;
1295 properties->degenerateLinesRasterized = VK_FALSE;
1296 properties->fullyCoveredFragmentShaderInputVariable = VK_FALSE;
1297 properties->conservativeRasterizationPostDepthCoverage = VK_FALSE;
1298 break;
1299 }
1300 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PCI_BUS_INFO_PROPERTIES_EXT: {
1301 VkPhysicalDevicePCIBusInfoPropertiesEXT *properties =
1302 (VkPhysicalDevicePCIBusInfoPropertiesEXT *)ext;
1303 properties->pciDomain = pdevice->bus_info.domain;
1304 properties->pciBus = pdevice->bus_info.bus;
1305 properties->pciDevice = pdevice->bus_info.dev;
1306 properties->pciFunction = pdevice->bus_info.func;
1307 break;
1308 }
1309 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DRIVER_PROPERTIES_KHR: {
1310 VkPhysicalDeviceDriverPropertiesKHR *driver_props =
1311 (VkPhysicalDeviceDriverPropertiesKHR *) ext;
1312
1313 driver_props->driverID = VK_DRIVER_ID_MESA_RADV_KHR;
1314 memset(driver_props->driverName, 0, VK_MAX_DRIVER_NAME_SIZE_KHR);
1315 strcpy(driver_props->driverName, "radv");
1316
1317 memset(driver_props->driverInfo, 0, VK_MAX_DRIVER_INFO_SIZE_KHR);
1318 snprintf(driver_props->driverInfo, VK_MAX_DRIVER_INFO_SIZE_KHR,
1319 "Mesa " PACKAGE_VERSION MESA_GIT_SHA1
1320 " (LLVM " MESA_LLVM_VERSION_STRING ")");
1321
1322 driver_props->conformanceVersion = (VkConformanceVersionKHR) {
1323 .major = 1,
1324 .minor = 1,
1325 .subminor = 2,
1326 .patch = 0,
1327 };
1328 break;
1329 }
1330 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_TRANSFORM_FEEDBACK_PROPERTIES_EXT: {
1331 VkPhysicalDeviceTransformFeedbackPropertiesEXT *properties =
1332 (VkPhysicalDeviceTransformFeedbackPropertiesEXT *)ext;
1333 properties->maxTransformFeedbackStreams = MAX_SO_STREAMS;
1334 properties->maxTransformFeedbackBuffers = MAX_SO_BUFFERS;
1335 properties->maxTransformFeedbackBufferSize = UINT32_MAX;
1336 properties->maxTransformFeedbackStreamDataSize = 512;
1337 properties->maxTransformFeedbackBufferDataSize = UINT32_MAX;
1338 properties->maxTransformFeedbackBufferDataStride = 512;
1339 properties->transformFeedbackQueries = true;
1340 properties->transformFeedbackStreamsLinesTriangles = false;
1341 properties->transformFeedbackRasterizationStreamSelect = false;
1342 properties->transformFeedbackDraw = true;
1343 break;
1344 }
1345 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_INLINE_UNIFORM_BLOCK_PROPERTIES_EXT: {
1346 VkPhysicalDeviceInlineUniformBlockPropertiesEXT *props =
1347 (VkPhysicalDeviceInlineUniformBlockPropertiesEXT *)ext;
1348
1349 props->maxInlineUniformBlockSize = MAX_INLINE_UNIFORM_BLOCK_SIZE;
1350 props->maxPerStageDescriptorInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1351 props->maxPerStageDescriptorUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_SIZE * MAX_SETS;
1352 props->maxDescriptorSetInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1353 props->maxDescriptorSetUpdateAfterBindInlineUniformBlocks = MAX_INLINE_UNIFORM_BLOCK_COUNT;
1354 break;
1355 }
1356 default:
1357 break;
1358 }
1359 }
1360 }
1361
1362 static void radv_get_physical_device_queue_family_properties(
1363 struct radv_physical_device* pdevice,
1364 uint32_t* pCount,
1365 VkQueueFamilyProperties** pQueueFamilyProperties)
1366 {
1367 int num_queue_families = 1;
1368 int idx;
1369 if (pdevice->rad_info.num_compute_rings > 0 &&
1370 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1371 num_queue_families++;
1372
1373 if (pQueueFamilyProperties == NULL) {
1374 *pCount = num_queue_families;
1375 return;
1376 }
1377
1378 if (!*pCount)
1379 return;
1380
1381 idx = 0;
1382 if (*pCount >= 1) {
1383 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1384 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1385 VK_QUEUE_COMPUTE_BIT |
1386 VK_QUEUE_TRANSFER_BIT |
1387 VK_QUEUE_SPARSE_BINDING_BIT,
1388 .queueCount = 1,
1389 .timestampValidBits = 64,
1390 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1391 };
1392 idx++;
1393 }
1394
1395 if (pdevice->rad_info.num_compute_rings > 0 &&
1396 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1397 if (*pCount > idx) {
1398 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1399 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1400 VK_QUEUE_TRANSFER_BIT |
1401 VK_QUEUE_SPARSE_BINDING_BIT,
1402 .queueCount = pdevice->rad_info.num_compute_rings,
1403 .timestampValidBits = 64,
1404 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1405 };
1406 idx++;
1407 }
1408 }
1409 *pCount = idx;
1410 }
1411
1412 void radv_GetPhysicalDeviceQueueFamilyProperties(
1413 VkPhysicalDevice physicalDevice,
1414 uint32_t* pCount,
1415 VkQueueFamilyProperties* pQueueFamilyProperties)
1416 {
1417 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1418 if (!pQueueFamilyProperties) {
1419 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1420 return;
1421 }
1422 VkQueueFamilyProperties *properties[] = {
1423 pQueueFamilyProperties + 0,
1424 pQueueFamilyProperties + 1,
1425 pQueueFamilyProperties + 2,
1426 };
1427 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1428 assert(*pCount <= 3);
1429 }
1430
1431 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1432 VkPhysicalDevice physicalDevice,
1433 uint32_t* pCount,
1434 VkQueueFamilyProperties2 *pQueueFamilyProperties)
1435 {
1436 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1437 if (!pQueueFamilyProperties) {
1438 radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1439 return;
1440 }
1441 VkQueueFamilyProperties *properties[] = {
1442 &pQueueFamilyProperties[0].queueFamilyProperties,
1443 &pQueueFamilyProperties[1].queueFamilyProperties,
1444 &pQueueFamilyProperties[2].queueFamilyProperties,
1445 };
1446 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1447 assert(*pCount <= 3);
1448 }
1449
1450 void radv_GetPhysicalDeviceMemoryProperties(
1451 VkPhysicalDevice physicalDevice,
1452 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1453 {
1454 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1455
1456 *pMemoryProperties = physical_device->memory_properties;
1457 }
1458
1459 static void
1460 radv_get_memory_budget_properties(VkPhysicalDevice physicalDevice,
1461 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memoryBudget)
1462 {
1463 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
1464 VkPhysicalDeviceMemoryProperties *memory_properties = &device->memory_properties;
1465 uint64_t visible_vram_size = radv_get_visible_vram_size(device);
1466 uint64_t vram_size = radv_get_vram_size(device);
1467 uint64_t gtt_size = device->rad_info.gart_size;
1468 uint64_t heap_budget, heap_usage;
1469
1470 /* For all memory heaps, the computation of budget is as follow:
1471 * heap_budget = heap_size - global_heap_usage + app_heap_usage
1472 *
1473 * The Vulkan spec 1.1.97 says that the budget should include any
1474 * currently allocated device memory.
1475 *
1476 * Note that the application heap usages are not really accurate (eg.
1477 * in presence of shared buffers).
1478 */
1479 if (vram_size) {
1480 heap_usage = device->ws->query_value(device->ws,
1481 RADEON_ALLOCATED_VRAM);
1482
1483 heap_budget = vram_size -
1484 device->ws->query_value(device->ws, RADEON_VRAM_USAGE) +
1485 heap_usage;
1486
1487 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM] = heap_budget;
1488 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM] = heap_usage;
1489 }
1490
1491 if (visible_vram_size) {
1492 heap_usage = device->ws->query_value(device->ws,
1493 RADEON_ALLOCATED_VRAM_VIS);
1494
1495 heap_budget = visible_vram_size -
1496 device->ws->query_value(device->ws, RADEON_VRAM_VIS_USAGE) +
1497 heap_usage;
1498
1499 memoryBudget->heapBudget[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_budget;
1500 memoryBudget->heapUsage[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = heap_usage;
1501 }
1502
1503 if (gtt_size) {
1504 heap_usage = device->ws->query_value(device->ws,
1505 RADEON_ALLOCATED_GTT);
1506
1507 heap_budget = gtt_size -
1508 device->ws->query_value(device->ws, RADEON_GTT_USAGE) +
1509 heap_usage;
1510
1511 memoryBudget->heapBudget[RADV_MEM_HEAP_GTT] = heap_budget;
1512 memoryBudget->heapUsage[RADV_MEM_HEAP_GTT] = heap_usage;
1513 }
1514
1515 /* The heapBudget and heapUsage values must be zero for array elements
1516 * greater than or equal to
1517 * VkPhysicalDeviceMemoryProperties::memoryHeapCount.
1518 */
1519 for (uint32_t i = memory_properties->memoryHeapCount; i < VK_MAX_MEMORY_HEAPS; i++) {
1520 memoryBudget->heapBudget[i] = 0;
1521 memoryBudget->heapUsage[i] = 0;
1522 }
1523 }
1524
1525 void radv_GetPhysicalDeviceMemoryProperties2(
1526 VkPhysicalDevice physicalDevice,
1527 VkPhysicalDeviceMemoryProperties2 *pMemoryProperties)
1528 {
1529 radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1530 &pMemoryProperties->memoryProperties);
1531
1532 VkPhysicalDeviceMemoryBudgetPropertiesEXT *memory_budget =
1533 vk_find_struct(pMemoryProperties->pNext,
1534 PHYSICAL_DEVICE_MEMORY_BUDGET_PROPERTIES_EXT);
1535 if (memory_budget)
1536 radv_get_memory_budget_properties(physicalDevice, memory_budget);
1537 }
1538
1539 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1540 VkDevice _device,
1541 VkExternalMemoryHandleTypeFlagBits handleType,
1542 const void *pHostPointer,
1543 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1544 {
1545 RADV_FROM_HANDLE(radv_device, device, _device);
1546
1547 switch (handleType)
1548 {
1549 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1550 const struct radv_physical_device *physical_device = device->physical_device;
1551 uint32_t memoryTypeBits = 0;
1552 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1553 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1554 memoryTypeBits = (1 << i);
1555 break;
1556 }
1557 }
1558 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1559 return VK_SUCCESS;
1560 }
1561 default:
1562 return VK_ERROR_INVALID_EXTERNAL_HANDLE;
1563 }
1564 }
1565
1566 static enum radeon_ctx_priority
1567 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1568 {
1569 /* Default to MEDIUM when a specific global priority isn't requested */
1570 if (!pObj)
1571 return RADEON_CTX_PRIORITY_MEDIUM;
1572
1573 switch(pObj->globalPriority) {
1574 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1575 return RADEON_CTX_PRIORITY_REALTIME;
1576 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1577 return RADEON_CTX_PRIORITY_HIGH;
1578 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1579 return RADEON_CTX_PRIORITY_MEDIUM;
1580 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1581 return RADEON_CTX_PRIORITY_LOW;
1582 default:
1583 unreachable("Illegal global priority value");
1584 return RADEON_CTX_PRIORITY_INVALID;
1585 }
1586 }
1587
1588 static int
1589 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1590 uint32_t queue_family_index, int idx,
1591 VkDeviceQueueCreateFlags flags,
1592 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1593 {
1594 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1595 queue->device = device;
1596 queue->queue_family_index = queue_family_index;
1597 queue->queue_idx = idx;
1598 queue->priority = radv_get_queue_global_priority(global_priority);
1599 queue->flags = flags;
1600
1601 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1602 if (!queue->hw_ctx)
1603 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1604
1605 return VK_SUCCESS;
1606 }
1607
1608 static void
1609 radv_queue_finish(struct radv_queue *queue)
1610 {
1611 if (queue->hw_ctx)
1612 queue->device->ws->ctx_destroy(queue->hw_ctx);
1613
1614 if (queue->initial_full_flush_preamble_cs)
1615 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1616 if (queue->initial_preamble_cs)
1617 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1618 if (queue->continue_preamble_cs)
1619 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1620 if (queue->descriptor_bo)
1621 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1622 if (queue->scratch_bo)
1623 queue->device->ws->buffer_destroy(queue->scratch_bo);
1624 if (queue->esgs_ring_bo)
1625 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1626 if (queue->gsvs_ring_bo)
1627 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1628 if (queue->tess_rings_bo)
1629 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1630 if (queue->compute_scratch_bo)
1631 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1632 }
1633
1634 static void
1635 radv_bo_list_init(struct radv_bo_list *bo_list)
1636 {
1637 pthread_mutex_init(&bo_list->mutex, NULL);
1638 bo_list->list.count = bo_list->capacity = 0;
1639 bo_list->list.bos = NULL;
1640 }
1641
1642 static void
1643 radv_bo_list_finish(struct radv_bo_list *bo_list)
1644 {
1645 free(bo_list->list.bos);
1646 pthread_mutex_destroy(&bo_list->mutex);
1647 }
1648
1649 static VkResult radv_bo_list_add(struct radv_device *device,
1650 struct radeon_winsys_bo *bo)
1651 {
1652 struct radv_bo_list *bo_list = &device->bo_list;
1653
1654 if (bo->is_local)
1655 return VK_SUCCESS;
1656
1657 if (unlikely(!device->use_global_bo_list))
1658 return VK_SUCCESS;
1659
1660 pthread_mutex_lock(&bo_list->mutex);
1661 if (bo_list->list.count == bo_list->capacity) {
1662 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1663 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1664
1665 if (!data) {
1666 pthread_mutex_unlock(&bo_list->mutex);
1667 return VK_ERROR_OUT_OF_HOST_MEMORY;
1668 }
1669
1670 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1671 bo_list->capacity = capacity;
1672 }
1673
1674 bo_list->list.bos[bo_list->list.count++] = bo;
1675 pthread_mutex_unlock(&bo_list->mutex);
1676 return VK_SUCCESS;
1677 }
1678
1679 static void radv_bo_list_remove(struct radv_device *device,
1680 struct radeon_winsys_bo *bo)
1681 {
1682 struct radv_bo_list *bo_list = &device->bo_list;
1683
1684 if (bo->is_local)
1685 return;
1686
1687 if (unlikely(!device->use_global_bo_list))
1688 return;
1689
1690 pthread_mutex_lock(&bo_list->mutex);
1691 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1692 if (bo_list->list.bos[i] == bo) {
1693 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1694 --bo_list->list.count;
1695 break;
1696 }
1697 }
1698 pthread_mutex_unlock(&bo_list->mutex);
1699 }
1700
1701 static void
1702 radv_device_init_gs_info(struct radv_device *device)
1703 {
1704 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1705 device->physical_device->rad_info.family);
1706 }
1707
1708 static int radv_get_device_extension_index(const char *name)
1709 {
1710 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1711 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1712 return i;
1713 }
1714 return -1;
1715 }
1716
1717 static int
1718 radv_get_int_debug_option(const char *name, int default_value)
1719 {
1720 const char *str;
1721 int result;
1722
1723 str = getenv(name);
1724 if (!str) {
1725 result = default_value;
1726 } else {
1727 char *endptr;
1728
1729 result = strtol(str, &endptr, 0);
1730 if (str == endptr) {
1731 /* No digits founs. */
1732 result = default_value;
1733 }
1734 }
1735
1736 return result;
1737 }
1738
1739 VkResult radv_CreateDevice(
1740 VkPhysicalDevice physicalDevice,
1741 const VkDeviceCreateInfo* pCreateInfo,
1742 const VkAllocationCallbacks* pAllocator,
1743 VkDevice* pDevice)
1744 {
1745 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1746 VkResult result;
1747 struct radv_device *device;
1748
1749 bool keep_shader_info = false;
1750
1751 /* Check enabled features */
1752 if (pCreateInfo->pEnabledFeatures) {
1753 VkPhysicalDeviceFeatures supported_features;
1754 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1755 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1756 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1757 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1758 for (uint32_t i = 0; i < num_features; i++) {
1759 if (enabled_feature[i] && !supported_feature[i])
1760 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1761 }
1762 }
1763
1764 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1765 sizeof(*device), 8,
1766 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1767 if (!device)
1768 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1769
1770 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1771 device->instance = physical_device->instance;
1772 device->physical_device = physical_device;
1773
1774 device->ws = physical_device->ws;
1775 if (pAllocator)
1776 device->alloc = *pAllocator;
1777 else
1778 device->alloc = physical_device->instance->alloc;
1779
1780 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1781 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1782 int index = radv_get_device_extension_index(ext_name);
1783 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1784 vk_free(&device->alloc, device);
1785 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1786 }
1787
1788 device->enabled_extensions.extensions[index] = true;
1789 }
1790
1791 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1792
1793 /* With update after bind we can't attach bo's to the command buffer
1794 * from the descriptor set anymore, so we have to use a global BO list.
1795 */
1796 device->use_global_bo_list =
1797 (device->instance->perftest_flags & RADV_PERFTEST_BO_LIST) ||
1798 device->enabled_extensions.EXT_descriptor_indexing ||
1799 device->enabled_extensions.EXT_buffer_device_address;
1800
1801 mtx_init(&device->shader_slab_mutex, mtx_plain);
1802 list_inithead(&device->shader_slabs);
1803
1804 radv_bo_list_init(&device->bo_list);
1805
1806 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1807 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1808 uint32_t qfi = queue_create->queueFamilyIndex;
1809 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1810 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1811
1812 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1813
1814 device->queues[qfi] = vk_alloc(&device->alloc,
1815 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1816 if (!device->queues[qfi]) {
1817 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1818 goto fail;
1819 }
1820
1821 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1822
1823 device->queue_count[qfi] = queue_create->queueCount;
1824
1825 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1826 result = radv_queue_init(device, &device->queues[qfi][q],
1827 qfi, q, queue_create->flags,
1828 global_priority);
1829 if (result != VK_SUCCESS)
1830 goto fail;
1831 }
1832 }
1833
1834 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1835 !(device->instance->debug_flags & RADV_DEBUG_NOBINNING);
1836
1837 /* Disabled and not implemented for now. */
1838 device->dfsm_allowed = device->pbb_allowed &&
1839 (device->physical_device->rad_info.family == CHIP_RAVEN ||
1840 device->physical_device->rad_info.family == CHIP_RAVEN2);
1841
1842 #ifdef ANDROID
1843 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1844 #endif
1845
1846 /* The maximum number of scratch waves. Scratch space isn't divided
1847 * evenly between CUs. The number is only a function of the number of CUs.
1848 * We can decrease the constant to decrease the scratch buffer size.
1849 *
1850 * sctx->scratch_waves must be >= the maximum possible size of
1851 * 1 threadgroup, so that the hw doesn't hang from being unable
1852 * to start any.
1853 *
1854 * The recommended value is 4 per CU at most. Higher numbers don't
1855 * bring much benefit, but they still occupy chip resources (think
1856 * async compute). I've seen ~2% performance difference between 4 and 32.
1857 */
1858 uint32_t max_threads_per_block = 2048;
1859 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1860 max_threads_per_block / 64);
1861
1862 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1863
1864 if (device->physical_device->rad_info.chip_class >= CIK) {
1865 /* If the KMD allows it (there is a KMD hw register for it),
1866 * allow launching waves out-of-order.
1867 */
1868 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1869 }
1870
1871 radv_device_init_gs_info(device);
1872
1873 device->tess_offchip_block_dw_size =
1874 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1875 device->has_distributed_tess =
1876 device->physical_device->rad_info.chip_class >= VI &&
1877 device->physical_device->rad_info.max_se >= 2;
1878
1879 if (getenv("RADV_TRACE_FILE")) {
1880 const char *filename = getenv("RADV_TRACE_FILE");
1881
1882 keep_shader_info = true;
1883
1884 if (!radv_init_trace(device))
1885 goto fail;
1886
1887 fprintf(stderr, "*****************************************************************************\n");
1888 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1889 fprintf(stderr, "*****************************************************************************\n");
1890
1891 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1892 radv_dump_enabled_options(device, stderr);
1893 }
1894
1895 device->keep_shader_info = keep_shader_info;
1896
1897 result = radv_device_init_meta(device);
1898 if (result != VK_SUCCESS)
1899 goto fail;
1900
1901 radv_device_init_msaa(device);
1902
1903 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1904 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1905 switch (family) {
1906 case RADV_QUEUE_GENERAL:
1907 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1908 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1909 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1910 break;
1911 case RADV_QUEUE_COMPUTE:
1912 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1913 radeon_emit(device->empty_cs[family], 0);
1914 break;
1915 }
1916 device->ws->cs_finalize(device->empty_cs[family]);
1917 }
1918
1919 if (device->physical_device->rad_info.chip_class >= CIK)
1920 cik_create_gfx_config(device);
1921
1922 VkPipelineCacheCreateInfo ci;
1923 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1924 ci.pNext = NULL;
1925 ci.flags = 0;
1926 ci.pInitialData = NULL;
1927 ci.initialDataSize = 0;
1928 VkPipelineCache pc;
1929 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1930 &ci, NULL, &pc);
1931 if (result != VK_SUCCESS)
1932 goto fail_meta;
1933
1934 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1935
1936 device->force_aniso =
1937 MIN2(16, radv_get_int_debug_option("RADV_TEX_ANISO", -1));
1938 if (device->force_aniso >= 0) {
1939 fprintf(stderr, "radv: Forcing anisotropy filter to %ix\n",
1940 1 << util_logbase2(device->force_aniso));
1941 }
1942
1943 *pDevice = radv_device_to_handle(device);
1944 return VK_SUCCESS;
1945
1946 fail_meta:
1947 radv_device_finish_meta(device);
1948 fail:
1949 radv_bo_list_finish(&device->bo_list);
1950
1951 if (device->trace_bo)
1952 device->ws->buffer_destroy(device->trace_bo);
1953
1954 if (device->gfx_init)
1955 device->ws->buffer_destroy(device->gfx_init);
1956
1957 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1958 for (unsigned q = 0; q < device->queue_count[i]; q++)
1959 radv_queue_finish(&device->queues[i][q]);
1960 if (device->queue_count[i])
1961 vk_free(&device->alloc, device->queues[i]);
1962 }
1963
1964 vk_free(&device->alloc, device);
1965 return result;
1966 }
1967
1968 void radv_DestroyDevice(
1969 VkDevice _device,
1970 const VkAllocationCallbacks* pAllocator)
1971 {
1972 RADV_FROM_HANDLE(radv_device, device, _device);
1973
1974 if (!device)
1975 return;
1976
1977 if (device->trace_bo)
1978 device->ws->buffer_destroy(device->trace_bo);
1979
1980 if (device->gfx_init)
1981 device->ws->buffer_destroy(device->gfx_init);
1982
1983 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1984 for (unsigned q = 0; q < device->queue_count[i]; q++)
1985 radv_queue_finish(&device->queues[i][q]);
1986 if (device->queue_count[i])
1987 vk_free(&device->alloc, device->queues[i]);
1988 if (device->empty_cs[i])
1989 device->ws->cs_destroy(device->empty_cs[i]);
1990 }
1991 radv_device_finish_meta(device);
1992
1993 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1994 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1995
1996 radv_destroy_shader_slabs(device);
1997
1998 radv_bo_list_finish(&device->bo_list);
1999 vk_free(&device->alloc, device);
2000 }
2001
2002 VkResult radv_EnumerateInstanceLayerProperties(
2003 uint32_t* pPropertyCount,
2004 VkLayerProperties* pProperties)
2005 {
2006 if (pProperties == NULL) {
2007 *pPropertyCount = 0;
2008 return VK_SUCCESS;
2009 }
2010
2011 /* None supported at this time */
2012 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2013 }
2014
2015 VkResult radv_EnumerateDeviceLayerProperties(
2016 VkPhysicalDevice physicalDevice,
2017 uint32_t* pPropertyCount,
2018 VkLayerProperties* pProperties)
2019 {
2020 if (pProperties == NULL) {
2021 *pPropertyCount = 0;
2022 return VK_SUCCESS;
2023 }
2024
2025 /* None supported at this time */
2026 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
2027 }
2028
2029 void radv_GetDeviceQueue2(
2030 VkDevice _device,
2031 const VkDeviceQueueInfo2* pQueueInfo,
2032 VkQueue* pQueue)
2033 {
2034 RADV_FROM_HANDLE(radv_device, device, _device);
2035 struct radv_queue *queue;
2036
2037 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
2038 if (pQueueInfo->flags != queue->flags) {
2039 /* From the Vulkan 1.1.70 spec:
2040 *
2041 * "The queue returned by vkGetDeviceQueue2 must have the same
2042 * flags value from this structure as that used at device
2043 * creation time in a VkDeviceQueueCreateInfo instance. If no
2044 * matching flags were specified at device creation time then
2045 * pQueue will return VK_NULL_HANDLE."
2046 */
2047 *pQueue = VK_NULL_HANDLE;
2048 return;
2049 }
2050
2051 *pQueue = radv_queue_to_handle(queue);
2052 }
2053
2054 void radv_GetDeviceQueue(
2055 VkDevice _device,
2056 uint32_t queueFamilyIndex,
2057 uint32_t queueIndex,
2058 VkQueue* pQueue)
2059 {
2060 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
2061 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
2062 .queueFamilyIndex = queueFamilyIndex,
2063 .queueIndex = queueIndex
2064 };
2065
2066 radv_GetDeviceQueue2(_device, &info, pQueue);
2067 }
2068
2069 static void
2070 fill_geom_tess_rings(struct radv_queue *queue,
2071 uint32_t *map,
2072 bool add_sample_positions,
2073 uint32_t esgs_ring_size,
2074 struct radeon_winsys_bo *esgs_ring_bo,
2075 uint32_t gsvs_ring_size,
2076 struct radeon_winsys_bo *gsvs_ring_bo,
2077 uint32_t tess_factor_ring_size,
2078 uint32_t tess_offchip_ring_offset,
2079 uint32_t tess_offchip_ring_size,
2080 struct radeon_winsys_bo *tess_rings_bo)
2081 {
2082 uint32_t *desc = &map[4];
2083
2084 if (esgs_ring_bo) {
2085 uint64_t esgs_va = radv_buffer_get_va(esgs_ring_bo);
2086
2087 /* stride 0, num records - size, add tid, swizzle, elsize4,
2088 index stride 64 */
2089 desc[0] = esgs_va;
2090 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
2091 S_008F04_STRIDE(0) |
2092 S_008F04_SWIZZLE_ENABLE(true);
2093 desc[2] = esgs_ring_size;
2094 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2095 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2096 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2097 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2098 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2099 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2100 S_008F0C_ELEMENT_SIZE(1) |
2101 S_008F0C_INDEX_STRIDE(3) |
2102 S_008F0C_ADD_TID_ENABLE(true);
2103
2104 /* GS entry for ES->GS ring */
2105 /* stride 0, num records - size, elsize0,
2106 index stride 0 */
2107 desc[4] = esgs_va;
2108 desc[5] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
2109 S_008F04_STRIDE(0) |
2110 S_008F04_SWIZZLE_ENABLE(false);
2111 desc[6] = esgs_ring_size;
2112 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2113 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2114 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2115 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2116 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2117 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2118 S_008F0C_ELEMENT_SIZE(0) |
2119 S_008F0C_INDEX_STRIDE(0) |
2120 S_008F0C_ADD_TID_ENABLE(false);
2121 }
2122
2123 desc += 8;
2124
2125 if (gsvs_ring_bo) {
2126 uint64_t gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
2127
2128 /* VS entry for GS->VS ring */
2129 /* stride 0, num records - size, elsize0,
2130 index stride 0 */
2131 desc[0] = gsvs_va;
2132 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2133 S_008F04_STRIDE(0) |
2134 S_008F04_SWIZZLE_ENABLE(false);
2135 desc[2] = gsvs_ring_size;
2136 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2137 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2138 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2139 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2140 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2141 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2142 S_008F0C_ELEMENT_SIZE(0) |
2143 S_008F0C_INDEX_STRIDE(0) |
2144 S_008F0C_ADD_TID_ENABLE(false);
2145
2146 /* stride gsvs_itemsize, num records 64
2147 elsize 4, index stride 16 */
2148 /* shader will patch stride and desc[2] */
2149 desc[4] = gsvs_va;
2150 desc[5] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
2151 S_008F04_STRIDE(0) |
2152 S_008F04_SWIZZLE_ENABLE(true);
2153 desc[6] = 0;
2154 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2155 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2156 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2157 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2158 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2159 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2160 S_008F0C_ELEMENT_SIZE(1) |
2161 S_008F0C_INDEX_STRIDE(1) |
2162 S_008F0C_ADD_TID_ENABLE(true);
2163 }
2164
2165 desc += 8;
2166
2167 if (tess_rings_bo) {
2168 uint64_t tess_va = radv_buffer_get_va(tess_rings_bo);
2169 uint64_t tess_offchip_va = tess_va + tess_offchip_ring_offset;
2170
2171 desc[0] = tess_va;
2172 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
2173 S_008F04_STRIDE(0) |
2174 S_008F04_SWIZZLE_ENABLE(false);
2175 desc[2] = tess_factor_ring_size;
2176 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2177 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2178 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2179 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2180 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2181 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2182 S_008F0C_ELEMENT_SIZE(0) |
2183 S_008F0C_INDEX_STRIDE(0) |
2184 S_008F0C_ADD_TID_ENABLE(false);
2185
2186 desc[4] = tess_offchip_va;
2187 desc[5] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
2188 S_008F04_STRIDE(0) |
2189 S_008F04_SWIZZLE_ENABLE(false);
2190 desc[6] = tess_offchip_ring_size;
2191 desc[7] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
2192 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
2193 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
2194 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
2195 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
2196 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
2197 S_008F0C_ELEMENT_SIZE(0) |
2198 S_008F0C_INDEX_STRIDE(0) |
2199 S_008F0C_ADD_TID_ENABLE(false);
2200 }
2201
2202 desc += 8;
2203
2204 if (add_sample_positions) {
2205 /* add sample positions after all rings */
2206 memcpy(desc, queue->device->sample_locations_1x, 8);
2207 desc += 2;
2208 memcpy(desc, queue->device->sample_locations_2x, 16);
2209 desc += 4;
2210 memcpy(desc, queue->device->sample_locations_4x, 32);
2211 desc += 8;
2212 memcpy(desc, queue->device->sample_locations_8x, 64);
2213 }
2214 }
2215
2216 static unsigned
2217 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
2218 {
2219 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
2220 device->physical_device->rad_info.family != CHIP_CARRIZO &&
2221 device->physical_device->rad_info.family != CHIP_STONEY;
2222 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
2223 unsigned max_offchip_buffers;
2224 unsigned offchip_granularity;
2225 unsigned hs_offchip_param;
2226
2227 /*
2228 * Per RadeonSI:
2229 * This must be one less than the maximum number due to a hw limitation.
2230 * Various hardware bugs in SI, CIK, and GFX9 need this.
2231 *
2232 * Per AMDVLK:
2233 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
2234 * Gfx7 should limit max_offchip_buffers to 508
2235 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
2236 *
2237 * Follow AMDVLK here.
2238 */
2239 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
2240 device->physical_device->rad_info.chip_class == CIK ||
2241 device->physical_device->rad_info.chip_class == SI)
2242 --max_offchip_buffers_per_se;
2243
2244 max_offchip_buffers = max_offchip_buffers_per_se *
2245 device->physical_device->rad_info.max_se;
2246
2247 /* Hawaii has a bug with offchip buffers > 256 that can be worked
2248 * around by setting 4K granularity.
2249 */
2250 if (device->tess_offchip_block_dw_size == 4096) {
2251 assert(device->physical_device->rad_info.family == CHIP_HAWAII);
2252 offchip_granularity = V_03093C_X_4K_DWORDS;
2253 } else {
2254 assert(device->tess_offchip_block_dw_size == 8192);
2255 offchip_granularity = V_03093C_X_8K_DWORDS;
2256 }
2257
2258 switch (device->physical_device->rad_info.chip_class) {
2259 case SI:
2260 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
2261 break;
2262 case CIK:
2263 case VI:
2264 case GFX9:
2265 default:
2266 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
2267 break;
2268 }
2269
2270 *max_offchip_buffers_p = max_offchip_buffers;
2271 if (device->physical_device->rad_info.chip_class >= CIK) {
2272 if (device->physical_device->rad_info.chip_class >= VI)
2273 --max_offchip_buffers;
2274 hs_offchip_param =
2275 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
2276 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
2277 } else {
2278 hs_offchip_param =
2279 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
2280 }
2281 return hs_offchip_param;
2282 }
2283
2284 static void
2285 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2286 struct radeon_winsys_bo *esgs_ring_bo,
2287 uint32_t esgs_ring_size,
2288 struct radeon_winsys_bo *gsvs_ring_bo,
2289 uint32_t gsvs_ring_size)
2290 {
2291 if (!esgs_ring_bo && !gsvs_ring_bo)
2292 return;
2293
2294 if (esgs_ring_bo)
2295 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
2296
2297 if (gsvs_ring_bo)
2298 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
2299
2300 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2301 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
2302 radeon_emit(cs, esgs_ring_size >> 8);
2303 radeon_emit(cs, gsvs_ring_size >> 8);
2304 } else {
2305 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
2306 radeon_emit(cs, esgs_ring_size >> 8);
2307 radeon_emit(cs, gsvs_ring_size >> 8);
2308 }
2309 }
2310
2311 static void
2312 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2313 unsigned hs_offchip_param, unsigned tf_ring_size,
2314 struct radeon_winsys_bo *tess_rings_bo)
2315 {
2316 uint64_t tf_va;
2317
2318 if (!tess_rings_bo)
2319 return;
2320
2321 tf_va = radv_buffer_get_va(tess_rings_bo);
2322
2323 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2324
2325 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2326 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2327 S_030938_SIZE(tf_ring_size / 4));
2328 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2329 tf_va >> 8);
2330 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2331 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2332 S_030944_BASE_HI(tf_va >> 40));
2333 }
2334 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2335 hs_offchip_param);
2336 } else {
2337 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2338 S_008988_SIZE(tf_ring_size / 4));
2339 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2340 tf_va >> 8);
2341 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2342 hs_offchip_param);
2343 }
2344 }
2345
2346 static void
2347 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2348 struct radeon_winsys_bo *compute_scratch_bo)
2349 {
2350 uint64_t scratch_va;
2351
2352 if (!compute_scratch_bo)
2353 return;
2354
2355 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2356
2357 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2358
2359 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2360 radeon_emit(cs, scratch_va);
2361 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2362 S_008F04_SWIZZLE_ENABLE(1));
2363 }
2364
2365 static void
2366 radv_emit_global_shader_pointers(struct radv_queue *queue,
2367 struct radeon_cmdbuf *cs,
2368 struct radeon_winsys_bo *descriptor_bo)
2369 {
2370 uint64_t va;
2371
2372 if (!descriptor_bo)
2373 return;
2374
2375 va = radv_buffer_get_va(descriptor_bo);
2376
2377 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2378
2379 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2380 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2381 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2382 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2383 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2384
2385 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2386 radv_emit_shader_pointer(queue->device, cs, regs[i],
2387 va, true);
2388 }
2389 } else {
2390 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2391 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2392 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2393 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2394 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2395 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2396
2397 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2398 radv_emit_shader_pointer(queue->device, cs, regs[i],
2399 va, true);
2400 }
2401 }
2402 }
2403
2404 static void
2405 radv_init_graphics_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2406 {
2407 struct radv_device *device = queue->device;
2408
2409 if (device->gfx_init) {
2410 uint64_t va = radv_buffer_get_va(device->gfx_init);
2411
2412 radeon_emit(cs, PKT3(PKT3_INDIRECT_BUFFER_CIK, 2, 0));
2413 radeon_emit(cs, va);
2414 radeon_emit(cs, va >> 32);
2415 radeon_emit(cs, device->gfx_init_size_dw & 0xffff);
2416
2417 radv_cs_add_buffer(device->ws, cs, device->gfx_init);
2418 } else {
2419 struct radv_physical_device *physical_device = device->physical_device;
2420 si_emit_graphics(physical_device, cs);
2421 }
2422 }
2423
2424 static void
2425 radv_init_compute_state(struct radeon_cmdbuf *cs, struct radv_queue *queue)
2426 {
2427 struct radv_physical_device *physical_device = queue->device->physical_device;
2428 si_emit_compute(physical_device, cs);
2429 }
2430
2431 static VkResult
2432 radv_get_preamble_cs(struct radv_queue *queue,
2433 uint32_t scratch_size,
2434 uint32_t compute_scratch_size,
2435 uint32_t esgs_ring_size,
2436 uint32_t gsvs_ring_size,
2437 bool needs_tess_rings,
2438 bool needs_sample_positions,
2439 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2440 struct radeon_cmdbuf **initial_preamble_cs,
2441 struct radeon_cmdbuf **continue_preamble_cs)
2442 {
2443 struct radeon_winsys_bo *scratch_bo = NULL;
2444 struct radeon_winsys_bo *descriptor_bo = NULL;
2445 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2446 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2447 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2448 struct radeon_winsys_bo *tess_rings_bo = NULL;
2449 struct radeon_cmdbuf *dest_cs[3] = {0};
2450 bool add_tess_rings = false, add_sample_positions = false;
2451 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2452 unsigned max_offchip_buffers;
2453 unsigned hs_offchip_param = 0;
2454 unsigned tess_offchip_ring_offset;
2455 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2456 if (!queue->has_tess_rings) {
2457 if (needs_tess_rings)
2458 add_tess_rings = true;
2459 }
2460 if (!queue->has_sample_positions) {
2461 if (needs_sample_positions)
2462 add_sample_positions = true;
2463 }
2464 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2465 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2466 &max_offchip_buffers);
2467 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2468 tess_offchip_ring_size = max_offchip_buffers *
2469 queue->device->tess_offchip_block_dw_size * 4;
2470
2471 if (scratch_size <= queue->scratch_size &&
2472 compute_scratch_size <= queue->compute_scratch_size &&
2473 esgs_ring_size <= queue->esgs_ring_size &&
2474 gsvs_ring_size <= queue->gsvs_ring_size &&
2475 !add_tess_rings && !add_sample_positions &&
2476 queue->initial_preamble_cs) {
2477 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2478 *initial_preamble_cs = queue->initial_preamble_cs;
2479 *continue_preamble_cs = queue->continue_preamble_cs;
2480 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2481 *continue_preamble_cs = NULL;
2482 return VK_SUCCESS;
2483 }
2484
2485 if (scratch_size > queue->scratch_size) {
2486 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2487 scratch_size,
2488 4096,
2489 RADEON_DOMAIN_VRAM,
2490 ring_bo_flags,
2491 RADV_BO_PRIORITY_SCRATCH);
2492 if (!scratch_bo)
2493 goto fail;
2494 } else
2495 scratch_bo = queue->scratch_bo;
2496
2497 if (compute_scratch_size > queue->compute_scratch_size) {
2498 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2499 compute_scratch_size,
2500 4096,
2501 RADEON_DOMAIN_VRAM,
2502 ring_bo_flags,
2503 RADV_BO_PRIORITY_SCRATCH);
2504 if (!compute_scratch_bo)
2505 goto fail;
2506
2507 } else
2508 compute_scratch_bo = queue->compute_scratch_bo;
2509
2510 if (esgs_ring_size > queue->esgs_ring_size) {
2511 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2512 esgs_ring_size,
2513 4096,
2514 RADEON_DOMAIN_VRAM,
2515 ring_bo_flags,
2516 RADV_BO_PRIORITY_SCRATCH);
2517 if (!esgs_ring_bo)
2518 goto fail;
2519 } else {
2520 esgs_ring_bo = queue->esgs_ring_bo;
2521 esgs_ring_size = queue->esgs_ring_size;
2522 }
2523
2524 if (gsvs_ring_size > queue->gsvs_ring_size) {
2525 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2526 gsvs_ring_size,
2527 4096,
2528 RADEON_DOMAIN_VRAM,
2529 ring_bo_flags,
2530 RADV_BO_PRIORITY_SCRATCH);
2531 if (!gsvs_ring_bo)
2532 goto fail;
2533 } else {
2534 gsvs_ring_bo = queue->gsvs_ring_bo;
2535 gsvs_ring_size = queue->gsvs_ring_size;
2536 }
2537
2538 if (add_tess_rings) {
2539 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2540 tess_offchip_ring_offset + tess_offchip_ring_size,
2541 256,
2542 RADEON_DOMAIN_VRAM,
2543 ring_bo_flags,
2544 RADV_BO_PRIORITY_SCRATCH);
2545 if (!tess_rings_bo)
2546 goto fail;
2547 } else {
2548 tess_rings_bo = queue->tess_rings_bo;
2549 }
2550
2551 if (scratch_bo != queue->scratch_bo ||
2552 esgs_ring_bo != queue->esgs_ring_bo ||
2553 gsvs_ring_bo != queue->gsvs_ring_bo ||
2554 tess_rings_bo != queue->tess_rings_bo ||
2555 add_sample_positions) {
2556 uint32_t size = 0;
2557 if (gsvs_ring_bo || esgs_ring_bo ||
2558 tess_rings_bo || add_sample_positions) {
2559 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2560 if (add_sample_positions)
2561 size += 128; /* 64+32+16+8 = 120 bytes */
2562 }
2563 else if (scratch_bo)
2564 size = 8; /* 2 dword */
2565
2566 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2567 size,
2568 4096,
2569 RADEON_DOMAIN_VRAM,
2570 RADEON_FLAG_CPU_ACCESS |
2571 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2572 RADEON_FLAG_READ_ONLY,
2573 RADV_BO_PRIORITY_DESCRIPTOR);
2574 if (!descriptor_bo)
2575 goto fail;
2576 } else
2577 descriptor_bo = queue->descriptor_bo;
2578
2579 if (descriptor_bo != queue->descriptor_bo) {
2580 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2581
2582 if (scratch_bo) {
2583 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2584 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2585 S_008F04_SWIZZLE_ENABLE(1);
2586 map[0] = scratch_va;
2587 map[1] = rsrc1;
2588 }
2589
2590 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo || add_sample_positions)
2591 fill_geom_tess_rings(queue, map, add_sample_positions,
2592 esgs_ring_size, esgs_ring_bo,
2593 gsvs_ring_size, gsvs_ring_bo,
2594 tess_factor_ring_size,
2595 tess_offchip_ring_offset,
2596 tess_offchip_ring_size,
2597 tess_rings_bo);
2598
2599 queue->device->ws->buffer_unmap(descriptor_bo);
2600 }
2601
2602 for(int i = 0; i < 3; ++i) {
2603 struct radeon_cmdbuf *cs = NULL;
2604 cs = queue->device->ws->cs_create(queue->device->ws,
2605 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2606 if (!cs)
2607 goto fail;
2608
2609 dest_cs[i] = cs;
2610
2611 if (scratch_bo)
2612 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2613
2614 /* Emit initial configuration. */
2615 switch (queue->queue_family_index) {
2616 case RADV_QUEUE_GENERAL:
2617 radv_init_graphics_state(cs, queue);
2618 break;
2619 case RADV_QUEUE_COMPUTE:
2620 radv_init_compute_state(cs, queue);
2621 break;
2622 case RADV_QUEUE_TRANSFER:
2623 break;
2624 }
2625
2626 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2627 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2628 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2629 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2630 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2631 }
2632
2633 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2634 gsvs_ring_bo, gsvs_ring_size);
2635 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2636 tess_factor_ring_size, tess_rings_bo);
2637 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2638 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2639
2640 if (i == 0) {
2641 si_cs_emit_cache_flush(cs,
2642 queue->device->physical_device->rad_info.chip_class,
2643 NULL, 0,
2644 queue->queue_family_index == RING_COMPUTE &&
2645 queue->device->physical_device->rad_info.chip_class >= CIK,
2646 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2647 RADV_CMD_FLAG_INV_ICACHE |
2648 RADV_CMD_FLAG_INV_SMEM_L1 |
2649 RADV_CMD_FLAG_INV_VMEM_L1 |
2650 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2651 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2652 } else if (i == 1) {
2653 si_cs_emit_cache_flush(cs,
2654 queue->device->physical_device->rad_info.chip_class,
2655 NULL, 0,
2656 queue->queue_family_index == RING_COMPUTE &&
2657 queue->device->physical_device->rad_info.chip_class >= CIK,
2658 RADV_CMD_FLAG_INV_ICACHE |
2659 RADV_CMD_FLAG_INV_SMEM_L1 |
2660 RADV_CMD_FLAG_INV_VMEM_L1 |
2661 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2662 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2663 }
2664
2665 if (!queue->device->ws->cs_finalize(cs))
2666 goto fail;
2667 }
2668
2669 if (queue->initial_full_flush_preamble_cs)
2670 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2671
2672 if (queue->initial_preamble_cs)
2673 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2674
2675 if (queue->continue_preamble_cs)
2676 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2677
2678 queue->initial_full_flush_preamble_cs = dest_cs[0];
2679 queue->initial_preamble_cs = dest_cs[1];
2680 queue->continue_preamble_cs = dest_cs[2];
2681
2682 if (scratch_bo != queue->scratch_bo) {
2683 if (queue->scratch_bo)
2684 queue->device->ws->buffer_destroy(queue->scratch_bo);
2685 queue->scratch_bo = scratch_bo;
2686 queue->scratch_size = scratch_size;
2687 }
2688
2689 if (compute_scratch_bo != queue->compute_scratch_bo) {
2690 if (queue->compute_scratch_bo)
2691 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2692 queue->compute_scratch_bo = compute_scratch_bo;
2693 queue->compute_scratch_size = compute_scratch_size;
2694 }
2695
2696 if (esgs_ring_bo != queue->esgs_ring_bo) {
2697 if (queue->esgs_ring_bo)
2698 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2699 queue->esgs_ring_bo = esgs_ring_bo;
2700 queue->esgs_ring_size = esgs_ring_size;
2701 }
2702
2703 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2704 if (queue->gsvs_ring_bo)
2705 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2706 queue->gsvs_ring_bo = gsvs_ring_bo;
2707 queue->gsvs_ring_size = gsvs_ring_size;
2708 }
2709
2710 if (tess_rings_bo != queue->tess_rings_bo) {
2711 queue->tess_rings_bo = tess_rings_bo;
2712 queue->has_tess_rings = true;
2713 }
2714
2715 if (descriptor_bo != queue->descriptor_bo) {
2716 if (queue->descriptor_bo)
2717 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2718
2719 queue->descriptor_bo = descriptor_bo;
2720 }
2721
2722 if (add_sample_positions)
2723 queue->has_sample_positions = true;
2724
2725 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2726 *initial_preamble_cs = queue->initial_preamble_cs;
2727 *continue_preamble_cs = queue->continue_preamble_cs;
2728 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2729 *continue_preamble_cs = NULL;
2730 return VK_SUCCESS;
2731 fail:
2732 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2733 if (dest_cs[i])
2734 queue->device->ws->cs_destroy(dest_cs[i]);
2735 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2736 queue->device->ws->buffer_destroy(descriptor_bo);
2737 if (scratch_bo && scratch_bo != queue->scratch_bo)
2738 queue->device->ws->buffer_destroy(scratch_bo);
2739 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2740 queue->device->ws->buffer_destroy(compute_scratch_bo);
2741 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2742 queue->device->ws->buffer_destroy(esgs_ring_bo);
2743 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2744 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2745 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2746 queue->device->ws->buffer_destroy(tess_rings_bo);
2747 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2748 }
2749
2750 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2751 struct radv_winsys_sem_counts *counts,
2752 int num_sems,
2753 const VkSemaphore *sems,
2754 VkFence _fence,
2755 bool reset_temp)
2756 {
2757 int syncobj_idx = 0, sem_idx = 0;
2758
2759 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2760 return VK_SUCCESS;
2761
2762 for (uint32_t i = 0; i < num_sems; i++) {
2763 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2764
2765 if (sem->temp_syncobj || sem->syncobj)
2766 counts->syncobj_count++;
2767 else
2768 counts->sem_count++;
2769 }
2770
2771 if (_fence != VK_NULL_HANDLE) {
2772 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2773 if (fence->temp_syncobj || fence->syncobj)
2774 counts->syncobj_count++;
2775 }
2776
2777 if (counts->syncobj_count) {
2778 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2779 if (!counts->syncobj)
2780 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2781 }
2782
2783 if (counts->sem_count) {
2784 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2785 if (!counts->sem) {
2786 free(counts->syncobj);
2787 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2788 }
2789 }
2790
2791 for (uint32_t i = 0; i < num_sems; i++) {
2792 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2793
2794 if (sem->temp_syncobj) {
2795 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2796 }
2797 else if (sem->syncobj)
2798 counts->syncobj[syncobj_idx++] = sem->syncobj;
2799 else {
2800 assert(sem->sem);
2801 counts->sem[sem_idx++] = sem->sem;
2802 }
2803 }
2804
2805 if (_fence != VK_NULL_HANDLE) {
2806 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2807 if (fence->temp_syncobj)
2808 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2809 else if (fence->syncobj)
2810 counts->syncobj[syncobj_idx++] = fence->syncobj;
2811 }
2812
2813 return VK_SUCCESS;
2814 }
2815
2816 static void
2817 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2818 {
2819 free(sem_info->wait.syncobj);
2820 free(sem_info->wait.sem);
2821 free(sem_info->signal.syncobj);
2822 free(sem_info->signal.sem);
2823 }
2824
2825
2826 static void radv_free_temp_syncobjs(struct radv_device *device,
2827 int num_sems,
2828 const VkSemaphore *sems)
2829 {
2830 for (uint32_t i = 0; i < num_sems; i++) {
2831 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2832
2833 if (sem->temp_syncobj) {
2834 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2835 sem->temp_syncobj = 0;
2836 }
2837 }
2838 }
2839
2840 static VkResult
2841 radv_alloc_sem_info(struct radv_instance *instance,
2842 struct radv_winsys_sem_info *sem_info,
2843 int num_wait_sems,
2844 const VkSemaphore *wait_sems,
2845 int num_signal_sems,
2846 const VkSemaphore *signal_sems,
2847 VkFence fence)
2848 {
2849 VkResult ret;
2850 memset(sem_info, 0, sizeof(*sem_info));
2851
2852 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2853 if (ret)
2854 return ret;
2855 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2856 if (ret)
2857 radv_free_sem_info(sem_info);
2858
2859 /* caller can override these */
2860 sem_info->cs_emit_wait = true;
2861 sem_info->cs_emit_signal = true;
2862 return ret;
2863 }
2864
2865 /* Signals fence as soon as all the work currently put on queue is done. */
2866 static VkResult radv_signal_fence(struct radv_queue *queue,
2867 struct radv_fence *fence)
2868 {
2869 int ret;
2870 VkResult result;
2871 struct radv_winsys_sem_info sem_info;
2872
2873 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2874 radv_fence_to_handle(fence));
2875 if (result != VK_SUCCESS)
2876 return result;
2877
2878 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2879 &queue->device->empty_cs[queue->queue_family_index],
2880 1, NULL, NULL, &sem_info, NULL,
2881 false, fence->fence);
2882 radv_free_sem_info(&sem_info);
2883
2884 if (ret)
2885 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2886
2887 return VK_SUCCESS;
2888 }
2889
2890 VkResult radv_QueueSubmit(
2891 VkQueue _queue,
2892 uint32_t submitCount,
2893 const VkSubmitInfo* pSubmits,
2894 VkFence _fence)
2895 {
2896 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2897 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2898 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2899 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2900 int ret;
2901 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : RADV_MAX_IBS_PER_SUBMIT;
2902 uint32_t scratch_size = 0;
2903 uint32_t compute_scratch_size = 0;
2904 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2905 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2906 VkResult result;
2907 bool fence_emitted = false;
2908 bool tess_rings_needed = false;
2909 bool sample_positions_needed = false;
2910
2911 /* Do this first so failing to allocate scratch buffers can't result in
2912 * partially executed submissions. */
2913 for (uint32_t i = 0; i < submitCount; i++) {
2914 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2915 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2916 pSubmits[i].pCommandBuffers[j]);
2917
2918 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2919 compute_scratch_size = MAX2(compute_scratch_size,
2920 cmd_buffer->compute_scratch_size_needed);
2921 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2922 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2923 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2924 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2925 }
2926 }
2927
2928 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2929 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2930 sample_positions_needed, &initial_flush_preamble_cs,
2931 &initial_preamble_cs, &continue_preamble_cs);
2932 if (result != VK_SUCCESS)
2933 return result;
2934
2935 for (uint32_t i = 0; i < submitCount; i++) {
2936 struct radeon_cmdbuf **cs_array;
2937 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2938 bool can_patch = true;
2939 uint32_t advance;
2940 struct radv_winsys_sem_info sem_info;
2941
2942 result = radv_alloc_sem_info(queue->device->instance,
2943 &sem_info,
2944 pSubmits[i].waitSemaphoreCount,
2945 pSubmits[i].pWaitSemaphores,
2946 pSubmits[i].signalSemaphoreCount,
2947 pSubmits[i].pSignalSemaphores,
2948 _fence);
2949 if (result != VK_SUCCESS)
2950 return result;
2951
2952 if (!pSubmits[i].commandBufferCount) {
2953 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2954 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2955 &queue->device->empty_cs[queue->queue_family_index],
2956 1, NULL, NULL,
2957 &sem_info, NULL,
2958 false, base_fence);
2959 if (ret) {
2960 radv_loge("failed to submit CS %d\n", i);
2961 abort();
2962 }
2963 fence_emitted = true;
2964 }
2965 radv_free_sem_info(&sem_info);
2966 continue;
2967 }
2968
2969 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2970 (pSubmits[i].commandBufferCount));
2971
2972 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2973 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2974 pSubmits[i].pCommandBuffers[j]);
2975 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2976
2977 cs_array[j] = cmd_buffer->cs;
2978 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2979 can_patch = false;
2980
2981 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2982 }
2983
2984 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2985 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2986 const struct radv_winsys_bo_list *bo_list = NULL;
2987
2988 advance = MIN2(max_cs_submission,
2989 pSubmits[i].commandBufferCount - j);
2990
2991 if (queue->device->trace_bo)
2992 *queue->device->trace_id_ptr = 0;
2993
2994 sem_info.cs_emit_wait = j == 0;
2995 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2996
2997 if (unlikely(queue->device->use_global_bo_list)) {
2998 pthread_mutex_lock(&queue->device->bo_list.mutex);
2999 bo_list = &queue->device->bo_list.list;
3000 }
3001
3002 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
3003 advance, initial_preamble, continue_preamble_cs,
3004 &sem_info, bo_list,
3005 can_patch, base_fence);
3006
3007 if (unlikely(queue->device->use_global_bo_list))
3008 pthread_mutex_unlock(&queue->device->bo_list.mutex);
3009
3010 if (ret) {
3011 radv_loge("failed to submit CS %d\n", i);
3012 abort();
3013 }
3014 fence_emitted = true;
3015 if (queue->device->trace_bo) {
3016 radv_check_gpu_hangs(queue, cs_array[j]);
3017 }
3018 }
3019
3020 radv_free_temp_syncobjs(queue->device,
3021 pSubmits[i].waitSemaphoreCount,
3022 pSubmits[i].pWaitSemaphores);
3023 radv_free_sem_info(&sem_info);
3024 free(cs_array);
3025 }
3026
3027 if (fence) {
3028 if (!fence_emitted) {
3029 result = radv_signal_fence(queue, fence);
3030 if (result != VK_SUCCESS)
3031 return result;
3032 }
3033 fence->submitted = true;
3034 }
3035
3036 return VK_SUCCESS;
3037 }
3038
3039 VkResult radv_QueueWaitIdle(
3040 VkQueue _queue)
3041 {
3042 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3043
3044 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
3045 radv_queue_family_to_ring(queue->queue_family_index),
3046 queue->queue_idx);
3047 return VK_SUCCESS;
3048 }
3049
3050 VkResult radv_DeviceWaitIdle(
3051 VkDevice _device)
3052 {
3053 RADV_FROM_HANDLE(radv_device, device, _device);
3054
3055 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
3056 for (unsigned q = 0; q < device->queue_count[i]; q++) {
3057 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
3058 }
3059 }
3060 return VK_SUCCESS;
3061 }
3062
3063 VkResult radv_EnumerateInstanceExtensionProperties(
3064 const char* pLayerName,
3065 uint32_t* pPropertyCount,
3066 VkExtensionProperties* pProperties)
3067 {
3068 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3069
3070 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
3071 if (radv_supported_instance_extensions.extensions[i]) {
3072 vk_outarray_append(&out, prop) {
3073 *prop = radv_instance_extensions[i];
3074 }
3075 }
3076 }
3077
3078 return vk_outarray_status(&out);
3079 }
3080
3081 VkResult radv_EnumerateDeviceExtensionProperties(
3082 VkPhysicalDevice physicalDevice,
3083 const char* pLayerName,
3084 uint32_t* pPropertyCount,
3085 VkExtensionProperties* pProperties)
3086 {
3087 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
3088 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
3089
3090 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
3091 if (device->supported_extensions.extensions[i]) {
3092 vk_outarray_append(&out, prop) {
3093 *prop = radv_device_extensions[i];
3094 }
3095 }
3096 }
3097
3098 return vk_outarray_status(&out);
3099 }
3100
3101 PFN_vkVoidFunction radv_GetInstanceProcAddr(
3102 VkInstance _instance,
3103 const char* pName)
3104 {
3105 RADV_FROM_HANDLE(radv_instance, instance, _instance);
3106
3107 return radv_lookup_entrypoint_checked(pName,
3108 instance ? instance->apiVersion : 0,
3109 instance ? &instance->enabled_extensions : NULL,
3110 NULL);
3111 }
3112
3113 /* The loader wants us to expose a second GetInstanceProcAddr function
3114 * to work around certain LD_PRELOAD issues seen in apps.
3115 */
3116 PUBLIC
3117 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3118 VkInstance instance,
3119 const char* pName);
3120
3121 PUBLIC
3122 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
3123 VkInstance instance,
3124 const char* pName)
3125 {
3126 return radv_GetInstanceProcAddr(instance, pName);
3127 }
3128
3129 PFN_vkVoidFunction radv_GetDeviceProcAddr(
3130 VkDevice _device,
3131 const char* pName)
3132 {
3133 RADV_FROM_HANDLE(radv_device, device, _device);
3134
3135 return radv_lookup_entrypoint_checked(pName,
3136 device->instance->apiVersion,
3137 &device->instance->enabled_extensions,
3138 &device->enabled_extensions);
3139 }
3140
3141 bool radv_get_memory_fd(struct radv_device *device,
3142 struct radv_device_memory *memory,
3143 int *pFD)
3144 {
3145 struct radeon_bo_metadata metadata;
3146
3147 if (memory->image) {
3148 radv_init_metadata(device, memory->image, &metadata);
3149 device->ws->buffer_set_metadata(memory->bo, &metadata);
3150 }
3151
3152 return device->ws->buffer_get_fd(device->ws, memory->bo,
3153 pFD);
3154 }
3155
3156 static VkResult radv_alloc_memory(struct radv_device *device,
3157 const VkMemoryAllocateInfo* pAllocateInfo,
3158 const VkAllocationCallbacks* pAllocator,
3159 VkDeviceMemory* pMem)
3160 {
3161 struct radv_device_memory *mem;
3162 VkResult result;
3163 enum radeon_bo_domain domain;
3164 uint32_t flags = 0;
3165 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
3166
3167 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
3168
3169 if (pAllocateInfo->allocationSize == 0) {
3170 /* Apparently, this is allowed */
3171 *pMem = VK_NULL_HANDLE;
3172 return VK_SUCCESS;
3173 }
3174
3175 const VkImportMemoryFdInfoKHR *import_info =
3176 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
3177 const VkMemoryDedicatedAllocateInfo *dedicate_info =
3178 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO);
3179 const VkExportMemoryAllocateInfo *export_info =
3180 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO);
3181 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
3182 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
3183
3184 const struct wsi_memory_allocate_info *wsi_info =
3185 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
3186
3187 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
3188 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3189 if (mem == NULL)
3190 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3191
3192 if (wsi_info && wsi_info->implicit_sync)
3193 flags |= RADEON_FLAG_IMPLICIT_SYNC;
3194
3195 if (dedicate_info) {
3196 mem->image = radv_image_from_handle(dedicate_info->image);
3197 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
3198 } else {
3199 mem->image = NULL;
3200 mem->buffer = NULL;
3201 }
3202
3203 float priority_float = 0.5;
3204 const struct VkMemoryPriorityAllocateInfoEXT *priority_ext =
3205 vk_find_struct_const(pAllocateInfo->pNext,
3206 MEMORY_PRIORITY_ALLOCATE_INFO_EXT);
3207 if (priority_ext)
3208 priority_float = priority_ext->priority;
3209
3210 unsigned priority = MIN2(RADV_BO_PRIORITY_APPLICATION_MAX - 1,
3211 (int)(priority_float * RADV_BO_PRIORITY_APPLICATION_MAX));
3212
3213 mem->user_ptr = NULL;
3214
3215 if (import_info) {
3216 assert(import_info->handleType ==
3217 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
3218 import_info->handleType ==
3219 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
3220 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
3221 priority, NULL, NULL);
3222 if (!mem->bo) {
3223 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3224 goto fail;
3225 } else {
3226 close(import_info->fd);
3227 }
3228 } else if (host_ptr_info) {
3229 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
3230 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
3231 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
3232 pAllocateInfo->allocationSize,
3233 priority);
3234 if (!mem->bo) {
3235 result = VK_ERROR_INVALID_EXTERNAL_HANDLE;
3236 goto fail;
3237 } else {
3238 mem->user_ptr = host_ptr_info->pHostPointer;
3239 }
3240 } else {
3241 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
3242 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
3243 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
3244 domain = RADEON_DOMAIN_GTT;
3245 else
3246 domain = RADEON_DOMAIN_VRAM;
3247
3248 if (mem_type_index == RADV_MEM_TYPE_VRAM)
3249 flags |= RADEON_FLAG_NO_CPU_ACCESS;
3250 else
3251 flags |= RADEON_FLAG_CPU_ACCESS;
3252
3253 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
3254 flags |= RADEON_FLAG_GTT_WC;
3255
3256 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes)) {
3257 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
3258 if (device->use_global_bo_list) {
3259 flags |= RADEON_FLAG_PREFER_LOCAL_BO;
3260 }
3261 }
3262
3263 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
3264 domain, flags, priority);
3265
3266 if (!mem->bo) {
3267 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
3268 goto fail;
3269 }
3270 mem->type_index = mem_type_index;
3271 }
3272
3273 result = radv_bo_list_add(device, mem->bo);
3274 if (result != VK_SUCCESS)
3275 goto fail_bo;
3276
3277 *pMem = radv_device_memory_to_handle(mem);
3278
3279 return VK_SUCCESS;
3280
3281 fail_bo:
3282 device->ws->buffer_destroy(mem->bo);
3283 fail:
3284 vk_free2(&device->alloc, pAllocator, mem);
3285
3286 return result;
3287 }
3288
3289 VkResult radv_AllocateMemory(
3290 VkDevice _device,
3291 const VkMemoryAllocateInfo* pAllocateInfo,
3292 const VkAllocationCallbacks* pAllocator,
3293 VkDeviceMemory* pMem)
3294 {
3295 RADV_FROM_HANDLE(radv_device, device, _device);
3296 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
3297 }
3298
3299 void radv_FreeMemory(
3300 VkDevice _device,
3301 VkDeviceMemory _mem,
3302 const VkAllocationCallbacks* pAllocator)
3303 {
3304 RADV_FROM_HANDLE(radv_device, device, _device);
3305 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
3306
3307 if (mem == NULL)
3308 return;
3309
3310 radv_bo_list_remove(device, mem->bo);
3311 device->ws->buffer_destroy(mem->bo);
3312 mem->bo = NULL;
3313
3314 vk_free2(&device->alloc, pAllocator, mem);
3315 }
3316
3317 VkResult radv_MapMemory(
3318 VkDevice _device,
3319 VkDeviceMemory _memory,
3320 VkDeviceSize offset,
3321 VkDeviceSize size,
3322 VkMemoryMapFlags flags,
3323 void** ppData)
3324 {
3325 RADV_FROM_HANDLE(radv_device, device, _device);
3326 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3327
3328 if (mem == NULL) {
3329 *ppData = NULL;
3330 return VK_SUCCESS;
3331 }
3332
3333 if (mem->user_ptr)
3334 *ppData = mem->user_ptr;
3335 else
3336 *ppData = device->ws->buffer_map(mem->bo);
3337
3338 if (*ppData) {
3339 *ppData += offset;
3340 return VK_SUCCESS;
3341 }
3342
3343 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
3344 }
3345
3346 void radv_UnmapMemory(
3347 VkDevice _device,
3348 VkDeviceMemory _memory)
3349 {
3350 RADV_FROM_HANDLE(radv_device, device, _device);
3351 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
3352
3353 if (mem == NULL)
3354 return;
3355
3356 if (mem->user_ptr == NULL)
3357 device->ws->buffer_unmap(mem->bo);
3358 }
3359
3360 VkResult radv_FlushMappedMemoryRanges(
3361 VkDevice _device,
3362 uint32_t memoryRangeCount,
3363 const VkMappedMemoryRange* pMemoryRanges)
3364 {
3365 return VK_SUCCESS;
3366 }
3367
3368 VkResult radv_InvalidateMappedMemoryRanges(
3369 VkDevice _device,
3370 uint32_t memoryRangeCount,
3371 const VkMappedMemoryRange* pMemoryRanges)
3372 {
3373 return VK_SUCCESS;
3374 }
3375
3376 void radv_GetBufferMemoryRequirements(
3377 VkDevice _device,
3378 VkBuffer _buffer,
3379 VkMemoryRequirements* pMemoryRequirements)
3380 {
3381 RADV_FROM_HANDLE(radv_device, device, _device);
3382 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3383
3384 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3385
3386 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3387 pMemoryRequirements->alignment = 4096;
3388 else
3389 pMemoryRequirements->alignment = 16;
3390
3391 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3392 }
3393
3394 void radv_GetBufferMemoryRequirements2(
3395 VkDevice device,
3396 const VkBufferMemoryRequirementsInfo2 *pInfo,
3397 VkMemoryRequirements2 *pMemoryRequirements)
3398 {
3399 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3400 &pMemoryRequirements->memoryRequirements);
3401 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3402 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3403 switch (ext->sType) {
3404 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3405 VkMemoryDedicatedRequirements *req =
3406 (VkMemoryDedicatedRequirements *) ext;
3407 req->requiresDedicatedAllocation = buffer->shareable;
3408 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3409 break;
3410 }
3411 default:
3412 break;
3413 }
3414 }
3415 }
3416
3417 void radv_GetImageMemoryRequirements(
3418 VkDevice _device,
3419 VkImage _image,
3420 VkMemoryRequirements* pMemoryRequirements)
3421 {
3422 RADV_FROM_HANDLE(radv_device, device, _device);
3423 RADV_FROM_HANDLE(radv_image, image, _image);
3424
3425 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3426
3427 pMemoryRequirements->size = image->size;
3428 pMemoryRequirements->alignment = image->alignment;
3429 }
3430
3431 void radv_GetImageMemoryRequirements2(
3432 VkDevice device,
3433 const VkImageMemoryRequirementsInfo2 *pInfo,
3434 VkMemoryRequirements2 *pMemoryRequirements)
3435 {
3436 radv_GetImageMemoryRequirements(device, pInfo->image,
3437 &pMemoryRequirements->memoryRequirements);
3438
3439 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3440
3441 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3442 switch (ext->sType) {
3443 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS: {
3444 VkMemoryDedicatedRequirements *req =
3445 (VkMemoryDedicatedRequirements *) ext;
3446 req->requiresDedicatedAllocation = image->shareable;
3447 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3448 break;
3449 }
3450 default:
3451 break;
3452 }
3453 }
3454 }
3455
3456 void radv_GetImageSparseMemoryRequirements(
3457 VkDevice device,
3458 VkImage image,
3459 uint32_t* pSparseMemoryRequirementCount,
3460 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3461 {
3462 stub();
3463 }
3464
3465 void radv_GetImageSparseMemoryRequirements2(
3466 VkDevice device,
3467 const VkImageSparseMemoryRequirementsInfo2 *pInfo,
3468 uint32_t* pSparseMemoryRequirementCount,
3469 VkSparseImageMemoryRequirements2 *pSparseMemoryRequirements)
3470 {
3471 stub();
3472 }
3473
3474 void radv_GetDeviceMemoryCommitment(
3475 VkDevice device,
3476 VkDeviceMemory memory,
3477 VkDeviceSize* pCommittedMemoryInBytes)
3478 {
3479 *pCommittedMemoryInBytes = 0;
3480 }
3481
3482 VkResult radv_BindBufferMemory2(VkDevice device,
3483 uint32_t bindInfoCount,
3484 const VkBindBufferMemoryInfo *pBindInfos)
3485 {
3486 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3487 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3488 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3489
3490 if (mem) {
3491 buffer->bo = mem->bo;
3492 buffer->offset = pBindInfos[i].memoryOffset;
3493 } else {
3494 buffer->bo = NULL;
3495 }
3496 }
3497 return VK_SUCCESS;
3498 }
3499
3500 VkResult radv_BindBufferMemory(
3501 VkDevice device,
3502 VkBuffer buffer,
3503 VkDeviceMemory memory,
3504 VkDeviceSize memoryOffset)
3505 {
3506 const VkBindBufferMemoryInfo info = {
3507 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3508 .buffer = buffer,
3509 .memory = memory,
3510 .memoryOffset = memoryOffset
3511 };
3512
3513 return radv_BindBufferMemory2(device, 1, &info);
3514 }
3515
3516 VkResult radv_BindImageMemory2(VkDevice device,
3517 uint32_t bindInfoCount,
3518 const VkBindImageMemoryInfo *pBindInfos)
3519 {
3520 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3521 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3522 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3523
3524 if (mem) {
3525 image->bo = mem->bo;
3526 image->offset = pBindInfos[i].memoryOffset;
3527 } else {
3528 image->bo = NULL;
3529 image->offset = 0;
3530 }
3531 }
3532 return VK_SUCCESS;
3533 }
3534
3535
3536 VkResult radv_BindImageMemory(
3537 VkDevice device,
3538 VkImage image,
3539 VkDeviceMemory memory,
3540 VkDeviceSize memoryOffset)
3541 {
3542 const VkBindImageMemoryInfo info = {
3543 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO,
3544 .image = image,
3545 .memory = memory,
3546 .memoryOffset = memoryOffset
3547 };
3548
3549 return radv_BindImageMemory2(device, 1, &info);
3550 }
3551
3552
3553 static void
3554 radv_sparse_buffer_bind_memory(struct radv_device *device,
3555 const VkSparseBufferMemoryBindInfo *bind)
3556 {
3557 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3558
3559 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3560 struct radv_device_memory *mem = NULL;
3561
3562 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3563 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3564
3565 device->ws->buffer_virtual_bind(buffer->bo,
3566 bind->pBinds[i].resourceOffset,
3567 bind->pBinds[i].size,
3568 mem ? mem->bo : NULL,
3569 bind->pBinds[i].memoryOffset);
3570 }
3571 }
3572
3573 static void
3574 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3575 const VkSparseImageOpaqueMemoryBindInfo *bind)
3576 {
3577 RADV_FROM_HANDLE(radv_image, image, bind->image);
3578
3579 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3580 struct radv_device_memory *mem = NULL;
3581
3582 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3583 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3584
3585 device->ws->buffer_virtual_bind(image->bo,
3586 bind->pBinds[i].resourceOffset,
3587 bind->pBinds[i].size,
3588 mem ? mem->bo : NULL,
3589 bind->pBinds[i].memoryOffset);
3590 }
3591 }
3592
3593 VkResult radv_QueueBindSparse(
3594 VkQueue _queue,
3595 uint32_t bindInfoCount,
3596 const VkBindSparseInfo* pBindInfo,
3597 VkFence _fence)
3598 {
3599 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3600 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3601 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3602 bool fence_emitted = false;
3603 VkResult result;
3604 int ret;
3605
3606 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3607 struct radv_winsys_sem_info sem_info;
3608 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3609 radv_sparse_buffer_bind_memory(queue->device,
3610 pBindInfo[i].pBufferBinds + j);
3611 }
3612
3613 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3614 radv_sparse_image_opaque_bind_memory(queue->device,
3615 pBindInfo[i].pImageOpaqueBinds + j);
3616 }
3617
3618 VkResult result;
3619 result = radv_alloc_sem_info(queue->device->instance,
3620 &sem_info,
3621 pBindInfo[i].waitSemaphoreCount,
3622 pBindInfo[i].pWaitSemaphores,
3623 pBindInfo[i].signalSemaphoreCount,
3624 pBindInfo[i].pSignalSemaphores,
3625 _fence);
3626 if (result != VK_SUCCESS)
3627 return result;
3628
3629 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3630 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3631 &queue->device->empty_cs[queue->queue_family_index],
3632 1, NULL, NULL,
3633 &sem_info, NULL,
3634 false, base_fence);
3635 if (ret) {
3636 radv_loge("failed to submit CS %d\n", i);
3637 abort();
3638 }
3639
3640 fence_emitted = true;
3641 if (fence)
3642 fence->submitted = true;
3643 }
3644
3645 radv_free_sem_info(&sem_info);
3646
3647 }
3648
3649 if (fence) {
3650 if (!fence_emitted) {
3651 result = radv_signal_fence(queue, fence);
3652 if (result != VK_SUCCESS)
3653 return result;
3654 }
3655 fence->submitted = true;
3656 }
3657
3658 return VK_SUCCESS;
3659 }
3660
3661 VkResult radv_CreateFence(
3662 VkDevice _device,
3663 const VkFenceCreateInfo* pCreateInfo,
3664 const VkAllocationCallbacks* pAllocator,
3665 VkFence* pFence)
3666 {
3667 RADV_FROM_HANDLE(radv_device, device, _device);
3668 const VkExportFenceCreateInfo *export =
3669 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO);
3670 VkExternalFenceHandleTypeFlags handleTypes =
3671 export ? export->handleTypes : 0;
3672
3673 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3674 sizeof(*fence), 8,
3675 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3676
3677 if (!fence)
3678 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3679
3680 fence->fence_wsi = NULL;
3681 fence->submitted = false;
3682 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3683 fence->temp_syncobj = 0;
3684 if (device->always_use_syncobj || handleTypes) {
3685 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3686 if (ret) {
3687 vk_free2(&device->alloc, pAllocator, fence);
3688 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3689 }
3690 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3691 device->ws->signal_syncobj(device->ws, fence->syncobj);
3692 }
3693 fence->fence = NULL;
3694 } else {
3695 fence->fence = device->ws->create_fence();
3696 if (!fence->fence) {
3697 vk_free2(&device->alloc, pAllocator, fence);
3698 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3699 }
3700 fence->syncobj = 0;
3701 }
3702
3703 *pFence = radv_fence_to_handle(fence);
3704
3705 return VK_SUCCESS;
3706 }
3707
3708 void radv_DestroyFence(
3709 VkDevice _device,
3710 VkFence _fence,
3711 const VkAllocationCallbacks* pAllocator)
3712 {
3713 RADV_FROM_HANDLE(radv_device, device, _device);
3714 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3715
3716 if (!fence)
3717 return;
3718
3719 if (fence->temp_syncobj)
3720 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3721 if (fence->syncobj)
3722 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3723 if (fence->fence)
3724 device->ws->destroy_fence(fence->fence);
3725 if (fence->fence_wsi)
3726 fence->fence_wsi->destroy(fence->fence_wsi);
3727 vk_free2(&device->alloc, pAllocator, fence);
3728 }
3729
3730
3731 uint64_t radv_get_current_time(void)
3732 {
3733 struct timespec tv;
3734 clock_gettime(CLOCK_MONOTONIC, &tv);
3735 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3736 }
3737
3738 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3739 {
3740 uint64_t current_time = radv_get_current_time();
3741
3742 timeout = MIN2(UINT64_MAX - current_time, timeout);
3743
3744 return current_time + timeout;
3745 }
3746
3747
3748 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3749 {
3750 for (uint32_t i = 0; i < fenceCount; ++i) {
3751 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3752 if (fence->fence == NULL || fence->syncobj ||
3753 fence->temp_syncobj ||
3754 (!fence->signalled && !fence->submitted))
3755 return false;
3756 }
3757 return true;
3758 }
3759
3760 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3761 {
3762 for (uint32_t i = 0; i < fenceCount; ++i) {
3763 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3764 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3765 return false;
3766 }
3767 return true;
3768 }
3769
3770 VkResult radv_WaitForFences(
3771 VkDevice _device,
3772 uint32_t fenceCount,
3773 const VkFence* pFences,
3774 VkBool32 waitAll,
3775 uint64_t timeout)
3776 {
3777 RADV_FROM_HANDLE(radv_device, device, _device);
3778 timeout = radv_get_absolute_timeout(timeout);
3779
3780 if (device->always_use_syncobj &&
3781 radv_all_fences_syncobj(fenceCount, pFences))
3782 {
3783 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3784 if (!handles)
3785 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3786
3787 for (uint32_t i = 0; i < fenceCount; ++i) {
3788 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3789 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3790 }
3791
3792 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3793
3794 free(handles);
3795 return success ? VK_SUCCESS : VK_TIMEOUT;
3796 }
3797
3798 if (!waitAll && fenceCount > 1) {
3799 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3800 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3801 uint32_t wait_count = 0;
3802 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3803 if (!fences)
3804 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3805
3806 for (uint32_t i = 0; i < fenceCount; ++i) {
3807 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3808
3809 if (fence->signalled) {
3810 free(fences);
3811 return VK_SUCCESS;
3812 }
3813
3814 fences[wait_count++] = fence->fence;
3815 }
3816
3817 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3818 waitAll, timeout - radv_get_current_time());
3819
3820 free(fences);
3821 return success ? VK_SUCCESS : VK_TIMEOUT;
3822 }
3823
3824 while(radv_get_current_time() <= timeout) {
3825 for (uint32_t i = 0; i < fenceCount; ++i) {
3826 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3827 return VK_SUCCESS;
3828 }
3829 }
3830 return VK_TIMEOUT;
3831 }
3832
3833 for (uint32_t i = 0; i < fenceCount; ++i) {
3834 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3835 bool expired = false;
3836
3837 if (fence->temp_syncobj) {
3838 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3839 return VK_TIMEOUT;
3840 continue;
3841 }
3842
3843 if (fence->syncobj) {
3844 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3845 return VK_TIMEOUT;
3846 continue;
3847 }
3848
3849 if (fence->signalled)
3850 continue;
3851
3852 if (fence->fence) {
3853 if (!fence->submitted) {
3854 while(radv_get_current_time() <= timeout &&
3855 !fence->submitted)
3856 /* Do nothing */;
3857
3858 if (!fence->submitted)
3859 return VK_TIMEOUT;
3860
3861 /* Recheck as it may have been set by
3862 * submitting operations. */
3863
3864 if (fence->signalled)
3865 continue;
3866 }
3867
3868 expired = device->ws->fence_wait(device->ws,
3869 fence->fence,
3870 true, timeout);
3871 if (!expired)
3872 return VK_TIMEOUT;
3873 }
3874
3875 if (fence->fence_wsi) {
3876 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3877 if (result != VK_SUCCESS)
3878 return result;
3879 }
3880
3881 fence->signalled = true;
3882 }
3883
3884 return VK_SUCCESS;
3885 }
3886
3887 VkResult radv_ResetFences(VkDevice _device,
3888 uint32_t fenceCount,
3889 const VkFence *pFences)
3890 {
3891 RADV_FROM_HANDLE(radv_device, device, _device);
3892
3893 for (unsigned i = 0; i < fenceCount; ++i) {
3894 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3895 fence->submitted = fence->signalled = false;
3896
3897 /* Per spec, we first restore the permanent payload, and then reset, so
3898 * having a temp syncobj should not skip resetting the permanent syncobj. */
3899 if (fence->temp_syncobj) {
3900 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3901 fence->temp_syncobj = 0;
3902 }
3903
3904 if (fence->syncobj) {
3905 device->ws->reset_syncobj(device->ws, fence->syncobj);
3906 }
3907 }
3908
3909 return VK_SUCCESS;
3910 }
3911
3912 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3913 {
3914 RADV_FROM_HANDLE(radv_device, device, _device);
3915 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3916
3917 if (fence->temp_syncobj) {
3918 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3919 return success ? VK_SUCCESS : VK_NOT_READY;
3920 }
3921
3922 if (fence->syncobj) {
3923 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3924 return success ? VK_SUCCESS : VK_NOT_READY;
3925 }
3926
3927 if (fence->signalled)
3928 return VK_SUCCESS;
3929 if (!fence->submitted)
3930 return VK_NOT_READY;
3931 if (fence->fence) {
3932 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3933 return VK_NOT_READY;
3934 }
3935 if (fence->fence_wsi) {
3936 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3937
3938 if (result != VK_SUCCESS) {
3939 if (result == VK_TIMEOUT)
3940 return VK_NOT_READY;
3941 return result;
3942 }
3943 }
3944 return VK_SUCCESS;
3945 }
3946
3947
3948 // Queue semaphore functions
3949
3950 VkResult radv_CreateSemaphore(
3951 VkDevice _device,
3952 const VkSemaphoreCreateInfo* pCreateInfo,
3953 const VkAllocationCallbacks* pAllocator,
3954 VkSemaphore* pSemaphore)
3955 {
3956 RADV_FROM_HANDLE(radv_device, device, _device);
3957 const VkExportSemaphoreCreateInfo *export =
3958 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO);
3959 VkExternalSemaphoreHandleTypeFlags handleTypes =
3960 export ? export->handleTypes : 0;
3961
3962 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3963 sizeof(*sem), 8,
3964 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3965 if (!sem)
3966 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3967
3968 sem->temp_syncobj = 0;
3969 /* create a syncobject if we are going to export this semaphore */
3970 if (device->always_use_syncobj || handleTypes) {
3971 assert (device->physical_device->rad_info.has_syncobj);
3972 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3973 if (ret) {
3974 vk_free2(&device->alloc, pAllocator, sem);
3975 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3976 }
3977 sem->sem = NULL;
3978 } else {
3979 sem->sem = device->ws->create_sem(device->ws);
3980 if (!sem->sem) {
3981 vk_free2(&device->alloc, pAllocator, sem);
3982 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3983 }
3984 sem->syncobj = 0;
3985 }
3986
3987 *pSemaphore = radv_semaphore_to_handle(sem);
3988 return VK_SUCCESS;
3989 }
3990
3991 void radv_DestroySemaphore(
3992 VkDevice _device,
3993 VkSemaphore _semaphore,
3994 const VkAllocationCallbacks* pAllocator)
3995 {
3996 RADV_FROM_HANDLE(radv_device, device, _device);
3997 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3998 if (!_semaphore)
3999 return;
4000
4001 if (sem->syncobj)
4002 device->ws->destroy_syncobj(device->ws, sem->syncobj);
4003 else
4004 device->ws->destroy_sem(sem->sem);
4005 vk_free2(&device->alloc, pAllocator, sem);
4006 }
4007
4008 VkResult radv_CreateEvent(
4009 VkDevice _device,
4010 const VkEventCreateInfo* pCreateInfo,
4011 const VkAllocationCallbacks* pAllocator,
4012 VkEvent* pEvent)
4013 {
4014 RADV_FROM_HANDLE(radv_device, device, _device);
4015 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
4016 sizeof(*event), 8,
4017 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4018
4019 if (!event)
4020 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4021
4022 event->bo = device->ws->buffer_create(device->ws, 8, 8,
4023 RADEON_DOMAIN_GTT,
4024 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING,
4025 RADV_BO_PRIORITY_FENCE);
4026 if (!event->bo) {
4027 vk_free2(&device->alloc, pAllocator, event);
4028 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4029 }
4030
4031 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
4032
4033 *pEvent = radv_event_to_handle(event);
4034
4035 return VK_SUCCESS;
4036 }
4037
4038 void radv_DestroyEvent(
4039 VkDevice _device,
4040 VkEvent _event,
4041 const VkAllocationCallbacks* pAllocator)
4042 {
4043 RADV_FROM_HANDLE(radv_device, device, _device);
4044 RADV_FROM_HANDLE(radv_event, event, _event);
4045
4046 if (!event)
4047 return;
4048 device->ws->buffer_destroy(event->bo);
4049 vk_free2(&device->alloc, pAllocator, event);
4050 }
4051
4052 VkResult radv_GetEventStatus(
4053 VkDevice _device,
4054 VkEvent _event)
4055 {
4056 RADV_FROM_HANDLE(radv_event, event, _event);
4057
4058 if (*event->map == 1)
4059 return VK_EVENT_SET;
4060 return VK_EVENT_RESET;
4061 }
4062
4063 VkResult radv_SetEvent(
4064 VkDevice _device,
4065 VkEvent _event)
4066 {
4067 RADV_FROM_HANDLE(radv_event, event, _event);
4068 *event->map = 1;
4069
4070 return VK_SUCCESS;
4071 }
4072
4073 VkResult radv_ResetEvent(
4074 VkDevice _device,
4075 VkEvent _event)
4076 {
4077 RADV_FROM_HANDLE(radv_event, event, _event);
4078 *event->map = 0;
4079
4080 return VK_SUCCESS;
4081 }
4082
4083 VkResult radv_CreateBuffer(
4084 VkDevice _device,
4085 const VkBufferCreateInfo* pCreateInfo,
4086 const VkAllocationCallbacks* pAllocator,
4087 VkBuffer* pBuffer)
4088 {
4089 RADV_FROM_HANDLE(radv_device, device, _device);
4090 struct radv_buffer *buffer;
4091
4092 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
4093
4094 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
4095 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4096 if (buffer == NULL)
4097 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4098
4099 buffer->size = pCreateInfo->size;
4100 buffer->usage = pCreateInfo->usage;
4101 buffer->bo = NULL;
4102 buffer->offset = 0;
4103 buffer->flags = pCreateInfo->flags;
4104
4105 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
4106 EXTERNAL_MEMORY_BUFFER_CREATE_INFO) != NULL;
4107
4108 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
4109 buffer->bo = device->ws->buffer_create(device->ws,
4110 align64(buffer->size, 4096),
4111 4096, 0, RADEON_FLAG_VIRTUAL,
4112 RADV_BO_PRIORITY_VIRTUAL);
4113 if (!buffer->bo) {
4114 vk_free2(&device->alloc, pAllocator, buffer);
4115 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4116 }
4117 }
4118
4119 *pBuffer = radv_buffer_to_handle(buffer);
4120
4121 return VK_SUCCESS;
4122 }
4123
4124 void radv_DestroyBuffer(
4125 VkDevice _device,
4126 VkBuffer _buffer,
4127 const VkAllocationCallbacks* pAllocator)
4128 {
4129 RADV_FROM_HANDLE(radv_device, device, _device);
4130 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
4131
4132 if (!buffer)
4133 return;
4134
4135 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
4136 device->ws->buffer_destroy(buffer->bo);
4137
4138 vk_free2(&device->alloc, pAllocator, buffer);
4139 }
4140
4141 VkDeviceAddress radv_GetBufferDeviceAddressEXT(
4142 VkDevice device,
4143 const VkBufferDeviceAddressInfoEXT* pInfo)
4144 {
4145 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
4146 return radv_buffer_get_va(buffer->bo) + buffer->offset;
4147 }
4148
4149
4150 static inline unsigned
4151 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
4152 {
4153 if (stencil)
4154 return plane->surface.u.legacy.stencil_tiling_index[level];
4155 else
4156 return plane->surface.u.legacy.tiling_index[level];
4157 }
4158
4159 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
4160 {
4161 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
4162 }
4163
4164 static uint32_t
4165 radv_init_dcc_control_reg(struct radv_device *device,
4166 struct radv_image_view *iview)
4167 {
4168 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
4169 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
4170 unsigned max_compressed_block_size;
4171 unsigned independent_64b_blocks;
4172
4173 if (!radv_image_has_dcc(iview->image))
4174 return 0;
4175
4176 if (iview->image->info.samples > 1) {
4177 if (iview->image->planes[0].surface.bpe == 1)
4178 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4179 else if (iview->image->planes[0].surface.bpe == 2)
4180 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
4181 }
4182
4183 if (!device->physical_device->rad_info.has_dedicated_vram) {
4184 /* amdvlk: [min-compressed-block-size] should be set to 32 for
4185 * dGPU and 64 for APU because all of our APUs to date use
4186 * DIMMs which have a request granularity size of 64B while all
4187 * other chips have a 32B request size.
4188 */
4189 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
4190 }
4191
4192 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
4193 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
4194 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
4195 /* If this DCC image is potentially going to be used in texture
4196 * fetches, we need some special settings.
4197 */
4198 independent_64b_blocks = 1;
4199 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
4200 } else {
4201 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
4202 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
4203 * big as possible for better compression state.
4204 */
4205 independent_64b_blocks = 0;
4206 max_compressed_block_size = max_uncompressed_block_size;
4207 }
4208
4209 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
4210 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
4211 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
4212 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
4213 }
4214
4215 static void
4216 radv_initialise_color_surface(struct radv_device *device,
4217 struct radv_color_buffer_info *cb,
4218 struct radv_image_view *iview)
4219 {
4220 const struct vk_format_description *desc;
4221 unsigned ntype, format, swap, endian;
4222 unsigned blend_clamp = 0, blend_bypass = 0;
4223 uint64_t va;
4224 const struct radv_image_plane *plane = &iview->image->planes[iview->plane_id];
4225 const struct radeon_surf *surf = &plane->surface;
4226
4227 desc = vk_format_description(iview->vk_format);
4228
4229 memset(cb, 0, sizeof(*cb));
4230
4231 /* Intensity is implemented as Red, so treat it that way. */
4232 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
4233
4234 va = radv_buffer_get_va(iview->bo) + iview->image->offset + plane->offset;
4235
4236 cb->cb_color_base = va >> 8;
4237
4238 if (device->physical_device->rad_info.chip_class >= GFX9) {
4239 struct gfx9_surf_meta_flags meta;
4240 if (iview->image->dcc_offset)
4241 meta = surf->u.gfx9.dcc;
4242 else
4243 meta = surf->u.gfx9.cmask;
4244
4245 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4246 S_028C74_FMASK_SW_MODE(surf->u.gfx9.fmask.swizzle_mode) |
4247 S_028C74_RB_ALIGNED(meta.rb_aligned) |
4248 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
4249
4250 cb->cb_color_base += surf->u.gfx9.surf_offset >> 8;
4251 cb->cb_color_base |= surf->tile_swizzle;
4252
4253 cb->cb_mrt_epitch = S_0287A0_EPITCH(surf->u.gfx9.surf.epitch);
4254 } else {
4255 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
4256 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
4257
4258 cb->cb_color_base += level_info->offset >> 8;
4259 if (level_info->mode == RADEON_SURF_MODE_2D)
4260 cb->cb_color_base |= surf->tile_swizzle;
4261
4262 pitch_tile_max = level_info->nblk_x / 8 - 1;
4263 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
4264 tile_mode_index = si_tile_mode_index(plane, iview->base_mip, false);
4265
4266 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
4267 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
4268 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
4269
4270 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
4271
4272 if (radv_image_has_fmask(iview->image)) {
4273 if (device->physical_device->rad_info.chip_class >= CIK)
4274 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
4275 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
4276 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
4277 } else {
4278 /* This must be set for fast clear to work without FMASK. */
4279 if (device->physical_device->rad_info.chip_class >= CIK)
4280 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
4281 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
4282 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
4283 }
4284 }
4285
4286 /* CMASK variables */
4287 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4288 va += iview->image->cmask.offset;
4289 cb->cb_color_cmask = va >> 8;
4290
4291 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4292 va += iview->image->dcc_offset;
4293 cb->cb_dcc_base = va >> 8;
4294 cb->cb_dcc_base |= surf->tile_swizzle;
4295
4296 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4297 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
4298 S_028C6C_SLICE_MAX(max_slice);
4299
4300 if (iview->image->info.samples > 1) {
4301 unsigned log_samples = util_logbase2(iview->image->info.samples);
4302
4303 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
4304 S_028C74_NUM_FRAGMENTS(log_samples);
4305 }
4306
4307 if (radv_image_has_fmask(iview->image)) {
4308 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
4309 cb->cb_color_fmask = va >> 8;
4310 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
4311 } else {
4312 cb->cb_color_fmask = cb->cb_color_base;
4313 }
4314
4315 ntype = radv_translate_color_numformat(iview->vk_format,
4316 desc,
4317 vk_format_get_first_non_void_channel(iview->vk_format));
4318 format = radv_translate_colorformat(iview->vk_format);
4319 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
4320 radv_finishme("Illegal color\n");
4321 swap = radv_translate_colorswap(iview->vk_format, FALSE);
4322 endian = radv_colorformat_endian_swap(format);
4323
4324 /* blend clamp should be set for all NORM/SRGB types */
4325 if (ntype == V_028C70_NUMBER_UNORM ||
4326 ntype == V_028C70_NUMBER_SNORM ||
4327 ntype == V_028C70_NUMBER_SRGB)
4328 blend_clamp = 1;
4329
4330 /* set blend bypass according to docs if SINT/UINT or
4331 8/24 COLOR variants */
4332 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
4333 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
4334 format == V_028C70_COLOR_X24_8_32_FLOAT) {
4335 blend_clamp = 0;
4336 blend_bypass = 1;
4337 }
4338 #if 0
4339 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
4340 (format == V_028C70_COLOR_8 ||
4341 format == V_028C70_COLOR_8_8 ||
4342 format == V_028C70_COLOR_8_8_8_8))
4343 ->color_is_int8 = true;
4344 #endif
4345 cb->cb_color_info = S_028C70_FORMAT(format) |
4346 S_028C70_COMP_SWAP(swap) |
4347 S_028C70_BLEND_CLAMP(blend_clamp) |
4348 S_028C70_BLEND_BYPASS(blend_bypass) |
4349 S_028C70_SIMPLE_FLOAT(1) |
4350 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
4351 ntype != V_028C70_NUMBER_SNORM &&
4352 ntype != V_028C70_NUMBER_SRGB &&
4353 format != V_028C70_COLOR_8_24 &&
4354 format != V_028C70_COLOR_24_8) |
4355 S_028C70_NUMBER_TYPE(ntype) |
4356 S_028C70_ENDIAN(endian);
4357 if (radv_image_has_fmask(iview->image)) {
4358 cb->cb_color_info |= S_028C70_COMPRESSION(1);
4359 if (device->physical_device->rad_info.chip_class == SI) {
4360 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
4361 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
4362 }
4363 }
4364
4365 if (radv_image_has_cmask(iview->image) &&
4366 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
4367 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
4368
4369 if (radv_dcc_enabled(iview->image, iview->base_mip))
4370 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
4371
4372 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
4373
4374 /* This must be set for fast clear to work without FMASK. */
4375 if (!radv_image_has_fmask(iview->image) &&
4376 device->physical_device->rad_info.chip_class == SI) {
4377 unsigned bankh = util_logbase2(surf->u.legacy.bankh);
4378 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
4379 }
4380
4381 if (device->physical_device->rad_info.chip_class >= GFX9) {
4382 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
4383 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
4384
4385 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
4386 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
4387 S_028C74_RESOURCE_TYPE(surf->u.gfx9.resource_type);
4388 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
4389 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
4390 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4391 }
4392 }
4393
4394 static unsigned
4395 radv_calc_decompress_on_z_planes(struct radv_device *device,
4396 struct radv_image_view *iview)
4397 {
4398 unsigned max_zplanes = 0;
4399
4400 assert(radv_image_is_tc_compat_htile(iview->image));
4401
4402 if (device->physical_device->rad_info.chip_class >= GFX9) {
4403 /* Default value for 32-bit depth surfaces. */
4404 max_zplanes = 4;
4405
4406 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4407 iview->image->info.samples > 1)
4408 max_zplanes = 2;
4409
4410 max_zplanes = max_zplanes + 1;
4411 } else {
4412 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4413 /* Do not enable Z plane compression for 16-bit depth
4414 * surfaces because isn't supported on GFX8. Only
4415 * 32-bit depth surfaces are supported by the hardware.
4416 * This allows to maintain shader compatibility and to
4417 * reduce the number of depth decompressions.
4418 */
4419 max_zplanes = 1;
4420 } else {
4421 if (iview->image->info.samples <= 1)
4422 max_zplanes = 5;
4423 else if (iview->image->info.samples <= 4)
4424 max_zplanes = 3;
4425 else
4426 max_zplanes = 2;
4427 }
4428 }
4429
4430 return max_zplanes;
4431 }
4432
4433 static void
4434 radv_initialise_ds_surface(struct radv_device *device,
4435 struct radv_ds_buffer_info *ds,
4436 struct radv_image_view *iview)
4437 {
4438 unsigned level = iview->base_mip;
4439 unsigned format, stencil_format;
4440 uint64_t va, s_offs, z_offs;
4441 bool stencil_only = false;
4442 const struct radv_image_plane *plane = &iview->image->planes[0];
4443 const struct radeon_surf *surf = &plane->surface;
4444
4445 assert(vk_format_get_plane_count(iview->image->vk_format) == 1);
4446
4447 memset(ds, 0, sizeof(*ds));
4448 switch (iview->image->vk_format) {
4449 case VK_FORMAT_D24_UNORM_S8_UINT:
4450 case VK_FORMAT_X8_D24_UNORM_PACK32:
4451 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4452 ds->offset_scale = 2.0f;
4453 break;
4454 case VK_FORMAT_D16_UNORM:
4455 case VK_FORMAT_D16_UNORM_S8_UINT:
4456 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4457 ds->offset_scale = 4.0f;
4458 break;
4459 case VK_FORMAT_D32_SFLOAT:
4460 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4461 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4462 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4463 ds->offset_scale = 1.0f;
4464 break;
4465 case VK_FORMAT_S8_UINT:
4466 stencil_only = true;
4467 break;
4468 default:
4469 break;
4470 }
4471
4472 format = radv_translate_dbformat(iview->image->vk_format);
4473 stencil_format = surf->has_stencil ?
4474 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4475
4476 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4477 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4478 S_028008_SLICE_MAX(max_slice);
4479
4480 ds->db_htile_data_base = 0;
4481 ds->db_htile_surface = 0;
4482
4483 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4484 s_offs = z_offs = va;
4485
4486 if (device->physical_device->rad_info.chip_class >= GFX9) {
4487 assert(surf->u.gfx9.surf_offset == 0);
4488 s_offs += surf->u.gfx9.stencil_offset;
4489
4490 ds->db_z_info = S_028038_FORMAT(format) |
4491 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4492 S_028038_SW_MODE(surf->u.gfx9.surf.swizzle_mode) |
4493 S_028038_MAXMIP(iview->image->info.levels - 1) |
4494 S_028038_ZRANGE_PRECISION(1);
4495 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4496 S_02803C_SW_MODE(surf->u.gfx9.stencil.swizzle_mode);
4497
4498 ds->db_z_info2 = S_028068_EPITCH(surf->u.gfx9.surf.epitch);
4499 ds->db_stencil_info2 = S_02806C_EPITCH(surf->u.gfx9.stencil.epitch);
4500 ds->db_depth_view |= S_028008_MIPID(level);
4501
4502 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4503 S_02801C_Y_MAX(iview->image->info.height - 1);
4504
4505 if (radv_htile_enabled(iview->image, level)) {
4506 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4507
4508 if (radv_image_is_tc_compat_htile(iview->image)) {
4509 unsigned max_zplanes =
4510 radv_calc_decompress_on_z_planes(device, iview);
4511
4512 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4513 S_028038_ITERATE_FLUSH(1);
4514 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4515 }
4516
4517 if (!surf->has_stencil)
4518 /* Use all of the htile_buffer for depth if there's no stencil. */
4519 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4520 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4521 iview->image->htile_offset;
4522 ds->db_htile_data_base = va >> 8;
4523 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4524 S_028ABC_PIPE_ALIGNED(surf->u.gfx9.htile.pipe_aligned) |
4525 S_028ABC_RB_ALIGNED(surf->u.gfx9.htile.rb_aligned);
4526 }
4527 } else {
4528 const struct legacy_surf_level *level_info = &surf->u.legacy.level[level];
4529
4530 if (stencil_only)
4531 level_info = &surf->u.legacy.stencil_level[level];
4532
4533 z_offs += surf->u.legacy.level[level].offset;
4534 s_offs += surf->u.legacy.stencil_level[level].offset;
4535
4536 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4537 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4538 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4539
4540 if (iview->image->info.samples > 1)
4541 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4542
4543 if (device->physical_device->rad_info.chip_class >= CIK) {
4544 struct radeon_info *info = &device->physical_device->rad_info;
4545 unsigned tiling_index = surf->u.legacy.tiling_index[level];
4546 unsigned stencil_index = surf->u.legacy.stencil_tiling_index[level];
4547 unsigned macro_index = surf->u.legacy.macro_tile_index;
4548 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4549 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4550 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4551
4552 if (stencil_only)
4553 tile_mode = stencil_tile_mode;
4554
4555 ds->db_depth_info |=
4556 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4557 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4558 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4559 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4560 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4561 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4562 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4563 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4564 } else {
4565 unsigned tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, false);
4566 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4567 tile_mode_index = si_tile_mode_index(&iview->image->planes[0], level, true);
4568 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4569 if (stencil_only)
4570 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4571 }
4572
4573 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4574 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4575 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4576
4577 if (radv_htile_enabled(iview->image, level)) {
4578 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4579
4580 if (!surf->has_stencil &&
4581 !radv_image_is_tc_compat_htile(iview->image))
4582 /* Use all of the htile_buffer for depth if there's no stencil. */
4583 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4584
4585 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4586 iview->image->htile_offset;
4587 ds->db_htile_data_base = va >> 8;
4588 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4589
4590 if (radv_image_is_tc_compat_htile(iview->image)) {
4591 unsigned max_zplanes =
4592 radv_calc_decompress_on_z_planes(device, iview);
4593
4594 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4595 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4596 }
4597 }
4598 }
4599
4600 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4601 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4602 }
4603
4604 VkResult radv_CreateFramebuffer(
4605 VkDevice _device,
4606 const VkFramebufferCreateInfo* pCreateInfo,
4607 const VkAllocationCallbacks* pAllocator,
4608 VkFramebuffer* pFramebuffer)
4609 {
4610 RADV_FROM_HANDLE(radv_device, device, _device);
4611 struct radv_framebuffer *framebuffer;
4612
4613 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4614
4615 size_t size = sizeof(*framebuffer) +
4616 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4617 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4618 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4619 if (framebuffer == NULL)
4620 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4621
4622 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4623 framebuffer->width = pCreateInfo->width;
4624 framebuffer->height = pCreateInfo->height;
4625 framebuffer->layers = pCreateInfo->layers;
4626 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4627 VkImageView _iview = pCreateInfo->pAttachments[i];
4628 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4629 framebuffer->attachments[i].attachment = iview;
4630 if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4631 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4632 } else {
4633 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4634 }
4635 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4636 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4637 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4638 }
4639
4640 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4641 return VK_SUCCESS;
4642 }
4643
4644 void radv_DestroyFramebuffer(
4645 VkDevice _device,
4646 VkFramebuffer _fb,
4647 const VkAllocationCallbacks* pAllocator)
4648 {
4649 RADV_FROM_HANDLE(radv_device, device, _device);
4650 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4651
4652 if (!fb)
4653 return;
4654 vk_free2(&device->alloc, pAllocator, fb);
4655 }
4656
4657 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4658 {
4659 switch (address_mode) {
4660 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4661 return V_008F30_SQ_TEX_WRAP;
4662 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4663 return V_008F30_SQ_TEX_MIRROR;
4664 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4665 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4666 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4667 return V_008F30_SQ_TEX_CLAMP_BORDER;
4668 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4669 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4670 default:
4671 unreachable("illegal tex wrap mode");
4672 break;
4673 }
4674 }
4675
4676 static unsigned
4677 radv_tex_compare(VkCompareOp op)
4678 {
4679 switch (op) {
4680 case VK_COMPARE_OP_NEVER:
4681 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4682 case VK_COMPARE_OP_LESS:
4683 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4684 case VK_COMPARE_OP_EQUAL:
4685 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4686 case VK_COMPARE_OP_LESS_OR_EQUAL:
4687 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4688 case VK_COMPARE_OP_GREATER:
4689 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4690 case VK_COMPARE_OP_NOT_EQUAL:
4691 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4692 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4693 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4694 case VK_COMPARE_OP_ALWAYS:
4695 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4696 default:
4697 unreachable("illegal compare mode");
4698 break;
4699 }
4700 }
4701
4702 static unsigned
4703 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4704 {
4705 switch (filter) {
4706 case VK_FILTER_NEAREST:
4707 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4708 V_008F38_SQ_TEX_XY_FILTER_POINT);
4709 case VK_FILTER_LINEAR:
4710 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4711 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4712 case VK_FILTER_CUBIC_IMG:
4713 default:
4714 fprintf(stderr, "illegal texture filter");
4715 return 0;
4716 }
4717 }
4718
4719 static unsigned
4720 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4721 {
4722 switch (mode) {
4723 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4724 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4725 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4726 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4727 default:
4728 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4729 }
4730 }
4731
4732 static unsigned
4733 radv_tex_bordercolor(VkBorderColor bcolor)
4734 {
4735 switch (bcolor) {
4736 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4737 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4738 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4739 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4740 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4741 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4742 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4743 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4744 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4745 default:
4746 break;
4747 }
4748 return 0;
4749 }
4750
4751 static unsigned
4752 radv_tex_aniso_filter(unsigned filter)
4753 {
4754 if (filter < 2)
4755 return 0;
4756 if (filter < 4)
4757 return 1;
4758 if (filter < 8)
4759 return 2;
4760 if (filter < 16)
4761 return 3;
4762 return 4;
4763 }
4764
4765 static unsigned
4766 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4767 {
4768 switch (mode) {
4769 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4770 return V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4771 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4772 return V_008F30_SQ_IMG_FILTER_MODE_MIN;
4773 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4774 return V_008F30_SQ_IMG_FILTER_MODE_MAX;
4775 default:
4776 break;
4777 }
4778 return 0;
4779 }
4780
4781 static uint32_t
4782 radv_get_max_anisotropy(struct radv_device *device,
4783 const VkSamplerCreateInfo *pCreateInfo)
4784 {
4785 if (device->force_aniso >= 0)
4786 return device->force_aniso;
4787
4788 if (pCreateInfo->anisotropyEnable &&
4789 pCreateInfo->maxAnisotropy > 1.0f)
4790 return (uint32_t)pCreateInfo->maxAnisotropy;
4791
4792 return 0;
4793 }
4794
4795 static void
4796 radv_init_sampler(struct radv_device *device,
4797 struct radv_sampler *sampler,
4798 const VkSamplerCreateInfo *pCreateInfo)
4799 {
4800 uint32_t max_aniso = radv_get_max_anisotropy(device, pCreateInfo);
4801 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4802 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4803 unsigned filter_mode = V_008F30_SQ_IMG_FILTER_MODE_BLEND;
4804
4805 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4806 vk_find_struct_const(pCreateInfo->pNext,
4807 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4808 if (sampler_reduction)
4809 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4810
4811 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4812 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4813 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4814 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4815 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4816 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4817 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4818 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4819 S_008F30_DISABLE_CUBE_WRAP(0) |
4820 S_008F30_COMPAT_MODE(is_vi) |
4821 S_008F30_FILTER_MODE(filter_mode));
4822 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4823 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4824 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4825 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4826 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4827 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4828 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4829 S_008F38_MIP_POINT_PRECLAMP(0) |
4830 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4831 S_008F38_FILTER_PREC_FIX(1) |
4832 S_008F38_ANISO_OVERRIDE(is_vi));
4833 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4834 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4835 }
4836
4837 VkResult radv_CreateSampler(
4838 VkDevice _device,
4839 const VkSamplerCreateInfo* pCreateInfo,
4840 const VkAllocationCallbacks* pAllocator,
4841 VkSampler* pSampler)
4842 {
4843 RADV_FROM_HANDLE(radv_device, device, _device);
4844 struct radv_sampler *sampler;
4845
4846 const struct VkSamplerYcbcrConversionInfo *ycbcr_conversion =
4847 vk_find_struct_const(pCreateInfo->pNext,
4848 SAMPLER_YCBCR_CONVERSION_INFO);
4849
4850 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4851
4852 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4853 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4854 if (!sampler)
4855 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4856
4857 radv_init_sampler(device, sampler, pCreateInfo);
4858
4859 sampler->ycbcr_sampler = ycbcr_conversion ? radv_sampler_ycbcr_conversion_from_handle(ycbcr_conversion->conversion): NULL;
4860 *pSampler = radv_sampler_to_handle(sampler);
4861
4862 return VK_SUCCESS;
4863 }
4864
4865 void radv_DestroySampler(
4866 VkDevice _device,
4867 VkSampler _sampler,
4868 const VkAllocationCallbacks* pAllocator)
4869 {
4870 RADV_FROM_HANDLE(radv_device, device, _device);
4871 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4872
4873 if (!sampler)
4874 return;
4875 vk_free2(&device->alloc, pAllocator, sampler);
4876 }
4877
4878 /* vk_icd.h does not declare this function, so we declare it here to
4879 * suppress Wmissing-prototypes.
4880 */
4881 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4882 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4883
4884 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4885 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4886 {
4887 /* For the full details on loader interface versioning, see
4888 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4889 * What follows is a condensed summary, to help you navigate the large and
4890 * confusing official doc.
4891 *
4892 * - Loader interface v0 is incompatible with later versions. We don't
4893 * support it.
4894 *
4895 * - In loader interface v1:
4896 * - The first ICD entrypoint called by the loader is
4897 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4898 * entrypoint.
4899 * - The ICD must statically expose no other Vulkan symbol unless it is
4900 * linked with -Bsymbolic.
4901 * - Each dispatchable Vulkan handle created by the ICD must be
4902 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4903 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4904 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4905 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4906 * such loader-managed surfaces.
4907 *
4908 * - Loader interface v2 differs from v1 in:
4909 * - The first ICD entrypoint called by the loader is
4910 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4911 * statically expose this entrypoint.
4912 *
4913 * - Loader interface v3 differs from v2 in:
4914 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4915 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4916 * because the loader no longer does so.
4917 */
4918 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4919 return VK_SUCCESS;
4920 }
4921
4922 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4923 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4924 int *pFD)
4925 {
4926 RADV_FROM_HANDLE(radv_device, device, _device);
4927 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4928
4929 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4930
4931 /* At the moment, we support only the below handle types. */
4932 assert(pGetFdInfo->handleType ==
4933 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT ||
4934 pGetFdInfo->handleType ==
4935 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4936
4937 bool ret = radv_get_memory_fd(device, memory, pFD);
4938 if (ret == false)
4939 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4940 return VK_SUCCESS;
4941 }
4942
4943 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4944 VkExternalMemoryHandleTypeFlagBits handleType,
4945 int fd,
4946 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4947 {
4948 RADV_FROM_HANDLE(radv_device, device, _device);
4949
4950 switch (handleType) {
4951 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4952 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4953 return VK_SUCCESS;
4954
4955 default:
4956 /* The valid usage section for this function says:
4957 *
4958 * "handleType must not be one of the handle types defined as
4959 * opaque."
4960 *
4961 * So opaque handle types fall into the default "unsupported" case.
4962 */
4963 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4964 }
4965 }
4966
4967 static VkResult radv_import_opaque_fd(struct radv_device *device,
4968 int fd,
4969 uint32_t *syncobj)
4970 {
4971 uint32_t syncobj_handle = 0;
4972 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4973 if (ret != 0)
4974 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4975
4976 if (*syncobj)
4977 device->ws->destroy_syncobj(device->ws, *syncobj);
4978
4979 *syncobj = syncobj_handle;
4980 close(fd);
4981
4982 return VK_SUCCESS;
4983 }
4984
4985 static VkResult radv_import_sync_fd(struct radv_device *device,
4986 int fd,
4987 uint32_t *syncobj)
4988 {
4989 /* If we create a syncobj we do it locally so that if we have an error, we don't
4990 * leave a syncobj in an undetermined state in the fence. */
4991 uint32_t syncobj_handle = *syncobj;
4992 if (!syncobj_handle) {
4993 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4994 if (ret) {
4995 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
4996 }
4997 }
4998
4999 if (fd == -1) {
5000 device->ws->signal_syncobj(device->ws, syncobj_handle);
5001 } else {
5002 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
5003 if (ret != 0)
5004 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5005 }
5006
5007 *syncobj = syncobj_handle;
5008 if (fd != -1)
5009 close(fd);
5010
5011 return VK_SUCCESS;
5012 }
5013
5014 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
5015 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
5016 {
5017 RADV_FROM_HANDLE(radv_device, device, _device);
5018 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
5019 uint32_t *syncobj_dst = NULL;
5020
5021 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT) {
5022 syncobj_dst = &sem->temp_syncobj;
5023 } else {
5024 syncobj_dst = &sem->syncobj;
5025 }
5026
5027 switch(pImportSemaphoreFdInfo->handleType) {
5028 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5029 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5030 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5031 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
5032 default:
5033 unreachable("Unhandled semaphore handle type");
5034 }
5035 }
5036
5037 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
5038 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
5039 int *pFd)
5040 {
5041 RADV_FROM_HANDLE(radv_device, device, _device);
5042 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
5043 int ret;
5044 uint32_t syncobj_handle;
5045
5046 if (sem->temp_syncobj)
5047 syncobj_handle = sem->temp_syncobj;
5048 else
5049 syncobj_handle = sem->syncobj;
5050
5051 switch(pGetFdInfo->handleType) {
5052 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT:
5053 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5054 break;
5055 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT:
5056 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5057 if (!ret) {
5058 if (sem->temp_syncobj) {
5059 close (sem->temp_syncobj);
5060 sem->temp_syncobj = 0;
5061 } else {
5062 device->ws->reset_syncobj(device->ws, syncobj_handle);
5063 }
5064 }
5065 break;
5066 default:
5067 unreachable("Unhandled semaphore handle type");
5068 }
5069
5070 if (ret)
5071 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5072 return VK_SUCCESS;
5073 }
5074
5075 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
5076 VkPhysicalDevice physicalDevice,
5077 const VkPhysicalDeviceExternalSemaphoreInfo *pExternalSemaphoreInfo,
5078 VkExternalSemaphoreProperties *pExternalSemaphoreProperties)
5079 {
5080 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5081
5082 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
5083 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5084 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5085 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT)) {
5086 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5087 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT;
5088 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5089 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5090 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT) {
5091 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5092 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT;
5093 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT |
5094 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5095 } else {
5096 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
5097 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
5098 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
5099 }
5100 }
5101
5102 VkResult radv_ImportFenceFdKHR(VkDevice _device,
5103 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
5104 {
5105 RADV_FROM_HANDLE(radv_device, device, _device);
5106 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
5107 uint32_t *syncobj_dst = NULL;
5108
5109
5110 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT) {
5111 syncobj_dst = &fence->temp_syncobj;
5112 } else {
5113 syncobj_dst = &fence->syncobj;
5114 }
5115
5116 switch(pImportFenceFdInfo->handleType) {
5117 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5118 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5119 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5120 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
5121 default:
5122 unreachable("Unhandled fence handle type");
5123 }
5124 }
5125
5126 VkResult radv_GetFenceFdKHR(VkDevice _device,
5127 const VkFenceGetFdInfoKHR *pGetFdInfo,
5128 int *pFd)
5129 {
5130 RADV_FROM_HANDLE(radv_device, device, _device);
5131 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
5132 int ret;
5133 uint32_t syncobj_handle;
5134
5135 if (fence->temp_syncobj)
5136 syncobj_handle = fence->temp_syncobj;
5137 else
5138 syncobj_handle = fence->syncobj;
5139
5140 switch(pGetFdInfo->handleType) {
5141 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT:
5142 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
5143 break;
5144 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT:
5145 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
5146 if (!ret) {
5147 if (fence->temp_syncobj) {
5148 close (fence->temp_syncobj);
5149 fence->temp_syncobj = 0;
5150 } else {
5151 device->ws->reset_syncobj(device->ws, syncobj_handle);
5152 }
5153 }
5154 break;
5155 default:
5156 unreachable("Unhandled fence handle type");
5157 }
5158
5159 if (ret)
5160 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE);
5161 return VK_SUCCESS;
5162 }
5163
5164 void radv_GetPhysicalDeviceExternalFenceProperties(
5165 VkPhysicalDevice physicalDevice,
5166 const VkPhysicalDeviceExternalFenceInfo *pExternalFenceInfo,
5167 VkExternalFenceProperties *pExternalFenceProperties)
5168 {
5169 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
5170
5171 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
5172 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT ||
5173 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT)) {
5174 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5175 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT;
5176 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT |
5177 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT;
5178 } else {
5179 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
5180 pExternalFenceProperties->compatibleHandleTypes = 0;
5181 pExternalFenceProperties->externalFenceFeatures = 0;
5182 }
5183 }
5184
5185 VkResult
5186 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
5187 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
5188 const VkAllocationCallbacks* pAllocator,
5189 VkDebugReportCallbackEXT* pCallback)
5190 {
5191 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5192 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
5193 pCreateInfo, pAllocator, &instance->alloc,
5194 pCallback);
5195 }
5196
5197 void
5198 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
5199 VkDebugReportCallbackEXT _callback,
5200 const VkAllocationCallbacks* pAllocator)
5201 {
5202 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5203 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
5204 _callback, pAllocator, &instance->alloc);
5205 }
5206
5207 void
5208 radv_DebugReportMessageEXT(VkInstance _instance,
5209 VkDebugReportFlagsEXT flags,
5210 VkDebugReportObjectTypeEXT objectType,
5211 uint64_t object,
5212 size_t location,
5213 int32_t messageCode,
5214 const char* pLayerPrefix,
5215 const char* pMessage)
5216 {
5217 RADV_FROM_HANDLE(radv_instance, instance, _instance);
5218 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
5219 object, location, messageCode, pLayerPrefix, pMessage);
5220 }
5221
5222 void
5223 radv_GetDeviceGroupPeerMemoryFeatures(
5224 VkDevice device,
5225 uint32_t heapIndex,
5226 uint32_t localDeviceIndex,
5227 uint32_t remoteDeviceIndex,
5228 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
5229 {
5230 assert(localDeviceIndex == remoteDeviceIndex);
5231
5232 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
5233 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
5234 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
5235 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
5236 }
5237
5238 static const VkTimeDomainEXT radv_time_domains[] = {
5239 VK_TIME_DOMAIN_DEVICE_EXT,
5240 VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT,
5241 VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT,
5242 };
5243
5244 VkResult radv_GetPhysicalDeviceCalibrateableTimeDomainsEXT(
5245 VkPhysicalDevice physicalDevice,
5246 uint32_t *pTimeDomainCount,
5247 VkTimeDomainEXT *pTimeDomains)
5248 {
5249 int d;
5250 VK_OUTARRAY_MAKE(out, pTimeDomains, pTimeDomainCount);
5251
5252 for (d = 0; d < ARRAY_SIZE(radv_time_domains); d++) {
5253 vk_outarray_append(&out, i) {
5254 *i = radv_time_domains[d];
5255 }
5256 }
5257
5258 return vk_outarray_status(&out);
5259 }
5260
5261 static uint64_t
5262 radv_clock_gettime(clockid_t clock_id)
5263 {
5264 struct timespec current;
5265 int ret;
5266
5267 ret = clock_gettime(clock_id, &current);
5268 if (ret < 0 && clock_id == CLOCK_MONOTONIC_RAW)
5269 ret = clock_gettime(CLOCK_MONOTONIC, &current);
5270 if (ret < 0)
5271 return 0;
5272
5273 return (uint64_t) current.tv_sec * 1000000000ULL + current.tv_nsec;
5274 }
5275
5276 VkResult radv_GetCalibratedTimestampsEXT(
5277 VkDevice _device,
5278 uint32_t timestampCount,
5279 const VkCalibratedTimestampInfoEXT *pTimestampInfos,
5280 uint64_t *pTimestamps,
5281 uint64_t *pMaxDeviation)
5282 {
5283 RADV_FROM_HANDLE(radv_device, device, _device);
5284 uint32_t clock_crystal_freq = device->physical_device->rad_info.clock_crystal_freq;
5285 int d;
5286 uint64_t begin, end;
5287 uint64_t max_clock_period = 0;
5288
5289 begin = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5290
5291 for (d = 0; d < timestampCount; d++) {
5292 switch (pTimestampInfos[d].timeDomain) {
5293 case VK_TIME_DOMAIN_DEVICE_EXT:
5294 pTimestamps[d] = device->ws->query_value(device->ws,
5295 RADEON_TIMESTAMP);
5296 uint64_t device_period = DIV_ROUND_UP(1000000, clock_crystal_freq);
5297 max_clock_period = MAX2(max_clock_period, device_period);
5298 break;
5299 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_EXT:
5300 pTimestamps[d] = radv_clock_gettime(CLOCK_MONOTONIC);
5301 max_clock_period = MAX2(max_clock_period, 1);
5302 break;
5303
5304 case VK_TIME_DOMAIN_CLOCK_MONOTONIC_RAW_EXT:
5305 pTimestamps[d] = begin;
5306 break;
5307 default:
5308 pTimestamps[d] = 0;
5309 break;
5310 }
5311 }
5312
5313 end = radv_clock_gettime(CLOCK_MONOTONIC_RAW);
5314
5315 /*
5316 * The maximum deviation is the sum of the interval over which we
5317 * perform the sampling and the maximum period of any sampled
5318 * clock. That's because the maximum skew between any two sampled
5319 * clock edges is when the sampled clock with the largest period is
5320 * sampled at the end of that period but right at the beginning of the
5321 * sampling interval and some other clock is sampled right at the
5322 * begining of its sampling period and right at the end of the
5323 * sampling interval. Let's assume the GPU has the longest clock
5324 * period and that the application is sampling GPU and monotonic:
5325 *
5326 * s e
5327 * w x y z 0 1 2 3 4 5 6 7 8 9 a b c d e f
5328 * Raw -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5329 *
5330 * g
5331 * 0 1 2 3
5332 * GPU -----_____-----_____-----_____-----_____
5333 *
5334 * m
5335 * x y z 0 1 2 3 4 5 6 7 8 9 a b c
5336 * Monotonic -_-_-_-_-_-_-_-_-_-_-_-_-_-_-_-
5337 *
5338 * Interval <----------------->
5339 * Deviation <-------------------------->
5340 *
5341 * s = read(raw) 2
5342 * g = read(GPU) 1
5343 * m = read(monotonic) 2
5344 * e = read(raw) b
5345 *
5346 * We round the sample interval up by one tick to cover sampling error
5347 * in the interval clock
5348 */
5349
5350 uint64_t sample_interval = end - begin + 1;
5351
5352 *pMaxDeviation = sample_interval + max_clock_period;
5353
5354 return VK_SUCCESS;
5355 }