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radv: Create single RADV_DEBUG env var.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <dlfcn.h>
29 #include <stdbool.h>
30 #include <string.h>
31 #include <unistd.h>
32 #include <fcntl.h>
33 #include <sys/stat.h>
34 #include "radv_private.h"
35 #include "util/strtod.h"
36
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46 struct radv_dispatch_table dtable;
47
48 static int
49 radv_get_function_timestamp(void *ptr, uint32_t* timestamp)
50 {
51 Dl_info info;
52 struct stat st;
53 if (!dladdr(ptr, &info) || !info.dli_fname) {
54 return -1;
55 }
56 if (stat(info.dli_fname, &st)) {
57 return -1;
58 }
59 *timestamp = st.st_mtim.tv_sec;
60 return 0;
61 }
62
63 static int
64 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
65 {
66 uint32_t mesa_timestamp, llvm_timestamp;
67 uint16_t f = family;
68 memset(uuid, 0, VK_UUID_SIZE);
69 if (radv_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
70 radv_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
71 return -1;
72
73 memcpy(uuid, &mesa_timestamp, 4);
74 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
75 memcpy((char*)uuid + 8, &f, 2);
76 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
77 return 0;
78 }
79
80 static VkResult
81 radv_physical_device_init(struct radv_physical_device *device,
82 struct radv_instance *instance,
83 const char *path)
84 {
85 VkResult result;
86 drmVersionPtr version;
87 int fd;
88
89 fd = open(path, O_RDWR | O_CLOEXEC);
90 if (fd < 0)
91 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
92 "failed to open %s: %m", path);
93
94 version = drmGetVersion(fd);
95 if (!version) {
96 close(fd);
97 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
98 "failed to get version %s: %m", path);
99 }
100
101 if (strcmp(version->name, "amdgpu")) {
102 drmFreeVersion(version);
103 close(fd);
104 return VK_ERROR_INCOMPATIBLE_DRIVER;
105 }
106 drmFreeVersion(version);
107
108 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
109 device->instance = instance;
110 assert(strlen(path) < ARRAY_SIZE(device->path));
111 strncpy(device->path, path, ARRAY_SIZE(device->path));
112
113 device->ws = radv_amdgpu_winsys_create(fd);
114 if (!device->ws) {
115 result = VK_ERROR_INCOMPATIBLE_DRIVER;
116 goto fail;
117 }
118 device->ws->query_info(device->ws, &device->rad_info);
119 result = radv_init_wsi(device);
120 if (result != VK_SUCCESS) {
121 device->ws->destroy(device->ws);
122 goto fail;
123 }
124
125 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
126 radv_finish_wsi(device);
127 device->ws->destroy(device->ws);
128 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
129 "cannot generate UUID");
130 goto fail;
131 }
132
133 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
134 device->name = device->rad_info.name;
135 close(fd);
136 return VK_SUCCESS;
137
138 fail:
139 close(fd);
140 return result;
141 }
142
143 static void
144 radv_physical_device_finish(struct radv_physical_device *device)
145 {
146 radv_finish_wsi(device);
147 device->ws->destroy(device->ws);
148 }
149
150 static const VkExtensionProperties global_extensions[] = {
151 {
152 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
153 .specVersion = 25,
154 },
155 #ifdef VK_USE_PLATFORM_XCB_KHR
156 {
157 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
158 .specVersion = 6,
159 },
160 #endif
161 #ifdef VK_USE_PLATFORM_XLIB_KHR
162 {
163 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
164 .specVersion = 6,
165 },
166 #endif
167 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
168 {
169 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
170 .specVersion = 5,
171 },
172 #endif
173 };
174
175 static const VkExtensionProperties device_extensions[] = {
176 {
177 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
178 .specVersion = 1,
179 },
180 {
181 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
182 .specVersion = 68,
183 },
184 {
185 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
186 .specVersion = 1,
187 },
188 {
189 .extensionName = VK_AMD_NEGATIVE_VIEWPORT_HEIGHT_EXTENSION_NAME,
190 .specVersion = 1,
191 },
192 };
193
194 static void *
195 default_alloc_func(void *pUserData, size_t size, size_t align,
196 VkSystemAllocationScope allocationScope)
197 {
198 return malloc(size);
199 }
200
201 static void *
202 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
203 size_t align, VkSystemAllocationScope allocationScope)
204 {
205 return realloc(pOriginal, size);
206 }
207
208 static void
209 default_free_func(void *pUserData, void *pMemory)
210 {
211 free(pMemory);
212 }
213
214 static const VkAllocationCallbacks default_alloc = {
215 .pUserData = NULL,
216 .pfnAllocation = default_alloc_func,
217 .pfnReallocation = default_realloc_func,
218 .pfnFree = default_free_func,
219 };
220
221 static const struct debug_control radv_debug_options[] = {
222 {"fastclears", RADV_DEBUG_FAST_CLEARS},
223 {"nodcc", RADV_DEBUG_NO_DCC},
224 {"shaders", RADV_DEBUG_DUMP_SHADERS},
225 {"nocache", RADV_DEBUG_NO_CACHE},
226 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
227 {"nohiz", RADV_DEBUG_NO_HIZ},
228 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
229 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
230 {NULL, 0}
231 };
232
233 VkResult radv_CreateInstance(
234 const VkInstanceCreateInfo* pCreateInfo,
235 const VkAllocationCallbacks* pAllocator,
236 VkInstance* pInstance)
237 {
238 struct radv_instance *instance;
239
240 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
241
242 uint32_t client_version;
243 if (pCreateInfo->pApplicationInfo &&
244 pCreateInfo->pApplicationInfo->apiVersion != 0) {
245 client_version = pCreateInfo->pApplicationInfo->apiVersion;
246 } else {
247 client_version = VK_MAKE_VERSION(1, 0, 0);
248 }
249
250 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
251 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
252 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
253 "Client requested version %d.%d.%d",
254 VK_VERSION_MAJOR(client_version),
255 VK_VERSION_MINOR(client_version),
256 VK_VERSION_PATCH(client_version));
257 }
258
259 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
260 bool found = false;
261 for (uint32_t j = 0; j < ARRAY_SIZE(global_extensions); j++) {
262 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
263 global_extensions[j].extensionName) == 0) {
264 found = true;
265 break;
266 }
267 }
268 if (!found)
269 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
270 }
271
272 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
273 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
274 if (!instance)
275 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
276
277 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
278
279 if (pAllocator)
280 instance->alloc = *pAllocator;
281 else
282 instance->alloc = default_alloc;
283
284 instance->apiVersion = client_version;
285 instance->physicalDeviceCount = -1;
286
287 _mesa_locale_init();
288
289 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
290
291 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
292 radv_debug_options);
293
294 *pInstance = radv_instance_to_handle(instance);
295
296 return VK_SUCCESS;
297 }
298
299 void radv_DestroyInstance(
300 VkInstance _instance,
301 const VkAllocationCallbacks* pAllocator)
302 {
303 RADV_FROM_HANDLE(radv_instance, instance, _instance);
304
305 if (instance->physicalDeviceCount > 0) {
306 /* We support at most one physical device. */
307 assert(instance->physicalDeviceCount == 1);
308 radv_physical_device_finish(&instance->physicalDevice);
309 }
310
311 VG(VALGRIND_DESTROY_MEMPOOL(instance));
312
313 _mesa_locale_fini();
314
315 vk_free(&instance->alloc, instance);
316 }
317
318 VkResult radv_EnumeratePhysicalDevices(
319 VkInstance _instance,
320 uint32_t* pPhysicalDeviceCount,
321 VkPhysicalDevice* pPhysicalDevices)
322 {
323 RADV_FROM_HANDLE(radv_instance, instance, _instance);
324 VkResult result;
325
326 if (instance->physicalDeviceCount < 0) {
327 char path[20];
328 for (unsigned i = 0; i < 8; i++) {
329 snprintf(path, sizeof(path), "/dev/dri/renderD%d", 128 + i);
330 result = radv_physical_device_init(&instance->physicalDevice,
331 instance, path);
332 if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
333 break;
334 }
335
336 if (result == VK_ERROR_INCOMPATIBLE_DRIVER) {
337 instance->physicalDeviceCount = 0;
338 } else if (result == VK_SUCCESS) {
339 instance->physicalDeviceCount = 1;
340 } else {
341 return result;
342 }
343 }
344
345 /* pPhysicalDeviceCount is an out parameter if pPhysicalDevices is NULL;
346 * otherwise it's an inout parameter.
347 *
348 * The Vulkan spec (git aaed022) says:
349 *
350 * pPhysicalDeviceCount is a pointer to an unsigned integer variable
351 * that is initialized with the number of devices the application is
352 * prepared to receive handles to. pname:pPhysicalDevices is pointer to
353 * an array of at least this many VkPhysicalDevice handles [...].
354 *
355 * Upon success, if pPhysicalDevices is NULL, vkEnumeratePhysicalDevices
356 * overwrites the contents of the variable pointed to by
357 * pPhysicalDeviceCount with the number of physical devices in in the
358 * instance; otherwise, vkEnumeratePhysicalDevices overwrites
359 * pPhysicalDeviceCount with the number of physical handles written to
360 * pPhysicalDevices.
361 */
362 if (!pPhysicalDevices) {
363 *pPhysicalDeviceCount = instance->physicalDeviceCount;
364 } else if (*pPhysicalDeviceCount >= 1) {
365 pPhysicalDevices[0] = radv_physical_device_to_handle(&instance->physicalDevice);
366 *pPhysicalDeviceCount = 1;
367 } else if (*pPhysicalDeviceCount < instance->physicalDeviceCount) {
368 return VK_INCOMPLETE;
369 } else {
370 *pPhysicalDeviceCount = 0;
371 }
372
373 return VK_SUCCESS;
374 }
375
376 void radv_GetPhysicalDeviceFeatures(
377 VkPhysicalDevice physicalDevice,
378 VkPhysicalDeviceFeatures* pFeatures)
379 {
380 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
381
382 memset(pFeatures, 0, sizeof(*pFeatures));
383
384 *pFeatures = (VkPhysicalDeviceFeatures) {
385 .robustBufferAccess = true,
386 .fullDrawIndexUint32 = true,
387 .imageCubeArray = true,
388 .independentBlend = true,
389 .geometryShader = false,
390 .tessellationShader = false,
391 .sampleRateShading = false,
392 .dualSrcBlend = true,
393 .logicOp = true,
394 .multiDrawIndirect = true,
395 .drawIndirectFirstInstance = true,
396 .depthClamp = true,
397 .depthBiasClamp = true,
398 .fillModeNonSolid = true,
399 .depthBounds = true,
400 .wideLines = true,
401 .largePoints = true,
402 .alphaToOne = true,
403 .multiViewport = false,
404 .samplerAnisotropy = true,
405 .textureCompressionETC2 = false,
406 .textureCompressionASTC_LDR = false,
407 .textureCompressionBC = true,
408 .occlusionQueryPrecise = true,
409 .pipelineStatisticsQuery = false,
410 .vertexPipelineStoresAndAtomics = true,
411 .fragmentStoresAndAtomics = true,
412 .shaderTessellationAndGeometryPointSize = true,
413 .shaderImageGatherExtended = true,
414 .shaderStorageImageExtendedFormats = true,
415 .shaderStorageImageMultisample = false,
416 .shaderUniformBufferArrayDynamicIndexing = true,
417 .shaderSampledImageArrayDynamicIndexing = true,
418 .shaderStorageBufferArrayDynamicIndexing = true,
419 .shaderStorageImageArrayDynamicIndexing = true,
420 .shaderStorageImageReadWithoutFormat = false,
421 .shaderStorageImageWriteWithoutFormat = false,
422 .shaderClipDistance = true,
423 .shaderCullDistance = true,
424 .shaderFloat64 = false,
425 .shaderInt64 = false,
426 .shaderInt16 = false,
427 .alphaToOne = true,
428 .variableMultisampleRate = false,
429 .inheritedQueries = false,
430 };
431 }
432
433 void radv_GetPhysicalDeviceProperties(
434 VkPhysicalDevice physicalDevice,
435 VkPhysicalDeviceProperties* pProperties)
436 {
437 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
438 VkSampleCountFlags sample_counts = 0xf;
439 VkPhysicalDeviceLimits limits = {
440 .maxImageDimension1D = (1 << 14),
441 .maxImageDimension2D = (1 << 14),
442 .maxImageDimension3D = (1 << 11),
443 .maxImageDimensionCube = (1 << 14),
444 .maxImageArrayLayers = (1 << 11),
445 .maxTexelBufferElements = 128 * 1024 * 1024,
446 .maxUniformBufferRange = UINT32_MAX,
447 .maxStorageBufferRange = UINT32_MAX,
448 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
449 .maxMemoryAllocationCount = UINT32_MAX,
450 .maxSamplerAllocationCount = 64 * 1024,
451 .bufferImageGranularity = 64, /* A cache line */
452 .sparseAddressSpaceSize = 0,
453 .maxBoundDescriptorSets = MAX_SETS,
454 .maxPerStageDescriptorSamplers = 64,
455 .maxPerStageDescriptorUniformBuffers = 64,
456 .maxPerStageDescriptorStorageBuffers = 64,
457 .maxPerStageDescriptorSampledImages = 64,
458 .maxPerStageDescriptorStorageImages = 64,
459 .maxPerStageDescriptorInputAttachments = 64,
460 .maxPerStageResources = 128,
461 .maxDescriptorSetSamplers = 256,
462 .maxDescriptorSetUniformBuffers = 256,
463 .maxDescriptorSetUniformBuffersDynamic = 256,
464 .maxDescriptorSetStorageBuffers = 256,
465 .maxDescriptorSetStorageBuffersDynamic = 256,
466 .maxDescriptorSetSampledImages = 256,
467 .maxDescriptorSetStorageImages = 256,
468 .maxDescriptorSetInputAttachments = 256,
469 .maxVertexInputAttributes = 32,
470 .maxVertexInputBindings = 32,
471 .maxVertexInputAttributeOffset = 2047,
472 .maxVertexInputBindingStride = 2048,
473 .maxVertexOutputComponents = 128,
474 .maxTessellationGenerationLevel = 0,
475 .maxTessellationPatchSize = 0,
476 .maxTessellationControlPerVertexInputComponents = 0,
477 .maxTessellationControlPerVertexOutputComponents = 0,
478 .maxTessellationControlPerPatchOutputComponents = 0,
479 .maxTessellationControlTotalOutputComponents = 0,
480 .maxTessellationEvaluationInputComponents = 0,
481 .maxTessellationEvaluationOutputComponents = 0,
482 .maxGeometryShaderInvocations = 32,
483 .maxGeometryInputComponents = 64,
484 .maxGeometryOutputComponents = 128,
485 .maxGeometryOutputVertices = 256,
486 .maxGeometryTotalOutputComponents = 1024,
487 .maxFragmentInputComponents = 128,
488 .maxFragmentOutputAttachments = 8,
489 .maxFragmentDualSrcAttachments = 1,
490 .maxFragmentCombinedOutputResources = 8,
491 .maxComputeSharedMemorySize = 32768,
492 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
493 .maxComputeWorkGroupInvocations = 2048,
494 .maxComputeWorkGroupSize = {
495 2048,
496 2048,
497 2048
498 },
499 .subPixelPrecisionBits = 4 /* FIXME */,
500 .subTexelPrecisionBits = 4 /* FIXME */,
501 .mipmapPrecisionBits = 4 /* FIXME */,
502 .maxDrawIndexedIndexValue = UINT32_MAX,
503 .maxDrawIndirectCount = UINT32_MAX,
504 .maxSamplerLodBias = 16,
505 .maxSamplerAnisotropy = 16,
506 .maxViewports = MAX_VIEWPORTS,
507 .maxViewportDimensions = { (1 << 14), (1 << 14) },
508 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
509 .viewportSubPixelBits = 13, /* We take a float? */
510 .minMemoryMapAlignment = 4096, /* A page */
511 .minTexelBufferOffsetAlignment = 1,
512 .minUniformBufferOffsetAlignment = 4,
513 .minStorageBufferOffsetAlignment = 4,
514 .minTexelOffset = -32,
515 .maxTexelOffset = 31,
516 .minTexelGatherOffset = -32,
517 .maxTexelGatherOffset = 31,
518 .minInterpolationOffset = -2,
519 .maxInterpolationOffset = 2,
520 .subPixelInterpolationOffsetBits = 8,
521 .maxFramebufferWidth = (1 << 14),
522 .maxFramebufferHeight = (1 << 14),
523 .maxFramebufferLayers = (1 << 10),
524 .framebufferColorSampleCounts = sample_counts,
525 .framebufferDepthSampleCounts = sample_counts,
526 .framebufferStencilSampleCounts = sample_counts,
527 .framebufferNoAttachmentsSampleCounts = sample_counts,
528 .maxColorAttachments = MAX_RTS,
529 .sampledImageColorSampleCounts = sample_counts,
530 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
531 .sampledImageDepthSampleCounts = sample_counts,
532 .sampledImageStencilSampleCounts = sample_counts,
533 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
534 .maxSampleMaskWords = 1,
535 .timestampComputeAndGraphics = false,
536 .timestampPeriod = 100000.0 / pdevice->rad_info.clock_crystal_freq,
537 .maxClipDistances = 8,
538 .maxCullDistances = 8,
539 .maxCombinedClipAndCullDistances = 8,
540 .discreteQueuePriorities = 1,
541 .pointSizeRange = { 0.125, 255.875 },
542 .lineWidthRange = { 0.0, 7.9921875 },
543 .pointSizeGranularity = (1.0 / 8.0),
544 .lineWidthGranularity = (1.0 / 128.0),
545 .strictLines = false, /* FINISHME */
546 .standardSampleLocations = true,
547 .optimalBufferCopyOffsetAlignment = 128,
548 .optimalBufferCopyRowPitchAlignment = 128,
549 .nonCoherentAtomSize = 64,
550 };
551
552 *pProperties = (VkPhysicalDeviceProperties) {
553 .apiVersion = VK_MAKE_VERSION(1, 0, 5),
554 .driverVersion = 1,
555 .vendorID = 0x1002,
556 .deviceID = pdevice->rad_info.pci_id,
557 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
558 .limits = limits,
559 .sparseProperties = {0}, /* Broadwell doesn't do sparse. */
560 };
561
562 strcpy(pProperties->deviceName, pdevice->name);
563 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
564 }
565
566 void radv_GetPhysicalDeviceQueueFamilyProperties(
567 VkPhysicalDevice physicalDevice,
568 uint32_t* pCount,
569 VkQueueFamilyProperties* pQueueFamilyProperties)
570 {
571 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
572 int num_queue_families = 1;
573 int idx;
574 if (pdevice->rad_info.compute_rings > 0 &&
575 pdevice->rad_info.chip_class >= CIK &&
576 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
577 num_queue_families++;
578
579 if (pQueueFamilyProperties == NULL) {
580 *pCount = num_queue_families;
581 return;
582 }
583
584 if (!*pCount)
585 return;
586
587 idx = 0;
588 if (*pCount >= 1) {
589 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
590 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
591 VK_QUEUE_COMPUTE_BIT |
592 VK_QUEUE_TRANSFER_BIT,
593 .queueCount = 1,
594 .timestampValidBits = 64,
595 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
596 };
597 idx++;
598 }
599
600 if (pdevice->rad_info.compute_rings > 0 &&
601 pdevice->rad_info.chip_class >= CIK &&
602 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
603 if (*pCount > idx) {
604 pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
605 .queueFlags = VK_QUEUE_COMPUTE_BIT | VK_QUEUE_TRANSFER_BIT,
606 .queueCount = pdevice->rad_info.compute_rings,
607 .timestampValidBits = 64,
608 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
609 };
610 idx++;
611 }
612 }
613 *pCount = idx;
614 }
615
616 void radv_GetPhysicalDeviceMemoryProperties(
617 VkPhysicalDevice physicalDevice,
618 VkPhysicalDeviceMemoryProperties* pMemoryProperties)
619 {
620 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
621
622 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
623
624 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
625 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
626 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
627 .heapIndex = RADV_MEM_HEAP_VRAM,
628 };
629 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
630 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
631 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
632 .heapIndex = RADV_MEM_HEAP_GTT,
633 };
634 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
635 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
636 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
637 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
638 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
639 };
640 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
641 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
642 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
643 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
644 .heapIndex = RADV_MEM_HEAP_GTT,
645 };
646
647 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
648
649 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
650 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
651 .size = physical_device->rad_info.vram_size -
652 physical_device->rad_info.visible_vram_size,
653 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
654 };
655 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
656 .size = physical_device->rad_info.visible_vram_size,
657 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
658 };
659 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
660 .size = physical_device->rad_info.gart_size,
661 .flags = 0,
662 };
663 }
664
665 static void
666 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
667 int queue_family_index, int idx)
668 {
669 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
670 queue->device = device;
671 queue->queue_family_index = queue_family_index;
672 queue->queue_idx = idx;
673 }
674
675 static void
676 radv_queue_finish(struct radv_queue *queue)
677 {
678 }
679
680 VkResult radv_CreateDevice(
681 VkPhysicalDevice physicalDevice,
682 const VkDeviceCreateInfo* pCreateInfo,
683 const VkAllocationCallbacks* pAllocator,
684 VkDevice* pDevice)
685 {
686 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
687 VkResult result;
688 struct radv_device *device;
689
690 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
691 bool found = false;
692 for (uint32_t j = 0; j < ARRAY_SIZE(device_extensions); j++) {
693 if (strcmp(pCreateInfo->ppEnabledExtensionNames[i],
694 device_extensions[j].extensionName) == 0) {
695 found = true;
696 break;
697 }
698 }
699 if (!found)
700 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
701 }
702
703 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
704 sizeof(*device), 8,
705 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
706 if (!device)
707 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
708
709 memset(device, 0, sizeof(*device));
710
711 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
712 device->instance = physical_device->instance;
713
714 device->debug_flags = device->instance->debug_flags;
715
716 device->ws = physical_device->ws;
717 if (pAllocator)
718 device->alloc = *pAllocator;
719 else
720 device->alloc = physical_device->instance->alloc;
721
722 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
723 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
724 uint32_t qfi = queue_create->queueFamilyIndex;
725
726 device->queues[qfi] = vk_alloc(&device->alloc,
727 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
728 if (!device->queues[qfi]) {
729 result = VK_ERROR_OUT_OF_HOST_MEMORY;
730 goto fail;
731 }
732
733 device->queue_count[qfi] = queue_create->queueCount;
734
735 for (unsigned q = 0; q < queue_create->queueCount; q++)
736 radv_queue_init(device, &device->queues[qfi][q], qfi, q);
737 }
738
739 device->hw_ctx = device->ws->ctx_create(device->ws);
740 if (!device->hw_ctx) {
741 result = VK_ERROR_OUT_OF_HOST_MEMORY;
742 goto fail;
743 }
744
745 result = radv_device_init_meta(device);
746 if (result != VK_SUCCESS) {
747 device->ws->ctx_destroy(device->hw_ctx);
748 goto fail;
749 }
750
751 radv_device_init_msaa(device);
752
753 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
754 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
755 switch (family) {
756 case RADV_QUEUE_GENERAL:
757 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
758 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
759 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
760 break;
761 case RADV_QUEUE_COMPUTE:
762 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
763 radeon_emit(device->empty_cs[family], 0);
764 break;
765 }
766 device->ws->cs_finalize(device->empty_cs[family]);
767 }
768
769 if (getenv("RADV_TRACE_FILE")) {
770 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
771 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
772 if (!device->trace_bo)
773 goto fail;
774
775 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
776 if (!device->trace_id_ptr)
777 goto fail;
778 }
779
780 *pDevice = radv_device_to_handle(device);
781 return VK_SUCCESS;
782
783 fail:
784 if (device->trace_bo)
785 device->ws->buffer_destroy(device->trace_bo);
786
787 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
788 for (unsigned q = 0; q < device->queue_count[i]; q++)
789 radv_queue_finish(&device->queues[i][q]);
790 if (device->queue_count[i])
791 vk_free(&device->alloc, device->queues[i]);
792 }
793
794 if (device->hw_ctx)
795 device->ws->ctx_destroy(device->hw_ctx);
796
797 vk_free(&device->alloc, device);
798 return result;
799 }
800
801 void radv_DestroyDevice(
802 VkDevice _device,
803 const VkAllocationCallbacks* pAllocator)
804 {
805 RADV_FROM_HANDLE(radv_device, device, _device);
806
807 if (device->trace_bo)
808 device->ws->buffer_destroy(device->trace_bo);
809
810 device->ws->ctx_destroy(device->hw_ctx);
811 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
812 for (unsigned q = 0; q < device->queue_count[i]; q++)
813 radv_queue_finish(&device->queues[i][q]);
814 if (device->queue_count[i])
815 vk_free(&device->alloc, device->queues[i]);
816 }
817 radv_device_finish_meta(device);
818
819 vk_free(&device->alloc, device);
820 }
821
822 VkResult radv_EnumerateInstanceExtensionProperties(
823 const char* pLayerName,
824 uint32_t* pPropertyCount,
825 VkExtensionProperties* pProperties)
826 {
827 if (pProperties == NULL) {
828 *pPropertyCount = ARRAY_SIZE(global_extensions);
829 return VK_SUCCESS;
830 }
831
832 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(global_extensions));
833 typed_memcpy(pProperties, global_extensions, *pPropertyCount);
834
835 if (*pPropertyCount < ARRAY_SIZE(global_extensions))
836 return VK_INCOMPLETE;
837
838 return VK_SUCCESS;
839 }
840
841 VkResult radv_EnumerateDeviceExtensionProperties(
842 VkPhysicalDevice physicalDevice,
843 const char* pLayerName,
844 uint32_t* pPropertyCount,
845 VkExtensionProperties* pProperties)
846 {
847 if (pProperties == NULL) {
848 *pPropertyCount = ARRAY_SIZE(device_extensions);
849 return VK_SUCCESS;
850 }
851
852 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(device_extensions));
853 typed_memcpy(pProperties, device_extensions, *pPropertyCount);
854
855 if (*pPropertyCount < ARRAY_SIZE(device_extensions))
856 return VK_INCOMPLETE;
857
858 return VK_SUCCESS;
859 }
860
861 VkResult radv_EnumerateInstanceLayerProperties(
862 uint32_t* pPropertyCount,
863 VkLayerProperties* pProperties)
864 {
865 if (pProperties == NULL) {
866 *pPropertyCount = 0;
867 return VK_SUCCESS;
868 }
869
870 /* None supported at this time */
871 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
872 }
873
874 VkResult radv_EnumerateDeviceLayerProperties(
875 VkPhysicalDevice physicalDevice,
876 uint32_t* pPropertyCount,
877 VkLayerProperties* pProperties)
878 {
879 if (pProperties == NULL) {
880 *pPropertyCount = 0;
881 return VK_SUCCESS;
882 }
883
884 /* None supported at this time */
885 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
886 }
887
888 void radv_GetDeviceQueue(
889 VkDevice _device,
890 uint32_t queueFamilyIndex,
891 uint32_t queueIndex,
892 VkQueue* pQueue)
893 {
894 RADV_FROM_HANDLE(radv_device, device, _device);
895
896 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
897 }
898
899 static void radv_dump_trace(struct radv_device *device,
900 struct radeon_winsys_cs *cs)
901 {
902 const char *filename = getenv("RADV_TRACE_FILE");
903 FILE *f = fopen(filename, "w");
904 if (!f) {
905 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
906 return;
907 }
908
909 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
910 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
911 fclose(f);
912 }
913
914 VkResult radv_QueueSubmit(
915 VkQueue _queue,
916 uint32_t submitCount,
917 const VkSubmitInfo* pSubmits,
918 VkFence _fence)
919 {
920 RADV_FROM_HANDLE(radv_queue, queue, _queue);
921 RADV_FROM_HANDLE(radv_fence, fence, _fence);
922 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
923 struct radeon_winsys_ctx *ctx = queue->device->hw_ctx;
924 int ret;
925 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
926
927 for (uint32_t i = 0; i < submitCount; i++) {
928 struct radeon_winsys_cs **cs_array;
929 bool can_patch = true;
930 uint32_t advance;
931
932 if (!pSubmits[i].commandBufferCount)
933 continue;
934
935 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
936 pSubmits[i].commandBufferCount);
937
938 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
939 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
940 pSubmits[i].pCommandBuffers[j]);
941 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
942
943 cs_array[j] = cmd_buffer->cs;
944 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
945 can_patch = false;
946 }
947
948 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
949 advance = MIN2(max_cs_submission,
950 pSubmits[i].commandBufferCount - j);
951 bool b = j == 0;
952 bool e = j + advance == pSubmits[i].commandBufferCount;
953
954 if (queue->device->trace_bo)
955 *queue->device->trace_id_ptr = 0;
956
957 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array,
958 pSubmits[i].commandBufferCount,
959 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
960 b ? pSubmits[i].waitSemaphoreCount : 0,
961 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
962 e ? pSubmits[i].signalSemaphoreCount : 0,
963 can_patch, base_fence);
964
965 if (ret) {
966 radv_loge("failed to submit CS %d\n", i);
967 abort();
968 }
969 if (queue->device->trace_bo) {
970 bool success = queue->device->ws->ctx_wait_idle(
971 queue->device->hw_ctx,
972 radv_queue_family_to_ring(
973 queue->queue_family_index),
974 queue->queue_idx);
975
976 if (!success) { /* Hang */
977 radv_dump_trace(queue->device, cs_array[j]);
978 abort();
979 }
980 }
981 }
982 free(cs_array);
983 }
984
985 if (fence) {
986 if (!submitCount)
987 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
988 &queue->device->empty_cs[queue->queue_family_index],
989 1, NULL, 0, NULL, 0, false, base_fence);
990
991 fence->submitted = true;
992 }
993
994 return VK_SUCCESS;
995 }
996
997 VkResult radv_QueueWaitIdle(
998 VkQueue _queue)
999 {
1000 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1001
1002 queue->device->ws->ctx_wait_idle(queue->device->hw_ctx,
1003 radv_queue_family_to_ring(queue->queue_family_index),
1004 queue->queue_idx);
1005 return VK_SUCCESS;
1006 }
1007
1008 VkResult radv_DeviceWaitIdle(
1009 VkDevice _device)
1010 {
1011 RADV_FROM_HANDLE(radv_device, device, _device);
1012
1013 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1014 for (unsigned q = 0; q < device->queue_count[i]; q++) {
1015 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
1016 }
1017 }
1018 return VK_SUCCESS;
1019 }
1020
1021 PFN_vkVoidFunction radv_GetInstanceProcAddr(
1022 VkInstance instance,
1023 const char* pName)
1024 {
1025 return radv_lookup_entrypoint(pName);
1026 }
1027
1028 /* The loader wants us to expose a second GetInstanceProcAddr function
1029 * to work around certain LD_PRELOAD issues seen in apps.
1030 */
1031 PUBLIC
1032 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1033 VkInstance instance,
1034 const char* pName);
1035
1036 PUBLIC
1037 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
1038 VkInstance instance,
1039 const char* pName)
1040 {
1041 return radv_GetInstanceProcAddr(instance, pName);
1042 }
1043
1044 PFN_vkVoidFunction radv_GetDeviceProcAddr(
1045 VkDevice device,
1046 const char* pName)
1047 {
1048 return radv_lookup_entrypoint(pName);
1049 }
1050
1051 VkResult radv_AllocateMemory(
1052 VkDevice _device,
1053 const VkMemoryAllocateInfo* pAllocateInfo,
1054 const VkAllocationCallbacks* pAllocator,
1055 VkDeviceMemory* pMem)
1056 {
1057 RADV_FROM_HANDLE(radv_device, device, _device);
1058 struct radv_device_memory *mem;
1059 VkResult result;
1060 enum radeon_bo_domain domain;
1061 uint32_t flags = 0;
1062 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
1063
1064 if (pAllocateInfo->allocationSize == 0) {
1065 /* Apparently, this is allowed */
1066 *pMem = VK_NULL_HANDLE;
1067 return VK_SUCCESS;
1068 }
1069
1070 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
1071 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1072 if (mem == NULL)
1073 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1074
1075 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
1076 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
1077 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
1078 domain = RADEON_DOMAIN_GTT;
1079 else
1080 domain = RADEON_DOMAIN_VRAM;
1081
1082 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
1083 flags |= RADEON_FLAG_NO_CPU_ACCESS;
1084 else
1085 flags |= RADEON_FLAG_CPU_ACCESS;
1086
1087 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
1088 flags |= RADEON_FLAG_GTT_WC;
1089
1090 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 32768,
1091 domain, flags);
1092
1093 if (!mem->bo) {
1094 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
1095 goto fail;
1096 }
1097 mem->type_index = pAllocateInfo->memoryTypeIndex;
1098
1099 *pMem = radv_device_memory_to_handle(mem);
1100
1101 return VK_SUCCESS;
1102
1103 fail:
1104 vk_free2(&device->alloc, pAllocator, mem);
1105
1106 return result;
1107 }
1108
1109 void radv_FreeMemory(
1110 VkDevice _device,
1111 VkDeviceMemory _mem,
1112 const VkAllocationCallbacks* pAllocator)
1113 {
1114 RADV_FROM_HANDLE(radv_device, device, _device);
1115 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
1116
1117 if (mem == NULL)
1118 return;
1119
1120 device->ws->buffer_destroy(mem->bo);
1121 mem->bo = NULL;
1122
1123 vk_free2(&device->alloc, pAllocator, mem);
1124 }
1125
1126 VkResult radv_MapMemory(
1127 VkDevice _device,
1128 VkDeviceMemory _memory,
1129 VkDeviceSize offset,
1130 VkDeviceSize size,
1131 VkMemoryMapFlags flags,
1132 void** ppData)
1133 {
1134 RADV_FROM_HANDLE(radv_device, device, _device);
1135 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1136
1137 if (mem == NULL) {
1138 *ppData = NULL;
1139 return VK_SUCCESS;
1140 }
1141
1142 *ppData = device->ws->buffer_map(mem->bo);
1143 if (*ppData) {
1144 *ppData += offset;
1145 return VK_SUCCESS;
1146 }
1147
1148 return VK_ERROR_MEMORY_MAP_FAILED;
1149 }
1150
1151 void radv_UnmapMemory(
1152 VkDevice _device,
1153 VkDeviceMemory _memory)
1154 {
1155 RADV_FROM_HANDLE(radv_device, device, _device);
1156 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1157
1158 if (mem == NULL)
1159 return;
1160
1161 device->ws->buffer_unmap(mem->bo);
1162 }
1163
1164 VkResult radv_FlushMappedMemoryRanges(
1165 VkDevice _device,
1166 uint32_t memoryRangeCount,
1167 const VkMappedMemoryRange* pMemoryRanges)
1168 {
1169 return VK_SUCCESS;
1170 }
1171
1172 VkResult radv_InvalidateMappedMemoryRanges(
1173 VkDevice _device,
1174 uint32_t memoryRangeCount,
1175 const VkMappedMemoryRange* pMemoryRanges)
1176 {
1177 return VK_SUCCESS;
1178 }
1179
1180 void radv_GetBufferMemoryRequirements(
1181 VkDevice device,
1182 VkBuffer _buffer,
1183 VkMemoryRequirements* pMemoryRequirements)
1184 {
1185 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1186
1187 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1188
1189 pMemoryRequirements->size = buffer->size;
1190 pMemoryRequirements->alignment = 16;
1191 }
1192
1193 void radv_GetImageMemoryRequirements(
1194 VkDevice device,
1195 VkImage _image,
1196 VkMemoryRequirements* pMemoryRequirements)
1197 {
1198 RADV_FROM_HANDLE(radv_image, image, _image);
1199
1200 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
1201
1202 pMemoryRequirements->size = image->size;
1203 pMemoryRequirements->alignment = image->alignment;
1204 }
1205
1206 void radv_GetImageSparseMemoryRequirements(
1207 VkDevice device,
1208 VkImage image,
1209 uint32_t* pSparseMemoryRequirementCount,
1210 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
1211 {
1212 stub();
1213 }
1214
1215 void radv_GetDeviceMemoryCommitment(
1216 VkDevice device,
1217 VkDeviceMemory memory,
1218 VkDeviceSize* pCommittedMemoryInBytes)
1219 {
1220 *pCommittedMemoryInBytes = 0;
1221 }
1222
1223 VkResult radv_BindBufferMemory(
1224 VkDevice device,
1225 VkBuffer _buffer,
1226 VkDeviceMemory _memory,
1227 VkDeviceSize memoryOffset)
1228 {
1229 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1230 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1231
1232 if (mem) {
1233 buffer->bo = mem->bo;
1234 buffer->offset = memoryOffset;
1235 } else {
1236 buffer->bo = NULL;
1237 buffer->offset = 0;
1238 }
1239
1240 return VK_SUCCESS;
1241 }
1242
1243 VkResult radv_BindImageMemory(
1244 VkDevice device,
1245 VkImage _image,
1246 VkDeviceMemory _memory,
1247 VkDeviceSize memoryOffset)
1248 {
1249 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
1250 RADV_FROM_HANDLE(radv_image, image, _image);
1251
1252 if (mem) {
1253 image->bo = mem->bo;
1254 image->offset = memoryOffset;
1255 } else {
1256 image->bo = NULL;
1257 image->offset = 0;
1258 }
1259
1260 return VK_SUCCESS;
1261 }
1262
1263 VkResult radv_QueueBindSparse(
1264 VkQueue queue,
1265 uint32_t bindInfoCount,
1266 const VkBindSparseInfo* pBindInfo,
1267 VkFence fence)
1268 {
1269 stub_return(VK_ERROR_INCOMPATIBLE_DRIVER);
1270 }
1271
1272 VkResult radv_CreateFence(
1273 VkDevice _device,
1274 const VkFenceCreateInfo* pCreateInfo,
1275 const VkAllocationCallbacks* pAllocator,
1276 VkFence* pFence)
1277 {
1278 RADV_FROM_HANDLE(radv_device, device, _device);
1279 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
1280 sizeof(*fence), 8,
1281 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1282
1283 if (!fence)
1284 return VK_ERROR_OUT_OF_HOST_MEMORY;
1285
1286 memset(fence, 0, sizeof(*fence));
1287 fence->submitted = false;
1288 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
1289 fence->fence = device->ws->create_fence();
1290 if (!fence->fence) {
1291 vk_free2(&device->alloc, pAllocator, fence);
1292 return VK_ERROR_OUT_OF_HOST_MEMORY;
1293 }
1294
1295 *pFence = radv_fence_to_handle(fence);
1296
1297 return VK_SUCCESS;
1298 }
1299
1300 void radv_DestroyFence(
1301 VkDevice _device,
1302 VkFence _fence,
1303 const VkAllocationCallbacks* pAllocator)
1304 {
1305 RADV_FROM_HANDLE(radv_device, device, _device);
1306 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1307
1308 if (!fence)
1309 return;
1310 device->ws->destroy_fence(fence->fence);
1311 vk_free2(&device->alloc, pAllocator, fence);
1312 }
1313
1314 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
1315 {
1316 uint64_t current_time;
1317 struct timespec tv;
1318
1319 clock_gettime(CLOCK_MONOTONIC, &tv);
1320 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
1321
1322 timeout = MIN2(UINT64_MAX - current_time, timeout);
1323
1324 return current_time + timeout;
1325 }
1326
1327 VkResult radv_WaitForFences(
1328 VkDevice _device,
1329 uint32_t fenceCount,
1330 const VkFence* pFences,
1331 VkBool32 waitAll,
1332 uint64_t timeout)
1333 {
1334 RADV_FROM_HANDLE(radv_device, device, _device);
1335 timeout = radv_get_absolute_timeout(timeout);
1336
1337 if (!waitAll && fenceCount > 1) {
1338 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
1339 }
1340
1341 for (uint32_t i = 0; i < fenceCount; ++i) {
1342 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1343 bool expired = false;
1344
1345 if (fence->signalled)
1346 continue;
1347
1348 if (!fence->submitted)
1349 return VK_TIMEOUT;
1350
1351 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
1352 if (!expired)
1353 return VK_TIMEOUT;
1354
1355 fence->signalled = true;
1356 }
1357
1358 return VK_SUCCESS;
1359 }
1360
1361 VkResult radv_ResetFences(VkDevice device,
1362 uint32_t fenceCount,
1363 const VkFence *pFences)
1364 {
1365 for (unsigned i = 0; i < fenceCount; ++i) {
1366 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
1367 fence->submitted = fence->signalled = false;
1368 }
1369
1370 return VK_SUCCESS;
1371 }
1372
1373 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
1374 {
1375 RADV_FROM_HANDLE(radv_device, device, _device);
1376 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1377
1378 if (fence->signalled)
1379 return VK_SUCCESS;
1380 if (!fence->submitted)
1381 return VK_NOT_READY;
1382
1383 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
1384 return VK_NOT_READY;
1385
1386 return VK_SUCCESS;
1387 }
1388
1389
1390 // Queue semaphore functions
1391
1392 VkResult radv_CreateSemaphore(
1393 VkDevice _device,
1394 const VkSemaphoreCreateInfo* pCreateInfo,
1395 const VkAllocationCallbacks* pAllocator,
1396 VkSemaphore* pSemaphore)
1397 {
1398 RADV_FROM_HANDLE(radv_device, device, _device);
1399 struct radeon_winsys_sem *sem;
1400
1401 sem = device->ws->create_sem(device->ws);
1402 if (!sem)
1403 return VK_ERROR_OUT_OF_HOST_MEMORY;
1404
1405 *pSemaphore = (VkSemaphore)sem;
1406 return VK_SUCCESS;
1407 }
1408
1409 void radv_DestroySemaphore(
1410 VkDevice _device,
1411 VkSemaphore _semaphore,
1412 const VkAllocationCallbacks* pAllocator)
1413 {
1414 RADV_FROM_HANDLE(radv_device, device, _device);
1415 struct radeon_winsys_sem *sem;
1416 if (!_semaphore)
1417 return;
1418
1419 sem = (struct radeon_winsys_sem *)_semaphore;
1420 device->ws->destroy_sem(sem);
1421 }
1422
1423 VkResult radv_CreateEvent(
1424 VkDevice _device,
1425 const VkEventCreateInfo* pCreateInfo,
1426 const VkAllocationCallbacks* pAllocator,
1427 VkEvent* pEvent)
1428 {
1429 RADV_FROM_HANDLE(radv_device, device, _device);
1430 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
1431 sizeof(*event), 8,
1432 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1433
1434 if (!event)
1435 return VK_ERROR_OUT_OF_HOST_MEMORY;
1436
1437 event->bo = device->ws->buffer_create(device->ws, 8, 8,
1438 RADEON_DOMAIN_GTT,
1439 RADEON_FLAG_CPU_ACCESS);
1440 if (!event->bo) {
1441 vk_free2(&device->alloc, pAllocator, event);
1442 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1443 }
1444
1445 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
1446
1447 *pEvent = radv_event_to_handle(event);
1448
1449 return VK_SUCCESS;
1450 }
1451
1452 void radv_DestroyEvent(
1453 VkDevice _device,
1454 VkEvent _event,
1455 const VkAllocationCallbacks* pAllocator)
1456 {
1457 RADV_FROM_HANDLE(radv_device, device, _device);
1458 RADV_FROM_HANDLE(radv_event, event, _event);
1459
1460 if (!event)
1461 return;
1462 device->ws->buffer_destroy(event->bo);
1463 vk_free2(&device->alloc, pAllocator, event);
1464 }
1465
1466 VkResult radv_GetEventStatus(
1467 VkDevice _device,
1468 VkEvent _event)
1469 {
1470 RADV_FROM_HANDLE(radv_event, event, _event);
1471
1472 if (*event->map == 1)
1473 return VK_EVENT_SET;
1474 return VK_EVENT_RESET;
1475 }
1476
1477 VkResult radv_SetEvent(
1478 VkDevice _device,
1479 VkEvent _event)
1480 {
1481 RADV_FROM_HANDLE(radv_event, event, _event);
1482 *event->map = 1;
1483
1484 return VK_SUCCESS;
1485 }
1486
1487 VkResult radv_ResetEvent(
1488 VkDevice _device,
1489 VkEvent _event)
1490 {
1491 RADV_FROM_HANDLE(radv_event, event, _event);
1492 *event->map = 0;
1493
1494 return VK_SUCCESS;
1495 }
1496
1497 VkResult radv_CreateBuffer(
1498 VkDevice _device,
1499 const VkBufferCreateInfo* pCreateInfo,
1500 const VkAllocationCallbacks* pAllocator,
1501 VkBuffer* pBuffer)
1502 {
1503 RADV_FROM_HANDLE(radv_device, device, _device);
1504 struct radv_buffer *buffer;
1505
1506 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
1507
1508 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
1509 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1510 if (buffer == NULL)
1511 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1512
1513 buffer->size = pCreateInfo->size;
1514 buffer->usage = pCreateInfo->usage;
1515 buffer->bo = NULL;
1516 buffer->offset = 0;
1517
1518 *pBuffer = radv_buffer_to_handle(buffer);
1519
1520 return VK_SUCCESS;
1521 }
1522
1523 void radv_DestroyBuffer(
1524 VkDevice _device,
1525 VkBuffer _buffer,
1526 const VkAllocationCallbacks* pAllocator)
1527 {
1528 RADV_FROM_HANDLE(radv_device, device, _device);
1529 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
1530
1531 if (!buffer)
1532 return;
1533
1534 vk_free2(&device->alloc, pAllocator, buffer);
1535 }
1536
1537 static inline unsigned
1538 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
1539 {
1540 if (stencil)
1541 return image->surface.stencil_tiling_index[level];
1542 else
1543 return image->surface.tiling_index[level];
1544 }
1545
1546 static void
1547 radv_initialise_color_surface(struct radv_device *device,
1548 struct radv_color_buffer_info *cb,
1549 struct radv_image_view *iview)
1550 {
1551 const struct vk_format_description *desc;
1552 unsigned ntype, format, swap, endian;
1553 unsigned blend_clamp = 0, blend_bypass = 0;
1554 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
1555 uint64_t va;
1556 const struct radeon_surf *surf = &iview->image->surface;
1557 const struct radeon_surf_level *level_info = &surf->level[iview->base_mip];
1558
1559 desc = vk_format_description(iview->vk_format);
1560
1561 memset(cb, 0, sizeof(*cb));
1562
1563 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1564 va += level_info->offset;
1565 cb->cb_color_base = va >> 8;
1566
1567 /* CMASK variables */
1568 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1569 va += iview->image->cmask.offset;
1570 cb->cb_color_cmask = va >> 8;
1571 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
1572
1573 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1574 va += iview->image->dcc_offset;
1575 cb->cb_dcc_base = va >> 8;
1576
1577 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
1578 S_028C6C_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1579
1580 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
1581 pitch_tile_max = level_info->nblk_x / 8 - 1;
1582 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
1583 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
1584
1585 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
1586 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
1587
1588 /* Intensity is implemented as Red, so treat it that way. */
1589 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1) |
1590 S_028C74_TILE_MODE_INDEX(tile_mode_index);
1591
1592 if (iview->image->samples > 1) {
1593 unsigned log_samples = util_logbase2(iview->image->samples);
1594
1595 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
1596 S_028C74_NUM_FRAGMENTS(log_samples);
1597 }
1598
1599 if (iview->image->fmask.size) {
1600 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
1601 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1602 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
1603 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
1604 cb->cb_color_fmask = va >> 8;
1605 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
1606 } else {
1607 /* This must be set for fast clear to work without FMASK. */
1608 if (device->instance->physicalDevice.rad_info.chip_class >= CIK)
1609 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
1610 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
1611 cb->cb_color_fmask = cb->cb_color_base;
1612 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
1613 }
1614
1615 ntype = radv_translate_color_numformat(iview->vk_format,
1616 desc,
1617 vk_format_get_first_non_void_channel(iview->vk_format));
1618 format = radv_translate_colorformat(iview->vk_format);
1619 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
1620 radv_finishme("Illegal color\n");
1621 swap = radv_translate_colorswap(iview->vk_format, FALSE);
1622 endian = radv_colorformat_endian_swap(format);
1623
1624 /* blend clamp should be set for all NORM/SRGB types */
1625 if (ntype == V_028C70_NUMBER_UNORM ||
1626 ntype == V_028C70_NUMBER_SNORM ||
1627 ntype == V_028C70_NUMBER_SRGB)
1628 blend_clamp = 1;
1629
1630 /* set blend bypass according to docs if SINT/UINT or
1631 8/24 COLOR variants */
1632 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
1633 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
1634 format == V_028C70_COLOR_X24_8_32_FLOAT) {
1635 blend_clamp = 0;
1636 blend_bypass = 1;
1637 }
1638 #if 0
1639 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
1640 (format == V_028C70_COLOR_8 ||
1641 format == V_028C70_COLOR_8_8 ||
1642 format == V_028C70_COLOR_8_8_8_8))
1643 ->color_is_int8 = true;
1644 #endif
1645 cb->cb_color_info = S_028C70_FORMAT(format) |
1646 S_028C70_COMP_SWAP(swap) |
1647 S_028C70_BLEND_CLAMP(blend_clamp) |
1648 S_028C70_BLEND_BYPASS(blend_bypass) |
1649 S_028C70_SIMPLE_FLOAT(1) |
1650 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
1651 ntype != V_028C70_NUMBER_SNORM &&
1652 ntype != V_028C70_NUMBER_SRGB &&
1653 format != V_028C70_COLOR_8_24 &&
1654 format != V_028C70_COLOR_24_8) |
1655 S_028C70_NUMBER_TYPE(ntype) |
1656 S_028C70_ENDIAN(endian);
1657 if (iview->image->samples > 1)
1658 if (iview->image->fmask.size)
1659 cb->cb_color_info |= S_028C70_COMPRESSION(1);
1660
1661 if (iview->image->cmask.size &&
1662 (device->debug_flags & RADV_DEBUG_FAST_CLEARS))
1663 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
1664
1665 if (iview->image->surface.dcc_size && level_info->dcc_enabled)
1666 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
1667
1668 if (device->instance->physicalDevice.rad_info.chip_class >= VI) {
1669 unsigned max_uncompressed_block_size = 2;
1670 if (iview->image->samples > 1) {
1671 if (iview->image->surface.bpe == 1)
1672 max_uncompressed_block_size = 0;
1673 else if (iview->image->surface.bpe == 2)
1674 max_uncompressed_block_size = 1;
1675 }
1676
1677 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
1678 S_028C78_INDEPENDENT_64B_BLOCKS(1);
1679 }
1680
1681 /* This must be set for fast clear to work without FMASK. */
1682 if (!iview->image->fmask.size &&
1683 device->instance->physicalDevice.rad_info.chip_class == SI) {
1684 unsigned bankh = util_logbase2(iview->image->surface.bankh);
1685 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
1686 }
1687 }
1688
1689 static void
1690 radv_initialise_ds_surface(struct radv_device *device,
1691 struct radv_ds_buffer_info *ds,
1692 struct radv_image_view *iview)
1693 {
1694 unsigned level = iview->base_mip;
1695 unsigned format;
1696 uint64_t va, s_offs, z_offs;
1697 const struct radeon_surf_level *level_info = &iview->image->surface.level[level];
1698 memset(ds, 0, sizeof(*ds));
1699 switch (iview->vk_format) {
1700 case VK_FORMAT_D24_UNORM_S8_UINT:
1701 case VK_FORMAT_X8_D24_UNORM_PACK32:
1702 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
1703 ds->offset_scale = 2.0f;
1704 break;
1705 case VK_FORMAT_D16_UNORM:
1706 case VK_FORMAT_D16_UNORM_S8_UINT:
1707 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
1708 ds->offset_scale = 4.0f;
1709 break;
1710 case VK_FORMAT_D32_SFLOAT:
1711 case VK_FORMAT_D32_SFLOAT_S8_UINT:
1712 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
1713 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
1714 ds->offset_scale = 1.0f;
1715 break;
1716 default:
1717 break;
1718 }
1719
1720 format = radv_translate_dbformat(iview->vk_format);
1721 if (format == V_028040_Z_INVALID) {
1722 fprintf(stderr, "Invalid DB format: %d, disabling DB.\n", iview->vk_format);
1723 }
1724
1725 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
1726 s_offs = z_offs = va;
1727 z_offs += iview->image->surface.level[level].offset;
1728 s_offs += iview->image->surface.stencil_level[level].offset;
1729
1730 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
1731 S_028008_SLICE_MAX(iview->base_layer + iview->extent.depth - 1);
1732 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
1733 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
1734
1735 if (iview->image->samples > 1)
1736 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->samples));
1737
1738 if (iview->image->surface.flags & RADEON_SURF_SBUFFER)
1739 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_8);
1740 else
1741 ds->db_stencil_info = S_028044_FORMAT(V_028044_STENCIL_INVALID);
1742
1743 if (device->instance->physicalDevice.rad_info.chip_class >= CIK) {
1744 struct radeon_info *info = &device->instance->physicalDevice.rad_info;
1745 unsigned tiling_index = iview->image->surface.tiling_index[level];
1746 unsigned stencil_index = iview->image->surface.stencil_tiling_index[level];
1747 unsigned macro_index = iview->image->surface.macro_tile_index;
1748 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
1749 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
1750 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
1751
1752 ds->db_depth_info |=
1753 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
1754 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
1755 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
1756 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
1757 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
1758 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
1759 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
1760 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
1761 } else {
1762 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
1763 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
1764 tile_mode_index = si_tile_mode_index(iview->image, level, true);
1765 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
1766 }
1767
1768 if (iview->image->htile.size && !level) {
1769 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1) |
1770 S_028040_ALLOW_EXPCLEAR(1);
1771
1772 if (iview->image->surface.flags & RADEON_SURF_SBUFFER) {
1773 /* Workaround: For a not yet understood reason, the
1774 * combination of MSAA, fast stencil clear and stencil
1775 * decompress messes with subsequent stencil buffer
1776 * uses. Problem was reproduced on Verde, Bonaire,
1777 * Tonga, and Carrizo.
1778 *
1779 * Disabling EXPCLEAR works around the problem.
1780 *
1781 * Check piglit's arb_texture_multisample-stencil-clear
1782 * test if you want to try changing this.
1783 */
1784 if (iview->image->samples <= 1)
1785 ds->db_stencil_info |= S_028044_ALLOW_EXPCLEAR(1);
1786 } else
1787 /* Use all of the htile_buffer for depth if there's no stencil. */
1788 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
1789
1790 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
1791 iview->image->htile.offset;
1792 ds->db_htile_data_base = va >> 8;
1793 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
1794 } else {
1795 ds->db_htile_data_base = 0;
1796 ds->db_htile_surface = 0;
1797 }
1798
1799 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
1800 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
1801
1802 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
1803 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
1804 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
1805 }
1806
1807 VkResult radv_CreateFramebuffer(
1808 VkDevice _device,
1809 const VkFramebufferCreateInfo* pCreateInfo,
1810 const VkAllocationCallbacks* pAllocator,
1811 VkFramebuffer* pFramebuffer)
1812 {
1813 RADV_FROM_HANDLE(radv_device, device, _device);
1814 struct radv_framebuffer *framebuffer;
1815
1816 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
1817
1818 size_t size = sizeof(*framebuffer) +
1819 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
1820 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
1821 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1822 if (framebuffer == NULL)
1823 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1824
1825 framebuffer->attachment_count = pCreateInfo->attachmentCount;
1826 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
1827 VkImageView _iview = pCreateInfo->pAttachments[i];
1828 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
1829 framebuffer->attachments[i].attachment = iview;
1830 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
1831 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
1832 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
1833 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
1834 }
1835 }
1836
1837 framebuffer->width = pCreateInfo->width;
1838 framebuffer->height = pCreateInfo->height;
1839 framebuffer->layers = pCreateInfo->layers;
1840
1841 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
1842 return VK_SUCCESS;
1843 }
1844
1845 void radv_DestroyFramebuffer(
1846 VkDevice _device,
1847 VkFramebuffer _fb,
1848 const VkAllocationCallbacks* pAllocator)
1849 {
1850 RADV_FROM_HANDLE(radv_device, device, _device);
1851 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
1852
1853 if (!fb)
1854 return;
1855 vk_free2(&device->alloc, pAllocator, fb);
1856 }
1857
1858 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
1859 {
1860 switch (address_mode) {
1861 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
1862 return V_008F30_SQ_TEX_WRAP;
1863 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
1864 return V_008F30_SQ_TEX_MIRROR;
1865 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
1866 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
1867 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
1868 return V_008F30_SQ_TEX_CLAMP_BORDER;
1869 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
1870 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
1871 default:
1872 unreachable("illegal tex wrap mode");
1873 break;
1874 }
1875 }
1876
1877 static unsigned
1878 radv_tex_compare(VkCompareOp op)
1879 {
1880 switch (op) {
1881 case VK_COMPARE_OP_NEVER:
1882 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
1883 case VK_COMPARE_OP_LESS:
1884 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
1885 case VK_COMPARE_OP_EQUAL:
1886 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
1887 case VK_COMPARE_OP_LESS_OR_EQUAL:
1888 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
1889 case VK_COMPARE_OP_GREATER:
1890 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
1891 case VK_COMPARE_OP_NOT_EQUAL:
1892 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
1893 case VK_COMPARE_OP_GREATER_OR_EQUAL:
1894 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
1895 case VK_COMPARE_OP_ALWAYS:
1896 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
1897 default:
1898 unreachable("illegal compare mode");
1899 break;
1900 }
1901 }
1902
1903 static unsigned
1904 radv_tex_filter(VkFilter filter, unsigned max_ansio)
1905 {
1906 switch (filter) {
1907 case VK_FILTER_NEAREST:
1908 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
1909 V_008F38_SQ_TEX_XY_FILTER_POINT);
1910 case VK_FILTER_LINEAR:
1911 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
1912 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
1913 case VK_FILTER_CUBIC_IMG:
1914 default:
1915 fprintf(stderr, "illegal texture filter");
1916 return 0;
1917 }
1918 }
1919
1920 static unsigned
1921 radv_tex_mipfilter(VkSamplerMipmapMode mode)
1922 {
1923 switch (mode) {
1924 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
1925 return V_008F38_SQ_TEX_Z_FILTER_POINT;
1926 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
1927 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
1928 default:
1929 return V_008F38_SQ_TEX_Z_FILTER_NONE;
1930 }
1931 }
1932
1933 static unsigned
1934 radv_tex_bordercolor(VkBorderColor bcolor)
1935 {
1936 switch (bcolor) {
1937 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
1938 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
1939 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
1940 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
1941 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
1942 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
1943 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
1944 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
1945 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
1946 default:
1947 break;
1948 }
1949 return 0;
1950 }
1951
1952 static unsigned
1953 radv_tex_aniso_filter(unsigned filter)
1954 {
1955 if (filter < 2)
1956 return 0;
1957 if (filter < 4)
1958 return 1;
1959 if (filter < 8)
1960 return 2;
1961 if (filter < 16)
1962 return 3;
1963 return 4;
1964 }
1965
1966 static void
1967 radv_init_sampler(struct radv_device *device,
1968 struct radv_sampler *sampler,
1969 const VkSamplerCreateInfo *pCreateInfo)
1970 {
1971 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
1972 (uint32_t) pCreateInfo->maxAnisotropy : 0;
1973 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
1974 bool is_vi = (device->instance->physicalDevice.rad_info.chip_class >= VI);
1975
1976 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
1977 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
1978 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
1979 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
1980 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
1981 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
1982 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
1983 S_008F30_ANISO_BIAS(max_aniso_ratio) |
1984 S_008F30_DISABLE_CUBE_WRAP(0) |
1985 S_008F30_COMPAT_MODE(is_vi));
1986 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
1987 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
1988 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
1989 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
1990 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
1991 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
1992 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
1993 S_008F38_MIP_POINT_PRECLAMP(1) |
1994 S_008F38_DISABLE_LSB_CEIL(1) |
1995 S_008F38_FILTER_PREC_FIX(1) |
1996 S_008F38_ANISO_OVERRIDE(is_vi));
1997 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
1998 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
1999 }
2000
2001 VkResult radv_CreateSampler(
2002 VkDevice _device,
2003 const VkSamplerCreateInfo* pCreateInfo,
2004 const VkAllocationCallbacks* pAllocator,
2005 VkSampler* pSampler)
2006 {
2007 RADV_FROM_HANDLE(radv_device, device, _device);
2008 struct radv_sampler *sampler;
2009
2010 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
2011
2012 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
2013 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2014 if (!sampler)
2015 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2016
2017 radv_init_sampler(device, sampler, pCreateInfo);
2018 *pSampler = radv_sampler_to_handle(sampler);
2019
2020 return VK_SUCCESS;
2021 }
2022
2023 void radv_DestroySampler(
2024 VkDevice _device,
2025 VkSampler _sampler,
2026 const VkAllocationCallbacks* pAllocator)
2027 {
2028 RADV_FROM_HANDLE(radv_device, device, _device);
2029 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
2030
2031 if (!sampler)
2032 return;
2033 vk_free2(&device->alloc, pAllocator, sampler);
2034 }