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radv: Add support for more DCC compression with VK_KHR_image_format_list.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "amdgpu_id.h"
43 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
44 #include "ac_llvm_util.h"
45 #include "vk_format.h"
46 #include "sid.h"
47 #include "gfx9d.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static const VkExtensionProperties instance_extensions[] = {
80 {
81 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
82 .specVersion = 25,
83 },
84 #ifdef VK_USE_PLATFORM_XCB_KHR
85 {
86 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_XLIB_KHR
91 {
92 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
93 .specVersion = 6,
94 },
95 #endif
96 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
97 {
98 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
99 .specVersion = 6,
100 },
101 #endif
102 {
103 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
104 .specVersion = 1,
105 },
106 {
107 .extensionName = VK_KHR_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
108 .specVersion = 1,
109 },
110 {
111 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_CAPABILITIES_EXTENSION_NAME,
112 .specVersion = 1,
113 },
114 };
115
116 static const VkExtensionProperties common_device_extensions[] = {
117 {
118 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
119 .specVersion = 1,
120 },
121 {
122 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
123 .specVersion = 1,
124 },
125 {
126 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
127 .specVersion = 1,
128 },
129 {
130 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
131 .specVersion = 1,
132 },
133 {
134 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
135 .specVersion = 1,
136 },
137 {
138 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
139 .specVersion = 68,
140 },
141 {
142 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
143 .specVersion = 1,
144 },
145 {
146 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
147 .specVersion = 1,
148 },
149 {
150 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
151 .specVersion = 1,
152 },
153 {
154 .extensionName = VK_KHR_DEDICATED_ALLOCATION_EXTENSION_NAME,
155 .specVersion = 1,
156 },
157 {
158 .extensionName = VK_KHR_EXTERNAL_MEMORY_EXTENSION_NAME,
159 .specVersion = 1,
160 },
161 {
162 .extensionName = VK_KHR_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
163 .specVersion = 1,
164 },
165 {
166 .extensionName = VK_KHR_STORAGE_BUFFER_STORAGE_CLASS_EXTENSION_NAME,
167 .specVersion = 1,
168 },
169 {
170 .extensionName = VK_KHR_VARIABLE_POINTERS_EXTENSION_NAME,
171 .specVersion = 1,
172 },
173 {
174 .extensionName = VK_KHR_IMAGE_FORMAT_LIST_EXTENSION_NAME,
175 .specVersion = 1,
176 },
177 };
178 static const VkExtensionProperties ext_sema_device_extensions[] = {
179 {
180 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_EXTENSION_NAME,
181 .specVersion = 1,
182 },
183 {
184 .extensionName = VK_KHR_EXTERNAL_SEMAPHORE_FD_EXTENSION_NAME,
185 .specVersion = 1,
186 },
187 {
188 .extensionName = VK_KHX_MULTIVIEW_EXTENSION_NAME,
189 .specVersion = 1,
190 },
191 };
192
193 static VkResult
194 radv_extensions_register(struct radv_instance *instance,
195 struct radv_extensions *extensions,
196 const VkExtensionProperties *new_ext,
197 uint32_t num_ext)
198 {
199 size_t new_size;
200 VkExtensionProperties *new_ptr;
201
202 assert(new_ext && num_ext > 0);
203
204 if (!new_ext)
205 return VK_ERROR_INITIALIZATION_FAILED;
206
207 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
208 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
209 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
210
211 /* Old array continues to be valid, update nothing */
212 if (!new_ptr)
213 return VK_ERROR_OUT_OF_HOST_MEMORY;
214
215 memcpy(&new_ptr[extensions->num_ext], new_ext,
216 num_ext * sizeof(VkExtensionProperties));
217 extensions->ext_array = new_ptr;
218 extensions->num_ext += num_ext;
219
220 return VK_SUCCESS;
221 }
222
223 static void
224 radv_extensions_finish(struct radv_instance *instance,
225 struct radv_extensions *extensions)
226 {
227 assert(extensions);
228
229 if (!extensions)
230 radv_loge("Attemted to free invalid extension struct\n");
231
232 if (extensions->ext_array)
233 vk_free(&instance->alloc, extensions->ext_array);
234 }
235
236 static bool
237 is_extension_enabled(const VkExtensionProperties *extensions,
238 size_t num_ext,
239 const char *name)
240 {
241 assert(extensions && name);
242
243 for (uint32_t i = 0; i < num_ext; i++) {
244 if (strcmp(name, extensions[i].extensionName) == 0)
245 return true;
246 }
247
248 return false;
249 }
250
251 static const char *
252 get_chip_name(enum radeon_family family)
253 {
254 switch (family) {
255 case CHIP_TAHITI: return "AMD RADV TAHITI";
256 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
257 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
258 case CHIP_OLAND: return "AMD RADV OLAND";
259 case CHIP_HAINAN: return "AMD RADV HAINAN";
260 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
261 case CHIP_KAVERI: return "AMD RADV KAVERI";
262 case CHIP_KABINI: return "AMD RADV KABINI";
263 case CHIP_HAWAII: return "AMD RADV HAWAII";
264 case CHIP_MULLINS: return "AMD RADV MULLINS";
265 case CHIP_TONGA: return "AMD RADV TONGA";
266 case CHIP_ICELAND: return "AMD RADV ICELAND";
267 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
268 case CHIP_FIJI: return "AMD RADV FIJI";
269 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
270 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
271 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
272 case CHIP_STONEY: return "AMD RADV STONEY";
273 case CHIP_VEGA10: return "AMD RADV VEGA";
274 case CHIP_RAVEN: return "AMD RADV RAVEN";
275 default: return "AMD RADV unknown";
276 }
277 }
278
279 static VkResult
280 radv_physical_device_init(struct radv_physical_device *device,
281 struct radv_instance *instance,
282 drmDevicePtr drm_device)
283 {
284 const char *path = drm_device->nodes[DRM_NODE_RENDER];
285 VkResult result;
286 drmVersionPtr version;
287 int fd;
288
289 fd = open(path, O_RDWR | O_CLOEXEC);
290 if (fd < 0)
291 return VK_ERROR_INCOMPATIBLE_DRIVER;
292
293 version = drmGetVersion(fd);
294 if (!version) {
295 close(fd);
296 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
297 "failed to get version %s: %m", path);
298 }
299
300 if (strcmp(version->name, "amdgpu")) {
301 drmFreeVersion(version);
302 close(fd);
303 return VK_ERROR_INCOMPATIBLE_DRIVER;
304 }
305 drmFreeVersion(version);
306
307 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
308 device->instance = instance;
309 assert(strlen(path) < ARRAY_SIZE(device->path));
310 strncpy(device->path, path, ARRAY_SIZE(device->path));
311
312 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
313 instance->perftest_flags);
314 if (!device->ws) {
315 result = VK_ERROR_INCOMPATIBLE_DRIVER;
316 goto fail;
317 }
318
319 device->local_fd = fd;
320 device->ws->query_info(device->ws, &device->rad_info);
321 result = radv_init_wsi(device);
322 if (result != VK_SUCCESS) {
323 device->ws->destroy(device->ws);
324 goto fail;
325 }
326
327 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
328 radv_finish_wsi(device);
329 device->ws->destroy(device->ws);
330 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
331 "cannot generate UUID");
332 goto fail;
333 }
334
335 result = radv_extensions_register(instance,
336 &device->extensions,
337 common_device_extensions,
338 ARRAY_SIZE(common_device_extensions));
339 if (result != VK_SUCCESS)
340 goto fail;
341
342 if (device->rad_info.has_syncobj) {
343 result = radv_extensions_register(instance,
344 &device->extensions,
345 ext_sema_device_extensions,
346 ARRAY_SIZE(ext_sema_device_extensions));
347 if (result != VK_SUCCESS)
348 goto fail;
349 }
350
351 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
352 device->name = get_chip_name(device->rad_info.family);
353
354 radv_get_driver_uuid(&device->device_uuid);
355 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
356
357 if (device->rad_info.family == CHIP_STONEY ||
358 device->rad_info.chip_class >= GFX9) {
359 device->has_rbplus = true;
360 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
361 }
362
363 return VK_SUCCESS;
364
365 fail:
366 close(fd);
367 return result;
368 }
369
370 static void
371 radv_physical_device_finish(struct radv_physical_device *device)
372 {
373 radv_extensions_finish(device->instance, &device->extensions);
374 radv_finish_wsi(device);
375 device->ws->destroy(device->ws);
376 close(device->local_fd);
377 }
378
379 static void *
380 default_alloc_func(void *pUserData, size_t size, size_t align,
381 VkSystemAllocationScope allocationScope)
382 {
383 return malloc(size);
384 }
385
386 static void *
387 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
388 size_t align, VkSystemAllocationScope allocationScope)
389 {
390 return realloc(pOriginal, size);
391 }
392
393 static void
394 default_free_func(void *pUserData, void *pMemory)
395 {
396 free(pMemory);
397 }
398
399 static const VkAllocationCallbacks default_alloc = {
400 .pUserData = NULL,
401 .pfnAllocation = default_alloc_func,
402 .pfnReallocation = default_realloc_func,
403 .pfnFree = default_free_func,
404 };
405
406 static const struct debug_control radv_debug_options[] = {
407 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
408 {"nodcc", RADV_DEBUG_NO_DCC},
409 {"shaders", RADV_DEBUG_DUMP_SHADERS},
410 {"nocache", RADV_DEBUG_NO_CACHE},
411 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
412 {"nohiz", RADV_DEBUG_NO_HIZ},
413 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
414 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
415 {"allbos", RADV_DEBUG_ALL_BOS},
416 {"noibs", RADV_DEBUG_NO_IBS},
417 {"spirv", RADV_DEBUG_DUMP_SPIRV},
418 {"vmfaults", RADV_DEBUG_VM_FAULTS},
419 {"zerovram", RADV_DEBUG_ZERO_VRAM},
420 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
421 {NULL, 0}
422 };
423
424 const char *
425 radv_get_debug_option_name(int id)
426 {
427 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
428 return radv_debug_options[id].string;
429 }
430
431 static const struct debug_control radv_perftest_options[] = {
432 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
433 {"sisched", RADV_PERFTEST_SISCHED},
434 {NULL, 0}
435 };
436
437 const char *
438 radv_get_perftest_option_name(int id)
439 {
440 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
441 return radv_perftest_options[id].string;
442 }
443
444 VkResult radv_CreateInstance(
445 const VkInstanceCreateInfo* pCreateInfo,
446 const VkAllocationCallbacks* pAllocator,
447 VkInstance* pInstance)
448 {
449 struct radv_instance *instance;
450
451 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
452
453 uint32_t client_version;
454 if (pCreateInfo->pApplicationInfo &&
455 pCreateInfo->pApplicationInfo->apiVersion != 0) {
456 client_version = pCreateInfo->pApplicationInfo->apiVersion;
457 } else {
458 client_version = VK_MAKE_VERSION(1, 0, 0);
459 }
460
461 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
462 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
463 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
464 "Client requested version %d.%d.%d",
465 VK_VERSION_MAJOR(client_version),
466 VK_VERSION_MINOR(client_version),
467 VK_VERSION_PATCH(client_version));
468 }
469
470 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
471 if (!is_extension_enabled(instance_extensions,
472 ARRAY_SIZE(instance_extensions),
473 pCreateInfo->ppEnabledExtensionNames[i]))
474 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
475 }
476
477 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
478 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
479 if (!instance)
480 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
481
482 memset(instance, 0, sizeof(*instance));
483
484 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
485
486 if (pAllocator)
487 instance->alloc = *pAllocator;
488 else
489 instance->alloc = default_alloc;
490
491 instance->apiVersion = client_version;
492 instance->physicalDeviceCount = -1;
493
494 _mesa_locale_init();
495
496 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
497
498 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
499 radv_debug_options);
500
501 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
502 radv_perftest_options);
503
504 *pInstance = radv_instance_to_handle(instance);
505
506 return VK_SUCCESS;
507 }
508
509 void radv_DestroyInstance(
510 VkInstance _instance,
511 const VkAllocationCallbacks* pAllocator)
512 {
513 RADV_FROM_HANDLE(radv_instance, instance, _instance);
514
515 if (!instance)
516 return;
517
518 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
519 radv_physical_device_finish(instance->physicalDevices + i);
520 }
521
522 VG(VALGRIND_DESTROY_MEMPOOL(instance));
523
524 _mesa_locale_fini();
525
526 vk_free(&instance->alloc, instance);
527 }
528
529 static VkResult
530 radv_enumerate_devices(struct radv_instance *instance)
531 {
532 /* TODO: Check for more devices ? */
533 drmDevicePtr devices[8];
534 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
535 int max_devices;
536
537 instance->physicalDeviceCount = 0;
538
539 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
540 if (max_devices < 1)
541 return VK_ERROR_INCOMPATIBLE_DRIVER;
542
543 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
544 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
545 devices[i]->bustype == DRM_BUS_PCI &&
546 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
547
548 result = radv_physical_device_init(instance->physicalDevices +
549 instance->physicalDeviceCount,
550 instance,
551 devices[i]);
552 if (result == VK_SUCCESS)
553 ++instance->physicalDeviceCount;
554 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
555 break;
556 }
557 }
558 drmFreeDevices(devices, max_devices);
559
560 return result;
561 }
562
563 VkResult radv_EnumeratePhysicalDevices(
564 VkInstance _instance,
565 uint32_t* pPhysicalDeviceCount,
566 VkPhysicalDevice* pPhysicalDevices)
567 {
568 RADV_FROM_HANDLE(radv_instance, instance, _instance);
569 VkResult result;
570
571 if (instance->physicalDeviceCount < 0) {
572 result = radv_enumerate_devices(instance);
573 if (result != VK_SUCCESS &&
574 result != VK_ERROR_INCOMPATIBLE_DRIVER)
575 return result;
576 }
577
578 if (!pPhysicalDevices) {
579 *pPhysicalDeviceCount = instance->physicalDeviceCount;
580 } else {
581 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
582 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
583 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
584 }
585
586 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
587 : VK_SUCCESS;
588 }
589
590 void radv_GetPhysicalDeviceFeatures(
591 VkPhysicalDevice physicalDevice,
592 VkPhysicalDeviceFeatures* pFeatures)
593 {
594 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
595 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
596 memset(pFeatures, 0, sizeof(*pFeatures));
597
598 *pFeatures = (VkPhysicalDeviceFeatures) {
599 .robustBufferAccess = true,
600 .fullDrawIndexUint32 = true,
601 .imageCubeArray = true,
602 .independentBlend = true,
603 .geometryShader = !is_gfx9,
604 .tessellationShader = !is_gfx9,
605 .sampleRateShading = true,
606 .dualSrcBlend = true,
607 .logicOp = true,
608 .multiDrawIndirect = true,
609 .drawIndirectFirstInstance = true,
610 .depthClamp = true,
611 .depthBiasClamp = true,
612 .fillModeNonSolid = true,
613 .depthBounds = true,
614 .wideLines = true,
615 .largePoints = true,
616 .alphaToOne = true,
617 .multiViewport = true,
618 .samplerAnisotropy = true,
619 .textureCompressionETC2 = false,
620 .textureCompressionASTC_LDR = false,
621 .textureCompressionBC = true,
622 .occlusionQueryPrecise = true,
623 .pipelineStatisticsQuery = true,
624 .vertexPipelineStoresAndAtomics = true,
625 .fragmentStoresAndAtomics = true,
626 .shaderTessellationAndGeometryPointSize = true,
627 .shaderImageGatherExtended = true,
628 .shaderStorageImageExtendedFormats = true,
629 .shaderStorageImageMultisample = false,
630 .shaderUniformBufferArrayDynamicIndexing = true,
631 .shaderSampledImageArrayDynamicIndexing = true,
632 .shaderStorageBufferArrayDynamicIndexing = true,
633 .shaderStorageImageArrayDynamicIndexing = true,
634 .shaderStorageImageReadWithoutFormat = true,
635 .shaderStorageImageWriteWithoutFormat = true,
636 .shaderClipDistance = true,
637 .shaderCullDistance = true,
638 .shaderFloat64 = true,
639 .shaderInt64 = true,
640 .shaderInt16 = false,
641 .sparseBinding = true,
642 .variableMultisampleRate = true,
643 .inheritedQueries = true,
644 };
645 }
646
647 void radv_GetPhysicalDeviceFeatures2KHR(
648 VkPhysicalDevice physicalDevice,
649 VkPhysicalDeviceFeatures2KHR *pFeatures)
650 {
651 vk_foreach_struct(ext, pFeatures->pNext) {
652 switch (ext->sType) {
653 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
654 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
655 features->variablePointersStorageBuffer = true;
656 features->variablePointers = false;
657 break;
658 }
659 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHX: {
660 VkPhysicalDeviceMultiviewFeaturesKHX *features = (VkPhysicalDeviceMultiviewFeaturesKHX*)ext;
661 features->multiview = true;
662 features->multiviewGeometryShader = true;
663 features->multiviewTessellationShader = true;
664 break;
665 }
666 default:
667 break;
668 }
669 }
670 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
671 }
672
673 void radv_GetPhysicalDeviceProperties(
674 VkPhysicalDevice physicalDevice,
675 VkPhysicalDeviceProperties* pProperties)
676 {
677 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
678 VkSampleCountFlags sample_counts = 0xf;
679
680 /* make sure that the entire descriptor set is addressable with a signed
681 * 32-bit int. So the sum of all limits scaled by descriptor size has to
682 * be at most 2 GiB. the combined image & samples object count as one of
683 * both. This limit is for the pipeline layout, not for the set layout, but
684 * there is no set limit, so we just set a pipeline limit. I don't think
685 * any app is going to hit this soon. */
686 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
687 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
688 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
689 32 /* sampler, largest when combined with image */ +
690 64 /* sampled image */ +
691 64 /* storage image */);
692
693 VkPhysicalDeviceLimits limits = {
694 .maxImageDimension1D = (1 << 14),
695 .maxImageDimension2D = (1 << 14),
696 .maxImageDimension3D = (1 << 11),
697 .maxImageDimensionCube = (1 << 14),
698 .maxImageArrayLayers = (1 << 11),
699 .maxTexelBufferElements = 128 * 1024 * 1024,
700 .maxUniformBufferRange = UINT32_MAX,
701 .maxStorageBufferRange = UINT32_MAX,
702 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
703 .maxMemoryAllocationCount = UINT32_MAX,
704 .maxSamplerAllocationCount = 64 * 1024,
705 .bufferImageGranularity = 64, /* A cache line */
706 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
707 .maxBoundDescriptorSets = MAX_SETS,
708 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
709 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
710 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
711 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
712 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
713 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
714 .maxPerStageResources = max_descriptor_set_size,
715 .maxDescriptorSetSamplers = max_descriptor_set_size,
716 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
717 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
718 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
719 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
720 .maxDescriptorSetSampledImages = max_descriptor_set_size,
721 .maxDescriptorSetStorageImages = max_descriptor_set_size,
722 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
723 .maxVertexInputAttributes = 32,
724 .maxVertexInputBindings = 32,
725 .maxVertexInputAttributeOffset = 2047,
726 .maxVertexInputBindingStride = 2048,
727 .maxVertexOutputComponents = 128,
728 .maxTessellationGenerationLevel = 64,
729 .maxTessellationPatchSize = 32,
730 .maxTessellationControlPerVertexInputComponents = 128,
731 .maxTessellationControlPerVertexOutputComponents = 128,
732 .maxTessellationControlPerPatchOutputComponents = 120,
733 .maxTessellationControlTotalOutputComponents = 4096,
734 .maxTessellationEvaluationInputComponents = 128,
735 .maxTessellationEvaluationOutputComponents = 128,
736 .maxGeometryShaderInvocations = 127,
737 .maxGeometryInputComponents = 64,
738 .maxGeometryOutputComponents = 128,
739 .maxGeometryOutputVertices = 256,
740 .maxGeometryTotalOutputComponents = 1024,
741 .maxFragmentInputComponents = 128,
742 .maxFragmentOutputAttachments = 8,
743 .maxFragmentDualSrcAttachments = 1,
744 .maxFragmentCombinedOutputResources = 8,
745 .maxComputeSharedMemorySize = 32768,
746 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
747 .maxComputeWorkGroupInvocations = 2048,
748 .maxComputeWorkGroupSize = {
749 2048,
750 2048,
751 2048
752 },
753 .subPixelPrecisionBits = 4 /* FIXME */,
754 .subTexelPrecisionBits = 4 /* FIXME */,
755 .mipmapPrecisionBits = 4 /* FIXME */,
756 .maxDrawIndexedIndexValue = UINT32_MAX,
757 .maxDrawIndirectCount = UINT32_MAX,
758 .maxSamplerLodBias = 16,
759 .maxSamplerAnisotropy = 16,
760 .maxViewports = MAX_VIEWPORTS,
761 .maxViewportDimensions = { (1 << 14), (1 << 14) },
762 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
763 .viewportSubPixelBits = 13, /* We take a float? */
764 .minMemoryMapAlignment = 4096, /* A page */
765 .minTexelBufferOffsetAlignment = 1,
766 .minUniformBufferOffsetAlignment = 4,
767 .minStorageBufferOffsetAlignment = 4,
768 .minTexelOffset = -32,
769 .maxTexelOffset = 31,
770 .minTexelGatherOffset = -32,
771 .maxTexelGatherOffset = 31,
772 .minInterpolationOffset = -2,
773 .maxInterpolationOffset = 2,
774 .subPixelInterpolationOffsetBits = 8,
775 .maxFramebufferWidth = (1 << 14),
776 .maxFramebufferHeight = (1 << 14),
777 .maxFramebufferLayers = (1 << 10),
778 .framebufferColorSampleCounts = sample_counts,
779 .framebufferDepthSampleCounts = sample_counts,
780 .framebufferStencilSampleCounts = sample_counts,
781 .framebufferNoAttachmentsSampleCounts = sample_counts,
782 .maxColorAttachments = MAX_RTS,
783 .sampledImageColorSampleCounts = sample_counts,
784 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
785 .sampledImageDepthSampleCounts = sample_counts,
786 .sampledImageStencilSampleCounts = sample_counts,
787 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
788 .maxSampleMaskWords = 1,
789 .timestampComputeAndGraphics = true,
790 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
791 .maxClipDistances = 8,
792 .maxCullDistances = 8,
793 .maxCombinedClipAndCullDistances = 8,
794 .discreteQueuePriorities = 1,
795 .pointSizeRange = { 0.125, 255.875 },
796 .lineWidthRange = { 0.0, 7.9921875 },
797 .pointSizeGranularity = (1.0 / 8.0),
798 .lineWidthGranularity = (1.0 / 128.0),
799 .strictLines = false, /* FINISHME */
800 .standardSampleLocations = true,
801 .optimalBufferCopyOffsetAlignment = 128,
802 .optimalBufferCopyRowPitchAlignment = 128,
803 .nonCoherentAtomSize = 64,
804 };
805
806 *pProperties = (VkPhysicalDeviceProperties) {
807 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
808 .driverVersion = vk_get_driver_version(),
809 .vendorID = 0x1002,
810 .deviceID = pdevice->rad_info.pci_id,
811 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
812 .limits = limits,
813 .sparseProperties = {0},
814 };
815
816 strcpy(pProperties->deviceName, pdevice->name);
817 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
818 }
819
820 void radv_GetPhysicalDeviceProperties2KHR(
821 VkPhysicalDevice physicalDevice,
822 VkPhysicalDeviceProperties2KHR *pProperties)
823 {
824 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
825 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
826
827 vk_foreach_struct(ext, pProperties->pNext) {
828 switch (ext->sType) {
829 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
830 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
831 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
832 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
833 break;
834 }
835 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
836 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
837 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
838 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
839 properties->deviceLUIDValid = false;
840 break;
841 }
842 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHX: {
843 VkPhysicalDeviceMultiviewPropertiesKHX *properties = (VkPhysicalDeviceMultiviewPropertiesKHX*)ext;
844 properties->maxMultiviewViewCount = MAX_VIEWS;
845 properties->maxMultiviewInstanceIndex = INT_MAX;
846 break;
847 }
848 default:
849 break;
850 }
851 }
852 }
853
854 static void radv_get_physical_device_queue_family_properties(
855 struct radv_physical_device* pdevice,
856 uint32_t* pCount,
857 VkQueueFamilyProperties** pQueueFamilyProperties)
858 {
859 int num_queue_families = 1;
860 int idx;
861 if (pdevice->rad_info.num_compute_rings > 0 &&
862 pdevice->rad_info.chip_class >= CIK &&
863 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
864 num_queue_families++;
865
866 if (pQueueFamilyProperties == NULL) {
867 *pCount = num_queue_families;
868 return;
869 }
870
871 if (!*pCount)
872 return;
873
874 idx = 0;
875 if (*pCount >= 1) {
876 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
877 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
878 VK_QUEUE_COMPUTE_BIT |
879 VK_QUEUE_TRANSFER_BIT |
880 VK_QUEUE_SPARSE_BINDING_BIT,
881 .queueCount = 1,
882 .timestampValidBits = 64,
883 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
884 };
885 idx++;
886 }
887
888 if (pdevice->rad_info.num_compute_rings > 0 &&
889 pdevice->rad_info.chip_class >= CIK &&
890 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
891 if (*pCount > idx) {
892 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
893 .queueFlags = VK_QUEUE_COMPUTE_BIT |
894 VK_QUEUE_TRANSFER_BIT |
895 VK_QUEUE_SPARSE_BINDING_BIT,
896 .queueCount = pdevice->rad_info.num_compute_rings,
897 .timestampValidBits = 64,
898 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
899 };
900 idx++;
901 }
902 }
903 *pCount = idx;
904 }
905
906 void radv_GetPhysicalDeviceQueueFamilyProperties(
907 VkPhysicalDevice physicalDevice,
908 uint32_t* pCount,
909 VkQueueFamilyProperties* pQueueFamilyProperties)
910 {
911 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
912 if (!pQueueFamilyProperties) {
913 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
914 return;
915 }
916 VkQueueFamilyProperties *properties[] = {
917 pQueueFamilyProperties + 0,
918 pQueueFamilyProperties + 1,
919 pQueueFamilyProperties + 2,
920 };
921 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
922 assert(*pCount <= 3);
923 }
924
925 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
926 VkPhysicalDevice physicalDevice,
927 uint32_t* pCount,
928 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
929 {
930 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
931 if (!pQueueFamilyProperties) {
932 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
933 return;
934 }
935 VkQueueFamilyProperties *properties[] = {
936 &pQueueFamilyProperties[0].queueFamilyProperties,
937 &pQueueFamilyProperties[1].queueFamilyProperties,
938 &pQueueFamilyProperties[2].queueFamilyProperties,
939 };
940 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
941 assert(*pCount <= 3);
942 }
943
944 void radv_GetPhysicalDeviceMemoryProperties(
945 VkPhysicalDevice physicalDevice,
946 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
947 {
948 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
949
950 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
951
952 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
953 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
954 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
955 .heapIndex = RADV_MEM_HEAP_VRAM,
956 };
957 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
958 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
959 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
960 .heapIndex = RADV_MEM_HEAP_GTT,
961 };
962 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
963 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
964 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
965 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
966 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
967 };
968 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
969 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
970 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
971 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
972 .heapIndex = RADV_MEM_HEAP_GTT,
973 };
974
975 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
976 uint64_t visible_vram_size = MIN2(physical_device->rad_info.vram_size,
977 physical_device->rad_info.vram_vis_size);
978
979 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
980 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
981 .size = physical_device->rad_info.vram_size -
982 visible_vram_size,
983 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
984 };
985 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
986 .size = visible_vram_size,
987 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
988 };
989 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
990 .size = physical_device->rad_info.gart_size,
991 .flags = 0,
992 };
993 }
994
995 void radv_GetPhysicalDeviceMemoryProperties2KHR(
996 VkPhysicalDevice physicalDevice,
997 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
998 {
999 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1000 &pMemoryProperties->memoryProperties);
1001 }
1002
1003 static int
1004 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1005 int queue_family_index, int idx)
1006 {
1007 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1008 queue->device = device;
1009 queue->queue_family_index = queue_family_index;
1010 queue->queue_idx = idx;
1011
1012 queue->hw_ctx = device->ws->ctx_create(device->ws);
1013 if (!queue->hw_ctx)
1014 return VK_ERROR_OUT_OF_HOST_MEMORY;
1015
1016 return VK_SUCCESS;
1017 }
1018
1019 static void
1020 radv_queue_finish(struct radv_queue *queue)
1021 {
1022 if (queue->hw_ctx)
1023 queue->device->ws->ctx_destroy(queue->hw_ctx);
1024
1025 if (queue->initial_full_flush_preamble_cs)
1026 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1027 if (queue->initial_preamble_cs)
1028 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1029 if (queue->continue_preamble_cs)
1030 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1031 if (queue->descriptor_bo)
1032 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1033 if (queue->scratch_bo)
1034 queue->device->ws->buffer_destroy(queue->scratch_bo);
1035 if (queue->esgs_ring_bo)
1036 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1037 if (queue->gsvs_ring_bo)
1038 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1039 if (queue->tess_factor_ring_bo)
1040 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
1041 if (queue->tess_offchip_ring_bo)
1042 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
1043 if (queue->compute_scratch_bo)
1044 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1045 }
1046
1047 static void
1048 radv_device_init_gs_info(struct radv_device *device)
1049 {
1050 switch (device->physical_device->rad_info.family) {
1051 case CHIP_OLAND:
1052 case CHIP_HAINAN:
1053 case CHIP_KAVERI:
1054 case CHIP_KABINI:
1055 case CHIP_MULLINS:
1056 case CHIP_ICELAND:
1057 case CHIP_CARRIZO:
1058 case CHIP_STONEY:
1059 device->gs_table_depth = 16;
1060 return;
1061 case CHIP_TAHITI:
1062 case CHIP_PITCAIRN:
1063 case CHIP_VERDE:
1064 case CHIP_BONAIRE:
1065 case CHIP_HAWAII:
1066 case CHIP_TONGA:
1067 case CHIP_FIJI:
1068 case CHIP_POLARIS10:
1069 case CHIP_POLARIS11:
1070 case CHIP_POLARIS12:
1071 case CHIP_VEGA10:
1072 case CHIP_RAVEN:
1073 device->gs_table_depth = 32;
1074 return;
1075 default:
1076 unreachable("unknown GPU");
1077 }
1078 }
1079
1080 VkResult radv_CreateDevice(
1081 VkPhysicalDevice physicalDevice,
1082 const VkDeviceCreateInfo* pCreateInfo,
1083 const VkAllocationCallbacks* pAllocator,
1084 VkDevice* pDevice)
1085 {
1086 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1087 VkResult result;
1088 struct radv_device *device;
1089
1090 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1091 if (!is_extension_enabled(physical_device->extensions.ext_array,
1092 physical_device->extensions.num_ext,
1093 pCreateInfo->ppEnabledExtensionNames[i]))
1094 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1095 }
1096
1097 /* Check enabled features */
1098 if (pCreateInfo->pEnabledFeatures) {
1099 VkPhysicalDeviceFeatures supported_features;
1100 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1101 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1102 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1103 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1104 for (uint32_t i = 0; i < num_features; i++) {
1105 if (enabled_feature[i] && !supported_feature[i])
1106 return vk_error(VK_ERROR_FEATURE_NOT_PRESENT);
1107 }
1108 }
1109
1110 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1111 sizeof(*device), 8,
1112 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1113 if (!device)
1114 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1115
1116 memset(device, 0, sizeof(*device));
1117
1118 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1119 device->instance = physical_device->instance;
1120 device->physical_device = physical_device;
1121
1122 device->debug_flags = device->instance->debug_flags;
1123
1124 device->ws = physical_device->ws;
1125 if (pAllocator)
1126 device->alloc = *pAllocator;
1127 else
1128 device->alloc = physical_device->instance->alloc;
1129
1130 mtx_init(&device->shader_slab_mutex, mtx_plain);
1131 list_inithead(&device->shader_slabs);
1132
1133 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1134 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1135 uint32_t qfi = queue_create->queueFamilyIndex;
1136
1137 device->queues[qfi] = vk_alloc(&device->alloc,
1138 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1139 if (!device->queues[qfi]) {
1140 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1141 goto fail;
1142 }
1143
1144 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1145
1146 device->queue_count[qfi] = queue_create->queueCount;
1147
1148 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1149 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1150 if (result != VK_SUCCESS)
1151 goto fail;
1152 }
1153 }
1154
1155 #if HAVE_LLVM < 0x0400
1156 device->llvm_supports_spill = false;
1157 #else
1158 device->llvm_supports_spill = true;
1159 #endif
1160
1161 /* The maximum number of scratch waves. Scratch space isn't divided
1162 * evenly between CUs. The number is only a function of the number of CUs.
1163 * We can decrease the constant to decrease the scratch buffer size.
1164 *
1165 * sctx->scratch_waves must be >= the maximum posible size of
1166 * 1 threadgroup, so that the hw doesn't hang from being unable
1167 * to start any.
1168 *
1169 * The recommended value is 4 per CU at most. Higher numbers don't
1170 * bring much benefit, but they still occupy chip resources (think
1171 * async compute). I've seen ~2% performance difference between 4 and 32.
1172 */
1173 uint32_t max_threads_per_block = 2048;
1174 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1175 max_threads_per_block / 64);
1176
1177 radv_device_init_gs_info(device);
1178
1179 device->tess_offchip_block_dw_size =
1180 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1181 device->has_distributed_tess =
1182 device->physical_device->rad_info.chip_class >= VI &&
1183 device->physical_device->rad_info.max_se >= 2;
1184
1185 result = radv_device_init_meta(device);
1186 if (result != VK_SUCCESS)
1187 goto fail;
1188
1189 radv_device_init_msaa(device);
1190
1191 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1192 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1193 switch (family) {
1194 case RADV_QUEUE_GENERAL:
1195 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1196 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1197 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1198 break;
1199 case RADV_QUEUE_COMPUTE:
1200 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1201 radeon_emit(device->empty_cs[family], 0);
1202 break;
1203 }
1204 device->ws->cs_finalize(device->empty_cs[family]);
1205 }
1206
1207 if (getenv("RADV_TRACE_FILE")) {
1208 if (!radv_init_trace(device))
1209 goto fail;
1210 }
1211
1212 if (device->physical_device->rad_info.chip_class >= CIK)
1213 cik_create_gfx_config(device);
1214
1215 VkPipelineCacheCreateInfo ci;
1216 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1217 ci.pNext = NULL;
1218 ci.flags = 0;
1219 ci.pInitialData = NULL;
1220 ci.initialDataSize = 0;
1221 VkPipelineCache pc;
1222 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1223 &ci, NULL, &pc);
1224 if (result != VK_SUCCESS)
1225 goto fail;
1226
1227 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1228
1229 *pDevice = radv_device_to_handle(device);
1230 return VK_SUCCESS;
1231
1232 fail:
1233 if (device->trace_bo)
1234 device->ws->buffer_destroy(device->trace_bo);
1235
1236 if (device->gfx_init)
1237 device->ws->buffer_destroy(device->gfx_init);
1238
1239 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1240 for (unsigned q = 0; q < device->queue_count[i]; q++)
1241 radv_queue_finish(&device->queues[i][q]);
1242 if (device->queue_count[i])
1243 vk_free(&device->alloc, device->queues[i]);
1244 }
1245
1246 vk_free(&device->alloc, device);
1247 return result;
1248 }
1249
1250 void radv_DestroyDevice(
1251 VkDevice _device,
1252 const VkAllocationCallbacks* pAllocator)
1253 {
1254 RADV_FROM_HANDLE(radv_device, device, _device);
1255
1256 if (!device)
1257 return;
1258
1259 if (device->trace_bo)
1260 device->ws->buffer_destroy(device->trace_bo);
1261
1262 if (device->gfx_init)
1263 device->ws->buffer_destroy(device->gfx_init);
1264
1265 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1266 for (unsigned q = 0; q < device->queue_count[i]; q++)
1267 radv_queue_finish(&device->queues[i][q]);
1268 if (device->queue_count[i])
1269 vk_free(&device->alloc, device->queues[i]);
1270 if (device->empty_cs[i])
1271 device->ws->cs_destroy(device->empty_cs[i]);
1272 }
1273 radv_device_finish_meta(device);
1274
1275 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1276 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1277
1278 radv_destroy_shader_slabs(device);
1279
1280 vk_free(&device->alloc, device);
1281 }
1282
1283 VkResult radv_EnumerateInstanceExtensionProperties(
1284 const char* pLayerName,
1285 uint32_t* pPropertyCount,
1286 VkExtensionProperties* pProperties)
1287 {
1288 if (pProperties == NULL) {
1289 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1290 return VK_SUCCESS;
1291 }
1292
1293 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1294 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1295
1296 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1297 return VK_INCOMPLETE;
1298
1299 return VK_SUCCESS;
1300 }
1301
1302 VkResult radv_EnumerateDeviceExtensionProperties(
1303 VkPhysicalDevice physicalDevice,
1304 const char* pLayerName,
1305 uint32_t* pPropertyCount,
1306 VkExtensionProperties* pProperties)
1307 {
1308 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1309
1310 if (pProperties == NULL) {
1311 *pPropertyCount = pdevice->extensions.num_ext;
1312 return VK_SUCCESS;
1313 }
1314
1315 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1316 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1317
1318 if (*pPropertyCount < pdevice->extensions.num_ext)
1319 return VK_INCOMPLETE;
1320
1321 return VK_SUCCESS;
1322 }
1323
1324 VkResult radv_EnumerateInstanceLayerProperties(
1325 uint32_t* pPropertyCount,
1326 VkLayerProperties* pProperties)
1327 {
1328 if (pProperties == NULL) {
1329 *pPropertyCount = 0;
1330 return VK_SUCCESS;
1331 }
1332
1333 /* None supported at this time */
1334 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1335 }
1336
1337 VkResult radv_EnumerateDeviceLayerProperties(
1338 VkPhysicalDevice physicalDevice,
1339 uint32_t* pPropertyCount,
1340 VkLayerProperties* pProperties)
1341 {
1342 if (pProperties == NULL) {
1343 *pPropertyCount = 0;
1344 return VK_SUCCESS;
1345 }
1346
1347 /* None supported at this time */
1348 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1349 }
1350
1351 void radv_GetDeviceQueue(
1352 VkDevice _device,
1353 uint32_t queueFamilyIndex,
1354 uint32_t queueIndex,
1355 VkQueue* pQueue)
1356 {
1357 RADV_FROM_HANDLE(radv_device, device, _device);
1358
1359 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1360 }
1361
1362 static void
1363 fill_geom_tess_rings(struct radv_queue *queue,
1364 uint32_t *map,
1365 bool add_sample_positions,
1366 uint32_t esgs_ring_size,
1367 struct radeon_winsys_bo *esgs_ring_bo,
1368 uint32_t gsvs_ring_size,
1369 struct radeon_winsys_bo *gsvs_ring_bo,
1370 uint32_t tess_factor_ring_size,
1371 struct radeon_winsys_bo *tess_factor_ring_bo,
1372 uint32_t tess_offchip_ring_size,
1373 struct radeon_winsys_bo *tess_offchip_ring_bo)
1374 {
1375 uint64_t esgs_va = 0, gsvs_va = 0;
1376 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1377 uint32_t *desc = &map[4];
1378
1379 if (esgs_ring_bo)
1380 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1381 if (gsvs_ring_bo)
1382 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1383 if (tess_factor_ring_bo)
1384 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1385 if (tess_offchip_ring_bo)
1386 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1387
1388 /* stride 0, num records - size, add tid, swizzle, elsize4,
1389 index stride 64 */
1390 desc[0] = esgs_va;
1391 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1392 S_008F04_STRIDE(0) |
1393 S_008F04_SWIZZLE_ENABLE(true);
1394 desc[2] = esgs_ring_size;
1395 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1396 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1397 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1398 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1399 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1400 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1401 S_008F0C_ELEMENT_SIZE(1) |
1402 S_008F0C_INDEX_STRIDE(3) |
1403 S_008F0C_ADD_TID_ENABLE(true);
1404
1405 desc += 4;
1406 /* GS entry for ES->GS ring */
1407 /* stride 0, num records - size, elsize0,
1408 index stride 0 */
1409 desc[0] = esgs_va;
1410 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1411 S_008F04_STRIDE(0) |
1412 S_008F04_SWIZZLE_ENABLE(false);
1413 desc[2] = esgs_ring_size;
1414 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1415 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1416 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1417 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1418 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1419 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1420 S_008F0C_ELEMENT_SIZE(0) |
1421 S_008F0C_INDEX_STRIDE(0) |
1422 S_008F0C_ADD_TID_ENABLE(false);
1423
1424 desc += 4;
1425 /* VS entry for GS->VS ring */
1426 /* stride 0, num records - size, elsize0,
1427 index stride 0 */
1428 desc[0] = gsvs_va;
1429 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1430 S_008F04_STRIDE(0) |
1431 S_008F04_SWIZZLE_ENABLE(false);
1432 desc[2] = gsvs_ring_size;
1433 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1434 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1435 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1436 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1437 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1438 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1439 S_008F0C_ELEMENT_SIZE(0) |
1440 S_008F0C_INDEX_STRIDE(0) |
1441 S_008F0C_ADD_TID_ENABLE(false);
1442 desc += 4;
1443
1444 /* stride gsvs_itemsize, num records 64
1445 elsize 4, index stride 16 */
1446 /* shader will patch stride and desc[2] */
1447 desc[0] = gsvs_va;
1448 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1449 S_008F04_STRIDE(0) |
1450 S_008F04_SWIZZLE_ENABLE(true);
1451 desc[2] = 0;
1452 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1453 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1454 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1455 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1456 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1457 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1458 S_008F0C_ELEMENT_SIZE(1) |
1459 S_008F0C_INDEX_STRIDE(1) |
1460 S_008F0C_ADD_TID_ENABLE(true);
1461 desc += 4;
1462
1463 desc[0] = tess_factor_va;
1464 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1465 S_008F04_STRIDE(0) |
1466 S_008F04_SWIZZLE_ENABLE(false);
1467 desc[2] = tess_factor_ring_size;
1468 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1469 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1470 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1471 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1472 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1473 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1474 S_008F0C_ELEMENT_SIZE(0) |
1475 S_008F0C_INDEX_STRIDE(0) |
1476 S_008F0C_ADD_TID_ENABLE(false);
1477 desc += 4;
1478
1479 desc[0] = tess_offchip_va;
1480 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1481 S_008F04_STRIDE(0) |
1482 S_008F04_SWIZZLE_ENABLE(false);
1483 desc[2] = tess_offchip_ring_size;
1484 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1485 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1486 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1487 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1488 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1489 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1490 S_008F0C_ELEMENT_SIZE(0) |
1491 S_008F0C_INDEX_STRIDE(0) |
1492 S_008F0C_ADD_TID_ENABLE(false);
1493 desc += 4;
1494
1495 /* add sample positions after all rings */
1496 memcpy(desc, queue->device->sample_locations_1x, 8);
1497 desc += 2;
1498 memcpy(desc, queue->device->sample_locations_2x, 16);
1499 desc += 4;
1500 memcpy(desc, queue->device->sample_locations_4x, 32);
1501 desc += 8;
1502 memcpy(desc, queue->device->sample_locations_8x, 64);
1503 desc += 16;
1504 memcpy(desc, queue->device->sample_locations_16x, 128);
1505 }
1506
1507 static unsigned
1508 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1509 {
1510 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1511 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1512 device->physical_device->rad_info.family != CHIP_STONEY;
1513 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1514 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1515 device->physical_device->rad_info.max_se;
1516 unsigned offchip_granularity;
1517 unsigned hs_offchip_param;
1518 switch (device->tess_offchip_block_dw_size) {
1519 default:
1520 assert(0);
1521 /* fall through */
1522 case 8192:
1523 offchip_granularity = V_03093C_X_8K_DWORDS;
1524 break;
1525 case 4096:
1526 offchip_granularity = V_03093C_X_4K_DWORDS;
1527 break;
1528 }
1529
1530 switch (device->physical_device->rad_info.chip_class) {
1531 case SI:
1532 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1533 break;
1534 case CIK:
1535 case VI:
1536 case GFX9:
1537 default:
1538 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1539 break;
1540 }
1541
1542 *max_offchip_buffers_p = max_offchip_buffers;
1543 if (device->physical_device->rad_info.chip_class >= CIK) {
1544 if (device->physical_device->rad_info.chip_class >= VI)
1545 --max_offchip_buffers;
1546 hs_offchip_param =
1547 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1548 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1549 } else {
1550 hs_offchip_param =
1551 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1552 }
1553 return hs_offchip_param;
1554 }
1555
1556 static VkResult
1557 radv_get_preamble_cs(struct radv_queue *queue,
1558 uint32_t scratch_size,
1559 uint32_t compute_scratch_size,
1560 uint32_t esgs_ring_size,
1561 uint32_t gsvs_ring_size,
1562 bool needs_tess_rings,
1563 bool needs_sample_positions,
1564 struct radeon_winsys_cs **initial_full_flush_preamble_cs,
1565 struct radeon_winsys_cs **initial_preamble_cs,
1566 struct radeon_winsys_cs **continue_preamble_cs)
1567 {
1568 struct radeon_winsys_bo *scratch_bo = NULL;
1569 struct radeon_winsys_bo *descriptor_bo = NULL;
1570 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1571 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1572 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1573 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1574 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1575 struct radeon_winsys_cs *dest_cs[3] = {0};
1576 bool add_tess_rings = false, add_sample_positions = false;
1577 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1578 unsigned max_offchip_buffers;
1579 unsigned hs_offchip_param = 0;
1580 if (!queue->has_tess_rings) {
1581 if (needs_tess_rings)
1582 add_tess_rings = true;
1583 }
1584 if (!queue->has_sample_positions) {
1585 if (needs_sample_positions)
1586 add_sample_positions = true;
1587 }
1588 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1589 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1590 &max_offchip_buffers);
1591 tess_offchip_ring_size = max_offchip_buffers *
1592 queue->device->tess_offchip_block_dw_size * 4;
1593
1594 if (scratch_size <= queue->scratch_size &&
1595 compute_scratch_size <= queue->compute_scratch_size &&
1596 esgs_ring_size <= queue->esgs_ring_size &&
1597 gsvs_ring_size <= queue->gsvs_ring_size &&
1598 !add_tess_rings && !add_sample_positions &&
1599 queue->initial_preamble_cs) {
1600 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1601 *initial_preamble_cs = queue->initial_preamble_cs;
1602 *continue_preamble_cs = queue->continue_preamble_cs;
1603 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1604 *continue_preamble_cs = NULL;
1605 return VK_SUCCESS;
1606 }
1607
1608 if (scratch_size > queue->scratch_size) {
1609 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1610 scratch_size,
1611 4096,
1612 RADEON_DOMAIN_VRAM,
1613 RADEON_FLAG_NO_CPU_ACCESS);
1614 if (!scratch_bo)
1615 goto fail;
1616 } else
1617 scratch_bo = queue->scratch_bo;
1618
1619 if (compute_scratch_size > queue->compute_scratch_size) {
1620 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1621 compute_scratch_size,
1622 4096,
1623 RADEON_DOMAIN_VRAM,
1624 RADEON_FLAG_NO_CPU_ACCESS);
1625 if (!compute_scratch_bo)
1626 goto fail;
1627
1628 } else
1629 compute_scratch_bo = queue->compute_scratch_bo;
1630
1631 if (esgs_ring_size > queue->esgs_ring_size) {
1632 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1633 esgs_ring_size,
1634 4096,
1635 RADEON_DOMAIN_VRAM,
1636 RADEON_FLAG_NO_CPU_ACCESS);
1637 if (!esgs_ring_bo)
1638 goto fail;
1639 } else {
1640 esgs_ring_bo = queue->esgs_ring_bo;
1641 esgs_ring_size = queue->esgs_ring_size;
1642 }
1643
1644 if (gsvs_ring_size > queue->gsvs_ring_size) {
1645 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1646 gsvs_ring_size,
1647 4096,
1648 RADEON_DOMAIN_VRAM,
1649 RADEON_FLAG_NO_CPU_ACCESS);
1650 if (!gsvs_ring_bo)
1651 goto fail;
1652 } else {
1653 gsvs_ring_bo = queue->gsvs_ring_bo;
1654 gsvs_ring_size = queue->gsvs_ring_size;
1655 }
1656
1657 if (add_tess_rings) {
1658 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1659 tess_factor_ring_size,
1660 256,
1661 RADEON_DOMAIN_VRAM,
1662 RADEON_FLAG_NO_CPU_ACCESS);
1663 if (!tess_factor_ring_bo)
1664 goto fail;
1665 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1666 tess_offchip_ring_size,
1667 256,
1668 RADEON_DOMAIN_VRAM,
1669 RADEON_FLAG_NO_CPU_ACCESS);
1670 if (!tess_offchip_ring_bo)
1671 goto fail;
1672 } else {
1673 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1674 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1675 }
1676
1677 if (scratch_bo != queue->scratch_bo ||
1678 esgs_ring_bo != queue->esgs_ring_bo ||
1679 gsvs_ring_bo != queue->gsvs_ring_bo ||
1680 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1681 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1682 uint32_t size = 0;
1683 if (gsvs_ring_bo || esgs_ring_bo ||
1684 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1685 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1686 if (add_sample_positions)
1687 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1688 }
1689 else if (scratch_bo)
1690 size = 8; /* 2 dword */
1691
1692 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1693 size,
1694 4096,
1695 RADEON_DOMAIN_VRAM,
1696 RADEON_FLAG_CPU_ACCESS);
1697 if (!descriptor_bo)
1698 goto fail;
1699 } else
1700 descriptor_bo = queue->descriptor_bo;
1701
1702 for(int i = 0; i < 3; ++i) {
1703 struct radeon_winsys_cs *cs = NULL;
1704 cs = queue->device->ws->cs_create(queue->device->ws,
1705 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1706 if (!cs)
1707 goto fail;
1708
1709 dest_cs[i] = cs;
1710
1711 if (scratch_bo)
1712 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1713
1714 if (esgs_ring_bo)
1715 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1716
1717 if (gsvs_ring_bo)
1718 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1719
1720 if (tess_factor_ring_bo)
1721 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1722
1723 if (tess_offchip_ring_bo)
1724 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1725
1726 if (descriptor_bo)
1727 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1728
1729 if (descriptor_bo != queue->descriptor_bo) {
1730 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1731
1732 if (scratch_bo) {
1733 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1734 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1735 S_008F04_SWIZZLE_ENABLE(1);
1736 map[0] = scratch_va;
1737 map[1] = rsrc1;
1738 }
1739
1740 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1741 add_sample_positions)
1742 fill_geom_tess_rings(queue, map, add_sample_positions,
1743 esgs_ring_size, esgs_ring_bo,
1744 gsvs_ring_size, gsvs_ring_bo,
1745 tess_factor_ring_size, tess_factor_ring_bo,
1746 tess_offchip_ring_size, tess_offchip_ring_bo);
1747
1748 queue->device->ws->buffer_unmap(descriptor_bo);
1749 }
1750
1751 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1752 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1753 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1754 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1755 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1756 }
1757
1758 if (esgs_ring_bo || gsvs_ring_bo) {
1759 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1760 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1761 radeon_emit(cs, esgs_ring_size >> 8);
1762 radeon_emit(cs, gsvs_ring_size >> 8);
1763 } else {
1764 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1765 radeon_emit(cs, esgs_ring_size >> 8);
1766 radeon_emit(cs, gsvs_ring_size >> 8);
1767 }
1768 }
1769
1770 if (tess_factor_ring_bo) {
1771 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1772 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1773 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1774 S_030938_SIZE(tess_factor_ring_size / 4));
1775 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1776 tf_va >> 8);
1777 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1778 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1779 tf_va >> 40);
1780 }
1781 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1782 } else {
1783 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1784 S_008988_SIZE(tess_factor_ring_size / 4));
1785 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1786 tf_va >> 8);
1787 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1788 hs_offchip_param);
1789 }
1790 }
1791
1792 if (descriptor_bo) {
1793 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1794 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1795 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1796 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1797 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1798 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1799
1800 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1801
1802 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1803 radeon_set_sh_reg_seq(cs, regs[i], 2);
1804 radeon_emit(cs, va);
1805 radeon_emit(cs, va >> 32);
1806 }
1807 }
1808
1809 if (compute_scratch_bo) {
1810 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1811 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1812 S_008F04_SWIZZLE_ENABLE(1);
1813
1814 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1815
1816 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1817 radeon_emit(cs, scratch_va);
1818 radeon_emit(cs, rsrc1);
1819 }
1820
1821 if (i == 0) {
1822 si_cs_emit_cache_flush(cs,
1823 false,
1824 queue->device->physical_device->rad_info.chip_class,
1825 NULL, 0,
1826 queue->queue_family_index == RING_COMPUTE &&
1827 queue->device->physical_device->rad_info.chip_class >= CIK,
1828 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
1829 RADV_CMD_FLAG_INV_ICACHE |
1830 RADV_CMD_FLAG_INV_SMEM_L1 |
1831 RADV_CMD_FLAG_INV_VMEM_L1 |
1832 RADV_CMD_FLAG_INV_GLOBAL_L2);
1833 } else if (i == 1) {
1834 si_cs_emit_cache_flush(cs,
1835 false,
1836 queue->device->physical_device->rad_info.chip_class,
1837 NULL, 0,
1838 queue->queue_family_index == RING_COMPUTE &&
1839 queue->device->physical_device->rad_info.chip_class >= CIK,
1840 RADV_CMD_FLAG_INV_ICACHE |
1841 RADV_CMD_FLAG_INV_SMEM_L1 |
1842 RADV_CMD_FLAG_INV_VMEM_L1 |
1843 RADV_CMD_FLAG_INV_GLOBAL_L2);
1844 }
1845
1846 if (!queue->device->ws->cs_finalize(cs))
1847 goto fail;
1848 }
1849
1850 if (queue->initial_full_flush_preamble_cs)
1851 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1852
1853 if (queue->initial_preamble_cs)
1854 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1855
1856 if (queue->continue_preamble_cs)
1857 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1858
1859 queue->initial_full_flush_preamble_cs = dest_cs[0];
1860 queue->initial_preamble_cs = dest_cs[1];
1861 queue->continue_preamble_cs = dest_cs[2];
1862
1863 if (scratch_bo != queue->scratch_bo) {
1864 if (queue->scratch_bo)
1865 queue->device->ws->buffer_destroy(queue->scratch_bo);
1866 queue->scratch_bo = scratch_bo;
1867 queue->scratch_size = scratch_size;
1868 }
1869
1870 if (compute_scratch_bo != queue->compute_scratch_bo) {
1871 if (queue->compute_scratch_bo)
1872 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1873 queue->compute_scratch_bo = compute_scratch_bo;
1874 queue->compute_scratch_size = compute_scratch_size;
1875 }
1876
1877 if (esgs_ring_bo != queue->esgs_ring_bo) {
1878 if (queue->esgs_ring_bo)
1879 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1880 queue->esgs_ring_bo = esgs_ring_bo;
1881 queue->esgs_ring_size = esgs_ring_size;
1882 }
1883
1884 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1885 if (queue->gsvs_ring_bo)
1886 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1887 queue->gsvs_ring_bo = gsvs_ring_bo;
1888 queue->gsvs_ring_size = gsvs_ring_size;
1889 }
1890
1891 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1892 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1893 }
1894
1895 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1896 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1897 queue->has_tess_rings = true;
1898 }
1899
1900 if (descriptor_bo != queue->descriptor_bo) {
1901 if (queue->descriptor_bo)
1902 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1903
1904 queue->descriptor_bo = descriptor_bo;
1905 }
1906
1907 if (add_sample_positions)
1908 queue->has_sample_positions = true;
1909
1910 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
1911 *initial_preamble_cs = queue->initial_preamble_cs;
1912 *continue_preamble_cs = queue->continue_preamble_cs;
1913 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1914 *continue_preamble_cs = NULL;
1915 return VK_SUCCESS;
1916 fail:
1917 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1918 if (dest_cs[i])
1919 queue->device->ws->cs_destroy(dest_cs[i]);
1920 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1921 queue->device->ws->buffer_destroy(descriptor_bo);
1922 if (scratch_bo && scratch_bo != queue->scratch_bo)
1923 queue->device->ws->buffer_destroy(scratch_bo);
1924 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1925 queue->device->ws->buffer_destroy(compute_scratch_bo);
1926 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1927 queue->device->ws->buffer_destroy(esgs_ring_bo);
1928 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1929 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1930 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1931 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1932 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1933 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1934 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1935 }
1936
1937 static VkResult radv_alloc_sem_counts(struct radv_winsys_sem_counts *counts,
1938 int num_sems,
1939 const VkSemaphore *sems,
1940 bool reset_temp)
1941 {
1942 int syncobj_idx = 0, sem_idx = 0;
1943
1944 if (num_sems == 0)
1945 return VK_SUCCESS;
1946 for (uint32_t i = 0; i < num_sems; i++) {
1947 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1948
1949 if (sem->temp_syncobj || sem->syncobj)
1950 counts->syncobj_count++;
1951 else
1952 counts->sem_count++;
1953 }
1954
1955 if (counts->syncobj_count) {
1956 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
1957 if (!counts->syncobj)
1958 return VK_ERROR_OUT_OF_HOST_MEMORY;
1959 }
1960
1961 if (counts->sem_count) {
1962 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
1963 if (!counts->sem) {
1964 free(counts->syncobj);
1965 return VK_ERROR_OUT_OF_HOST_MEMORY;
1966 }
1967 }
1968
1969 for (uint32_t i = 0; i < num_sems; i++) {
1970 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
1971
1972 if (sem->temp_syncobj) {
1973 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
1974 if (reset_temp) {
1975 /* after we wait on a temp import - drop it */
1976 sem->temp_syncobj = 0;
1977 }
1978 }
1979 else if (sem->syncobj)
1980 counts->syncobj[syncobj_idx++] = sem->syncobj;
1981 else {
1982 assert(sem->sem);
1983 counts->sem[sem_idx++] = sem->sem;
1984 }
1985 }
1986
1987 return VK_SUCCESS;
1988 }
1989
1990 void radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
1991 {
1992 free(sem_info->wait.syncobj);
1993 free(sem_info->wait.sem);
1994 free(sem_info->signal.syncobj);
1995 free(sem_info->signal.sem);
1996 }
1997
1998 VkResult radv_alloc_sem_info(struct radv_winsys_sem_info *sem_info,
1999 int num_wait_sems,
2000 const VkSemaphore *wait_sems,
2001 int num_signal_sems,
2002 const VkSemaphore *signal_sems)
2003 {
2004 VkResult ret;
2005 memset(sem_info, 0, sizeof(*sem_info));
2006
2007 ret = radv_alloc_sem_counts(&sem_info->wait, num_wait_sems, wait_sems, true);
2008 if (ret)
2009 return ret;
2010 ret = radv_alloc_sem_counts(&sem_info->signal, num_signal_sems, signal_sems, false);
2011 if (ret)
2012 radv_free_sem_info(sem_info);
2013
2014 /* caller can override these */
2015 sem_info->cs_emit_wait = true;
2016 sem_info->cs_emit_signal = true;
2017 return ret;
2018 }
2019
2020 VkResult radv_QueueSubmit(
2021 VkQueue _queue,
2022 uint32_t submitCount,
2023 const VkSubmitInfo* pSubmits,
2024 VkFence _fence)
2025 {
2026 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2027 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2028 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2029 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2030 int ret;
2031 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2032 uint32_t scratch_size = 0;
2033 uint32_t compute_scratch_size = 0;
2034 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2035 struct radeon_winsys_cs *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2036 VkResult result;
2037 bool fence_emitted = false;
2038 bool tess_rings_needed = false;
2039 bool sample_positions_needed = false;
2040
2041 /* Do this first so failing to allocate scratch buffers can't result in
2042 * partially executed submissions. */
2043 for (uint32_t i = 0; i < submitCount; i++) {
2044 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2045 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2046 pSubmits[i].pCommandBuffers[j]);
2047
2048 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2049 compute_scratch_size = MAX2(compute_scratch_size,
2050 cmd_buffer->compute_scratch_size_needed);
2051 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2052 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2053 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2054 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2055 }
2056 }
2057
2058 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2059 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2060 sample_positions_needed, &initial_flush_preamble_cs,
2061 &initial_preamble_cs, &continue_preamble_cs);
2062 if (result != VK_SUCCESS)
2063 return result;
2064
2065 for (uint32_t i = 0; i < submitCount; i++) {
2066 struct radeon_winsys_cs **cs_array;
2067 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2068 bool can_patch = true;
2069 uint32_t advance;
2070 struct radv_winsys_sem_info sem_info;
2071
2072 result = radv_alloc_sem_info(&sem_info,
2073 pSubmits[i].waitSemaphoreCount,
2074 pSubmits[i].pWaitSemaphores,
2075 pSubmits[i].signalSemaphoreCount,
2076 pSubmits[i].pSignalSemaphores);
2077 if (result != VK_SUCCESS)
2078 return result;
2079
2080 if (!pSubmits[i].commandBufferCount) {
2081 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2082 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2083 &queue->device->empty_cs[queue->queue_family_index],
2084 1, NULL, NULL,
2085 &sem_info,
2086 false, base_fence);
2087 if (ret) {
2088 radv_loge("failed to submit CS %d\n", i);
2089 abort();
2090 }
2091 fence_emitted = true;
2092 }
2093 radv_free_sem_info(&sem_info);
2094 continue;
2095 }
2096
2097 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
2098 (pSubmits[i].commandBufferCount));
2099
2100 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2101 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2102 pSubmits[i].pCommandBuffers[j]);
2103 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2104
2105 cs_array[j] = cmd_buffer->cs;
2106 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2107 can_patch = false;
2108 }
2109
2110 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2111 struct radeon_winsys_cs *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2112 advance = MIN2(max_cs_submission,
2113 pSubmits[i].commandBufferCount - j);
2114
2115 if (queue->device->trace_bo)
2116 *queue->device->trace_id_ptr = 0;
2117
2118 sem_info.cs_emit_wait = j == 0;
2119 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2120
2121 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2122 advance, initial_preamble, continue_preamble_cs,
2123 &sem_info,
2124 can_patch, base_fence);
2125
2126 if (ret) {
2127 radv_loge("failed to submit CS %d\n", i);
2128 abort();
2129 }
2130 fence_emitted = true;
2131 if (queue->device->trace_bo) {
2132 radv_check_gpu_hangs(queue, cs_array[j]);
2133 }
2134 }
2135
2136 radv_free_sem_info(&sem_info);
2137 free(cs_array);
2138 }
2139
2140 if (fence) {
2141 if (!fence_emitted) {
2142 struct radv_winsys_sem_info sem_info = {0};
2143 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2144 &queue->device->empty_cs[queue->queue_family_index],
2145 1, NULL, NULL, &sem_info,
2146 false, base_fence);
2147 }
2148 fence->submitted = true;
2149 }
2150
2151 return VK_SUCCESS;
2152 }
2153
2154 VkResult radv_QueueWaitIdle(
2155 VkQueue _queue)
2156 {
2157 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2158
2159 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2160 radv_queue_family_to_ring(queue->queue_family_index),
2161 queue->queue_idx);
2162 return VK_SUCCESS;
2163 }
2164
2165 VkResult radv_DeviceWaitIdle(
2166 VkDevice _device)
2167 {
2168 RADV_FROM_HANDLE(radv_device, device, _device);
2169
2170 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2171 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2172 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2173 }
2174 }
2175 return VK_SUCCESS;
2176 }
2177
2178 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2179 VkInstance instance,
2180 const char* pName)
2181 {
2182 return radv_lookup_entrypoint(pName);
2183 }
2184
2185 /* The loader wants us to expose a second GetInstanceProcAddr function
2186 * to work around certain LD_PRELOAD issues seen in apps.
2187 */
2188 PUBLIC
2189 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2190 VkInstance instance,
2191 const char* pName);
2192
2193 PUBLIC
2194 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2195 VkInstance instance,
2196 const char* pName)
2197 {
2198 return radv_GetInstanceProcAddr(instance, pName);
2199 }
2200
2201 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2202 VkDevice device,
2203 const char* pName)
2204 {
2205 return radv_lookup_entrypoint(pName);
2206 }
2207
2208 bool radv_get_memory_fd(struct radv_device *device,
2209 struct radv_device_memory *memory,
2210 int *pFD)
2211 {
2212 struct radeon_bo_metadata metadata;
2213
2214 if (memory->image) {
2215 radv_init_metadata(device, memory->image, &metadata);
2216 device->ws->buffer_set_metadata(memory->bo, &metadata);
2217 }
2218
2219 return device->ws->buffer_get_fd(device->ws, memory->bo,
2220 pFD);
2221 }
2222
2223 VkResult radv_AllocateMemory(
2224 VkDevice _device,
2225 const VkMemoryAllocateInfo* pAllocateInfo,
2226 const VkAllocationCallbacks* pAllocator,
2227 VkDeviceMemory* pMem)
2228 {
2229 RADV_FROM_HANDLE(radv_device, device, _device);
2230 struct radv_device_memory *mem;
2231 VkResult result;
2232 enum radeon_bo_domain domain;
2233 uint32_t flags = 0;
2234
2235 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2236
2237 if (pAllocateInfo->allocationSize == 0) {
2238 /* Apparently, this is allowed */
2239 *pMem = VK_NULL_HANDLE;
2240 return VK_SUCCESS;
2241 }
2242
2243 const VkImportMemoryFdInfoKHR *import_info =
2244 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2245 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2246 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2247
2248 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2249 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2250 if (mem == NULL)
2251 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2252
2253 if (dedicate_info) {
2254 mem->image = radv_image_from_handle(dedicate_info->image);
2255 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2256 } else {
2257 mem->image = NULL;
2258 mem->buffer = NULL;
2259 }
2260
2261 if (import_info) {
2262 assert(import_info->handleType ==
2263 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2264 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2265 NULL, NULL);
2266 if (!mem->bo) {
2267 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2268 goto fail;
2269 } else {
2270 close(import_info->fd);
2271 goto out_success;
2272 }
2273 }
2274
2275 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2276 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2277 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2278 domain = RADEON_DOMAIN_GTT;
2279 else
2280 domain = RADEON_DOMAIN_VRAM;
2281
2282 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2283 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2284 else
2285 flags |= RADEON_FLAG_CPU_ACCESS;
2286
2287 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2288 flags |= RADEON_FLAG_GTT_WC;
2289
2290 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2291 domain, flags);
2292
2293 if (!mem->bo) {
2294 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2295 goto fail;
2296 }
2297 mem->type_index = pAllocateInfo->memoryTypeIndex;
2298 out_success:
2299 *pMem = radv_device_memory_to_handle(mem);
2300
2301 return VK_SUCCESS;
2302
2303 fail:
2304 vk_free2(&device->alloc, pAllocator, mem);
2305
2306 return result;
2307 }
2308
2309 void radv_FreeMemory(
2310 VkDevice _device,
2311 VkDeviceMemory _mem,
2312 const VkAllocationCallbacks* pAllocator)
2313 {
2314 RADV_FROM_HANDLE(radv_device, device, _device);
2315 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2316
2317 if (mem == NULL)
2318 return;
2319
2320 device->ws->buffer_destroy(mem->bo);
2321 mem->bo = NULL;
2322
2323 vk_free2(&device->alloc, pAllocator, mem);
2324 }
2325
2326 VkResult radv_MapMemory(
2327 VkDevice _device,
2328 VkDeviceMemory _memory,
2329 VkDeviceSize offset,
2330 VkDeviceSize size,
2331 VkMemoryMapFlags flags,
2332 void** ppData)
2333 {
2334 RADV_FROM_HANDLE(radv_device, device, _device);
2335 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2336
2337 if (mem == NULL) {
2338 *ppData = NULL;
2339 return VK_SUCCESS;
2340 }
2341
2342 *ppData = device->ws->buffer_map(mem->bo);
2343 if (*ppData) {
2344 *ppData += offset;
2345 return VK_SUCCESS;
2346 }
2347
2348 return VK_ERROR_MEMORY_MAP_FAILED;
2349 }
2350
2351 void radv_UnmapMemory(
2352 VkDevice _device,
2353 VkDeviceMemory _memory)
2354 {
2355 RADV_FROM_HANDLE(radv_device, device, _device);
2356 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2357
2358 if (mem == NULL)
2359 return;
2360
2361 device->ws->buffer_unmap(mem->bo);
2362 }
2363
2364 VkResult radv_FlushMappedMemoryRanges(
2365 VkDevice _device,
2366 uint32_t memoryRangeCount,
2367 const VkMappedMemoryRange* pMemoryRanges)
2368 {
2369 return VK_SUCCESS;
2370 }
2371
2372 VkResult radv_InvalidateMappedMemoryRanges(
2373 VkDevice _device,
2374 uint32_t memoryRangeCount,
2375 const VkMappedMemoryRange* pMemoryRanges)
2376 {
2377 return VK_SUCCESS;
2378 }
2379
2380 void radv_GetBufferMemoryRequirements(
2381 VkDevice device,
2382 VkBuffer _buffer,
2383 VkMemoryRequirements* pMemoryRequirements)
2384 {
2385 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2386
2387 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2388
2389 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2390 pMemoryRequirements->alignment = 4096;
2391 else
2392 pMemoryRequirements->alignment = 16;
2393
2394 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2395 }
2396
2397 void radv_GetBufferMemoryRequirements2KHR(
2398 VkDevice device,
2399 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2400 VkMemoryRequirements2KHR* pMemoryRequirements)
2401 {
2402 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2403 &pMemoryRequirements->memoryRequirements);
2404
2405 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2406 switch (ext->sType) {
2407 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2408 VkMemoryDedicatedRequirementsKHR *req =
2409 (VkMemoryDedicatedRequirementsKHR *) ext;
2410 req->requiresDedicatedAllocation = false;
2411 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2412 break;
2413 }
2414 default:
2415 break;
2416 }
2417 }
2418 }
2419
2420 void radv_GetImageMemoryRequirements(
2421 VkDevice device,
2422 VkImage _image,
2423 VkMemoryRequirements* pMemoryRequirements)
2424 {
2425 RADV_FROM_HANDLE(radv_image, image, _image);
2426
2427 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2428
2429 pMemoryRequirements->size = image->size;
2430 pMemoryRequirements->alignment = image->alignment;
2431 }
2432
2433 void radv_GetImageMemoryRequirements2KHR(
2434 VkDevice device,
2435 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2436 VkMemoryRequirements2KHR* pMemoryRequirements)
2437 {
2438 radv_GetImageMemoryRequirements(device, pInfo->image,
2439 &pMemoryRequirements->memoryRequirements);
2440
2441 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
2442
2443 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
2444 switch (ext->sType) {
2445 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
2446 VkMemoryDedicatedRequirementsKHR *req =
2447 (VkMemoryDedicatedRequirementsKHR *) ext;
2448 req->requiresDedicatedAllocation = image->shareable;
2449 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
2450 break;
2451 }
2452 default:
2453 break;
2454 }
2455 }
2456 }
2457
2458 void radv_GetImageSparseMemoryRequirements(
2459 VkDevice device,
2460 VkImage image,
2461 uint32_t* pSparseMemoryRequirementCount,
2462 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2463 {
2464 stub();
2465 }
2466
2467 void radv_GetImageSparseMemoryRequirements2KHR(
2468 VkDevice device,
2469 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2470 uint32_t* pSparseMemoryRequirementCount,
2471 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2472 {
2473 stub();
2474 }
2475
2476 void radv_GetDeviceMemoryCommitment(
2477 VkDevice device,
2478 VkDeviceMemory memory,
2479 VkDeviceSize* pCommittedMemoryInBytes)
2480 {
2481 *pCommittedMemoryInBytes = 0;
2482 }
2483
2484 VkResult radv_BindBufferMemory(
2485 VkDevice device,
2486 VkBuffer _buffer,
2487 VkDeviceMemory _memory,
2488 VkDeviceSize memoryOffset)
2489 {
2490 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2491 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2492
2493 if (mem) {
2494 buffer->bo = mem->bo;
2495 buffer->offset = memoryOffset;
2496 } else {
2497 buffer->bo = NULL;
2498 buffer->offset = 0;
2499 }
2500
2501 return VK_SUCCESS;
2502 }
2503
2504 VkResult radv_BindImageMemory(
2505 VkDevice device,
2506 VkImage _image,
2507 VkDeviceMemory _memory,
2508 VkDeviceSize memoryOffset)
2509 {
2510 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2511 RADV_FROM_HANDLE(radv_image, image, _image);
2512
2513 if (mem) {
2514 image->bo = mem->bo;
2515 image->offset = memoryOffset;
2516 } else {
2517 image->bo = NULL;
2518 image->offset = 0;
2519 }
2520
2521 return VK_SUCCESS;
2522 }
2523
2524
2525 static void
2526 radv_sparse_buffer_bind_memory(struct radv_device *device,
2527 const VkSparseBufferMemoryBindInfo *bind)
2528 {
2529 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2530
2531 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2532 struct radv_device_memory *mem = NULL;
2533
2534 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2535 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2536
2537 device->ws->buffer_virtual_bind(buffer->bo,
2538 bind->pBinds[i].resourceOffset,
2539 bind->pBinds[i].size,
2540 mem ? mem->bo : NULL,
2541 bind->pBinds[i].memoryOffset);
2542 }
2543 }
2544
2545 static void
2546 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2547 const VkSparseImageOpaqueMemoryBindInfo *bind)
2548 {
2549 RADV_FROM_HANDLE(radv_image, image, bind->image);
2550
2551 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2552 struct radv_device_memory *mem = NULL;
2553
2554 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2555 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2556
2557 device->ws->buffer_virtual_bind(image->bo,
2558 bind->pBinds[i].resourceOffset,
2559 bind->pBinds[i].size,
2560 mem ? mem->bo : NULL,
2561 bind->pBinds[i].memoryOffset);
2562 }
2563 }
2564
2565 VkResult radv_QueueBindSparse(
2566 VkQueue _queue,
2567 uint32_t bindInfoCount,
2568 const VkBindSparseInfo* pBindInfo,
2569 VkFence _fence)
2570 {
2571 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2572 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2573 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2574 bool fence_emitted = false;
2575
2576 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2577 struct radv_winsys_sem_info sem_info;
2578 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2579 radv_sparse_buffer_bind_memory(queue->device,
2580 pBindInfo[i].pBufferBinds + j);
2581 }
2582
2583 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2584 radv_sparse_image_opaque_bind_memory(queue->device,
2585 pBindInfo[i].pImageOpaqueBinds + j);
2586 }
2587
2588 VkResult result;
2589 result = radv_alloc_sem_info(&sem_info,
2590 pBindInfo[i].waitSemaphoreCount,
2591 pBindInfo[i].pWaitSemaphores,
2592 pBindInfo[i].signalSemaphoreCount,
2593 pBindInfo[i].pSignalSemaphores);
2594 if (result != VK_SUCCESS)
2595 return result;
2596
2597 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2598 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2599 &queue->device->empty_cs[queue->queue_family_index],
2600 1, NULL, NULL,
2601 &sem_info,
2602 false, base_fence);
2603 fence_emitted = true;
2604 if (fence)
2605 fence->submitted = true;
2606 }
2607
2608 radv_free_sem_info(&sem_info);
2609
2610 }
2611
2612 if (fence && !fence_emitted) {
2613 fence->signalled = true;
2614 }
2615
2616 return VK_SUCCESS;
2617 }
2618
2619 VkResult radv_CreateFence(
2620 VkDevice _device,
2621 const VkFenceCreateInfo* pCreateInfo,
2622 const VkAllocationCallbacks* pAllocator,
2623 VkFence* pFence)
2624 {
2625 RADV_FROM_HANDLE(radv_device, device, _device);
2626 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2627 sizeof(*fence), 8,
2628 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2629
2630 if (!fence)
2631 return VK_ERROR_OUT_OF_HOST_MEMORY;
2632
2633 memset(fence, 0, sizeof(*fence));
2634 fence->submitted = false;
2635 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2636 fence->fence = device->ws->create_fence();
2637 if (!fence->fence) {
2638 vk_free2(&device->alloc, pAllocator, fence);
2639 return VK_ERROR_OUT_OF_HOST_MEMORY;
2640 }
2641
2642 *pFence = radv_fence_to_handle(fence);
2643
2644 return VK_SUCCESS;
2645 }
2646
2647 void radv_DestroyFence(
2648 VkDevice _device,
2649 VkFence _fence,
2650 const VkAllocationCallbacks* pAllocator)
2651 {
2652 RADV_FROM_HANDLE(radv_device, device, _device);
2653 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2654
2655 if (!fence)
2656 return;
2657 device->ws->destroy_fence(fence->fence);
2658 vk_free2(&device->alloc, pAllocator, fence);
2659 }
2660
2661 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2662 {
2663 uint64_t current_time;
2664 struct timespec tv;
2665
2666 clock_gettime(CLOCK_MONOTONIC, &tv);
2667 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2668
2669 timeout = MIN2(UINT64_MAX - current_time, timeout);
2670
2671 return current_time + timeout;
2672 }
2673
2674 VkResult radv_WaitForFences(
2675 VkDevice _device,
2676 uint32_t fenceCount,
2677 const VkFence* pFences,
2678 VkBool32 waitAll,
2679 uint64_t timeout)
2680 {
2681 RADV_FROM_HANDLE(radv_device, device, _device);
2682 timeout = radv_get_absolute_timeout(timeout);
2683
2684 if (!waitAll && fenceCount > 1) {
2685 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2686 }
2687
2688 for (uint32_t i = 0; i < fenceCount; ++i) {
2689 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2690 bool expired = false;
2691
2692 if (fence->signalled)
2693 continue;
2694
2695 if (!fence->submitted)
2696 return VK_TIMEOUT;
2697
2698 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2699 if (!expired)
2700 return VK_TIMEOUT;
2701
2702 fence->signalled = true;
2703 }
2704
2705 return VK_SUCCESS;
2706 }
2707
2708 VkResult radv_ResetFences(VkDevice device,
2709 uint32_t fenceCount,
2710 const VkFence *pFences)
2711 {
2712 for (unsigned i = 0; i < fenceCount; ++i) {
2713 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2714 fence->submitted = fence->signalled = false;
2715 }
2716
2717 return VK_SUCCESS;
2718 }
2719
2720 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2721 {
2722 RADV_FROM_HANDLE(radv_device, device, _device);
2723 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2724
2725 if (fence->signalled)
2726 return VK_SUCCESS;
2727 if (!fence->submitted)
2728 return VK_NOT_READY;
2729
2730 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2731 return VK_NOT_READY;
2732
2733 return VK_SUCCESS;
2734 }
2735
2736
2737 // Queue semaphore functions
2738
2739 VkResult radv_CreateSemaphore(
2740 VkDevice _device,
2741 const VkSemaphoreCreateInfo* pCreateInfo,
2742 const VkAllocationCallbacks* pAllocator,
2743 VkSemaphore* pSemaphore)
2744 {
2745 RADV_FROM_HANDLE(radv_device, device, _device);
2746 const VkExportSemaphoreCreateInfoKHR *export =
2747 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
2748 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
2749 export ? export->handleTypes : 0;
2750
2751 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
2752 sizeof(*sem), 8,
2753 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2754 if (!sem)
2755 return VK_ERROR_OUT_OF_HOST_MEMORY;
2756
2757 sem->temp_syncobj = 0;
2758 /* create a syncobject if we are going to export this semaphore */
2759 if (handleTypes) {
2760 assert (device->physical_device->rad_info.has_syncobj);
2761 assert (handleTypes == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
2762 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
2763 if (ret) {
2764 vk_free2(&device->alloc, pAllocator, sem);
2765 return VK_ERROR_OUT_OF_HOST_MEMORY;
2766 }
2767 sem->sem = NULL;
2768 } else {
2769 sem->sem = device->ws->create_sem(device->ws);
2770 if (!sem->sem) {
2771 vk_free2(&device->alloc, pAllocator, sem);
2772 return VK_ERROR_OUT_OF_HOST_MEMORY;
2773 }
2774 sem->syncobj = 0;
2775 }
2776
2777 *pSemaphore = radv_semaphore_to_handle(sem);
2778 return VK_SUCCESS;
2779 }
2780
2781 void radv_DestroySemaphore(
2782 VkDevice _device,
2783 VkSemaphore _semaphore,
2784 const VkAllocationCallbacks* pAllocator)
2785 {
2786 RADV_FROM_HANDLE(radv_device, device, _device);
2787 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
2788 if (!_semaphore)
2789 return;
2790
2791 if (sem->syncobj)
2792 device->ws->destroy_syncobj(device->ws, sem->syncobj);
2793 else
2794 device->ws->destroy_sem(sem->sem);
2795 vk_free2(&device->alloc, pAllocator, sem);
2796 }
2797
2798 VkResult radv_CreateEvent(
2799 VkDevice _device,
2800 const VkEventCreateInfo* pCreateInfo,
2801 const VkAllocationCallbacks* pAllocator,
2802 VkEvent* pEvent)
2803 {
2804 RADV_FROM_HANDLE(radv_device, device, _device);
2805 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2806 sizeof(*event), 8,
2807 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2808
2809 if (!event)
2810 return VK_ERROR_OUT_OF_HOST_MEMORY;
2811
2812 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2813 RADEON_DOMAIN_GTT,
2814 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS);
2815 if (!event->bo) {
2816 vk_free2(&device->alloc, pAllocator, event);
2817 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2818 }
2819
2820 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2821
2822 *pEvent = radv_event_to_handle(event);
2823
2824 return VK_SUCCESS;
2825 }
2826
2827 void radv_DestroyEvent(
2828 VkDevice _device,
2829 VkEvent _event,
2830 const VkAllocationCallbacks* pAllocator)
2831 {
2832 RADV_FROM_HANDLE(radv_device, device, _device);
2833 RADV_FROM_HANDLE(radv_event, event, _event);
2834
2835 if (!event)
2836 return;
2837 device->ws->buffer_destroy(event->bo);
2838 vk_free2(&device->alloc, pAllocator, event);
2839 }
2840
2841 VkResult radv_GetEventStatus(
2842 VkDevice _device,
2843 VkEvent _event)
2844 {
2845 RADV_FROM_HANDLE(radv_event, event, _event);
2846
2847 if (*event->map == 1)
2848 return VK_EVENT_SET;
2849 return VK_EVENT_RESET;
2850 }
2851
2852 VkResult radv_SetEvent(
2853 VkDevice _device,
2854 VkEvent _event)
2855 {
2856 RADV_FROM_HANDLE(radv_event, event, _event);
2857 *event->map = 1;
2858
2859 return VK_SUCCESS;
2860 }
2861
2862 VkResult radv_ResetEvent(
2863 VkDevice _device,
2864 VkEvent _event)
2865 {
2866 RADV_FROM_HANDLE(radv_event, event, _event);
2867 *event->map = 0;
2868
2869 return VK_SUCCESS;
2870 }
2871
2872 VkResult radv_CreateBuffer(
2873 VkDevice _device,
2874 const VkBufferCreateInfo* pCreateInfo,
2875 const VkAllocationCallbacks* pAllocator,
2876 VkBuffer* pBuffer)
2877 {
2878 RADV_FROM_HANDLE(radv_device, device, _device);
2879 struct radv_buffer *buffer;
2880
2881 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2882
2883 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2884 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2885 if (buffer == NULL)
2886 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2887
2888 buffer->size = pCreateInfo->size;
2889 buffer->usage = pCreateInfo->usage;
2890 buffer->bo = NULL;
2891 buffer->offset = 0;
2892 buffer->flags = pCreateInfo->flags;
2893
2894 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2895 buffer->bo = device->ws->buffer_create(device->ws,
2896 align64(buffer->size, 4096),
2897 4096, 0, RADEON_FLAG_VIRTUAL);
2898 if (!buffer->bo) {
2899 vk_free2(&device->alloc, pAllocator, buffer);
2900 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2901 }
2902 }
2903
2904 *pBuffer = radv_buffer_to_handle(buffer);
2905
2906 return VK_SUCCESS;
2907 }
2908
2909 void radv_DestroyBuffer(
2910 VkDevice _device,
2911 VkBuffer _buffer,
2912 const VkAllocationCallbacks* pAllocator)
2913 {
2914 RADV_FROM_HANDLE(radv_device, device, _device);
2915 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2916
2917 if (!buffer)
2918 return;
2919
2920 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2921 device->ws->buffer_destroy(buffer->bo);
2922
2923 vk_free2(&device->alloc, pAllocator, buffer);
2924 }
2925
2926 static inline unsigned
2927 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2928 {
2929 if (stencil)
2930 return image->surface.u.legacy.stencil_tiling_index[level];
2931 else
2932 return image->surface.u.legacy.tiling_index[level];
2933 }
2934
2935 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2936 {
2937 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2938 }
2939
2940 static void
2941 radv_initialise_color_surface(struct radv_device *device,
2942 struct radv_color_buffer_info *cb,
2943 struct radv_image_view *iview)
2944 {
2945 const struct vk_format_description *desc;
2946 unsigned ntype, format, swap, endian;
2947 unsigned blend_clamp = 0, blend_bypass = 0;
2948 uint64_t va;
2949 const struct radeon_surf *surf = &iview->image->surface;
2950
2951 desc = vk_format_description(iview->vk_format);
2952
2953 memset(cb, 0, sizeof(*cb));
2954
2955 /* Intensity is implemented as Red, so treat it that way. */
2956 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2957
2958 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2959
2960 cb->cb_color_base = va >> 8;
2961
2962 if (device->physical_device->rad_info.chip_class >= GFX9) {
2963 struct gfx9_surf_meta_flags meta;
2964 if (iview->image->dcc_offset)
2965 meta = iview->image->surface.u.gfx9.dcc;
2966 else
2967 meta = iview->image->surface.u.gfx9.cmask;
2968
2969 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2970 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2971 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2972 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2973
2974 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
2975 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2976 } else {
2977 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2978 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2979
2980 cb->cb_color_base += level_info->offset >> 8;
2981 if (level_info->mode == RADEON_SURF_MODE_2D)
2982 cb->cb_color_base |= iview->image->surface.tile_swizzle;
2983
2984 pitch_tile_max = level_info->nblk_x / 8 - 1;
2985 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2986 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2987
2988 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2989 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2990 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2991
2992 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2993 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2994
2995 if (iview->image->fmask.size) {
2996 if (device->physical_device->rad_info.chip_class >= CIK)
2997 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2998 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2999 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3000 } else {
3001 /* This must be set for fast clear to work without FMASK. */
3002 if (device->physical_device->rad_info.chip_class >= CIK)
3003 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3004 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3005 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3006 }
3007 }
3008
3009 /* CMASK variables */
3010 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3011 va += iview->image->cmask.offset;
3012 cb->cb_color_cmask = va >> 8;
3013
3014 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3015 va += iview->image->dcc_offset;
3016 cb->cb_dcc_base = va >> 8;
3017 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3018
3019 uint32_t max_slice = radv_surface_layer_count(iview);
3020 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3021 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
3022
3023 if (iview->image->info.samples > 1) {
3024 unsigned log_samples = util_logbase2(iview->image->info.samples);
3025
3026 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3027 S_028C74_NUM_FRAGMENTS(log_samples);
3028 }
3029
3030 if (iview->image->fmask.size) {
3031 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3032 cb->cb_color_fmask = va >> 8;
3033 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3034 } else {
3035 cb->cb_color_fmask = cb->cb_color_base;
3036 }
3037
3038 ntype = radv_translate_color_numformat(iview->vk_format,
3039 desc,
3040 vk_format_get_first_non_void_channel(iview->vk_format));
3041 format = radv_translate_colorformat(iview->vk_format);
3042 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3043 radv_finishme("Illegal color\n");
3044 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3045 endian = radv_colorformat_endian_swap(format);
3046
3047 /* blend clamp should be set for all NORM/SRGB types */
3048 if (ntype == V_028C70_NUMBER_UNORM ||
3049 ntype == V_028C70_NUMBER_SNORM ||
3050 ntype == V_028C70_NUMBER_SRGB)
3051 blend_clamp = 1;
3052
3053 /* set blend bypass according to docs if SINT/UINT or
3054 8/24 COLOR variants */
3055 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3056 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3057 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3058 blend_clamp = 0;
3059 blend_bypass = 1;
3060 }
3061 #if 0
3062 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3063 (format == V_028C70_COLOR_8 ||
3064 format == V_028C70_COLOR_8_8 ||
3065 format == V_028C70_COLOR_8_8_8_8))
3066 ->color_is_int8 = true;
3067 #endif
3068 cb->cb_color_info = S_028C70_FORMAT(format) |
3069 S_028C70_COMP_SWAP(swap) |
3070 S_028C70_BLEND_CLAMP(blend_clamp) |
3071 S_028C70_BLEND_BYPASS(blend_bypass) |
3072 S_028C70_SIMPLE_FLOAT(1) |
3073 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3074 ntype != V_028C70_NUMBER_SNORM &&
3075 ntype != V_028C70_NUMBER_SRGB &&
3076 format != V_028C70_COLOR_8_24 &&
3077 format != V_028C70_COLOR_24_8) |
3078 S_028C70_NUMBER_TYPE(ntype) |
3079 S_028C70_ENDIAN(endian);
3080 if ((iview->image->info.samples > 1) && iview->image->fmask.size) {
3081 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3082 if (device->physical_device->rad_info.chip_class == SI) {
3083 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3084 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3085 }
3086 }
3087
3088 if (iview->image->cmask.size &&
3089 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3090 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3091
3092 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
3093 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3094
3095 if (device->physical_device->rad_info.chip_class >= VI) {
3096 unsigned max_uncompressed_block_size = 2;
3097 if (iview->image->info.samples > 1) {
3098 if (iview->image->surface.bpe == 1)
3099 max_uncompressed_block_size = 0;
3100 else if (iview->image->surface.bpe == 2)
3101 max_uncompressed_block_size = 1;
3102 }
3103
3104 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3105 S_028C78_INDEPENDENT_64B_BLOCKS(1);
3106 }
3107
3108 /* This must be set for fast clear to work without FMASK. */
3109 if (!iview->image->fmask.size &&
3110 device->physical_device->rad_info.chip_class == SI) {
3111 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3112 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3113 }
3114
3115 if (device->physical_device->rad_info.chip_class >= GFX9) {
3116 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3117 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3118
3119 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3120 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3121 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3122 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3123 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3124 S_028C68_MAX_MIP(iview->image->info.levels - 1);
3125
3126 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3127
3128 }
3129 }
3130
3131 static void
3132 radv_initialise_ds_surface(struct radv_device *device,
3133 struct radv_ds_buffer_info *ds,
3134 struct radv_image_view *iview)
3135 {
3136 unsigned level = iview->base_mip;
3137 unsigned format, stencil_format;
3138 uint64_t va, s_offs, z_offs;
3139 bool stencil_only = false;
3140 memset(ds, 0, sizeof(*ds));
3141 switch (iview->image->vk_format) {
3142 case VK_FORMAT_D24_UNORM_S8_UINT:
3143 case VK_FORMAT_X8_D24_UNORM_PACK32:
3144 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
3145 ds->offset_scale = 2.0f;
3146 break;
3147 case VK_FORMAT_D16_UNORM:
3148 case VK_FORMAT_D16_UNORM_S8_UINT:
3149 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
3150 ds->offset_scale = 4.0f;
3151 break;
3152 case VK_FORMAT_D32_SFLOAT:
3153 case VK_FORMAT_D32_SFLOAT_S8_UINT:
3154 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
3155 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
3156 ds->offset_scale = 1.0f;
3157 break;
3158 case VK_FORMAT_S8_UINT:
3159 stencil_only = true;
3160 break;
3161 default:
3162 break;
3163 }
3164
3165 format = radv_translate_dbformat(iview->image->vk_format);
3166 stencil_format = iview->image->surface.has_stencil ?
3167 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
3168
3169 uint32_t max_slice = radv_surface_layer_count(iview);
3170 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
3171 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
3172
3173 ds->db_htile_data_base = 0;
3174 ds->db_htile_surface = 0;
3175
3176 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
3177 s_offs = z_offs = va;
3178
3179 if (device->physical_device->rad_info.chip_class >= GFX9) {
3180 assert(iview->image->surface.u.gfx9.surf_offset == 0);
3181 s_offs += iview->image->surface.u.gfx9.stencil_offset;
3182
3183 ds->db_z_info = S_028038_FORMAT(format) |
3184 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
3185 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3186 S_028038_MAXMIP(iview->image->info.levels - 1);
3187 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
3188 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
3189
3190 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
3191 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
3192 ds->db_depth_view |= S_028008_MIPID(level);
3193
3194 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
3195 S_02801C_Y_MAX(iview->image->info.height - 1);
3196
3197 /* Only use HTILE for the first level. */
3198 if (iview->image->surface.htile_size && !level) {
3199 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
3200
3201 if (!iview->image->surface.has_stencil)
3202 /* Use all of the htile_buffer for depth if there's no stencil. */
3203 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
3204 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3205 iview->image->htile_offset;
3206 ds->db_htile_data_base = va >> 8;
3207 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
3208 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
3209 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
3210 }
3211 } else {
3212 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
3213
3214 if (stencil_only)
3215 level_info = &iview->image->surface.u.legacy.stencil_level[level];
3216
3217 z_offs += iview->image->surface.u.legacy.level[level].offset;
3218 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
3219
3220 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
3221 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
3222 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
3223
3224 if (iview->image->info.samples > 1)
3225 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
3226
3227 if (device->physical_device->rad_info.chip_class >= CIK) {
3228 struct radeon_info *info = &device->physical_device->rad_info;
3229 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
3230 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
3231 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
3232 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
3233 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
3234 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
3235
3236 if (stencil_only)
3237 tile_mode = stencil_tile_mode;
3238
3239 ds->db_depth_info |=
3240 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
3241 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
3242 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
3243 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
3244 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
3245 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
3246 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
3247 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
3248 } else {
3249 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
3250 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3251 tile_mode_index = si_tile_mode_index(iview->image, level, true);
3252 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
3253 if (stencil_only)
3254 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
3255 }
3256
3257 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
3258 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
3259 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
3260
3261 if (iview->image->surface.htile_size && !level) {
3262 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
3263
3264 if (!iview->image->surface.has_stencil)
3265 /* Use all of the htile_buffer for depth if there's no stencil. */
3266 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3267
3268 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3269 iview->image->htile_offset;
3270 ds->db_htile_data_base = va >> 8;
3271 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3272 }
3273 }
3274
3275 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3276 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3277 }
3278
3279 VkResult radv_CreateFramebuffer(
3280 VkDevice _device,
3281 const VkFramebufferCreateInfo* pCreateInfo,
3282 const VkAllocationCallbacks* pAllocator,
3283 VkFramebuffer* pFramebuffer)
3284 {
3285 RADV_FROM_HANDLE(radv_device, device, _device);
3286 struct radv_framebuffer *framebuffer;
3287
3288 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3289
3290 size_t size = sizeof(*framebuffer) +
3291 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3292 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3293 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3294 if (framebuffer == NULL)
3295 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3296
3297 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3298 framebuffer->width = pCreateInfo->width;
3299 framebuffer->height = pCreateInfo->height;
3300 framebuffer->layers = pCreateInfo->layers;
3301 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3302 VkImageView _iview = pCreateInfo->pAttachments[i];
3303 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3304 framebuffer->attachments[i].attachment = iview;
3305 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3306 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3307 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3308 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3309 }
3310 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3311 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3312 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3313 }
3314
3315 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3316 return VK_SUCCESS;
3317 }
3318
3319 void radv_DestroyFramebuffer(
3320 VkDevice _device,
3321 VkFramebuffer _fb,
3322 const VkAllocationCallbacks* pAllocator)
3323 {
3324 RADV_FROM_HANDLE(radv_device, device, _device);
3325 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3326
3327 if (!fb)
3328 return;
3329 vk_free2(&device->alloc, pAllocator, fb);
3330 }
3331
3332 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3333 {
3334 switch (address_mode) {
3335 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3336 return V_008F30_SQ_TEX_WRAP;
3337 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3338 return V_008F30_SQ_TEX_MIRROR;
3339 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3340 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3341 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3342 return V_008F30_SQ_TEX_CLAMP_BORDER;
3343 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3344 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3345 default:
3346 unreachable("illegal tex wrap mode");
3347 break;
3348 }
3349 }
3350
3351 static unsigned
3352 radv_tex_compare(VkCompareOp op)
3353 {
3354 switch (op) {
3355 case VK_COMPARE_OP_NEVER:
3356 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3357 case VK_COMPARE_OP_LESS:
3358 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3359 case VK_COMPARE_OP_EQUAL:
3360 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3361 case VK_COMPARE_OP_LESS_OR_EQUAL:
3362 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3363 case VK_COMPARE_OP_GREATER:
3364 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3365 case VK_COMPARE_OP_NOT_EQUAL:
3366 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3367 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3368 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3369 case VK_COMPARE_OP_ALWAYS:
3370 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3371 default:
3372 unreachable("illegal compare mode");
3373 break;
3374 }
3375 }
3376
3377 static unsigned
3378 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3379 {
3380 switch (filter) {
3381 case VK_FILTER_NEAREST:
3382 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3383 V_008F38_SQ_TEX_XY_FILTER_POINT);
3384 case VK_FILTER_LINEAR:
3385 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3386 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3387 case VK_FILTER_CUBIC_IMG:
3388 default:
3389 fprintf(stderr, "illegal texture filter");
3390 return 0;
3391 }
3392 }
3393
3394 static unsigned
3395 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3396 {
3397 switch (mode) {
3398 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3399 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3400 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3401 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3402 default:
3403 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3404 }
3405 }
3406
3407 static unsigned
3408 radv_tex_bordercolor(VkBorderColor bcolor)
3409 {
3410 switch (bcolor) {
3411 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3412 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3413 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3414 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3415 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3416 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3417 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3418 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3419 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3420 default:
3421 break;
3422 }
3423 return 0;
3424 }
3425
3426 static unsigned
3427 radv_tex_aniso_filter(unsigned filter)
3428 {
3429 if (filter < 2)
3430 return 0;
3431 if (filter < 4)
3432 return 1;
3433 if (filter < 8)
3434 return 2;
3435 if (filter < 16)
3436 return 3;
3437 return 4;
3438 }
3439
3440 static void
3441 radv_init_sampler(struct radv_device *device,
3442 struct radv_sampler *sampler,
3443 const VkSamplerCreateInfo *pCreateInfo)
3444 {
3445 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3446 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3447 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3448 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3449
3450 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3451 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3452 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3453 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3454 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3455 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3456 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3457 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3458 S_008F30_DISABLE_CUBE_WRAP(0) |
3459 S_008F30_COMPAT_MODE(is_vi));
3460 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3461 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3462 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3463 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3464 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3465 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3466 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3467 S_008F38_MIP_POINT_PRECLAMP(0) |
3468 S_008F38_DISABLE_LSB_CEIL(1) |
3469 S_008F38_FILTER_PREC_FIX(1) |
3470 S_008F38_ANISO_OVERRIDE(is_vi));
3471 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3472 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3473 }
3474
3475 VkResult radv_CreateSampler(
3476 VkDevice _device,
3477 const VkSamplerCreateInfo* pCreateInfo,
3478 const VkAllocationCallbacks* pAllocator,
3479 VkSampler* pSampler)
3480 {
3481 RADV_FROM_HANDLE(radv_device, device, _device);
3482 struct radv_sampler *sampler;
3483
3484 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3485
3486 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3487 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3488 if (!sampler)
3489 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3490
3491 radv_init_sampler(device, sampler, pCreateInfo);
3492 *pSampler = radv_sampler_to_handle(sampler);
3493
3494 return VK_SUCCESS;
3495 }
3496
3497 void radv_DestroySampler(
3498 VkDevice _device,
3499 VkSampler _sampler,
3500 const VkAllocationCallbacks* pAllocator)
3501 {
3502 RADV_FROM_HANDLE(radv_device, device, _device);
3503 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3504
3505 if (!sampler)
3506 return;
3507 vk_free2(&device->alloc, pAllocator, sampler);
3508 }
3509
3510 /* vk_icd.h does not declare this function, so we declare it here to
3511 * suppress Wmissing-prototypes.
3512 */
3513 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3514 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3515
3516 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3517 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3518 {
3519 /* For the full details on loader interface versioning, see
3520 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3521 * What follows is a condensed summary, to help you navigate the large and
3522 * confusing official doc.
3523 *
3524 * - Loader interface v0 is incompatible with later versions. We don't
3525 * support it.
3526 *
3527 * - In loader interface v1:
3528 * - The first ICD entrypoint called by the loader is
3529 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3530 * entrypoint.
3531 * - The ICD must statically expose no other Vulkan symbol unless it is
3532 * linked with -Bsymbolic.
3533 * - Each dispatchable Vulkan handle created by the ICD must be
3534 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3535 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3536 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3537 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3538 * such loader-managed surfaces.
3539 *
3540 * - Loader interface v2 differs from v1 in:
3541 * - The first ICD entrypoint called by the loader is
3542 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3543 * statically expose this entrypoint.
3544 *
3545 * - Loader interface v3 differs from v2 in:
3546 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3547 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3548 * because the loader no longer does so.
3549 */
3550 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3551 return VK_SUCCESS;
3552 }
3553
3554 VkResult radv_GetMemoryFdKHR(VkDevice _device,
3555 const VkMemoryGetFdInfoKHR *pGetFdInfo,
3556 int *pFD)
3557 {
3558 RADV_FROM_HANDLE(radv_device, device, _device);
3559 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
3560
3561 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
3562
3563 /* We support only one handle type. */
3564 assert(pGetFdInfo->handleType ==
3565 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3566
3567 bool ret = radv_get_memory_fd(device, memory, pFD);
3568 if (ret == false)
3569 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3570 return VK_SUCCESS;
3571 }
3572
3573 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
3574 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
3575 int fd,
3576 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
3577 {
3578 /* The valid usage section for this function says:
3579 *
3580 * "handleType must not be one of the handle types defined as opaque."
3581 *
3582 * Since we only handle opaque handles for now, there are no FD properties.
3583 */
3584 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3585 }
3586
3587 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
3588 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
3589 {
3590 RADV_FROM_HANDLE(radv_device, device, _device);
3591 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
3592 uint32_t syncobj_handle = 0;
3593 assert(pImportSemaphoreFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3594
3595 int ret = device->ws->import_syncobj(device->ws, pImportSemaphoreFdInfo->fd, &syncobj_handle);
3596 if (ret != 0)
3597 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
3598
3599 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
3600 sem->temp_syncobj = syncobj_handle;
3601 } else {
3602 sem->syncobj = syncobj_handle;
3603 }
3604 close(pImportSemaphoreFdInfo->fd);
3605 return VK_SUCCESS;
3606 }
3607
3608 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
3609 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
3610 int *pFd)
3611 {
3612 RADV_FROM_HANDLE(radv_device, device, _device);
3613 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
3614 int ret;
3615 uint32_t syncobj_handle;
3616
3617 assert(pGetFdInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR);
3618 if (sem->temp_syncobj)
3619 syncobj_handle = sem->temp_syncobj;
3620 else
3621 syncobj_handle = sem->syncobj;
3622 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
3623 if (ret)
3624 return vk_error(VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
3625 return VK_SUCCESS;
3626 }
3627
3628 void radv_GetPhysicalDeviceExternalSemaphorePropertiesKHR(
3629 VkPhysicalDevice physicalDevice,
3630 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
3631 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
3632 {
3633 if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
3634 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3635 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
3636 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
3637 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
3638 } else {
3639 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
3640 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
3641 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
3642 }
3643 }