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radv: Add support for VK_KHR_get_memory_requirements2.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "gfx9d.h"
46 #include "util/debug.h"
47
48 static int
49 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
50 {
51 uint32_t mesa_timestamp, llvm_timestamp;
52 uint16_t f = family;
53 memset(uuid, 0, VK_UUID_SIZE);
54 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
55 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
56 return -1;
57
58 memcpy(uuid, &mesa_timestamp, 4);
59 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
60 memcpy((char*)uuid + 8, &f, 2);
61 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
62 return 0;
63 }
64
65 static void
66 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
67 memset(uuid, 0, VK_UUID_SIZE);
68 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
69 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
70 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
71 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
72 }
73
74 static const VkExtensionProperties instance_extensions[] = {
75 {
76 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
77 .specVersion = 25,
78 },
79 #ifdef VK_USE_PLATFORM_XCB_KHR
80 {
81 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
82 .specVersion = 6,
83 },
84 #endif
85 #ifdef VK_USE_PLATFORM_XLIB_KHR
86 {
87 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
88 .specVersion = 6,
89 },
90 #endif
91 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
92 {
93 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
94 .specVersion = 5,
95 },
96 #endif
97 {
98 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
99 .specVersion = 1,
100 },
101 };
102
103 static const VkExtensionProperties common_device_extensions[] = {
104 {
105 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
106 .specVersion = 1,
107 },
108 {
109 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
110 .specVersion = 1,
111 },
112 {
113 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
114 .specVersion = 1,
115 },
116 {
117 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
118 .specVersion = 1,
119 },
120 {
121 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
122 .specVersion = 1,
123 },
124 {
125 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
126 .specVersion = 68,
127 },
128 {
129 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
130 .specVersion = 1,
131 },
132 {
133 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
134 .specVersion = 1,
135 },
136 {
137 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
138 .specVersion = 1,
139 },
140 {
141 .extensionName = VK_KHR_GET_MEMORY_REQUIREMENTS_2_EXTENSION_NAME,
142 .specVersion = 1,
143 },
144 };
145
146 static VkResult
147 radv_extensions_register(struct radv_instance *instance,
148 struct radv_extensions *extensions,
149 const VkExtensionProperties *new_ext,
150 uint32_t num_ext)
151 {
152 size_t new_size;
153 VkExtensionProperties *new_ptr;
154
155 assert(new_ext && num_ext > 0);
156
157 if (!new_ext)
158 return VK_ERROR_INITIALIZATION_FAILED;
159
160 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
161 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
162 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
163
164 /* Old array continues to be valid, update nothing */
165 if (!new_ptr)
166 return VK_ERROR_OUT_OF_HOST_MEMORY;
167
168 memcpy(&new_ptr[extensions->num_ext], new_ext,
169 num_ext * sizeof(VkExtensionProperties));
170 extensions->ext_array = new_ptr;
171 extensions->num_ext += num_ext;
172
173 return VK_SUCCESS;
174 }
175
176 static void
177 radv_extensions_finish(struct radv_instance *instance,
178 struct radv_extensions *extensions)
179 {
180 assert(extensions);
181
182 if (!extensions)
183 radv_loge("Attemted to free invalid extension struct\n");
184
185 if (extensions->ext_array)
186 vk_free(&instance->alloc, extensions->ext_array);
187 }
188
189 static bool
190 is_extension_enabled(const VkExtensionProperties *extensions,
191 size_t num_ext,
192 const char *name)
193 {
194 assert(extensions && name);
195
196 for (uint32_t i = 0; i < num_ext; i++) {
197 if (strcmp(name, extensions[i].extensionName) == 0)
198 return true;
199 }
200
201 return false;
202 }
203
204 static const char *
205 get_chip_name(enum radeon_family family)
206 {
207 switch (family) {
208 case CHIP_TAHITI: return "AMD RADV TAHITI";
209 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
210 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
211 case CHIP_OLAND: return "AMD RADV OLAND";
212 case CHIP_HAINAN: return "AMD RADV HAINAN";
213 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
214 case CHIP_KAVERI: return "AMD RADV KAVERI";
215 case CHIP_KABINI: return "AMD RADV KABINI";
216 case CHIP_HAWAII: return "AMD RADV HAWAII";
217 case CHIP_MULLINS: return "AMD RADV MULLINS";
218 case CHIP_TONGA: return "AMD RADV TONGA";
219 case CHIP_ICELAND: return "AMD RADV ICELAND";
220 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
221 case CHIP_FIJI: return "AMD RADV FIJI";
222 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
223 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
224 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
225 case CHIP_STONEY: return "AMD RADV STONEY";
226 case CHIP_VEGA10: return "AMD RADV VEGA";
227 case CHIP_RAVEN: return "AMD RADV RAVEN";
228 default: return "AMD RADV unknown";
229 }
230 }
231
232 static VkResult
233 radv_physical_device_init(struct radv_physical_device *device,
234 struct radv_instance *instance,
235 drmDevicePtr drm_device)
236 {
237 const char *path = drm_device->nodes[DRM_NODE_RENDER];
238 VkResult result;
239 drmVersionPtr version;
240 int fd;
241
242 fd = open(path, O_RDWR | O_CLOEXEC);
243 if (fd < 0)
244 return VK_ERROR_INCOMPATIBLE_DRIVER;
245
246 version = drmGetVersion(fd);
247 if (!version) {
248 close(fd);
249 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
250 "failed to get version %s: %m", path);
251 }
252
253 if (strcmp(version->name, "amdgpu")) {
254 drmFreeVersion(version);
255 close(fd);
256 return VK_ERROR_INCOMPATIBLE_DRIVER;
257 }
258 drmFreeVersion(version);
259
260 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
261 device->instance = instance;
262 assert(strlen(path) < ARRAY_SIZE(device->path));
263 strncpy(device->path, path, ARRAY_SIZE(device->path));
264
265 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
266 instance->perftest_flags);
267 if (!device->ws) {
268 result = VK_ERROR_INCOMPATIBLE_DRIVER;
269 goto fail;
270 }
271
272 device->local_fd = fd;
273 device->ws->query_info(device->ws, &device->rad_info);
274 result = radv_init_wsi(device);
275 if (result != VK_SUCCESS) {
276 device->ws->destroy(device->ws);
277 goto fail;
278 }
279
280 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
281 radv_finish_wsi(device);
282 device->ws->destroy(device->ws);
283 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
284 "cannot generate UUID");
285 goto fail;
286 }
287
288 result = radv_extensions_register(instance,
289 &device->extensions,
290 common_device_extensions,
291 ARRAY_SIZE(common_device_extensions));
292 if (result != VK_SUCCESS)
293 goto fail;
294
295 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
296 device->name = get_chip_name(device->rad_info.family);
297
298 radv_get_device_uuid(drm_device, device->device_uuid);
299
300 if (device->rad_info.family == CHIP_STONEY ||
301 device->rad_info.chip_class >= GFX9) {
302 device->has_rbplus = true;
303 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY;
304 }
305
306 return VK_SUCCESS;
307
308 fail:
309 close(fd);
310 return result;
311 }
312
313 static void
314 radv_physical_device_finish(struct radv_physical_device *device)
315 {
316 radv_extensions_finish(device->instance, &device->extensions);
317 radv_finish_wsi(device);
318 device->ws->destroy(device->ws);
319 close(device->local_fd);
320 }
321
322 static void *
323 default_alloc_func(void *pUserData, size_t size, size_t align,
324 VkSystemAllocationScope allocationScope)
325 {
326 return malloc(size);
327 }
328
329 static void *
330 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
331 size_t align, VkSystemAllocationScope allocationScope)
332 {
333 return realloc(pOriginal, size);
334 }
335
336 static void
337 default_free_func(void *pUserData, void *pMemory)
338 {
339 free(pMemory);
340 }
341
342 static const VkAllocationCallbacks default_alloc = {
343 .pUserData = NULL,
344 .pfnAllocation = default_alloc_func,
345 .pfnReallocation = default_realloc_func,
346 .pfnFree = default_free_func,
347 };
348
349 static const struct debug_control radv_debug_options[] = {
350 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
351 {"nodcc", RADV_DEBUG_NO_DCC},
352 {"shaders", RADV_DEBUG_DUMP_SHADERS},
353 {"nocache", RADV_DEBUG_NO_CACHE},
354 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
355 {"nohiz", RADV_DEBUG_NO_HIZ},
356 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
357 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
358 {"allbos", RADV_DEBUG_ALL_BOS},
359 {"noibs", RADV_DEBUG_NO_IBS},
360 {NULL, 0}
361 };
362
363 static const struct debug_control radv_perftest_options[] = {
364 {"batchchain", RADV_PERFTEST_BATCHCHAIN},
365 {"sisched", RADV_PERFTEST_SISCHED},
366 {NULL, 0}
367 };
368
369 VkResult radv_CreateInstance(
370 const VkInstanceCreateInfo* pCreateInfo,
371 const VkAllocationCallbacks* pAllocator,
372 VkInstance* pInstance)
373 {
374 struct radv_instance *instance;
375
376 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
377
378 uint32_t client_version;
379 if (pCreateInfo->pApplicationInfo &&
380 pCreateInfo->pApplicationInfo->apiVersion != 0) {
381 client_version = pCreateInfo->pApplicationInfo->apiVersion;
382 } else {
383 client_version = VK_MAKE_VERSION(1, 0, 0);
384 }
385
386 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
387 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
388 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
389 "Client requested version %d.%d.%d",
390 VK_VERSION_MAJOR(client_version),
391 VK_VERSION_MINOR(client_version),
392 VK_VERSION_PATCH(client_version));
393 }
394
395 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
396 if (!is_extension_enabled(instance_extensions,
397 ARRAY_SIZE(instance_extensions),
398 pCreateInfo->ppEnabledExtensionNames[i]))
399 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
400 }
401
402 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
403 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
404 if (!instance)
405 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
406
407 memset(instance, 0, sizeof(*instance));
408
409 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
410
411 if (pAllocator)
412 instance->alloc = *pAllocator;
413 else
414 instance->alloc = default_alloc;
415
416 instance->apiVersion = client_version;
417 instance->physicalDeviceCount = -1;
418
419 _mesa_locale_init();
420
421 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
422
423 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
424 radv_debug_options);
425
426 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
427 radv_perftest_options);
428
429 *pInstance = radv_instance_to_handle(instance);
430
431 return VK_SUCCESS;
432 }
433
434 void radv_DestroyInstance(
435 VkInstance _instance,
436 const VkAllocationCallbacks* pAllocator)
437 {
438 RADV_FROM_HANDLE(radv_instance, instance, _instance);
439
440 if (!instance)
441 return;
442
443 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
444 radv_physical_device_finish(instance->physicalDevices + i);
445 }
446
447 VG(VALGRIND_DESTROY_MEMPOOL(instance));
448
449 _mesa_locale_fini();
450
451 vk_free(&instance->alloc, instance);
452 }
453
454 static VkResult
455 radv_enumerate_devices(struct radv_instance *instance)
456 {
457 /* TODO: Check for more devices ? */
458 drmDevicePtr devices[8];
459 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
460 int max_devices;
461
462 instance->physicalDeviceCount = 0;
463
464 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
465 if (max_devices < 1)
466 return VK_ERROR_INCOMPATIBLE_DRIVER;
467
468 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
469 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
470 devices[i]->bustype == DRM_BUS_PCI &&
471 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
472
473 result = radv_physical_device_init(instance->physicalDevices +
474 instance->physicalDeviceCount,
475 instance,
476 devices[i]);
477 if (result == VK_SUCCESS)
478 ++instance->physicalDeviceCount;
479 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
480 break;
481 }
482 }
483 drmFreeDevices(devices, max_devices);
484
485 return result;
486 }
487
488 VkResult radv_EnumeratePhysicalDevices(
489 VkInstance _instance,
490 uint32_t* pPhysicalDeviceCount,
491 VkPhysicalDevice* pPhysicalDevices)
492 {
493 RADV_FROM_HANDLE(radv_instance, instance, _instance);
494 VkResult result;
495
496 if (instance->physicalDeviceCount < 0) {
497 result = radv_enumerate_devices(instance);
498 if (result != VK_SUCCESS &&
499 result != VK_ERROR_INCOMPATIBLE_DRIVER)
500 return result;
501 }
502
503 if (!pPhysicalDevices) {
504 *pPhysicalDeviceCount = instance->physicalDeviceCount;
505 } else {
506 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
507 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
508 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
509 }
510
511 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
512 : VK_SUCCESS;
513 }
514
515 void radv_GetPhysicalDeviceFeatures(
516 VkPhysicalDevice physicalDevice,
517 VkPhysicalDeviceFeatures* pFeatures)
518 {
519 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
520 bool is_gfx9 = pdevice->rad_info.chip_class >= GFX9;
521 memset(pFeatures, 0, sizeof(*pFeatures));
522
523 *pFeatures = (VkPhysicalDeviceFeatures) {
524 .robustBufferAccess = true,
525 .fullDrawIndexUint32 = true,
526 .imageCubeArray = true,
527 .independentBlend = true,
528 .geometryShader = !is_gfx9,
529 .tessellationShader = !is_gfx9,
530 .sampleRateShading = false,
531 .dualSrcBlend = true,
532 .logicOp = true,
533 .multiDrawIndirect = true,
534 .drawIndirectFirstInstance = true,
535 .depthClamp = true,
536 .depthBiasClamp = true,
537 .fillModeNonSolid = true,
538 .depthBounds = true,
539 .wideLines = true,
540 .largePoints = true,
541 .alphaToOne = true,
542 .multiViewport = true,
543 .samplerAnisotropy = true,
544 .textureCompressionETC2 = false,
545 .textureCompressionASTC_LDR = false,
546 .textureCompressionBC = true,
547 .occlusionQueryPrecise = true,
548 .pipelineStatisticsQuery = true,
549 .vertexPipelineStoresAndAtomics = true,
550 .fragmentStoresAndAtomics = true,
551 .shaderTessellationAndGeometryPointSize = true,
552 .shaderImageGatherExtended = true,
553 .shaderStorageImageExtendedFormats = true,
554 .shaderStorageImageMultisample = false,
555 .shaderUniformBufferArrayDynamicIndexing = true,
556 .shaderSampledImageArrayDynamicIndexing = true,
557 .shaderStorageBufferArrayDynamicIndexing = true,
558 .shaderStorageImageArrayDynamicIndexing = true,
559 .shaderStorageImageReadWithoutFormat = true,
560 .shaderStorageImageWriteWithoutFormat = true,
561 .shaderClipDistance = true,
562 .shaderCullDistance = true,
563 .shaderFloat64 = true,
564 .shaderInt64 = true,
565 .shaderInt16 = false,
566 .sparseBinding = true,
567 .variableMultisampleRate = true,
568 .inheritedQueries = true,
569 };
570 }
571
572 void radv_GetPhysicalDeviceFeatures2KHR(
573 VkPhysicalDevice physicalDevice,
574 VkPhysicalDeviceFeatures2KHR *pFeatures)
575 {
576 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
577 }
578
579 void radv_GetPhysicalDeviceProperties(
580 VkPhysicalDevice physicalDevice,
581 VkPhysicalDeviceProperties* pProperties)
582 {
583 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
584 VkSampleCountFlags sample_counts = 0xf;
585
586 /* make sure that the entire descriptor set is addressable with a signed
587 * 32-bit int. So the sum of all limits scaled by descriptor size has to
588 * be at most 2 GiB. the combined image & samples object count as one of
589 * both. This limit is for the pipeline layout, not for the set layout, but
590 * there is no set limit, so we just set a pipeline limit. I don't think
591 * any app is going to hit this soon. */
592 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
593 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
594 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
595 32 /* sampler, largest when combined with image */ +
596 64 /* sampled image */ +
597 64 /* storage image */);
598
599 VkPhysicalDeviceLimits limits = {
600 .maxImageDimension1D = (1 << 14),
601 .maxImageDimension2D = (1 << 14),
602 .maxImageDimension3D = (1 << 11),
603 .maxImageDimensionCube = (1 << 14),
604 .maxImageArrayLayers = (1 << 11),
605 .maxTexelBufferElements = 128 * 1024 * 1024,
606 .maxUniformBufferRange = UINT32_MAX,
607 .maxStorageBufferRange = UINT32_MAX,
608 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
609 .maxMemoryAllocationCount = UINT32_MAX,
610 .maxSamplerAllocationCount = 64 * 1024,
611 .bufferImageGranularity = 64, /* A cache line */
612 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
613 .maxBoundDescriptorSets = MAX_SETS,
614 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
615 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
616 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
617 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
618 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
619 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
620 .maxPerStageResources = max_descriptor_set_size,
621 .maxDescriptorSetSamplers = max_descriptor_set_size,
622 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
623 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
624 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
625 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
626 .maxDescriptorSetSampledImages = max_descriptor_set_size,
627 .maxDescriptorSetStorageImages = max_descriptor_set_size,
628 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
629 .maxVertexInputAttributes = 32,
630 .maxVertexInputBindings = 32,
631 .maxVertexInputAttributeOffset = 2047,
632 .maxVertexInputBindingStride = 2048,
633 .maxVertexOutputComponents = 128,
634 .maxTessellationGenerationLevel = 64,
635 .maxTessellationPatchSize = 32,
636 .maxTessellationControlPerVertexInputComponents = 128,
637 .maxTessellationControlPerVertexOutputComponents = 128,
638 .maxTessellationControlPerPatchOutputComponents = 120,
639 .maxTessellationControlTotalOutputComponents = 4096,
640 .maxTessellationEvaluationInputComponents = 128,
641 .maxTessellationEvaluationOutputComponents = 128,
642 .maxGeometryShaderInvocations = 127,
643 .maxGeometryInputComponents = 64,
644 .maxGeometryOutputComponents = 128,
645 .maxGeometryOutputVertices = 256,
646 .maxGeometryTotalOutputComponents = 1024,
647 .maxFragmentInputComponents = 128,
648 .maxFragmentOutputAttachments = 8,
649 .maxFragmentDualSrcAttachments = 1,
650 .maxFragmentCombinedOutputResources = 8,
651 .maxComputeSharedMemorySize = 32768,
652 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
653 .maxComputeWorkGroupInvocations = 2048,
654 .maxComputeWorkGroupSize = {
655 2048,
656 2048,
657 2048
658 },
659 .subPixelPrecisionBits = 4 /* FIXME */,
660 .subTexelPrecisionBits = 4 /* FIXME */,
661 .mipmapPrecisionBits = 4 /* FIXME */,
662 .maxDrawIndexedIndexValue = UINT32_MAX,
663 .maxDrawIndirectCount = UINT32_MAX,
664 .maxSamplerLodBias = 16,
665 .maxSamplerAnisotropy = 16,
666 .maxViewports = MAX_VIEWPORTS,
667 .maxViewportDimensions = { (1 << 14), (1 << 14) },
668 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
669 .viewportSubPixelBits = 13, /* We take a float? */
670 .minMemoryMapAlignment = 4096, /* A page */
671 .minTexelBufferOffsetAlignment = 1,
672 .minUniformBufferOffsetAlignment = 4,
673 .minStorageBufferOffsetAlignment = 4,
674 .minTexelOffset = -32,
675 .maxTexelOffset = 31,
676 .minTexelGatherOffset = -32,
677 .maxTexelGatherOffset = 31,
678 .minInterpolationOffset = -2,
679 .maxInterpolationOffset = 2,
680 .subPixelInterpolationOffsetBits = 8,
681 .maxFramebufferWidth = (1 << 14),
682 .maxFramebufferHeight = (1 << 14),
683 .maxFramebufferLayers = (1 << 10),
684 .framebufferColorSampleCounts = sample_counts,
685 .framebufferDepthSampleCounts = sample_counts,
686 .framebufferStencilSampleCounts = sample_counts,
687 .framebufferNoAttachmentsSampleCounts = sample_counts,
688 .maxColorAttachments = MAX_RTS,
689 .sampledImageColorSampleCounts = sample_counts,
690 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
691 .sampledImageDepthSampleCounts = sample_counts,
692 .sampledImageStencilSampleCounts = sample_counts,
693 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
694 .maxSampleMaskWords = 1,
695 .timestampComputeAndGraphics = true,
696 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
697 .maxClipDistances = 8,
698 .maxCullDistances = 8,
699 .maxCombinedClipAndCullDistances = 8,
700 .discreteQueuePriorities = 1,
701 .pointSizeRange = { 0.125, 255.875 },
702 .lineWidthRange = { 0.0, 7.9921875 },
703 .pointSizeGranularity = (1.0 / 8.0),
704 .lineWidthGranularity = (1.0 / 128.0),
705 .strictLines = false, /* FINISHME */
706 .standardSampleLocations = true,
707 .optimalBufferCopyOffsetAlignment = 128,
708 .optimalBufferCopyRowPitchAlignment = 128,
709 .nonCoherentAtomSize = 64,
710 };
711
712 *pProperties = (VkPhysicalDeviceProperties) {
713 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
714 .driverVersion = vk_get_driver_version(),
715 .vendorID = 0x1002,
716 .deviceID = pdevice->rad_info.pci_id,
717 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
718 .limits = limits,
719 .sparseProperties = {0},
720 };
721
722 strcpy(pProperties->deviceName, pdevice->name);
723 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
724 }
725
726 void radv_GetPhysicalDeviceProperties2KHR(
727 VkPhysicalDevice physicalDevice,
728 VkPhysicalDeviceProperties2KHR *pProperties)
729 {
730 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
731
732 vk_foreach_struct(ext, pProperties->pNext) {
733 switch (ext->sType) {
734 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
735 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
736 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
737 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
738 break;
739 }
740 default:
741 break;
742 }
743 }
744 }
745
746 static void radv_get_physical_device_queue_family_properties(
747 struct radv_physical_device* pdevice,
748 uint32_t* pCount,
749 VkQueueFamilyProperties** pQueueFamilyProperties)
750 {
751 int num_queue_families = 1;
752 int idx;
753 if (pdevice->rad_info.num_compute_rings > 0 &&
754 pdevice->rad_info.chip_class >= CIK &&
755 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
756 num_queue_families++;
757
758 if (pQueueFamilyProperties == NULL) {
759 *pCount = num_queue_families;
760 return;
761 }
762
763 if (!*pCount)
764 return;
765
766 idx = 0;
767 if (*pCount >= 1) {
768 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
769 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
770 VK_QUEUE_COMPUTE_BIT |
771 VK_QUEUE_TRANSFER_BIT |
772 VK_QUEUE_SPARSE_BINDING_BIT,
773 .queueCount = 1,
774 .timestampValidBits = 64,
775 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
776 };
777 idx++;
778 }
779
780 if (pdevice->rad_info.num_compute_rings > 0 &&
781 pdevice->rad_info.chip_class >= CIK &&
782 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
783 if (*pCount > idx) {
784 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
785 .queueFlags = VK_QUEUE_COMPUTE_BIT |
786 VK_QUEUE_TRANSFER_BIT |
787 VK_QUEUE_SPARSE_BINDING_BIT,
788 .queueCount = pdevice->rad_info.num_compute_rings,
789 .timestampValidBits = 64,
790 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
791 };
792 idx++;
793 }
794 }
795 *pCount = idx;
796 }
797
798 void radv_GetPhysicalDeviceQueueFamilyProperties(
799 VkPhysicalDevice physicalDevice,
800 uint32_t* pCount,
801 VkQueueFamilyProperties* pQueueFamilyProperties)
802 {
803 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
804 if (!pQueueFamilyProperties) {
805 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
806 return;
807 }
808 VkQueueFamilyProperties *properties[] = {
809 pQueueFamilyProperties + 0,
810 pQueueFamilyProperties + 1,
811 pQueueFamilyProperties + 2,
812 };
813 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
814 assert(*pCount <= 3);
815 }
816
817 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
818 VkPhysicalDevice physicalDevice,
819 uint32_t* pCount,
820 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
821 {
822 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
823 if (!pQueueFamilyProperties) {
824 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
825 return;
826 }
827 VkQueueFamilyProperties *properties[] = {
828 &pQueueFamilyProperties[0].queueFamilyProperties,
829 &pQueueFamilyProperties[1].queueFamilyProperties,
830 &pQueueFamilyProperties[2].queueFamilyProperties,
831 };
832 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
833 assert(*pCount <= 3);
834 }
835
836 void radv_GetPhysicalDeviceMemoryProperties(
837 VkPhysicalDevice physicalDevice,
838 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
839 {
840 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
841
842 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
843
844 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
845 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
846 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
847 .heapIndex = RADV_MEM_HEAP_VRAM,
848 };
849 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
850 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
851 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
852 .heapIndex = RADV_MEM_HEAP_GTT,
853 };
854 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
855 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
856 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
857 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
858 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
859 };
860 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
861 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
862 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
863 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
864 .heapIndex = RADV_MEM_HEAP_GTT,
865 };
866
867 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
868
869 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
870 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
871 .size = physical_device->rad_info.vram_size -
872 physical_device->rad_info.vram_vis_size,
873 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
874 };
875 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
876 .size = physical_device->rad_info.vram_vis_size,
877 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
878 };
879 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
880 .size = physical_device->rad_info.gart_size,
881 .flags = 0,
882 };
883 }
884
885 void radv_GetPhysicalDeviceMemoryProperties2KHR(
886 VkPhysicalDevice physicalDevice,
887 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
888 {
889 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
890 &pMemoryProperties->memoryProperties);
891 }
892
893 static int
894 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
895 int queue_family_index, int idx)
896 {
897 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
898 queue->device = device;
899 queue->queue_family_index = queue_family_index;
900 queue->queue_idx = idx;
901
902 queue->hw_ctx = device->ws->ctx_create(device->ws);
903 if (!queue->hw_ctx)
904 return VK_ERROR_OUT_OF_HOST_MEMORY;
905
906 return VK_SUCCESS;
907 }
908
909 static void
910 radv_queue_finish(struct radv_queue *queue)
911 {
912 if (queue->hw_ctx)
913 queue->device->ws->ctx_destroy(queue->hw_ctx);
914
915 if (queue->initial_preamble_cs)
916 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
917 if (queue->continue_preamble_cs)
918 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
919 if (queue->descriptor_bo)
920 queue->device->ws->buffer_destroy(queue->descriptor_bo);
921 if (queue->scratch_bo)
922 queue->device->ws->buffer_destroy(queue->scratch_bo);
923 if (queue->esgs_ring_bo)
924 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
925 if (queue->gsvs_ring_bo)
926 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
927 if (queue->tess_factor_ring_bo)
928 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
929 if (queue->tess_offchip_ring_bo)
930 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
931 if (queue->compute_scratch_bo)
932 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
933 }
934
935 static void
936 radv_device_init_gs_info(struct radv_device *device)
937 {
938 switch (device->physical_device->rad_info.family) {
939 case CHIP_OLAND:
940 case CHIP_HAINAN:
941 case CHIP_KAVERI:
942 case CHIP_KABINI:
943 case CHIP_MULLINS:
944 case CHIP_ICELAND:
945 case CHIP_CARRIZO:
946 case CHIP_STONEY:
947 device->gs_table_depth = 16;
948 return;
949 case CHIP_TAHITI:
950 case CHIP_PITCAIRN:
951 case CHIP_VERDE:
952 case CHIP_BONAIRE:
953 case CHIP_HAWAII:
954 case CHIP_TONGA:
955 case CHIP_FIJI:
956 case CHIP_POLARIS10:
957 case CHIP_POLARIS11:
958 case CHIP_POLARIS12:
959 case CHIP_VEGA10:
960 case CHIP_RAVEN:
961 device->gs_table_depth = 32;
962 return;
963 default:
964 unreachable("unknown GPU");
965 }
966 }
967
968 VkResult radv_CreateDevice(
969 VkPhysicalDevice physicalDevice,
970 const VkDeviceCreateInfo* pCreateInfo,
971 const VkAllocationCallbacks* pAllocator,
972 VkDevice* pDevice)
973 {
974 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
975 VkResult result;
976 struct radv_device *device;
977
978 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
979 if (!is_extension_enabled(physical_device->extensions.ext_array,
980 physical_device->extensions.num_ext,
981 pCreateInfo->ppEnabledExtensionNames[i]))
982 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
983 }
984
985 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
986 sizeof(*device), 8,
987 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
988 if (!device)
989 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
990
991 memset(device, 0, sizeof(*device));
992
993 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
994 device->instance = physical_device->instance;
995 device->physical_device = physical_device;
996
997 device->debug_flags = device->instance->debug_flags;
998
999 device->ws = physical_device->ws;
1000 if (pAllocator)
1001 device->alloc = *pAllocator;
1002 else
1003 device->alloc = physical_device->instance->alloc;
1004
1005 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1006 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1007 uint32_t qfi = queue_create->queueFamilyIndex;
1008
1009 device->queues[qfi] = vk_alloc(&device->alloc,
1010 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1011 if (!device->queues[qfi]) {
1012 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1013 goto fail;
1014 }
1015
1016 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1017
1018 device->queue_count[qfi] = queue_create->queueCount;
1019
1020 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1021 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1022 if (result != VK_SUCCESS)
1023 goto fail;
1024 }
1025 }
1026
1027 #if HAVE_LLVM < 0x0400
1028 device->llvm_supports_spill = false;
1029 #else
1030 device->llvm_supports_spill = true;
1031 #endif
1032
1033 /* The maximum number of scratch waves. Scratch space isn't divided
1034 * evenly between CUs. The number is only a function of the number of CUs.
1035 * We can decrease the constant to decrease the scratch buffer size.
1036 *
1037 * sctx->scratch_waves must be >= the maximum posible size of
1038 * 1 threadgroup, so that the hw doesn't hang from being unable
1039 * to start any.
1040 *
1041 * The recommended value is 4 per CU at most. Higher numbers don't
1042 * bring much benefit, but they still occupy chip resources (think
1043 * async compute). I've seen ~2% performance difference between 4 and 32.
1044 */
1045 uint32_t max_threads_per_block = 2048;
1046 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1047 max_threads_per_block / 64);
1048
1049 radv_device_init_gs_info(device);
1050
1051 device->tess_offchip_block_dw_size =
1052 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1053 device->has_distributed_tess =
1054 device->physical_device->rad_info.chip_class >= VI &&
1055 device->physical_device->rad_info.max_se >= 2;
1056
1057 result = radv_device_init_meta(device);
1058 if (result != VK_SUCCESS)
1059 goto fail;
1060
1061 radv_device_init_msaa(device);
1062
1063 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1064 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1065 switch (family) {
1066 case RADV_QUEUE_GENERAL:
1067 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1068 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1069 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1070 break;
1071 case RADV_QUEUE_COMPUTE:
1072 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1073 radeon_emit(device->empty_cs[family], 0);
1074 break;
1075 }
1076 device->ws->cs_finalize(device->empty_cs[family]);
1077
1078 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1079 switch (family) {
1080 case RADV_QUEUE_GENERAL:
1081 case RADV_QUEUE_COMPUTE:
1082 si_cs_emit_cache_flush(device->flush_cs[family],
1083 false,
1084 device->physical_device->rad_info.chip_class,
1085 NULL, 0,
1086 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1087 RADV_CMD_FLAG_INV_ICACHE |
1088 RADV_CMD_FLAG_INV_SMEM_L1 |
1089 RADV_CMD_FLAG_INV_VMEM_L1 |
1090 RADV_CMD_FLAG_INV_GLOBAL_L2);
1091 break;
1092 }
1093 device->ws->cs_finalize(device->flush_cs[family]);
1094
1095 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1096 switch (family) {
1097 case RADV_QUEUE_GENERAL:
1098 case RADV_QUEUE_COMPUTE:
1099 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1100 false,
1101 device->physical_device->rad_info.chip_class,
1102 NULL, 0,
1103 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1104 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1105 RADV_CMD_FLAG_INV_ICACHE |
1106 RADV_CMD_FLAG_INV_SMEM_L1 |
1107 RADV_CMD_FLAG_INV_VMEM_L1 |
1108 RADV_CMD_FLAG_INV_GLOBAL_L2);
1109 break;
1110 }
1111 device->ws->cs_finalize(device->flush_shader_cs[family]);
1112 }
1113
1114 if (getenv("RADV_TRACE_FILE")) {
1115 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1116 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1117 if (!device->trace_bo)
1118 goto fail;
1119
1120 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1121 if (!device->trace_id_ptr)
1122 goto fail;
1123 }
1124
1125 if (device->physical_device->rad_info.chip_class >= CIK)
1126 cik_create_gfx_config(device);
1127
1128 VkPipelineCacheCreateInfo ci;
1129 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1130 ci.pNext = NULL;
1131 ci.flags = 0;
1132 ci.pInitialData = NULL;
1133 ci.initialDataSize = 0;
1134 VkPipelineCache pc;
1135 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1136 &ci, NULL, &pc);
1137 if (result != VK_SUCCESS)
1138 goto fail;
1139
1140 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1141
1142 *pDevice = radv_device_to_handle(device);
1143 return VK_SUCCESS;
1144
1145 fail:
1146 if (device->trace_bo)
1147 device->ws->buffer_destroy(device->trace_bo);
1148
1149 if (device->gfx_init)
1150 device->ws->buffer_destroy(device->gfx_init);
1151
1152 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1153 for (unsigned q = 0; q < device->queue_count[i]; q++)
1154 radv_queue_finish(&device->queues[i][q]);
1155 if (device->queue_count[i])
1156 vk_free(&device->alloc, device->queues[i]);
1157 }
1158
1159 vk_free(&device->alloc, device);
1160 return result;
1161 }
1162
1163 void radv_DestroyDevice(
1164 VkDevice _device,
1165 const VkAllocationCallbacks* pAllocator)
1166 {
1167 RADV_FROM_HANDLE(radv_device, device, _device);
1168
1169 if (!device)
1170 return;
1171
1172 if (device->trace_bo)
1173 device->ws->buffer_destroy(device->trace_bo);
1174
1175 if (device->gfx_init)
1176 device->ws->buffer_destroy(device->gfx_init);
1177
1178 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1179 for (unsigned q = 0; q < device->queue_count[i]; q++)
1180 radv_queue_finish(&device->queues[i][q]);
1181 if (device->queue_count[i])
1182 vk_free(&device->alloc, device->queues[i]);
1183 if (device->empty_cs[i])
1184 device->ws->cs_destroy(device->empty_cs[i]);
1185 if (device->flush_cs[i])
1186 device->ws->cs_destroy(device->flush_cs[i]);
1187 if (device->flush_shader_cs[i])
1188 device->ws->cs_destroy(device->flush_shader_cs[i]);
1189 }
1190 radv_device_finish_meta(device);
1191
1192 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1193 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1194
1195 vk_free(&device->alloc, device);
1196 }
1197
1198 VkResult radv_EnumerateInstanceExtensionProperties(
1199 const char* pLayerName,
1200 uint32_t* pPropertyCount,
1201 VkExtensionProperties* pProperties)
1202 {
1203 if (pProperties == NULL) {
1204 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1205 return VK_SUCCESS;
1206 }
1207
1208 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1209 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1210
1211 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1212 return VK_INCOMPLETE;
1213
1214 return VK_SUCCESS;
1215 }
1216
1217 VkResult radv_EnumerateDeviceExtensionProperties(
1218 VkPhysicalDevice physicalDevice,
1219 const char* pLayerName,
1220 uint32_t* pPropertyCount,
1221 VkExtensionProperties* pProperties)
1222 {
1223 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1224
1225 if (pProperties == NULL) {
1226 *pPropertyCount = pdevice->extensions.num_ext;
1227 return VK_SUCCESS;
1228 }
1229
1230 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1231 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1232
1233 if (*pPropertyCount < pdevice->extensions.num_ext)
1234 return VK_INCOMPLETE;
1235
1236 return VK_SUCCESS;
1237 }
1238
1239 VkResult radv_EnumerateInstanceLayerProperties(
1240 uint32_t* pPropertyCount,
1241 VkLayerProperties* pProperties)
1242 {
1243 if (pProperties == NULL) {
1244 *pPropertyCount = 0;
1245 return VK_SUCCESS;
1246 }
1247
1248 /* None supported at this time */
1249 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1250 }
1251
1252 VkResult radv_EnumerateDeviceLayerProperties(
1253 VkPhysicalDevice physicalDevice,
1254 uint32_t* pPropertyCount,
1255 VkLayerProperties* pProperties)
1256 {
1257 if (pProperties == NULL) {
1258 *pPropertyCount = 0;
1259 return VK_SUCCESS;
1260 }
1261
1262 /* None supported at this time */
1263 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1264 }
1265
1266 void radv_GetDeviceQueue(
1267 VkDevice _device,
1268 uint32_t queueFamilyIndex,
1269 uint32_t queueIndex,
1270 VkQueue* pQueue)
1271 {
1272 RADV_FROM_HANDLE(radv_device, device, _device);
1273
1274 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1275 }
1276
1277 static void radv_dump_trace(struct radv_device *device,
1278 struct radeon_winsys_cs *cs)
1279 {
1280 const char *filename = getenv("RADV_TRACE_FILE");
1281 FILE *f = fopen(filename, "w");
1282 if (!f) {
1283 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1284 return;
1285 }
1286
1287 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1288 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1289 fclose(f);
1290 }
1291
1292 static void
1293 fill_geom_tess_rings(struct radv_queue *queue,
1294 uint32_t *map,
1295 bool add_sample_positions,
1296 uint32_t esgs_ring_size,
1297 struct radeon_winsys_bo *esgs_ring_bo,
1298 uint32_t gsvs_ring_size,
1299 struct radeon_winsys_bo *gsvs_ring_bo,
1300 uint32_t tess_factor_ring_size,
1301 struct radeon_winsys_bo *tess_factor_ring_bo,
1302 uint32_t tess_offchip_ring_size,
1303 struct radeon_winsys_bo *tess_offchip_ring_bo)
1304 {
1305 uint64_t esgs_va = 0, gsvs_va = 0;
1306 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1307 uint32_t *desc = &map[4];
1308
1309 if (esgs_ring_bo)
1310 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1311 if (gsvs_ring_bo)
1312 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1313 if (tess_factor_ring_bo)
1314 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1315 if (tess_offchip_ring_bo)
1316 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1317
1318 /* stride 0, num records - size, add tid, swizzle, elsize4,
1319 index stride 64 */
1320 desc[0] = esgs_va;
1321 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1322 S_008F04_STRIDE(0) |
1323 S_008F04_SWIZZLE_ENABLE(true);
1324 desc[2] = esgs_ring_size;
1325 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1326 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1327 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1328 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1329 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1330 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1331 S_008F0C_ELEMENT_SIZE(1) |
1332 S_008F0C_INDEX_STRIDE(3) |
1333 S_008F0C_ADD_TID_ENABLE(true);
1334
1335 desc += 4;
1336 /* GS entry for ES->GS ring */
1337 /* stride 0, num records - size, elsize0,
1338 index stride 0 */
1339 desc[0] = esgs_va;
1340 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1341 S_008F04_STRIDE(0) |
1342 S_008F04_SWIZZLE_ENABLE(false);
1343 desc[2] = esgs_ring_size;
1344 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1345 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1346 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1347 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1348 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1349 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1350 S_008F0C_ELEMENT_SIZE(0) |
1351 S_008F0C_INDEX_STRIDE(0) |
1352 S_008F0C_ADD_TID_ENABLE(false);
1353
1354 desc += 4;
1355 /* VS entry for GS->VS ring */
1356 /* stride 0, num records - size, elsize0,
1357 index stride 0 */
1358 desc[0] = gsvs_va;
1359 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1360 S_008F04_STRIDE(0) |
1361 S_008F04_SWIZZLE_ENABLE(false);
1362 desc[2] = gsvs_ring_size;
1363 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1364 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1365 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1366 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1367 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1368 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1369 S_008F0C_ELEMENT_SIZE(0) |
1370 S_008F0C_INDEX_STRIDE(0) |
1371 S_008F0C_ADD_TID_ENABLE(false);
1372 desc += 4;
1373
1374 /* stride gsvs_itemsize, num records 64
1375 elsize 4, index stride 16 */
1376 /* shader will patch stride and desc[2] */
1377 desc[0] = gsvs_va;
1378 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1379 S_008F04_STRIDE(0) |
1380 S_008F04_SWIZZLE_ENABLE(true);
1381 desc[2] = 0;
1382 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1383 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1384 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1385 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1386 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1387 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1388 S_008F0C_ELEMENT_SIZE(1) |
1389 S_008F0C_INDEX_STRIDE(1) |
1390 S_008F0C_ADD_TID_ENABLE(true);
1391 desc += 4;
1392
1393 desc[0] = tess_factor_va;
1394 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1395 S_008F04_STRIDE(0) |
1396 S_008F04_SWIZZLE_ENABLE(false);
1397 desc[2] = tess_factor_ring_size;
1398 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1399 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1400 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1401 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1402 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1403 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1404 S_008F0C_ELEMENT_SIZE(0) |
1405 S_008F0C_INDEX_STRIDE(0) |
1406 S_008F0C_ADD_TID_ENABLE(false);
1407 desc += 4;
1408
1409 desc[0] = tess_offchip_va;
1410 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1411 S_008F04_STRIDE(0) |
1412 S_008F04_SWIZZLE_ENABLE(false);
1413 desc[2] = tess_offchip_ring_size;
1414 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1415 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1416 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1417 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1418 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1419 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1420 S_008F0C_ELEMENT_SIZE(0) |
1421 S_008F0C_INDEX_STRIDE(0) |
1422 S_008F0C_ADD_TID_ENABLE(false);
1423 desc += 4;
1424
1425 /* add sample positions after all rings */
1426 memcpy(desc, queue->device->sample_locations_1x, 8);
1427 desc += 2;
1428 memcpy(desc, queue->device->sample_locations_2x, 16);
1429 desc += 4;
1430 memcpy(desc, queue->device->sample_locations_4x, 32);
1431 desc += 8;
1432 memcpy(desc, queue->device->sample_locations_8x, 64);
1433 desc += 16;
1434 memcpy(desc, queue->device->sample_locations_16x, 128);
1435 }
1436
1437 static unsigned
1438 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1439 {
1440 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1441 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1442 device->physical_device->rad_info.family != CHIP_STONEY;
1443 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1444 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1445 device->physical_device->rad_info.max_se;
1446 unsigned offchip_granularity;
1447 unsigned hs_offchip_param;
1448 switch (device->tess_offchip_block_dw_size) {
1449 default:
1450 assert(0);
1451 /* fall through */
1452 case 8192:
1453 offchip_granularity = V_03093C_X_8K_DWORDS;
1454 break;
1455 case 4096:
1456 offchip_granularity = V_03093C_X_4K_DWORDS;
1457 break;
1458 }
1459
1460 switch (device->physical_device->rad_info.chip_class) {
1461 case SI:
1462 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1463 break;
1464 case CIK:
1465 case VI:
1466 case GFX9:
1467 default:
1468 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1469 break;
1470 }
1471
1472 *max_offchip_buffers_p = max_offchip_buffers;
1473 if (device->physical_device->rad_info.chip_class >= CIK) {
1474 if (device->physical_device->rad_info.chip_class >= VI)
1475 --max_offchip_buffers;
1476 hs_offchip_param =
1477 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1478 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1479 } else {
1480 hs_offchip_param =
1481 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1482 }
1483 return hs_offchip_param;
1484 }
1485
1486 static VkResult
1487 radv_get_preamble_cs(struct radv_queue *queue,
1488 uint32_t scratch_size,
1489 uint32_t compute_scratch_size,
1490 uint32_t esgs_ring_size,
1491 uint32_t gsvs_ring_size,
1492 bool needs_tess_rings,
1493 bool needs_sample_positions,
1494 struct radeon_winsys_cs **initial_preamble_cs,
1495 struct radeon_winsys_cs **continue_preamble_cs)
1496 {
1497 struct radeon_winsys_bo *scratch_bo = NULL;
1498 struct radeon_winsys_bo *descriptor_bo = NULL;
1499 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1500 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1501 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1502 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1503 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1504 struct radeon_winsys_cs *dest_cs[2] = {0};
1505 bool add_tess_rings = false, add_sample_positions = false;
1506 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1507 unsigned max_offchip_buffers;
1508 unsigned hs_offchip_param = 0;
1509 if (!queue->has_tess_rings) {
1510 if (needs_tess_rings)
1511 add_tess_rings = true;
1512 }
1513 if (!queue->has_sample_positions) {
1514 if (needs_sample_positions)
1515 add_sample_positions = true;
1516 }
1517 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1518 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1519 &max_offchip_buffers);
1520 tess_offchip_ring_size = max_offchip_buffers *
1521 queue->device->tess_offchip_block_dw_size * 4;
1522
1523 if (scratch_size <= queue->scratch_size &&
1524 compute_scratch_size <= queue->compute_scratch_size &&
1525 esgs_ring_size <= queue->esgs_ring_size &&
1526 gsvs_ring_size <= queue->gsvs_ring_size &&
1527 !add_tess_rings && !add_sample_positions &&
1528 queue->initial_preamble_cs) {
1529 *initial_preamble_cs = queue->initial_preamble_cs;
1530 *continue_preamble_cs = queue->continue_preamble_cs;
1531 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1532 *continue_preamble_cs = NULL;
1533 return VK_SUCCESS;
1534 }
1535
1536 if (scratch_size > queue->scratch_size) {
1537 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1538 scratch_size,
1539 4096,
1540 RADEON_DOMAIN_VRAM,
1541 RADEON_FLAG_NO_CPU_ACCESS);
1542 if (!scratch_bo)
1543 goto fail;
1544 } else
1545 scratch_bo = queue->scratch_bo;
1546
1547 if (compute_scratch_size > queue->compute_scratch_size) {
1548 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1549 compute_scratch_size,
1550 4096,
1551 RADEON_DOMAIN_VRAM,
1552 RADEON_FLAG_NO_CPU_ACCESS);
1553 if (!compute_scratch_bo)
1554 goto fail;
1555
1556 } else
1557 compute_scratch_bo = queue->compute_scratch_bo;
1558
1559 if (esgs_ring_size > queue->esgs_ring_size) {
1560 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1561 esgs_ring_size,
1562 4096,
1563 RADEON_DOMAIN_VRAM,
1564 RADEON_FLAG_NO_CPU_ACCESS);
1565 if (!esgs_ring_bo)
1566 goto fail;
1567 } else {
1568 esgs_ring_bo = queue->esgs_ring_bo;
1569 esgs_ring_size = queue->esgs_ring_size;
1570 }
1571
1572 if (gsvs_ring_size > queue->gsvs_ring_size) {
1573 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1574 gsvs_ring_size,
1575 4096,
1576 RADEON_DOMAIN_VRAM,
1577 RADEON_FLAG_NO_CPU_ACCESS);
1578 if (!gsvs_ring_bo)
1579 goto fail;
1580 } else {
1581 gsvs_ring_bo = queue->gsvs_ring_bo;
1582 gsvs_ring_size = queue->gsvs_ring_size;
1583 }
1584
1585 if (add_tess_rings) {
1586 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1587 tess_factor_ring_size,
1588 256,
1589 RADEON_DOMAIN_VRAM,
1590 RADEON_FLAG_NO_CPU_ACCESS);
1591 if (!tess_factor_ring_bo)
1592 goto fail;
1593 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1594 tess_offchip_ring_size,
1595 256,
1596 RADEON_DOMAIN_VRAM,
1597 RADEON_FLAG_NO_CPU_ACCESS);
1598 if (!tess_offchip_ring_bo)
1599 goto fail;
1600 } else {
1601 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1602 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1603 }
1604
1605 if (scratch_bo != queue->scratch_bo ||
1606 esgs_ring_bo != queue->esgs_ring_bo ||
1607 gsvs_ring_bo != queue->gsvs_ring_bo ||
1608 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1609 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1610 uint32_t size = 0;
1611 if (gsvs_ring_bo || esgs_ring_bo ||
1612 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1613 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1614 if (add_sample_positions)
1615 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1616 }
1617 else if (scratch_bo)
1618 size = 8; /* 2 dword */
1619
1620 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1621 size,
1622 4096,
1623 RADEON_DOMAIN_VRAM,
1624 RADEON_FLAG_CPU_ACCESS);
1625 if (!descriptor_bo)
1626 goto fail;
1627 } else
1628 descriptor_bo = queue->descriptor_bo;
1629
1630 for(int i = 0; i < 2; ++i) {
1631 struct radeon_winsys_cs *cs = NULL;
1632 cs = queue->device->ws->cs_create(queue->device->ws,
1633 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1634 if (!cs)
1635 goto fail;
1636
1637 dest_cs[i] = cs;
1638
1639 if (scratch_bo)
1640 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1641
1642 if (esgs_ring_bo)
1643 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1644
1645 if (gsvs_ring_bo)
1646 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1647
1648 if (tess_factor_ring_bo)
1649 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1650
1651 if (tess_offchip_ring_bo)
1652 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1653
1654 if (descriptor_bo)
1655 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1656
1657 if (descriptor_bo != queue->descriptor_bo) {
1658 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1659
1660 if (scratch_bo) {
1661 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1662 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1663 S_008F04_SWIZZLE_ENABLE(1);
1664 map[0] = scratch_va;
1665 map[1] = rsrc1;
1666 }
1667
1668 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1669 add_sample_positions)
1670 fill_geom_tess_rings(queue, map, add_sample_positions,
1671 esgs_ring_size, esgs_ring_bo,
1672 gsvs_ring_size, gsvs_ring_bo,
1673 tess_factor_ring_size, tess_factor_ring_bo,
1674 tess_offchip_ring_size, tess_offchip_ring_bo);
1675
1676 queue->device->ws->buffer_unmap(descriptor_bo);
1677 }
1678
1679 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1680 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1681 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1682 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1683 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1684 }
1685
1686 if (esgs_ring_bo || gsvs_ring_bo) {
1687 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1688 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1689 radeon_emit(cs, esgs_ring_size >> 8);
1690 radeon_emit(cs, gsvs_ring_size >> 8);
1691 } else {
1692 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1693 radeon_emit(cs, esgs_ring_size >> 8);
1694 radeon_emit(cs, gsvs_ring_size >> 8);
1695 }
1696 }
1697
1698 if (tess_factor_ring_bo) {
1699 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1700 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1701 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1702 S_030938_SIZE(tess_factor_ring_size / 4));
1703 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1704 tf_va >> 8);
1705 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
1706 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
1707 tf_va >> 40);
1708 }
1709 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1710 } else {
1711 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1712 S_008988_SIZE(tess_factor_ring_size / 4));
1713 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1714 tf_va >> 8);
1715 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1716 hs_offchip_param);
1717 }
1718 }
1719
1720 if (descriptor_bo) {
1721 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1722 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1723 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1724 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1725 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1726 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1727
1728 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1729
1730 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1731 radeon_set_sh_reg_seq(cs, regs[i], 2);
1732 radeon_emit(cs, va);
1733 radeon_emit(cs, va >> 32);
1734 }
1735 }
1736
1737 if (compute_scratch_bo) {
1738 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1739 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1740 S_008F04_SWIZZLE_ENABLE(1);
1741
1742 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1743
1744 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1745 radeon_emit(cs, scratch_va);
1746 radeon_emit(cs, rsrc1);
1747 }
1748
1749 if (!i) {
1750 si_cs_emit_cache_flush(cs,
1751 false,
1752 queue->device->physical_device->rad_info.chip_class,
1753 NULL, 0,
1754 queue->queue_family_index == RING_COMPUTE &&
1755 queue->device->physical_device->rad_info.chip_class >= CIK,
1756 RADV_CMD_FLAG_INV_ICACHE |
1757 RADV_CMD_FLAG_INV_SMEM_L1 |
1758 RADV_CMD_FLAG_INV_VMEM_L1 |
1759 RADV_CMD_FLAG_INV_GLOBAL_L2);
1760 }
1761
1762 if (!queue->device->ws->cs_finalize(cs))
1763 goto fail;
1764 }
1765
1766 if (queue->initial_preamble_cs)
1767 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1768
1769 if (queue->continue_preamble_cs)
1770 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1771
1772 queue->initial_preamble_cs = dest_cs[0];
1773 queue->continue_preamble_cs = dest_cs[1];
1774
1775 if (scratch_bo != queue->scratch_bo) {
1776 if (queue->scratch_bo)
1777 queue->device->ws->buffer_destroy(queue->scratch_bo);
1778 queue->scratch_bo = scratch_bo;
1779 queue->scratch_size = scratch_size;
1780 }
1781
1782 if (compute_scratch_bo != queue->compute_scratch_bo) {
1783 if (queue->compute_scratch_bo)
1784 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1785 queue->compute_scratch_bo = compute_scratch_bo;
1786 queue->compute_scratch_size = compute_scratch_size;
1787 }
1788
1789 if (esgs_ring_bo != queue->esgs_ring_bo) {
1790 if (queue->esgs_ring_bo)
1791 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1792 queue->esgs_ring_bo = esgs_ring_bo;
1793 queue->esgs_ring_size = esgs_ring_size;
1794 }
1795
1796 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1797 if (queue->gsvs_ring_bo)
1798 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1799 queue->gsvs_ring_bo = gsvs_ring_bo;
1800 queue->gsvs_ring_size = gsvs_ring_size;
1801 }
1802
1803 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1804 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1805 }
1806
1807 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1808 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1809 queue->has_tess_rings = true;
1810 }
1811
1812 if (descriptor_bo != queue->descriptor_bo) {
1813 if (queue->descriptor_bo)
1814 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1815
1816 queue->descriptor_bo = descriptor_bo;
1817 }
1818
1819 if (add_sample_positions)
1820 queue->has_sample_positions = true;
1821
1822 *initial_preamble_cs = queue->initial_preamble_cs;
1823 *continue_preamble_cs = queue->continue_preamble_cs;
1824 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1825 *continue_preamble_cs = NULL;
1826 return VK_SUCCESS;
1827 fail:
1828 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1829 if (dest_cs[i])
1830 queue->device->ws->cs_destroy(dest_cs[i]);
1831 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1832 queue->device->ws->buffer_destroy(descriptor_bo);
1833 if (scratch_bo && scratch_bo != queue->scratch_bo)
1834 queue->device->ws->buffer_destroy(scratch_bo);
1835 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1836 queue->device->ws->buffer_destroy(compute_scratch_bo);
1837 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1838 queue->device->ws->buffer_destroy(esgs_ring_bo);
1839 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1840 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1841 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1842 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1843 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1844 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1845 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1846 }
1847
1848 VkResult radv_QueueSubmit(
1849 VkQueue _queue,
1850 uint32_t submitCount,
1851 const VkSubmitInfo* pSubmits,
1852 VkFence _fence)
1853 {
1854 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1855 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1856 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1857 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1858 int ret;
1859 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1860 uint32_t scratch_size = 0;
1861 uint32_t compute_scratch_size = 0;
1862 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1863 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1864 VkResult result;
1865 bool fence_emitted = false;
1866 bool tess_rings_needed = false;
1867 bool sample_positions_needed = false;
1868
1869 /* Do this first so failing to allocate scratch buffers can't result in
1870 * partially executed submissions. */
1871 for (uint32_t i = 0; i < submitCount; i++) {
1872 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1873 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1874 pSubmits[i].pCommandBuffers[j]);
1875
1876 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1877 compute_scratch_size = MAX2(compute_scratch_size,
1878 cmd_buffer->compute_scratch_size_needed);
1879 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1880 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1881 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1882 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1883 }
1884 }
1885
1886 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1887 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1888 sample_positions_needed,
1889 &initial_preamble_cs, &continue_preamble_cs);
1890 if (result != VK_SUCCESS)
1891 return result;
1892
1893 for (uint32_t i = 0; i < submitCount; i++) {
1894 struct radeon_winsys_cs **cs_array;
1895 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1896 bool can_patch = !do_flush;
1897 uint32_t advance;
1898
1899 if (!pSubmits[i].commandBufferCount) {
1900 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1901 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1902 &queue->device->empty_cs[queue->queue_family_index],
1903 1, NULL, NULL,
1904 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1905 pSubmits[i].waitSemaphoreCount,
1906 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1907 pSubmits[i].signalSemaphoreCount,
1908 false, base_fence);
1909 if (ret) {
1910 radv_loge("failed to submit CS %d\n", i);
1911 abort();
1912 }
1913 fence_emitted = true;
1914 }
1915 continue;
1916 }
1917
1918 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1919 (pSubmits[i].commandBufferCount + do_flush));
1920
1921 if(do_flush)
1922 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
1923 queue->device->flush_shader_cs[queue->queue_family_index] :
1924 queue->device->flush_cs[queue->queue_family_index];
1925
1926 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1927 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1928 pSubmits[i].pCommandBuffers[j]);
1929 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1930
1931 cs_array[j + do_flush] = cmd_buffer->cs;
1932 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1933 can_patch = false;
1934 }
1935
1936 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1937 advance = MIN2(max_cs_submission,
1938 pSubmits[i].commandBufferCount + do_flush - j);
1939 bool b = j == 0;
1940 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1941
1942 if (queue->device->trace_bo)
1943 *queue->device->trace_id_ptr = 0;
1944
1945 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1946 advance, initial_preamble_cs, continue_preamble_cs,
1947 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1948 b ? pSubmits[i].waitSemaphoreCount : 0,
1949 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1950 e ? pSubmits[i].signalSemaphoreCount : 0,
1951 can_patch, base_fence);
1952
1953 if (ret) {
1954 radv_loge("failed to submit CS %d\n", i);
1955 abort();
1956 }
1957 fence_emitted = true;
1958 if (queue->device->trace_bo) {
1959 bool success = queue->device->ws->ctx_wait_idle(
1960 queue->hw_ctx,
1961 radv_queue_family_to_ring(
1962 queue->queue_family_index),
1963 queue->queue_idx);
1964
1965 if (!success) { /* Hang */
1966 radv_dump_trace(queue->device, cs_array[j]);
1967 abort();
1968 }
1969 }
1970 }
1971 free(cs_array);
1972 }
1973
1974 if (fence) {
1975 if (!fence_emitted)
1976 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1977 &queue->device->empty_cs[queue->queue_family_index],
1978 1, NULL, NULL, NULL, 0, NULL, 0,
1979 false, base_fence);
1980
1981 fence->submitted = true;
1982 }
1983
1984 return VK_SUCCESS;
1985 }
1986
1987 VkResult radv_QueueWaitIdle(
1988 VkQueue _queue)
1989 {
1990 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1991
1992 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1993 radv_queue_family_to_ring(queue->queue_family_index),
1994 queue->queue_idx);
1995 return VK_SUCCESS;
1996 }
1997
1998 VkResult radv_DeviceWaitIdle(
1999 VkDevice _device)
2000 {
2001 RADV_FROM_HANDLE(radv_device, device, _device);
2002
2003 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2004 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2005 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2006 }
2007 }
2008 return VK_SUCCESS;
2009 }
2010
2011 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2012 VkInstance instance,
2013 const char* pName)
2014 {
2015 return radv_lookup_entrypoint(pName);
2016 }
2017
2018 /* The loader wants us to expose a second GetInstanceProcAddr function
2019 * to work around certain LD_PRELOAD issues seen in apps.
2020 */
2021 PUBLIC
2022 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2023 VkInstance instance,
2024 const char* pName);
2025
2026 PUBLIC
2027 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2028 VkInstance instance,
2029 const char* pName)
2030 {
2031 return radv_GetInstanceProcAddr(instance, pName);
2032 }
2033
2034 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2035 VkDevice device,
2036 const char* pName)
2037 {
2038 return radv_lookup_entrypoint(pName);
2039 }
2040
2041 bool radv_get_memory_fd(struct radv_device *device,
2042 struct radv_device_memory *memory,
2043 int *pFD)
2044 {
2045 struct radeon_bo_metadata metadata;
2046
2047 if (memory->image) {
2048 radv_init_metadata(device, memory->image, &metadata);
2049 device->ws->buffer_set_metadata(memory->bo, &metadata);
2050 }
2051
2052 return device->ws->buffer_get_fd(device->ws, memory->bo,
2053 pFD);
2054 }
2055
2056 VkResult radv_AllocateMemory(
2057 VkDevice _device,
2058 const VkMemoryAllocateInfo* pAllocateInfo,
2059 const VkAllocationCallbacks* pAllocator,
2060 VkDeviceMemory* pMem)
2061 {
2062 RADV_FROM_HANDLE(radv_device, device, _device);
2063 struct radv_device_memory *mem;
2064 VkResult result;
2065 enum radeon_bo_domain domain;
2066 uint32_t flags = 0;
2067
2068 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2069
2070 if (pAllocateInfo->allocationSize == 0) {
2071 /* Apparently, this is allowed */
2072 *pMem = VK_NULL_HANDLE;
2073 return VK_SUCCESS;
2074 }
2075 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info =
2076 vk_find_struct_const(pAllocateInfo->pNext, DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV);
2077
2078 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2079 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2080 if (mem == NULL)
2081 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2082
2083 if (dedicate_info) {
2084 mem->image = radv_image_from_handle(dedicate_info->image);
2085 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2086 } else {
2087 mem->image = NULL;
2088 mem->buffer = NULL;
2089 }
2090
2091 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2092 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2093 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2094 domain = RADEON_DOMAIN_GTT;
2095 else
2096 domain = RADEON_DOMAIN_VRAM;
2097
2098 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2099 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2100 else
2101 flags |= RADEON_FLAG_CPU_ACCESS;
2102
2103 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2104 flags |= RADEON_FLAG_GTT_WC;
2105
2106 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2107 domain, flags);
2108
2109 if (!mem->bo) {
2110 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2111 goto fail;
2112 }
2113 mem->type_index = pAllocateInfo->memoryTypeIndex;
2114
2115 *pMem = radv_device_memory_to_handle(mem);
2116
2117 return VK_SUCCESS;
2118
2119 fail:
2120 vk_free2(&device->alloc, pAllocator, mem);
2121
2122 return result;
2123 }
2124
2125 void radv_FreeMemory(
2126 VkDevice _device,
2127 VkDeviceMemory _mem,
2128 const VkAllocationCallbacks* pAllocator)
2129 {
2130 RADV_FROM_HANDLE(radv_device, device, _device);
2131 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2132
2133 if (mem == NULL)
2134 return;
2135
2136 device->ws->buffer_destroy(mem->bo);
2137 mem->bo = NULL;
2138
2139 vk_free2(&device->alloc, pAllocator, mem);
2140 }
2141
2142 VkResult radv_MapMemory(
2143 VkDevice _device,
2144 VkDeviceMemory _memory,
2145 VkDeviceSize offset,
2146 VkDeviceSize size,
2147 VkMemoryMapFlags flags,
2148 void** ppData)
2149 {
2150 RADV_FROM_HANDLE(radv_device, device, _device);
2151 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2152
2153 if (mem == NULL) {
2154 *ppData = NULL;
2155 return VK_SUCCESS;
2156 }
2157
2158 *ppData = device->ws->buffer_map(mem->bo);
2159 if (*ppData) {
2160 *ppData += offset;
2161 return VK_SUCCESS;
2162 }
2163
2164 return VK_ERROR_MEMORY_MAP_FAILED;
2165 }
2166
2167 void radv_UnmapMemory(
2168 VkDevice _device,
2169 VkDeviceMemory _memory)
2170 {
2171 RADV_FROM_HANDLE(radv_device, device, _device);
2172 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2173
2174 if (mem == NULL)
2175 return;
2176
2177 device->ws->buffer_unmap(mem->bo);
2178 }
2179
2180 VkResult radv_FlushMappedMemoryRanges(
2181 VkDevice _device,
2182 uint32_t memoryRangeCount,
2183 const VkMappedMemoryRange* pMemoryRanges)
2184 {
2185 return VK_SUCCESS;
2186 }
2187
2188 VkResult radv_InvalidateMappedMemoryRanges(
2189 VkDevice _device,
2190 uint32_t memoryRangeCount,
2191 const VkMappedMemoryRange* pMemoryRanges)
2192 {
2193 return VK_SUCCESS;
2194 }
2195
2196 void radv_GetBufferMemoryRequirements(
2197 VkDevice device,
2198 VkBuffer _buffer,
2199 VkMemoryRequirements* pMemoryRequirements)
2200 {
2201 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2202
2203 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2204
2205 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2206 pMemoryRequirements->alignment = 4096;
2207 else
2208 pMemoryRequirements->alignment = 16;
2209
2210 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2211 }
2212
2213 void radv_GetBufferMemoryRequirements2KHR(
2214 VkDevice device,
2215 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
2216 VkMemoryRequirements2KHR* pMemoryRequirements)
2217 {
2218 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
2219 &pMemoryRequirements->memoryRequirements);
2220 }
2221
2222 void radv_GetImageMemoryRequirements(
2223 VkDevice device,
2224 VkImage _image,
2225 VkMemoryRequirements* pMemoryRequirements)
2226 {
2227 RADV_FROM_HANDLE(radv_image, image, _image);
2228
2229 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2230
2231 pMemoryRequirements->size = image->size;
2232 pMemoryRequirements->alignment = image->alignment;
2233 }
2234
2235 void radv_GetImageMemoryRequirements2KHR(
2236 VkDevice device,
2237 const VkImageMemoryRequirementsInfo2KHR* pInfo,
2238 VkMemoryRequirements2KHR* pMemoryRequirements)
2239 {
2240 radv_GetImageMemoryRequirements(device, pInfo->image,
2241 &pMemoryRequirements->memoryRequirements);
2242 }
2243
2244 void radv_GetImageSparseMemoryRequirements(
2245 VkDevice device,
2246 VkImage image,
2247 uint32_t* pSparseMemoryRequirementCount,
2248 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2249 {
2250 stub();
2251 }
2252
2253 void radv_GetImageSparseMemoryRequirements2KHR(
2254 VkDevice device,
2255 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
2256 uint32_t* pSparseMemoryRequirementCount,
2257 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
2258 {
2259 stub();
2260 }
2261
2262 void radv_GetDeviceMemoryCommitment(
2263 VkDevice device,
2264 VkDeviceMemory memory,
2265 VkDeviceSize* pCommittedMemoryInBytes)
2266 {
2267 *pCommittedMemoryInBytes = 0;
2268 }
2269
2270 VkResult radv_BindBufferMemory(
2271 VkDevice device,
2272 VkBuffer _buffer,
2273 VkDeviceMemory _memory,
2274 VkDeviceSize memoryOffset)
2275 {
2276 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2277 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2278
2279 if (mem) {
2280 buffer->bo = mem->bo;
2281 buffer->offset = memoryOffset;
2282 } else {
2283 buffer->bo = NULL;
2284 buffer->offset = 0;
2285 }
2286
2287 return VK_SUCCESS;
2288 }
2289
2290 VkResult radv_BindImageMemory(
2291 VkDevice device,
2292 VkImage _image,
2293 VkDeviceMemory _memory,
2294 VkDeviceSize memoryOffset)
2295 {
2296 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2297 RADV_FROM_HANDLE(radv_image, image, _image);
2298
2299 if (mem) {
2300 image->bo = mem->bo;
2301 image->offset = memoryOffset;
2302 } else {
2303 image->bo = NULL;
2304 image->offset = 0;
2305 }
2306
2307 return VK_SUCCESS;
2308 }
2309
2310
2311 static void
2312 radv_sparse_buffer_bind_memory(struct radv_device *device,
2313 const VkSparseBufferMemoryBindInfo *bind)
2314 {
2315 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2316
2317 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2318 struct radv_device_memory *mem = NULL;
2319
2320 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2321 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2322
2323 device->ws->buffer_virtual_bind(buffer->bo,
2324 bind->pBinds[i].resourceOffset,
2325 bind->pBinds[i].size,
2326 mem ? mem->bo : NULL,
2327 bind->pBinds[i].memoryOffset);
2328 }
2329 }
2330
2331 static void
2332 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2333 const VkSparseImageOpaqueMemoryBindInfo *bind)
2334 {
2335 RADV_FROM_HANDLE(radv_image, image, bind->image);
2336
2337 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2338 struct radv_device_memory *mem = NULL;
2339
2340 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2341 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2342
2343 device->ws->buffer_virtual_bind(image->bo,
2344 bind->pBinds[i].resourceOffset,
2345 bind->pBinds[i].size,
2346 mem ? mem->bo : NULL,
2347 bind->pBinds[i].memoryOffset);
2348 }
2349 }
2350
2351 VkResult radv_QueueBindSparse(
2352 VkQueue _queue,
2353 uint32_t bindInfoCount,
2354 const VkBindSparseInfo* pBindInfo,
2355 VkFence _fence)
2356 {
2357 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2358 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2359 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2360 bool fence_emitted = false;
2361
2362 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2363 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2364 radv_sparse_buffer_bind_memory(queue->device,
2365 pBindInfo[i].pBufferBinds + j);
2366 }
2367
2368 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2369 radv_sparse_image_opaque_bind_memory(queue->device,
2370 pBindInfo[i].pImageOpaqueBinds + j);
2371 }
2372
2373 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2374 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2375 &queue->device->empty_cs[queue->queue_family_index],
2376 1, NULL, NULL,
2377 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2378 pBindInfo[i].waitSemaphoreCount,
2379 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2380 pBindInfo[i].signalSemaphoreCount,
2381 false, base_fence);
2382 fence_emitted = true;
2383 if (fence)
2384 fence->submitted = true;
2385 }
2386 }
2387
2388 if (fence && !fence_emitted) {
2389 fence->signalled = true;
2390 }
2391
2392 return VK_SUCCESS;
2393 }
2394
2395 VkResult radv_CreateFence(
2396 VkDevice _device,
2397 const VkFenceCreateInfo* pCreateInfo,
2398 const VkAllocationCallbacks* pAllocator,
2399 VkFence* pFence)
2400 {
2401 RADV_FROM_HANDLE(radv_device, device, _device);
2402 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2403 sizeof(*fence), 8,
2404 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2405
2406 if (!fence)
2407 return VK_ERROR_OUT_OF_HOST_MEMORY;
2408
2409 memset(fence, 0, sizeof(*fence));
2410 fence->submitted = false;
2411 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2412 fence->fence = device->ws->create_fence();
2413 if (!fence->fence) {
2414 vk_free2(&device->alloc, pAllocator, fence);
2415 return VK_ERROR_OUT_OF_HOST_MEMORY;
2416 }
2417
2418 *pFence = radv_fence_to_handle(fence);
2419
2420 return VK_SUCCESS;
2421 }
2422
2423 void radv_DestroyFence(
2424 VkDevice _device,
2425 VkFence _fence,
2426 const VkAllocationCallbacks* pAllocator)
2427 {
2428 RADV_FROM_HANDLE(radv_device, device, _device);
2429 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2430
2431 if (!fence)
2432 return;
2433 device->ws->destroy_fence(fence->fence);
2434 vk_free2(&device->alloc, pAllocator, fence);
2435 }
2436
2437 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2438 {
2439 uint64_t current_time;
2440 struct timespec tv;
2441
2442 clock_gettime(CLOCK_MONOTONIC, &tv);
2443 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2444
2445 timeout = MIN2(UINT64_MAX - current_time, timeout);
2446
2447 return current_time + timeout;
2448 }
2449
2450 VkResult radv_WaitForFences(
2451 VkDevice _device,
2452 uint32_t fenceCount,
2453 const VkFence* pFences,
2454 VkBool32 waitAll,
2455 uint64_t timeout)
2456 {
2457 RADV_FROM_HANDLE(radv_device, device, _device);
2458 timeout = radv_get_absolute_timeout(timeout);
2459
2460 if (!waitAll && fenceCount > 1) {
2461 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2462 }
2463
2464 for (uint32_t i = 0; i < fenceCount; ++i) {
2465 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2466 bool expired = false;
2467
2468 if (fence->signalled)
2469 continue;
2470
2471 if (!fence->submitted)
2472 return VK_TIMEOUT;
2473
2474 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2475 if (!expired)
2476 return VK_TIMEOUT;
2477
2478 fence->signalled = true;
2479 }
2480
2481 return VK_SUCCESS;
2482 }
2483
2484 VkResult radv_ResetFences(VkDevice device,
2485 uint32_t fenceCount,
2486 const VkFence *pFences)
2487 {
2488 for (unsigned i = 0; i < fenceCount; ++i) {
2489 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2490 fence->submitted = fence->signalled = false;
2491 }
2492
2493 return VK_SUCCESS;
2494 }
2495
2496 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2497 {
2498 RADV_FROM_HANDLE(radv_device, device, _device);
2499 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2500
2501 if (fence->signalled)
2502 return VK_SUCCESS;
2503 if (!fence->submitted)
2504 return VK_NOT_READY;
2505
2506 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2507 return VK_NOT_READY;
2508
2509 return VK_SUCCESS;
2510 }
2511
2512
2513 // Queue semaphore functions
2514
2515 VkResult radv_CreateSemaphore(
2516 VkDevice _device,
2517 const VkSemaphoreCreateInfo* pCreateInfo,
2518 const VkAllocationCallbacks* pAllocator,
2519 VkSemaphore* pSemaphore)
2520 {
2521 RADV_FROM_HANDLE(radv_device, device, _device);
2522 struct radeon_winsys_sem *sem;
2523
2524 sem = device->ws->create_sem(device->ws);
2525 if (!sem)
2526 return VK_ERROR_OUT_OF_HOST_MEMORY;
2527
2528 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2529 return VK_SUCCESS;
2530 }
2531
2532 void radv_DestroySemaphore(
2533 VkDevice _device,
2534 VkSemaphore _semaphore,
2535 const VkAllocationCallbacks* pAllocator)
2536 {
2537 RADV_FROM_HANDLE(radv_device, device, _device);
2538 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2539 if (!_semaphore)
2540 return;
2541
2542 device->ws->destroy_sem(sem);
2543 }
2544
2545 VkResult radv_CreateEvent(
2546 VkDevice _device,
2547 const VkEventCreateInfo* pCreateInfo,
2548 const VkAllocationCallbacks* pAllocator,
2549 VkEvent* pEvent)
2550 {
2551 RADV_FROM_HANDLE(radv_device, device, _device);
2552 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2553 sizeof(*event), 8,
2554 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2555
2556 if (!event)
2557 return VK_ERROR_OUT_OF_HOST_MEMORY;
2558
2559 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2560 RADEON_DOMAIN_GTT,
2561 RADEON_FLAG_CPU_ACCESS);
2562 if (!event->bo) {
2563 vk_free2(&device->alloc, pAllocator, event);
2564 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2565 }
2566
2567 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2568
2569 *pEvent = radv_event_to_handle(event);
2570
2571 return VK_SUCCESS;
2572 }
2573
2574 void radv_DestroyEvent(
2575 VkDevice _device,
2576 VkEvent _event,
2577 const VkAllocationCallbacks* pAllocator)
2578 {
2579 RADV_FROM_HANDLE(radv_device, device, _device);
2580 RADV_FROM_HANDLE(radv_event, event, _event);
2581
2582 if (!event)
2583 return;
2584 device->ws->buffer_destroy(event->bo);
2585 vk_free2(&device->alloc, pAllocator, event);
2586 }
2587
2588 VkResult radv_GetEventStatus(
2589 VkDevice _device,
2590 VkEvent _event)
2591 {
2592 RADV_FROM_HANDLE(radv_event, event, _event);
2593
2594 if (*event->map == 1)
2595 return VK_EVENT_SET;
2596 return VK_EVENT_RESET;
2597 }
2598
2599 VkResult radv_SetEvent(
2600 VkDevice _device,
2601 VkEvent _event)
2602 {
2603 RADV_FROM_HANDLE(radv_event, event, _event);
2604 *event->map = 1;
2605
2606 return VK_SUCCESS;
2607 }
2608
2609 VkResult radv_ResetEvent(
2610 VkDevice _device,
2611 VkEvent _event)
2612 {
2613 RADV_FROM_HANDLE(radv_event, event, _event);
2614 *event->map = 0;
2615
2616 return VK_SUCCESS;
2617 }
2618
2619 VkResult radv_CreateBuffer(
2620 VkDevice _device,
2621 const VkBufferCreateInfo* pCreateInfo,
2622 const VkAllocationCallbacks* pAllocator,
2623 VkBuffer* pBuffer)
2624 {
2625 RADV_FROM_HANDLE(radv_device, device, _device);
2626 struct radv_buffer *buffer;
2627
2628 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2629
2630 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2631 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2632 if (buffer == NULL)
2633 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2634
2635 buffer->size = pCreateInfo->size;
2636 buffer->usage = pCreateInfo->usage;
2637 buffer->bo = NULL;
2638 buffer->offset = 0;
2639 buffer->flags = pCreateInfo->flags;
2640
2641 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2642 buffer->bo = device->ws->buffer_create(device->ws,
2643 align64(buffer->size, 4096),
2644 4096, 0, RADEON_FLAG_VIRTUAL);
2645 if (!buffer->bo) {
2646 vk_free2(&device->alloc, pAllocator, buffer);
2647 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2648 }
2649 }
2650
2651 *pBuffer = radv_buffer_to_handle(buffer);
2652
2653 return VK_SUCCESS;
2654 }
2655
2656 void radv_DestroyBuffer(
2657 VkDevice _device,
2658 VkBuffer _buffer,
2659 const VkAllocationCallbacks* pAllocator)
2660 {
2661 RADV_FROM_HANDLE(radv_device, device, _device);
2662 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2663
2664 if (!buffer)
2665 return;
2666
2667 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2668 device->ws->buffer_destroy(buffer->bo);
2669
2670 vk_free2(&device->alloc, pAllocator, buffer);
2671 }
2672
2673 static inline unsigned
2674 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2675 {
2676 if (stencil)
2677 return image->surface.u.legacy.stencil_tiling_index[level];
2678 else
2679 return image->surface.u.legacy.tiling_index[level];
2680 }
2681
2682 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2683 {
2684 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2685 }
2686
2687 static void
2688 radv_initialise_color_surface(struct radv_device *device,
2689 struct radv_color_buffer_info *cb,
2690 struct radv_image_view *iview)
2691 {
2692 const struct vk_format_description *desc;
2693 unsigned ntype, format, swap, endian;
2694 unsigned blend_clamp = 0, blend_bypass = 0;
2695 uint64_t va;
2696 const struct radeon_surf *surf = &iview->image->surface;
2697
2698 desc = vk_format_description(iview->vk_format);
2699
2700 memset(cb, 0, sizeof(*cb));
2701
2702 /* Intensity is implemented as Red, so treat it that way. */
2703 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2704
2705 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2706
2707 if (device->physical_device->rad_info.chip_class >= GFX9) {
2708 struct gfx9_surf_meta_flags meta;
2709 if (iview->image->dcc_offset)
2710 meta = iview->image->surface.u.gfx9.dcc;
2711 else
2712 meta = iview->image->surface.u.gfx9.cmask;
2713
2714 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2715 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
2716 S_028C74_RB_ALIGNED(meta.rb_aligned) |
2717 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
2718
2719 va += iview->image->surface.u.gfx9.surf_offset >> 8;
2720 } else {
2721 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2722 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2723
2724 va += level_info->offset;
2725
2726 pitch_tile_max = level_info->nblk_x / 8 - 1;
2727 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2728 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2729
2730 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2731 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2732 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2733
2734 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2735 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2736
2737 if (iview->image->fmask.size) {
2738 if (device->physical_device->rad_info.chip_class >= CIK)
2739 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2740 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2741 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2742 } else {
2743 /* This must be set for fast clear to work without FMASK. */
2744 if (device->physical_device->rad_info.chip_class >= CIK)
2745 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2746 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2747 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2748 }
2749 }
2750
2751 cb->cb_color_base = va >> 8;
2752
2753 /* CMASK variables */
2754 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2755 va += iview->image->cmask.offset;
2756 cb->cb_color_cmask = va >> 8;
2757
2758 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2759 va += iview->image->dcc_offset;
2760 cb->cb_dcc_base = va >> 8;
2761
2762 uint32_t max_slice = radv_surface_layer_count(iview);
2763 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2764 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2765
2766 if (iview->image->info.samples > 1) {
2767 unsigned log_samples = util_logbase2(iview->image->info.samples);
2768
2769 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2770 S_028C74_NUM_FRAGMENTS(log_samples);
2771 }
2772
2773 if (iview->image->fmask.size) {
2774 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2775 cb->cb_color_fmask = va >> 8;
2776 } else {
2777 cb->cb_color_fmask = cb->cb_color_base;
2778 }
2779
2780 ntype = radv_translate_color_numformat(iview->vk_format,
2781 desc,
2782 vk_format_get_first_non_void_channel(iview->vk_format));
2783 format = radv_translate_colorformat(iview->vk_format);
2784 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2785 radv_finishme("Illegal color\n");
2786 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2787 endian = radv_colorformat_endian_swap(format);
2788
2789 /* blend clamp should be set for all NORM/SRGB types */
2790 if (ntype == V_028C70_NUMBER_UNORM ||
2791 ntype == V_028C70_NUMBER_SNORM ||
2792 ntype == V_028C70_NUMBER_SRGB)
2793 blend_clamp = 1;
2794
2795 /* set blend bypass according to docs if SINT/UINT or
2796 8/24 COLOR variants */
2797 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2798 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2799 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2800 blend_clamp = 0;
2801 blend_bypass = 1;
2802 }
2803 #if 0
2804 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2805 (format == V_028C70_COLOR_8 ||
2806 format == V_028C70_COLOR_8_8 ||
2807 format == V_028C70_COLOR_8_8_8_8))
2808 ->color_is_int8 = true;
2809 #endif
2810 cb->cb_color_info = S_028C70_FORMAT(format) |
2811 S_028C70_COMP_SWAP(swap) |
2812 S_028C70_BLEND_CLAMP(blend_clamp) |
2813 S_028C70_BLEND_BYPASS(blend_bypass) |
2814 S_028C70_SIMPLE_FLOAT(1) |
2815 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2816 ntype != V_028C70_NUMBER_SNORM &&
2817 ntype != V_028C70_NUMBER_SRGB &&
2818 format != V_028C70_COLOR_8_24 &&
2819 format != V_028C70_COLOR_24_8) |
2820 S_028C70_NUMBER_TYPE(ntype) |
2821 S_028C70_ENDIAN(endian);
2822 if (iview->image->info.samples > 1)
2823 if (iview->image->fmask.size)
2824 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2825
2826 if (iview->image->cmask.size &&
2827 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2828 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2829
2830 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
2831 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2832
2833 if (device->physical_device->rad_info.chip_class >= VI) {
2834 unsigned max_uncompressed_block_size = 2;
2835 if (iview->image->info.samples > 1) {
2836 if (iview->image->surface.bpe == 1)
2837 max_uncompressed_block_size = 0;
2838 else if (iview->image->surface.bpe == 2)
2839 max_uncompressed_block_size = 1;
2840 }
2841
2842 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2843 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2844 }
2845
2846 /* This must be set for fast clear to work without FMASK. */
2847 if (!iview->image->fmask.size &&
2848 device->physical_device->rad_info.chip_class == SI) {
2849 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
2850 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2851 }
2852
2853 if (device->physical_device->rad_info.chip_class >= GFX9) {
2854 uint32_t max_slice = radv_surface_layer_count(iview);
2855 unsigned mip0_depth = iview->base_layer + max_slice - 1;
2856
2857 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
2858 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
2859 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
2860 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->image->info.width - 1) |
2861 S_028C68_MIP0_HEIGHT(iview->image->info.height - 1) |
2862 S_028C68_MAX_MIP(iview->image->info.levels);
2863
2864 cb->gfx9_epitch = S_0287A0_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
2865
2866 }
2867 }
2868
2869 static void
2870 radv_initialise_ds_surface(struct radv_device *device,
2871 struct radv_ds_buffer_info *ds,
2872 struct radv_image_view *iview)
2873 {
2874 unsigned level = iview->base_mip;
2875 unsigned format, stencil_format;
2876 uint64_t va, s_offs, z_offs;
2877 bool stencil_only = false;
2878 memset(ds, 0, sizeof(*ds));
2879 switch (iview->image->vk_format) {
2880 case VK_FORMAT_D24_UNORM_S8_UINT:
2881 case VK_FORMAT_X8_D24_UNORM_PACK32:
2882 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2883 ds->offset_scale = 2.0f;
2884 break;
2885 case VK_FORMAT_D16_UNORM:
2886 case VK_FORMAT_D16_UNORM_S8_UINT:
2887 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2888 ds->offset_scale = 4.0f;
2889 break;
2890 case VK_FORMAT_D32_SFLOAT:
2891 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2892 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2893 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2894 ds->offset_scale = 1.0f;
2895 break;
2896 case VK_FORMAT_S8_UINT:
2897 stencil_only = true;
2898 break;
2899 default:
2900 break;
2901 }
2902
2903 format = radv_translate_dbformat(iview->image->vk_format);
2904 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
2905 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2906
2907 uint32_t max_slice = radv_surface_layer_count(iview);
2908 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2909 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2910
2911 ds->db_htile_data_base = 0;
2912 ds->db_htile_surface = 0;
2913
2914 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2915 s_offs = z_offs = va;
2916
2917 if (device->physical_device->rad_info.chip_class >= GFX9) {
2918 assert(iview->image->surface.u.gfx9.surf_offset == 0);
2919 s_offs += iview->image->surface.u.gfx9.stencil_offset;
2920
2921 ds->db_z_info = S_028038_FORMAT(format) |
2922 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
2923 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
2924 S_028038_MAXMIP(iview->image->info.levels - 1);
2925 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
2926 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
2927
2928 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
2929 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
2930 ds->db_depth_view |= S_028008_MIPID(level);
2931
2932 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
2933 S_02801C_Y_MAX(iview->image->info.height - 1);
2934
2935 /* Only use HTILE for the first level. */
2936 if (iview->image->surface.htile_size && !level) {
2937 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
2938
2939 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
2940 /* Use all of the htile_buffer for depth if there's no stencil. */
2941 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
2942 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2943 iview->image->htile_offset;
2944 ds->db_htile_data_base = va >> 8;
2945 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
2946 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
2947 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
2948 }
2949 } else {
2950 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
2951
2952 if (stencil_only)
2953 level_info = &iview->image->surface.u.legacy.stencil_level[level];
2954
2955 z_offs += iview->image->surface.u.legacy.level[level].offset;
2956 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
2957
2958 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2959 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2960 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
2961
2962 if (iview->image->info.samples > 1)
2963 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
2964
2965 if (device->physical_device->rad_info.chip_class >= CIK) {
2966 struct radeon_info *info = &device->physical_device->rad_info;
2967 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
2968 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
2969 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
2970 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2971 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2972 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2973
2974 if (stencil_only)
2975 tile_mode = stencil_tile_mode;
2976
2977 ds->db_depth_info |=
2978 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2979 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2980 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2981 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2982 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2983 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2984 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2985 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2986 } else {
2987 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2988 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2989 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2990 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2991 }
2992
2993 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2994 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2995 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2996
2997 if (iview->image->surface.htile_size && !level) {
2998 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
2999
3000 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
3001 /* Use all of the htile_buffer for depth if there's no stencil. */
3002 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
3003
3004 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
3005 iview->image->htile_offset;
3006 ds->db_htile_data_base = va >> 8;
3007 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
3008 }
3009 }
3010
3011 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
3012 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
3013 }
3014
3015 VkResult radv_CreateFramebuffer(
3016 VkDevice _device,
3017 const VkFramebufferCreateInfo* pCreateInfo,
3018 const VkAllocationCallbacks* pAllocator,
3019 VkFramebuffer* pFramebuffer)
3020 {
3021 RADV_FROM_HANDLE(radv_device, device, _device);
3022 struct radv_framebuffer *framebuffer;
3023
3024 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
3025
3026 size_t size = sizeof(*framebuffer) +
3027 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
3028 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
3029 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3030 if (framebuffer == NULL)
3031 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3032
3033 framebuffer->attachment_count = pCreateInfo->attachmentCount;
3034 framebuffer->width = pCreateInfo->width;
3035 framebuffer->height = pCreateInfo->height;
3036 framebuffer->layers = pCreateInfo->layers;
3037 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
3038 VkImageView _iview = pCreateInfo->pAttachments[i];
3039 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
3040 framebuffer->attachments[i].attachment = iview;
3041 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
3042 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
3043 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
3044 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
3045 }
3046 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
3047 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
3048 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
3049 }
3050
3051 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
3052 return VK_SUCCESS;
3053 }
3054
3055 void radv_DestroyFramebuffer(
3056 VkDevice _device,
3057 VkFramebuffer _fb,
3058 const VkAllocationCallbacks* pAllocator)
3059 {
3060 RADV_FROM_HANDLE(radv_device, device, _device);
3061 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
3062
3063 if (!fb)
3064 return;
3065 vk_free2(&device->alloc, pAllocator, fb);
3066 }
3067
3068 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3069 {
3070 switch (address_mode) {
3071 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3072 return V_008F30_SQ_TEX_WRAP;
3073 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3074 return V_008F30_SQ_TEX_MIRROR;
3075 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3076 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3077 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3078 return V_008F30_SQ_TEX_CLAMP_BORDER;
3079 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3080 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3081 default:
3082 unreachable("illegal tex wrap mode");
3083 break;
3084 }
3085 }
3086
3087 static unsigned
3088 radv_tex_compare(VkCompareOp op)
3089 {
3090 switch (op) {
3091 case VK_COMPARE_OP_NEVER:
3092 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3093 case VK_COMPARE_OP_LESS:
3094 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3095 case VK_COMPARE_OP_EQUAL:
3096 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3097 case VK_COMPARE_OP_LESS_OR_EQUAL:
3098 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3099 case VK_COMPARE_OP_GREATER:
3100 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3101 case VK_COMPARE_OP_NOT_EQUAL:
3102 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3103 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3104 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3105 case VK_COMPARE_OP_ALWAYS:
3106 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3107 default:
3108 unreachable("illegal compare mode");
3109 break;
3110 }
3111 }
3112
3113 static unsigned
3114 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3115 {
3116 switch (filter) {
3117 case VK_FILTER_NEAREST:
3118 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3119 V_008F38_SQ_TEX_XY_FILTER_POINT);
3120 case VK_FILTER_LINEAR:
3121 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3122 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3123 case VK_FILTER_CUBIC_IMG:
3124 default:
3125 fprintf(stderr, "illegal texture filter");
3126 return 0;
3127 }
3128 }
3129
3130 static unsigned
3131 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3132 {
3133 switch (mode) {
3134 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3135 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3136 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3137 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3138 default:
3139 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3140 }
3141 }
3142
3143 static unsigned
3144 radv_tex_bordercolor(VkBorderColor bcolor)
3145 {
3146 switch (bcolor) {
3147 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3148 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3149 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3150 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3151 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3152 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3153 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3154 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3155 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3156 default:
3157 break;
3158 }
3159 return 0;
3160 }
3161
3162 static unsigned
3163 radv_tex_aniso_filter(unsigned filter)
3164 {
3165 if (filter < 2)
3166 return 0;
3167 if (filter < 4)
3168 return 1;
3169 if (filter < 8)
3170 return 2;
3171 if (filter < 16)
3172 return 3;
3173 return 4;
3174 }
3175
3176 static void
3177 radv_init_sampler(struct radv_device *device,
3178 struct radv_sampler *sampler,
3179 const VkSamplerCreateInfo *pCreateInfo)
3180 {
3181 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3182 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3183 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3184 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3185
3186 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3187 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3188 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3189 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3190 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3191 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3192 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3193 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3194 S_008F30_DISABLE_CUBE_WRAP(0) |
3195 S_008F30_COMPAT_MODE(is_vi));
3196 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3197 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3198 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3199 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3200 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3201 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3202 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3203 S_008F38_MIP_POINT_PRECLAMP(0) |
3204 S_008F38_DISABLE_LSB_CEIL(1) |
3205 S_008F38_FILTER_PREC_FIX(1) |
3206 S_008F38_ANISO_OVERRIDE(is_vi));
3207 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3208 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3209 }
3210
3211 VkResult radv_CreateSampler(
3212 VkDevice _device,
3213 const VkSamplerCreateInfo* pCreateInfo,
3214 const VkAllocationCallbacks* pAllocator,
3215 VkSampler* pSampler)
3216 {
3217 RADV_FROM_HANDLE(radv_device, device, _device);
3218 struct radv_sampler *sampler;
3219
3220 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3221
3222 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3223 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3224 if (!sampler)
3225 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3226
3227 radv_init_sampler(device, sampler, pCreateInfo);
3228 *pSampler = radv_sampler_to_handle(sampler);
3229
3230 return VK_SUCCESS;
3231 }
3232
3233 void radv_DestroySampler(
3234 VkDevice _device,
3235 VkSampler _sampler,
3236 const VkAllocationCallbacks* pAllocator)
3237 {
3238 RADV_FROM_HANDLE(radv_device, device, _device);
3239 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3240
3241 if (!sampler)
3242 return;
3243 vk_free2(&device->alloc, pAllocator, sampler);
3244 }
3245
3246 /* vk_icd.h does not declare this function, so we declare it here to
3247 * suppress Wmissing-prototypes.
3248 */
3249 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3250 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3251
3252 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3253 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3254 {
3255 /* For the full details on loader interface versioning, see
3256 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3257 * What follows is a condensed summary, to help you navigate the large and
3258 * confusing official doc.
3259 *
3260 * - Loader interface v0 is incompatible with later versions. We don't
3261 * support it.
3262 *
3263 * - In loader interface v1:
3264 * - The first ICD entrypoint called by the loader is
3265 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3266 * entrypoint.
3267 * - The ICD must statically expose no other Vulkan symbol unless it is
3268 * linked with -Bsymbolic.
3269 * - Each dispatchable Vulkan handle created by the ICD must be
3270 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3271 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3272 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3273 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3274 * such loader-managed surfaces.
3275 *
3276 * - Loader interface v2 differs from v1 in:
3277 * - The first ICD entrypoint called by the loader is
3278 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3279 * statically expose this entrypoint.
3280 *
3281 * - Loader interface v3 differs from v2 in:
3282 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3283 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3284 * because the loader no longer does so.
3285 */
3286 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3287 return VK_SUCCESS;
3288 }