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radv: set offchip hs param like radeonsi.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "util/disk_cache.h"
35 #include "util/strtod.h"
36 #include "util/vk_util.h"
37 #include <xf86drm.h>
38 #include <amdgpu.h>
39 #include <amdgpu_drm.h>
40 #include "amdgpu_id.h"
41 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
42 #include "ac_llvm_util.h"
43 #include "vk_format.h"
44 #include "sid.h"
45 #include "util/debug.h"
46
47 static int
48 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
49 {
50 uint32_t mesa_timestamp, llvm_timestamp;
51 uint16_t f = family;
52 memset(uuid, 0, VK_UUID_SIZE);
53 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
54 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
55 return -1;
56
57 memcpy(uuid, &mesa_timestamp, 4);
58 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
59 memcpy((char*)uuid + 8, &f, 2);
60 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv");
61 return 0;
62 }
63
64 static void
65 radv_get_device_uuid(drmDevicePtr device, void *uuid) {
66 memset(uuid, 0, VK_UUID_SIZE);
67 memcpy((char*)uuid + 0, &device->businfo.pci->domain, 2);
68 memcpy((char*)uuid + 2, &device->businfo.pci->bus, 1);
69 memcpy((char*)uuid + 3, &device->businfo.pci->dev, 1);
70 memcpy((char*)uuid + 4, &device->businfo.pci->func, 1);
71 }
72
73 static const VkExtensionProperties instance_extensions[] = {
74 {
75 .extensionName = VK_KHR_SURFACE_EXTENSION_NAME,
76 .specVersion = 25,
77 },
78 #ifdef VK_USE_PLATFORM_XCB_KHR
79 {
80 .extensionName = VK_KHR_XCB_SURFACE_EXTENSION_NAME,
81 .specVersion = 6,
82 },
83 #endif
84 #ifdef VK_USE_PLATFORM_XLIB_KHR
85 {
86 .extensionName = VK_KHR_XLIB_SURFACE_EXTENSION_NAME,
87 .specVersion = 6,
88 },
89 #endif
90 #ifdef VK_USE_PLATFORM_WAYLAND_KHR
91 {
92 .extensionName = VK_KHR_WAYLAND_SURFACE_EXTENSION_NAME,
93 .specVersion = 5,
94 },
95 #endif
96 {
97 .extensionName = VK_KHR_GET_PHYSICAL_DEVICE_PROPERTIES_2_EXTENSION_NAME,
98 .specVersion = 1,
99 },
100 {
101 .extensionName = VK_KHX_EXTERNAL_MEMORY_CAPABILITIES_EXTENSION_NAME,
102 .specVersion = 1,
103 },
104 };
105
106 static const VkExtensionProperties common_device_extensions[] = {
107 {
108 .extensionName = VK_KHR_DESCRIPTOR_UPDATE_TEMPLATE_EXTENSION_NAME,
109 .specVersion = 1,
110 },
111 {
112 .extensionName = VK_KHR_INCREMENTAL_PRESENT_EXTENSION_NAME,
113 .specVersion = 1,
114 },
115 {
116 .extensionName = VK_KHR_MAINTENANCE1_EXTENSION_NAME,
117 .specVersion = 1,
118 },
119 {
120 .extensionName = VK_KHR_PUSH_DESCRIPTOR_EXTENSION_NAME,
121 .specVersion = 1,
122 },
123 {
124 .extensionName = VK_KHR_SAMPLER_MIRROR_CLAMP_TO_EDGE_EXTENSION_NAME,
125 .specVersion = 1,
126 },
127 {
128 .extensionName = VK_KHR_SWAPCHAIN_EXTENSION_NAME,
129 .specVersion = 68,
130 },
131 {
132 .extensionName = VK_AMD_DRAW_INDIRECT_COUNT_EXTENSION_NAME,
133 .specVersion = 1,
134 },
135 {
136 .extensionName = VK_KHR_SHADER_DRAW_PARAMETERS_EXTENSION_NAME,
137 .specVersion = 1,
138 },
139 {
140 .extensionName = VK_NV_DEDICATED_ALLOCATION_EXTENSION_NAME,
141 .specVersion = 1,
142 },
143 {
144 .extensionName = VK_KHX_EXTERNAL_MEMORY_EXTENSION_NAME,
145 .specVersion = 1,
146 },
147 {
148 .extensionName = VK_KHX_EXTERNAL_MEMORY_FD_EXTENSION_NAME,
149 .specVersion = 1,
150 },
151 };
152
153 static VkResult
154 radv_extensions_register(struct radv_instance *instance,
155 struct radv_extensions *extensions,
156 const VkExtensionProperties *new_ext,
157 uint32_t num_ext)
158 {
159 size_t new_size;
160 VkExtensionProperties *new_ptr;
161
162 assert(new_ext && num_ext > 0);
163
164 if (!new_ext)
165 return VK_ERROR_INITIALIZATION_FAILED;
166
167 new_size = (extensions->num_ext + num_ext) * sizeof(VkExtensionProperties);
168 new_ptr = vk_realloc(&instance->alloc, extensions->ext_array,
169 new_size, 8, VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
170
171 /* Old array continues to be valid, update nothing */
172 if (!new_ptr)
173 return VK_ERROR_OUT_OF_HOST_MEMORY;
174
175 memcpy(&new_ptr[extensions->num_ext], new_ext,
176 num_ext * sizeof(VkExtensionProperties));
177 extensions->ext_array = new_ptr;
178 extensions->num_ext += num_ext;
179
180 return VK_SUCCESS;
181 }
182
183 static void
184 radv_extensions_finish(struct radv_instance *instance,
185 struct radv_extensions *extensions)
186 {
187 assert(extensions);
188
189 if (!extensions)
190 radv_loge("Attemted to free invalid extension struct\n");
191
192 if (extensions->ext_array)
193 vk_free(&instance->alloc, extensions->ext_array);
194 }
195
196 static bool
197 is_extension_enabled(const VkExtensionProperties *extensions,
198 size_t num_ext,
199 const char *name)
200 {
201 assert(extensions && name);
202
203 for (uint32_t i = 0; i < num_ext; i++) {
204 if (strcmp(name, extensions[i].extensionName) == 0)
205 return true;
206 }
207
208 return false;
209 }
210
211 static const char *
212 get_chip_name(enum radeon_family family)
213 {
214 switch (family) {
215 case CHIP_TAHITI: return "AMD RADV TAHITI";
216 case CHIP_PITCAIRN: return "AMD RADV PITCAIRN";
217 case CHIP_VERDE: return "AMD RADV CAPE VERDE";
218 case CHIP_OLAND: return "AMD RADV OLAND";
219 case CHIP_HAINAN: return "AMD RADV HAINAN";
220 case CHIP_BONAIRE: return "AMD RADV BONAIRE";
221 case CHIP_KAVERI: return "AMD RADV KAVERI";
222 case CHIP_KABINI: return "AMD RADV KABINI";
223 case CHIP_HAWAII: return "AMD RADV HAWAII";
224 case CHIP_MULLINS: return "AMD RADV MULLINS";
225 case CHIP_TONGA: return "AMD RADV TONGA";
226 case CHIP_ICELAND: return "AMD RADV ICELAND";
227 case CHIP_CARRIZO: return "AMD RADV CARRIZO";
228 case CHIP_FIJI: return "AMD RADV FIJI";
229 case CHIP_POLARIS10: return "AMD RADV POLARIS10";
230 case CHIP_POLARIS11: return "AMD RADV POLARIS11";
231 case CHIP_POLARIS12: return "AMD RADV POLARIS12";
232 case CHIP_STONEY: return "AMD RADV STONEY";
233 default: return "AMD RADV unknown";
234 }
235 }
236
237 static VkResult
238 radv_physical_device_init(struct radv_physical_device *device,
239 struct radv_instance *instance,
240 drmDevicePtr drm_device)
241 {
242 const char *path = drm_device->nodes[DRM_NODE_RENDER];
243 VkResult result;
244 drmVersionPtr version;
245 int fd;
246
247 fd = open(path, O_RDWR | O_CLOEXEC);
248 if (fd < 0)
249 return VK_ERROR_INCOMPATIBLE_DRIVER;
250
251 version = drmGetVersion(fd);
252 if (!version) {
253 close(fd);
254 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
255 "failed to get version %s: %m", path);
256 }
257
258 if (strcmp(version->name, "amdgpu")) {
259 drmFreeVersion(version);
260 close(fd);
261 return VK_ERROR_INCOMPATIBLE_DRIVER;
262 }
263 drmFreeVersion(version);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags);
271 if (!device->ws) {
272 result = VK_ERROR_INCOMPATIBLE_DRIVER;
273 goto fail;
274 }
275
276 device->local_fd = fd;
277 device->ws->query_info(device->ws, &device->rad_info);
278 result = radv_init_wsi(device);
279 if (result != VK_SUCCESS) {
280 device->ws->destroy(device->ws);
281 goto fail;
282 }
283
284 if (radv_device_get_cache_uuid(device->rad_info.family, device->uuid)) {
285 radv_finish_wsi(device);
286 device->ws->destroy(device->ws);
287 result = vk_errorf(VK_ERROR_INITIALIZATION_FAILED,
288 "cannot generate UUID");
289 goto fail;
290 }
291
292 result = radv_extensions_register(instance,
293 &device->extensions,
294 common_device_extensions,
295 ARRAY_SIZE(common_device_extensions));
296 if (result != VK_SUCCESS)
297 goto fail;
298
299 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
300 device->name = get_chip_name(device->rad_info.family);
301
302 radv_get_device_uuid(drm_device, device->device_uuid);
303
304 return VK_SUCCESS;
305
306 fail:
307 close(fd);
308 return result;
309 }
310
311 static void
312 radv_physical_device_finish(struct radv_physical_device *device)
313 {
314 radv_extensions_finish(device->instance, &device->extensions);
315 radv_finish_wsi(device);
316 device->ws->destroy(device->ws);
317 close(device->local_fd);
318 }
319
320 static void *
321 default_alloc_func(void *pUserData, size_t size, size_t align,
322 VkSystemAllocationScope allocationScope)
323 {
324 return malloc(size);
325 }
326
327 static void *
328 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
329 size_t align, VkSystemAllocationScope allocationScope)
330 {
331 return realloc(pOriginal, size);
332 }
333
334 static void
335 default_free_func(void *pUserData, void *pMemory)
336 {
337 free(pMemory);
338 }
339
340 static const VkAllocationCallbacks default_alloc = {
341 .pUserData = NULL,
342 .pfnAllocation = default_alloc_func,
343 .pfnReallocation = default_realloc_func,
344 .pfnFree = default_free_func,
345 };
346
347 static const struct debug_control radv_debug_options[] = {
348 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
349 {"nodcc", RADV_DEBUG_NO_DCC},
350 {"shaders", RADV_DEBUG_DUMP_SHADERS},
351 {"nocache", RADV_DEBUG_NO_CACHE},
352 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
353 {"nohiz", RADV_DEBUG_NO_HIZ},
354 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
355 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
356 {"allbos", RADV_DEBUG_ALL_BOS},
357 {"noibs", RADV_DEBUG_NO_IBS},
358 {NULL, 0}
359 };
360
361 VkResult radv_CreateInstance(
362 const VkInstanceCreateInfo* pCreateInfo,
363 const VkAllocationCallbacks* pAllocator,
364 VkInstance* pInstance)
365 {
366 struct radv_instance *instance;
367
368 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
369
370 uint32_t client_version;
371 if (pCreateInfo->pApplicationInfo &&
372 pCreateInfo->pApplicationInfo->apiVersion != 0) {
373 client_version = pCreateInfo->pApplicationInfo->apiVersion;
374 } else {
375 client_version = VK_MAKE_VERSION(1, 0, 0);
376 }
377
378 if (VK_MAKE_VERSION(1, 0, 0) > client_version ||
379 client_version > VK_MAKE_VERSION(1, 0, 0xfff)) {
380 return vk_errorf(VK_ERROR_INCOMPATIBLE_DRIVER,
381 "Client requested version %d.%d.%d",
382 VK_VERSION_MAJOR(client_version),
383 VK_VERSION_MINOR(client_version),
384 VK_VERSION_PATCH(client_version));
385 }
386
387 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
388 if (!is_extension_enabled(instance_extensions,
389 ARRAY_SIZE(instance_extensions),
390 pCreateInfo->ppEnabledExtensionNames[i]))
391 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
392 }
393
394 instance = vk_alloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
395 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
396 if (!instance)
397 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
398
399 memset(instance, 0, sizeof(*instance));
400
401 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
402
403 if (pAllocator)
404 instance->alloc = *pAllocator;
405 else
406 instance->alloc = default_alloc;
407
408 instance->apiVersion = client_version;
409 instance->physicalDeviceCount = -1;
410
411 _mesa_locale_init();
412
413 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
414
415 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
416 radv_debug_options);
417
418 *pInstance = radv_instance_to_handle(instance);
419
420 return VK_SUCCESS;
421 }
422
423 void radv_DestroyInstance(
424 VkInstance _instance,
425 const VkAllocationCallbacks* pAllocator)
426 {
427 RADV_FROM_HANDLE(radv_instance, instance, _instance);
428
429 if (!instance)
430 return;
431
432 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
433 radv_physical_device_finish(instance->physicalDevices + i);
434 }
435
436 VG(VALGRIND_DESTROY_MEMPOOL(instance));
437
438 _mesa_locale_fini();
439
440 vk_free(&instance->alloc, instance);
441 }
442
443 static VkResult
444 radv_enumerate_devices(struct radv_instance *instance)
445 {
446 /* TODO: Check for more devices ? */
447 drmDevicePtr devices[8];
448 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
449 int max_devices;
450
451 instance->physicalDeviceCount = 0;
452
453 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
454 if (max_devices < 1)
455 return VK_ERROR_INCOMPATIBLE_DRIVER;
456
457 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
458 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
459 devices[i]->bustype == DRM_BUS_PCI &&
460 devices[i]->deviceinfo.pci->vendor_id == 0x1002) {
461
462 result = radv_physical_device_init(instance->physicalDevices +
463 instance->physicalDeviceCount,
464 instance,
465 devices[i]);
466 if (result == VK_SUCCESS)
467 ++instance->physicalDeviceCount;
468 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
469 break;
470 }
471 }
472 drmFreeDevices(devices, max_devices);
473
474 return result;
475 }
476
477 VkResult radv_EnumeratePhysicalDevices(
478 VkInstance _instance,
479 uint32_t* pPhysicalDeviceCount,
480 VkPhysicalDevice* pPhysicalDevices)
481 {
482 RADV_FROM_HANDLE(radv_instance, instance, _instance);
483 VkResult result;
484
485 if (instance->physicalDeviceCount < 0) {
486 result = radv_enumerate_devices(instance);
487 if (result != VK_SUCCESS &&
488 result != VK_ERROR_INCOMPATIBLE_DRIVER)
489 return result;
490 }
491
492 if (!pPhysicalDevices) {
493 *pPhysicalDeviceCount = instance->physicalDeviceCount;
494 } else {
495 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
496 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
497 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
498 }
499
500 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
501 : VK_SUCCESS;
502 }
503
504 void radv_GetPhysicalDeviceFeatures(
505 VkPhysicalDevice physicalDevice,
506 VkPhysicalDeviceFeatures* pFeatures)
507 {
508 // RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
509
510 memset(pFeatures, 0, sizeof(*pFeatures));
511
512 *pFeatures = (VkPhysicalDeviceFeatures) {
513 .robustBufferAccess = true,
514 .fullDrawIndexUint32 = true,
515 .imageCubeArray = true,
516 .independentBlend = true,
517 .geometryShader = true,
518 .tessellationShader = true,
519 .sampleRateShading = false,
520 .dualSrcBlend = true,
521 .logicOp = true,
522 .multiDrawIndirect = true,
523 .drawIndirectFirstInstance = true,
524 .depthClamp = true,
525 .depthBiasClamp = true,
526 .fillModeNonSolid = true,
527 .depthBounds = true,
528 .wideLines = true,
529 .largePoints = true,
530 .alphaToOne = true,
531 .multiViewport = true,
532 .samplerAnisotropy = true,
533 .textureCompressionETC2 = false,
534 .textureCompressionASTC_LDR = false,
535 .textureCompressionBC = true,
536 .occlusionQueryPrecise = true,
537 .pipelineStatisticsQuery = true,
538 .vertexPipelineStoresAndAtomics = true,
539 .fragmentStoresAndAtomics = true,
540 .shaderTessellationAndGeometryPointSize = true,
541 .shaderImageGatherExtended = true,
542 .shaderStorageImageExtendedFormats = true,
543 .shaderStorageImageMultisample = false,
544 .shaderUniformBufferArrayDynamicIndexing = true,
545 .shaderSampledImageArrayDynamicIndexing = true,
546 .shaderStorageBufferArrayDynamicIndexing = true,
547 .shaderStorageImageArrayDynamicIndexing = true,
548 .shaderStorageImageReadWithoutFormat = true,
549 .shaderStorageImageWriteWithoutFormat = true,
550 .shaderClipDistance = true,
551 .shaderCullDistance = true,
552 .shaderFloat64 = true,
553 .shaderInt64 = false,
554 .shaderInt16 = false,
555 .sparseBinding = true,
556 .variableMultisampleRate = true,
557 .inheritedQueries = true,
558 };
559 }
560
561 void radv_GetPhysicalDeviceFeatures2KHR(
562 VkPhysicalDevice physicalDevice,
563 VkPhysicalDeviceFeatures2KHR *pFeatures)
564 {
565 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
566 }
567
568 static uint32_t radv_get_driver_version()
569 {
570 const char *minor_string = strchr(VERSION, '.');
571 const char *patch_string = minor_string ? strchr(minor_string + 1, ','): NULL;
572 int major = atoi(VERSION);
573 int minor = minor_string ? atoi(minor_string + 1) : 0;
574 int patch = patch_string ? atoi(patch_string + 1) : 0;
575 if (strstr(VERSION, "devel")) {
576 if (patch == 0) {
577 patch = 99;
578 if (minor == 0) {
579 minor = 99;
580 --major;
581 } else
582 --minor;
583 } else
584 --patch;
585 }
586 uint32_t version = VK_MAKE_VERSION(major, minor, patch);
587 return version;
588 }
589
590 void radv_GetPhysicalDeviceProperties(
591 VkPhysicalDevice physicalDevice,
592 VkPhysicalDeviceProperties* pProperties)
593 {
594 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
595 VkSampleCountFlags sample_counts = 0xf;
596
597 /* make sure that the entire descriptor set is addressable with a signed
598 * 32-bit int. So the sum of all limits scaled by descriptor size has to
599 * be at most 2 GiB. the combined image & samples object count as one of
600 * both. This limit is for the pipeline layout, not for the set layout, but
601 * there is no set limit, so we just set a pipeline limit. I don't think
602 * any app is going to hit this soon. */
603 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
604 (32 /* uniform buffer, 32 due to potential space wasted on alignement */ +
605 32 /* storage buffer, 32 due to potential space wasted on alignement */ +
606 32 /* sampler, largest when combined with image */ +
607 64 /* sampled image */ +
608 64 /* storage image */);
609
610 VkPhysicalDeviceLimits limits = {
611 .maxImageDimension1D = (1 << 14),
612 .maxImageDimension2D = (1 << 14),
613 .maxImageDimension3D = (1 << 11),
614 .maxImageDimensionCube = (1 << 14),
615 .maxImageArrayLayers = (1 << 11),
616 .maxTexelBufferElements = 128 * 1024 * 1024,
617 .maxUniformBufferRange = UINT32_MAX,
618 .maxStorageBufferRange = UINT32_MAX,
619 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
620 .maxMemoryAllocationCount = UINT32_MAX,
621 .maxSamplerAllocationCount = 64 * 1024,
622 .bufferImageGranularity = 64, /* A cache line */
623 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
624 .maxBoundDescriptorSets = MAX_SETS,
625 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
626 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
627 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
628 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
629 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
630 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
631 .maxPerStageResources = max_descriptor_set_size,
632 .maxDescriptorSetSamplers = max_descriptor_set_size,
633 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
634 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
635 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
636 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_BUFFERS / 2,
637 .maxDescriptorSetSampledImages = max_descriptor_set_size,
638 .maxDescriptorSetStorageImages = max_descriptor_set_size,
639 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
640 .maxVertexInputAttributes = 32,
641 .maxVertexInputBindings = 32,
642 .maxVertexInputAttributeOffset = 2047,
643 .maxVertexInputBindingStride = 2048,
644 .maxVertexOutputComponents = 128,
645 .maxTessellationGenerationLevel = 64,
646 .maxTessellationPatchSize = 32,
647 .maxTessellationControlPerVertexInputComponents = 128,
648 .maxTessellationControlPerVertexOutputComponents = 128,
649 .maxTessellationControlPerPatchOutputComponents = 120,
650 .maxTessellationControlTotalOutputComponents = 4096,
651 .maxTessellationEvaluationInputComponents = 128,
652 .maxTessellationEvaluationOutputComponents = 128,
653 .maxGeometryShaderInvocations = 127,
654 .maxGeometryInputComponents = 64,
655 .maxGeometryOutputComponents = 128,
656 .maxGeometryOutputVertices = 256,
657 .maxGeometryTotalOutputComponents = 1024,
658 .maxFragmentInputComponents = 128,
659 .maxFragmentOutputAttachments = 8,
660 .maxFragmentDualSrcAttachments = 1,
661 .maxFragmentCombinedOutputResources = 8,
662 .maxComputeSharedMemorySize = 32768,
663 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
664 .maxComputeWorkGroupInvocations = 2048,
665 .maxComputeWorkGroupSize = {
666 2048,
667 2048,
668 2048
669 },
670 .subPixelPrecisionBits = 4 /* FIXME */,
671 .subTexelPrecisionBits = 4 /* FIXME */,
672 .mipmapPrecisionBits = 4 /* FIXME */,
673 .maxDrawIndexedIndexValue = UINT32_MAX,
674 .maxDrawIndirectCount = UINT32_MAX,
675 .maxSamplerLodBias = 16,
676 .maxSamplerAnisotropy = 16,
677 .maxViewports = MAX_VIEWPORTS,
678 .maxViewportDimensions = { (1 << 14), (1 << 14) },
679 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
680 .viewportSubPixelBits = 13, /* We take a float? */
681 .minMemoryMapAlignment = 4096, /* A page */
682 .minTexelBufferOffsetAlignment = 1,
683 .minUniformBufferOffsetAlignment = 4,
684 .minStorageBufferOffsetAlignment = 4,
685 .minTexelOffset = -32,
686 .maxTexelOffset = 31,
687 .minTexelGatherOffset = -32,
688 .maxTexelGatherOffset = 31,
689 .minInterpolationOffset = -2,
690 .maxInterpolationOffset = 2,
691 .subPixelInterpolationOffsetBits = 8,
692 .maxFramebufferWidth = (1 << 14),
693 .maxFramebufferHeight = (1 << 14),
694 .maxFramebufferLayers = (1 << 10),
695 .framebufferColorSampleCounts = sample_counts,
696 .framebufferDepthSampleCounts = sample_counts,
697 .framebufferStencilSampleCounts = sample_counts,
698 .framebufferNoAttachmentsSampleCounts = sample_counts,
699 .maxColorAttachments = MAX_RTS,
700 .sampledImageColorSampleCounts = sample_counts,
701 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
702 .sampledImageDepthSampleCounts = sample_counts,
703 .sampledImageStencilSampleCounts = sample_counts,
704 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
705 .maxSampleMaskWords = 1,
706 .timestampComputeAndGraphics = true,
707 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
708 .maxClipDistances = 8,
709 .maxCullDistances = 8,
710 .maxCombinedClipAndCullDistances = 8,
711 .discreteQueuePriorities = 1,
712 .pointSizeRange = { 0.125, 255.875 },
713 .lineWidthRange = { 0.0, 7.9921875 },
714 .pointSizeGranularity = (1.0 / 8.0),
715 .lineWidthGranularity = (1.0 / 128.0),
716 .strictLines = false, /* FINISHME */
717 .standardSampleLocations = true,
718 .optimalBufferCopyOffsetAlignment = 128,
719 .optimalBufferCopyRowPitchAlignment = 128,
720 .nonCoherentAtomSize = 64,
721 };
722
723 *pProperties = (VkPhysicalDeviceProperties) {
724 .apiVersion = VK_MAKE_VERSION(1, 0, 42),
725 .driverVersion = radv_get_driver_version(),
726 .vendorID = 0x1002,
727 .deviceID = pdevice->rad_info.pci_id,
728 .deviceType = VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU,
729 .limits = limits,
730 .sparseProperties = {0},
731 };
732
733 strcpy(pProperties->deviceName, pdevice->name);
734 memcpy(pProperties->pipelineCacheUUID, pdevice->uuid, VK_UUID_SIZE);
735 }
736
737 void radv_GetPhysicalDeviceProperties2KHR(
738 VkPhysicalDevice physicalDevice,
739 VkPhysicalDeviceProperties2KHR *pProperties)
740 {
741 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
742 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
743
744 vk_foreach_struct(ext, pProperties->pNext) {
745 switch (ext->sType) {
746 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
747 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
748 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
749 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
750 break;
751 }
752 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHX: {
753 VkPhysicalDeviceIDPropertiesKHX *properties = (VkPhysicalDeviceIDPropertiesKHX*)ext;
754 radv_device_get_cache_uuid(0, properties->driverUUID);
755 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
756 properties->deviceLUIDValid = false;
757 break;
758 }
759 default:
760 break;
761 }
762 }
763 }
764
765 static void radv_get_physical_device_queue_family_properties(
766 struct radv_physical_device* pdevice,
767 uint32_t* pCount,
768 VkQueueFamilyProperties** pQueueFamilyProperties)
769 {
770 int num_queue_families = 1;
771 int idx;
772 if (pdevice->rad_info.num_compute_rings > 0 &&
773 pdevice->rad_info.chip_class >= CIK &&
774 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
775 num_queue_families++;
776
777 if (pQueueFamilyProperties == NULL) {
778 *pCount = num_queue_families;
779 return;
780 }
781
782 if (!*pCount)
783 return;
784
785 idx = 0;
786 if (*pCount >= 1) {
787 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
788 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
789 VK_QUEUE_COMPUTE_BIT |
790 VK_QUEUE_TRANSFER_BIT |
791 VK_QUEUE_SPARSE_BINDING_BIT,
792 .queueCount = 1,
793 .timestampValidBits = 64,
794 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
795 };
796 idx++;
797 }
798
799 if (pdevice->rad_info.num_compute_rings > 0 &&
800 pdevice->rad_info.chip_class >= CIK &&
801 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
802 if (*pCount > idx) {
803 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
804 .queueFlags = VK_QUEUE_COMPUTE_BIT |
805 VK_QUEUE_TRANSFER_BIT |
806 VK_QUEUE_SPARSE_BINDING_BIT,
807 .queueCount = pdevice->rad_info.num_compute_rings,
808 .timestampValidBits = 64,
809 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
810 };
811 idx++;
812 }
813 }
814 *pCount = idx;
815 }
816
817 void radv_GetPhysicalDeviceQueueFamilyProperties(
818 VkPhysicalDevice physicalDevice,
819 uint32_t* pCount,
820 VkQueueFamilyProperties* pQueueFamilyProperties)
821 {
822 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
823 if (!pQueueFamilyProperties) {
824 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
825 return;
826 }
827 VkQueueFamilyProperties *properties[] = {
828 pQueueFamilyProperties + 0,
829 pQueueFamilyProperties + 1,
830 pQueueFamilyProperties + 2,
831 };
832 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
833 assert(*pCount <= 3);
834 }
835
836 void radv_GetPhysicalDeviceQueueFamilyProperties2KHR(
837 VkPhysicalDevice physicalDevice,
838 uint32_t* pCount,
839 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
840 {
841 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
842 if (!pQueueFamilyProperties) {
843 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
844 return;
845 }
846 VkQueueFamilyProperties *properties[] = {
847 &pQueueFamilyProperties[0].queueFamilyProperties,
848 &pQueueFamilyProperties[1].queueFamilyProperties,
849 &pQueueFamilyProperties[2].queueFamilyProperties,
850 };
851 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
852 assert(*pCount <= 3);
853 }
854
855 void radv_GetPhysicalDeviceMemoryProperties(
856 VkPhysicalDevice physicalDevice,
857 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
858 {
859 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
860
861 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
862
863 pMemoryProperties->memoryTypeCount = RADV_MEM_TYPE_COUNT;
864 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM] = (VkMemoryType) {
865 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
866 .heapIndex = RADV_MEM_HEAP_VRAM,
867 };
868 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_WRITE_COMBINE] = (VkMemoryType) {
869 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
870 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
871 .heapIndex = RADV_MEM_HEAP_GTT,
872 };
873 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_VRAM_CPU_ACCESS] = (VkMemoryType) {
874 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
875 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
876 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
877 .heapIndex = RADV_MEM_HEAP_VRAM_CPU_ACCESS,
878 };
879 pMemoryProperties->memoryTypes[RADV_MEM_TYPE_GTT_CACHED] = (VkMemoryType) {
880 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
881 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
882 VK_MEMORY_PROPERTY_HOST_CACHED_BIT,
883 .heapIndex = RADV_MEM_HEAP_GTT,
884 };
885
886 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
887
888 pMemoryProperties->memoryHeapCount = RADV_MEM_HEAP_COUNT;
889 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM] = (VkMemoryHeap) {
890 .size = physical_device->rad_info.vram_size -
891 physical_device->rad_info.vram_vis_size,
892 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
893 };
894 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_VRAM_CPU_ACCESS] = (VkMemoryHeap) {
895 .size = physical_device->rad_info.vram_vis_size,
896 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
897 };
898 pMemoryProperties->memoryHeaps[RADV_MEM_HEAP_GTT] = (VkMemoryHeap) {
899 .size = physical_device->rad_info.gart_size,
900 .flags = 0,
901 };
902 }
903
904 void radv_GetPhysicalDeviceMemoryProperties2KHR(
905 VkPhysicalDevice physicalDevice,
906 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
907 {
908 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
909 &pMemoryProperties->memoryProperties);
910 }
911
912 static int
913 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
914 int queue_family_index, int idx)
915 {
916 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
917 queue->device = device;
918 queue->queue_family_index = queue_family_index;
919 queue->queue_idx = idx;
920
921 queue->hw_ctx = device->ws->ctx_create(device->ws);
922 if (!queue->hw_ctx)
923 return VK_ERROR_OUT_OF_HOST_MEMORY;
924
925 return VK_SUCCESS;
926 }
927
928 static void
929 radv_queue_finish(struct radv_queue *queue)
930 {
931 if (queue->hw_ctx)
932 queue->device->ws->ctx_destroy(queue->hw_ctx);
933
934 if (queue->initial_preamble_cs)
935 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
936 if (queue->continue_preamble_cs)
937 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
938 if (queue->descriptor_bo)
939 queue->device->ws->buffer_destroy(queue->descriptor_bo);
940 if (queue->scratch_bo)
941 queue->device->ws->buffer_destroy(queue->scratch_bo);
942 if (queue->esgs_ring_bo)
943 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
944 if (queue->gsvs_ring_bo)
945 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
946 if (queue->tess_factor_ring_bo)
947 queue->device->ws->buffer_destroy(queue->tess_factor_ring_bo);
948 if (queue->tess_offchip_ring_bo)
949 queue->device->ws->buffer_destroy(queue->tess_offchip_ring_bo);
950 if (queue->compute_scratch_bo)
951 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
952 }
953
954 static void
955 radv_device_init_gs_info(struct radv_device *device)
956 {
957 switch (device->physical_device->rad_info.family) {
958 case CHIP_OLAND:
959 case CHIP_HAINAN:
960 case CHIP_KAVERI:
961 case CHIP_KABINI:
962 case CHIP_MULLINS:
963 case CHIP_ICELAND:
964 case CHIP_CARRIZO:
965 case CHIP_STONEY:
966 device->gs_table_depth = 16;
967 return;
968 case CHIP_TAHITI:
969 case CHIP_PITCAIRN:
970 case CHIP_VERDE:
971 case CHIP_BONAIRE:
972 case CHIP_HAWAII:
973 case CHIP_TONGA:
974 case CHIP_FIJI:
975 case CHIP_POLARIS10:
976 case CHIP_POLARIS11:
977 case CHIP_POLARIS12:
978 device->gs_table_depth = 32;
979 return;
980 default:
981 unreachable("unknown GPU");
982 }
983 }
984
985 VkResult radv_CreateDevice(
986 VkPhysicalDevice physicalDevice,
987 const VkDeviceCreateInfo* pCreateInfo,
988 const VkAllocationCallbacks* pAllocator,
989 VkDevice* pDevice)
990 {
991 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
992 VkResult result;
993 struct radv_device *device;
994
995 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
996 if (!is_extension_enabled(physical_device->extensions.ext_array,
997 physical_device->extensions.num_ext,
998 pCreateInfo->ppEnabledExtensionNames[i]))
999 return vk_error(VK_ERROR_EXTENSION_NOT_PRESENT);
1000 }
1001
1002 device = vk_alloc2(&physical_device->instance->alloc, pAllocator,
1003 sizeof(*device), 8,
1004 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1005 if (!device)
1006 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
1007
1008 memset(device, 0, sizeof(*device));
1009
1010 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1011 device->instance = physical_device->instance;
1012 device->physical_device = physical_device;
1013
1014 device->debug_flags = device->instance->debug_flags;
1015
1016 device->ws = physical_device->ws;
1017 if (pAllocator)
1018 device->alloc = *pAllocator;
1019 else
1020 device->alloc = physical_device->instance->alloc;
1021
1022 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1023 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1024 uint32_t qfi = queue_create->queueFamilyIndex;
1025
1026 device->queues[qfi] = vk_alloc(&device->alloc,
1027 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1028 if (!device->queues[qfi]) {
1029 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1030 goto fail;
1031 }
1032
1033 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1034
1035 device->queue_count[qfi] = queue_create->queueCount;
1036
1037 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1038 result = radv_queue_init(device, &device->queues[qfi][q], qfi, q);
1039 if (result != VK_SUCCESS)
1040 goto fail;
1041 }
1042 }
1043
1044 #if HAVE_LLVM < 0x0400
1045 device->llvm_supports_spill = false;
1046 #else
1047 device->llvm_supports_spill = true;
1048 #endif
1049
1050 /* The maximum number of scratch waves. Scratch space isn't divided
1051 * evenly between CUs. The number is only a function of the number of CUs.
1052 * We can decrease the constant to decrease the scratch buffer size.
1053 *
1054 * sctx->scratch_waves must be >= the maximum posible size of
1055 * 1 threadgroup, so that the hw doesn't hang from being unable
1056 * to start any.
1057 *
1058 * The recommended value is 4 per CU at most. Higher numbers don't
1059 * bring much benefit, but they still occupy chip resources (think
1060 * async compute). I've seen ~2% performance difference between 4 and 32.
1061 */
1062 uint32_t max_threads_per_block = 2048;
1063 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1064 max_threads_per_block / 64);
1065
1066 radv_device_init_gs_info(device);
1067
1068 device->tess_offchip_block_dw_size =
1069 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1070 device->has_distributed_tess =
1071 device->physical_device->rad_info.chip_class >= VI &&
1072 device->physical_device->rad_info.max_se >= 2;
1073
1074 result = radv_device_init_meta(device);
1075 if (result != VK_SUCCESS)
1076 goto fail;
1077
1078 radv_device_init_msaa(device);
1079
1080 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1081 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1082 switch (family) {
1083 case RADV_QUEUE_GENERAL:
1084 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1085 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1086 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1087 break;
1088 case RADV_QUEUE_COMPUTE:
1089 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1090 radeon_emit(device->empty_cs[family], 0);
1091 break;
1092 }
1093 device->ws->cs_finalize(device->empty_cs[family]);
1094
1095 device->flush_cs[family] = device->ws->cs_create(device->ws, family);
1096 switch (family) {
1097 case RADV_QUEUE_GENERAL:
1098 case RADV_QUEUE_COMPUTE:
1099 si_cs_emit_cache_flush(device->flush_cs[family],
1100 device->physical_device->rad_info.chip_class,
1101 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1102 RADV_CMD_FLAG_INV_ICACHE |
1103 RADV_CMD_FLAG_INV_SMEM_L1 |
1104 RADV_CMD_FLAG_INV_VMEM_L1 |
1105 RADV_CMD_FLAG_INV_GLOBAL_L2);
1106 break;
1107 }
1108 device->ws->cs_finalize(device->flush_cs[family]);
1109
1110 device->flush_shader_cs[family] = device->ws->cs_create(device->ws, family);
1111 switch (family) {
1112 case RADV_QUEUE_GENERAL:
1113 case RADV_QUEUE_COMPUTE:
1114 si_cs_emit_cache_flush(device->flush_shader_cs[family],
1115 device->physical_device->rad_info.chip_class,
1116 family == RADV_QUEUE_COMPUTE && device->physical_device->rad_info.chip_class >= CIK,
1117 family == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH) |
1118 RADV_CMD_FLAG_INV_ICACHE |
1119 RADV_CMD_FLAG_INV_SMEM_L1 |
1120 RADV_CMD_FLAG_INV_VMEM_L1 |
1121 RADV_CMD_FLAG_INV_GLOBAL_L2);
1122 break;
1123 }
1124 device->ws->cs_finalize(device->flush_shader_cs[family]);
1125 }
1126
1127 if (getenv("RADV_TRACE_FILE")) {
1128 device->trace_bo = device->ws->buffer_create(device->ws, 4096, 8,
1129 RADEON_DOMAIN_VRAM, RADEON_FLAG_CPU_ACCESS);
1130 if (!device->trace_bo)
1131 goto fail;
1132
1133 device->trace_id_ptr = device->ws->buffer_map(device->trace_bo);
1134 if (!device->trace_id_ptr)
1135 goto fail;
1136 }
1137
1138 if (device->physical_device->rad_info.chip_class >= CIK)
1139 cik_create_gfx_config(device);
1140
1141 VkPipelineCacheCreateInfo ci;
1142 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1143 ci.pNext = NULL;
1144 ci.flags = 0;
1145 ci.pInitialData = NULL;
1146 ci.initialDataSize = 0;
1147 VkPipelineCache pc;
1148 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1149 &ci, NULL, &pc);
1150 if (result != VK_SUCCESS)
1151 goto fail;
1152
1153 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1154
1155 *pDevice = radv_device_to_handle(device);
1156 return VK_SUCCESS;
1157
1158 fail:
1159 if (device->trace_bo)
1160 device->ws->buffer_destroy(device->trace_bo);
1161
1162 if (device->gfx_init)
1163 device->ws->buffer_destroy(device->gfx_init);
1164
1165 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1166 for (unsigned q = 0; q < device->queue_count[i]; q++)
1167 radv_queue_finish(&device->queues[i][q]);
1168 if (device->queue_count[i])
1169 vk_free(&device->alloc, device->queues[i]);
1170 }
1171
1172 vk_free(&device->alloc, device);
1173 return result;
1174 }
1175
1176 void radv_DestroyDevice(
1177 VkDevice _device,
1178 const VkAllocationCallbacks* pAllocator)
1179 {
1180 RADV_FROM_HANDLE(radv_device, device, _device);
1181
1182 if (!device)
1183 return;
1184
1185 if (device->trace_bo)
1186 device->ws->buffer_destroy(device->trace_bo);
1187
1188 if (device->gfx_init)
1189 device->ws->buffer_destroy(device->gfx_init);
1190
1191 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1192 for (unsigned q = 0; q < device->queue_count[i]; q++)
1193 radv_queue_finish(&device->queues[i][q]);
1194 if (device->queue_count[i])
1195 vk_free(&device->alloc, device->queues[i]);
1196 if (device->empty_cs[i])
1197 device->ws->cs_destroy(device->empty_cs[i]);
1198 if (device->flush_cs[i])
1199 device->ws->cs_destroy(device->flush_cs[i]);
1200 if (device->flush_shader_cs[i])
1201 device->ws->cs_destroy(device->flush_shader_cs[i]);
1202 }
1203 radv_device_finish_meta(device);
1204
1205 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1206 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1207
1208 vk_free(&device->alloc, device);
1209 }
1210
1211 VkResult radv_EnumerateInstanceExtensionProperties(
1212 const char* pLayerName,
1213 uint32_t* pPropertyCount,
1214 VkExtensionProperties* pProperties)
1215 {
1216 if (pProperties == NULL) {
1217 *pPropertyCount = ARRAY_SIZE(instance_extensions);
1218 return VK_SUCCESS;
1219 }
1220
1221 *pPropertyCount = MIN2(*pPropertyCount, ARRAY_SIZE(instance_extensions));
1222 typed_memcpy(pProperties, instance_extensions, *pPropertyCount);
1223
1224 if (*pPropertyCount < ARRAY_SIZE(instance_extensions))
1225 return VK_INCOMPLETE;
1226
1227 return VK_SUCCESS;
1228 }
1229
1230 VkResult radv_EnumerateDeviceExtensionProperties(
1231 VkPhysicalDevice physicalDevice,
1232 const char* pLayerName,
1233 uint32_t* pPropertyCount,
1234 VkExtensionProperties* pProperties)
1235 {
1236 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1237
1238 if (pProperties == NULL) {
1239 *pPropertyCount = pdevice->extensions.num_ext;
1240 return VK_SUCCESS;
1241 }
1242
1243 *pPropertyCount = MIN2(*pPropertyCount, pdevice->extensions.num_ext);
1244 typed_memcpy(pProperties, pdevice->extensions.ext_array, *pPropertyCount);
1245
1246 if (*pPropertyCount < pdevice->extensions.num_ext)
1247 return VK_INCOMPLETE;
1248
1249 return VK_SUCCESS;
1250 }
1251
1252 VkResult radv_EnumerateInstanceLayerProperties(
1253 uint32_t* pPropertyCount,
1254 VkLayerProperties* pProperties)
1255 {
1256 if (pProperties == NULL) {
1257 *pPropertyCount = 0;
1258 return VK_SUCCESS;
1259 }
1260
1261 /* None supported at this time */
1262 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1263 }
1264
1265 VkResult radv_EnumerateDeviceLayerProperties(
1266 VkPhysicalDevice physicalDevice,
1267 uint32_t* pPropertyCount,
1268 VkLayerProperties* pProperties)
1269 {
1270 if (pProperties == NULL) {
1271 *pPropertyCount = 0;
1272 return VK_SUCCESS;
1273 }
1274
1275 /* None supported at this time */
1276 return vk_error(VK_ERROR_LAYER_NOT_PRESENT);
1277 }
1278
1279 void radv_GetDeviceQueue(
1280 VkDevice _device,
1281 uint32_t queueFamilyIndex,
1282 uint32_t queueIndex,
1283 VkQueue* pQueue)
1284 {
1285 RADV_FROM_HANDLE(radv_device, device, _device);
1286
1287 *pQueue = radv_queue_to_handle(&device->queues[queueFamilyIndex][queueIndex]);
1288 }
1289
1290 static void radv_dump_trace(struct radv_device *device,
1291 struct radeon_winsys_cs *cs)
1292 {
1293 const char *filename = getenv("RADV_TRACE_FILE");
1294 FILE *f = fopen(filename, "w");
1295 if (!f) {
1296 fprintf(stderr, "Failed to write trace dump to %s\n", filename);
1297 return;
1298 }
1299
1300 fprintf(f, "Trace ID: %x\n", *device->trace_id_ptr);
1301 device->ws->cs_dump(cs, f, *device->trace_id_ptr);
1302 fclose(f);
1303 }
1304
1305 static void
1306 fill_geom_tess_rings(struct radv_queue *queue,
1307 uint32_t *map,
1308 bool add_sample_positions,
1309 uint32_t esgs_ring_size,
1310 struct radeon_winsys_bo *esgs_ring_bo,
1311 uint32_t gsvs_ring_size,
1312 struct radeon_winsys_bo *gsvs_ring_bo,
1313 uint32_t tess_factor_ring_size,
1314 struct radeon_winsys_bo *tess_factor_ring_bo,
1315 uint32_t tess_offchip_ring_size,
1316 struct radeon_winsys_bo *tess_offchip_ring_bo)
1317 {
1318 uint64_t esgs_va = 0, gsvs_va = 0;
1319 uint64_t tess_factor_va = 0, tess_offchip_va = 0;
1320 uint32_t *desc = &map[4];
1321
1322 if (esgs_ring_bo)
1323 esgs_va = queue->device->ws->buffer_get_va(esgs_ring_bo);
1324 if (gsvs_ring_bo)
1325 gsvs_va = queue->device->ws->buffer_get_va(gsvs_ring_bo);
1326 if (tess_factor_ring_bo)
1327 tess_factor_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1328 if (tess_offchip_ring_bo)
1329 tess_offchip_va = queue->device->ws->buffer_get_va(tess_offchip_ring_bo);
1330
1331 /* stride 0, num records - size, add tid, swizzle, elsize4,
1332 index stride 64 */
1333 desc[0] = esgs_va;
1334 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1335 S_008F04_STRIDE(0) |
1336 S_008F04_SWIZZLE_ENABLE(true);
1337 desc[2] = esgs_ring_size;
1338 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1339 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1340 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1341 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1342 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1343 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1344 S_008F0C_ELEMENT_SIZE(1) |
1345 S_008F0C_INDEX_STRIDE(3) |
1346 S_008F0C_ADD_TID_ENABLE(true);
1347
1348 desc += 4;
1349 /* GS entry for ES->GS ring */
1350 /* stride 0, num records - size, elsize0,
1351 index stride 0 */
1352 desc[0] = esgs_va;
1353 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1354 S_008F04_STRIDE(0) |
1355 S_008F04_SWIZZLE_ENABLE(false);
1356 desc[2] = esgs_ring_size;
1357 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1358 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1359 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1360 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1361 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1362 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1363 S_008F0C_ELEMENT_SIZE(0) |
1364 S_008F0C_INDEX_STRIDE(0) |
1365 S_008F0C_ADD_TID_ENABLE(false);
1366
1367 desc += 4;
1368 /* VS entry for GS->VS ring */
1369 /* stride 0, num records - size, elsize0,
1370 index stride 0 */
1371 desc[0] = gsvs_va;
1372 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1373 S_008F04_STRIDE(0) |
1374 S_008F04_SWIZZLE_ENABLE(false);
1375 desc[2] = gsvs_ring_size;
1376 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1377 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1378 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1379 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1380 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1381 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1382 S_008F0C_ELEMENT_SIZE(0) |
1383 S_008F0C_INDEX_STRIDE(0) |
1384 S_008F0C_ADD_TID_ENABLE(false);
1385 desc += 4;
1386
1387 /* stride gsvs_itemsize, num records 64
1388 elsize 4, index stride 16 */
1389 /* shader will patch stride and desc[2] */
1390 desc[0] = gsvs_va;
1391 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1392 S_008F04_STRIDE(0) |
1393 S_008F04_SWIZZLE_ENABLE(true);
1394 desc[2] = 0;
1395 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1396 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1397 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1398 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1399 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1400 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1401 S_008F0C_ELEMENT_SIZE(1) |
1402 S_008F0C_INDEX_STRIDE(1) |
1403 S_008F0C_ADD_TID_ENABLE(true);
1404 desc += 4;
1405
1406 desc[0] = tess_factor_va;
1407 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_factor_va >> 32) |
1408 S_008F04_STRIDE(0) |
1409 S_008F04_SWIZZLE_ENABLE(false);
1410 desc[2] = tess_factor_ring_size;
1411 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1412 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1413 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1414 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1415 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1416 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1417 S_008F0C_ELEMENT_SIZE(0) |
1418 S_008F0C_INDEX_STRIDE(0) |
1419 S_008F0C_ADD_TID_ENABLE(false);
1420 desc += 4;
1421
1422 desc[0] = tess_offchip_va;
1423 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1424 S_008F04_STRIDE(0) |
1425 S_008F04_SWIZZLE_ENABLE(false);
1426 desc[2] = tess_offchip_ring_size;
1427 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1428 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1429 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1430 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1431 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1432 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1433 S_008F0C_ELEMENT_SIZE(0) |
1434 S_008F0C_INDEX_STRIDE(0) |
1435 S_008F0C_ADD_TID_ENABLE(false);
1436 desc += 4;
1437
1438 /* add sample positions after all rings */
1439 memcpy(desc, queue->device->sample_locations_1x, 8);
1440 desc += 2;
1441 memcpy(desc, queue->device->sample_locations_2x, 16);
1442 desc += 4;
1443 memcpy(desc, queue->device->sample_locations_4x, 32);
1444 desc += 8;
1445 memcpy(desc, queue->device->sample_locations_8x, 64);
1446 desc += 16;
1447 memcpy(desc, queue->device->sample_locations_16x, 128);
1448 }
1449
1450 static unsigned
1451 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1452 {
1453 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1454 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1455 device->physical_device->rad_info.family != CHIP_STONEY;
1456 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1457 unsigned max_offchip_buffers = max_offchip_buffers_per_se *
1458 device->physical_device->rad_info.max_se;
1459 unsigned offchip_granularity;
1460 unsigned hs_offchip_param;
1461 switch (device->tess_offchip_block_dw_size) {
1462 default:
1463 assert(0);
1464 /* fall through */
1465 case 8192:
1466 offchip_granularity = V_03093C_X_8K_DWORDS;
1467 break;
1468 case 4096:
1469 offchip_granularity = V_03093C_X_4K_DWORDS;
1470 break;
1471 }
1472
1473 switch (device->physical_device->rad_info.chip_class) {
1474 case SI:
1475 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1476 break;
1477 case CIK:
1478 case VI:
1479 default:
1480 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1481 break;
1482 }
1483
1484 *max_offchip_buffers_p = max_offchip_buffers;
1485 if (device->physical_device->rad_info.chip_class >= CIK) {
1486 if (device->physical_device->rad_info.chip_class >= VI)
1487 --max_offchip_buffers;
1488 hs_offchip_param =
1489 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1490 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1491 } else {
1492 hs_offchip_param =
1493 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1494 }
1495 return hs_offchip_param;
1496 }
1497
1498 static VkResult
1499 radv_get_preamble_cs(struct radv_queue *queue,
1500 uint32_t scratch_size,
1501 uint32_t compute_scratch_size,
1502 uint32_t esgs_ring_size,
1503 uint32_t gsvs_ring_size,
1504 bool needs_tess_rings,
1505 bool needs_sample_positions,
1506 struct radeon_winsys_cs **initial_preamble_cs,
1507 struct radeon_winsys_cs **continue_preamble_cs)
1508 {
1509 struct radeon_winsys_bo *scratch_bo = NULL;
1510 struct radeon_winsys_bo *descriptor_bo = NULL;
1511 struct radeon_winsys_bo *compute_scratch_bo = NULL;
1512 struct radeon_winsys_bo *esgs_ring_bo = NULL;
1513 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
1514 struct radeon_winsys_bo *tess_factor_ring_bo = NULL;
1515 struct radeon_winsys_bo *tess_offchip_ring_bo = NULL;
1516 struct radeon_winsys_cs *dest_cs[2] = {0};
1517 bool add_tess_rings = false, add_sample_positions = false;
1518 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
1519 unsigned max_offchip_buffers;
1520 unsigned hs_offchip_param = 0;
1521 if (!queue->has_tess_rings) {
1522 if (needs_tess_rings)
1523 add_tess_rings = true;
1524 }
1525 if (!queue->has_sample_positions) {
1526 if (needs_sample_positions)
1527 add_sample_positions = true;
1528 }
1529 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
1530 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
1531 &max_offchip_buffers);
1532 tess_offchip_ring_size = max_offchip_buffers *
1533 queue->device->tess_offchip_block_dw_size * 4;
1534
1535 if (scratch_size <= queue->scratch_size &&
1536 compute_scratch_size <= queue->compute_scratch_size &&
1537 esgs_ring_size <= queue->esgs_ring_size &&
1538 gsvs_ring_size <= queue->gsvs_ring_size &&
1539 !add_tess_rings && !add_sample_positions &&
1540 queue->initial_preamble_cs) {
1541 *initial_preamble_cs = queue->initial_preamble_cs;
1542 *continue_preamble_cs = queue->continue_preamble_cs;
1543 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1544 *continue_preamble_cs = NULL;
1545 return VK_SUCCESS;
1546 }
1547
1548 if (scratch_size > queue->scratch_size) {
1549 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1550 scratch_size,
1551 4096,
1552 RADEON_DOMAIN_VRAM,
1553 RADEON_FLAG_NO_CPU_ACCESS);
1554 if (!scratch_bo)
1555 goto fail;
1556 } else
1557 scratch_bo = queue->scratch_bo;
1558
1559 if (compute_scratch_size > queue->compute_scratch_size) {
1560 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
1561 compute_scratch_size,
1562 4096,
1563 RADEON_DOMAIN_VRAM,
1564 RADEON_FLAG_NO_CPU_ACCESS);
1565 if (!compute_scratch_bo)
1566 goto fail;
1567
1568 } else
1569 compute_scratch_bo = queue->compute_scratch_bo;
1570
1571 if (esgs_ring_size > queue->esgs_ring_size) {
1572 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1573 esgs_ring_size,
1574 4096,
1575 RADEON_DOMAIN_VRAM,
1576 RADEON_FLAG_NO_CPU_ACCESS);
1577 if (!esgs_ring_bo)
1578 goto fail;
1579 } else {
1580 esgs_ring_bo = queue->esgs_ring_bo;
1581 esgs_ring_size = queue->esgs_ring_size;
1582 }
1583
1584 if (gsvs_ring_size > queue->gsvs_ring_size) {
1585 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1586 gsvs_ring_size,
1587 4096,
1588 RADEON_DOMAIN_VRAM,
1589 RADEON_FLAG_NO_CPU_ACCESS);
1590 if (!gsvs_ring_bo)
1591 goto fail;
1592 } else {
1593 gsvs_ring_bo = queue->gsvs_ring_bo;
1594 gsvs_ring_size = queue->gsvs_ring_size;
1595 }
1596
1597 if (add_tess_rings) {
1598 tess_factor_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1599 tess_factor_ring_size,
1600 256,
1601 RADEON_DOMAIN_VRAM,
1602 RADEON_FLAG_NO_CPU_ACCESS);
1603 if (!tess_factor_ring_bo)
1604 goto fail;
1605 tess_offchip_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
1606 tess_offchip_ring_size,
1607 256,
1608 RADEON_DOMAIN_VRAM,
1609 RADEON_FLAG_NO_CPU_ACCESS);
1610 if (!tess_offchip_ring_bo)
1611 goto fail;
1612 } else {
1613 tess_factor_ring_bo = queue->tess_factor_ring_bo;
1614 tess_offchip_ring_bo = queue->tess_offchip_ring_bo;
1615 }
1616
1617 if (scratch_bo != queue->scratch_bo ||
1618 esgs_ring_bo != queue->esgs_ring_bo ||
1619 gsvs_ring_bo != queue->gsvs_ring_bo ||
1620 tess_factor_ring_bo != queue->tess_factor_ring_bo ||
1621 tess_offchip_ring_bo != queue->tess_offchip_ring_bo || add_sample_positions) {
1622 uint32_t size = 0;
1623 if (gsvs_ring_bo || esgs_ring_bo ||
1624 tess_factor_ring_bo || tess_offchip_ring_bo || add_sample_positions) {
1625 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
1626 if (add_sample_positions)
1627 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
1628 }
1629 else if (scratch_bo)
1630 size = 8; /* 2 dword */
1631
1632 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
1633 size,
1634 4096,
1635 RADEON_DOMAIN_VRAM,
1636 RADEON_FLAG_CPU_ACCESS);
1637 if (!descriptor_bo)
1638 goto fail;
1639 } else
1640 descriptor_bo = queue->descriptor_bo;
1641
1642 for(int i = 0; i < 2; ++i) {
1643 struct radeon_winsys_cs *cs = NULL;
1644 cs = queue->device->ws->cs_create(queue->device->ws,
1645 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
1646 if (!cs)
1647 goto fail;
1648
1649 dest_cs[i] = cs;
1650
1651 if (scratch_bo)
1652 queue->device->ws->cs_add_buffer(cs, scratch_bo, 8);
1653
1654 if (esgs_ring_bo)
1655 queue->device->ws->cs_add_buffer(cs, esgs_ring_bo, 8);
1656
1657 if (gsvs_ring_bo)
1658 queue->device->ws->cs_add_buffer(cs, gsvs_ring_bo, 8);
1659
1660 if (tess_factor_ring_bo)
1661 queue->device->ws->cs_add_buffer(cs, tess_factor_ring_bo, 8);
1662
1663 if (tess_offchip_ring_bo)
1664 queue->device->ws->cs_add_buffer(cs, tess_offchip_ring_bo, 8);
1665
1666 if (descriptor_bo)
1667 queue->device->ws->cs_add_buffer(cs, descriptor_bo, 8);
1668
1669 if (descriptor_bo != queue->descriptor_bo) {
1670 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
1671
1672 if (scratch_bo) {
1673 uint64_t scratch_va = queue->device->ws->buffer_get_va(scratch_bo);
1674 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1675 S_008F04_SWIZZLE_ENABLE(1);
1676 map[0] = scratch_va;
1677 map[1] = rsrc1;
1678 }
1679
1680 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo ||
1681 add_sample_positions)
1682 fill_geom_tess_rings(queue, map, add_sample_positions,
1683 esgs_ring_size, esgs_ring_bo,
1684 gsvs_ring_size, gsvs_ring_bo,
1685 tess_factor_ring_size, tess_factor_ring_bo,
1686 tess_offchip_ring_size, tess_offchip_ring_bo);
1687
1688 queue->device->ws->buffer_unmap(descriptor_bo);
1689 }
1690
1691 if (esgs_ring_bo || gsvs_ring_bo || tess_factor_ring_bo || tess_offchip_ring_bo) {
1692 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1693 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1694 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1695 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1696 }
1697
1698 if (esgs_ring_bo || gsvs_ring_bo) {
1699 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1700 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1701 radeon_emit(cs, esgs_ring_size >> 8);
1702 radeon_emit(cs, gsvs_ring_size >> 8);
1703 } else {
1704 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1705 radeon_emit(cs, esgs_ring_size >> 8);
1706 radeon_emit(cs, gsvs_ring_size >> 8);
1707 }
1708 }
1709
1710 if (tess_factor_ring_bo) {
1711 uint64_t tf_va = queue->device->ws->buffer_get_va(tess_factor_ring_bo);
1712 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1713 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
1714 S_030938_SIZE(tess_factor_ring_size / 4));
1715 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
1716 tf_va >> 8);
1717 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM, hs_offchip_param);
1718 } else {
1719 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
1720 S_008988_SIZE(tess_factor_ring_size / 4));
1721 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
1722 tf_va >> 8);
1723 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1724 hs_offchip_param);
1725 }
1726 }
1727
1728 if (descriptor_bo) {
1729 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
1730 R_00B130_SPI_SHADER_USER_DATA_VS_0,
1731 R_00B230_SPI_SHADER_USER_DATA_GS_0,
1732 R_00B330_SPI_SHADER_USER_DATA_ES_0,
1733 R_00B430_SPI_SHADER_USER_DATA_HS_0,
1734 R_00B530_SPI_SHADER_USER_DATA_LS_0};
1735
1736 uint64_t va = queue->device->ws->buffer_get_va(descriptor_bo);
1737
1738 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
1739 radeon_set_sh_reg_seq(cs, regs[i], 2);
1740 radeon_emit(cs, va);
1741 radeon_emit(cs, va >> 32);
1742 }
1743 }
1744
1745 if (compute_scratch_bo) {
1746 uint64_t scratch_va = queue->device->ws->buffer_get_va(compute_scratch_bo);
1747 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
1748 S_008F04_SWIZZLE_ENABLE(1);
1749
1750 queue->device->ws->cs_add_buffer(cs, compute_scratch_bo, 8);
1751
1752 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
1753 radeon_emit(cs, scratch_va);
1754 radeon_emit(cs, rsrc1);
1755 }
1756
1757 if (!i) {
1758 si_cs_emit_cache_flush(cs,
1759 queue->device->physical_device->rad_info.chip_class,
1760 queue->queue_family_index == RING_COMPUTE &&
1761 queue->device->physical_device->rad_info.chip_class >= CIK,
1762 RADV_CMD_FLAG_INV_ICACHE |
1763 RADV_CMD_FLAG_INV_SMEM_L1 |
1764 RADV_CMD_FLAG_INV_VMEM_L1 |
1765 RADV_CMD_FLAG_INV_GLOBAL_L2);
1766 }
1767
1768 if (!queue->device->ws->cs_finalize(cs))
1769 goto fail;
1770 }
1771
1772 if (queue->initial_preamble_cs)
1773 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1774
1775 if (queue->continue_preamble_cs)
1776 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1777
1778 queue->initial_preamble_cs = dest_cs[0];
1779 queue->continue_preamble_cs = dest_cs[1];
1780
1781 if (scratch_bo != queue->scratch_bo) {
1782 if (queue->scratch_bo)
1783 queue->device->ws->buffer_destroy(queue->scratch_bo);
1784 queue->scratch_bo = scratch_bo;
1785 queue->scratch_size = scratch_size;
1786 }
1787
1788 if (compute_scratch_bo != queue->compute_scratch_bo) {
1789 if (queue->compute_scratch_bo)
1790 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1791 queue->compute_scratch_bo = compute_scratch_bo;
1792 queue->compute_scratch_size = compute_scratch_size;
1793 }
1794
1795 if (esgs_ring_bo != queue->esgs_ring_bo) {
1796 if (queue->esgs_ring_bo)
1797 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1798 queue->esgs_ring_bo = esgs_ring_bo;
1799 queue->esgs_ring_size = esgs_ring_size;
1800 }
1801
1802 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
1803 if (queue->gsvs_ring_bo)
1804 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1805 queue->gsvs_ring_bo = gsvs_ring_bo;
1806 queue->gsvs_ring_size = gsvs_ring_size;
1807 }
1808
1809 if (tess_factor_ring_bo != queue->tess_factor_ring_bo) {
1810 queue->tess_factor_ring_bo = tess_factor_ring_bo;
1811 }
1812
1813 if (tess_offchip_ring_bo != queue->tess_offchip_ring_bo) {
1814 queue->tess_offchip_ring_bo = tess_offchip_ring_bo;
1815 queue->has_tess_rings = true;
1816 }
1817
1818 if (descriptor_bo != queue->descriptor_bo) {
1819 if (queue->descriptor_bo)
1820 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1821
1822 queue->descriptor_bo = descriptor_bo;
1823 }
1824
1825 if (add_sample_positions)
1826 queue->has_sample_positions = true;
1827
1828 *initial_preamble_cs = queue->initial_preamble_cs;
1829 *continue_preamble_cs = queue->continue_preamble_cs;
1830 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
1831 *continue_preamble_cs = NULL;
1832 return VK_SUCCESS;
1833 fail:
1834 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
1835 if (dest_cs[i])
1836 queue->device->ws->cs_destroy(dest_cs[i]);
1837 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
1838 queue->device->ws->buffer_destroy(descriptor_bo);
1839 if (scratch_bo && scratch_bo != queue->scratch_bo)
1840 queue->device->ws->buffer_destroy(scratch_bo);
1841 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
1842 queue->device->ws->buffer_destroy(compute_scratch_bo);
1843 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
1844 queue->device->ws->buffer_destroy(esgs_ring_bo);
1845 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
1846 queue->device->ws->buffer_destroy(gsvs_ring_bo);
1847 if (tess_factor_ring_bo && tess_factor_ring_bo != queue->tess_factor_ring_bo)
1848 queue->device->ws->buffer_destroy(tess_factor_ring_bo);
1849 if (tess_offchip_ring_bo && tess_offchip_ring_bo != queue->tess_offchip_ring_bo)
1850 queue->device->ws->buffer_destroy(tess_offchip_ring_bo);
1851 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
1852 }
1853
1854 VkResult radv_QueueSubmit(
1855 VkQueue _queue,
1856 uint32_t submitCount,
1857 const VkSubmitInfo* pSubmits,
1858 VkFence _fence)
1859 {
1860 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1861 RADV_FROM_HANDLE(radv_fence, fence, _fence);
1862 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
1863 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
1864 int ret;
1865 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
1866 uint32_t scratch_size = 0;
1867 uint32_t compute_scratch_size = 0;
1868 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
1869 struct radeon_winsys_cs *initial_preamble_cs = NULL, *continue_preamble_cs = NULL;
1870 VkResult result;
1871 bool fence_emitted = false;
1872 bool tess_rings_needed = false;
1873 bool sample_positions_needed = false;
1874
1875 /* Do this first so failing to allocate scratch buffers can't result in
1876 * partially executed submissions. */
1877 for (uint32_t i = 0; i < submitCount; i++) {
1878 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1879 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1880 pSubmits[i].pCommandBuffers[j]);
1881
1882 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
1883 compute_scratch_size = MAX2(compute_scratch_size,
1884 cmd_buffer->compute_scratch_size_needed);
1885 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
1886 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
1887 tess_rings_needed |= cmd_buffer->tess_rings_needed;
1888 sample_positions_needed |= cmd_buffer->sample_positions_needed;
1889 }
1890 }
1891
1892 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
1893 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
1894 sample_positions_needed,
1895 &initial_preamble_cs, &continue_preamble_cs);
1896 if (result != VK_SUCCESS)
1897 return result;
1898
1899 for (uint32_t i = 0; i < submitCount; i++) {
1900 struct radeon_winsys_cs **cs_array;
1901 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
1902 bool can_patch = !do_flush;
1903 uint32_t advance;
1904
1905 if (!pSubmits[i].commandBufferCount) {
1906 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
1907 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1908 &queue->device->empty_cs[queue->queue_family_index],
1909 1, NULL, NULL,
1910 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1911 pSubmits[i].waitSemaphoreCount,
1912 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1913 pSubmits[i].signalSemaphoreCount,
1914 false, base_fence);
1915 if (ret) {
1916 radv_loge("failed to submit CS %d\n", i);
1917 abort();
1918 }
1919 fence_emitted = true;
1920 }
1921 continue;
1922 }
1923
1924 cs_array = malloc(sizeof(struct radeon_winsys_cs *) *
1925 (pSubmits[i].commandBufferCount + do_flush));
1926
1927 if(do_flush)
1928 cs_array[0] = pSubmits[i].waitSemaphoreCount ?
1929 queue->device->flush_shader_cs[queue->queue_family_index] :
1930 queue->device->flush_cs[queue->queue_family_index];
1931
1932 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
1933 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
1934 pSubmits[i].pCommandBuffers[j]);
1935 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
1936
1937 cs_array[j + do_flush] = cmd_buffer->cs;
1938 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
1939 can_patch = false;
1940 }
1941
1942 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount + do_flush; j += advance) {
1943 advance = MIN2(max_cs_submission,
1944 pSubmits[i].commandBufferCount + do_flush - j);
1945 bool b = j == 0;
1946 bool e = j + advance == pSubmits[i].commandBufferCount + do_flush;
1947
1948 if (queue->device->trace_bo)
1949 *queue->device->trace_id_ptr = 0;
1950
1951 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
1952 advance, initial_preamble_cs, continue_preamble_cs,
1953 (struct radeon_winsys_sem **)pSubmits[i].pWaitSemaphores,
1954 b ? pSubmits[i].waitSemaphoreCount : 0,
1955 (struct radeon_winsys_sem **)pSubmits[i].pSignalSemaphores,
1956 e ? pSubmits[i].signalSemaphoreCount : 0,
1957 can_patch, base_fence);
1958
1959 if (ret) {
1960 radv_loge("failed to submit CS %d\n", i);
1961 abort();
1962 }
1963 fence_emitted = true;
1964 if (queue->device->trace_bo) {
1965 bool success = queue->device->ws->ctx_wait_idle(
1966 queue->hw_ctx,
1967 radv_queue_family_to_ring(
1968 queue->queue_family_index),
1969 queue->queue_idx);
1970
1971 if (!success) { /* Hang */
1972 radv_dump_trace(queue->device, cs_array[j]);
1973 abort();
1974 }
1975 }
1976 }
1977 free(cs_array);
1978 }
1979
1980 if (fence) {
1981 if (!fence_emitted)
1982 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
1983 &queue->device->empty_cs[queue->queue_family_index],
1984 1, NULL, NULL, NULL, 0, NULL, 0,
1985 false, base_fence);
1986
1987 fence->submitted = true;
1988 }
1989
1990 return VK_SUCCESS;
1991 }
1992
1993 VkResult radv_QueueWaitIdle(
1994 VkQueue _queue)
1995 {
1996 RADV_FROM_HANDLE(radv_queue, queue, _queue);
1997
1998 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
1999 radv_queue_family_to_ring(queue->queue_family_index),
2000 queue->queue_idx);
2001 return VK_SUCCESS;
2002 }
2003
2004 VkResult radv_DeviceWaitIdle(
2005 VkDevice _device)
2006 {
2007 RADV_FROM_HANDLE(radv_device, device, _device);
2008
2009 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2010 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2011 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2012 }
2013 }
2014 return VK_SUCCESS;
2015 }
2016
2017 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2018 VkInstance instance,
2019 const char* pName)
2020 {
2021 return radv_lookup_entrypoint(pName);
2022 }
2023
2024 /* The loader wants us to expose a second GetInstanceProcAddr function
2025 * to work around certain LD_PRELOAD issues seen in apps.
2026 */
2027 PUBLIC
2028 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2029 VkInstance instance,
2030 const char* pName);
2031
2032 PUBLIC
2033 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2034 VkInstance instance,
2035 const char* pName)
2036 {
2037 return radv_GetInstanceProcAddr(instance, pName);
2038 }
2039
2040 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2041 VkDevice device,
2042 const char* pName)
2043 {
2044 return radv_lookup_entrypoint(pName);
2045 }
2046
2047 bool radv_get_memory_fd(struct radv_device *device,
2048 struct radv_device_memory *memory,
2049 int *pFD)
2050 {
2051 struct radeon_bo_metadata metadata;
2052
2053 if (memory->image) {
2054 radv_init_metadata(device, memory->image, &metadata);
2055 device->ws->buffer_set_metadata(memory->bo, &metadata);
2056 }
2057
2058 return device->ws->buffer_get_fd(device->ws, memory->bo,
2059 pFD);
2060 }
2061
2062 VkResult radv_AllocateMemory(
2063 VkDevice _device,
2064 const VkMemoryAllocateInfo* pAllocateInfo,
2065 const VkAllocationCallbacks* pAllocator,
2066 VkDeviceMemory* pMem)
2067 {
2068 RADV_FROM_HANDLE(radv_device, device, _device);
2069 struct radv_device_memory *mem;
2070 VkResult result;
2071 enum radeon_bo_domain domain;
2072 uint32_t flags = 0;
2073
2074 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2075
2076 if (pAllocateInfo->allocationSize == 0) {
2077 /* Apparently, this is allowed */
2078 *pMem = VK_NULL_HANDLE;
2079 return VK_SUCCESS;
2080 }
2081
2082 const VkImportMemoryFdInfoKHX *import_info =
2083 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHX);
2084 const VkDedicatedAllocationMemoryAllocateInfoNV *dedicate_info =
2085 vk_find_struct_const(pAllocateInfo->pNext, DEDICATED_ALLOCATION_MEMORY_ALLOCATE_INFO_NV);
2086
2087 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2089 if (mem == NULL)
2090 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2091
2092 if (dedicate_info) {
2093 mem->image = radv_image_from_handle(dedicate_info->image);
2094 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2095 } else {
2096 mem->image = NULL;
2097 mem->buffer = NULL;
2098 }
2099
2100 if (import_info) {
2101 assert(import_info->handleType ==
2102 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX);
2103 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2104 NULL, NULL);
2105 if (!mem->bo)
2106 goto fail;
2107 else
2108 goto out_success;
2109 }
2110
2111 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2112 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2113 pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_CACHED)
2114 domain = RADEON_DOMAIN_GTT;
2115 else
2116 domain = RADEON_DOMAIN_VRAM;
2117
2118 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_VRAM)
2119 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2120 else
2121 flags |= RADEON_FLAG_CPU_ACCESS;
2122
2123 if (pAllocateInfo->memoryTypeIndex == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2124 flags |= RADEON_FLAG_GTT_WC;
2125
2126 mem->bo = device->ws->buffer_create(device->ws, alloc_size, 65536,
2127 domain, flags);
2128
2129 if (!mem->bo) {
2130 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2131 goto fail;
2132 }
2133 mem->type_index = pAllocateInfo->memoryTypeIndex;
2134 out_success:
2135 *pMem = radv_device_memory_to_handle(mem);
2136
2137 return VK_SUCCESS;
2138
2139 fail:
2140 vk_free2(&device->alloc, pAllocator, mem);
2141
2142 return result;
2143 }
2144
2145 void radv_FreeMemory(
2146 VkDevice _device,
2147 VkDeviceMemory _mem,
2148 const VkAllocationCallbacks* pAllocator)
2149 {
2150 RADV_FROM_HANDLE(radv_device, device, _device);
2151 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2152
2153 if (mem == NULL)
2154 return;
2155
2156 device->ws->buffer_destroy(mem->bo);
2157 mem->bo = NULL;
2158
2159 vk_free2(&device->alloc, pAllocator, mem);
2160 }
2161
2162 VkResult radv_MapMemory(
2163 VkDevice _device,
2164 VkDeviceMemory _memory,
2165 VkDeviceSize offset,
2166 VkDeviceSize size,
2167 VkMemoryMapFlags flags,
2168 void** ppData)
2169 {
2170 RADV_FROM_HANDLE(radv_device, device, _device);
2171 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2172
2173 if (mem == NULL) {
2174 *ppData = NULL;
2175 return VK_SUCCESS;
2176 }
2177
2178 *ppData = device->ws->buffer_map(mem->bo);
2179 if (*ppData) {
2180 *ppData += offset;
2181 return VK_SUCCESS;
2182 }
2183
2184 return VK_ERROR_MEMORY_MAP_FAILED;
2185 }
2186
2187 void radv_UnmapMemory(
2188 VkDevice _device,
2189 VkDeviceMemory _memory)
2190 {
2191 RADV_FROM_HANDLE(radv_device, device, _device);
2192 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2193
2194 if (mem == NULL)
2195 return;
2196
2197 device->ws->buffer_unmap(mem->bo);
2198 }
2199
2200 VkResult radv_FlushMappedMemoryRanges(
2201 VkDevice _device,
2202 uint32_t memoryRangeCount,
2203 const VkMappedMemoryRange* pMemoryRanges)
2204 {
2205 return VK_SUCCESS;
2206 }
2207
2208 VkResult radv_InvalidateMappedMemoryRanges(
2209 VkDevice _device,
2210 uint32_t memoryRangeCount,
2211 const VkMappedMemoryRange* pMemoryRanges)
2212 {
2213 return VK_SUCCESS;
2214 }
2215
2216 void radv_GetBufferMemoryRequirements(
2217 VkDevice device,
2218 VkBuffer _buffer,
2219 VkMemoryRequirements* pMemoryRequirements)
2220 {
2221 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2222
2223 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2224
2225 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2226 pMemoryRequirements->alignment = 4096;
2227 else
2228 pMemoryRequirements->alignment = 16;
2229
2230 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
2231 }
2232
2233 void radv_GetImageMemoryRequirements(
2234 VkDevice device,
2235 VkImage _image,
2236 VkMemoryRequirements* pMemoryRequirements)
2237 {
2238 RADV_FROM_HANDLE(radv_image, image, _image);
2239
2240 pMemoryRequirements->memoryTypeBits = (1u << RADV_MEM_TYPE_COUNT) - 1;
2241
2242 pMemoryRequirements->size = image->size;
2243 pMemoryRequirements->alignment = image->alignment;
2244 }
2245
2246 void radv_GetImageSparseMemoryRequirements(
2247 VkDevice device,
2248 VkImage image,
2249 uint32_t* pSparseMemoryRequirementCount,
2250 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
2251 {
2252 stub();
2253 }
2254
2255 void radv_GetDeviceMemoryCommitment(
2256 VkDevice device,
2257 VkDeviceMemory memory,
2258 VkDeviceSize* pCommittedMemoryInBytes)
2259 {
2260 *pCommittedMemoryInBytes = 0;
2261 }
2262
2263 VkResult radv_BindBufferMemory(
2264 VkDevice device,
2265 VkBuffer _buffer,
2266 VkDeviceMemory _memory,
2267 VkDeviceSize memoryOffset)
2268 {
2269 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2270 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2271
2272 if (mem) {
2273 buffer->bo = mem->bo;
2274 buffer->offset = memoryOffset;
2275 } else {
2276 buffer->bo = NULL;
2277 buffer->offset = 0;
2278 }
2279
2280 return VK_SUCCESS;
2281 }
2282
2283 VkResult radv_BindImageMemory(
2284 VkDevice device,
2285 VkImage _image,
2286 VkDeviceMemory _memory,
2287 VkDeviceSize memoryOffset)
2288 {
2289 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2290 RADV_FROM_HANDLE(radv_image, image, _image);
2291
2292 if (mem) {
2293 image->bo = mem->bo;
2294 image->offset = memoryOffset;
2295 } else {
2296 image->bo = NULL;
2297 image->offset = 0;
2298 }
2299
2300 return VK_SUCCESS;
2301 }
2302
2303
2304 static void
2305 radv_sparse_buffer_bind_memory(struct radv_device *device,
2306 const VkSparseBufferMemoryBindInfo *bind)
2307 {
2308 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
2309
2310 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2311 struct radv_device_memory *mem = NULL;
2312
2313 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2314 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2315
2316 device->ws->buffer_virtual_bind(buffer->bo,
2317 bind->pBinds[i].resourceOffset,
2318 bind->pBinds[i].size,
2319 mem ? mem->bo : NULL,
2320 bind->pBinds[i].memoryOffset);
2321 }
2322 }
2323
2324 static void
2325 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
2326 const VkSparseImageOpaqueMemoryBindInfo *bind)
2327 {
2328 RADV_FROM_HANDLE(radv_image, image, bind->image);
2329
2330 for (uint32_t i = 0; i < bind->bindCount; ++i) {
2331 struct radv_device_memory *mem = NULL;
2332
2333 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
2334 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
2335
2336 device->ws->buffer_virtual_bind(image->bo,
2337 bind->pBinds[i].resourceOffset,
2338 bind->pBinds[i].size,
2339 mem ? mem->bo : NULL,
2340 bind->pBinds[i].memoryOffset);
2341 }
2342 }
2343
2344 VkResult radv_QueueBindSparse(
2345 VkQueue _queue,
2346 uint32_t bindInfoCount,
2347 const VkBindSparseInfo* pBindInfo,
2348 VkFence _fence)
2349 {
2350 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2351 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2352 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2353 bool fence_emitted = false;
2354
2355 for (uint32_t i = 0; i < bindInfoCount; ++i) {
2356 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
2357 radv_sparse_buffer_bind_memory(queue->device,
2358 pBindInfo[i].pBufferBinds + j);
2359 }
2360
2361 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
2362 radv_sparse_image_opaque_bind_memory(queue->device,
2363 pBindInfo[i].pImageOpaqueBinds + j);
2364 }
2365
2366 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
2367 queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2368 &queue->device->empty_cs[queue->queue_family_index],
2369 1, NULL, NULL,
2370 (struct radeon_winsys_sem **)pBindInfo[i].pWaitSemaphores,
2371 pBindInfo[i].waitSemaphoreCount,
2372 (struct radeon_winsys_sem **)pBindInfo[i].pSignalSemaphores,
2373 pBindInfo[i].signalSemaphoreCount,
2374 false, base_fence);
2375 fence_emitted = true;
2376 if (fence)
2377 fence->submitted = true;
2378 }
2379 }
2380
2381 if (fence && !fence_emitted) {
2382 fence->signalled = true;
2383 }
2384
2385 return VK_SUCCESS;
2386 }
2387
2388 VkResult radv_CreateFence(
2389 VkDevice _device,
2390 const VkFenceCreateInfo* pCreateInfo,
2391 const VkAllocationCallbacks* pAllocator,
2392 VkFence* pFence)
2393 {
2394 RADV_FROM_HANDLE(radv_device, device, _device);
2395 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
2396 sizeof(*fence), 8,
2397 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2398
2399 if (!fence)
2400 return VK_ERROR_OUT_OF_HOST_MEMORY;
2401
2402 memset(fence, 0, sizeof(*fence));
2403 fence->submitted = false;
2404 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
2405 fence->fence = device->ws->create_fence();
2406 if (!fence->fence) {
2407 vk_free2(&device->alloc, pAllocator, fence);
2408 return VK_ERROR_OUT_OF_HOST_MEMORY;
2409 }
2410
2411 *pFence = radv_fence_to_handle(fence);
2412
2413 return VK_SUCCESS;
2414 }
2415
2416 void radv_DestroyFence(
2417 VkDevice _device,
2418 VkFence _fence,
2419 const VkAllocationCallbacks* pAllocator)
2420 {
2421 RADV_FROM_HANDLE(radv_device, device, _device);
2422 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2423
2424 if (!fence)
2425 return;
2426 device->ws->destroy_fence(fence->fence);
2427 vk_free2(&device->alloc, pAllocator, fence);
2428 }
2429
2430 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
2431 {
2432 uint64_t current_time;
2433 struct timespec tv;
2434
2435 clock_gettime(CLOCK_MONOTONIC, &tv);
2436 current_time = tv.tv_nsec + tv.tv_sec*1000000000ull;
2437
2438 timeout = MIN2(UINT64_MAX - current_time, timeout);
2439
2440 return current_time + timeout;
2441 }
2442
2443 VkResult radv_WaitForFences(
2444 VkDevice _device,
2445 uint32_t fenceCount,
2446 const VkFence* pFences,
2447 VkBool32 waitAll,
2448 uint64_t timeout)
2449 {
2450 RADV_FROM_HANDLE(radv_device, device, _device);
2451 timeout = radv_get_absolute_timeout(timeout);
2452
2453 if (!waitAll && fenceCount > 1) {
2454 fprintf(stderr, "radv: WaitForFences without waitAll not implemented yet\n");
2455 }
2456
2457 for (uint32_t i = 0; i < fenceCount; ++i) {
2458 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2459 bool expired = false;
2460
2461 if (fence->signalled)
2462 continue;
2463
2464 if (!fence->submitted)
2465 return VK_TIMEOUT;
2466
2467 expired = device->ws->fence_wait(device->ws, fence->fence, true, timeout);
2468 if (!expired)
2469 return VK_TIMEOUT;
2470
2471 fence->signalled = true;
2472 }
2473
2474 return VK_SUCCESS;
2475 }
2476
2477 VkResult radv_ResetFences(VkDevice device,
2478 uint32_t fenceCount,
2479 const VkFence *pFences)
2480 {
2481 for (unsigned i = 0; i < fenceCount; ++i) {
2482 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
2483 fence->submitted = fence->signalled = false;
2484 }
2485
2486 return VK_SUCCESS;
2487 }
2488
2489 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
2490 {
2491 RADV_FROM_HANDLE(radv_device, device, _device);
2492 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2493
2494 if (fence->signalled)
2495 return VK_SUCCESS;
2496 if (!fence->submitted)
2497 return VK_NOT_READY;
2498
2499 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
2500 return VK_NOT_READY;
2501
2502 return VK_SUCCESS;
2503 }
2504
2505
2506 // Queue semaphore functions
2507
2508 VkResult radv_CreateSemaphore(
2509 VkDevice _device,
2510 const VkSemaphoreCreateInfo* pCreateInfo,
2511 const VkAllocationCallbacks* pAllocator,
2512 VkSemaphore* pSemaphore)
2513 {
2514 RADV_FROM_HANDLE(radv_device, device, _device);
2515 struct radeon_winsys_sem *sem;
2516
2517 sem = device->ws->create_sem(device->ws);
2518 if (!sem)
2519 return VK_ERROR_OUT_OF_HOST_MEMORY;
2520
2521 *pSemaphore = radeon_winsys_sem_to_handle(sem);
2522 return VK_SUCCESS;
2523 }
2524
2525 void radv_DestroySemaphore(
2526 VkDevice _device,
2527 VkSemaphore _semaphore,
2528 const VkAllocationCallbacks* pAllocator)
2529 {
2530 RADV_FROM_HANDLE(radv_device, device, _device);
2531 RADV_FROM_HANDLE(radeon_winsys_sem, sem, _semaphore);
2532 if (!_semaphore)
2533 return;
2534
2535 device->ws->destroy_sem(sem);
2536 }
2537
2538 VkResult radv_CreateEvent(
2539 VkDevice _device,
2540 const VkEventCreateInfo* pCreateInfo,
2541 const VkAllocationCallbacks* pAllocator,
2542 VkEvent* pEvent)
2543 {
2544 RADV_FROM_HANDLE(radv_device, device, _device);
2545 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
2546 sizeof(*event), 8,
2547 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2548
2549 if (!event)
2550 return VK_ERROR_OUT_OF_HOST_MEMORY;
2551
2552 event->bo = device->ws->buffer_create(device->ws, 8, 8,
2553 RADEON_DOMAIN_GTT,
2554 RADEON_FLAG_CPU_ACCESS);
2555 if (!event->bo) {
2556 vk_free2(&device->alloc, pAllocator, event);
2557 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
2558 }
2559
2560 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
2561
2562 *pEvent = radv_event_to_handle(event);
2563
2564 return VK_SUCCESS;
2565 }
2566
2567 void radv_DestroyEvent(
2568 VkDevice _device,
2569 VkEvent _event,
2570 const VkAllocationCallbacks* pAllocator)
2571 {
2572 RADV_FROM_HANDLE(radv_device, device, _device);
2573 RADV_FROM_HANDLE(radv_event, event, _event);
2574
2575 if (!event)
2576 return;
2577 device->ws->buffer_destroy(event->bo);
2578 vk_free2(&device->alloc, pAllocator, event);
2579 }
2580
2581 VkResult radv_GetEventStatus(
2582 VkDevice _device,
2583 VkEvent _event)
2584 {
2585 RADV_FROM_HANDLE(radv_event, event, _event);
2586
2587 if (*event->map == 1)
2588 return VK_EVENT_SET;
2589 return VK_EVENT_RESET;
2590 }
2591
2592 VkResult radv_SetEvent(
2593 VkDevice _device,
2594 VkEvent _event)
2595 {
2596 RADV_FROM_HANDLE(radv_event, event, _event);
2597 *event->map = 1;
2598
2599 return VK_SUCCESS;
2600 }
2601
2602 VkResult radv_ResetEvent(
2603 VkDevice _device,
2604 VkEvent _event)
2605 {
2606 RADV_FROM_HANDLE(radv_event, event, _event);
2607 *event->map = 0;
2608
2609 return VK_SUCCESS;
2610 }
2611
2612 VkResult radv_CreateBuffer(
2613 VkDevice _device,
2614 const VkBufferCreateInfo* pCreateInfo,
2615 const VkAllocationCallbacks* pAllocator,
2616 VkBuffer* pBuffer)
2617 {
2618 RADV_FROM_HANDLE(radv_device, device, _device);
2619 struct radv_buffer *buffer;
2620
2621 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
2622
2623 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
2624 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2625 if (buffer == NULL)
2626 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2627
2628 buffer->size = pCreateInfo->size;
2629 buffer->usage = pCreateInfo->usage;
2630 buffer->bo = NULL;
2631 buffer->offset = 0;
2632 buffer->flags = pCreateInfo->flags;
2633
2634 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
2635 buffer->bo = device->ws->buffer_create(device->ws,
2636 align64(buffer->size, 4096),
2637 4096, 0, RADEON_FLAG_VIRTUAL);
2638 if (!buffer->bo) {
2639 vk_free2(&device->alloc, pAllocator, buffer);
2640 return vk_error(VK_ERROR_OUT_OF_DEVICE_MEMORY);
2641 }
2642 }
2643
2644 *pBuffer = radv_buffer_to_handle(buffer);
2645
2646 return VK_SUCCESS;
2647 }
2648
2649 void radv_DestroyBuffer(
2650 VkDevice _device,
2651 VkBuffer _buffer,
2652 const VkAllocationCallbacks* pAllocator)
2653 {
2654 RADV_FROM_HANDLE(radv_device, device, _device);
2655 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
2656
2657 if (!buffer)
2658 return;
2659
2660 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
2661 device->ws->buffer_destroy(buffer->bo);
2662
2663 vk_free2(&device->alloc, pAllocator, buffer);
2664 }
2665
2666 static inline unsigned
2667 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
2668 {
2669 if (stencil)
2670 return image->surface.u.legacy.stencil_tiling_index[level];
2671 else
2672 return image->surface.u.legacy.tiling_index[level];
2673 }
2674
2675 static uint32_t radv_surface_layer_count(struct radv_image_view *iview)
2676 {
2677 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : iview->layer_count;
2678 }
2679
2680 static void
2681 radv_initialise_color_surface(struct radv_device *device,
2682 struct radv_color_buffer_info *cb,
2683 struct radv_image_view *iview)
2684 {
2685 const struct vk_format_description *desc;
2686 unsigned ntype, format, swap, endian;
2687 unsigned blend_clamp = 0, blend_bypass = 0;
2688 uint64_t va;
2689 const struct radeon_surf *surf = &iview->image->surface;
2690
2691 desc = vk_format_description(iview->vk_format);
2692
2693 memset(cb, 0, sizeof(*cb));
2694
2695 /* Intensity is implemented as Red, so treat it that way. */
2696 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
2697
2698 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2699
2700 {
2701 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
2702 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
2703
2704 va += level_info->offset;
2705
2706 pitch_tile_max = level_info->nblk_x / 8 - 1;
2707 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
2708 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
2709
2710 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
2711 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
2712 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
2713
2714 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
2715 cb->micro_tile_mode = iview->image->surface.micro_tile_mode;
2716
2717 if (iview->image->fmask.size) {
2718 if (device->physical_device->rad_info.chip_class >= CIK)
2719 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
2720 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
2721 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
2722 } else {
2723 /* This must be set for fast clear to work without FMASK. */
2724 if (device->physical_device->rad_info.chip_class >= CIK)
2725 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
2726 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
2727 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
2728 }
2729 }
2730
2731 cb->cb_color_base = va >> 8;
2732
2733 /* CMASK variables */
2734 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2735 va += iview->image->cmask.offset;
2736 cb->cb_color_cmask = va >> 8;
2737
2738 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2739 va += iview->image->dcc_offset;
2740 cb->cb_dcc_base = va >> 8;
2741
2742 uint32_t max_slice = radv_surface_layer_count(iview);
2743 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
2744 S_028C6C_SLICE_MAX(iview->base_layer + max_slice - 1);
2745
2746 if (iview->image->info.samples > 1) {
2747 unsigned log_samples = util_logbase2(iview->image->info.samples);
2748
2749 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
2750 S_028C74_NUM_FRAGMENTS(log_samples);
2751 }
2752
2753 if (iview->image->fmask.size) {
2754 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
2755 cb->cb_color_fmask = va >> 8;
2756 } else {
2757 cb->cb_color_fmask = cb->cb_color_base;
2758 }
2759
2760 ntype = radv_translate_color_numformat(iview->vk_format,
2761 desc,
2762 vk_format_get_first_non_void_channel(iview->vk_format));
2763 format = radv_translate_colorformat(iview->vk_format);
2764 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
2765 radv_finishme("Illegal color\n");
2766 swap = radv_translate_colorswap(iview->vk_format, FALSE);
2767 endian = radv_colorformat_endian_swap(format);
2768
2769 /* blend clamp should be set for all NORM/SRGB types */
2770 if (ntype == V_028C70_NUMBER_UNORM ||
2771 ntype == V_028C70_NUMBER_SNORM ||
2772 ntype == V_028C70_NUMBER_SRGB)
2773 blend_clamp = 1;
2774
2775 /* set blend bypass according to docs if SINT/UINT or
2776 8/24 COLOR variants */
2777 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
2778 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
2779 format == V_028C70_COLOR_X24_8_32_FLOAT) {
2780 blend_clamp = 0;
2781 blend_bypass = 1;
2782 }
2783 #if 0
2784 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
2785 (format == V_028C70_COLOR_8 ||
2786 format == V_028C70_COLOR_8_8 ||
2787 format == V_028C70_COLOR_8_8_8_8))
2788 ->color_is_int8 = true;
2789 #endif
2790 cb->cb_color_info = S_028C70_FORMAT(format) |
2791 S_028C70_COMP_SWAP(swap) |
2792 S_028C70_BLEND_CLAMP(blend_clamp) |
2793 S_028C70_BLEND_BYPASS(blend_bypass) |
2794 S_028C70_SIMPLE_FLOAT(1) |
2795 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
2796 ntype != V_028C70_NUMBER_SNORM &&
2797 ntype != V_028C70_NUMBER_SRGB &&
2798 format != V_028C70_COLOR_8_24 &&
2799 format != V_028C70_COLOR_24_8) |
2800 S_028C70_NUMBER_TYPE(ntype) |
2801 S_028C70_ENDIAN(endian);
2802 if (iview->image->info.samples > 1)
2803 if (iview->image->fmask.size)
2804 cb->cb_color_info |= S_028C70_COMPRESSION(1);
2805
2806 if (iview->image->cmask.size &&
2807 !(device->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
2808 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
2809
2810 if (iview->image->surface.dcc_size && iview->base_mip < surf->num_dcc_levels)
2811 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
2812
2813 if (device->physical_device->rad_info.chip_class >= VI) {
2814 unsigned max_uncompressed_block_size = 2;
2815 if (iview->image->info.samples > 1) {
2816 if (iview->image->surface.bpe == 1)
2817 max_uncompressed_block_size = 0;
2818 else if (iview->image->surface.bpe == 2)
2819 max_uncompressed_block_size = 1;
2820 }
2821
2822 cb->cb_dcc_control = S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
2823 S_028C78_INDEPENDENT_64B_BLOCKS(1);
2824 }
2825
2826 /* This must be set for fast clear to work without FMASK. */
2827 if (!iview->image->fmask.size &&
2828 device->physical_device->rad_info.chip_class == SI) {
2829 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
2830 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
2831 }
2832 }
2833
2834 static void
2835 radv_initialise_ds_surface(struct radv_device *device,
2836 struct radv_ds_buffer_info *ds,
2837 struct radv_image_view *iview)
2838 {
2839 unsigned level = iview->base_mip;
2840 unsigned format, stencil_format;
2841 uint64_t va, s_offs, z_offs;
2842 bool stencil_only = false;
2843 memset(ds, 0, sizeof(*ds));
2844 switch (iview->vk_format) {
2845 case VK_FORMAT_D24_UNORM_S8_UINT:
2846 case VK_FORMAT_X8_D24_UNORM_PACK32:
2847 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
2848 ds->offset_scale = 2.0f;
2849 break;
2850 case VK_FORMAT_D16_UNORM:
2851 case VK_FORMAT_D16_UNORM_S8_UINT:
2852 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
2853 ds->offset_scale = 4.0f;
2854 break;
2855 case VK_FORMAT_D32_SFLOAT:
2856 case VK_FORMAT_D32_SFLOAT_S8_UINT:
2857 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
2858 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
2859 ds->offset_scale = 1.0f;
2860 break;
2861 case VK_FORMAT_S8_UINT:
2862 stencil_only = true;
2863 break;
2864 default:
2865 break;
2866 }
2867
2868 format = radv_translate_dbformat(iview->vk_format);
2869 stencil_format = iview->image->surface.flags & RADEON_SURF_SBUFFER ?
2870 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
2871
2872 uint32_t max_slice = radv_surface_layer_count(iview);
2873 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
2874 S_028008_SLICE_MAX(iview->base_layer + max_slice - 1);
2875
2876 ds->db_htile_data_base = 0;
2877 ds->db_htile_surface = 0;
2878
2879 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
2880 s_offs = z_offs = va;
2881
2882 {
2883 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
2884
2885 if (stencil_only)
2886 level_info = &iview->image->surface.u.legacy.stencil_level[level];
2887
2888 z_offs += iview->image->surface.u.legacy.level[level].offset;
2889 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
2890
2891 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
2892 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
2893 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
2894
2895 if (iview->image->info.samples > 1)
2896 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
2897
2898 if (device->physical_device->rad_info.chip_class >= CIK) {
2899 struct radeon_info *info = &device->physical_device->rad_info;
2900 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
2901 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
2902 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
2903 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
2904 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
2905 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
2906
2907 if (stencil_only)
2908 tile_mode = stencil_tile_mode;
2909
2910 ds->db_depth_info |=
2911 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
2912 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
2913 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
2914 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
2915 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
2916 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
2917 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
2918 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
2919 } else {
2920 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
2921 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
2922 tile_mode_index = si_tile_mode_index(iview->image, level, true);
2923 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
2924 }
2925
2926 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
2927 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
2928 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
2929
2930 if (iview->image->surface.htile_size && !level) {
2931 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
2932
2933 if (!(iview->image->surface.flags & RADEON_SURF_SBUFFER))
2934 /* Use all of the htile_buffer for depth if there's no stencil. */
2935 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
2936
2937 va = device->ws->buffer_get_va(iview->bo) + iview->image->offset +
2938 iview->image->htile_offset;
2939 ds->db_htile_data_base = va >> 8;
2940 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
2941 }
2942 }
2943
2944 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
2945 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
2946 }
2947
2948 VkResult radv_CreateFramebuffer(
2949 VkDevice _device,
2950 const VkFramebufferCreateInfo* pCreateInfo,
2951 const VkAllocationCallbacks* pAllocator,
2952 VkFramebuffer* pFramebuffer)
2953 {
2954 RADV_FROM_HANDLE(radv_device, device, _device);
2955 struct radv_framebuffer *framebuffer;
2956
2957 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
2958
2959 size_t size = sizeof(*framebuffer) +
2960 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
2961 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
2962 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2963 if (framebuffer == NULL)
2964 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
2965
2966 framebuffer->attachment_count = pCreateInfo->attachmentCount;
2967 framebuffer->width = pCreateInfo->width;
2968 framebuffer->height = pCreateInfo->height;
2969 framebuffer->layers = pCreateInfo->layers;
2970 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
2971 VkImageView _iview = pCreateInfo->pAttachments[i];
2972 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
2973 framebuffer->attachments[i].attachment = iview;
2974 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
2975 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
2976 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
2977 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
2978 }
2979 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
2980 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
2981 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_layer_count(iview));
2982 }
2983
2984 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
2985 return VK_SUCCESS;
2986 }
2987
2988 void radv_DestroyFramebuffer(
2989 VkDevice _device,
2990 VkFramebuffer _fb,
2991 const VkAllocationCallbacks* pAllocator)
2992 {
2993 RADV_FROM_HANDLE(radv_device, device, _device);
2994 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
2995
2996 if (!fb)
2997 return;
2998 vk_free2(&device->alloc, pAllocator, fb);
2999 }
3000
3001 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
3002 {
3003 switch (address_mode) {
3004 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
3005 return V_008F30_SQ_TEX_WRAP;
3006 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
3007 return V_008F30_SQ_TEX_MIRROR;
3008 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
3009 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
3010 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
3011 return V_008F30_SQ_TEX_CLAMP_BORDER;
3012 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
3013 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
3014 default:
3015 unreachable("illegal tex wrap mode");
3016 break;
3017 }
3018 }
3019
3020 static unsigned
3021 radv_tex_compare(VkCompareOp op)
3022 {
3023 switch (op) {
3024 case VK_COMPARE_OP_NEVER:
3025 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
3026 case VK_COMPARE_OP_LESS:
3027 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
3028 case VK_COMPARE_OP_EQUAL:
3029 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
3030 case VK_COMPARE_OP_LESS_OR_EQUAL:
3031 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
3032 case VK_COMPARE_OP_GREATER:
3033 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
3034 case VK_COMPARE_OP_NOT_EQUAL:
3035 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
3036 case VK_COMPARE_OP_GREATER_OR_EQUAL:
3037 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
3038 case VK_COMPARE_OP_ALWAYS:
3039 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
3040 default:
3041 unreachable("illegal compare mode");
3042 break;
3043 }
3044 }
3045
3046 static unsigned
3047 radv_tex_filter(VkFilter filter, unsigned max_ansio)
3048 {
3049 switch (filter) {
3050 case VK_FILTER_NEAREST:
3051 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
3052 V_008F38_SQ_TEX_XY_FILTER_POINT);
3053 case VK_FILTER_LINEAR:
3054 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
3055 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
3056 case VK_FILTER_CUBIC_IMG:
3057 default:
3058 fprintf(stderr, "illegal texture filter");
3059 return 0;
3060 }
3061 }
3062
3063 static unsigned
3064 radv_tex_mipfilter(VkSamplerMipmapMode mode)
3065 {
3066 switch (mode) {
3067 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
3068 return V_008F38_SQ_TEX_Z_FILTER_POINT;
3069 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
3070 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
3071 default:
3072 return V_008F38_SQ_TEX_Z_FILTER_NONE;
3073 }
3074 }
3075
3076 static unsigned
3077 radv_tex_bordercolor(VkBorderColor bcolor)
3078 {
3079 switch (bcolor) {
3080 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
3081 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
3082 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
3083 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
3084 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
3085 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
3086 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
3087 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
3088 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
3089 default:
3090 break;
3091 }
3092 return 0;
3093 }
3094
3095 static unsigned
3096 radv_tex_aniso_filter(unsigned filter)
3097 {
3098 if (filter < 2)
3099 return 0;
3100 if (filter < 4)
3101 return 1;
3102 if (filter < 8)
3103 return 2;
3104 if (filter < 16)
3105 return 3;
3106 return 4;
3107 }
3108
3109 static void
3110 radv_init_sampler(struct radv_device *device,
3111 struct radv_sampler *sampler,
3112 const VkSamplerCreateInfo *pCreateInfo)
3113 {
3114 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
3115 (uint32_t) pCreateInfo->maxAnisotropy : 0;
3116 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
3117 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
3118
3119 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
3120 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
3121 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
3122 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
3123 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
3124 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
3125 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
3126 S_008F30_ANISO_BIAS(max_aniso_ratio) |
3127 S_008F30_DISABLE_CUBE_WRAP(0) |
3128 S_008F30_COMPAT_MODE(is_vi));
3129 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
3130 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
3131 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
3132 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
3133 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
3134 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
3135 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
3136 S_008F38_MIP_POINT_PRECLAMP(0) |
3137 S_008F38_DISABLE_LSB_CEIL(1) |
3138 S_008F38_FILTER_PREC_FIX(1) |
3139 S_008F38_ANISO_OVERRIDE(is_vi));
3140 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
3141 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
3142 }
3143
3144 VkResult radv_CreateSampler(
3145 VkDevice _device,
3146 const VkSamplerCreateInfo* pCreateInfo,
3147 const VkAllocationCallbacks* pAllocator,
3148 VkSampler* pSampler)
3149 {
3150 RADV_FROM_HANDLE(radv_device, device, _device);
3151 struct radv_sampler *sampler;
3152
3153 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
3154
3155 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
3156 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3157 if (!sampler)
3158 return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
3159
3160 radv_init_sampler(device, sampler, pCreateInfo);
3161 *pSampler = radv_sampler_to_handle(sampler);
3162
3163 return VK_SUCCESS;
3164 }
3165
3166 void radv_DestroySampler(
3167 VkDevice _device,
3168 VkSampler _sampler,
3169 const VkAllocationCallbacks* pAllocator)
3170 {
3171 RADV_FROM_HANDLE(radv_device, device, _device);
3172 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
3173
3174 if (!sampler)
3175 return;
3176 vk_free2(&device->alloc, pAllocator, sampler);
3177 }
3178
3179 /* vk_icd.h does not declare this function, so we declare it here to
3180 * suppress Wmissing-prototypes.
3181 */
3182 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3183 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
3184
3185 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
3186 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
3187 {
3188 /* For the full details on loader interface versioning, see
3189 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
3190 * What follows is a condensed summary, to help you navigate the large and
3191 * confusing official doc.
3192 *
3193 * - Loader interface v0 is incompatible with later versions. We don't
3194 * support it.
3195 *
3196 * - In loader interface v1:
3197 * - The first ICD entrypoint called by the loader is
3198 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
3199 * entrypoint.
3200 * - The ICD must statically expose no other Vulkan symbol unless it is
3201 * linked with -Bsymbolic.
3202 * - Each dispatchable Vulkan handle created by the ICD must be
3203 * a pointer to a struct whose first member is VK_LOADER_DATA. The
3204 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
3205 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
3206 * vkDestroySurfaceKHR(). The ICD must be capable of working with
3207 * such loader-managed surfaces.
3208 *
3209 * - Loader interface v2 differs from v1 in:
3210 * - The first ICD entrypoint called by the loader is
3211 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
3212 * statically expose this entrypoint.
3213 *
3214 * - Loader interface v3 differs from v2 in:
3215 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
3216 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
3217 * because the loader no longer does so.
3218 */
3219 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
3220 return VK_SUCCESS;
3221 }
3222
3223 VkResult radv_GetMemoryFdKHX(VkDevice _device,
3224 VkDeviceMemory _memory,
3225 VkExternalMemoryHandleTypeFlagsKHX handleType,
3226 int *pFD)
3227 {
3228 RADV_FROM_HANDLE(radv_device, device, _device);
3229 RADV_FROM_HANDLE(radv_device_memory, memory, _memory);
3230
3231 /* We support only one handle type. */
3232 assert(handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHX);
3233
3234 bool ret = radv_get_memory_fd(device, memory, pFD);
3235 if (ret == false)
3236 return VK_ERROR_OUT_OF_DEVICE_MEMORY;
3237 return VK_SUCCESS;
3238 }
3239
3240 VkResult radv_GetMemoryFdPropertiesKHX(VkDevice _device,
3241 VkExternalMemoryHandleTypeFlagBitsKHX handleType,
3242 int fd,
3243 VkMemoryFdPropertiesKHX *pMemoryFdProperties)
3244 {
3245 /* The valid usage section for this function says:
3246 *
3247 * "handleType must not be one of the handle types defined as opaque."
3248 *
3249 * Since we only handle opaque handles for now, there are no FD properties.
3250 */
3251 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHX;
3252 }