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radv: Use a lower max offchip buffer count.
[mesa.git] / src / amd / vulkan / radv_device.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include <stdbool.h>
29 #include <string.h>
30 #include <unistd.h>
31 #include <fcntl.h>
32 #include "radv_debug.h"
33 #include "radv_private.h"
34 #include "radv_shader.h"
35 #include "radv_cs.h"
36 #include "util/disk_cache.h"
37 #include "util/strtod.h"
38 #include "vk_util.h"
39 #include <xf86drm.h>
40 #include <amdgpu.h>
41 #include <amdgpu_drm.h>
42 #include "winsys/amdgpu/radv_amdgpu_winsys_public.h"
43 #include "ac_llvm_util.h"
44 #include "vk_format.h"
45 #include "sid.h"
46 #include "gfx9d.h"
47 #include "addrlib/gfx9/chip/gfx9_enum.h"
48 #include "util/debug.h"
49
50 static int
51 radv_device_get_cache_uuid(enum radeon_family family, void *uuid)
52 {
53 uint32_t mesa_timestamp, llvm_timestamp;
54 uint16_t f = family;
55 memset(uuid, 0, VK_UUID_SIZE);
56 if (!disk_cache_get_function_timestamp(radv_device_get_cache_uuid, &mesa_timestamp) ||
57 !disk_cache_get_function_timestamp(LLVMInitializeAMDGPUTargetInfo, &llvm_timestamp))
58 return -1;
59
60 memcpy(uuid, &mesa_timestamp, 4);
61 memcpy((char*)uuid + 4, &llvm_timestamp, 4);
62 memcpy((char*)uuid + 8, &f, 2);
63 snprintf((char*)uuid + 10, VK_UUID_SIZE - 10, "radv%zd", sizeof(void *));
64 return 0;
65 }
66
67 static void
68 radv_get_driver_uuid(void *uuid)
69 {
70 ac_compute_driver_uuid(uuid, VK_UUID_SIZE);
71 }
72
73 static void
74 radv_get_device_uuid(struct radeon_info *info, void *uuid)
75 {
76 ac_compute_device_uuid(info, uuid, VK_UUID_SIZE);
77 }
78
79 static void
80 radv_get_device_name(enum radeon_family family, char *name, size_t name_len)
81 {
82 const char *chip_string;
83 char llvm_string[32] = {};
84
85 switch (family) {
86 case CHIP_TAHITI: chip_string = "AMD RADV TAHITI"; break;
87 case CHIP_PITCAIRN: chip_string = "AMD RADV PITCAIRN"; break;
88 case CHIP_VERDE: chip_string = "AMD RADV CAPE VERDE"; break;
89 case CHIP_OLAND: chip_string = "AMD RADV OLAND"; break;
90 case CHIP_HAINAN: chip_string = "AMD RADV HAINAN"; break;
91 case CHIP_BONAIRE: chip_string = "AMD RADV BONAIRE"; break;
92 case CHIP_KAVERI: chip_string = "AMD RADV KAVERI"; break;
93 case CHIP_KABINI: chip_string = "AMD RADV KABINI"; break;
94 case CHIP_HAWAII: chip_string = "AMD RADV HAWAII"; break;
95 case CHIP_MULLINS: chip_string = "AMD RADV MULLINS"; break;
96 case CHIP_TONGA: chip_string = "AMD RADV TONGA"; break;
97 case CHIP_ICELAND: chip_string = "AMD RADV ICELAND"; break;
98 case CHIP_CARRIZO: chip_string = "AMD RADV CARRIZO"; break;
99 case CHIP_FIJI: chip_string = "AMD RADV FIJI"; break;
100 case CHIP_POLARIS10: chip_string = "AMD RADV POLARIS10"; break;
101 case CHIP_POLARIS11: chip_string = "AMD RADV POLARIS11"; break;
102 case CHIP_POLARIS12: chip_string = "AMD RADV POLARIS12"; break;
103 case CHIP_STONEY: chip_string = "AMD RADV STONEY"; break;
104 case CHIP_VEGAM: chip_string = "AMD RADV VEGA M"; break;
105 case CHIP_VEGA10: chip_string = "AMD RADV VEGA10"; break;
106 case CHIP_VEGA12: chip_string = "AMD RADV VEGA12"; break;
107 case CHIP_RAVEN: chip_string = "AMD RADV RAVEN"; break;
108 default: chip_string = "AMD RADV unknown"; break;
109 }
110
111 snprintf(llvm_string, sizeof(llvm_string),
112 " (LLVM %i.%i.%i)", (HAVE_LLVM >> 8) & 0xff,
113 HAVE_LLVM & 0xff, MESA_LLVM_VERSION_PATCH);
114 snprintf(name, name_len, "%s%s", chip_string, llvm_string);
115 }
116
117 static void
118 radv_physical_device_init_mem_types(struct radv_physical_device *device)
119 {
120 STATIC_ASSERT(RADV_MEM_HEAP_COUNT <= VK_MAX_MEMORY_HEAPS);
121 uint64_t visible_vram_size = MIN2(device->rad_info.vram_size,
122 device->rad_info.vram_vis_size);
123
124 int vram_index = -1, visible_vram_index = -1, gart_index = -1;
125 device->memory_properties.memoryHeapCount = 0;
126 if (device->rad_info.vram_size - visible_vram_size > 0) {
127 vram_index = device->memory_properties.memoryHeapCount++;
128 device->memory_properties.memoryHeaps[vram_index] = (VkMemoryHeap) {
129 .size = device->rad_info.vram_size - visible_vram_size,
130 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
131 };
132 }
133 if (visible_vram_size) {
134 visible_vram_index = device->memory_properties.memoryHeapCount++;
135 device->memory_properties.memoryHeaps[visible_vram_index] = (VkMemoryHeap) {
136 .size = visible_vram_size,
137 .flags = VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
138 };
139 }
140 if (device->rad_info.gart_size > 0) {
141 gart_index = device->memory_properties.memoryHeapCount++;
142 device->memory_properties.memoryHeaps[gart_index] = (VkMemoryHeap) {
143 .size = device->rad_info.gart_size,
144 .flags = device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_HEAP_DEVICE_LOCAL_BIT,
145 };
146 }
147
148 STATIC_ASSERT(RADV_MEM_TYPE_COUNT <= VK_MAX_MEMORY_TYPES);
149 unsigned type_count = 0;
150 if (vram_index >= 0) {
151 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM;
152 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
153 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT,
154 .heapIndex = vram_index,
155 };
156 }
157 if (gart_index >= 0) {
158 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_WRITE_COMBINE;
159 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
160 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
161 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
162 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
163 .heapIndex = gart_index,
164 };
165 }
166 if (visible_vram_index >= 0) {
167 device->mem_type_indices[type_count] = RADV_MEM_TYPE_VRAM_CPU_ACCESS;
168 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
169 .propertyFlags = VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT |
170 VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
171 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT,
172 .heapIndex = visible_vram_index,
173 };
174 }
175 if (gart_index >= 0) {
176 device->mem_type_indices[type_count] = RADV_MEM_TYPE_GTT_CACHED;
177 device->memory_properties.memoryTypes[type_count++] = (VkMemoryType) {
178 .propertyFlags = VK_MEMORY_PROPERTY_HOST_VISIBLE_BIT |
179 VK_MEMORY_PROPERTY_HOST_COHERENT_BIT |
180 VK_MEMORY_PROPERTY_HOST_CACHED_BIT |
181 (device->rad_info.has_dedicated_vram ? 0 : VK_MEMORY_PROPERTY_DEVICE_LOCAL_BIT),
182 .heapIndex = gart_index,
183 };
184 }
185 device->memory_properties.memoryTypeCount = type_count;
186 }
187
188 static void
189 radv_handle_env_var_force_family(struct radv_physical_device *device)
190 {
191 const char *family = getenv("RADV_FORCE_FAMILY");
192 unsigned i;
193
194 if (!family)
195 return;
196
197 for (i = CHIP_TAHITI; i < CHIP_LAST; i++) {
198 if (!strcmp(family, ac_get_llvm_processor_name(i))) {
199 /* Override family and chip_class. */
200 device->rad_info.family = i;
201
202 if (i >= CHIP_VEGA10)
203 device->rad_info.chip_class = GFX9;
204 else if (i >= CHIP_TONGA)
205 device->rad_info.chip_class = VI;
206 else if (i >= CHIP_BONAIRE)
207 device->rad_info.chip_class = CIK;
208 else
209 device->rad_info.chip_class = SI;
210
211 return;
212 }
213 }
214
215 fprintf(stderr, "radv: Unknown family: %s\n", family);
216 exit(1);
217 }
218
219 static VkResult
220 radv_physical_device_init(struct radv_physical_device *device,
221 struct radv_instance *instance,
222 drmDevicePtr drm_device)
223 {
224 const char *path = drm_device->nodes[DRM_NODE_RENDER];
225 VkResult result;
226 drmVersionPtr version;
227 int fd;
228 int master_fd = -1;
229
230 fd = open(path, O_RDWR | O_CLOEXEC);
231 if (fd < 0) {
232 if (instance->debug_flags & RADV_DEBUG_STARTUP)
233 radv_logi("Could not open device '%s'", path);
234
235 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
236 }
237
238 version = drmGetVersion(fd);
239 if (!version) {
240 close(fd);
241
242 if (instance->debug_flags & RADV_DEBUG_STARTUP)
243 radv_logi("Could not get the kernel driver version for device '%s'", path);
244
245 return vk_errorf(instance, VK_ERROR_INCOMPATIBLE_DRIVER,
246 "failed to get version %s: %m", path);
247 }
248
249 if (strcmp(version->name, "amdgpu")) {
250 drmFreeVersion(version);
251 if (master_fd != -1)
252 close(master_fd);
253 close(fd);
254
255 if (instance->debug_flags & RADV_DEBUG_STARTUP)
256 radv_logi("Device '%s' is not using the amdgpu kernel driver.", path);
257
258 return VK_ERROR_INCOMPATIBLE_DRIVER;
259 }
260 drmFreeVersion(version);
261
262 if (instance->debug_flags & RADV_DEBUG_STARTUP)
263 radv_logi("Found compatible device '%s'.", path);
264
265 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
266 device->instance = instance;
267 assert(strlen(path) < ARRAY_SIZE(device->path));
268 strncpy(device->path, path, ARRAY_SIZE(device->path));
269
270 device->ws = radv_amdgpu_winsys_create(fd, instance->debug_flags,
271 instance->perftest_flags);
272 if (!device->ws) {
273 result = vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
274 goto fail;
275 }
276
277 if (instance->enabled_extensions.KHR_display) {
278 master_fd = open(drm_device->nodes[DRM_NODE_PRIMARY], O_RDWR | O_CLOEXEC);
279 if (master_fd >= 0) {
280 uint32_t accel_working = 0;
281 struct drm_amdgpu_info request = {
282 .return_pointer = (uintptr_t)&accel_working,
283 .return_size = sizeof(accel_working),
284 .query = AMDGPU_INFO_ACCEL_WORKING
285 };
286
287 if (drmCommandWrite(master_fd, DRM_AMDGPU_INFO, &request, sizeof (struct drm_amdgpu_info)) < 0 || !accel_working) {
288 close(master_fd);
289 master_fd = -1;
290 }
291 }
292 }
293
294 device->master_fd = master_fd;
295 device->local_fd = fd;
296 device->ws->query_info(device->ws, &device->rad_info);
297
298 radv_handle_env_var_force_family(device);
299
300 radv_get_device_name(device->rad_info.family, device->name, sizeof(device->name));
301
302 if (radv_device_get_cache_uuid(device->rad_info.family, device->cache_uuid)) {
303 device->ws->destroy(device->ws);
304 result = vk_errorf(instance, VK_ERROR_INITIALIZATION_FAILED,
305 "cannot generate UUID");
306 goto fail;
307 }
308
309 /* These flags affect shader compilation. */
310 uint64_t shader_env_flags =
311 (device->instance->perftest_flags & RADV_PERFTEST_SISCHED ? 0x1 : 0) |
312 (device->instance->debug_flags & RADV_DEBUG_UNSAFE_MATH ? 0x2 : 0);
313
314 /* The gpu id is already embedded in the uuid so we just pass "radv"
315 * when creating the cache.
316 */
317 char buf[VK_UUID_SIZE * 2 + 1];
318 disk_cache_format_hex_id(buf, device->cache_uuid, VK_UUID_SIZE * 2);
319 device->disk_cache = disk_cache_create(device->name, buf, shader_env_flags);
320
321 if (device->rad_info.chip_class < VI ||
322 device->rad_info.chip_class > GFX9)
323 fprintf(stderr, "WARNING: radv is not a conformant vulkan implementation, testing use only.\n");
324
325 radv_get_driver_uuid(&device->device_uuid);
326 radv_get_device_uuid(&device->rad_info, &device->device_uuid);
327
328 if (device->rad_info.family == CHIP_STONEY ||
329 device->rad_info.chip_class >= GFX9) {
330 device->has_rbplus = true;
331 device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
332 device->rad_info.family == CHIP_VEGA12 ||
333 device->rad_info.family == CHIP_RAVEN;
334 }
335
336 /* The mere presence of CLEAR_STATE in the IB causes random GPU hangs
337 * on SI.
338 */
339 device->has_clear_state = device->rad_info.chip_class >= CIK;
340
341 device->cpdma_prefetch_writes_memory = device->rad_info.chip_class <= VI;
342
343 /* Vega10/Raven need a special workaround for a hardware bug. */
344 device->has_scissor_bug = device->rad_info.family == CHIP_VEGA10 ||
345 device->rad_info.family == CHIP_RAVEN;
346
347 /* Out-of-order primitive rasterization. */
348 device->has_out_of_order_rast = device->rad_info.chip_class >= VI &&
349 device->rad_info.max_se >= 2;
350 device->out_of_order_rast_allowed = device->has_out_of_order_rast &&
351 !(device->instance->debug_flags & RADV_DEBUG_NO_OUT_OF_ORDER);
352
353 device->dcc_msaa_allowed =
354 (device->instance->perftest_flags & RADV_PERFTEST_DCC_MSAA);
355
356 radv_physical_device_init_mem_types(device);
357 radv_fill_device_extension_table(device, &device->supported_extensions);
358
359 result = radv_init_wsi(device);
360 if (result != VK_SUCCESS) {
361 device->ws->destroy(device->ws);
362 vk_error(instance, result);
363 goto fail;
364 }
365
366 if ((device->instance->debug_flags & RADV_DEBUG_INFO))
367 ac_print_gpu_info(&device->rad_info);
368
369 return VK_SUCCESS;
370
371 fail:
372 close(fd);
373 if (master_fd != -1)
374 close(master_fd);
375 return result;
376 }
377
378 static void
379 radv_physical_device_finish(struct radv_physical_device *device)
380 {
381 radv_finish_wsi(device);
382 device->ws->destroy(device->ws);
383 disk_cache_destroy(device->disk_cache);
384 close(device->local_fd);
385 if (device->master_fd != -1)
386 close(device->master_fd);
387 }
388
389 static void *
390 default_alloc_func(void *pUserData, size_t size, size_t align,
391 VkSystemAllocationScope allocationScope)
392 {
393 return malloc(size);
394 }
395
396 static void *
397 default_realloc_func(void *pUserData, void *pOriginal, size_t size,
398 size_t align, VkSystemAllocationScope allocationScope)
399 {
400 return realloc(pOriginal, size);
401 }
402
403 static void
404 default_free_func(void *pUserData, void *pMemory)
405 {
406 free(pMemory);
407 }
408
409 static const VkAllocationCallbacks default_alloc = {
410 .pUserData = NULL,
411 .pfnAllocation = default_alloc_func,
412 .pfnReallocation = default_realloc_func,
413 .pfnFree = default_free_func,
414 };
415
416 static const struct debug_control radv_debug_options[] = {
417 {"nofastclears", RADV_DEBUG_NO_FAST_CLEARS},
418 {"nodcc", RADV_DEBUG_NO_DCC},
419 {"shaders", RADV_DEBUG_DUMP_SHADERS},
420 {"nocache", RADV_DEBUG_NO_CACHE},
421 {"shaderstats", RADV_DEBUG_DUMP_SHADER_STATS},
422 {"nohiz", RADV_DEBUG_NO_HIZ},
423 {"nocompute", RADV_DEBUG_NO_COMPUTE_QUEUE},
424 {"unsafemath", RADV_DEBUG_UNSAFE_MATH},
425 {"allbos", RADV_DEBUG_ALL_BOS},
426 {"noibs", RADV_DEBUG_NO_IBS},
427 {"spirv", RADV_DEBUG_DUMP_SPIRV},
428 {"vmfaults", RADV_DEBUG_VM_FAULTS},
429 {"zerovram", RADV_DEBUG_ZERO_VRAM},
430 {"syncshaders", RADV_DEBUG_SYNC_SHADERS},
431 {"nosisched", RADV_DEBUG_NO_SISCHED},
432 {"preoptir", RADV_DEBUG_PREOPTIR},
433 {"nodynamicbounds", RADV_DEBUG_NO_DYNAMIC_BOUNDS},
434 {"nooutoforder", RADV_DEBUG_NO_OUT_OF_ORDER},
435 {"info", RADV_DEBUG_INFO},
436 {"errors", RADV_DEBUG_ERRORS},
437 {"startup", RADV_DEBUG_STARTUP},
438 {"checkir", RADV_DEBUG_CHECKIR},
439 {"nothreadllvm", RADV_DEBUG_NOTHREADLLVM},
440 {NULL, 0}
441 };
442
443 const char *
444 radv_get_debug_option_name(int id)
445 {
446 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
447 return radv_debug_options[id].string;
448 }
449
450 static const struct debug_control radv_perftest_options[] = {
451 {"nobatchchain", RADV_PERFTEST_NO_BATCHCHAIN},
452 {"sisched", RADV_PERFTEST_SISCHED},
453 {"localbos", RADV_PERFTEST_LOCAL_BOS},
454 {"binning", RADV_PERFTEST_BINNING},
455 {"dccmsaa", RADV_PERFTEST_DCC_MSAA},
456 {NULL, 0}
457 };
458
459 const char *
460 radv_get_perftest_option_name(int id)
461 {
462 assert(id < ARRAY_SIZE(radv_debug_options) - 1);
463 return radv_perftest_options[id].string;
464 }
465
466 static void
467 radv_handle_per_app_options(struct radv_instance *instance,
468 const VkApplicationInfo *info)
469 {
470 const char *name = info ? info->pApplicationName : NULL;
471
472 if (!name)
473 return;
474
475 if (!strcmp(name, "Talos - Linux - 32bit") ||
476 !strcmp(name, "Talos - Linux - 64bit")) {
477 if (!(instance->debug_flags & RADV_DEBUG_NO_SISCHED)) {
478 /* Force enable LLVM sisched for Talos because it looks
479 * safe and it gives few more FPS.
480 */
481 instance->perftest_flags |= RADV_PERFTEST_SISCHED;
482 }
483 } else if (!strcmp(name, "DOOM_VFR")) {
484 /* Work around a Doom VFR game bug */
485 instance->debug_flags |= RADV_DEBUG_NO_DYNAMIC_BOUNDS;
486 }
487 }
488
489 static int radv_get_instance_extension_index(const char *name)
490 {
491 for (unsigned i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; ++i) {
492 if (strcmp(name, radv_instance_extensions[i].extensionName) == 0)
493 return i;
494 }
495 return -1;
496 }
497
498
499 VkResult radv_CreateInstance(
500 const VkInstanceCreateInfo* pCreateInfo,
501 const VkAllocationCallbacks* pAllocator,
502 VkInstance* pInstance)
503 {
504 struct radv_instance *instance;
505 VkResult result;
506
507 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_INSTANCE_CREATE_INFO);
508
509 uint32_t client_version;
510 if (pCreateInfo->pApplicationInfo &&
511 pCreateInfo->pApplicationInfo->apiVersion != 0) {
512 client_version = pCreateInfo->pApplicationInfo->apiVersion;
513 } else {
514 radv_EnumerateInstanceVersion(&client_version);
515 }
516
517 instance = vk_zalloc2(&default_alloc, pAllocator, sizeof(*instance), 8,
518 VK_SYSTEM_ALLOCATION_SCOPE_INSTANCE);
519 if (!instance)
520 return vk_error(NULL, VK_ERROR_OUT_OF_HOST_MEMORY);
521
522 instance->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
523
524 if (pAllocator)
525 instance->alloc = *pAllocator;
526 else
527 instance->alloc = default_alloc;
528
529 instance->apiVersion = client_version;
530 instance->physicalDeviceCount = -1;
531
532 instance->debug_flags = parse_debug_string(getenv("RADV_DEBUG"),
533 radv_debug_options);
534
535 instance->perftest_flags = parse_debug_string(getenv("RADV_PERFTEST"),
536 radv_perftest_options);
537
538
539 if (instance->debug_flags & RADV_DEBUG_STARTUP)
540 radv_logi("Created an instance");
541
542 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
543 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
544 int index = radv_get_instance_extension_index(ext_name);
545
546 if (index < 0 || !radv_supported_instance_extensions.extensions[index]) {
547 vk_free2(&default_alloc, pAllocator, instance);
548 return vk_error(instance, VK_ERROR_EXTENSION_NOT_PRESENT);
549 }
550
551 instance->enabled_extensions.extensions[index] = true;
552 }
553
554 result = vk_debug_report_instance_init(&instance->debug_report_callbacks);
555 if (result != VK_SUCCESS) {
556 vk_free2(&default_alloc, pAllocator, instance);
557 return vk_error(instance, result);
558 }
559
560 _mesa_locale_init();
561
562 VG(VALGRIND_CREATE_MEMPOOL(instance, 0, false));
563
564 radv_handle_per_app_options(instance, pCreateInfo->pApplicationInfo);
565
566 *pInstance = radv_instance_to_handle(instance);
567
568 return VK_SUCCESS;
569 }
570
571 void radv_DestroyInstance(
572 VkInstance _instance,
573 const VkAllocationCallbacks* pAllocator)
574 {
575 RADV_FROM_HANDLE(radv_instance, instance, _instance);
576
577 if (!instance)
578 return;
579
580 for (int i = 0; i < instance->physicalDeviceCount; ++i) {
581 radv_physical_device_finish(instance->physicalDevices + i);
582 }
583
584 VG(VALGRIND_DESTROY_MEMPOOL(instance));
585
586 _mesa_locale_fini();
587
588 vk_debug_report_instance_destroy(&instance->debug_report_callbacks);
589
590 vk_free(&instance->alloc, instance);
591 }
592
593 static VkResult
594 radv_enumerate_devices(struct radv_instance *instance)
595 {
596 /* TODO: Check for more devices ? */
597 drmDevicePtr devices[8];
598 VkResult result = VK_ERROR_INCOMPATIBLE_DRIVER;
599 int max_devices;
600
601 instance->physicalDeviceCount = 0;
602
603 max_devices = drmGetDevices2(0, devices, ARRAY_SIZE(devices));
604
605 if (instance->debug_flags & RADV_DEBUG_STARTUP)
606 radv_logi("Found %d drm nodes", max_devices);
607
608 if (max_devices < 1)
609 return vk_error(instance, VK_ERROR_INCOMPATIBLE_DRIVER);
610
611 for (unsigned i = 0; i < (unsigned)max_devices; i++) {
612 if (devices[i]->available_nodes & 1 << DRM_NODE_RENDER &&
613 devices[i]->bustype == DRM_BUS_PCI &&
614 devices[i]->deviceinfo.pci->vendor_id == ATI_VENDOR_ID) {
615
616 result = radv_physical_device_init(instance->physicalDevices +
617 instance->physicalDeviceCount,
618 instance,
619 devices[i]);
620 if (result == VK_SUCCESS)
621 ++instance->physicalDeviceCount;
622 else if (result != VK_ERROR_INCOMPATIBLE_DRIVER)
623 break;
624 }
625 }
626 drmFreeDevices(devices, max_devices);
627
628 return result;
629 }
630
631 VkResult radv_EnumeratePhysicalDevices(
632 VkInstance _instance,
633 uint32_t* pPhysicalDeviceCount,
634 VkPhysicalDevice* pPhysicalDevices)
635 {
636 RADV_FROM_HANDLE(radv_instance, instance, _instance);
637 VkResult result;
638
639 if (instance->physicalDeviceCount < 0) {
640 result = radv_enumerate_devices(instance);
641 if (result != VK_SUCCESS &&
642 result != VK_ERROR_INCOMPATIBLE_DRIVER)
643 return result;
644 }
645
646 if (!pPhysicalDevices) {
647 *pPhysicalDeviceCount = instance->physicalDeviceCount;
648 } else {
649 *pPhysicalDeviceCount = MIN2(*pPhysicalDeviceCount, instance->physicalDeviceCount);
650 for (unsigned i = 0; i < *pPhysicalDeviceCount; ++i)
651 pPhysicalDevices[i] = radv_physical_device_to_handle(instance->physicalDevices + i);
652 }
653
654 return *pPhysicalDeviceCount < instance->physicalDeviceCount ? VK_INCOMPLETE
655 : VK_SUCCESS;
656 }
657
658 VkResult radv_EnumeratePhysicalDeviceGroups(
659 VkInstance _instance,
660 uint32_t* pPhysicalDeviceGroupCount,
661 VkPhysicalDeviceGroupProperties* pPhysicalDeviceGroupProperties)
662 {
663 RADV_FROM_HANDLE(radv_instance, instance, _instance);
664 VkResult result;
665
666 if (instance->physicalDeviceCount < 0) {
667 result = radv_enumerate_devices(instance);
668 if (result != VK_SUCCESS &&
669 result != VK_ERROR_INCOMPATIBLE_DRIVER)
670 return result;
671 }
672
673 if (!pPhysicalDeviceGroupProperties) {
674 *pPhysicalDeviceGroupCount = instance->physicalDeviceCount;
675 } else {
676 *pPhysicalDeviceGroupCount = MIN2(*pPhysicalDeviceGroupCount, instance->physicalDeviceCount);
677 for (unsigned i = 0; i < *pPhysicalDeviceGroupCount; ++i) {
678 pPhysicalDeviceGroupProperties[i].physicalDeviceCount = 1;
679 pPhysicalDeviceGroupProperties[i].physicalDevices[0] = radv_physical_device_to_handle(instance->physicalDevices + i);
680 pPhysicalDeviceGroupProperties[i].subsetAllocation = false;
681 }
682 }
683 return *pPhysicalDeviceGroupCount < instance->physicalDeviceCount ? VK_INCOMPLETE
684 : VK_SUCCESS;
685 }
686
687 void radv_GetPhysicalDeviceFeatures(
688 VkPhysicalDevice physicalDevice,
689 VkPhysicalDeviceFeatures* pFeatures)
690 {
691 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
692 memset(pFeatures, 0, sizeof(*pFeatures));
693
694 *pFeatures = (VkPhysicalDeviceFeatures) {
695 .robustBufferAccess = true,
696 .fullDrawIndexUint32 = true,
697 .imageCubeArray = true,
698 .independentBlend = true,
699 .geometryShader = true,
700 .tessellationShader = true,
701 .sampleRateShading = true,
702 .dualSrcBlend = true,
703 .logicOp = true,
704 .multiDrawIndirect = true,
705 .drawIndirectFirstInstance = true,
706 .depthClamp = true,
707 .depthBiasClamp = true,
708 .fillModeNonSolid = true,
709 .depthBounds = true,
710 .wideLines = true,
711 .largePoints = true,
712 .alphaToOne = true,
713 .multiViewport = true,
714 .samplerAnisotropy = true,
715 .textureCompressionETC2 = pdevice->rad_info.chip_class >= GFX9 ||
716 pdevice->rad_info.family == CHIP_STONEY,
717 .textureCompressionASTC_LDR = false,
718 .textureCompressionBC = true,
719 .occlusionQueryPrecise = true,
720 .pipelineStatisticsQuery = true,
721 .vertexPipelineStoresAndAtomics = true,
722 .fragmentStoresAndAtomics = true,
723 .shaderTessellationAndGeometryPointSize = true,
724 .shaderImageGatherExtended = true,
725 .shaderStorageImageExtendedFormats = true,
726 .shaderStorageImageMultisample = false,
727 .shaderUniformBufferArrayDynamicIndexing = true,
728 .shaderSampledImageArrayDynamicIndexing = true,
729 .shaderStorageBufferArrayDynamicIndexing = true,
730 .shaderStorageImageArrayDynamicIndexing = true,
731 .shaderStorageImageReadWithoutFormat = true,
732 .shaderStorageImageWriteWithoutFormat = true,
733 .shaderClipDistance = true,
734 .shaderCullDistance = true,
735 .shaderFloat64 = true,
736 .shaderInt64 = true,
737 .shaderInt16 = false,
738 .sparseBinding = true,
739 .variableMultisampleRate = true,
740 .inheritedQueries = true,
741 };
742 }
743
744 void radv_GetPhysicalDeviceFeatures2(
745 VkPhysicalDevice physicalDevice,
746 VkPhysicalDeviceFeatures2KHR *pFeatures)
747 {
748 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
749 vk_foreach_struct(ext, pFeatures->pNext) {
750 switch (ext->sType) {
751 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VARIABLE_POINTER_FEATURES_KHR: {
752 VkPhysicalDeviceVariablePointerFeaturesKHR *features = (void *)ext;
753 features->variablePointersStorageBuffer = true;
754 features->variablePointers = false;
755 break;
756 }
757 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_FEATURES_KHR: {
758 VkPhysicalDeviceMultiviewFeaturesKHR *features = (VkPhysicalDeviceMultiviewFeaturesKHR*)ext;
759 features->multiview = true;
760 features->multiviewGeometryShader = true;
761 features->multiviewTessellationShader = true;
762 break;
763 }
764 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_DRAW_PARAMETER_FEATURES: {
765 VkPhysicalDeviceShaderDrawParameterFeatures *features =
766 (VkPhysicalDeviceShaderDrawParameterFeatures*)ext;
767 features->shaderDrawParameters = true;
768 break;
769 }
770 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_FEATURES: {
771 VkPhysicalDeviceProtectedMemoryFeatures *features =
772 (VkPhysicalDeviceProtectedMemoryFeatures*)ext;
773 features->protectedMemory = false;
774 break;
775 }
776 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_16BIT_STORAGE_FEATURES: {
777 VkPhysicalDevice16BitStorageFeatures *features =
778 (VkPhysicalDevice16BitStorageFeatures*)ext;
779 bool enabled = HAVE_LLVM >= 0x0700 && pdevice->rad_info.chip_class >= VI;
780 features->storageBuffer16BitAccess = enabled;
781 features->uniformAndStorageBuffer16BitAccess = enabled;
782 features->storagePushConstant16 = enabled;
783 features->storageInputOutput16 = enabled;
784 break;
785 }
786 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES: {
787 VkPhysicalDeviceSamplerYcbcrConversionFeatures *features =
788 (VkPhysicalDeviceSamplerYcbcrConversionFeatures*)ext;
789 features->samplerYcbcrConversion = false;
790 break;
791 }
792 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_FEATURES_EXT: {
793 VkPhysicalDeviceDescriptorIndexingFeaturesEXT *features =
794 (VkPhysicalDeviceDescriptorIndexingFeaturesEXT*)ext;
795 features->shaderInputAttachmentArrayDynamicIndexing = true;
796 features->shaderUniformTexelBufferArrayDynamicIndexing = true;
797 features->shaderStorageTexelBufferArrayDynamicIndexing = true;
798 features->shaderUniformBufferArrayNonUniformIndexing = false;
799 features->shaderSampledImageArrayNonUniformIndexing = false;
800 features->shaderStorageBufferArrayNonUniformIndexing = false;
801 features->shaderStorageImageArrayNonUniformIndexing = false;
802 features->shaderInputAttachmentArrayNonUniformIndexing = false;
803 features->shaderUniformTexelBufferArrayNonUniformIndexing = false;
804 features->shaderStorageTexelBufferArrayNonUniformIndexing = false;
805 features->descriptorBindingUniformBufferUpdateAfterBind = true;
806 features->descriptorBindingSampledImageUpdateAfterBind = true;
807 features->descriptorBindingStorageImageUpdateAfterBind = true;
808 features->descriptorBindingStorageBufferUpdateAfterBind = true;
809 features->descriptorBindingUniformTexelBufferUpdateAfterBind = true;
810 features->descriptorBindingStorageTexelBufferUpdateAfterBind = true;
811 features->descriptorBindingUpdateUnusedWhilePending = true;
812 features->descriptorBindingPartiallyBound = true;
813 features->descriptorBindingVariableDescriptorCount = true;
814 features->runtimeDescriptorArray = true;
815 break;
816 }
817 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_CONDITIONAL_RENDERING_FEATURES_EXT: {
818 VkPhysicalDeviceConditionalRenderingFeaturesEXT *features =
819 (VkPhysicalDeviceConditionalRenderingFeaturesEXT*)ext;
820 features->conditionalRendering = true;
821 features->inheritedConditionalRendering = false;
822 break;
823 }
824 default:
825 break;
826 }
827 }
828 return radv_GetPhysicalDeviceFeatures(physicalDevice, &pFeatures->features);
829 }
830
831 void radv_GetPhysicalDeviceProperties(
832 VkPhysicalDevice physicalDevice,
833 VkPhysicalDeviceProperties* pProperties)
834 {
835 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
836 VkSampleCountFlags sample_counts = 0xf;
837
838 /* make sure that the entire descriptor set is addressable with a signed
839 * 32-bit int. So the sum of all limits scaled by descriptor size has to
840 * be at most 2 GiB. the combined image & samples object count as one of
841 * both. This limit is for the pipeline layout, not for the set layout, but
842 * there is no set limit, so we just set a pipeline limit. I don't think
843 * any app is going to hit this soon. */
844 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
845 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
846 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
847 32 /* sampler, largest when combined with image */ +
848 64 /* sampled image */ +
849 64 /* storage image */);
850
851 VkPhysicalDeviceLimits limits = {
852 .maxImageDimension1D = (1 << 14),
853 .maxImageDimension2D = (1 << 14),
854 .maxImageDimension3D = (1 << 11),
855 .maxImageDimensionCube = (1 << 14),
856 .maxImageArrayLayers = (1 << 11),
857 .maxTexelBufferElements = 128 * 1024 * 1024,
858 .maxUniformBufferRange = UINT32_MAX,
859 .maxStorageBufferRange = UINT32_MAX,
860 .maxPushConstantsSize = MAX_PUSH_CONSTANTS_SIZE,
861 .maxMemoryAllocationCount = UINT32_MAX,
862 .maxSamplerAllocationCount = 64 * 1024,
863 .bufferImageGranularity = 64, /* A cache line */
864 .sparseAddressSpaceSize = 0xffffffffu, /* buffer max size */
865 .maxBoundDescriptorSets = MAX_SETS,
866 .maxPerStageDescriptorSamplers = max_descriptor_set_size,
867 .maxPerStageDescriptorUniformBuffers = max_descriptor_set_size,
868 .maxPerStageDescriptorStorageBuffers = max_descriptor_set_size,
869 .maxPerStageDescriptorSampledImages = max_descriptor_set_size,
870 .maxPerStageDescriptorStorageImages = max_descriptor_set_size,
871 .maxPerStageDescriptorInputAttachments = max_descriptor_set_size,
872 .maxPerStageResources = max_descriptor_set_size,
873 .maxDescriptorSetSamplers = max_descriptor_set_size,
874 .maxDescriptorSetUniformBuffers = max_descriptor_set_size,
875 .maxDescriptorSetUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS,
876 .maxDescriptorSetStorageBuffers = max_descriptor_set_size,
877 .maxDescriptorSetStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS,
878 .maxDescriptorSetSampledImages = max_descriptor_set_size,
879 .maxDescriptorSetStorageImages = max_descriptor_set_size,
880 .maxDescriptorSetInputAttachments = max_descriptor_set_size,
881 .maxVertexInputAttributes = 32,
882 .maxVertexInputBindings = 32,
883 .maxVertexInputAttributeOffset = 2047,
884 .maxVertexInputBindingStride = 2048,
885 .maxVertexOutputComponents = 128,
886 .maxTessellationGenerationLevel = 64,
887 .maxTessellationPatchSize = 32,
888 .maxTessellationControlPerVertexInputComponents = 128,
889 .maxTessellationControlPerVertexOutputComponents = 128,
890 .maxTessellationControlPerPatchOutputComponents = 120,
891 .maxTessellationControlTotalOutputComponents = 4096,
892 .maxTessellationEvaluationInputComponents = 128,
893 .maxTessellationEvaluationOutputComponents = 128,
894 .maxGeometryShaderInvocations = 127,
895 .maxGeometryInputComponents = 64,
896 .maxGeometryOutputComponents = 128,
897 .maxGeometryOutputVertices = 256,
898 .maxGeometryTotalOutputComponents = 1024,
899 .maxFragmentInputComponents = 128,
900 .maxFragmentOutputAttachments = 8,
901 .maxFragmentDualSrcAttachments = 1,
902 .maxFragmentCombinedOutputResources = 8,
903 .maxComputeSharedMemorySize = 32768,
904 .maxComputeWorkGroupCount = { 65535, 65535, 65535 },
905 .maxComputeWorkGroupInvocations = 2048,
906 .maxComputeWorkGroupSize = {
907 2048,
908 2048,
909 2048
910 },
911 .subPixelPrecisionBits = 4 /* FIXME */,
912 .subTexelPrecisionBits = 4 /* FIXME */,
913 .mipmapPrecisionBits = 4 /* FIXME */,
914 .maxDrawIndexedIndexValue = UINT32_MAX,
915 .maxDrawIndirectCount = UINT32_MAX,
916 .maxSamplerLodBias = 16,
917 .maxSamplerAnisotropy = 16,
918 .maxViewports = MAX_VIEWPORTS,
919 .maxViewportDimensions = { (1 << 14), (1 << 14) },
920 .viewportBoundsRange = { INT16_MIN, INT16_MAX },
921 .viewportSubPixelBits = 8,
922 .minMemoryMapAlignment = 4096, /* A page */
923 .minTexelBufferOffsetAlignment = 1,
924 .minUniformBufferOffsetAlignment = 4,
925 .minStorageBufferOffsetAlignment = 4,
926 .minTexelOffset = -32,
927 .maxTexelOffset = 31,
928 .minTexelGatherOffset = -32,
929 .maxTexelGatherOffset = 31,
930 .minInterpolationOffset = -2,
931 .maxInterpolationOffset = 2,
932 .subPixelInterpolationOffsetBits = 8,
933 .maxFramebufferWidth = (1 << 14),
934 .maxFramebufferHeight = (1 << 14),
935 .maxFramebufferLayers = (1 << 10),
936 .framebufferColorSampleCounts = sample_counts,
937 .framebufferDepthSampleCounts = sample_counts,
938 .framebufferStencilSampleCounts = sample_counts,
939 .framebufferNoAttachmentsSampleCounts = sample_counts,
940 .maxColorAttachments = MAX_RTS,
941 .sampledImageColorSampleCounts = sample_counts,
942 .sampledImageIntegerSampleCounts = VK_SAMPLE_COUNT_1_BIT,
943 .sampledImageDepthSampleCounts = sample_counts,
944 .sampledImageStencilSampleCounts = sample_counts,
945 .storageImageSampleCounts = VK_SAMPLE_COUNT_1_BIT,
946 .maxSampleMaskWords = 1,
947 .timestampComputeAndGraphics = true,
948 .timestampPeriod = 1000000.0 / pdevice->rad_info.clock_crystal_freq,
949 .maxClipDistances = 8,
950 .maxCullDistances = 8,
951 .maxCombinedClipAndCullDistances = 8,
952 .discreteQueuePriorities = 1,
953 .pointSizeRange = { 0.125, 255.875 },
954 .lineWidthRange = { 0.0, 7.9921875 },
955 .pointSizeGranularity = (1.0 / 8.0),
956 .lineWidthGranularity = (1.0 / 128.0),
957 .strictLines = false, /* FINISHME */
958 .standardSampleLocations = true,
959 .optimalBufferCopyOffsetAlignment = 128,
960 .optimalBufferCopyRowPitchAlignment = 128,
961 .nonCoherentAtomSize = 64,
962 };
963
964 *pProperties = (VkPhysicalDeviceProperties) {
965 .apiVersion = radv_physical_device_api_version(pdevice),
966 .driverVersion = vk_get_driver_version(),
967 .vendorID = ATI_VENDOR_ID,
968 .deviceID = pdevice->rad_info.pci_id,
969 .deviceType = pdevice->rad_info.has_dedicated_vram ? VK_PHYSICAL_DEVICE_TYPE_DISCRETE_GPU : VK_PHYSICAL_DEVICE_TYPE_INTEGRATED_GPU,
970 .limits = limits,
971 .sparseProperties = {0},
972 };
973
974 strcpy(pProperties->deviceName, pdevice->name);
975 memcpy(pProperties->pipelineCacheUUID, pdevice->cache_uuid, VK_UUID_SIZE);
976 }
977
978 void radv_GetPhysicalDeviceProperties2(
979 VkPhysicalDevice physicalDevice,
980 VkPhysicalDeviceProperties2KHR *pProperties)
981 {
982 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
983 radv_GetPhysicalDeviceProperties(physicalDevice, &pProperties->properties);
984
985 vk_foreach_struct(ext, pProperties->pNext) {
986 switch (ext->sType) {
987 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PUSH_DESCRIPTOR_PROPERTIES_KHR: {
988 VkPhysicalDevicePushDescriptorPropertiesKHR *properties =
989 (VkPhysicalDevicePushDescriptorPropertiesKHR *) ext;
990 properties->maxPushDescriptors = MAX_PUSH_DESCRIPTORS;
991 break;
992 }
993 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_ID_PROPERTIES_KHR: {
994 VkPhysicalDeviceIDPropertiesKHR *properties = (VkPhysicalDeviceIDPropertiesKHR*)ext;
995 memcpy(properties->driverUUID, pdevice->driver_uuid, VK_UUID_SIZE);
996 memcpy(properties->deviceUUID, pdevice->device_uuid, VK_UUID_SIZE);
997 properties->deviceLUIDValid = false;
998 break;
999 }
1000 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MULTIVIEW_PROPERTIES_KHR: {
1001 VkPhysicalDeviceMultiviewPropertiesKHR *properties = (VkPhysicalDeviceMultiviewPropertiesKHR*)ext;
1002 properties->maxMultiviewViewCount = MAX_VIEWS;
1003 properties->maxMultiviewInstanceIndex = INT_MAX;
1004 break;
1005 }
1006 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_POINT_CLIPPING_PROPERTIES_KHR: {
1007 VkPhysicalDevicePointClippingPropertiesKHR *properties =
1008 (VkPhysicalDevicePointClippingPropertiesKHR*)ext;
1009 properties->pointClippingBehavior = VK_POINT_CLIPPING_BEHAVIOR_ALL_CLIP_PLANES_KHR;
1010 break;
1011 }
1012 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DISCARD_RECTANGLE_PROPERTIES_EXT: {
1013 VkPhysicalDeviceDiscardRectanglePropertiesEXT *properties =
1014 (VkPhysicalDeviceDiscardRectanglePropertiesEXT*)ext;
1015 properties->maxDiscardRectangles = MAX_DISCARD_RECTANGLES;
1016 break;
1017 }
1018 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_EXTERNAL_MEMORY_HOST_PROPERTIES_EXT: {
1019 VkPhysicalDeviceExternalMemoryHostPropertiesEXT *properties =
1020 (VkPhysicalDeviceExternalMemoryHostPropertiesEXT *) ext;
1021 properties->minImportedHostPointerAlignment = 4096;
1022 break;
1023 }
1024 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SUBGROUP_PROPERTIES: {
1025 VkPhysicalDeviceSubgroupProperties *properties =
1026 (VkPhysicalDeviceSubgroupProperties*)ext;
1027 properties->subgroupSize = 64;
1028 properties->supportedStages = VK_SHADER_STAGE_ALL;
1029 properties->supportedOperations =
1030 VK_SUBGROUP_FEATURE_BASIC_BIT |
1031 VK_SUBGROUP_FEATURE_BALLOT_BIT |
1032 VK_SUBGROUP_FEATURE_QUAD_BIT |
1033 VK_SUBGROUP_FEATURE_VOTE_BIT;
1034 if (pdevice->rad_info.chip_class >= VI) {
1035 properties->supportedOperations |=
1036 VK_SUBGROUP_FEATURE_SHUFFLE_BIT |
1037 VK_SUBGROUP_FEATURE_SHUFFLE_RELATIVE_BIT;
1038 }
1039 properties->quadOperationsInAllStages = true;
1040 break;
1041 }
1042 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_MAINTENANCE_3_PROPERTIES: {
1043 VkPhysicalDeviceMaintenance3Properties *properties =
1044 (VkPhysicalDeviceMaintenance3Properties*)ext;
1045 /* Make sure everything is addressable by a signed 32-bit int, and
1046 * our largest descriptors are 96 bytes. */
1047 properties->maxPerSetDescriptors = (1ull << 31) / 96;
1048 /* Our buffer size fields allow only this much */
1049 properties->maxMemoryAllocationSize = 0xFFFFFFFFull;
1050 break;
1051 }
1052 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_FILTER_MINMAX_PROPERTIES_EXT: {
1053 VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *properties =
1054 (VkPhysicalDeviceSamplerFilterMinmaxPropertiesEXT *)ext;
1055 /* GFX6-8 only support single channel min/max filter. */
1056 properties->filterMinmaxImageComponentMapping = pdevice->rad_info.chip_class >= GFX9;
1057 properties->filterMinmaxSingleComponentFormats = true;
1058 break;
1059 }
1060 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SHADER_CORE_PROPERTIES_AMD: {
1061 VkPhysicalDeviceShaderCorePropertiesAMD *properties =
1062 (VkPhysicalDeviceShaderCorePropertiesAMD *)ext;
1063
1064 /* Shader engines. */
1065 properties->shaderEngineCount =
1066 pdevice->rad_info.max_se;
1067 properties->shaderArraysPerEngineCount =
1068 pdevice->rad_info.max_sh_per_se;
1069 properties->computeUnitsPerShaderArray =
1070 pdevice->rad_info.num_good_compute_units /
1071 (pdevice->rad_info.max_se *
1072 pdevice->rad_info.max_sh_per_se);
1073 properties->simdPerComputeUnit = 4;
1074 properties->wavefrontsPerSimd =
1075 pdevice->rad_info.family == CHIP_TONGA ||
1076 pdevice->rad_info.family == CHIP_ICELAND ||
1077 pdevice->rad_info.family == CHIP_POLARIS10 ||
1078 pdevice->rad_info.family == CHIP_POLARIS11 ||
1079 pdevice->rad_info.family == CHIP_POLARIS12 ||
1080 pdevice->rad_info.family == CHIP_VEGAM ? 8 : 10;
1081 properties->wavefrontSize = 64;
1082
1083 /* SGPR. */
1084 properties->sgprsPerSimd =
1085 radv_get_num_physical_sgprs(pdevice);
1086 properties->minSgprAllocation =
1087 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1088 properties->maxSgprAllocation =
1089 pdevice->rad_info.family == CHIP_TONGA ||
1090 pdevice->rad_info.family == CHIP_ICELAND ? 96 : 104;
1091 properties->sgprAllocationGranularity =
1092 pdevice->rad_info.chip_class >= VI ? 16 : 8;
1093
1094 /* VGPR. */
1095 properties->vgprsPerSimd = RADV_NUM_PHYSICAL_VGPRS;
1096 properties->minVgprAllocation = 4;
1097 properties->maxVgprAllocation = 256;
1098 properties->vgprAllocationGranularity = 4;
1099 break;
1100 }
1101 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_VERTEX_ATTRIBUTE_DIVISOR_PROPERTIES_EXT: {
1102 VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *properties =
1103 (VkPhysicalDeviceVertexAttributeDivisorPropertiesEXT *)ext;
1104 properties->maxVertexAttribDivisor = UINT32_MAX;
1105 break;
1106 }
1107 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_DESCRIPTOR_INDEXING_PROPERTIES_EXT: {
1108 VkPhysicalDeviceDescriptorIndexingPropertiesEXT *properties =
1109 (VkPhysicalDeviceDescriptorIndexingPropertiesEXT*)ext;
1110 properties->maxUpdateAfterBindDescriptorsInAllPools = UINT32_MAX / 64;
1111 properties->shaderUniformBufferArrayNonUniformIndexingNative = false;
1112 properties->shaderSampledImageArrayNonUniformIndexingNative = false;
1113 properties->shaderStorageBufferArrayNonUniformIndexingNative = false;
1114 properties->shaderStorageImageArrayNonUniformIndexingNative = false;
1115 properties->shaderInputAttachmentArrayNonUniformIndexingNative = false;
1116 properties->robustBufferAccessUpdateAfterBind = false;
1117 properties->quadDivergentImplicitLod = false;
1118
1119 size_t max_descriptor_set_size = ((1ull << 31) - 16 * MAX_DYNAMIC_BUFFERS) /
1120 (32 /* uniform buffer, 32 due to potential space wasted on alignment */ +
1121 32 /* storage buffer, 32 due to potential space wasted on alignment */ +
1122 32 /* sampler, largest when combined with image */ +
1123 64 /* sampled image */ +
1124 64 /* storage image */);
1125 properties->maxPerStageDescriptorUpdateAfterBindSamplers = max_descriptor_set_size;
1126 properties->maxPerStageDescriptorUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1127 properties->maxPerStageDescriptorUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1128 properties->maxPerStageDescriptorUpdateAfterBindSampledImages = max_descriptor_set_size;
1129 properties->maxPerStageDescriptorUpdateAfterBindStorageImages = max_descriptor_set_size;
1130 properties->maxPerStageDescriptorUpdateAfterBindInputAttachments = max_descriptor_set_size;
1131 properties->maxPerStageUpdateAfterBindResources = max_descriptor_set_size;
1132 properties->maxDescriptorSetUpdateAfterBindSamplers = max_descriptor_set_size;
1133 properties->maxDescriptorSetUpdateAfterBindUniformBuffers = max_descriptor_set_size;
1134 properties->maxDescriptorSetUpdateAfterBindUniformBuffersDynamic = MAX_DYNAMIC_UNIFORM_BUFFERS;
1135 properties->maxDescriptorSetUpdateAfterBindStorageBuffers = max_descriptor_set_size;
1136 properties->maxDescriptorSetUpdateAfterBindStorageBuffersDynamic = MAX_DYNAMIC_STORAGE_BUFFERS;
1137 properties->maxDescriptorSetUpdateAfterBindSampledImages = max_descriptor_set_size;
1138 properties->maxDescriptorSetUpdateAfterBindStorageImages = max_descriptor_set_size;
1139 properties->maxDescriptorSetUpdateAfterBindInputAttachments = max_descriptor_set_size;
1140 break;
1141 }
1142 case VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_PROTECTED_MEMORY_PROPERTIES: {
1143 VkPhysicalDeviceProtectedMemoryProperties *properties =
1144 (VkPhysicalDeviceProtectedMemoryProperties *)ext;
1145 properties->protectedNoFault = false;
1146 break;
1147 }
1148 default:
1149 break;
1150 }
1151 }
1152 }
1153
1154 static void radv_get_physical_device_queue_family_properties(
1155 struct radv_physical_device* pdevice,
1156 uint32_t* pCount,
1157 VkQueueFamilyProperties** pQueueFamilyProperties)
1158 {
1159 int num_queue_families = 1;
1160 int idx;
1161 if (pdevice->rad_info.num_compute_rings > 0 &&
1162 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE))
1163 num_queue_families++;
1164
1165 if (pQueueFamilyProperties == NULL) {
1166 *pCount = num_queue_families;
1167 return;
1168 }
1169
1170 if (!*pCount)
1171 return;
1172
1173 idx = 0;
1174 if (*pCount >= 1) {
1175 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1176 .queueFlags = VK_QUEUE_GRAPHICS_BIT |
1177 VK_QUEUE_COMPUTE_BIT |
1178 VK_QUEUE_TRANSFER_BIT |
1179 VK_QUEUE_SPARSE_BINDING_BIT,
1180 .queueCount = 1,
1181 .timestampValidBits = 64,
1182 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1183 };
1184 idx++;
1185 }
1186
1187 if (pdevice->rad_info.num_compute_rings > 0 &&
1188 !(pdevice->instance->debug_flags & RADV_DEBUG_NO_COMPUTE_QUEUE)) {
1189 if (*pCount > idx) {
1190 *pQueueFamilyProperties[idx] = (VkQueueFamilyProperties) {
1191 .queueFlags = VK_QUEUE_COMPUTE_BIT |
1192 VK_QUEUE_TRANSFER_BIT |
1193 VK_QUEUE_SPARSE_BINDING_BIT,
1194 .queueCount = pdevice->rad_info.num_compute_rings,
1195 .timestampValidBits = 64,
1196 .minImageTransferGranularity = (VkExtent3D) { 1, 1, 1 },
1197 };
1198 idx++;
1199 }
1200 }
1201 *pCount = idx;
1202 }
1203
1204 void radv_GetPhysicalDeviceQueueFamilyProperties(
1205 VkPhysicalDevice physicalDevice,
1206 uint32_t* pCount,
1207 VkQueueFamilyProperties* pQueueFamilyProperties)
1208 {
1209 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1210 if (!pQueueFamilyProperties) {
1211 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1212 return;
1213 }
1214 VkQueueFamilyProperties *properties[] = {
1215 pQueueFamilyProperties + 0,
1216 pQueueFamilyProperties + 1,
1217 pQueueFamilyProperties + 2,
1218 };
1219 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1220 assert(*pCount <= 3);
1221 }
1222
1223 void radv_GetPhysicalDeviceQueueFamilyProperties2(
1224 VkPhysicalDevice physicalDevice,
1225 uint32_t* pCount,
1226 VkQueueFamilyProperties2KHR *pQueueFamilyProperties)
1227 {
1228 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
1229 if (!pQueueFamilyProperties) {
1230 return radv_get_physical_device_queue_family_properties(pdevice, pCount, NULL);
1231 return;
1232 }
1233 VkQueueFamilyProperties *properties[] = {
1234 &pQueueFamilyProperties[0].queueFamilyProperties,
1235 &pQueueFamilyProperties[1].queueFamilyProperties,
1236 &pQueueFamilyProperties[2].queueFamilyProperties,
1237 };
1238 radv_get_physical_device_queue_family_properties(pdevice, pCount, properties);
1239 assert(*pCount <= 3);
1240 }
1241
1242 void radv_GetPhysicalDeviceMemoryProperties(
1243 VkPhysicalDevice physicalDevice,
1244 VkPhysicalDeviceMemoryProperties *pMemoryProperties)
1245 {
1246 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1247
1248 *pMemoryProperties = physical_device->memory_properties;
1249 }
1250
1251 void radv_GetPhysicalDeviceMemoryProperties2(
1252 VkPhysicalDevice physicalDevice,
1253 VkPhysicalDeviceMemoryProperties2KHR *pMemoryProperties)
1254 {
1255 return radv_GetPhysicalDeviceMemoryProperties(physicalDevice,
1256 &pMemoryProperties->memoryProperties);
1257 }
1258
1259 VkResult radv_GetMemoryHostPointerPropertiesEXT(
1260 VkDevice _device,
1261 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
1262 const void *pHostPointer,
1263 VkMemoryHostPointerPropertiesEXT *pMemoryHostPointerProperties)
1264 {
1265 RADV_FROM_HANDLE(radv_device, device, _device);
1266
1267 switch (handleType)
1268 {
1269 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT: {
1270 const struct radv_physical_device *physical_device = device->physical_device;
1271 uint32_t memoryTypeBits = 0;
1272 for (int i = 0; i < physical_device->memory_properties.memoryTypeCount; i++) {
1273 if (physical_device->mem_type_indices[i] == RADV_MEM_TYPE_GTT_CACHED) {
1274 memoryTypeBits = (1 << i);
1275 break;
1276 }
1277 }
1278 pMemoryHostPointerProperties->memoryTypeBits = memoryTypeBits;
1279 return VK_SUCCESS;
1280 }
1281 default:
1282 return VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
1283 }
1284 }
1285
1286 static enum radeon_ctx_priority
1287 radv_get_queue_global_priority(const VkDeviceQueueGlobalPriorityCreateInfoEXT *pObj)
1288 {
1289 /* Default to MEDIUM when a specific global priority isn't requested */
1290 if (!pObj)
1291 return RADEON_CTX_PRIORITY_MEDIUM;
1292
1293 switch(pObj->globalPriority) {
1294 case VK_QUEUE_GLOBAL_PRIORITY_REALTIME_EXT:
1295 return RADEON_CTX_PRIORITY_REALTIME;
1296 case VK_QUEUE_GLOBAL_PRIORITY_HIGH_EXT:
1297 return RADEON_CTX_PRIORITY_HIGH;
1298 case VK_QUEUE_GLOBAL_PRIORITY_MEDIUM_EXT:
1299 return RADEON_CTX_PRIORITY_MEDIUM;
1300 case VK_QUEUE_GLOBAL_PRIORITY_LOW_EXT:
1301 return RADEON_CTX_PRIORITY_LOW;
1302 default:
1303 unreachable("Illegal global priority value");
1304 return RADEON_CTX_PRIORITY_INVALID;
1305 }
1306 }
1307
1308 static int
1309 radv_queue_init(struct radv_device *device, struct radv_queue *queue,
1310 uint32_t queue_family_index, int idx,
1311 VkDeviceQueueCreateFlags flags,
1312 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority)
1313 {
1314 queue->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1315 queue->device = device;
1316 queue->queue_family_index = queue_family_index;
1317 queue->queue_idx = idx;
1318 queue->priority = radv_get_queue_global_priority(global_priority);
1319 queue->flags = flags;
1320
1321 queue->hw_ctx = device->ws->ctx_create(device->ws, queue->priority);
1322 if (!queue->hw_ctx)
1323 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1324
1325 return VK_SUCCESS;
1326 }
1327
1328 static void
1329 radv_queue_finish(struct radv_queue *queue)
1330 {
1331 if (queue->hw_ctx)
1332 queue->device->ws->ctx_destroy(queue->hw_ctx);
1333
1334 if (queue->initial_full_flush_preamble_cs)
1335 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
1336 if (queue->initial_preamble_cs)
1337 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
1338 if (queue->continue_preamble_cs)
1339 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
1340 if (queue->descriptor_bo)
1341 queue->device->ws->buffer_destroy(queue->descriptor_bo);
1342 if (queue->scratch_bo)
1343 queue->device->ws->buffer_destroy(queue->scratch_bo);
1344 if (queue->esgs_ring_bo)
1345 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
1346 if (queue->gsvs_ring_bo)
1347 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
1348 if (queue->tess_rings_bo)
1349 queue->device->ws->buffer_destroy(queue->tess_rings_bo);
1350 if (queue->compute_scratch_bo)
1351 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
1352 }
1353
1354 static void
1355 radv_bo_list_init(struct radv_bo_list *bo_list)
1356 {
1357 pthread_mutex_init(&bo_list->mutex, NULL);
1358 bo_list->list.count = bo_list->capacity = 0;
1359 bo_list->list.bos = NULL;
1360 }
1361
1362 static void
1363 radv_bo_list_finish(struct radv_bo_list *bo_list)
1364 {
1365 free(bo_list->list.bos);
1366 pthread_mutex_destroy(&bo_list->mutex);
1367 }
1368
1369 static VkResult radv_bo_list_add(struct radv_device *device,
1370 struct radeon_winsys_bo *bo)
1371 {
1372 struct radv_bo_list *bo_list = &device->bo_list;
1373
1374 if (unlikely(!device->use_global_bo_list))
1375 return VK_SUCCESS;
1376
1377 pthread_mutex_lock(&bo_list->mutex);
1378 if (bo_list->list.count == bo_list->capacity) {
1379 unsigned capacity = MAX2(4, bo_list->capacity * 2);
1380 void *data = realloc(bo_list->list.bos, capacity * sizeof(struct radeon_winsys_bo*));
1381
1382 if (!data) {
1383 pthread_mutex_unlock(&bo_list->mutex);
1384 return VK_ERROR_OUT_OF_HOST_MEMORY;
1385 }
1386
1387 bo_list->list.bos = (struct radeon_winsys_bo**)data;
1388 bo_list->capacity = capacity;
1389 }
1390
1391 bo_list->list.bos[bo_list->list.count++] = bo;
1392 pthread_mutex_unlock(&bo_list->mutex);
1393 return VK_SUCCESS;
1394 }
1395
1396 static void radv_bo_list_remove(struct radv_device *device,
1397 struct radeon_winsys_bo *bo)
1398 {
1399 struct radv_bo_list *bo_list = &device->bo_list;
1400
1401 if (unlikely(!device->use_global_bo_list))
1402 return;
1403
1404 pthread_mutex_lock(&bo_list->mutex);
1405 for(unsigned i = 0; i < bo_list->list.count; ++i) {
1406 if (bo_list->list.bos[i] == bo) {
1407 bo_list->list.bos[i] = bo_list->list.bos[bo_list->list.count - 1];
1408 --bo_list->list.count;
1409 break;
1410 }
1411 }
1412 pthread_mutex_unlock(&bo_list->mutex);
1413 }
1414
1415 static void
1416 radv_device_init_gs_info(struct radv_device *device)
1417 {
1418 device->gs_table_depth = ac_get_gs_table_depth(device->physical_device->rad_info.chip_class,
1419 device->physical_device->rad_info.family);
1420 }
1421
1422 static int radv_get_device_extension_index(const char *name)
1423 {
1424 for (unsigned i = 0; i < RADV_DEVICE_EXTENSION_COUNT; ++i) {
1425 if (strcmp(name, radv_device_extensions[i].extensionName) == 0)
1426 return i;
1427 }
1428 return -1;
1429 }
1430
1431 VkResult radv_CreateDevice(
1432 VkPhysicalDevice physicalDevice,
1433 const VkDeviceCreateInfo* pCreateInfo,
1434 const VkAllocationCallbacks* pAllocator,
1435 VkDevice* pDevice)
1436 {
1437 RADV_FROM_HANDLE(radv_physical_device, physical_device, physicalDevice);
1438 VkResult result;
1439 struct radv_device *device;
1440
1441 bool keep_shader_info = false;
1442
1443 /* Check enabled features */
1444 if (pCreateInfo->pEnabledFeatures) {
1445 VkPhysicalDeviceFeatures supported_features;
1446 radv_GetPhysicalDeviceFeatures(physicalDevice, &supported_features);
1447 VkBool32 *supported_feature = (VkBool32 *)&supported_features;
1448 VkBool32 *enabled_feature = (VkBool32 *)pCreateInfo->pEnabledFeatures;
1449 unsigned num_features = sizeof(VkPhysicalDeviceFeatures) / sizeof(VkBool32);
1450 for (uint32_t i = 0; i < num_features; i++) {
1451 if (enabled_feature[i] && !supported_feature[i])
1452 return vk_error(physical_device->instance, VK_ERROR_FEATURE_NOT_PRESENT);
1453 }
1454 }
1455
1456 device = vk_zalloc2(&physical_device->instance->alloc, pAllocator,
1457 sizeof(*device), 8,
1458 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1459 if (!device)
1460 return vk_error(physical_device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1461
1462 device->_loader_data.loaderMagic = ICD_LOADER_MAGIC;
1463 device->instance = physical_device->instance;
1464 device->physical_device = physical_device;
1465
1466 device->ws = physical_device->ws;
1467 if (pAllocator)
1468 device->alloc = *pAllocator;
1469 else
1470 device->alloc = physical_device->instance->alloc;
1471
1472 for (uint32_t i = 0; i < pCreateInfo->enabledExtensionCount; i++) {
1473 const char *ext_name = pCreateInfo->ppEnabledExtensionNames[i];
1474 int index = radv_get_device_extension_index(ext_name);
1475 if (index < 0 || !physical_device->supported_extensions.extensions[index]) {
1476 vk_free(&device->alloc, device);
1477 return vk_error(physical_device->instance, VK_ERROR_EXTENSION_NOT_PRESENT);
1478 }
1479
1480 device->enabled_extensions.extensions[index] = true;
1481 }
1482
1483 keep_shader_info = device->enabled_extensions.AMD_shader_info;
1484
1485 /* With update after bind we can't attach bo's to the command buffer
1486 * from the descriptor set anymore, so we have to use a global BO list.
1487 */
1488 device->use_global_bo_list =
1489 device->enabled_extensions.EXT_descriptor_indexing;
1490
1491 mtx_init(&device->shader_slab_mutex, mtx_plain);
1492 list_inithead(&device->shader_slabs);
1493
1494 radv_bo_list_init(&device->bo_list);
1495
1496 for (unsigned i = 0; i < pCreateInfo->queueCreateInfoCount; i++) {
1497 const VkDeviceQueueCreateInfo *queue_create = &pCreateInfo->pQueueCreateInfos[i];
1498 uint32_t qfi = queue_create->queueFamilyIndex;
1499 const VkDeviceQueueGlobalPriorityCreateInfoEXT *global_priority =
1500 vk_find_struct_const(queue_create->pNext, DEVICE_QUEUE_GLOBAL_PRIORITY_CREATE_INFO_EXT);
1501
1502 assert(!global_priority || device->physical_device->rad_info.has_ctx_priority);
1503
1504 device->queues[qfi] = vk_alloc(&device->alloc,
1505 queue_create->queueCount * sizeof(struct radv_queue), 8, VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
1506 if (!device->queues[qfi]) {
1507 result = VK_ERROR_OUT_OF_HOST_MEMORY;
1508 goto fail;
1509 }
1510
1511 memset(device->queues[qfi], 0, queue_create->queueCount * sizeof(struct radv_queue));
1512
1513 device->queue_count[qfi] = queue_create->queueCount;
1514
1515 for (unsigned q = 0; q < queue_create->queueCount; q++) {
1516 result = radv_queue_init(device, &device->queues[qfi][q],
1517 qfi, q, queue_create->flags,
1518 global_priority);
1519 if (result != VK_SUCCESS)
1520 goto fail;
1521 }
1522 }
1523
1524 device->pbb_allowed = device->physical_device->rad_info.chip_class >= GFX9 &&
1525 ((device->instance->perftest_flags & RADV_PERFTEST_BINNING) ||
1526 device->physical_device->rad_info.family == CHIP_RAVEN);
1527
1528 /* Disabled and not implemented for now. */
1529 device->dfsm_allowed = device->pbb_allowed &&
1530 device->physical_device->rad_info.family == CHIP_RAVEN;
1531
1532 #ifdef ANDROID
1533 device->always_use_syncobj = device->physical_device->rad_info.has_syncobj_wait_for_submit;
1534 #endif
1535
1536 /* The maximum number of scratch waves. Scratch space isn't divided
1537 * evenly between CUs. The number is only a function of the number of CUs.
1538 * We can decrease the constant to decrease the scratch buffer size.
1539 *
1540 * sctx->scratch_waves must be >= the maximum possible size of
1541 * 1 threadgroup, so that the hw doesn't hang from being unable
1542 * to start any.
1543 *
1544 * The recommended value is 4 per CU at most. Higher numbers don't
1545 * bring much benefit, but they still occupy chip resources (think
1546 * async compute). I've seen ~2% performance difference between 4 and 32.
1547 */
1548 uint32_t max_threads_per_block = 2048;
1549 device->scratch_waves = MAX2(32 * physical_device->rad_info.num_good_compute_units,
1550 max_threads_per_block / 64);
1551
1552 device->dispatch_initiator = S_00B800_COMPUTE_SHADER_EN(1);
1553
1554 if (device->physical_device->rad_info.chip_class >= CIK) {
1555 /* If the KMD allows it (there is a KMD hw register for it),
1556 * allow launching waves out-of-order.
1557 */
1558 device->dispatch_initiator |= S_00B800_ORDER_MODE(1);
1559 }
1560
1561 radv_device_init_gs_info(device);
1562
1563 device->tess_offchip_block_dw_size =
1564 device->physical_device->rad_info.family == CHIP_HAWAII ? 4096 : 8192;
1565 device->has_distributed_tess =
1566 device->physical_device->rad_info.chip_class >= VI &&
1567 device->physical_device->rad_info.max_se >= 2;
1568
1569 if (getenv("RADV_TRACE_FILE")) {
1570 const char *filename = getenv("RADV_TRACE_FILE");
1571
1572 keep_shader_info = true;
1573
1574 if (!radv_init_trace(device))
1575 goto fail;
1576
1577 fprintf(stderr, "*****************************************************************************\n");
1578 fprintf(stderr, "* WARNING: RADV_TRACE_FILE is costly and should only be used for debugging! *\n");
1579 fprintf(stderr, "*****************************************************************************\n");
1580
1581 fprintf(stderr, "Trace file will be dumped to %s\n", filename);
1582 radv_dump_enabled_options(device, stderr);
1583 }
1584
1585 device->keep_shader_info = keep_shader_info;
1586
1587 result = radv_device_init_meta(device);
1588 if (result != VK_SUCCESS)
1589 goto fail;
1590
1591 radv_device_init_msaa(device);
1592
1593 for (int family = 0; family < RADV_MAX_QUEUE_FAMILIES; ++family) {
1594 device->empty_cs[family] = device->ws->cs_create(device->ws, family);
1595 switch (family) {
1596 case RADV_QUEUE_GENERAL:
1597 radeon_emit(device->empty_cs[family], PKT3(PKT3_CONTEXT_CONTROL, 1, 0));
1598 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_LOAD_ENABLE(1));
1599 radeon_emit(device->empty_cs[family], CONTEXT_CONTROL_SHADOW_ENABLE(1));
1600 break;
1601 case RADV_QUEUE_COMPUTE:
1602 radeon_emit(device->empty_cs[family], PKT3(PKT3_NOP, 0, 0));
1603 radeon_emit(device->empty_cs[family], 0);
1604 break;
1605 }
1606 device->ws->cs_finalize(device->empty_cs[family]);
1607 }
1608
1609 if (device->physical_device->rad_info.chip_class >= CIK)
1610 cik_create_gfx_config(device);
1611
1612 VkPipelineCacheCreateInfo ci;
1613 ci.sType = VK_STRUCTURE_TYPE_PIPELINE_CACHE_CREATE_INFO;
1614 ci.pNext = NULL;
1615 ci.flags = 0;
1616 ci.pInitialData = NULL;
1617 ci.initialDataSize = 0;
1618 VkPipelineCache pc;
1619 result = radv_CreatePipelineCache(radv_device_to_handle(device),
1620 &ci, NULL, &pc);
1621 if (result != VK_SUCCESS)
1622 goto fail_meta;
1623
1624 device->mem_cache = radv_pipeline_cache_from_handle(pc);
1625
1626 *pDevice = radv_device_to_handle(device);
1627 return VK_SUCCESS;
1628
1629 fail_meta:
1630 radv_device_finish_meta(device);
1631 fail:
1632 radv_bo_list_finish(&device->bo_list);
1633
1634 if (device->trace_bo)
1635 device->ws->buffer_destroy(device->trace_bo);
1636
1637 if (device->gfx_init)
1638 device->ws->buffer_destroy(device->gfx_init);
1639
1640 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1641 for (unsigned q = 0; q < device->queue_count[i]; q++)
1642 radv_queue_finish(&device->queues[i][q]);
1643 if (device->queue_count[i])
1644 vk_free(&device->alloc, device->queues[i]);
1645 }
1646
1647 vk_free(&device->alloc, device);
1648 return result;
1649 }
1650
1651 void radv_DestroyDevice(
1652 VkDevice _device,
1653 const VkAllocationCallbacks* pAllocator)
1654 {
1655 RADV_FROM_HANDLE(radv_device, device, _device);
1656
1657 if (!device)
1658 return;
1659
1660 if (device->trace_bo)
1661 device->ws->buffer_destroy(device->trace_bo);
1662
1663 if (device->gfx_init)
1664 device->ws->buffer_destroy(device->gfx_init);
1665
1666 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
1667 for (unsigned q = 0; q < device->queue_count[i]; q++)
1668 radv_queue_finish(&device->queues[i][q]);
1669 if (device->queue_count[i])
1670 vk_free(&device->alloc, device->queues[i]);
1671 if (device->empty_cs[i])
1672 device->ws->cs_destroy(device->empty_cs[i]);
1673 }
1674 radv_device_finish_meta(device);
1675
1676 VkPipelineCache pc = radv_pipeline_cache_to_handle(device->mem_cache);
1677 radv_DestroyPipelineCache(radv_device_to_handle(device), pc, NULL);
1678
1679 radv_destroy_shader_slabs(device);
1680
1681 radv_bo_list_finish(&device->bo_list);
1682 vk_free(&device->alloc, device);
1683 }
1684
1685 VkResult radv_EnumerateInstanceLayerProperties(
1686 uint32_t* pPropertyCount,
1687 VkLayerProperties* pProperties)
1688 {
1689 if (pProperties == NULL) {
1690 *pPropertyCount = 0;
1691 return VK_SUCCESS;
1692 }
1693
1694 /* None supported at this time */
1695 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1696 }
1697
1698 VkResult radv_EnumerateDeviceLayerProperties(
1699 VkPhysicalDevice physicalDevice,
1700 uint32_t* pPropertyCount,
1701 VkLayerProperties* pProperties)
1702 {
1703 if (pProperties == NULL) {
1704 *pPropertyCount = 0;
1705 return VK_SUCCESS;
1706 }
1707
1708 /* None supported at this time */
1709 return vk_error(NULL, VK_ERROR_LAYER_NOT_PRESENT);
1710 }
1711
1712 void radv_GetDeviceQueue2(
1713 VkDevice _device,
1714 const VkDeviceQueueInfo2* pQueueInfo,
1715 VkQueue* pQueue)
1716 {
1717 RADV_FROM_HANDLE(radv_device, device, _device);
1718 struct radv_queue *queue;
1719
1720 queue = &device->queues[pQueueInfo->queueFamilyIndex][pQueueInfo->queueIndex];
1721 if (pQueueInfo->flags != queue->flags) {
1722 /* From the Vulkan 1.1.70 spec:
1723 *
1724 * "The queue returned by vkGetDeviceQueue2 must have the same
1725 * flags value from this structure as that used at device
1726 * creation time in a VkDeviceQueueCreateInfo instance. If no
1727 * matching flags were specified at device creation time then
1728 * pQueue will return VK_NULL_HANDLE."
1729 */
1730 *pQueue = VK_NULL_HANDLE;
1731 return;
1732 }
1733
1734 *pQueue = radv_queue_to_handle(queue);
1735 }
1736
1737 void radv_GetDeviceQueue(
1738 VkDevice _device,
1739 uint32_t queueFamilyIndex,
1740 uint32_t queueIndex,
1741 VkQueue* pQueue)
1742 {
1743 const VkDeviceQueueInfo2 info = (VkDeviceQueueInfo2) {
1744 .sType = VK_STRUCTURE_TYPE_DEVICE_QUEUE_INFO_2,
1745 .queueFamilyIndex = queueFamilyIndex,
1746 .queueIndex = queueIndex
1747 };
1748
1749 radv_GetDeviceQueue2(_device, &info, pQueue);
1750 }
1751
1752 static void
1753 fill_geom_tess_rings(struct radv_queue *queue,
1754 uint32_t *map,
1755 bool add_sample_positions,
1756 uint32_t esgs_ring_size,
1757 struct radeon_winsys_bo *esgs_ring_bo,
1758 uint32_t gsvs_ring_size,
1759 struct radeon_winsys_bo *gsvs_ring_bo,
1760 uint32_t tess_factor_ring_size,
1761 uint32_t tess_offchip_ring_offset,
1762 uint32_t tess_offchip_ring_size,
1763 struct radeon_winsys_bo *tess_rings_bo)
1764 {
1765 uint64_t esgs_va = 0, gsvs_va = 0;
1766 uint64_t tess_va = 0, tess_offchip_va = 0;
1767 uint32_t *desc = &map[4];
1768
1769 if (esgs_ring_bo)
1770 esgs_va = radv_buffer_get_va(esgs_ring_bo);
1771 if (gsvs_ring_bo)
1772 gsvs_va = radv_buffer_get_va(gsvs_ring_bo);
1773 if (tess_rings_bo) {
1774 tess_va = radv_buffer_get_va(tess_rings_bo);
1775 tess_offchip_va = tess_va + tess_offchip_ring_offset;
1776 }
1777
1778 /* stride 0, num records - size, add tid, swizzle, elsize4,
1779 index stride 64 */
1780 desc[0] = esgs_va;
1781 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32) |
1782 S_008F04_STRIDE(0) |
1783 S_008F04_SWIZZLE_ENABLE(true);
1784 desc[2] = esgs_ring_size;
1785 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1786 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1787 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1788 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1789 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1790 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1791 S_008F0C_ELEMENT_SIZE(1) |
1792 S_008F0C_INDEX_STRIDE(3) |
1793 S_008F0C_ADD_TID_ENABLE(true);
1794
1795 desc += 4;
1796 /* GS entry for ES->GS ring */
1797 /* stride 0, num records - size, elsize0,
1798 index stride 0 */
1799 desc[0] = esgs_va;
1800 desc[1] = S_008F04_BASE_ADDRESS_HI(esgs_va >> 32)|
1801 S_008F04_STRIDE(0) |
1802 S_008F04_SWIZZLE_ENABLE(false);
1803 desc[2] = esgs_ring_size;
1804 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1805 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1806 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1807 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1808 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1809 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1810 S_008F0C_ELEMENT_SIZE(0) |
1811 S_008F0C_INDEX_STRIDE(0) |
1812 S_008F0C_ADD_TID_ENABLE(false);
1813
1814 desc += 4;
1815 /* VS entry for GS->VS ring */
1816 /* stride 0, num records - size, elsize0,
1817 index stride 0 */
1818 desc[0] = gsvs_va;
1819 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1820 S_008F04_STRIDE(0) |
1821 S_008F04_SWIZZLE_ENABLE(false);
1822 desc[2] = gsvs_ring_size;
1823 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1824 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1825 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1826 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1827 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1828 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1829 S_008F0C_ELEMENT_SIZE(0) |
1830 S_008F0C_INDEX_STRIDE(0) |
1831 S_008F0C_ADD_TID_ENABLE(false);
1832 desc += 4;
1833
1834 /* stride gsvs_itemsize, num records 64
1835 elsize 4, index stride 16 */
1836 /* shader will patch stride and desc[2] */
1837 desc[0] = gsvs_va;
1838 desc[1] = S_008F04_BASE_ADDRESS_HI(gsvs_va >> 32)|
1839 S_008F04_STRIDE(0) |
1840 S_008F04_SWIZZLE_ENABLE(true);
1841 desc[2] = 0;
1842 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1843 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1844 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1845 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1846 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1847 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1848 S_008F0C_ELEMENT_SIZE(1) |
1849 S_008F0C_INDEX_STRIDE(1) |
1850 S_008F0C_ADD_TID_ENABLE(true);
1851 desc += 4;
1852
1853 desc[0] = tess_va;
1854 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_va >> 32) |
1855 S_008F04_STRIDE(0) |
1856 S_008F04_SWIZZLE_ENABLE(false);
1857 desc[2] = tess_factor_ring_size;
1858 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1859 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1860 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1861 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1862 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1863 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1864 S_008F0C_ELEMENT_SIZE(0) |
1865 S_008F0C_INDEX_STRIDE(0) |
1866 S_008F0C_ADD_TID_ENABLE(false);
1867 desc += 4;
1868
1869 desc[0] = tess_offchip_va;
1870 desc[1] = S_008F04_BASE_ADDRESS_HI(tess_offchip_va >> 32) |
1871 S_008F04_STRIDE(0) |
1872 S_008F04_SWIZZLE_ENABLE(false);
1873 desc[2] = tess_offchip_ring_size;
1874 desc[3] = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1875 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1876 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1877 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W) |
1878 S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1879 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32) |
1880 S_008F0C_ELEMENT_SIZE(0) |
1881 S_008F0C_INDEX_STRIDE(0) |
1882 S_008F0C_ADD_TID_ENABLE(false);
1883 desc += 4;
1884
1885 /* add sample positions after all rings */
1886 memcpy(desc, queue->device->sample_locations_1x, 8);
1887 desc += 2;
1888 memcpy(desc, queue->device->sample_locations_2x, 16);
1889 desc += 4;
1890 memcpy(desc, queue->device->sample_locations_4x, 32);
1891 desc += 8;
1892 memcpy(desc, queue->device->sample_locations_8x, 64);
1893 desc += 16;
1894 memcpy(desc, queue->device->sample_locations_16x, 128);
1895 }
1896
1897 static unsigned
1898 radv_get_hs_offchip_param(struct radv_device *device, uint32_t *max_offchip_buffers_p)
1899 {
1900 bool double_offchip_buffers = device->physical_device->rad_info.chip_class >= CIK &&
1901 device->physical_device->rad_info.family != CHIP_CARRIZO &&
1902 device->physical_device->rad_info.family != CHIP_STONEY;
1903 unsigned max_offchip_buffers_per_se = double_offchip_buffers ? 128 : 64;
1904 unsigned max_offchip_buffers;
1905 unsigned offchip_granularity;
1906 unsigned hs_offchip_param;
1907
1908 /*
1909 * Per RadeonSI:
1910 * This must be one less than the maximum number due to a hw limitation.
1911 * Various hardware bugs in SI, CIK, and GFX9 need this.
1912 *
1913 * Per AMDVLK:
1914 * Vega10 should limit max_offchip_buffers to 508 (4 * 127).
1915 * Gfx7 should limit max_offchip_buffers to 508
1916 * Gfx6 should limit max_offchip_buffers to 126 (2 * 63)
1917 *
1918 * Follow AMDVLK here.
1919 */
1920 if (device->physical_device->rad_info.family == CHIP_VEGA10 ||
1921 device->physical_device->rad_info.chip_class == CIK ||
1922 device->physical_device->rad_info.chip_class == SI)
1923 --max_offchip_buffers_per_se;
1924
1925 max_offchip_buffers = max_offchip_buffers_per_se *
1926 device->physical_device->rad_info.max_se;
1927
1928 switch (device->tess_offchip_block_dw_size) {
1929 default:
1930 assert(0);
1931 /* fall through */
1932 case 8192:
1933 offchip_granularity = V_03093C_X_8K_DWORDS;
1934 break;
1935 case 4096:
1936 offchip_granularity = V_03093C_X_4K_DWORDS;
1937 break;
1938 }
1939
1940 switch (device->physical_device->rad_info.chip_class) {
1941 case SI:
1942 max_offchip_buffers = MIN2(max_offchip_buffers, 126);
1943 break;
1944 case CIK:
1945 case VI:
1946 case GFX9:
1947 default:
1948 max_offchip_buffers = MIN2(max_offchip_buffers, 508);
1949 break;
1950 }
1951
1952 *max_offchip_buffers_p = max_offchip_buffers;
1953 if (device->physical_device->rad_info.chip_class >= CIK) {
1954 if (device->physical_device->rad_info.chip_class >= VI)
1955 --max_offchip_buffers;
1956 hs_offchip_param =
1957 S_03093C_OFFCHIP_BUFFERING(max_offchip_buffers) |
1958 S_03093C_OFFCHIP_GRANULARITY(offchip_granularity);
1959 } else {
1960 hs_offchip_param =
1961 S_0089B0_OFFCHIP_BUFFERING(max_offchip_buffers);
1962 }
1963 return hs_offchip_param;
1964 }
1965
1966 static void
1967 radv_emit_gs_ring_sizes(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1968 struct radeon_winsys_bo *esgs_ring_bo,
1969 uint32_t esgs_ring_size,
1970 struct radeon_winsys_bo *gsvs_ring_bo,
1971 uint32_t gsvs_ring_size)
1972 {
1973 if (!esgs_ring_bo && !gsvs_ring_bo)
1974 return;
1975
1976 if (esgs_ring_bo)
1977 radv_cs_add_buffer(queue->device->ws, cs, esgs_ring_bo);
1978
1979 if (gsvs_ring_bo)
1980 radv_cs_add_buffer(queue->device->ws, cs, gsvs_ring_bo);
1981
1982 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
1983 radeon_set_uconfig_reg_seq(cs, R_030900_VGT_ESGS_RING_SIZE, 2);
1984 radeon_emit(cs, esgs_ring_size >> 8);
1985 radeon_emit(cs, gsvs_ring_size >> 8);
1986 } else {
1987 radeon_set_config_reg_seq(cs, R_0088C8_VGT_ESGS_RING_SIZE, 2);
1988 radeon_emit(cs, esgs_ring_size >> 8);
1989 radeon_emit(cs, gsvs_ring_size >> 8);
1990 }
1991 }
1992
1993 static void
1994 radv_emit_tess_factor_ring(struct radv_queue *queue, struct radeon_cmdbuf *cs,
1995 unsigned hs_offchip_param, unsigned tf_ring_size,
1996 struct radeon_winsys_bo *tess_rings_bo)
1997 {
1998 uint64_t tf_va;
1999
2000 if (!tess_rings_bo)
2001 return;
2002
2003 tf_va = radv_buffer_get_va(tess_rings_bo);
2004
2005 radv_cs_add_buffer(queue->device->ws, cs, tess_rings_bo);
2006
2007 if (queue->device->physical_device->rad_info.chip_class >= CIK) {
2008 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
2009 S_030938_SIZE(tf_ring_size / 4));
2010 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE,
2011 tf_va >> 8);
2012 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2013 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
2014 S_030944_BASE_HI(tf_va >> 40));
2015 }
2016 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
2017 hs_offchip_param);
2018 } else {
2019 radeon_set_config_reg(cs, R_008988_VGT_TF_RING_SIZE,
2020 S_008988_SIZE(tf_ring_size / 4));
2021 radeon_set_config_reg(cs, R_0089B8_VGT_TF_MEMORY_BASE,
2022 tf_va >> 8);
2023 radeon_set_config_reg(cs, R_0089B0_VGT_HS_OFFCHIP_PARAM,
2024 hs_offchip_param);
2025 }
2026 }
2027
2028 static void
2029 radv_emit_compute_scratch(struct radv_queue *queue, struct radeon_cmdbuf *cs,
2030 struct radeon_winsys_bo *compute_scratch_bo)
2031 {
2032 uint64_t scratch_va;
2033
2034 if (!compute_scratch_bo)
2035 return;
2036
2037 scratch_va = radv_buffer_get_va(compute_scratch_bo);
2038
2039 radv_cs_add_buffer(queue->device->ws, cs, compute_scratch_bo);
2040
2041 radeon_set_sh_reg_seq(cs, R_00B900_COMPUTE_USER_DATA_0, 2);
2042 radeon_emit(cs, scratch_va);
2043 radeon_emit(cs, S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2044 S_008F04_SWIZZLE_ENABLE(1));
2045 }
2046
2047 static void
2048 radv_emit_global_shader_pointers(struct radv_queue *queue,
2049 struct radeon_cmdbuf *cs,
2050 struct radeon_winsys_bo *descriptor_bo)
2051 {
2052 uint64_t va;
2053
2054 if (!descriptor_bo)
2055 return;
2056
2057 va = radv_buffer_get_va(descriptor_bo);
2058
2059 radv_cs_add_buffer(queue->device->ws, cs, descriptor_bo);
2060
2061 if (queue->device->physical_device->rad_info.chip_class >= GFX9) {
2062 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2063 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2064 R_00B208_SPI_SHADER_USER_DATA_ADDR_LO_GS,
2065 R_00B408_SPI_SHADER_USER_DATA_ADDR_LO_HS};
2066
2067 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2068 radv_emit_shader_pointer(queue->device, cs, regs[i],
2069 va, true);
2070 }
2071 } else {
2072 uint32_t regs[] = {R_00B030_SPI_SHADER_USER_DATA_PS_0,
2073 R_00B130_SPI_SHADER_USER_DATA_VS_0,
2074 R_00B230_SPI_SHADER_USER_DATA_GS_0,
2075 R_00B330_SPI_SHADER_USER_DATA_ES_0,
2076 R_00B430_SPI_SHADER_USER_DATA_HS_0,
2077 R_00B530_SPI_SHADER_USER_DATA_LS_0};
2078
2079 for (int i = 0; i < ARRAY_SIZE(regs); ++i) {
2080 radv_emit_shader_pointer(queue->device, cs, regs[i],
2081 va, true);
2082 }
2083 }
2084 }
2085
2086 static VkResult
2087 radv_get_preamble_cs(struct radv_queue *queue,
2088 uint32_t scratch_size,
2089 uint32_t compute_scratch_size,
2090 uint32_t esgs_ring_size,
2091 uint32_t gsvs_ring_size,
2092 bool needs_tess_rings,
2093 bool needs_sample_positions,
2094 struct radeon_cmdbuf **initial_full_flush_preamble_cs,
2095 struct radeon_cmdbuf **initial_preamble_cs,
2096 struct radeon_cmdbuf **continue_preamble_cs)
2097 {
2098 struct radeon_winsys_bo *scratch_bo = NULL;
2099 struct radeon_winsys_bo *descriptor_bo = NULL;
2100 struct radeon_winsys_bo *compute_scratch_bo = NULL;
2101 struct radeon_winsys_bo *esgs_ring_bo = NULL;
2102 struct radeon_winsys_bo *gsvs_ring_bo = NULL;
2103 struct radeon_winsys_bo *tess_rings_bo = NULL;
2104 struct radeon_cmdbuf *dest_cs[3] = {0};
2105 bool add_tess_rings = false, add_sample_positions = false;
2106 unsigned tess_factor_ring_size = 0, tess_offchip_ring_size = 0;
2107 unsigned max_offchip_buffers;
2108 unsigned hs_offchip_param = 0;
2109 unsigned tess_offchip_ring_offset;
2110 uint32_t ring_bo_flags = RADEON_FLAG_NO_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING;
2111 if (!queue->has_tess_rings) {
2112 if (needs_tess_rings)
2113 add_tess_rings = true;
2114 }
2115 if (!queue->has_sample_positions) {
2116 if (needs_sample_positions)
2117 add_sample_positions = true;
2118 }
2119 tess_factor_ring_size = 32768 * queue->device->physical_device->rad_info.max_se;
2120 hs_offchip_param = radv_get_hs_offchip_param(queue->device,
2121 &max_offchip_buffers);
2122 tess_offchip_ring_offset = align(tess_factor_ring_size, 64 * 1024);
2123 tess_offchip_ring_size = max_offchip_buffers *
2124 queue->device->tess_offchip_block_dw_size * 4;
2125
2126 if (scratch_size <= queue->scratch_size &&
2127 compute_scratch_size <= queue->compute_scratch_size &&
2128 esgs_ring_size <= queue->esgs_ring_size &&
2129 gsvs_ring_size <= queue->gsvs_ring_size &&
2130 !add_tess_rings && !add_sample_positions &&
2131 queue->initial_preamble_cs) {
2132 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2133 *initial_preamble_cs = queue->initial_preamble_cs;
2134 *continue_preamble_cs = queue->continue_preamble_cs;
2135 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2136 *continue_preamble_cs = NULL;
2137 return VK_SUCCESS;
2138 }
2139
2140 if (scratch_size > queue->scratch_size) {
2141 scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2142 scratch_size,
2143 4096,
2144 RADEON_DOMAIN_VRAM,
2145 ring_bo_flags);
2146 if (!scratch_bo)
2147 goto fail;
2148 } else
2149 scratch_bo = queue->scratch_bo;
2150
2151 if (compute_scratch_size > queue->compute_scratch_size) {
2152 compute_scratch_bo = queue->device->ws->buffer_create(queue->device->ws,
2153 compute_scratch_size,
2154 4096,
2155 RADEON_DOMAIN_VRAM,
2156 ring_bo_flags);
2157 if (!compute_scratch_bo)
2158 goto fail;
2159
2160 } else
2161 compute_scratch_bo = queue->compute_scratch_bo;
2162
2163 if (esgs_ring_size > queue->esgs_ring_size) {
2164 esgs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2165 esgs_ring_size,
2166 4096,
2167 RADEON_DOMAIN_VRAM,
2168 ring_bo_flags);
2169 if (!esgs_ring_bo)
2170 goto fail;
2171 } else {
2172 esgs_ring_bo = queue->esgs_ring_bo;
2173 esgs_ring_size = queue->esgs_ring_size;
2174 }
2175
2176 if (gsvs_ring_size > queue->gsvs_ring_size) {
2177 gsvs_ring_bo = queue->device->ws->buffer_create(queue->device->ws,
2178 gsvs_ring_size,
2179 4096,
2180 RADEON_DOMAIN_VRAM,
2181 ring_bo_flags);
2182 if (!gsvs_ring_bo)
2183 goto fail;
2184 } else {
2185 gsvs_ring_bo = queue->gsvs_ring_bo;
2186 gsvs_ring_size = queue->gsvs_ring_size;
2187 }
2188
2189 if (add_tess_rings) {
2190 tess_rings_bo = queue->device->ws->buffer_create(queue->device->ws,
2191 tess_offchip_ring_offset + tess_offchip_ring_size,
2192 256,
2193 RADEON_DOMAIN_VRAM,
2194 ring_bo_flags);
2195 if (!tess_rings_bo)
2196 goto fail;
2197 } else {
2198 tess_rings_bo = queue->tess_rings_bo;
2199 }
2200
2201 if (scratch_bo != queue->scratch_bo ||
2202 esgs_ring_bo != queue->esgs_ring_bo ||
2203 gsvs_ring_bo != queue->gsvs_ring_bo ||
2204 tess_rings_bo != queue->tess_rings_bo ||
2205 add_sample_positions) {
2206 uint32_t size = 0;
2207 if (gsvs_ring_bo || esgs_ring_bo ||
2208 tess_rings_bo || add_sample_positions) {
2209 size = 112; /* 2 dword + 2 padding + 4 dword * 6 */
2210 if (add_sample_positions)
2211 size += 256; /* 32+16+8+4+2+1 samples * 4 * 2 = 248 bytes. */
2212 }
2213 else if (scratch_bo)
2214 size = 8; /* 2 dword */
2215
2216 descriptor_bo = queue->device->ws->buffer_create(queue->device->ws,
2217 size,
2218 4096,
2219 RADEON_DOMAIN_VRAM,
2220 RADEON_FLAG_CPU_ACCESS |
2221 RADEON_FLAG_NO_INTERPROCESS_SHARING |
2222 RADEON_FLAG_READ_ONLY);
2223 if (!descriptor_bo)
2224 goto fail;
2225 } else
2226 descriptor_bo = queue->descriptor_bo;
2227
2228 for(int i = 0; i < 3; ++i) {
2229 struct radeon_cmdbuf *cs = NULL;
2230 cs = queue->device->ws->cs_create(queue->device->ws,
2231 queue->queue_family_index ? RING_COMPUTE : RING_GFX);
2232 if (!cs)
2233 goto fail;
2234
2235 dest_cs[i] = cs;
2236
2237 if (scratch_bo)
2238 radv_cs_add_buffer(queue->device->ws, cs, scratch_bo);
2239
2240 if (descriptor_bo != queue->descriptor_bo) {
2241 uint32_t *map = (uint32_t*)queue->device->ws->buffer_map(descriptor_bo);
2242
2243 if (scratch_bo) {
2244 uint64_t scratch_va = radv_buffer_get_va(scratch_bo);
2245 uint32_t rsrc1 = S_008F04_BASE_ADDRESS_HI(scratch_va >> 32) |
2246 S_008F04_SWIZZLE_ENABLE(1);
2247 map[0] = scratch_va;
2248 map[1] = rsrc1;
2249 }
2250
2251 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo ||
2252 add_sample_positions)
2253 fill_geom_tess_rings(queue, map, add_sample_positions,
2254 esgs_ring_size, esgs_ring_bo,
2255 gsvs_ring_size, gsvs_ring_bo,
2256 tess_factor_ring_size,
2257 tess_offchip_ring_offset,
2258 tess_offchip_ring_size,
2259 tess_rings_bo);
2260
2261 queue->device->ws->buffer_unmap(descriptor_bo);
2262 }
2263
2264 if (esgs_ring_bo || gsvs_ring_bo || tess_rings_bo) {
2265 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2266 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
2267 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
2268 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
2269 }
2270
2271 radv_emit_gs_ring_sizes(queue, cs, esgs_ring_bo, esgs_ring_size,
2272 gsvs_ring_bo, gsvs_ring_size);
2273 radv_emit_tess_factor_ring(queue, cs, hs_offchip_param,
2274 tess_factor_ring_size, tess_rings_bo);
2275 radv_emit_global_shader_pointers(queue, cs, descriptor_bo);
2276 radv_emit_compute_scratch(queue, cs, compute_scratch_bo);
2277
2278 if (i == 0) {
2279 si_cs_emit_cache_flush(cs,
2280 queue->device->physical_device->rad_info.chip_class,
2281 NULL, 0,
2282 queue->queue_family_index == RING_COMPUTE &&
2283 queue->device->physical_device->rad_info.chip_class >= CIK,
2284 (queue->queue_family_index == RADV_QUEUE_COMPUTE ? RADV_CMD_FLAG_CS_PARTIAL_FLUSH : (RADV_CMD_FLAG_CS_PARTIAL_FLUSH | RADV_CMD_FLAG_PS_PARTIAL_FLUSH)) |
2285 RADV_CMD_FLAG_INV_ICACHE |
2286 RADV_CMD_FLAG_INV_SMEM_L1 |
2287 RADV_CMD_FLAG_INV_VMEM_L1 |
2288 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2289 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2290 } else if (i == 1) {
2291 si_cs_emit_cache_flush(cs,
2292 queue->device->physical_device->rad_info.chip_class,
2293 NULL, 0,
2294 queue->queue_family_index == RING_COMPUTE &&
2295 queue->device->physical_device->rad_info.chip_class >= CIK,
2296 RADV_CMD_FLAG_INV_ICACHE |
2297 RADV_CMD_FLAG_INV_SMEM_L1 |
2298 RADV_CMD_FLAG_INV_VMEM_L1 |
2299 RADV_CMD_FLAG_INV_GLOBAL_L2 |
2300 RADV_CMD_FLAG_START_PIPELINE_STATS, 0);
2301 }
2302
2303 if (!queue->device->ws->cs_finalize(cs))
2304 goto fail;
2305 }
2306
2307 if (queue->initial_full_flush_preamble_cs)
2308 queue->device->ws->cs_destroy(queue->initial_full_flush_preamble_cs);
2309
2310 if (queue->initial_preamble_cs)
2311 queue->device->ws->cs_destroy(queue->initial_preamble_cs);
2312
2313 if (queue->continue_preamble_cs)
2314 queue->device->ws->cs_destroy(queue->continue_preamble_cs);
2315
2316 queue->initial_full_flush_preamble_cs = dest_cs[0];
2317 queue->initial_preamble_cs = dest_cs[1];
2318 queue->continue_preamble_cs = dest_cs[2];
2319
2320 if (scratch_bo != queue->scratch_bo) {
2321 if (queue->scratch_bo)
2322 queue->device->ws->buffer_destroy(queue->scratch_bo);
2323 queue->scratch_bo = scratch_bo;
2324 queue->scratch_size = scratch_size;
2325 }
2326
2327 if (compute_scratch_bo != queue->compute_scratch_bo) {
2328 if (queue->compute_scratch_bo)
2329 queue->device->ws->buffer_destroy(queue->compute_scratch_bo);
2330 queue->compute_scratch_bo = compute_scratch_bo;
2331 queue->compute_scratch_size = compute_scratch_size;
2332 }
2333
2334 if (esgs_ring_bo != queue->esgs_ring_bo) {
2335 if (queue->esgs_ring_bo)
2336 queue->device->ws->buffer_destroy(queue->esgs_ring_bo);
2337 queue->esgs_ring_bo = esgs_ring_bo;
2338 queue->esgs_ring_size = esgs_ring_size;
2339 }
2340
2341 if (gsvs_ring_bo != queue->gsvs_ring_bo) {
2342 if (queue->gsvs_ring_bo)
2343 queue->device->ws->buffer_destroy(queue->gsvs_ring_bo);
2344 queue->gsvs_ring_bo = gsvs_ring_bo;
2345 queue->gsvs_ring_size = gsvs_ring_size;
2346 }
2347
2348 if (tess_rings_bo != queue->tess_rings_bo) {
2349 queue->tess_rings_bo = tess_rings_bo;
2350 queue->has_tess_rings = true;
2351 }
2352
2353 if (descriptor_bo != queue->descriptor_bo) {
2354 if (queue->descriptor_bo)
2355 queue->device->ws->buffer_destroy(queue->descriptor_bo);
2356
2357 queue->descriptor_bo = descriptor_bo;
2358 }
2359
2360 if (add_sample_positions)
2361 queue->has_sample_positions = true;
2362
2363 *initial_full_flush_preamble_cs = queue->initial_full_flush_preamble_cs;
2364 *initial_preamble_cs = queue->initial_preamble_cs;
2365 *continue_preamble_cs = queue->continue_preamble_cs;
2366 if (!scratch_size && !compute_scratch_size && !esgs_ring_size && !gsvs_ring_size)
2367 *continue_preamble_cs = NULL;
2368 return VK_SUCCESS;
2369 fail:
2370 for (int i = 0; i < ARRAY_SIZE(dest_cs); ++i)
2371 if (dest_cs[i])
2372 queue->device->ws->cs_destroy(dest_cs[i]);
2373 if (descriptor_bo && descriptor_bo != queue->descriptor_bo)
2374 queue->device->ws->buffer_destroy(descriptor_bo);
2375 if (scratch_bo && scratch_bo != queue->scratch_bo)
2376 queue->device->ws->buffer_destroy(scratch_bo);
2377 if (compute_scratch_bo && compute_scratch_bo != queue->compute_scratch_bo)
2378 queue->device->ws->buffer_destroy(compute_scratch_bo);
2379 if (esgs_ring_bo && esgs_ring_bo != queue->esgs_ring_bo)
2380 queue->device->ws->buffer_destroy(esgs_ring_bo);
2381 if (gsvs_ring_bo && gsvs_ring_bo != queue->gsvs_ring_bo)
2382 queue->device->ws->buffer_destroy(gsvs_ring_bo);
2383 if (tess_rings_bo && tess_rings_bo != queue->tess_rings_bo)
2384 queue->device->ws->buffer_destroy(tess_rings_bo);
2385 return vk_error(queue->device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
2386 }
2387
2388 static VkResult radv_alloc_sem_counts(struct radv_instance *instance,
2389 struct radv_winsys_sem_counts *counts,
2390 int num_sems,
2391 const VkSemaphore *sems,
2392 VkFence _fence,
2393 bool reset_temp)
2394 {
2395 int syncobj_idx = 0, sem_idx = 0;
2396
2397 if (num_sems == 0 && _fence == VK_NULL_HANDLE)
2398 return VK_SUCCESS;
2399
2400 for (uint32_t i = 0; i < num_sems; i++) {
2401 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2402
2403 if (sem->temp_syncobj || sem->syncobj)
2404 counts->syncobj_count++;
2405 else
2406 counts->sem_count++;
2407 }
2408
2409 if (_fence != VK_NULL_HANDLE) {
2410 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2411 if (fence->temp_syncobj || fence->syncobj)
2412 counts->syncobj_count++;
2413 }
2414
2415 if (counts->syncobj_count) {
2416 counts->syncobj = (uint32_t *)malloc(sizeof(uint32_t) * counts->syncobj_count);
2417 if (!counts->syncobj)
2418 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2419 }
2420
2421 if (counts->sem_count) {
2422 counts->sem = (struct radeon_winsys_sem **)malloc(sizeof(struct radeon_winsys_sem *) * counts->sem_count);
2423 if (!counts->sem) {
2424 free(counts->syncobj);
2425 return vk_error(instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2426 }
2427 }
2428
2429 for (uint32_t i = 0; i < num_sems; i++) {
2430 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2431
2432 if (sem->temp_syncobj) {
2433 counts->syncobj[syncobj_idx++] = sem->temp_syncobj;
2434 }
2435 else if (sem->syncobj)
2436 counts->syncobj[syncobj_idx++] = sem->syncobj;
2437 else {
2438 assert(sem->sem);
2439 counts->sem[sem_idx++] = sem->sem;
2440 }
2441 }
2442
2443 if (_fence != VK_NULL_HANDLE) {
2444 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2445 if (fence->temp_syncobj)
2446 counts->syncobj[syncobj_idx++] = fence->temp_syncobj;
2447 else if (fence->syncobj)
2448 counts->syncobj[syncobj_idx++] = fence->syncobj;
2449 }
2450
2451 return VK_SUCCESS;
2452 }
2453
2454 static void
2455 radv_free_sem_info(struct radv_winsys_sem_info *sem_info)
2456 {
2457 free(sem_info->wait.syncobj);
2458 free(sem_info->wait.sem);
2459 free(sem_info->signal.syncobj);
2460 free(sem_info->signal.sem);
2461 }
2462
2463
2464 static void radv_free_temp_syncobjs(struct radv_device *device,
2465 int num_sems,
2466 const VkSemaphore *sems)
2467 {
2468 for (uint32_t i = 0; i < num_sems; i++) {
2469 RADV_FROM_HANDLE(radv_semaphore, sem, sems[i]);
2470
2471 if (sem->temp_syncobj) {
2472 device->ws->destroy_syncobj(device->ws, sem->temp_syncobj);
2473 sem->temp_syncobj = 0;
2474 }
2475 }
2476 }
2477
2478 static VkResult
2479 radv_alloc_sem_info(struct radv_instance *instance,
2480 struct radv_winsys_sem_info *sem_info,
2481 int num_wait_sems,
2482 const VkSemaphore *wait_sems,
2483 int num_signal_sems,
2484 const VkSemaphore *signal_sems,
2485 VkFence fence)
2486 {
2487 VkResult ret;
2488 memset(sem_info, 0, sizeof(*sem_info));
2489
2490 ret = radv_alloc_sem_counts(instance, &sem_info->wait, num_wait_sems, wait_sems, VK_NULL_HANDLE, true);
2491 if (ret)
2492 return ret;
2493 ret = radv_alloc_sem_counts(instance, &sem_info->signal, num_signal_sems, signal_sems, fence, false);
2494 if (ret)
2495 radv_free_sem_info(sem_info);
2496
2497 /* caller can override these */
2498 sem_info->cs_emit_wait = true;
2499 sem_info->cs_emit_signal = true;
2500 return ret;
2501 }
2502
2503 /* Signals fence as soon as all the work currently put on queue is done. */
2504 static VkResult radv_signal_fence(struct radv_queue *queue,
2505 struct radv_fence *fence)
2506 {
2507 int ret;
2508 VkResult result;
2509 struct radv_winsys_sem_info sem_info;
2510
2511 result = radv_alloc_sem_info(queue->device->instance, &sem_info, 0, NULL, 0, NULL,
2512 radv_fence_to_handle(fence));
2513 if (result != VK_SUCCESS)
2514 return result;
2515
2516 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
2517 &queue->device->empty_cs[queue->queue_family_index],
2518 1, NULL, NULL, &sem_info, NULL,
2519 false, fence->fence);
2520 radv_free_sem_info(&sem_info);
2521
2522 if (ret)
2523 return vk_error(queue->device->instance, VK_ERROR_DEVICE_LOST);
2524
2525 return VK_SUCCESS;
2526 }
2527
2528 VkResult radv_QueueSubmit(
2529 VkQueue _queue,
2530 uint32_t submitCount,
2531 const VkSubmitInfo* pSubmits,
2532 VkFence _fence)
2533 {
2534 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2535 RADV_FROM_HANDLE(radv_fence, fence, _fence);
2536 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
2537 struct radeon_winsys_ctx *ctx = queue->hw_ctx;
2538 int ret;
2539 uint32_t max_cs_submission = queue->device->trace_bo ? 1 : UINT32_MAX;
2540 uint32_t scratch_size = 0;
2541 uint32_t compute_scratch_size = 0;
2542 uint32_t esgs_ring_size = 0, gsvs_ring_size = 0;
2543 struct radeon_cmdbuf *initial_preamble_cs = NULL, *initial_flush_preamble_cs = NULL, *continue_preamble_cs = NULL;
2544 VkResult result;
2545 bool fence_emitted = false;
2546 bool tess_rings_needed = false;
2547 bool sample_positions_needed = false;
2548
2549 /* Do this first so failing to allocate scratch buffers can't result in
2550 * partially executed submissions. */
2551 for (uint32_t i = 0; i < submitCount; i++) {
2552 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2553 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2554 pSubmits[i].pCommandBuffers[j]);
2555
2556 scratch_size = MAX2(scratch_size, cmd_buffer->scratch_size_needed);
2557 compute_scratch_size = MAX2(compute_scratch_size,
2558 cmd_buffer->compute_scratch_size_needed);
2559 esgs_ring_size = MAX2(esgs_ring_size, cmd_buffer->esgs_ring_size_needed);
2560 gsvs_ring_size = MAX2(gsvs_ring_size, cmd_buffer->gsvs_ring_size_needed);
2561 tess_rings_needed |= cmd_buffer->tess_rings_needed;
2562 sample_positions_needed |= cmd_buffer->sample_positions_needed;
2563 }
2564 }
2565
2566 result = radv_get_preamble_cs(queue, scratch_size, compute_scratch_size,
2567 esgs_ring_size, gsvs_ring_size, tess_rings_needed,
2568 sample_positions_needed, &initial_flush_preamble_cs,
2569 &initial_preamble_cs, &continue_preamble_cs);
2570 if (result != VK_SUCCESS)
2571 return result;
2572
2573 for (uint32_t i = 0; i < submitCount; i++) {
2574 struct radeon_cmdbuf **cs_array;
2575 bool do_flush = !i || pSubmits[i].pWaitDstStageMask;
2576 bool can_patch = true;
2577 uint32_t advance;
2578 struct radv_winsys_sem_info sem_info;
2579
2580 result = radv_alloc_sem_info(queue->device->instance,
2581 &sem_info,
2582 pSubmits[i].waitSemaphoreCount,
2583 pSubmits[i].pWaitSemaphores,
2584 pSubmits[i].signalSemaphoreCount,
2585 pSubmits[i].pSignalSemaphores,
2586 _fence);
2587 if (result != VK_SUCCESS)
2588 return result;
2589
2590 if (!pSubmits[i].commandBufferCount) {
2591 if (pSubmits[i].waitSemaphoreCount || pSubmits[i].signalSemaphoreCount) {
2592 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx,
2593 &queue->device->empty_cs[queue->queue_family_index],
2594 1, NULL, NULL,
2595 &sem_info, NULL,
2596 false, base_fence);
2597 if (ret) {
2598 radv_loge("failed to submit CS %d\n", i);
2599 abort();
2600 }
2601 fence_emitted = true;
2602 }
2603 radv_free_sem_info(&sem_info);
2604 continue;
2605 }
2606
2607 cs_array = malloc(sizeof(struct radeon_cmdbuf *) *
2608 (pSubmits[i].commandBufferCount));
2609
2610 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j++) {
2611 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer,
2612 pSubmits[i].pCommandBuffers[j]);
2613 assert(cmd_buffer->level == VK_COMMAND_BUFFER_LEVEL_PRIMARY);
2614
2615 cs_array[j] = cmd_buffer->cs;
2616 if ((cmd_buffer->usage_flags & VK_COMMAND_BUFFER_USAGE_SIMULTANEOUS_USE_BIT))
2617 can_patch = false;
2618
2619 cmd_buffer->status = RADV_CMD_BUFFER_STATUS_PENDING;
2620 }
2621
2622 for (uint32_t j = 0; j < pSubmits[i].commandBufferCount; j += advance) {
2623 struct radeon_cmdbuf *initial_preamble = (do_flush && !j) ? initial_flush_preamble_cs : initial_preamble_cs;
2624 const struct radv_winsys_bo_list *bo_list = NULL;
2625
2626 advance = MIN2(max_cs_submission,
2627 pSubmits[i].commandBufferCount - j);
2628
2629 if (queue->device->trace_bo)
2630 *queue->device->trace_id_ptr = 0;
2631
2632 sem_info.cs_emit_wait = j == 0;
2633 sem_info.cs_emit_signal = j + advance == pSubmits[i].commandBufferCount;
2634
2635 if (unlikely(queue->device->use_global_bo_list)) {
2636 pthread_mutex_lock(&queue->device->bo_list.mutex);
2637 bo_list = &queue->device->bo_list.list;
2638 }
2639
2640 ret = queue->device->ws->cs_submit(ctx, queue->queue_idx, cs_array + j,
2641 advance, initial_preamble, continue_preamble_cs,
2642 &sem_info, bo_list,
2643 can_patch, base_fence);
2644
2645 if (unlikely(queue->device->use_global_bo_list))
2646 pthread_mutex_unlock(&queue->device->bo_list.mutex);
2647
2648 if (ret) {
2649 radv_loge("failed to submit CS %d\n", i);
2650 abort();
2651 }
2652 fence_emitted = true;
2653 if (queue->device->trace_bo) {
2654 radv_check_gpu_hangs(queue, cs_array[j]);
2655 }
2656 }
2657
2658 radv_free_temp_syncobjs(queue->device,
2659 pSubmits[i].waitSemaphoreCount,
2660 pSubmits[i].pWaitSemaphores);
2661 radv_free_sem_info(&sem_info);
2662 free(cs_array);
2663 }
2664
2665 if (fence) {
2666 if (!fence_emitted) {
2667 result = radv_signal_fence(queue, fence);
2668 if (result != VK_SUCCESS)
2669 return result;
2670 }
2671 fence->submitted = true;
2672 }
2673
2674 return VK_SUCCESS;
2675 }
2676
2677 VkResult radv_QueueWaitIdle(
2678 VkQueue _queue)
2679 {
2680 RADV_FROM_HANDLE(radv_queue, queue, _queue);
2681
2682 queue->device->ws->ctx_wait_idle(queue->hw_ctx,
2683 radv_queue_family_to_ring(queue->queue_family_index),
2684 queue->queue_idx);
2685 return VK_SUCCESS;
2686 }
2687
2688 VkResult radv_DeviceWaitIdle(
2689 VkDevice _device)
2690 {
2691 RADV_FROM_HANDLE(radv_device, device, _device);
2692
2693 for (unsigned i = 0; i < RADV_MAX_QUEUE_FAMILIES; i++) {
2694 for (unsigned q = 0; q < device->queue_count[i]; q++) {
2695 radv_QueueWaitIdle(radv_queue_to_handle(&device->queues[i][q]));
2696 }
2697 }
2698 return VK_SUCCESS;
2699 }
2700
2701 VkResult radv_EnumerateInstanceExtensionProperties(
2702 const char* pLayerName,
2703 uint32_t* pPropertyCount,
2704 VkExtensionProperties* pProperties)
2705 {
2706 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2707
2708 for (int i = 0; i < RADV_INSTANCE_EXTENSION_COUNT; i++) {
2709 if (radv_supported_instance_extensions.extensions[i]) {
2710 vk_outarray_append(&out, prop) {
2711 *prop = radv_instance_extensions[i];
2712 }
2713 }
2714 }
2715
2716 return vk_outarray_status(&out);
2717 }
2718
2719 VkResult radv_EnumerateDeviceExtensionProperties(
2720 VkPhysicalDevice physicalDevice,
2721 const char* pLayerName,
2722 uint32_t* pPropertyCount,
2723 VkExtensionProperties* pProperties)
2724 {
2725 RADV_FROM_HANDLE(radv_physical_device, device, physicalDevice);
2726 VK_OUTARRAY_MAKE(out, pProperties, pPropertyCount);
2727
2728 for (int i = 0; i < RADV_DEVICE_EXTENSION_COUNT; i++) {
2729 if (device->supported_extensions.extensions[i]) {
2730 vk_outarray_append(&out, prop) {
2731 *prop = radv_device_extensions[i];
2732 }
2733 }
2734 }
2735
2736 return vk_outarray_status(&out);
2737 }
2738
2739 PFN_vkVoidFunction radv_GetInstanceProcAddr(
2740 VkInstance _instance,
2741 const char* pName)
2742 {
2743 RADV_FROM_HANDLE(radv_instance, instance, _instance);
2744
2745 return radv_lookup_entrypoint_checked(pName,
2746 instance ? instance->apiVersion : 0,
2747 instance ? &instance->enabled_extensions : NULL,
2748 NULL);
2749 }
2750
2751 /* The loader wants us to expose a second GetInstanceProcAddr function
2752 * to work around certain LD_PRELOAD issues seen in apps.
2753 */
2754 PUBLIC
2755 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2756 VkInstance instance,
2757 const char* pName);
2758
2759 PUBLIC
2760 VKAPI_ATTR PFN_vkVoidFunction VKAPI_CALL vk_icdGetInstanceProcAddr(
2761 VkInstance instance,
2762 const char* pName)
2763 {
2764 return radv_GetInstanceProcAddr(instance, pName);
2765 }
2766
2767 PFN_vkVoidFunction radv_GetDeviceProcAddr(
2768 VkDevice _device,
2769 const char* pName)
2770 {
2771 RADV_FROM_HANDLE(radv_device, device, _device);
2772
2773 return radv_lookup_entrypoint_checked(pName,
2774 device->instance->apiVersion,
2775 &device->instance->enabled_extensions,
2776 &device->enabled_extensions);
2777 }
2778
2779 bool radv_get_memory_fd(struct radv_device *device,
2780 struct radv_device_memory *memory,
2781 int *pFD)
2782 {
2783 struct radeon_bo_metadata metadata;
2784
2785 if (memory->image) {
2786 radv_init_metadata(device, memory->image, &metadata);
2787 device->ws->buffer_set_metadata(memory->bo, &metadata);
2788 }
2789
2790 return device->ws->buffer_get_fd(device->ws, memory->bo,
2791 pFD);
2792 }
2793
2794 static VkResult radv_alloc_memory(struct radv_device *device,
2795 const VkMemoryAllocateInfo* pAllocateInfo,
2796 const VkAllocationCallbacks* pAllocator,
2797 VkDeviceMemory* pMem)
2798 {
2799 struct radv_device_memory *mem;
2800 VkResult result;
2801 enum radeon_bo_domain domain;
2802 uint32_t flags = 0;
2803 enum radv_mem_type mem_type_index = device->physical_device->mem_type_indices[pAllocateInfo->memoryTypeIndex];
2804
2805 assert(pAllocateInfo->sType == VK_STRUCTURE_TYPE_MEMORY_ALLOCATE_INFO);
2806
2807 if (pAllocateInfo->allocationSize == 0) {
2808 /* Apparently, this is allowed */
2809 *pMem = VK_NULL_HANDLE;
2810 return VK_SUCCESS;
2811 }
2812
2813 const VkImportMemoryFdInfoKHR *import_info =
2814 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_FD_INFO_KHR);
2815 const VkMemoryDedicatedAllocateInfoKHR *dedicate_info =
2816 vk_find_struct_const(pAllocateInfo->pNext, MEMORY_DEDICATED_ALLOCATE_INFO_KHR);
2817 const VkExportMemoryAllocateInfoKHR *export_info =
2818 vk_find_struct_const(pAllocateInfo->pNext, EXPORT_MEMORY_ALLOCATE_INFO_KHR);
2819 const VkImportMemoryHostPointerInfoEXT *host_ptr_info =
2820 vk_find_struct_const(pAllocateInfo->pNext, IMPORT_MEMORY_HOST_POINTER_INFO_EXT);
2821
2822 const struct wsi_memory_allocate_info *wsi_info =
2823 vk_find_struct_const(pAllocateInfo->pNext, WSI_MEMORY_ALLOCATE_INFO_MESA);
2824
2825 mem = vk_alloc2(&device->alloc, pAllocator, sizeof(*mem), 8,
2826 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
2827 if (mem == NULL)
2828 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
2829
2830 if (wsi_info && wsi_info->implicit_sync)
2831 flags |= RADEON_FLAG_IMPLICIT_SYNC;
2832
2833 if (dedicate_info) {
2834 mem->image = radv_image_from_handle(dedicate_info->image);
2835 mem->buffer = radv_buffer_from_handle(dedicate_info->buffer);
2836 } else {
2837 mem->image = NULL;
2838 mem->buffer = NULL;
2839 }
2840
2841 mem->user_ptr = NULL;
2842
2843 if (import_info) {
2844 assert(import_info->handleType ==
2845 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
2846 import_info->handleType ==
2847 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
2848 mem->bo = device->ws->buffer_from_fd(device->ws, import_info->fd,
2849 NULL, NULL);
2850 if (!mem->bo) {
2851 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2852 goto fail;
2853 } else {
2854 close(import_info->fd);
2855 }
2856 } else if (host_ptr_info) {
2857 assert(host_ptr_info->handleType == VK_EXTERNAL_MEMORY_HANDLE_TYPE_HOST_ALLOCATION_BIT_EXT);
2858 assert(mem_type_index == RADV_MEM_TYPE_GTT_CACHED);
2859 mem->bo = device->ws->buffer_from_ptr(device->ws, host_ptr_info->pHostPointer,
2860 pAllocateInfo->allocationSize);
2861 if (!mem->bo) {
2862 result = VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR;
2863 goto fail;
2864 } else {
2865 mem->user_ptr = host_ptr_info->pHostPointer;
2866 }
2867 } else {
2868 uint64_t alloc_size = align_u64(pAllocateInfo->allocationSize, 4096);
2869 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE ||
2870 mem_type_index == RADV_MEM_TYPE_GTT_CACHED)
2871 domain = RADEON_DOMAIN_GTT;
2872 else
2873 domain = RADEON_DOMAIN_VRAM;
2874
2875 if (mem_type_index == RADV_MEM_TYPE_VRAM)
2876 flags |= RADEON_FLAG_NO_CPU_ACCESS;
2877 else
2878 flags |= RADEON_FLAG_CPU_ACCESS;
2879
2880 if (mem_type_index == RADV_MEM_TYPE_GTT_WRITE_COMBINE)
2881 flags |= RADEON_FLAG_GTT_WC;
2882
2883 if (!dedicate_info && !import_info && (!export_info || !export_info->handleTypes))
2884 flags |= RADEON_FLAG_NO_INTERPROCESS_SHARING;
2885
2886 mem->bo = device->ws->buffer_create(device->ws, alloc_size, device->physical_device->rad_info.max_alignment,
2887 domain, flags);
2888
2889 if (!mem->bo) {
2890 result = VK_ERROR_OUT_OF_DEVICE_MEMORY;
2891 goto fail;
2892 }
2893 mem->type_index = mem_type_index;
2894 }
2895
2896 result = radv_bo_list_add(device, mem->bo);
2897 if (result != VK_SUCCESS)
2898 goto fail_bo;
2899
2900 *pMem = radv_device_memory_to_handle(mem);
2901
2902 return VK_SUCCESS;
2903
2904 fail_bo:
2905 device->ws->buffer_destroy(mem->bo);
2906 fail:
2907 vk_free2(&device->alloc, pAllocator, mem);
2908
2909 return result;
2910 }
2911
2912 VkResult radv_AllocateMemory(
2913 VkDevice _device,
2914 const VkMemoryAllocateInfo* pAllocateInfo,
2915 const VkAllocationCallbacks* pAllocator,
2916 VkDeviceMemory* pMem)
2917 {
2918 RADV_FROM_HANDLE(radv_device, device, _device);
2919 return radv_alloc_memory(device, pAllocateInfo, pAllocator, pMem);
2920 }
2921
2922 void radv_FreeMemory(
2923 VkDevice _device,
2924 VkDeviceMemory _mem,
2925 const VkAllocationCallbacks* pAllocator)
2926 {
2927 RADV_FROM_HANDLE(radv_device, device, _device);
2928 RADV_FROM_HANDLE(radv_device_memory, mem, _mem);
2929
2930 if (mem == NULL)
2931 return;
2932
2933 radv_bo_list_remove(device, mem->bo);
2934 device->ws->buffer_destroy(mem->bo);
2935 mem->bo = NULL;
2936
2937 vk_free2(&device->alloc, pAllocator, mem);
2938 }
2939
2940 VkResult radv_MapMemory(
2941 VkDevice _device,
2942 VkDeviceMemory _memory,
2943 VkDeviceSize offset,
2944 VkDeviceSize size,
2945 VkMemoryMapFlags flags,
2946 void** ppData)
2947 {
2948 RADV_FROM_HANDLE(radv_device, device, _device);
2949 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2950
2951 if (mem == NULL) {
2952 *ppData = NULL;
2953 return VK_SUCCESS;
2954 }
2955
2956 if (mem->user_ptr)
2957 *ppData = mem->user_ptr;
2958 else
2959 *ppData = device->ws->buffer_map(mem->bo);
2960
2961 if (*ppData) {
2962 *ppData += offset;
2963 return VK_SUCCESS;
2964 }
2965
2966 return vk_error(device->instance, VK_ERROR_MEMORY_MAP_FAILED);
2967 }
2968
2969 void radv_UnmapMemory(
2970 VkDevice _device,
2971 VkDeviceMemory _memory)
2972 {
2973 RADV_FROM_HANDLE(radv_device, device, _device);
2974 RADV_FROM_HANDLE(radv_device_memory, mem, _memory);
2975
2976 if (mem == NULL)
2977 return;
2978
2979 if (mem->user_ptr == NULL)
2980 device->ws->buffer_unmap(mem->bo);
2981 }
2982
2983 VkResult radv_FlushMappedMemoryRanges(
2984 VkDevice _device,
2985 uint32_t memoryRangeCount,
2986 const VkMappedMemoryRange* pMemoryRanges)
2987 {
2988 return VK_SUCCESS;
2989 }
2990
2991 VkResult radv_InvalidateMappedMemoryRanges(
2992 VkDevice _device,
2993 uint32_t memoryRangeCount,
2994 const VkMappedMemoryRange* pMemoryRanges)
2995 {
2996 return VK_SUCCESS;
2997 }
2998
2999 void radv_GetBufferMemoryRequirements(
3000 VkDevice _device,
3001 VkBuffer _buffer,
3002 VkMemoryRequirements* pMemoryRequirements)
3003 {
3004 RADV_FROM_HANDLE(radv_device, device, _device);
3005 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3006
3007 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3008
3009 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3010 pMemoryRequirements->alignment = 4096;
3011 else
3012 pMemoryRequirements->alignment = 16;
3013
3014 pMemoryRequirements->size = align64(buffer->size, pMemoryRequirements->alignment);
3015 }
3016
3017 void radv_GetBufferMemoryRequirements2(
3018 VkDevice device,
3019 const VkBufferMemoryRequirementsInfo2KHR* pInfo,
3020 VkMemoryRequirements2KHR* pMemoryRequirements)
3021 {
3022 radv_GetBufferMemoryRequirements(device, pInfo->buffer,
3023 &pMemoryRequirements->memoryRequirements);
3024 RADV_FROM_HANDLE(radv_buffer, buffer, pInfo->buffer);
3025 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3026 switch (ext->sType) {
3027 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3028 VkMemoryDedicatedRequirementsKHR *req =
3029 (VkMemoryDedicatedRequirementsKHR *) ext;
3030 req->requiresDedicatedAllocation = buffer->shareable;
3031 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3032 break;
3033 }
3034 default:
3035 break;
3036 }
3037 }
3038 }
3039
3040 void radv_GetImageMemoryRequirements(
3041 VkDevice _device,
3042 VkImage _image,
3043 VkMemoryRequirements* pMemoryRequirements)
3044 {
3045 RADV_FROM_HANDLE(radv_device, device, _device);
3046 RADV_FROM_HANDLE(radv_image, image, _image);
3047
3048 pMemoryRequirements->memoryTypeBits = (1u << device->physical_device->memory_properties.memoryTypeCount) - 1;
3049
3050 pMemoryRequirements->size = image->size;
3051 pMemoryRequirements->alignment = image->alignment;
3052 }
3053
3054 void radv_GetImageMemoryRequirements2(
3055 VkDevice device,
3056 const VkImageMemoryRequirementsInfo2KHR* pInfo,
3057 VkMemoryRequirements2KHR* pMemoryRequirements)
3058 {
3059 radv_GetImageMemoryRequirements(device, pInfo->image,
3060 &pMemoryRequirements->memoryRequirements);
3061
3062 RADV_FROM_HANDLE(radv_image, image, pInfo->image);
3063
3064 vk_foreach_struct(ext, pMemoryRequirements->pNext) {
3065 switch (ext->sType) {
3066 case VK_STRUCTURE_TYPE_MEMORY_DEDICATED_REQUIREMENTS_KHR: {
3067 VkMemoryDedicatedRequirementsKHR *req =
3068 (VkMemoryDedicatedRequirementsKHR *) ext;
3069 req->requiresDedicatedAllocation = image->shareable;
3070 req->prefersDedicatedAllocation = req->requiresDedicatedAllocation;
3071 break;
3072 }
3073 default:
3074 break;
3075 }
3076 }
3077 }
3078
3079 void radv_GetImageSparseMemoryRequirements(
3080 VkDevice device,
3081 VkImage image,
3082 uint32_t* pSparseMemoryRequirementCount,
3083 VkSparseImageMemoryRequirements* pSparseMemoryRequirements)
3084 {
3085 stub();
3086 }
3087
3088 void radv_GetImageSparseMemoryRequirements2(
3089 VkDevice device,
3090 const VkImageSparseMemoryRequirementsInfo2KHR* pInfo,
3091 uint32_t* pSparseMemoryRequirementCount,
3092 VkSparseImageMemoryRequirements2KHR* pSparseMemoryRequirements)
3093 {
3094 stub();
3095 }
3096
3097 void radv_GetDeviceMemoryCommitment(
3098 VkDevice device,
3099 VkDeviceMemory memory,
3100 VkDeviceSize* pCommittedMemoryInBytes)
3101 {
3102 *pCommittedMemoryInBytes = 0;
3103 }
3104
3105 VkResult radv_BindBufferMemory2(VkDevice device,
3106 uint32_t bindInfoCount,
3107 const VkBindBufferMemoryInfoKHR *pBindInfos)
3108 {
3109 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3110 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3111 RADV_FROM_HANDLE(radv_buffer, buffer, pBindInfos[i].buffer);
3112
3113 if (mem) {
3114 buffer->bo = mem->bo;
3115 buffer->offset = pBindInfos[i].memoryOffset;
3116 } else {
3117 buffer->bo = NULL;
3118 }
3119 }
3120 return VK_SUCCESS;
3121 }
3122
3123 VkResult radv_BindBufferMemory(
3124 VkDevice device,
3125 VkBuffer buffer,
3126 VkDeviceMemory memory,
3127 VkDeviceSize memoryOffset)
3128 {
3129 const VkBindBufferMemoryInfoKHR info = {
3130 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3131 .buffer = buffer,
3132 .memory = memory,
3133 .memoryOffset = memoryOffset
3134 };
3135
3136 return radv_BindBufferMemory2(device, 1, &info);
3137 }
3138
3139 VkResult radv_BindImageMemory2(VkDevice device,
3140 uint32_t bindInfoCount,
3141 const VkBindImageMemoryInfoKHR *pBindInfos)
3142 {
3143 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3144 RADV_FROM_HANDLE(radv_device_memory, mem, pBindInfos[i].memory);
3145 RADV_FROM_HANDLE(radv_image, image, pBindInfos[i].image);
3146
3147 if (mem) {
3148 image->bo = mem->bo;
3149 image->offset = pBindInfos[i].memoryOffset;
3150 } else {
3151 image->bo = NULL;
3152 image->offset = 0;
3153 }
3154 }
3155 return VK_SUCCESS;
3156 }
3157
3158
3159 VkResult radv_BindImageMemory(
3160 VkDevice device,
3161 VkImage image,
3162 VkDeviceMemory memory,
3163 VkDeviceSize memoryOffset)
3164 {
3165 const VkBindImageMemoryInfoKHR info = {
3166 .sType = VK_STRUCTURE_TYPE_BIND_BUFFER_MEMORY_INFO_KHR,
3167 .image = image,
3168 .memory = memory,
3169 .memoryOffset = memoryOffset
3170 };
3171
3172 return radv_BindImageMemory2(device, 1, &info);
3173 }
3174
3175
3176 static void
3177 radv_sparse_buffer_bind_memory(struct radv_device *device,
3178 const VkSparseBufferMemoryBindInfo *bind)
3179 {
3180 RADV_FROM_HANDLE(radv_buffer, buffer, bind->buffer);
3181
3182 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3183 struct radv_device_memory *mem = NULL;
3184
3185 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3186 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3187
3188 device->ws->buffer_virtual_bind(buffer->bo,
3189 bind->pBinds[i].resourceOffset,
3190 bind->pBinds[i].size,
3191 mem ? mem->bo : NULL,
3192 bind->pBinds[i].memoryOffset);
3193 }
3194 }
3195
3196 static void
3197 radv_sparse_image_opaque_bind_memory(struct radv_device *device,
3198 const VkSparseImageOpaqueMemoryBindInfo *bind)
3199 {
3200 RADV_FROM_HANDLE(radv_image, image, bind->image);
3201
3202 for (uint32_t i = 0; i < bind->bindCount; ++i) {
3203 struct radv_device_memory *mem = NULL;
3204
3205 if (bind->pBinds[i].memory != VK_NULL_HANDLE)
3206 mem = radv_device_memory_from_handle(bind->pBinds[i].memory);
3207
3208 device->ws->buffer_virtual_bind(image->bo,
3209 bind->pBinds[i].resourceOffset,
3210 bind->pBinds[i].size,
3211 mem ? mem->bo : NULL,
3212 bind->pBinds[i].memoryOffset);
3213 }
3214 }
3215
3216 VkResult radv_QueueBindSparse(
3217 VkQueue _queue,
3218 uint32_t bindInfoCount,
3219 const VkBindSparseInfo* pBindInfo,
3220 VkFence _fence)
3221 {
3222 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3223 RADV_FROM_HANDLE(radv_queue, queue, _queue);
3224 struct radeon_winsys_fence *base_fence = fence ? fence->fence : NULL;
3225 bool fence_emitted = false;
3226 VkResult result;
3227 int ret;
3228
3229 for (uint32_t i = 0; i < bindInfoCount; ++i) {
3230 struct radv_winsys_sem_info sem_info;
3231 for (uint32_t j = 0; j < pBindInfo[i].bufferBindCount; ++j) {
3232 radv_sparse_buffer_bind_memory(queue->device,
3233 pBindInfo[i].pBufferBinds + j);
3234 }
3235
3236 for (uint32_t j = 0; j < pBindInfo[i].imageOpaqueBindCount; ++j) {
3237 radv_sparse_image_opaque_bind_memory(queue->device,
3238 pBindInfo[i].pImageOpaqueBinds + j);
3239 }
3240
3241 VkResult result;
3242 result = radv_alloc_sem_info(queue->device->instance,
3243 &sem_info,
3244 pBindInfo[i].waitSemaphoreCount,
3245 pBindInfo[i].pWaitSemaphores,
3246 pBindInfo[i].signalSemaphoreCount,
3247 pBindInfo[i].pSignalSemaphores,
3248 _fence);
3249 if (result != VK_SUCCESS)
3250 return result;
3251
3252 if (pBindInfo[i].waitSemaphoreCount || pBindInfo[i].signalSemaphoreCount) {
3253 ret = queue->device->ws->cs_submit(queue->hw_ctx, queue->queue_idx,
3254 &queue->device->empty_cs[queue->queue_family_index],
3255 1, NULL, NULL,
3256 &sem_info, NULL,
3257 false, base_fence);
3258 if (ret) {
3259 radv_loge("failed to submit CS %d\n", i);
3260 abort();
3261 }
3262
3263 fence_emitted = true;
3264 if (fence)
3265 fence->submitted = true;
3266 }
3267
3268 radv_free_sem_info(&sem_info);
3269
3270 }
3271
3272 if (fence) {
3273 if (!fence_emitted) {
3274 result = radv_signal_fence(queue, fence);
3275 if (result != VK_SUCCESS)
3276 return result;
3277 }
3278 fence->submitted = true;
3279 }
3280
3281 return VK_SUCCESS;
3282 }
3283
3284 VkResult radv_CreateFence(
3285 VkDevice _device,
3286 const VkFenceCreateInfo* pCreateInfo,
3287 const VkAllocationCallbacks* pAllocator,
3288 VkFence* pFence)
3289 {
3290 RADV_FROM_HANDLE(radv_device, device, _device);
3291 const VkExportFenceCreateInfoKHR *export =
3292 vk_find_struct_const(pCreateInfo->pNext, EXPORT_FENCE_CREATE_INFO_KHR);
3293 VkExternalFenceHandleTypeFlagsKHR handleTypes =
3294 export ? export->handleTypes : 0;
3295
3296 struct radv_fence *fence = vk_alloc2(&device->alloc, pAllocator,
3297 sizeof(*fence), 8,
3298 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3299
3300 if (!fence)
3301 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3302
3303 fence->fence_wsi = NULL;
3304 fence->submitted = false;
3305 fence->signalled = !!(pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT);
3306 fence->temp_syncobj = 0;
3307 if (device->always_use_syncobj || handleTypes) {
3308 int ret = device->ws->create_syncobj(device->ws, &fence->syncobj);
3309 if (ret) {
3310 vk_free2(&device->alloc, pAllocator, fence);
3311 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3312 }
3313 if (pCreateInfo->flags & VK_FENCE_CREATE_SIGNALED_BIT) {
3314 device->ws->signal_syncobj(device->ws, fence->syncobj);
3315 }
3316 fence->fence = NULL;
3317 } else {
3318 fence->fence = device->ws->create_fence();
3319 if (!fence->fence) {
3320 vk_free2(&device->alloc, pAllocator, fence);
3321 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3322 }
3323 fence->syncobj = 0;
3324 }
3325
3326 *pFence = radv_fence_to_handle(fence);
3327
3328 return VK_SUCCESS;
3329 }
3330
3331 void radv_DestroyFence(
3332 VkDevice _device,
3333 VkFence _fence,
3334 const VkAllocationCallbacks* pAllocator)
3335 {
3336 RADV_FROM_HANDLE(radv_device, device, _device);
3337 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3338
3339 if (!fence)
3340 return;
3341
3342 if (fence->temp_syncobj)
3343 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3344 if (fence->syncobj)
3345 device->ws->destroy_syncobj(device->ws, fence->syncobj);
3346 if (fence->fence)
3347 device->ws->destroy_fence(fence->fence);
3348 if (fence->fence_wsi)
3349 fence->fence_wsi->destroy(fence->fence_wsi);
3350 vk_free2(&device->alloc, pAllocator, fence);
3351 }
3352
3353
3354 static uint64_t radv_get_current_time()
3355 {
3356 struct timespec tv;
3357 clock_gettime(CLOCK_MONOTONIC, &tv);
3358 return tv.tv_nsec + tv.tv_sec*1000000000ull;
3359 }
3360
3361 static uint64_t radv_get_absolute_timeout(uint64_t timeout)
3362 {
3363 uint64_t current_time = radv_get_current_time();
3364
3365 timeout = MIN2(UINT64_MAX - current_time, timeout);
3366
3367 return current_time + timeout;
3368 }
3369
3370
3371 static bool radv_all_fences_plain_and_submitted(uint32_t fenceCount, const VkFence *pFences)
3372 {
3373 for (uint32_t i = 0; i < fenceCount; ++i) {
3374 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3375 if (fence->fence == NULL || fence->syncobj ||
3376 fence->temp_syncobj ||
3377 (!fence->signalled && !fence->submitted))
3378 return false;
3379 }
3380 return true;
3381 }
3382
3383 static bool radv_all_fences_syncobj(uint32_t fenceCount, const VkFence *pFences)
3384 {
3385 for (uint32_t i = 0; i < fenceCount; ++i) {
3386 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3387 if (fence->syncobj == 0 && fence->temp_syncobj == 0)
3388 return false;
3389 }
3390 return true;
3391 }
3392
3393 VkResult radv_WaitForFences(
3394 VkDevice _device,
3395 uint32_t fenceCount,
3396 const VkFence* pFences,
3397 VkBool32 waitAll,
3398 uint64_t timeout)
3399 {
3400 RADV_FROM_HANDLE(radv_device, device, _device);
3401 timeout = radv_get_absolute_timeout(timeout);
3402
3403 if (device->always_use_syncobj &&
3404 radv_all_fences_syncobj(fenceCount, pFences))
3405 {
3406 uint32_t *handles = malloc(sizeof(uint32_t) * fenceCount);
3407 if (!handles)
3408 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3409
3410 for (uint32_t i = 0; i < fenceCount; ++i) {
3411 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3412 handles[i] = fence->temp_syncobj ? fence->temp_syncobj : fence->syncobj;
3413 }
3414
3415 bool success = device->ws->wait_syncobj(device->ws, handles, fenceCount, waitAll, timeout);
3416
3417 free(handles);
3418 return success ? VK_SUCCESS : VK_TIMEOUT;
3419 }
3420
3421 if (!waitAll && fenceCount > 1) {
3422 /* Not doing this by default for waitAll, due to needing to allocate twice. */
3423 if (device->physical_device->rad_info.drm_minor >= 10 && radv_all_fences_plain_and_submitted(fenceCount, pFences)) {
3424 uint32_t wait_count = 0;
3425 struct radeon_winsys_fence **fences = malloc(sizeof(struct radeon_winsys_fence *) * fenceCount);
3426 if (!fences)
3427 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3428
3429 for (uint32_t i = 0; i < fenceCount; ++i) {
3430 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3431
3432 if (fence->signalled) {
3433 free(fences);
3434 return VK_SUCCESS;
3435 }
3436
3437 fences[wait_count++] = fence->fence;
3438 }
3439
3440 bool success = device->ws->fences_wait(device->ws, fences, wait_count,
3441 waitAll, timeout - radv_get_current_time());
3442
3443 free(fences);
3444 return success ? VK_SUCCESS : VK_TIMEOUT;
3445 }
3446
3447 while(radv_get_current_time() <= timeout) {
3448 for (uint32_t i = 0; i < fenceCount; ++i) {
3449 if (radv_GetFenceStatus(_device, pFences[i]) == VK_SUCCESS)
3450 return VK_SUCCESS;
3451 }
3452 }
3453 return VK_TIMEOUT;
3454 }
3455
3456 for (uint32_t i = 0; i < fenceCount; ++i) {
3457 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3458 bool expired = false;
3459
3460 if (fence->temp_syncobj) {
3461 if (!device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, timeout))
3462 return VK_TIMEOUT;
3463 continue;
3464 }
3465
3466 if (fence->syncobj) {
3467 if (!device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, timeout))
3468 return VK_TIMEOUT;
3469 continue;
3470 }
3471
3472 if (fence->signalled)
3473 continue;
3474
3475 if (fence->fence) {
3476 if (!fence->submitted) {
3477 while(radv_get_current_time() <= timeout &&
3478 !fence->submitted)
3479 /* Do nothing */;
3480
3481 if (!fence->submitted)
3482 return VK_TIMEOUT;
3483
3484 /* Recheck as it may have been set by
3485 * submitting operations. */
3486
3487 if (fence->signalled)
3488 continue;
3489 }
3490
3491 expired = device->ws->fence_wait(device->ws,
3492 fence->fence,
3493 true, timeout);
3494 if (!expired)
3495 return VK_TIMEOUT;
3496 }
3497
3498 if (fence->fence_wsi) {
3499 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, timeout);
3500 if (result != VK_SUCCESS)
3501 return result;
3502 }
3503
3504 fence->signalled = true;
3505 }
3506
3507 return VK_SUCCESS;
3508 }
3509
3510 VkResult radv_ResetFences(VkDevice _device,
3511 uint32_t fenceCount,
3512 const VkFence *pFences)
3513 {
3514 RADV_FROM_HANDLE(radv_device, device, _device);
3515
3516 for (unsigned i = 0; i < fenceCount; ++i) {
3517 RADV_FROM_HANDLE(radv_fence, fence, pFences[i]);
3518 fence->submitted = fence->signalled = false;
3519
3520 /* Per spec, we first restore the permanent payload, and then reset, so
3521 * having a temp syncobj should not skip resetting the permanent syncobj. */
3522 if (fence->temp_syncobj) {
3523 device->ws->destroy_syncobj(device->ws, fence->temp_syncobj);
3524 fence->temp_syncobj = 0;
3525 }
3526
3527 if (fence->syncobj) {
3528 device->ws->reset_syncobj(device->ws, fence->syncobj);
3529 }
3530 }
3531
3532 return VK_SUCCESS;
3533 }
3534
3535 VkResult radv_GetFenceStatus(VkDevice _device, VkFence _fence)
3536 {
3537 RADV_FROM_HANDLE(radv_device, device, _device);
3538 RADV_FROM_HANDLE(radv_fence, fence, _fence);
3539
3540 if (fence->temp_syncobj) {
3541 bool success = device->ws->wait_syncobj(device->ws, &fence->temp_syncobj, 1, true, 0);
3542 return success ? VK_SUCCESS : VK_NOT_READY;
3543 }
3544
3545 if (fence->syncobj) {
3546 bool success = device->ws->wait_syncobj(device->ws, &fence->syncobj, 1, true, 0);
3547 return success ? VK_SUCCESS : VK_NOT_READY;
3548 }
3549
3550 if (fence->signalled)
3551 return VK_SUCCESS;
3552 if (!fence->submitted)
3553 return VK_NOT_READY;
3554 if (fence->fence) {
3555 if (!device->ws->fence_wait(device->ws, fence->fence, false, 0))
3556 return VK_NOT_READY;
3557 }
3558 if (fence->fence_wsi) {
3559 VkResult result = fence->fence_wsi->wait(fence->fence_wsi, 0);
3560
3561 if (result != VK_SUCCESS) {
3562 if (result == VK_TIMEOUT)
3563 return VK_NOT_READY;
3564 return result;
3565 }
3566 }
3567 return VK_SUCCESS;
3568 }
3569
3570
3571 // Queue semaphore functions
3572
3573 VkResult radv_CreateSemaphore(
3574 VkDevice _device,
3575 const VkSemaphoreCreateInfo* pCreateInfo,
3576 const VkAllocationCallbacks* pAllocator,
3577 VkSemaphore* pSemaphore)
3578 {
3579 RADV_FROM_HANDLE(radv_device, device, _device);
3580 const VkExportSemaphoreCreateInfoKHR *export =
3581 vk_find_struct_const(pCreateInfo->pNext, EXPORT_SEMAPHORE_CREATE_INFO_KHR);
3582 VkExternalSemaphoreHandleTypeFlagsKHR handleTypes =
3583 export ? export->handleTypes : 0;
3584
3585 struct radv_semaphore *sem = vk_alloc2(&device->alloc, pAllocator,
3586 sizeof(*sem), 8,
3587 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3588 if (!sem)
3589 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3590
3591 sem->temp_syncobj = 0;
3592 /* create a syncobject if we are going to export this semaphore */
3593 if (device->always_use_syncobj || handleTypes) {
3594 assert (device->physical_device->rad_info.has_syncobj);
3595 int ret = device->ws->create_syncobj(device->ws, &sem->syncobj);
3596 if (ret) {
3597 vk_free2(&device->alloc, pAllocator, sem);
3598 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3599 }
3600 sem->sem = NULL;
3601 } else {
3602 sem->sem = device->ws->create_sem(device->ws);
3603 if (!sem->sem) {
3604 vk_free2(&device->alloc, pAllocator, sem);
3605 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3606 }
3607 sem->syncobj = 0;
3608 }
3609
3610 *pSemaphore = radv_semaphore_to_handle(sem);
3611 return VK_SUCCESS;
3612 }
3613
3614 void radv_DestroySemaphore(
3615 VkDevice _device,
3616 VkSemaphore _semaphore,
3617 const VkAllocationCallbacks* pAllocator)
3618 {
3619 RADV_FROM_HANDLE(radv_device, device, _device);
3620 RADV_FROM_HANDLE(radv_semaphore, sem, _semaphore);
3621 if (!_semaphore)
3622 return;
3623
3624 if (sem->syncobj)
3625 device->ws->destroy_syncobj(device->ws, sem->syncobj);
3626 else
3627 device->ws->destroy_sem(sem->sem);
3628 vk_free2(&device->alloc, pAllocator, sem);
3629 }
3630
3631 VkResult radv_CreateEvent(
3632 VkDevice _device,
3633 const VkEventCreateInfo* pCreateInfo,
3634 const VkAllocationCallbacks* pAllocator,
3635 VkEvent* pEvent)
3636 {
3637 RADV_FROM_HANDLE(radv_device, device, _device);
3638 struct radv_event *event = vk_alloc2(&device->alloc, pAllocator,
3639 sizeof(*event), 8,
3640 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3641
3642 if (!event)
3643 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3644
3645 event->bo = device->ws->buffer_create(device->ws, 8, 8,
3646 RADEON_DOMAIN_GTT,
3647 RADEON_FLAG_VA_UNCACHED | RADEON_FLAG_CPU_ACCESS | RADEON_FLAG_NO_INTERPROCESS_SHARING);
3648 if (!event->bo) {
3649 vk_free2(&device->alloc, pAllocator, event);
3650 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3651 }
3652
3653 event->map = (uint64_t*)device->ws->buffer_map(event->bo);
3654
3655 *pEvent = radv_event_to_handle(event);
3656
3657 return VK_SUCCESS;
3658 }
3659
3660 void radv_DestroyEvent(
3661 VkDevice _device,
3662 VkEvent _event,
3663 const VkAllocationCallbacks* pAllocator)
3664 {
3665 RADV_FROM_HANDLE(radv_device, device, _device);
3666 RADV_FROM_HANDLE(radv_event, event, _event);
3667
3668 if (!event)
3669 return;
3670 device->ws->buffer_destroy(event->bo);
3671 vk_free2(&device->alloc, pAllocator, event);
3672 }
3673
3674 VkResult radv_GetEventStatus(
3675 VkDevice _device,
3676 VkEvent _event)
3677 {
3678 RADV_FROM_HANDLE(radv_event, event, _event);
3679
3680 if (*event->map == 1)
3681 return VK_EVENT_SET;
3682 return VK_EVENT_RESET;
3683 }
3684
3685 VkResult radv_SetEvent(
3686 VkDevice _device,
3687 VkEvent _event)
3688 {
3689 RADV_FROM_HANDLE(radv_event, event, _event);
3690 *event->map = 1;
3691
3692 return VK_SUCCESS;
3693 }
3694
3695 VkResult radv_ResetEvent(
3696 VkDevice _device,
3697 VkEvent _event)
3698 {
3699 RADV_FROM_HANDLE(radv_event, event, _event);
3700 *event->map = 0;
3701
3702 return VK_SUCCESS;
3703 }
3704
3705 VkResult radv_CreateBuffer(
3706 VkDevice _device,
3707 const VkBufferCreateInfo* pCreateInfo,
3708 const VkAllocationCallbacks* pAllocator,
3709 VkBuffer* pBuffer)
3710 {
3711 RADV_FROM_HANDLE(radv_device, device, _device);
3712 struct radv_buffer *buffer;
3713
3714 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_BUFFER_CREATE_INFO);
3715
3716 buffer = vk_alloc2(&device->alloc, pAllocator, sizeof(*buffer), 8,
3717 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
3718 if (buffer == NULL)
3719 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
3720
3721 buffer->size = pCreateInfo->size;
3722 buffer->usage = pCreateInfo->usage;
3723 buffer->bo = NULL;
3724 buffer->offset = 0;
3725 buffer->flags = pCreateInfo->flags;
3726
3727 buffer->shareable = vk_find_struct_const(pCreateInfo->pNext,
3728 EXTERNAL_MEMORY_BUFFER_CREATE_INFO_KHR) != NULL;
3729
3730 if (pCreateInfo->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT) {
3731 buffer->bo = device->ws->buffer_create(device->ws,
3732 align64(buffer->size, 4096),
3733 4096, 0, RADEON_FLAG_VIRTUAL);
3734 if (!buffer->bo) {
3735 vk_free2(&device->alloc, pAllocator, buffer);
3736 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
3737 }
3738 }
3739
3740 *pBuffer = radv_buffer_to_handle(buffer);
3741
3742 return VK_SUCCESS;
3743 }
3744
3745 void radv_DestroyBuffer(
3746 VkDevice _device,
3747 VkBuffer _buffer,
3748 const VkAllocationCallbacks* pAllocator)
3749 {
3750 RADV_FROM_HANDLE(radv_device, device, _device);
3751 RADV_FROM_HANDLE(radv_buffer, buffer, _buffer);
3752
3753 if (!buffer)
3754 return;
3755
3756 if (buffer->flags & VK_BUFFER_CREATE_SPARSE_BINDING_BIT)
3757 device->ws->buffer_destroy(buffer->bo);
3758
3759 vk_free2(&device->alloc, pAllocator, buffer);
3760 }
3761
3762 static inline unsigned
3763 si_tile_mode_index(const struct radv_image *image, unsigned level, bool stencil)
3764 {
3765 if (stencil)
3766 return image->surface.u.legacy.stencil_tiling_index[level];
3767 else
3768 return image->surface.u.legacy.tiling_index[level];
3769 }
3770
3771 static uint32_t radv_surface_max_layer_count(struct radv_image_view *iview)
3772 {
3773 return iview->type == VK_IMAGE_VIEW_TYPE_3D ? iview->extent.depth : (iview->base_layer + iview->layer_count);
3774 }
3775
3776 static uint32_t
3777 radv_init_dcc_control_reg(struct radv_device *device,
3778 struct radv_image_view *iview)
3779 {
3780 unsigned max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_256B;
3781 unsigned min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_32B;
3782 unsigned max_compressed_block_size;
3783 unsigned independent_64b_blocks;
3784
3785 if (device->physical_device->rad_info.chip_class < VI)
3786 return 0;
3787
3788 if (iview->image->info.samples > 1) {
3789 if (iview->image->surface.bpe == 1)
3790 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3791 else if (iview->image->surface.bpe == 2)
3792 max_uncompressed_block_size = V_028C78_MAX_BLOCK_SIZE_128B;
3793 }
3794
3795 if (!device->physical_device->rad_info.has_dedicated_vram) {
3796 /* amdvlk: [min-compressed-block-size] should be set to 32 for
3797 * dGPU and 64 for APU because all of our APUs to date use
3798 * DIMMs which have a request granularity size of 64B while all
3799 * other chips have a 32B request size.
3800 */
3801 min_compressed_block_size = V_028C78_MIN_BLOCK_SIZE_64B;
3802 }
3803
3804 if (iview->image->usage & (VK_IMAGE_USAGE_SAMPLED_BIT |
3805 VK_IMAGE_USAGE_TRANSFER_SRC_BIT |
3806 VK_IMAGE_USAGE_INPUT_ATTACHMENT_BIT)) {
3807 /* If this DCC image is potentially going to be used in texture
3808 * fetches, we need some special settings.
3809 */
3810 independent_64b_blocks = 1;
3811 max_compressed_block_size = V_028C78_MAX_BLOCK_SIZE_64B;
3812 } else {
3813 /* MAX_UNCOMPRESSED_BLOCK_SIZE must be >=
3814 * MAX_COMPRESSED_BLOCK_SIZE. Set MAX_COMPRESSED_BLOCK_SIZE as
3815 * big as possible for better compression state.
3816 */
3817 independent_64b_blocks = 0;
3818 max_compressed_block_size = max_uncompressed_block_size;
3819 }
3820
3821 return S_028C78_MAX_UNCOMPRESSED_BLOCK_SIZE(max_uncompressed_block_size) |
3822 S_028C78_MAX_COMPRESSED_BLOCK_SIZE(max_compressed_block_size) |
3823 S_028C78_MIN_COMPRESSED_BLOCK_SIZE(min_compressed_block_size) |
3824 S_028C78_INDEPENDENT_64B_BLOCKS(independent_64b_blocks);
3825 }
3826
3827 static void
3828 radv_initialise_color_surface(struct radv_device *device,
3829 struct radv_color_buffer_info *cb,
3830 struct radv_image_view *iview)
3831 {
3832 const struct vk_format_description *desc;
3833 unsigned ntype, format, swap, endian;
3834 unsigned blend_clamp = 0, blend_bypass = 0;
3835 uint64_t va;
3836 const struct radeon_surf *surf = &iview->image->surface;
3837
3838 desc = vk_format_description(iview->vk_format);
3839
3840 memset(cb, 0, sizeof(*cb));
3841
3842 /* Intensity is implemented as Red, so treat it that way. */
3843 cb->cb_color_attrib = S_028C74_FORCE_DST_ALPHA_1(desc->swizzle[3] == VK_SWIZZLE_1);
3844
3845 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3846
3847 cb->cb_color_base = va >> 8;
3848
3849 if (device->physical_device->rad_info.chip_class >= GFX9) {
3850 struct gfx9_surf_meta_flags meta;
3851 if (iview->image->dcc_offset)
3852 meta = iview->image->surface.u.gfx9.dcc;
3853 else
3854 meta = iview->image->surface.u.gfx9.cmask;
3855
3856 cb->cb_color_attrib |= S_028C74_COLOR_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
3857 S_028C74_FMASK_SW_MODE(iview->image->surface.u.gfx9.fmask.swizzle_mode) |
3858 S_028C74_RB_ALIGNED(meta.rb_aligned) |
3859 S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
3860
3861 cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset >> 8;
3862 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3863 } else {
3864 const struct legacy_surf_level *level_info = &surf->u.legacy.level[iview->base_mip];
3865 unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
3866
3867 cb->cb_color_base += level_info->offset >> 8;
3868 if (level_info->mode == RADEON_SURF_MODE_2D)
3869 cb->cb_color_base |= iview->image->surface.tile_swizzle;
3870
3871 pitch_tile_max = level_info->nblk_x / 8 - 1;
3872 slice_tile_max = (level_info->nblk_x * level_info->nblk_y) / 64 - 1;
3873 tile_mode_index = si_tile_mode_index(iview->image, iview->base_mip, false);
3874
3875 cb->cb_color_pitch = S_028C64_TILE_MAX(pitch_tile_max);
3876 cb->cb_color_slice = S_028C68_TILE_MAX(slice_tile_max);
3877 cb->cb_color_cmask_slice = iview->image->cmask.slice_tile_max;
3878
3879 cb->cb_color_attrib |= S_028C74_TILE_MODE_INDEX(tile_mode_index);
3880
3881 if (radv_image_has_fmask(iview->image)) {
3882 if (device->physical_device->rad_info.chip_class >= CIK)
3883 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(iview->image->fmask.pitch_in_pixels / 8 - 1);
3884 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(iview->image->fmask.tile_mode_index);
3885 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(iview->image->fmask.slice_tile_max);
3886 } else {
3887 /* This must be set for fast clear to work without FMASK. */
3888 if (device->physical_device->rad_info.chip_class >= CIK)
3889 cb->cb_color_pitch |= S_028C64_FMASK_TILE_MAX(pitch_tile_max);
3890 cb->cb_color_attrib |= S_028C74_FMASK_TILE_MODE_INDEX(tile_mode_index);
3891 cb->cb_color_fmask_slice = S_028C88_TILE_MAX(slice_tile_max);
3892 }
3893 }
3894
3895 /* CMASK variables */
3896 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3897 va += iview->image->cmask.offset;
3898 cb->cb_color_cmask = va >> 8;
3899
3900 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
3901 va += iview->image->dcc_offset;
3902 cb->cb_dcc_base = va >> 8;
3903 cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
3904
3905 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
3906 cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
3907 S_028C6C_SLICE_MAX(max_slice);
3908
3909 if (iview->image->info.samples > 1) {
3910 unsigned log_samples = util_logbase2(iview->image->info.samples);
3911
3912 cb->cb_color_attrib |= S_028C74_NUM_SAMPLES(log_samples) |
3913 S_028C74_NUM_FRAGMENTS(log_samples);
3914 }
3915
3916 if (radv_image_has_fmask(iview->image)) {
3917 va = radv_buffer_get_va(iview->bo) + iview->image->offset + iview->image->fmask.offset;
3918 cb->cb_color_fmask = va >> 8;
3919 cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
3920 } else {
3921 cb->cb_color_fmask = cb->cb_color_base;
3922 }
3923
3924 ntype = radv_translate_color_numformat(iview->vk_format,
3925 desc,
3926 vk_format_get_first_non_void_channel(iview->vk_format));
3927 format = radv_translate_colorformat(iview->vk_format);
3928 if (format == V_028C70_COLOR_INVALID || ntype == ~0u)
3929 radv_finishme("Illegal color\n");
3930 swap = radv_translate_colorswap(iview->vk_format, FALSE);
3931 endian = radv_colorformat_endian_swap(format);
3932
3933 /* blend clamp should be set for all NORM/SRGB types */
3934 if (ntype == V_028C70_NUMBER_UNORM ||
3935 ntype == V_028C70_NUMBER_SNORM ||
3936 ntype == V_028C70_NUMBER_SRGB)
3937 blend_clamp = 1;
3938
3939 /* set blend bypass according to docs if SINT/UINT or
3940 8/24 COLOR variants */
3941 if (ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT ||
3942 format == V_028C70_COLOR_8_24 || format == V_028C70_COLOR_24_8 ||
3943 format == V_028C70_COLOR_X24_8_32_FLOAT) {
3944 blend_clamp = 0;
3945 blend_bypass = 1;
3946 }
3947 #if 0
3948 if ((ntype == V_028C70_NUMBER_UINT || ntype == V_028C70_NUMBER_SINT) &&
3949 (format == V_028C70_COLOR_8 ||
3950 format == V_028C70_COLOR_8_8 ||
3951 format == V_028C70_COLOR_8_8_8_8))
3952 ->color_is_int8 = true;
3953 #endif
3954 cb->cb_color_info = S_028C70_FORMAT(format) |
3955 S_028C70_COMP_SWAP(swap) |
3956 S_028C70_BLEND_CLAMP(blend_clamp) |
3957 S_028C70_BLEND_BYPASS(blend_bypass) |
3958 S_028C70_SIMPLE_FLOAT(1) |
3959 S_028C70_ROUND_MODE(ntype != V_028C70_NUMBER_UNORM &&
3960 ntype != V_028C70_NUMBER_SNORM &&
3961 ntype != V_028C70_NUMBER_SRGB &&
3962 format != V_028C70_COLOR_8_24 &&
3963 format != V_028C70_COLOR_24_8) |
3964 S_028C70_NUMBER_TYPE(ntype) |
3965 S_028C70_ENDIAN(endian);
3966 if (radv_image_has_fmask(iview->image)) {
3967 cb->cb_color_info |= S_028C70_COMPRESSION(1);
3968 if (device->physical_device->rad_info.chip_class == SI) {
3969 unsigned fmask_bankh = util_logbase2(iview->image->fmask.bank_height);
3970 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(fmask_bankh);
3971 }
3972 }
3973
3974 if (radv_image_has_cmask(iview->image) &&
3975 !(device->instance->debug_flags & RADV_DEBUG_NO_FAST_CLEARS))
3976 cb->cb_color_info |= S_028C70_FAST_CLEAR(1);
3977
3978 if (radv_dcc_enabled(iview->image, iview->base_mip))
3979 cb->cb_color_info |= S_028C70_DCC_ENABLE(1);
3980
3981 cb->cb_dcc_control = radv_init_dcc_control_reg(device, iview);
3982
3983 /* This must be set for fast clear to work without FMASK. */
3984 if (!radv_image_has_fmask(iview->image) &&
3985 device->physical_device->rad_info.chip_class == SI) {
3986 unsigned bankh = util_logbase2(iview->image->surface.u.legacy.bankh);
3987 cb->cb_color_attrib |= S_028C74_FMASK_BANK_HEIGHT(bankh);
3988 }
3989
3990 if (device->physical_device->rad_info.chip_class >= GFX9) {
3991 unsigned mip0_depth = iview->image->type == VK_IMAGE_TYPE_3D ?
3992 (iview->extent.depth - 1) : (iview->image->info.array_size - 1);
3993
3994 cb->cb_color_view |= S_028C6C_MIP_LEVEL(iview->base_mip);
3995 cb->cb_color_attrib |= S_028C74_MIP0_DEPTH(mip0_depth) |
3996 S_028C74_RESOURCE_TYPE(iview->image->surface.u.gfx9.resource_type);
3997 cb->cb_color_attrib2 = S_028C68_MIP0_WIDTH(iview->extent.width - 1) |
3998 S_028C68_MIP0_HEIGHT(iview->extent.height - 1) |
3999 S_028C68_MAX_MIP(iview->image->info.levels - 1);
4000 }
4001 }
4002
4003 static unsigned
4004 radv_calc_decompress_on_z_planes(struct radv_device *device,
4005 struct radv_image_view *iview)
4006 {
4007 unsigned max_zplanes = 0;
4008
4009 assert(radv_image_is_tc_compat_htile(iview->image));
4010
4011 if (device->physical_device->rad_info.chip_class >= GFX9) {
4012 /* Default value for 32-bit depth surfaces. */
4013 max_zplanes = 4;
4014
4015 if (iview->vk_format == VK_FORMAT_D16_UNORM &&
4016 iview->image->info.samples > 1)
4017 max_zplanes = 2;
4018
4019 max_zplanes = max_zplanes + 1;
4020 } else {
4021 if (iview->vk_format == VK_FORMAT_D16_UNORM) {
4022 /* Do not enable Z plane compression for 16-bit depth
4023 * surfaces because isn't supported on GFX8. Only
4024 * 32-bit depth surfaces are supported by the hardware.
4025 * This allows to maintain shader compatibility and to
4026 * reduce the number of depth decompressions.
4027 */
4028 max_zplanes = 1;
4029 } else {
4030 if (iview->image->info.samples <= 1)
4031 max_zplanes = 5;
4032 else if (iview->image->info.samples <= 4)
4033 max_zplanes = 3;
4034 else
4035 max_zplanes = 2;
4036 }
4037 }
4038
4039 return max_zplanes;
4040 }
4041
4042 static void
4043 radv_initialise_ds_surface(struct radv_device *device,
4044 struct radv_ds_buffer_info *ds,
4045 struct radv_image_view *iview)
4046 {
4047 unsigned level = iview->base_mip;
4048 unsigned format, stencil_format;
4049 uint64_t va, s_offs, z_offs;
4050 bool stencil_only = false;
4051 memset(ds, 0, sizeof(*ds));
4052 switch (iview->image->vk_format) {
4053 case VK_FORMAT_D24_UNORM_S8_UINT:
4054 case VK_FORMAT_X8_D24_UNORM_PACK32:
4055 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-24);
4056 ds->offset_scale = 2.0f;
4057 break;
4058 case VK_FORMAT_D16_UNORM:
4059 case VK_FORMAT_D16_UNORM_S8_UINT:
4060 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-16);
4061 ds->offset_scale = 4.0f;
4062 break;
4063 case VK_FORMAT_D32_SFLOAT:
4064 case VK_FORMAT_D32_SFLOAT_S8_UINT:
4065 ds->pa_su_poly_offset_db_fmt_cntl = S_028B78_POLY_OFFSET_NEG_NUM_DB_BITS(-23) |
4066 S_028B78_POLY_OFFSET_DB_IS_FLOAT_FMT(1);
4067 ds->offset_scale = 1.0f;
4068 break;
4069 case VK_FORMAT_S8_UINT:
4070 stencil_only = true;
4071 break;
4072 default:
4073 break;
4074 }
4075
4076 format = radv_translate_dbformat(iview->image->vk_format);
4077 stencil_format = iview->image->surface.has_stencil ?
4078 V_028044_STENCIL_8 : V_028044_STENCIL_INVALID;
4079
4080 uint32_t max_slice = radv_surface_max_layer_count(iview) - 1;
4081 ds->db_depth_view = S_028008_SLICE_START(iview->base_layer) |
4082 S_028008_SLICE_MAX(max_slice);
4083
4084 ds->db_htile_data_base = 0;
4085 ds->db_htile_surface = 0;
4086
4087 va = radv_buffer_get_va(iview->bo) + iview->image->offset;
4088 s_offs = z_offs = va;
4089
4090 if (device->physical_device->rad_info.chip_class >= GFX9) {
4091 assert(iview->image->surface.u.gfx9.surf_offset == 0);
4092 s_offs += iview->image->surface.u.gfx9.stencil_offset;
4093
4094 ds->db_z_info = S_028038_FORMAT(format) |
4095 S_028038_NUM_SAMPLES(util_logbase2(iview->image->info.samples)) |
4096 S_028038_SW_MODE(iview->image->surface.u.gfx9.surf.swizzle_mode) |
4097 S_028038_MAXMIP(iview->image->info.levels - 1) |
4098 S_028038_ZRANGE_PRECISION(1);
4099 ds->db_stencil_info = S_02803C_FORMAT(stencil_format) |
4100 S_02803C_SW_MODE(iview->image->surface.u.gfx9.stencil.swizzle_mode);
4101
4102 ds->db_z_info2 = S_028068_EPITCH(iview->image->surface.u.gfx9.surf.epitch);
4103 ds->db_stencil_info2 = S_02806C_EPITCH(iview->image->surface.u.gfx9.stencil.epitch);
4104 ds->db_depth_view |= S_028008_MIPID(level);
4105
4106 ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 1) |
4107 S_02801C_Y_MAX(iview->image->info.height - 1);
4108
4109 if (radv_htile_enabled(iview->image, level)) {
4110 ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
4111
4112 if (radv_image_is_tc_compat_htile(iview->image)) {
4113 unsigned max_zplanes =
4114 radv_calc_decompress_on_z_planes(device, iview);
4115
4116 ds->db_z_info |= S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes) |
4117 S_028038_ITERATE_FLUSH(1);
4118 ds->db_stencil_info |= S_02803C_ITERATE_FLUSH(1);
4119 }
4120
4121 if (!iview->image->surface.has_stencil)
4122 /* Use all of the htile_buffer for depth if there's no stencil. */
4123 ds->db_stencil_info |= S_02803C_TILE_STENCIL_DISABLE(1);
4124 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4125 iview->image->htile_offset;
4126 ds->db_htile_data_base = va >> 8;
4127 ds->db_htile_surface = S_028ABC_FULL_CACHE(1) |
4128 S_028ABC_PIPE_ALIGNED(iview->image->surface.u.gfx9.htile.pipe_aligned) |
4129 S_028ABC_RB_ALIGNED(iview->image->surface.u.gfx9.htile.rb_aligned);
4130 }
4131 } else {
4132 const struct legacy_surf_level *level_info = &iview->image->surface.u.legacy.level[level];
4133
4134 if (stencil_only)
4135 level_info = &iview->image->surface.u.legacy.stencil_level[level];
4136
4137 z_offs += iview->image->surface.u.legacy.level[level].offset;
4138 s_offs += iview->image->surface.u.legacy.stencil_level[level].offset;
4139
4140 ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(!radv_image_is_tc_compat_htile(iview->image));
4141 ds->db_z_info = S_028040_FORMAT(format) | S_028040_ZRANGE_PRECISION(1);
4142 ds->db_stencil_info = S_028044_FORMAT(stencil_format);
4143
4144 if (iview->image->info.samples > 1)
4145 ds->db_z_info |= S_028040_NUM_SAMPLES(util_logbase2(iview->image->info.samples));
4146
4147 if (device->physical_device->rad_info.chip_class >= CIK) {
4148 struct radeon_info *info = &device->physical_device->rad_info;
4149 unsigned tiling_index = iview->image->surface.u.legacy.tiling_index[level];
4150 unsigned stencil_index = iview->image->surface.u.legacy.stencil_tiling_index[level];
4151 unsigned macro_index = iview->image->surface.u.legacy.macro_tile_index;
4152 unsigned tile_mode = info->si_tile_mode_array[tiling_index];
4153 unsigned stencil_tile_mode = info->si_tile_mode_array[stencil_index];
4154 unsigned macro_mode = info->cik_macrotile_mode_array[macro_index];
4155
4156 if (stencil_only)
4157 tile_mode = stencil_tile_mode;
4158
4159 ds->db_depth_info |=
4160 S_02803C_ARRAY_MODE(G_009910_ARRAY_MODE(tile_mode)) |
4161 S_02803C_PIPE_CONFIG(G_009910_PIPE_CONFIG(tile_mode)) |
4162 S_02803C_BANK_WIDTH(G_009990_BANK_WIDTH(macro_mode)) |
4163 S_02803C_BANK_HEIGHT(G_009990_BANK_HEIGHT(macro_mode)) |
4164 S_02803C_MACRO_TILE_ASPECT(G_009990_MACRO_TILE_ASPECT(macro_mode)) |
4165 S_02803C_NUM_BANKS(G_009990_NUM_BANKS(macro_mode));
4166 ds->db_z_info |= S_028040_TILE_SPLIT(G_009910_TILE_SPLIT(tile_mode));
4167 ds->db_stencil_info |= S_028044_TILE_SPLIT(G_009910_TILE_SPLIT(stencil_tile_mode));
4168 } else {
4169 unsigned tile_mode_index = si_tile_mode_index(iview->image, level, false);
4170 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4171 tile_mode_index = si_tile_mode_index(iview->image, level, true);
4172 ds->db_stencil_info |= S_028044_TILE_MODE_INDEX(tile_mode_index);
4173 if (stencil_only)
4174 ds->db_z_info |= S_028040_TILE_MODE_INDEX(tile_mode_index);
4175 }
4176
4177 ds->db_depth_size = S_028058_PITCH_TILE_MAX((level_info->nblk_x / 8) - 1) |
4178 S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
4179 ds->db_depth_slice = S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
4180
4181 if (radv_htile_enabled(iview->image, level)) {
4182 ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
4183
4184 if (!iview->image->surface.has_stencil &&
4185 !radv_image_is_tc_compat_htile(iview->image))
4186 /* Use all of the htile_buffer for depth if there's no stencil. */
4187 ds->db_stencil_info |= S_028044_TILE_STENCIL_DISABLE(1);
4188
4189 va = radv_buffer_get_va(iview->bo) + iview->image->offset +
4190 iview->image->htile_offset;
4191 ds->db_htile_data_base = va >> 8;
4192 ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
4193
4194 if (radv_image_is_tc_compat_htile(iview->image)) {
4195 unsigned max_zplanes =
4196 radv_calc_decompress_on_z_planes(device, iview);
4197
4198 ds->db_htile_surface |= S_028ABC_TC_COMPATIBLE(1);
4199 ds->db_z_info |= S_028040_DECOMPRESS_ON_N_ZPLANES(max_zplanes);
4200 }
4201 }
4202 }
4203
4204 ds->db_z_read_base = ds->db_z_write_base = z_offs >> 8;
4205 ds->db_stencil_read_base = ds->db_stencil_write_base = s_offs >> 8;
4206 }
4207
4208 VkResult radv_CreateFramebuffer(
4209 VkDevice _device,
4210 const VkFramebufferCreateInfo* pCreateInfo,
4211 const VkAllocationCallbacks* pAllocator,
4212 VkFramebuffer* pFramebuffer)
4213 {
4214 RADV_FROM_HANDLE(radv_device, device, _device);
4215 struct radv_framebuffer *framebuffer;
4216
4217 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO);
4218
4219 size_t size = sizeof(*framebuffer) +
4220 sizeof(struct radv_attachment_info) * pCreateInfo->attachmentCount;
4221 framebuffer = vk_alloc2(&device->alloc, pAllocator, size, 8,
4222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4223 if (framebuffer == NULL)
4224 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4225
4226 framebuffer->attachment_count = pCreateInfo->attachmentCount;
4227 framebuffer->width = pCreateInfo->width;
4228 framebuffer->height = pCreateInfo->height;
4229 framebuffer->layers = pCreateInfo->layers;
4230 for (uint32_t i = 0; i < pCreateInfo->attachmentCount; i++) {
4231 VkImageView _iview = pCreateInfo->pAttachments[i];
4232 struct radv_image_view *iview = radv_image_view_from_handle(_iview);
4233 framebuffer->attachments[i].attachment = iview;
4234 if (iview->aspect_mask & VK_IMAGE_ASPECT_COLOR_BIT) {
4235 radv_initialise_color_surface(device, &framebuffer->attachments[i].cb, iview);
4236 } else if (iview->aspect_mask & (VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT)) {
4237 radv_initialise_ds_surface(device, &framebuffer->attachments[i].ds, iview);
4238 }
4239 framebuffer->width = MIN2(framebuffer->width, iview->extent.width);
4240 framebuffer->height = MIN2(framebuffer->height, iview->extent.height);
4241 framebuffer->layers = MIN2(framebuffer->layers, radv_surface_max_layer_count(iview));
4242 }
4243
4244 *pFramebuffer = radv_framebuffer_to_handle(framebuffer);
4245 return VK_SUCCESS;
4246 }
4247
4248 void radv_DestroyFramebuffer(
4249 VkDevice _device,
4250 VkFramebuffer _fb,
4251 const VkAllocationCallbacks* pAllocator)
4252 {
4253 RADV_FROM_HANDLE(radv_device, device, _device);
4254 RADV_FROM_HANDLE(radv_framebuffer, fb, _fb);
4255
4256 if (!fb)
4257 return;
4258 vk_free2(&device->alloc, pAllocator, fb);
4259 }
4260
4261 static unsigned radv_tex_wrap(VkSamplerAddressMode address_mode)
4262 {
4263 switch (address_mode) {
4264 case VK_SAMPLER_ADDRESS_MODE_REPEAT:
4265 return V_008F30_SQ_TEX_WRAP;
4266 case VK_SAMPLER_ADDRESS_MODE_MIRRORED_REPEAT:
4267 return V_008F30_SQ_TEX_MIRROR;
4268 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE:
4269 return V_008F30_SQ_TEX_CLAMP_LAST_TEXEL;
4270 case VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_BORDER:
4271 return V_008F30_SQ_TEX_CLAMP_BORDER;
4272 case VK_SAMPLER_ADDRESS_MODE_MIRROR_CLAMP_TO_EDGE:
4273 return V_008F30_SQ_TEX_MIRROR_ONCE_LAST_TEXEL;
4274 default:
4275 unreachable("illegal tex wrap mode");
4276 break;
4277 }
4278 }
4279
4280 static unsigned
4281 radv_tex_compare(VkCompareOp op)
4282 {
4283 switch (op) {
4284 case VK_COMPARE_OP_NEVER:
4285 return V_008F30_SQ_TEX_DEPTH_COMPARE_NEVER;
4286 case VK_COMPARE_OP_LESS:
4287 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESS;
4288 case VK_COMPARE_OP_EQUAL:
4289 return V_008F30_SQ_TEX_DEPTH_COMPARE_EQUAL;
4290 case VK_COMPARE_OP_LESS_OR_EQUAL:
4291 return V_008F30_SQ_TEX_DEPTH_COMPARE_LESSEQUAL;
4292 case VK_COMPARE_OP_GREATER:
4293 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATER;
4294 case VK_COMPARE_OP_NOT_EQUAL:
4295 return V_008F30_SQ_TEX_DEPTH_COMPARE_NOTEQUAL;
4296 case VK_COMPARE_OP_GREATER_OR_EQUAL:
4297 return V_008F30_SQ_TEX_DEPTH_COMPARE_GREATEREQUAL;
4298 case VK_COMPARE_OP_ALWAYS:
4299 return V_008F30_SQ_TEX_DEPTH_COMPARE_ALWAYS;
4300 default:
4301 unreachable("illegal compare mode");
4302 break;
4303 }
4304 }
4305
4306 static unsigned
4307 radv_tex_filter(VkFilter filter, unsigned max_ansio)
4308 {
4309 switch (filter) {
4310 case VK_FILTER_NEAREST:
4311 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_POINT :
4312 V_008F38_SQ_TEX_XY_FILTER_POINT);
4313 case VK_FILTER_LINEAR:
4314 return (max_ansio > 1 ? V_008F38_SQ_TEX_XY_FILTER_ANISO_BILINEAR :
4315 V_008F38_SQ_TEX_XY_FILTER_BILINEAR);
4316 case VK_FILTER_CUBIC_IMG:
4317 default:
4318 fprintf(stderr, "illegal texture filter");
4319 return 0;
4320 }
4321 }
4322
4323 static unsigned
4324 radv_tex_mipfilter(VkSamplerMipmapMode mode)
4325 {
4326 switch (mode) {
4327 case VK_SAMPLER_MIPMAP_MODE_NEAREST:
4328 return V_008F38_SQ_TEX_Z_FILTER_POINT;
4329 case VK_SAMPLER_MIPMAP_MODE_LINEAR:
4330 return V_008F38_SQ_TEX_Z_FILTER_LINEAR;
4331 default:
4332 return V_008F38_SQ_TEX_Z_FILTER_NONE;
4333 }
4334 }
4335
4336 static unsigned
4337 radv_tex_bordercolor(VkBorderColor bcolor)
4338 {
4339 switch (bcolor) {
4340 case VK_BORDER_COLOR_FLOAT_TRANSPARENT_BLACK:
4341 case VK_BORDER_COLOR_INT_TRANSPARENT_BLACK:
4342 return V_008F3C_SQ_TEX_BORDER_COLOR_TRANS_BLACK;
4343 case VK_BORDER_COLOR_FLOAT_OPAQUE_BLACK:
4344 case VK_BORDER_COLOR_INT_OPAQUE_BLACK:
4345 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_BLACK;
4346 case VK_BORDER_COLOR_FLOAT_OPAQUE_WHITE:
4347 case VK_BORDER_COLOR_INT_OPAQUE_WHITE:
4348 return V_008F3C_SQ_TEX_BORDER_COLOR_OPAQUE_WHITE;
4349 default:
4350 break;
4351 }
4352 return 0;
4353 }
4354
4355 static unsigned
4356 radv_tex_aniso_filter(unsigned filter)
4357 {
4358 if (filter < 2)
4359 return 0;
4360 if (filter < 4)
4361 return 1;
4362 if (filter < 8)
4363 return 2;
4364 if (filter < 16)
4365 return 3;
4366 return 4;
4367 }
4368
4369 static unsigned
4370 radv_tex_filter_mode(VkSamplerReductionModeEXT mode)
4371 {
4372 switch (mode) {
4373 case VK_SAMPLER_REDUCTION_MODE_WEIGHTED_AVERAGE_EXT:
4374 return SQ_IMG_FILTER_MODE_BLEND;
4375 case VK_SAMPLER_REDUCTION_MODE_MIN_EXT:
4376 return SQ_IMG_FILTER_MODE_MIN;
4377 case VK_SAMPLER_REDUCTION_MODE_MAX_EXT:
4378 return SQ_IMG_FILTER_MODE_MAX;
4379 default:
4380 break;
4381 }
4382 return 0;
4383 }
4384
4385 static void
4386 radv_init_sampler(struct radv_device *device,
4387 struct radv_sampler *sampler,
4388 const VkSamplerCreateInfo *pCreateInfo)
4389 {
4390 uint32_t max_aniso = pCreateInfo->anisotropyEnable && pCreateInfo->maxAnisotropy > 1.0 ?
4391 (uint32_t) pCreateInfo->maxAnisotropy : 0;
4392 uint32_t max_aniso_ratio = radv_tex_aniso_filter(max_aniso);
4393 bool is_vi = (device->physical_device->rad_info.chip_class >= VI);
4394 unsigned filter_mode = SQ_IMG_FILTER_MODE_BLEND;
4395
4396 const struct VkSamplerReductionModeCreateInfoEXT *sampler_reduction =
4397 vk_find_struct_const(pCreateInfo->pNext,
4398 SAMPLER_REDUCTION_MODE_CREATE_INFO_EXT);
4399 if (sampler_reduction)
4400 filter_mode = radv_tex_filter_mode(sampler_reduction->reductionMode);
4401
4402 sampler->state[0] = (S_008F30_CLAMP_X(radv_tex_wrap(pCreateInfo->addressModeU)) |
4403 S_008F30_CLAMP_Y(radv_tex_wrap(pCreateInfo->addressModeV)) |
4404 S_008F30_CLAMP_Z(radv_tex_wrap(pCreateInfo->addressModeW)) |
4405 S_008F30_MAX_ANISO_RATIO(max_aniso_ratio) |
4406 S_008F30_DEPTH_COMPARE_FUNC(radv_tex_compare(pCreateInfo->compareOp)) |
4407 S_008F30_FORCE_UNNORMALIZED(pCreateInfo->unnormalizedCoordinates ? 1 : 0) |
4408 S_008F30_ANISO_THRESHOLD(max_aniso_ratio >> 1) |
4409 S_008F30_ANISO_BIAS(max_aniso_ratio) |
4410 S_008F30_DISABLE_CUBE_WRAP(0) |
4411 S_008F30_COMPAT_MODE(is_vi) |
4412 S_008F30_FILTER_MODE(filter_mode));
4413 sampler->state[1] = (S_008F34_MIN_LOD(S_FIXED(CLAMP(pCreateInfo->minLod, 0, 15), 8)) |
4414 S_008F34_MAX_LOD(S_FIXED(CLAMP(pCreateInfo->maxLod, 0, 15), 8)) |
4415 S_008F34_PERF_MIP(max_aniso_ratio ? max_aniso_ratio + 6 : 0));
4416 sampler->state[2] = (S_008F38_LOD_BIAS(S_FIXED(CLAMP(pCreateInfo->mipLodBias, -16, 16), 8)) |
4417 S_008F38_XY_MAG_FILTER(radv_tex_filter(pCreateInfo->magFilter, max_aniso)) |
4418 S_008F38_XY_MIN_FILTER(radv_tex_filter(pCreateInfo->minFilter, max_aniso)) |
4419 S_008F38_MIP_FILTER(radv_tex_mipfilter(pCreateInfo->mipmapMode)) |
4420 S_008F38_MIP_POINT_PRECLAMP(0) |
4421 S_008F38_DISABLE_LSB_CEIL(device->physical_device->rad_info.chip_class <= VI) |
4422 S_008F38_FILTER_PREC_FIX(1) |
4423 S_008F38_ANISO_OVERRIDE(is_vi));
4424 sampler->state[3] = (S_008F3C_BORDER_COLOR_PTR(0) |
4425 S_008F3C_BORDER_COLOR_TYPE(radv_tex_bordercolor(pCreateInfo->borderColor)));
4426 }
4427
4428 VkResult radv_CreateSampler(
4429 VkDevice _device,
4430 const VkSamplerCreateInfo* pCreateInfo,
4431 const VkAllocationCallbacks* pAllocator,
4432 VkSampler* pSampler)
4433 {
4434 RADV_FROM_HANDLE(radv_device, device, _device);
4435 struct radv_sampler *sampler;
4436
4437 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
4438
4439 sampler = vk_alloc2(&device->alloc, pAllocator, sizeof(*sampler), 8,
4440 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4441 if (!sampler)
4442 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4443
4444 radv_init_sampler(device, sampler, pCreateInfo);
4445 *pSampler = radv_sampler_to_handle(sampler);
4446
4447 return VK_SUCCESS;
4448 }
4449
4450 void radv_DestroySampler(
4451 VkDevice _device,
4452 VkSampler _sampler,
4453 const VkAllocationCallbacks* pAllocator)
4454 {
4455 RADV_FROM_HANDLE(radv_device, device, _device);
4456 RADV_FROM_HANDLE(radv_sampler, sampler, _sampler);
4457
4458 if (!sampler)
4459 return;
4460 vk_free2(&device->alloc, pAllocator, sampler);
4461 }
4462
4463 /* vk_icd.h does not declare this function, so we declare it here to
4464 * suppress Wmissing-prototypes.
4465 */
4466 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4467 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion);
4468
4469 PUBLIC VKAPI_ATTR VkResult VKAPI_CALL
4470 vk_icdNegotiateLoaderICDInterfaceVersion(uint32_t *pSupportedVersion)
4471 {
4472 /* For the full details on loader interface versioning, see
4473 * <https://github.com/KhronosGroup/Vulkan-LoaderAndValidationLayers/blob/master/loader/LoaderAndLayerInterface.md>.
4474 * What follows is a condensed summary, to help you navigate the large and
4475 * confusing official doc.
4476 *
4477 * - Loader interface v0 is incompatible with later versions. We don't
4478 * support it.
4479 *
4480 * - In loader interface v1:
4481 * - The first ICD entrypoint called by the loader is
4482 * vk_icdGetInstanceProcAddr(). The ICD must statically expose this
4483 * entrypoint.
4484 * - The ICD must statically expose no other Vulkan symbol unless it is
4485 * linked with -Bsymbolic.
4486 * - Each dispatchable Vulkan handle created by the ICD must be
4487 * a pointer to a struct whose first member is VK_LOADER_DATA. The
4488 * ICD must initialize VK_LOADER_DATA.loadMagic to ICD_LOADER_MAGIC.
4489 * - The loader implements vkCreate{PLATFORM}SurfaceKHR() and
4490 * vkDestroySurfaceKHR(). The ICD must be capable of working with
4491 * such loader-managed surfaces.
4492 *
4493 * - Loader interface v2 differs from v1 in:
4494 * - The first ICD entrypoint called by the loader is
4495 * vk_icdNegotiateLoaderICDInterfaceVersion(). The ICD must
4496 * statically expose this entrypoint.
4497 *
4498 * - Loader interface v3 differs from v2 in:
4499 * - The ICD must implement vkCreate{PLATFORM}SurfaceKHR(),
4500 * vkDestroySurfaceKHR(), and other API which uses VKSurfaceKHR,
4501 * because the loader no longer does so.
4502 */
4503 *pSupportedVersion = MIN2(*pSupportedVersion, 3u);
4504 return VK_SUCCESS;
4505 }
4506
4507 VkResult radv_GetMemoryFdKHR(VkDevice _device,
4508 const VkMemoryGetFdInfoKHR *pGetFdInfo,
4509 int *pFD)
4510 {
4511 RADV_FROM_HANDLE(radv_device, device, _device);
4512 RADV_FROM_HANDLE(radv_device_memory, memory, pGetFdInfo->memory);
4513
4514 assert(pGetFdInfo->sType == VK_STRUCTURE_TYPE_MEMORY_GET_FD_INFO_KHR);
4515
4516 /* At the moment, we support only the below handle types. */
4517 assert(pGetFdInfo->handleType ==
4518 VK_EXTERNAL_MEMORY_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4519 pGetFdInfo->handleType ==
4520 VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT);
4521
4522 bool ret = radv_get_memory_fd(device, memory, pFD);
4523 if (ret == false)
4524 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
4525 return VK_SUCCESS;
4526 }
4527
4528 VkResult radv_GetMemoryFdPropertiesKHR(VkDevice _device,
4529 VkExternalMemoryHandleTypeFlagBitsKHR handleType,
4530 int fd,
4531 VkMemoryFdPropertiesKHR *pMemoryFdProperties)
4532 {
4533 RADV_FROM_HANDLE(radv_device, device, _device);
4534
4535 switch (handleType) {
4536 case VK_EXTERNAL_MEMORY_HANDLE_TYPE_DMA_BUF_BIT_EXT:
4537 pMemoryFdProperties->memoryTypeBits = (1 << RADV_MEM_TYPE_COUNT) - 1;
4538 return VK_SUCCESS;
4539
4540 default:
4541 /* The valid usage section for this function says:
4542 *
4543 * "handleType must not be one of the handle types defined as
4544 * opaque."
4545 *
4546 * So opaque handle types fall into the default "unsupported" case.
4547 */
4548 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4549 }
4550 }
4551
4552 static VkResult radv_import_opaque_fd(struct radv_device *device,
4553 int fd,
4554 uint32_t *syncobj)
4555 {
4556 uint32_t syncobj_handle = 0;
4557 int ret = device->ws->import_syncobj(device->ws, fd, &syncobj_handle);
4558 if (ret != 0)
4559 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4560
4561 if (*syncobj)
4562 device->ws->destroy_syncobj(device->ws, *syncobj);
4563
4564 *syncobj = syncobj_handle;
4565 close(fd);
4566
4567 return VK_SUCCESS;
4568 }
4569
4570 static VkResult radv_import_sync_fd(struct radv_device *device,
4571 int fd,
4572 uint32_t *syncobj)
4573 {
4574 /* If we create a syncobj we do it locally so that if we have an error, we don't
4575 * leave a syncobj in an undetermined state in the fence. */
4576 uint32_t syncobj_handle = *syncobj;
4577 if (!syncobj_handle) {
4578 int ret = device->ws->create_syncobj(device->ws, &syncobj_handle);
4579 if (ret) {
4580 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4581 }
4582 }
4583
4584 if (fd == -1) {
4585 device->ws->signal_syncobj(device->ws, syncobj_handle);
4586 } else {
4587 int ret = device->ws->import_syncobj_from_sync_file(device->ws, syncobj_handle, fd);
4588 if (ret != 0)
4589 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4590 }
4591
4592 *syncobj = syncobj_handle;
4593 if (fd != -1)
4594 close(fd);
4595
4596 return VK_SUCCESS;
4597 }
4598
4599 VkResult radv_ImportSemaphoreFdKHR(VkDevice _device,
4600 const VkImportSemaphoreFdInfoKHR *pImportSemaphoreFdInfo)
4601 {
4602 RADV_FROM_HANDLE(radv_device, device, _device);
4603 RADV_FROM_HANDLE(radv_semaphore, sem, pImportSemaphoreFdInfo->semaphore);
4604 uint32_t *syncobj_dst = NULL;
4605
4606 if (pImportSemaphoreFdInfo->flags & VK_SEMAPHORE_IMPORT_TEMPORARY_BIT_KHR) {
4607 syncobj_dst = &sem->temp_syncobj;
4608 } else {
4609 syncobj_dst = &sem->syncobj;
4610 }
4611
4612 switch(pImportSemaphoreFdInfo->handleType) {
4613 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4614 return radv_import_opaque_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4615 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4616 return radv_import_sync_fd(device, pImportSemaphoreFdInfo->fd, syncobj_dst);
4617 default:
4618 unreachable("Unhandled semaphore handle type");
4619 }
4620 }
4621
4622 VkResult radv_GetSemaphoreFdKHR(VkDevice _device,
4623 const VkSemaphoreGetFdInfoKHR *pGetFdInfo,
4624 int *pFd)
4625 {
4626 RADV_FROM_HANDLE(radv_device, device, _device);
4627 RADV_FROM_HANDLE(radv_semaphore, sem, pGetFdInfo->semaphore);
4628 int ret;
4629 uint32_t syncobj_handle;
4630
4631 if (sem->temp_syncobj)
4632 syncobj_handle = sem->temp_syncobj;
4633 else
4634 syncobj_handle = sem->syncobj;
4635
4636 switch(pGetFdInfo->handleType) {
4637 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4638 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4639 break;
4640 case VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4641 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4642 if (!ret) {
4643 if (sem->temp_syncobj) {
4644 close (sem->temp_syncobj);
4645 sem->temp_syncobj = 0;
4646 } else {
4647 device->ws->reset_syncobj(device->ws, syncobj_handle);
4648 }
4649 }
4650 break;
4651 default:
4652 unreachable("Unhandled semaphore handle type");
4653 }
4654
4655 if (ret)
4656 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4657 return VK_SUCCESS;
4658 }
4659
4660 void radv_GetPhysicalDeviceExternalSemaphoreProperties(
4661 VkPhysicalDevice physicalDevice,
4662 const VkPhysicalDeviceExternalSemaphoreInfoKHR* pExternalSemaphoreInfo,
4663 VkExternalSemaphorePropertiesKHR* pExternalSemaphoreProperties)
4664 {
4665 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4666
4667 /* Require has_syncobj_wait_for_submit for the syncobj signal ioctl introduced at virtually the same time */
4668 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4669 (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4670 pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4671 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4672 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4673 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4674 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4675 } else if (pExternalSemaphoreInfo->handleType == VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR) {
4676 pExternalSemaphoreProperties->exportFromImportedHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4677 pExternalSemaphoreProperties->compatibleHandleTypes = VK_EXTERNAL_SEMAPHORE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR;
4678 pExternalSemaphoreProperties->externalSemaphoreFeatures = VK_EXTERNAL_SEMAPHORE_FEATURE_EXPORTABLE_BIT_KHR |
4679 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4680 } else {
4681 pExternalSemaphoreProperties->exportFromImportedHandleTypes = 0;
4682 pExternalSemaphoreProperties->compatibleHandleTypes = 0;
4683 pExternalSemaphoreProperties->externalSemaphoreFeatures = 0;
4684 }
4685 }
4686
4687 VkResult radv_ImportFenceFdKHR(VkDevice _device,
4688 const VkImportFenceFdInfoKHR *pImportFenceFdInfo)
4689 {
4690 RADV_FROM_HANDLE(radv_device, device, _device);
4691 RADV_FROM_HANDLE(radv_fence, fence, pImportFenceFdInfo->fence);
4692 uint32_t *syncobj_dst = NULL;
4693
4694
4695 if (pImportFenceFdInfo->flags & VK_FENCE_IMPORT_TEMPORARY_BIT_KHR) {
4696 syncobj_dst = &fence->temp_syncobj;
4697 } else {
4698 syncobj_dst = &fence->syncobj;
4699 }
4700
4701 switch(pImportFenceFdInfo->handleType) {
4702 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4703 return radv_import_opaque_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4704 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4705 return radv_import_sync_fd(device, pImportFenceFdInfo->fd, syncobj_dst);
4706 default:
4707 unreachable("Unhandled fence handle type");
4708 }
4709 }
4710
4711 VkResult radv_GetFenceFdKHR(VkDevice _device,
4712 const VkFenceGetFdInfoKHR *pGetFdInfo,
4713 int *pFd)
4714 {
4715 RADV_FROM_HANDLE(radv_device, device, _device);
4716 RADV_FROM_HANDLE(radv_fence, fence, pGetFdInfo->fence);
4717 int ret;
4718 uint32_t syncobj_handle;
4719
4720 if (fence->temp_syncobj)
4721 syncobj_handle = fence->temp_syncobj;
4722 else
4723 syncobj_handle = fence->syncobj;
4724
4725 switch(pGetFdInfo->handleType) {
4726 case VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR:
4727 ret = device->ws->export_syncobj(device->ws, syncobj_handle, pFd);
4728 break;
4729 case VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR:
4730 ret = device->ws->export_syncobj_to_sync_file(device->ws, syncobj_handle, pFd);
4731 if (!ret) {
4732 if (fence->temp_syncobj) {
4733 close (fence->temp_syncobj);
4734 fence->temp_syncobj = 0;
4735 } else {
4736 device->ws->reset_syncobj(device->ws, syncobj_handle);
4737 }
4738 }
4739 break;
4740 default:
4741 unreachable("Unhandled fence handle type");
4742 }
4743
4744 if (ret)
4745 return vk_error(device->instance, VK_ERROR_INVALID_EXTERNAL_HANDLE_KHR);
4746 return VK_SUCCESS;
4747 }
4748
4749 void radv_GetPhysicalDeviceExternalFenceProperties(
4750 VkPhysicalDevice physicalDevice,
4751 const VkPhysicalDeviceExternalFenceInfoKHR* pExternalFenceInfo,
4752 VkExternalFencePropertiesKHR* pExternalFenceProperties)
4753 {
4754 RADV_FROM_HANDLE(radv_physical_device, pdevice, physicalDevice);
4755
4756 if (pdevice->rad_info.has_syncobj_wait_for_submit &&
4757 (pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR ||
4758 pExternalFenceInfo->handleType == VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR)) {
4759 pExternalFenceProperties->exportFromImportedHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4760 pExternalFenceProperties->compatibleHandleTypes = VK_EXTERNAL_FENCE_HANDLE_TYPE_OPAQUE_FD_BIT_KHR | VK_EXTERNAL_FENCE_HANDLE_TYPE_SYNC_FD_BIT_KHR;
4761 pExternalFenceProperties->externalFenceFeatures = VK_EXTERNAL_FENCE_FEATURE_EXPORTABLE_BIT_KHR |
4762 VK_EXTERNAL_SEMAPHORE_FEATURE_IMPORTABLE_BIT_KHR;
4763 } else {
4764 pExternalFenceProperties->exportFromImportedHandleTypes = 0;
4765 pExternalFenceProperties->compatibleHandleTypes = 0;
4766 pExternalFenceProperties->externalFenceFeatures = 0;
4767 }
4768 }
4769
4770 VkResult
4771 radv_CreateDebugReportCallbackEXT(VkInstance _instance,
4772 const VkDebugReportCallbackCreateInfoEXT* pCreateInfo,
4773 const VkAllocationCallbacks* pAllocator,
4774 VkDebugReportCallbackEXT* pCallback)
4775 {
4776 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4777 return vk_create_debug_report_callback(&instance->debug_report_callbacks,
4778 pCreateInfo, pAllocator, &instance->alloc,
4779 pCallback);
4780 }
4781
4782 void
4783 radv_DestroyDebugReportCallbackEXT(VkInstance _instance,
4784 VkDebugReportCallbackEXT _callback,
4785 const VkAllocationCallbacks* pAllocator)
4786 {
4787 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4788 vk_destroy_debug_report_callback(&instance->debug_report_callbacks,
4789 _callback, pAllocator, &instance->alloc);
4790 }
4791
4792 void
4793 radv_DebugReportMessageEXT(VkInstance _instance,
4794 VkDebugReportFlagsEXT flags,
4795 VkDebugReportObjectTypeEXT objectType,
4796 uint64_t object,
4797 size_t location,
4798 int32_t messageCode,
4799 const char* pLayerPrefix,
4800 const char* pMessage)
4801 {
4802 RADV_FROM_HANDLE(radv_instance, instance, _instance);
4803 vk_debug_report(&instance->debug_report_callbacks, flags, objectType,
4804 object, location, messageCode, pLayerPrefix, pMessage);
4805 }
4806
4807 void
4808 radv_GetDeviceGroupPeerMemoryFeatures(
4809 VkDevice device,
4810 uint32_t heapIndex,
4811 uint32_t localDeviceIndex,
4812 uint32_t remoteDeviceIndex,
4813 VkPeerMemoryFeatureFlags* pPeerMemoryFeatures)
4814 {
4815 assert(localDeviceIndex == remoteDeviceIndex);
4816
4817 *pPeerMemoryFeatures = VK_PEER_MEMORY_FEATURE_COPY_SRC_BIT |
4818 VK_PEER_MEMORY_FEATURE_COPY_DST_BIT |
4819 VK_PEER_MEMORY_FEATURE_GENERIC_SRC_BIT |
4820 VK_PEER_MEMORY_FEATURE_GENERIC_DST_BIT;
4821 }